From 58219fe636ec30447ebc3048d69717918b73c988 Mon Sep 17 00:00:00 2001 From: Koki Mizumoto <21km43@gmail.com> Date: Sat, 11 Jan 2025 18:13:12 +0900 Subject: [PATCH] update sdk --- cores/arduino/ch32/pinmap.c | 6 +- system/CH32L10x/SRC/Debug/debug.c | 3 + system/CH32L10x/SRC/Debug/debug.h | 107 +- system/CH32L10x/SRC/Peripheral/inc/ch32l103.h | 9526 ++++++------- .../SRC/Peripheral/inc/ch32l103_adc.h | 429 +- .../SRC/Peripheral/inc/ch32l103_bkp.h | 130 +- .../SRC/Peripheral/inc/ch32l103_can.h | 1260 +- .../SRC/Peripheral/inc/ch32l103_crc.h | 66 +- .../SRC/Peripheral/inc/ch32l103_dbgmcu.h | 92 +- .../SRC/Peripheral/inc/ch32l103_dma.h | 368 +- .../SRC/Peripheral/inc/ch32l103_exti.h | 181 +- .../SRC/Peripheral/inc/ch32l103_flash.h | 284 +- .../SRC/Peripheral/inc/ch32l103_gpio.h | 356 +- .../SRC/Peripheral/inc/ch32l103_i2c.h | 848 +- .../SRC/Peripheral/inc/ch32l103_iwdg.h | 100 +- .../SRC/Peripheral/inc/ch32l103_lptim.h | 394 +- .../SRC/Peripheral/inc/ch32l103_misc.h | 144 +- .../SRC/Peripheral/inc/ch32l103_opa.h | 463 +- .../SRC/Peripheral/inc/ch32l103_pwr.h | 136 +- .../SRC/Peripheral/inc/ch32l103_rcc.h | 440 +- .../SRC/Peripheral/inc/ch32l103_rtc.h | 110 +- .../SRC/Peripheral/inc/ch32l103_spi.h | 315 +- .../SRC/Peripheral/inc/ch32l103_tim.h | 1034 +- .../SRC/Peripheral/inc/ch32l103_usart.h | 376 +- .../SRC/Peripheral/inc/ch32l103_usb.h | 1022 +- .../SRC/Peripheral/inc/ch32l103_usbpd.h | 816 +- .../SRC/Peripheral/inc/ch32l103_wwdg.h | 82 +- .../SRC/Peripheral/src/ch32l103_adc.c | 2728 ++-- .../SRC/Peripheral/src/ch32l103_bkp.c | 488 +- .../SRC/Peripheral/src/ch32l103_can.c | 3394 ++--- .../SRC/Peripheral/src/ch32l103_crc.c | 198 +- .../SRC/Peripheral/src/ch32l103_dbgmcu.c | 254 +- .../SRC/Peripheral/src/ch32l103_dma.c | 864 +- .../SRC/Peripheral/src/ch32l103_exti.c | 364 +- .../SRC/Peripheral/src/ch32l103_flash.c | 2022 +-- .../SRC/Peripheral/src/ch32l103_gpio.c | 1412 +- .../SRC/Peripheral/src/ch32l103_i2c.c | 2026 +-- .../SRC/Peripheral/src/ch32l103_iwdg.c | 247 +- .../SRC/Peripheral/src/ch32l103_lptim.c | 727 +- .../SRC/Peripheral/src/ch32l103_misc.c | 162 +- .../SRC/Peripheral/src/ch32l103_opa.c | 666 +- .../SRC/Peripheral/src/ch32l103_pwr.c | 932 +- .../SRC/Peripheral/src/ch32l103_rcc.c | 2090 +-- .../SRC/Peripheral/src/ch32l103_rtc.c | 562 +- .../SRC/Peripheral/src/ch32l103_spi.c | 1071 +- .../SRC/Peripheral/src/ch32l103_tim.c | 4824 +++---- .../SRC/Peripheral/src/ch32l103_usart.c | 1632 +-- .../SRC/Peripheral/src/ch32l103_wwdg.c | 284 +- .../CH32L10x/SRC/Startup/startup_ch32l103.S | 6 +- system/CH32L10x/USER/ch32l103_conf.h | 76 +- system/CH32L10x/USER/ch32l103_it.c | 93 +- system/CH32L10x/USER/system_ch32l103.c | 1508 +- system/CH32L10x/USER/system_ch32l103.h | 58 +- system/CH32V00x/SRC/Core/core_riscv.c | 552 +- system/CH32V00x/SRC/Core/core_riscv.h | 778 +- system/CH32V00x/SRC/Debug/debug.c | 404 +- system/CH32V00x/SRC/Debug/debug.h | 92 +- system/CH32V00x/SRC/Peripheral/inc/ch32v00x.h | 4603 +++--- .../SRC/Peripheral/inc/ch32v00x_adc.h | 351 +- .../SRC/Peripheral/inc/ch32v00x_dbgmcu.h | 76 +- .../SRC/Peripheral/inc/ch32v00x_dma.h | 354 +- .../SRC/Peripheral/inc/ch32v00x_exti.h | 156 +- .../SRC/Peripheral/inc/ch32v00x_flash.h | 267 +- .../SRC/Peripheral/inc/ch32v00x_gpio.h | 262 +- .../SRC/Peripheral/inc/ch32v00x_i2c.h | 830 +- .../SRC/Peripheral/inc/ch32v00x_iwdg.h | 100 +- .../SRC/Peripheral/inc/ch32v00x_misc.h | 122 +- .../SRC/Peripheral/inc/ch32v00x_opa.h | 106 +- .../SRC/Peripheral/inc/ch32v00x_pwr.h | 147 +- .../SRC/Peripheral/inc/ch32v00x_rcc.h | 308 +- .../SRC/Peripheral/inc/ch32v00x_spi.h | 310 +- .../SRC/Peripheral/inc/ch32v00x_tim.h | 1017 +- .../SRC/Peripheral/inc/ch32v00x_usart.h | 374 +- .../SRC/Peripheral/inc/ch32v00x_wwdg.h | 82 +- .../SRC/Peripheral/src/ch32v00x_adc.c | 2120 +-- .../SRC/Peripheral/src/ch32v00x_dbgmcu.c | 217 +- .../SRC/Peripheral/src/ch32v00x_dma.c | 832 +- .../SRC/Peripheral/src/ch32v00x_exti.c | 364 +- .../SRC/Peripheral/src/ch32v00x_flash.c | 1903 +-- .../SRC/Peripheral/src/ch32v00x_gpio.c | 935 +- .../SRC/Peripheral/src/ch32v00x_i2c.c | 1950 +-- .../SRC/Peripheral/src/ch32v00x_iwdg.c | 251 +- .../SRC/Peripheral/src/ch32v00x_misc.c | 190 +- .../SRC/Peripheral/src/ch32v00x_opa.c | 164 +- .../SRC/Peripheral/src/ch32v00x_pwr.c | 426 +- .../SRC/Peripheral/src/ch32v00x_rcc.c | 1521 +- .../SRC/Peripheral/src/ch32v00x_spi.c | 1032 +- .../SRC/Peripheral/src/ch32v00x_tim.c | 4712 +++--- .../SRC/Peripheral/src/ch32v00x_usart.c | 1592 +-- .../SRC/Peripheral/src/ch32v00x_wwdg.c | 282 +- .../CH32V00x/SRC/Startup/startup_ch32v00x.S | 76 +- system/CH32V00x/USER/ch32v00x_conf.h | 80 +- system/CH32V00x/USER/ch32v00x_it.c | 87 +- system/CH32V00x/USER/system_ch32v00x.c | 896 +- system/CH32V00x/USER/system_ch32v00x.h | 64 +- system/CH32V10x/SRC/Core/core_riscv.c | 606 +- system/CH32V10x/SRC/Core/core_riscv.h | 1227 +- system/CH32V10x/SRC/Debug/debug.c | 459 +- system/CH32V10x/SRC/Debug/debug.h | 99 +- system/CH32V10x/SRC/Peripheral/inc/ch32v10x.h | 6459 ++++----- .../SRC/Peripheral/inc/ch32v10x_adc.h | 380 +- .../SRC/Peripheral/inc/ch32v10x_bkp.h | 186 +- .../SRC/Peripheral/inc/ch32v10x_crc.h | 66 +- .../SRC/Peripheral/inc/ch32v10x_dbgmcu.h | 94 +- .../SRC/Peripheral/inc/ch32v10x_dma.h | 436 +- .../SRC/Peripheral/inc/ch32v10x_exti.h | 176 +- .../SRC/Peripheral/inc/ch32v10x_flash.h | 319 +- .../SRC/Peripheral/inc/ch32v10x_gpio.h | 320 +- .../SRC/Peripheral/inc/ch32v10x_i2c.h | 858 +- .../SRC/Peripheral/inc/ch32v10x_iwdg.h | 100 +- .../SRC/Peripheral/inc/ch32v10x_misc.h | 122 +- .../SRC/Peripheral/inc/ch32v10x_pwr.h | 135 +- .../SRC/Peripheral/inc/ch32v10x_rcc.h | 461 +- .../SRC/Peripheral/inc/ch32v10x_rtc.h | 106 +- .../SRC/Peripheral/inc/ch32v10x_spi.h | 440 +- .../SRC/Peripheral/inc/ch32v10x_tim.h | 1016 +- .../SRC/Peripheral/inc/ch32v10x_usart.h | 372 +- .../SRC/Peripheral/inc/ch32v10x_usb.h | 1436 +- .../SRC/Peripheral/inc/ch32v10x_usb_host.h | 202 +- .../SRC/Peripheral/inc/ch32v10x_wwdg.h | 82 +- .../SRC/Peripheral/src/ch32v10x_adc.c | 2294 +-- .../SRC/Peripheral/src/ch32v10x_bkp.c | 500 +- .../SRC/Peripheral/src/ch32v10x_crc.c | 210 +- .../SRC/Peripheral/src/ch32v10x_dbgmcu.c | 200 +- .../SRC/Peripheral/src/ch32v10x_dma.c | 1104 +- .../SRC/Peripheral/src/ch32v10x_exti.c | 364 +- .../SRC/Peripheral/src/ch32v10x_flash.c | 2152 +-- .../SRC/Peripheral/src/ch32v10x_gpio.c | 1158 +- .../SRC/Peripheral/src/ch32v10x_i2c.c | 2030 +-- .../SRC/Peripheral/src/ch32v10x_iwdg.c | 251 +- .../SRC/Peripheral/src/ch32v10x_misc.c | 196 +- .../SRC/Peripheral/src/ch32v10x_pwr.c | 493 +- .../SRC/Peripheral/src/ch32v10x_rcc.c | 1900 +-- .../SRC/Peripheral/src/ch32v10x_rtc.c | 595 +- .../SRC/Peripheral/src/ch32v10x_spi.c | 1342 +- .../SRC/Peripheral/src/ch32v10x_tim.c | 4710 +++--- .../SRC/Peripheral/src/ch32v10x_usart.c | 1565 +- .../SRC/Peripheral/src/ch32v10x_usb.c | 344 +- .../SRC/Peripheral/src/ch32v10x_usb_host.c | 1614 +-- .../SRC/Peripheral/src/ch32v10x_wwdg.c | 282 +- .../SRC/Startup/startup_ch32v10x_3v3.S | 119 +- .../SRC/Startup/startup_ch32v10x_5v.S | 119 +- system/CH32V10x/USER/ch32v10x_conf.h | 80 +- system/CH32V10x/USER/ch32v10x_it.c | 85 +- system/CH32V10x/USER/ch32v10x_it.h | 3 - system/CH32V10x/USER/system_ch32v10x.c | 1193 +- system/CH32V10x/USER/system_ch32v10x.h | 61 +- system/CH32V20x/SRC/Core/core_riscv.c | 639 +- system/CH32V20x/SRC/Core/core_riscv.h | 966 +- system/CH32V20x/SRC/Debug/debug.c | 448 +- system/CH32V20x/SRC/Debug/debug.h | 106 +- system/CH32V20x/SRC/Ld/Link.ld | 184 +- system/CH32V20x/SRC/Peripheral/inc/ch32v20x.h | 9706 ++++++------- .../SRC/Peripheral/inc/ch32v20x_adc.h | 438 +- .../SRC/Peripheral/inc/ch32v20x_bkp.h | 184 +- .../SRC/Peripheral/inc/ch32v20x_can.h | 727 +- .../SRC/Peripheral/inc/ch32v20x_crc.h | 64 +- .../SRC/Peripheral/inc/ch32v20x_dbgmcu.h | 102 +- .../SRC/Peripheral/inc/ch32v20x_dma.h | 366 +- .../SRC/Peripheral/inc/ch32v20x_exti.h | 188 +- .../SRC/Peripheral/inc/ch32v20x_flash.h | 290 +- .../SRC/Peripheral/inc/ch32v20x_gpio.h | 380 +- .../SRC/Peripheral/inc/ch32v20x_i2c.h | 628 +- .../SRC/Peripheral/inc/ch32v20x_iwdg.h | 98 +- .../SRC/Peripheral/inc/ch32v20x_misc.h | 115 +- .../SRC/Peripheral/inc/ch32v20x_opa.h | 146 +- .../SRC/Peripheral/inc/ch32v20x_pwr.h | 136 +- .../SRC/Peripheral/inc/ch32v20x_rcc.h | 519 +- .../SRC/Peripheral/inc/ch32v20x_rtc.h | 194 +- .../SRC/Peripheral/inc/ch32v20x_spi.h | 438 +- .../SRC/Peripheral/inc/ch32v20x_tim.h | 1014 +- .../SRC/Peripheral/inc/ch32v20x_usart.h | 370 +- .../SRC/Peripheral/inc/ch32v20x_usb.h | 528 + .../SRC/Peripheral/inc/ch32v20x_wwdg.h | 80 +- .../SRC/Peripheral/src/ch32v20x_adc.c | 2418 ++-- .../SRC/Peripheral/src/ch32v20x_bkp.c | 486 +- .../SRC/Peripheral/src/ch32v20x_can.c | 2489 ++-- .../SRC/Peripheral/src/ch32v20x_crc.c | 196 +- .../SRC/Peripheral/src/ch32v20x_dbgmcu.c | 224 +- .../SRC/Peripheral/src/ch32v20x_dma.c | 862 +- .../SRC/Peripheral/src/ch32v20x_exti.c | 362 +- .../SRC/Peripheral/src/ch32v20x_flash.c | 2197 +-- .../SRC/Peripheral/src/ch32v20x_gpio.c | 1670 ++- .../SRC/Peripheral/src/ch32v20x_i2c.c | 1984 +-- .../SRC/Peripheral/src/ch32v20x_iwdg.c | 243 +- .../SRC/Peripheral/src/ch32v20x_misc.c | 188 +- .../SRC/Peripheral/src/ch32v20x_opa.c | 170 +- .../SRC/Peripheral/src/ch32v20x_pwr.c | 798 +- .../SRC/Peripheral/src/ch32v20x_rcc.c | 2079 +-- .../SRC/Peripheral/src/ch32v20x_rtc.c | 851 +- .../SRC/Peripheral/src/ch32v20x_spi.c | 1298 +- .../SRC/Peripheral/src/ch32v20x_tim.c | 4704 +++--- .../SRC/Peripheral/src/ch32v20x_usart.c | 1546 +- .../SRC/Peripheral/src/ch32v20x_wwdg.c | 280 +- .../SRC/Startup/startup_ch32v20x_D6.S | 166 +- .../SRC/Startup/startup_ch32v20x_D8.S | 166 +- .../SRC/Startup/startup_ch32v20x_D8W.S | 170 +- system/CH32V20x/USER/ch32v20x_conf.h | 89 +- system/CH32V20x/USER/ch32v20x_it.c | 121 +- system/CH32V20x/USER/ch32v20x_it.h | 18 +- system/CH32V20x/USER/system_ch32v20x.c | 55 +- system/CH32V20x/USER/system_ch32v20x.h | 62 +- system/CH32V30x/SRC/Core/core_riscv.c | 784 +- system/CH32V30x/SRC/Core/core_riscv.h | 1179 +- system/CH32V30x/SRC/Debug/debug.c | 457 +- system/CH32V30x/SRC/Debug/debug.h | 101 +- system/CH32V30x/SRC/Peripheral/inc/ch32v30x.h | 11901 +++++++++------- .../SRC/Peripheral/inc/ch32v30x_adc.h | 460 +- .../SRC/Peripheral/inc/ch32v30x_bkp.h | 198 +- .../SRC/Peripheral/inc/ch32v30x_can.h | 752 +- .../SRC/Peripheral/inc/ch32v30x_crc.h | 78 +- .../SRC/Peripheral/inc/ch32v30x_dac.h | 244 +- .../SRC/Peripheral/inc/ch32v30x_dbgmcu.h | 120 +- .../SRC/Peripheral/inc/ch32v30x_dma.h | 540 +- .../SRC/Peripheral/inc/ch32v30x_dvp.h | 138 +- .../SRC/Peripheral/inc/ch32v30x_eth.h | 2676 ++-- .../SRC/Peripheral/inc/ch32v30x_exti.h | 184 +- .../SRC/Peripheral/inc/ch32v30x_flash.h | 292 +- .../SRC/Peripheral/inc/ch32v30x_fsmc.h | 565 +- .../SRC/Peripheral/inc/ch32v30x_gpio.h | 395 +- .../SRC/Peripheral/inc/ch32v30x_i2c.h | 878 +- .../SRC/Peripheral/inc/ch32v30x_iwdg.h | 116 +- .../SRC/Peripheral/inc/ch32v30x_misc.h | 141 +- .../SRC/Peripheral/inc/ch32v30x_opa.h | 154 +- .../SRC/Peripheral/inc/ch32v30x_pwr.h | 143 +- .../SRC/Peripheral/inc/ch32v30x_rcc.h | 922 +- .../SRC/Peripheral/inc/ch32v30x_rng.h | 86 +- .../SRC/Peripheral/inc/ch32v30x_rtc.h | 112 +- .../SRC/Peripheral/inc/ch32v30x_sdio.h | 522 +- .../SRC/Peripheral/inc/ch32v30x_spi.h | 462 +- .../SRC/Peripheral/inc/ch32v30x_tim.h | 1034 +- .../SRC/Peripheral/inc/ch32v30x_usart.h | 392 +- .../SRC/Peripheral/inc/ch32v30x_usb.h | 834 ++ .../SRC/Peripheral/inc/ch32v30x_wwdg.h | 88 +- .../SRC/Peripheral/src/ch32v30x_adc.c | 2364 +-- .../SRC/Peripheral/src/ch32v30x_bkp.c | 488 +- .../SRC/Peripheral/src/ch32v30x_can.c | 2436 ++-- .../SRC/Peripheral/src/ch32v30x_crc.c | 200 +- .../SRC/Peripheral/src/ch32v30x_dac.c | 608 +- .../SRC/Peripheral/src/ch32v30x_dbgmcu.c | 254 +- .../SRC/Peripheral/src/ch32v30x_dma.c | 1384 +- .../SRC/Peripheral/src/ch32v30x_dvp.c | 270 +- .../SRC/Peripheral/src/ch32v30x_eth.c | 5046 +++---- .../SRC/Peripheral/src/ch32v30x_exti.c | 364 +- .../SRC/Peripheral/src/ch32v30x_flash.c | 2190 +-- .../SRC/Peripheral/src/ch32v30x_fsmc.c | 883 +- .../SRC/Peripheral/src/ch32v30x_gpio.c | 1463 +- .../SRC/Peripheral/src/ch32v30x_i2c.c | 2020 +-- .../SRC/Peripheral/src/ch32v30x_iwdg.c | 245 +- .../SRC/Peripheral/src/ch32v30x_misc.c | 214 +- .../SRC/Peripheral/src/ch32v30x_opa.c | 172 +- .../SRC/Peripheral/src/ch32v30x_pwr.c | 722 +- .../SRC/Peripheral/src/ch32v30x_rcc.c | 2954 ++-- .../SRC/Peripheral/src/ch32v30x_rng.c | 308 +- .../SRC/Peripheral/src/ch32v30x_rtc.c | 594 +- .../SRC/Peripheral/src/ch32v30x_sdio.c | 1344 +- .../SRC/Peripheral/src/ch32v30x_spi.c | 1336 +- .../SRC/Peripheral/src/ch32v30x_tim.c | 4736 +++--- .../SRC/Peripheral/src/ch32v30x_usart.c | 1589 +-- .../SRC/Peripheral/src/ch32v30x_wwdg.c | 282 +- .../SRC/Startup/startup_ch32v30x_D8.S | 217 +- .../SRC/Startup/startup_ch32v30x_D8C.S | 237 +- system/CH32V30x/USER/ch32v30x_conf.h | 90 +- system/CH32V30x/USER/ch32v30x_it.c | 88 +- system/CH32V30x/USER/system_ch32v30x.c | 2050 +-- system/CH32V30x/USER/system_ch32v30x.h | 64 +- system/CH32VM00X/SRC/Core/core_riscv.c | 552 +- system/CH32VM00X/SRC/Core/core_riscv.h | 802 +- system/CH32VM00X/SRC/Debug/debug.c | 735 +- system/CH32VM00X/SRC/Debug/debug.h | 134 +- .../CH32VM00X/SRC/Peripheral/inc/ch32v00X.h | 5066 +++---- .../SRC/Peripheral/inc/ch32v00X_adc.h | 420 +- .../SRC/Peripheral/inc/ch32v00X_dbgmcu.h | 82 +- .../SRC/Peripheral/inc/ch32v00X_dma.h | 354 +- .../SRC/Peripheral/inc/ch32v00X_exti.h | 156 +- .../SRC/Peripheral/inc/ch32v00X_flash.h | 293 +- .../SRC/Peripheral/inc/ch32v00X_gpio.h | 318 +- .../SRC/Peripheral/inc/ch32v00X_i2c.h | 830 +- .../SRC/Peripheral/inc/ch32v00X_iwdg.h | 100 +- .../SRC/Peripheral/inc/ch32v00X_misc.h | 148 +- .../SRC/Peripheral/inc/ch32v00X_opa.h | 746 +- .../SRC/Peripheral/inc/ch32v00X_pwr.h | 132 +- .../SRC/Peripheral/inc/ch32v00X_rcc.h | 354 +- .../SRC/Peripheral/inc/ch32v00X_spi.h | 307 +- .../SRC/Peripheral/inc/ch32v00X_tim.h | 1058 +- .../SRC/Peripheral/inc/ch32v00X_usart.h | 294 +- .../SRC/Peripheral/inc/ch32v00X_wwdg.h | 82 +- .../SRC/Peripheral/src/ch32v00X_adc.c | 2650 ++-- .../SRC/Peripheral/src/ch32v00X_dbgmcu.c | 274 +- .../SRC/Peripheral/src/ch32v00X_dma.c | 822 +- .../SRC/Peripheral/src/ch32v00X_exti.c | 364 +- .../SRC/Peripheral/src/ch32v00X_flash.c | 2132 +-- .../SRC/Peripheral/src/ch32v00X_gpio.c | 1469 +- .../SRC/Peripheral/src/ch32v00X_i2c.c | 1946 +-- .../SRC/Peripheral/src/ch32v00X_iwdg.c | 252 +- .../SRC/Peripheral/src/ch32v00X_misc.c | 162 +- .../SRC/Peripheral/src/ch32v00X_opa.c | 938 +- .../SRC/Peripheral/src/ch32v00X_pwr.c | 454 +- .../SRC/Peripheral/src/ch32v00X_rcc.c | 1760 +-- .../SRC/Peripheral/src/ch32v00X_spi.c | 1061 +- .../SRC/Peripheral/src/ch32v00X_tim.c | 5202 +++---- .../SRC/Peripheral/src/ch32v00X_usart.c | 1250 +- .../SRC/Peripheral/src/ch32v00X_wwdg.c | 282 +- .../CH32VM00X/SRC/Startup/startup_ch32v00X.S | 6 +- system/CH32VM00X/USER/ch32v00X_conf.h | 80 +- system/CH32VM00X/USER/ch32v00X_it.c | 91 +- system/CH32VM00X/USER/system_ch32v00X.c | 897 +- system/CH32VM00X/USER/system_ch32v00X.h | 64 +- system/CH32X035/SRC/Core/core_riscv.c | 614 +- system/CH32X035/SRC/Core/core_riscv.h | 1154 +- system/CH32X035/SRC/Debug/debug.c | 64 +- system/CH32X035/SRC/Debug/debug.h | 105 +- system/CH32X035/SRC/Peripheral/inc/PIOC_SFR.h | 266 + system/CH32X035/SRC/Peripheral/inc/ch32x035.h | 5821 ++++---- .../SRC/Peripheral/inc/ch32x035_adc.h | 420 +- .../SRC/Peripheral/inc/ch32x035_awu.h | 96 +- .../SRC/Peripheral/inc/ch32x035_dbgmcu.h | 82 +- .../SRC/Peripheral/inc/ch32x035_dma.h | 368 +- .../SRC/Peripheral/inc/ch32x035_exti.h | 198 +- .../SRC/Peripheral/inc/ch32x035_flash.h | 293 +- .../SRC/Peripheral/inc/ch32x035_gpio.h | 364 +- .../SRC/Peripheral/inc/ch32x035_i2c.h | 832 +- .../SRC/Peripheral/inc/ch32x035_iwdg.h | 100 +- .../SRC/Peripheral/inc/ch32x035_misc.h | 117 +- .../SRC/Peripheral/inc/ch32x035_opa.h | 442 +- .../SRC/Peripheral/inc/ch32x035_pwr.h | 101 +- .../SRC/Peripheral/inc/ch32x035_rcc.h | 222 +- .../SRC/Peripheral/inc/ch32x035_spi.h | 307 +- .../SRC/Peripheral/inc/ch32x035_tim.h | 1060 +- .../SRC/Peripheral/inc/ch32x035_usart.h | 370 +- .../SRC/Peripheral/inc/ch32x035_usb.h | 522 + .../SRC/Peripheral/inc/ch32x035_usbpd.h | 412 + .../SRC/Peripheral/inc/ch32x035_wwdg.h | 82 +- .../SRC/Peripheral/src/ch32x035_adc.c | 2250 +-- .../SRC/Peripheral/src/ch32x035_awu.c | 184 +- .../SRC/Peripheral/src/ch32x035_dbgmcu.c | 239 +- .../SRC/Peripheral/src/ch32x035_dma.c | 864 +- .../SRC/Peripheral/src/ch32x035_exti.c | 364 +- .../SRC/Peripheral/src/ch32x035_flash.c | 1783 ++- .../SRC/Peripheral/src/ch32x035_gpio.c | 1336 +- .../SRC/Peripheral/src/ch32x035_i2c.c | 1934 +-- .../SRC/Peripheral/src/ch32x035_iwdg.c | 244 +- .../SRC/Peripheral/src/ch32x035_misc.c | 190 +- .../SRC/Peripheral/src/ch32x035_opa.c | 639 +- .../SRC/Peripheral/src/ch32x035_pwr.c | 286 +- .../SRC/Peripheral/src/ch32x035_rcc.c | 822 +- .../SRC/Peripheral/src/ch32x035_spi.c | 1013 +- .../SRC/Peripheral/src/ch32x035_tim.c | 4914 +++---- .../SRC/Peripheral/src/ch32x035_usart.c | 1486 +- .../SRC/Peripheral/src/ch32x035_wwdg.c | 282 +- .../CH32X035/SRC/Startup/startup_ch32x035.S | 117 +- system/CH32X035/USER/ch32x035_conf.h | 78 +- system/CH32X035/USER/ch32x035_it.c | 88 +- system/CH32X035/USER/system_ch32x035.c | 482 +- system/CH32X035/USER/system_ch32x035.h | 64 +- variants/CH32V20x/PinAF_CH32V20x.h | 8 - 356 files changed, 152790 insertions(+), 145396 deletions(-) create mode 100644 system/CH32V20x/SRC/Peripheral/inc/ch32v20x_usb.h create mode 100644 system/CH32V30x/SRC/Peripheral/inc/ch32v30x_usb.h create mode 100644 system/CH32X035/SRC/Peripheral/inc/PIOC_SFR.h create mode 100644 system/CH32X035/SRC/Peripheral/inc/ch32x035_usb.h create mode 100644 system/CH32X035/SRC/Peripheral/inc/ch32x035_usbpd.h diff --git a/cores/arduino/ch32/pinmap.c b/cores/arduino/ch32/pinmap.c index 07a4004..8d4f85e 100644 --- a/cores/arduino/ch32/pinmap.c +++ b/cores/arduino/ch32/pinmap.c @@ -130,15 +130,19 @@ void pin_function(PinName pin, int function) case CH_CNF_OUTPUT_PP: GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; break; +#if !defined(CH32X035) case CH_CNF_OUTPUT_OD: GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; break; +#endif case CH_CNF_OUTPUT_AFPP: GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; break; +#if !defined(CH32X035) case CH_CNF_OUTPUT_AFOD: GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; - break; + break; +#endif default: GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; break; diff --git a/system/CH32L10x/SRC/Debug/debug.c b/system/CH32L10x/SRC/Debug/debug.c index efcee4c..ed9d9dc 100644 --- a/system/CH32L10x/SRC/Debug/debug.c +++ b/system/CH32L10x/SRC/Debug/debug.c @@ -193,3 +193,6 @@ void *_sbrk(ptrdiff_t incr) curbrk += incr; return curbrk - incr; } + +void _fini() {} +void _init() {} diff --git a/system/CH32L10x/SRC/Debug/debug.h b/system/CH32L10x/SRC/Debug/debug.h index 9c2379e..9fe09e3 100644 --- a/system/CH32L10x/SRC/Debug/debug.h +++ b/system/CH32L10x/SRC/Debug/debug.h @@ -1,53 +1,54 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : debug.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for UART - * Printf , Delay functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __DEBUG_H -#define __DEBUG_H - -#include "stdio.h" -#include "ch32l103.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* UART Printf Definition */ -#define DEBUG_UART1 1 -#define DEBUG_UART2 2 -#define DEBUG_UART3 3 - -/* DEBUG UATR Definition */ -#ifndef DEBUG -#define DEBUG DEBUG_UART1 -#endif - -extern uint32_t OPA_Trim; -extern uint16_t ADC_Trim; -extern uint32_t TS_Val; -extern uint32_t CHIPID; - -void Delay_Init(void); -void Delay_Us(uint32_t n); -void Delay_Ms(uint32_t n); -void USART_Printf_Init(uint32_t baudrate); - -#if(DEBUG) - #define PRINT(format, ...) printf(format, ##__VA_ARGS__) -#else - #define PRINT(X...) -#endif - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/11/06 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __DEBUG_H +#define __DEBUG_H + +#include "stdio.h" +#include "ch32l103.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* UART Printf Definition */ +#define DEBUG_UART1 1 +#define DEBUG_UART2 2 +#define DEBUG_UART3 3 + +/* DEBUG UATR Definition */ +#ifndef DEBUG +#define DEBUG DEBUG_UART1 +#endif + +extern uint32_t OPA_Trim; +extern uint16_t ADC_Trim; +extern uint32_t TS_Val; +extern uint32_t CHIPID; +extern uint16_t USBPD_CFG; + +void Delay_Init(void); +void Delay_Us(uint32_t n); +void Delay_Ms(uint32_t n); +void USART_Printf_Init(uint32_t baudrate); + +#if(DEBUG) + #define PRINT(format, ...) printf(format, ##__VA_ARGS__) +#else + #define PRINT(X...) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103.h index e6b9878..b138d11 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103.h @@ -1,4766 +1,4760 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : CH32L103 Device Peripheral Access Layer Header File. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_H -#define __CH32L103_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ - -/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x1000) /* Time out for HSE start up */ - -#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ - -#define HSI_LP_VALUE ((uint32_t)1000000) /* Value of the Internal oscillator in Hz for low power mode */ - -/* Standard Peripheral Library version number */ -#define __CH32L103_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ -#define __CH32L103_STDPERIPH_VERSION_SUB (0x00) /* [7:0] sub version */ -#define __CH32L103_STDPERIPH_VERSION ((__CH32L103_STDPERIPH_VERSION_MAIN << 8)\ - |(__CH32L103_STDPERIPH_VERSION_SUB << 0)) - -/* Interrupt Number Definition, according to the selected device */ -typedef enum IRQn -{ - /****** RISC-V Processor Exceptions Numbers *******************************************************/ - NonMaskableInt_IRQn = 2, /* Non Maskable Interrupt */ - EXC_IRQn = 3, /* Exception Interrupt */ - Ecall_M_Mode_IRQn = 5, /* Ecall M Mode Interrupt */ - Ecall_U_Mode_IRQn = 8, /* Ecall U Mode Interrupt */ - Break_Point_IRQn = 9, /* Break Point Interrupt */ - SysTicK_IRQn = 12, /* System timer Interrupt */ - Software_IRQn = 14, /* Software Interrupt */ - - /****** RISC-V specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 16, /* Window WatchDog Interrupt */ - PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 18, /* Tamper Interrupt */ - RTC_IRQn = 19, /* RTC global Interrupt */ - FLASH_IRQn = 20, /* FLASH global Interrupt */ - RCC_IRQn = 21, /* RCC global Interrupt */ - EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ - EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ - EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ - EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ - EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ - ADC_IRQn = 34, /* ADC1 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ - TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 44, /* TIM2 global Interrupt */ - TIM3_IRQn = 45, /* TIM3 global Interrupt */ - TIM4_IRQn = 46, /* TIM4 global Interrupt */ - I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ - I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ - I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ - I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ - SPI1_IRQn = 51, /* SPI1 global Interrupt */ - SPI2_IRQn = 52, /* SPI2 global Interrupt */ - USART1_IRQn = 53, /* USART1 global Interrupt */ - USART2_IRQn = 54, /* USART2 global Interrupt */ - USART3_IRQn = 55, /* USART3 global Interrupt */ - EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ - LPTIMWakeUp_IRQn = 58, /* LPTIM WakeUp Interrupt */ - USBFS_IRQn = 59, /* USBFS global Interrupt */ - USBFSWakeUp_IRQn = 60, /* USBFS WakeUp Interrupt */ - USART4_IRQn = 61, /* USART4 global Interrupt */ - DMA1_Channel8_IRQn = 62, /* DMA1 Channel 8 global Interrupt */ - LPTIM_IRQn = 63, /* LPTIM global Interrupt */ - OPA_IRQn = 64, /* OPA global Interrupt */ - USBPD_IRQn = 65, /* USBPD global Interrupt */ - TKeyWakeUp_IRQn = 66, /* TKey WakeUp Interrupt */ - USBPDWakeUp_IRQn = 67, /* USBPD WakeUp Interrupt */ - CMPWakeUp_IRQn = 68, /* CMP WakeUp Interrupt */ - -} IRQn_Type; - -#define HardFault_IRQn EXC_IRQn -#define ADC1_2_IRQn ADC_IRQn - -#include -#include "core_riscv.h" -#include "system_ch32l103.h" - -#define HSI_Value HSI_VALUE -#define HSE_Value HSE_VALUE -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT - -/* Analog to Digital Converter */ -typedef struct -{ - __IO uint32_t STATR; - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t SAMPTR1; - __IO uint32_t SAMPTR2; - __IO uint32_t IOFR1; - __IO uint32_t IOFR2; - __IO uint32_t IOFR3; - __IO uint32_t IOFR4; - __IO uint32_t WDHTR; - __IO uint32_t WDLTR; - __IO uint32_t RSQR1; - __IO uint32_t RSQR2; - __IO uint32_t RSQR3; - __IO uint32_t ISQR; - __IO uint32_t IDATAR1; - __IO uint32_t IDATAR2; - __IO uint32_t IDATAR3; - __IO uint32_t IDATAR4; - __IO uint32_t RDATAR; - __IO uint32_t CFG; -} ADC_TypeDef; - -/* Backup Registers */ -typedef struct -{ - uint32_t RESERVED0; - __IO uint16_t DATAR1; - uint16_t RESERVED1; - __IO uint16_t DATAR2; - uint16_t RESERVED2; - __IO uint16_t DATAR3; - uint16_t RESERVED3; - __IO uint16_t DATAR4; - uint16_t RESERVED4; - __IO uint16_t DATAR5; - uint16_t RESERVED5; - __IO uint16_t DATAR6; - uint16_t RESERVED6; - __IO uint16_t DATAR7; - uint16_t RESERVED7; - __IO uint16_t DATAR8; - uint16_t RESERVED8; - __IO uint16_t DATAR9; - uint16_t RESERVED9; - __IO uint16_t DATAR10; - uint16_t RESERVED10; - __IO uint16_t OCTLR; - uint16_t RESERVED11; - __IO uint16_t TPCTLR; - uint16_t RESERVED12; - __IO uint16_t TPCSR; - uint16_t RESERVED13[5]; - __IO uint16_t DATAR11; - uint16_t RESERVED14; - __IO uint16_t DATAR12; - uint16_t RESERVED15; - __IO uint16_t DATAR13; - uint16_t RESERVED16; -} BKP_TypeDef; - -/* Controller Area Network TxMailBox */ -typedef struct -{ - __IO uint32_t TXMIR; - __IO uint32_t TXMDTR; - __IO uint32_t TXMDLR; - __IO uint32_t TXMDHR; -} CAN_TxMailBox_TypeDef; - -/* Controller Area Network FIFOMailBox */ -typedef struct -{ - __IO uint32_t RXMIR; - __IO uint32_t RXMDTR; - __IO uint32_t RXMDLR; - __IO uint32_t RXMDHR; -} CAN_FIFOMailBox_TypeDef; - -/* Controller Area Network FilterRegister */ -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/* Controller Area Network */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t STATR; - __IO uint32_t TSTATR; - __IO uint32_t RFIFO0; - __IO uint32_t RFIFO1; - __IO uint32_t INTENR; - __IO uint32_t ERRSR; - __IO uint32_t BTIMR; - __IO uint32_t TTCTLR; - __IO uint32_t TTCNT; - __IO uint32_t TERR_CNT; - __IO uint32_t CANFD_CR; - __IO uint32_t CANFD_BTR; - __IO uint32_t CANFD_TDCT; - __IO uint32_t CANFD_PSR; - __IO uint32_t CANFD_DMA_T[3]; - __IO uint32_t CANFD_DMA_R[2]; - uint32_t RESERVED0[76]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FCTLR; - __IO uint32_t FMCFGR; - uint32_t RESERVED2; - __IO uint32_t FSCFGR; - uint32_t RESERVED3; - __IO uint32_t FAFIFOR; - uint32_t RESERVED4; - __IO uint32_t FWR; - uint32_t RESERVED5[8]; - CAN_FilterRegister_TypeDef sFilterRegister[14]; -} CAN_TypeDef; - -/* CRC Calculation Unit */ -typedef struct -{ - __IO uint32_t DATAR; - __IO uint8_t IDATAR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CTLR; -} CRC_TypeDef; - -/* DMA Channel Controller */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t CNTR; - __IO uint32_t PADDR; - __IO uint32_t MADDR; -} DMA_Channel_TypeDef; - -/* DMA Controller */ -typedef struct -{ - __IO uint32_t INTFR; - __IO uint32_t INTFCR; -} DMA_TypeDef; - -/* External Interrupt/Event Controller */ -typedef struct -{ - __IO uint32_t INTENR; - __IO uint32_t EVENR; - __IO uint32_t RTENR; - __IO uint32_t FTENR; - __IO uint32_t SWIEVR; - __IO uint32_t INTFR; -} EXTI_TypeDef; - -/* FLASH Registers */ -typedef struct -{ - __IO uint32_t ACTLR; - __IO uint32_t KEYR; - __IO uint32_t OBKEYR; - __IO uint32_t STATR; - __IO uint32_t CTLR; - __IO uint32_t ADDR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WPR; - __IO uint32_t MODEKEYR; -} FLASH_TypeDef; - -/* Option Bytes Registers */ -typedef struct -{ - __IO uint16_t RDPR; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRPR0; - __IO uint16_t WRPR1; - __IO uint16_t WRPR2; - __IO uint16_t WRPR3; -} OB_TypeDef; - -/* General Purpose I/O */ -typedef struct -{ - __IO uint32_t CFGLR; - __IO uint32_t CFGHR; - __IO uint32_t INDR; - __IO uint32_t OUTDR; - __IO uint32_t BSHR; - __IO uint32_t BCR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/* Alternate Function I/O */ -typedef struct -{ - __IO uint32_t ECR; - __IO uint32_t PCFR1; - __IO uint32_t EXTICR[4]; - __IO uint32_t CR; - __IO uint32_t PCFR2; -} AFIO_TypeDef; - -/* Inter Integrated Circuit Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t OADDR1; - uint16_t RESERVED2; - __IO uint16_t OADDR2; - uint16_t RESERVED3; - __IO uint16_t DATAR; - uint16_t RESERVED4; - __IO uint16_t STAR1; - uint16_t RESERVED5; - __IO uint16_t STAR2; - uint16_t RESERVED6; - __IO uint16_t CKCFGR; - uint16_t RESERVED7; - __IO uint16_t RTR; - uint16_t RESERVED8; -} I2C_TypeDef; - -/* Independent WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t PSCR; - __IO uint32_t RLDR; - __IO uint32_t STATR; -} IWDG_TypeDef; - -/* Power Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/* Reset and Clock Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR0; - __IO uint32_t INTR; - __IO uint32_t PB2PRSTR; - __IO uint32_t PB1PRSTR; - __IO uint32_t HBPCENR; - __IO uint32_t PB2PCENR; - __IO uint32_t PB1PCENR; - __IO uint32_t BDCTLR; - __IO uint32_t RSTSCKR; - __IO uint32_t HBRSTR; -} RCC_TypeDef; - -/* Real-Time Clock */ -typedef struct -{ - __IO uint16_t CTLRH; - uint16_t RESERVED0; - __IO uint16_t CTLRL; - uint16_t RESERVED1; - __IO uint16_t PSCRH; - uint16_t RESERVED2; - __IO uint16_t PSCRL; - uint16_t RESERVED3; - __IO uint16_t DIVH; - uint16_t RESERVED4; - __IO uint16_t DIVL; - uint16_t RESERVED5; - __IO uint16_t CNTH; - uint16_t RESERVED6; - __IO uint16_t CNTL; - uint16_t RESERVED7; - __IO uint16_t ALRMH; - uint16_t RESERVED8; - __IO uint16_t ALRML; - uint16_t RESERVED9; -} RTC_TypeDef; - -/* Serial Peripheral Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t STATR; - uint16_t RESERVED2; - __IO uint16_t DATAR; - uint16_t RESERVED3; - __IO uint16_t CRCR; - uint16_t RESERVED4; - __IO uint16_t RCRCR; - uint16_t RESERVED5; - __IO uint16_t TCRCR; - uint16_t RESERVED6; - uint32_t RESERVED7; - uint32_t RESERVED8; - __IO uint16_t HSCR; - uint16_t RESERVED9; -} SPI_TypeDef; - -/* TIM */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t SMCFGR; - uint16_t RESERVED2; - __IO uint16_t DMAINTENR; - uint16_t RESERVED3; - __IO uint16_t INTFR; - uint16_t RESERVED4; - __IO uint16_t SWEVGR; - uint16_t RESERVED5; - __IO uint16_t CHCTLR1; - uint16_t RESERVED6; - __IO uint16_t CHCTLR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - union - { - __IO uint32_t CNT_TIM4; - struct - { - __IO uint16_t CNT; - uint16_t RESERVED9; - }; - }; - __IO uint16_t PSC; - uint16_t RESERVED10; - union - { - __IO uint32_t ATRLR_TIM4; - struct - { - __IO uint16_t ATRLR; - uint16_t RESERVED11; - }; - }; - __IO uint16_t RPTCR; - uint16_t RESERVED12; - union - { - __IO uint32_t CH1CVR_TIM4; - - __IO uint32_t CH1CVR; - }; - union - { - __IO uint32_t CH2CVR_TIM4; - - __IO uint32_t CH2CVR; - }; - union - { - __IO uint32_t CH3CVR_TIM4; - - __IO uint32_t CH3CVR; - }; - union - { - __IO uint32_t CH4CVR_TIM4; - - __IO uint32_t CH4CVR; - }; - __IO uint16_t BDTR; - uint16_t RESERVED13; - __IO uint16_t DMACFGR; - uint16_t RESERVED14; - __IO uint32_t DMAADR; -} TIM_TypeDef; - -/* Universal Synchronous Asynchronous Receiver Transmitter */ -typedef struct -{ - __IO uint16_t STATR; - uint16_t RESERVED0; - __IO uint16_t DATAR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CTLR1; - uint16_t RESERVED3; - __IO uint16_t CTLR2; - uint16_t RESERVED4; - __IO uint16_t CTLR3; - uint16_t RESERVED5; - __IO uint16_t GPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/* Window WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR; - __IO uint32_t STATR; -} WWDG_TypeDef; - -/* Enhanced Registers */ -typedef struct -{ - __IO uint32_t EXTEN_CTR; -} EXTEN_TypeDef; - -/* OPA Registers */ -typedef struct -{ - __IO uint16_t CFGR1; - __IO uint16_t CFGR2; - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t RESERVED0; - __IO uint32_t RESERVED1; - __IO uint32_t OPCMKEY; -} OPA_TypeDef; - -/* LPTIM Registers */ -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t ICR; - __IO uint32_t IER; - __IO uint32_t CFGR; - __IO uint32_t CR; - __IO uint16_t CMP; - uint16_t RESERVED0; - __IO uint16_t ARR; - uint16_t RESERVED1; - __IO uint16_t CNT; - uint16_t RESERVED2; -} LPTIM_TypeDef; - -/* PD Registers */ -typedef struct -{ - union - { - __IO uint32_t USBPD_CONFIG; - struct - { - __IO uint16_t CONFIG; - __IO uint16_t BMC_CLK_CNT; - }; - }; - union - { - __IO uint32_t USBPD_CONTROL; - struct - { - union - { - __IO uint16_t R16_CONTROL; - struct - { - __IO uint8_t CONTROL; - __IO uint8_t TX_SEL; - }; - }; - __IO uint16_t BMC_TX_SZ; - }; - }; - union - { - __IO uint32_t USBPD_STATUS; - struct - { - union - { - __IO uint16_t R16_STATUS; - struct - { - __IO uint8_t DATA_BUF; - __IO uint8_t STATUS; - }; - }; - __IO uint16_t BMC_BYTE_CNT; - }; - }; - union - { - __IO uint32_t USBPD_PORT; - struct - { - __IO uint16_t PORT_CC1; - __IO uint16_t PORT_CC2; - }; - }; - union - { - __IO uint32_t USBPD_DMA; - struct - { - __IO uint16_t DMA; - __IO uint16_t RESERVED; - }; - }; -} USBPD_TypeDef; - -/* USBFS Registers */ -typedef struct -{ - __IO uint8_t BASE_CTRL; - __IO uint8_t UDEV_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_ADDR; - __IO uint8_t Reserve0; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint32_t RX_LEN; - __IO uint8_t UEP4_1_MOD; - __IO uint8_t UEP2_3_MOD; - __IO uint8_t UEP5_6_MOD; - __IO uint8_t UEP7_MOD; - __IO uint32_t UEP0_DMA; - __IO uint32_t UEP1_DMA; - __IO uint32_t UEP2_DMA; - __IO uint32_t UEP3_DMA; - __IO uint32_t UEP4_DMA; - __IO uint32_t UEP5_DMA; - __IO uint32_t UEP6_DMA; - __IO uint32_t UEP7_DMA; - __IO uint16_t UEP0_TX_LEN; - union{ - __IO uint16_t UEP0_CTRL; - struct{ - __IO uint8_t UEP0_TX_CTRL; - __IO uint8_t UEP0_RX_CTRL; - }; - }; - __IO uint16_t UEP1_TX_LEN; - union{ - __IO uint16_t UEP1_CTRL; - struct{ - __IO uint8_t UEP1_TX_CTRL; - __IO uint8_t UEP1_RX_CTRL; - }; - }; - __IO uint16_t UEP2_TX_LEN; - union{ - __IO uint16_t UEP2_CTRL; - struct{ - __IO uint8_t UEP2_TX_CTRL; - __IO uint8_t UEP2_RX_CTRL; - }; - }; - __IO uint16_t UEP3_TX_LEN; - union{ - __IO uint16_t UEP3_CTRL; - struct{ - __IO uint8_t UEP3_TX_CTRL; - __IO uint8_t UEP3_RX_CTRL; - }; - }; - __IO uint16_t UEP4_TX_LEN; - union{ - __IO uint16_t UEP4_CTRL; - struct{ - __IO uint8_t UEP4_TX_CTRL; - __IO uint8_t UEP4_RX_CTRL; - }; - }; - __IO uint16_t UEP5_TX_LEN; - union{ - __IO uint16_t UEP5_CTRL; - struct{ - __IO uint8_t UEP5_TX_CTRL; - __IO uint8_t UEP5_RX_CTRL; - }; - }; - __IO uint16_t UEP6_TX_LEN; - union{ - __IO uint16_t UEP6_CTRL; - struct{ - __IO uint8_t UEP6_TX_CTRL; - __IO uint8_t UEP6_RX_CTRL; - }; - }; - __IO uint16_t UEP7_TX_LEN; - union{ - __IO uint16_t UEP7_CTRL; - struct{ - __IO uint8_t UEP7_TX_CTRL; - __IO uint8_t UEP7_RX_CTRL; - }; - }; - __IO uint32_t Reserve1; - __IO uint32_t OTG_CR; - __IO uint32_t OTG_SR; -} USBFSD_TypeDef; - -typedef struct -{ - __IO uint8_t BASE_CTRL; - __IO uint8_t HOST_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_ADDR; - __IO uint8_t Reserve0; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint16_t RX_LEN; - __IO uint16_t Reserve1; - __IO uint8_t Reserve2; - __IO uint8_t HOST_EP_MOD; - __IO uint16_t Reserve3; - __IO uint32_t Reserve4; - __IO uint32_t Reserve5; - __IO uint32_t HOST_RX_DMA; - __IO uint32_t HOST_TX_DMA; - __IO uint32_t Reserve6; - __IO uint32_t Reserve7; - __IO uint32_t Reserve8; - __IO uint32_t Reserve9; - __IO uint32_t Reserve10; - __IO uint16_t Reserve11; - __IO uint16_t HOST_SETUP; - __IO uint8_t HOST_EP_PID; - __IO uint8_t Reserve12; - __IO uint8_t Reserve13; - __IO uint8_t HOST_RX_CTRL; - __IO uint16_t HOST_TX_LEN; - __IO uint8_t HOST_TX_CTRL; - __IO uint8_t Reserve14; - __IO uint32_t Reserve15; - __IO uint32_t Reserve16; - __IO uint32_t Reserve17; - __IO uint32_t Reserve18; - __IO uint32_t Reserve19; - __IO uint32_t OTG_CR; - __IO uint32_t OTG_SR; -} USBFSH_TypeDef; - -/* Peripheral memory map */ -#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ - -#define PB1PERIPH_BASE (PERIPH_BASE) -#define PB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define HBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (PB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (PB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (PB1PERIPH_BASE + 0x0800) -#define RTC_BASE (PB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (PB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (PB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (PB1PERIPH_BASE + 0x3800) -#define USART2_BASE (PB1PERIPH_BASE + 0x4400) -#define USART3_BASE (PB1PERIPH_BASE + 0x4800) -#define USART4_BASE (PB1PERIPH_BASE + 0x4C00) -#define I2C1_BASE (PB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (PB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (PB1PERIPH_BASE + 0x6400) -#define BKP_BASE (PB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (PB1PERIPH_BASE + 0x7000) -#define LPTIM_BASE (PB1PERIPH_BASE + 0x7C00) - -#define AFIO_BASE (PB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (PB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (PB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (PB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (PB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (PB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (PB2PERIPH_BASE + 0x2400) -#define TIM1_BASE (PB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (PB2PERIPH_BASE + 0x3000) -#define USART1_BASE (PB2PERIPH_BASE + 0x3800) - -#define DMA1_BASE (HBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (HBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (HBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (HBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (HBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (HBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (HBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (HBPERIPH_BASE + 0x0080) -#define DMA1_Channel8_BASE (HBPERIPH_BASE + 0x0094) -#define RCC_BASE (HBPERIPH_BASE + 0x1000) -#define FLASH_R_BASE (HBPERIPH_BASE + 0x2000) -#define CRC_BASE (HBPERIPH_BASE + 0x3000) -#define EXTEN_BASE (HBPERIPH_BASE + 0x3800) -#define OPA_BASE (HBPERIPH_BASE + 0x6000) -#define USBPD_BASE (HBPERIPH_BASE + 0x7000) - -#define USBFS_BASE ((uint32_t)0x50000000) - -#define OB_BASE ((uint32_t)0x1FFFF800) - -#define TS_BASE ((uint32_t)0x1FFFF720) -#define OPA_TRIM_BASE ((uint32_t)0x1FFFF724) -#define ADC_TRIM_BASE ((uint32_t)0x1FFFF728) -#define HSI_LP_TRIM_BASE ((uint32_t)0x1FFFF72A) -#define CHIPID_BASE ((uint32_t)0x1FFFF704) - - -/* Peripheral declaration */ -#define TIM2 ((TIM_TypeDef *)TIM2_BASE) -#define TIM3 ((TIM_TypeDef *)TIM3_BASE) -#define TIM4 ((TIM_TypeDef *)TIM4_BASE) -#define RTC ((RTC_TypeDef *)RTC_BASE) -#define WWDG ((WWDG_TypeDef *)WWDG_BASE) -#define IWDG ((IWDG_TypeDef *)IWDG_BASE) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) -#define USART2 ((USART_TypeDef *)USART2_BASE) -#define USART3 ((USART_TypeDef *)USART3_BASE) -#define USART4 ((USART_TypeDef *)USART4_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define I2C2 ((I2C_TypeDef *)I2C2_BASE) -#define CAN1 ((CAN_TypeDef *)CAN1_BASE) -#define BKP ((BKP_TypeDef *)BKP_BASE) -#define PWR ((PWR_TypeDef *)PWR_BASE) -#define LPTIM ((LPTIM_TypeDef *)LPTIM_BASE) - -#define AFIO ((AFIO_TypeDef *)AFIO_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#define TKey1 ((ADC_TypeDef *)ADC1_BASE) -#define TIM1 ((TIM_TypeDef *)TIM1_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) - -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE) -#define RCC ((RCC_TypeDef *)RCC_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#define CRC ((CRC_TypeDef *)CRC_BASE) -#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE) -#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE) -#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) -#define OPA ((OPA_TypeDef *)OPA_BASE) -#define USBPD ((USBPD_TypeDef *)USBPD_BASE) - -#define OB ((OB_TypeDef *)OB_BASE) - - -/******************************************************************************/ -/* Peripheral Registers Bits Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* Analog to Digital Converter */ -/******************************************************************************/ - -/******************** Bit definition for ADC_STATR register ********************/ -#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ -#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ -#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ -#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ -#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ - -/******************* Bit definition for ADC_CTLR1 register ********************/ -#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ -#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ -#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ -#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ -#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ -#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ -#define ADC_RDISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ -#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ - -#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ -#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ - -#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ -#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ - -#define ADC_TKENABLE ((uint32_t)0x01000000) -#define ADC_TK1TUNE ((uint32_t)0x02000000) -#define ADC_BUFEN ((uint32_t)0x04000000) - -#define ADC_PGA ((uint32_t)0x18000000) /* PGA[1:0] bits */ -#define ADC_PGA_0 ((uint32_t)0x08000000) -#define ADC_PGA_1 ((uint32_t)0x10000000) - -/******************* Bit definition for ADC_CTLR2 register ********************/ -#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ -#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ -#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ -#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ -#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ -#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ - -#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ - -#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ -#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ -#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ - -#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ -#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ -#define ADC_RSWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ -#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ - -/****************** Bit definition for ADC_SAMPTR1 register *******************/ -#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ - -#define ADC_SMP18 ((uint32_t)0x07000000) /* SMP18[2:0] bits (Channel 18 Sample time selection) */ -#define ADC_SMP18_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define ADC_SMP18_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define ADC_SMP18_2 ((uint32_t)0x04000000) /* Bit 2 */ - -/****************** Bit definition for ADC_SAMPTR2 register *******************/ -#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ - -#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ -#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ -#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ - -/****************** Bit definition for ADC_IOFR1 register *******************/ -#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_IOFR2 register *******************/ -#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_IOFR3 register *******************/ -#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_IOFR4 register *******************/ -#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_WDHTR register ********************/ -#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ - -/******************* Bit definition for ADC_WDLTR register ********************/ -#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ - -/******************* Bit definition for ADC_RSQR1 register *******************/ -#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ -#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ - -/******************* Bit definition for ADC_RSQR2 register *******************/ -#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_RSQR3 register *******************/ -#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_ISQR register *******************/ -#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ -#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ - -/******************* Bit definition for ADC_IDATAR1 register *******************/ -#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR2 register *******************/ -#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR3 register *******************/ -#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR4 register *******************/ -#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************** Bit definition for ADC_RDATAR register ********************/ -#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ -/******************** Bit definition for ADC_CFG register ********************/ -#define ADC_BUFTRIM ((uint32_t)0x0000000F) /* BUFTRIM[3:0] bits */ -#define ADC_BUFTRIM_0 ((uint32_t)0x00000001) -#define ADC_BUFTRIM_1 ((uint32_t)0x00000002) -#define ADC_BUFTRIM_2 ((uint32_t)0x00000004) -#define ADC_BUFTRIM_3 ((uint32_t)0x00000008) - -#define ADC_AWDRST_EN ((uint32_t)0x00000010) -#define ADC_LP ((uint32_t)0x00000020) -#define ADC_FIFO_EN ((uint32_t)0x00000040) -#define ADC_DUTY_EN ((uint32_t)0x00000080) -#define ADC_TKEY_DRV_EN ((uint32_t)0x00000100) - -#define ADC_TKEY_DRV_OUTEN ((uint32_t)0x0007FE00) /* TKEY_DRV_OUTEN[9:0] bits */ -#define ADC_TKEY_DRV_OUTEN_0 ((uint32_t)0x00000200) -#define ADC_TKEY_DRV_OUTEN_1 ((uint32_t)0x00000400) -#define ADC_TKEY_DRV_OUTEN_2 ((uint32_t)0x00000800) -#define ADC_TKEY_DRV_OUTEN_3 ((uint32_t)0x00001000) -#define ADC_TKEY_DRV_OUTEN_4 ((uint32_t)0x00002000) -#define ADC_TKEY_DRV_OUTEN_5 ((uint32_t)0x00004000) -#define ADC_TKEY_DRV_OUTEN_6 ((uint32_t)0x00008000) -#define ADC_TKEY_DRV_OUTEN_7 ((uint32_t)0x00010000) -#define ADC_TKEY_DRV_OUTEN_8 ((uint32_t)0x00020000) -#define ADC_TKEY_DRV_OUTEN_9 ((uint32_t)0x00040000) - -#define ADC_TKEY_SEL ((uint32_t)0x00180000) /* TKEY_SEL[1:0] bits */ -#define ADC_TKEY_SEL_0 ((uint32_t)0x00080000) -#define ADC_TKEY_SEL_1 ((uint32_t)0x00080000) - -#define ADC_TKEY_WAKE_EN ((uint32_t)0x8FE00000) /* TKEY_WAKE_EN[9:0] bits */ -#define ADC_TKEY_WAKE_EN_0 ((uint32_t)0x00200000) -#define ADC_TKEY_WAKE_EN_1 ((uint32_t)0x00400000) -#define ADC_TKEY_WAKE_EN_2 ((uint32_t)0x00800000) -#define ADC_TKEY_WAKE_EN_3 ((uint32_t)0x01000000) -#define ADC_TKEY_WAKE_EN_4 ((uint32_t)0x02000000) -#define ADC_TKEY_WAKE_EN_5 ((uint32_t)0x04000000) -#define ADC_TKEY_WAKE_EN_6 ((uint32_t)0x08000000) -#define ADC_TKEY_WAKE_EN_7 ((uint32_t)0x10000000) -#define ADC_TKEY_WAKE_EN_8 ((uint32_t)0x20000000) -#define ADC_TKEY_WAKE_EN_9 ((uint32_t)0x40000000) - -/******************************************************************************/ -/* Backup registers */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DATAR1 register ********************/ -#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR2 register ********************/ -#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR3 register ********************/ -#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR4 register ********************/ -#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR5 register ********************/ -#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR6 register ********************/ -#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR7 register ********************/ -#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR8 register ********************/ -#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR9 register ********************/ -#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR10 register *******************/ -#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR11 register *******************/ -#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR12 register *******************/ -#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR13 register *******************/ -#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ - -/****************** Bit definition for BKP_OCTLR register *******************/ -#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ -#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ -#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ -#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_TPCTLR register ********************/ -#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ -#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ - -/******************* Bit definition for BKP_TPCSR register ********************/ -#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ -#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ -#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ -#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ -#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ - -/******************************************************************************/ -/* Controller Area Network */ -/******************************************************************************/ - -/******************* Bit definition for CAN_CTLR register ********************/ -#define CAN_CTLR_INRQ ((uint32_t)0x00000001) /* Initialization Request */ -#define CAN_CTLR_SLEEP ((uint32_t)0x00000002) /* Sleep Mode Request */ -#define CAN_CTLR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO Priority */ -#define CAN_CTLR_RFLM ((uint32_t)0x00000008) /* Receive FIFO Locked Mode */ -#define CAN_CTLR_NART ((uint32_t)0x00000010) /* No Automatic Retransmission */ -#define CAN_CTLR_AWUM ((uint32_t)0x00000020) /* Automatic Wakeup Mode */ -#define CAN_CTLR_ABOM ((uint32_t)0x00000040) /* Automatic Bus-Off Management */ -#define CAN_CTLR_TTCM ((uint32_t)0x00000080) /* Time Triggered Communication Mode */ -#define CAN_CTLR_RESET ((uint32_t)0x00008000) /* CAN software master reset */ -#define CAN_CTLR_DBF ((uint32_t)0x00010000) /* CAN controller operating state selection during debugging */ - -/******************* Bit definition for CAN_STATR register ********************/ -#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ -#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ -#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ -#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ -#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ -#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ -#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ -#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ -#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ - -/******************* Bit definition for CAN_TSTATR register ********************/ -#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ -#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ -#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ -#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ -#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ -#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ -#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ -#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ -#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ -#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ -#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ -#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ -#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ -#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ -#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ -#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ - -#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ -#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ -#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ -#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ - -#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ -#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ - -/******************* Bit definition for CAN_RFIFO0 register *******************/ -#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ -#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ -#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ -#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ - -/******************* Bit definition for CAN_RFIFO1 register *******************/ -#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ -#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ -#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ -#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ - -/******************** Bit definition for CAN_INTENR register *******************/ -#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ -#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ -#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ -#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ -#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ -#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ -#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ -#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ -#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ -#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ -#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ -#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ -#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ -#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ - -/******************** Bit definition for CAN_ERRSR register *******************/ -#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ -#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ -#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ - -#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ -#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ - -#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ -#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ - -/******************* Bit definition for CAN_BTIMR register ********************/ -#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) /* Baud Rate Prescaler */ -#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) /* Time Segment 1 */ -#define CAN_BTIMR_TS2 ((uint32_t)0x00700000) /* Time Segment 2 */ -#define CAN_BTIMR_SJW ((uint32_t)0x03000000) /* Resynchronization Jump Width */ -#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */ -#define CAN_BTIMR_SILM ((uint32_t)0x80000000) /* Silent Mode */ - -/******************** Bit definition for CAN_TTCTLR register *******************/ -#define CAN_TTCTLR_TIMCMV ((uint32_t)0x0000FFFF) -#define CAN_TTCTLR_TIMRST ((uint32_t)0x00010000) -#define CAN_TTCTLR_MODE ((uint32_t)0x00020000) - -/******************** Bit definition for CAN_TTCNT register *******************/ -#define CAN_TTCNT ((uint32_t)0x0000FFFF) - -/******************** Bit definition for CAN_TERR_CNT register *******************/ -#define CAN_TERR_CNT ((uint32_t)0x000001FF) - -/******************** Bit definition for CANFD_CR register *******************/ -#define CANFD_CR_TX_FD ((uint32_t)0x00000001) -#define CANFD_CR_TX_BRS_B ((uint32_t)0x0000000E) -#define CANFD_CR_USER_ESI_B ((uint32_t)0x00000070) -#define CANFD_CR_RES_EXCEPT ((uint32_t)0x00000080) -#define CANFD_CR_CLAS_LONG_TS1 ((uint32_t)0x00000100) -#define CANFD_CR_RESTRICT_MODE ((uint32_t)0x00000200) - -/******************** Bit definition for CANFD_BTR register *******************/ -#define CANFD_BTR_BTR_SJW_FD ((uint32_t)0x0000000F) -#define CANFD_BTR_BTR_TS2_FD ((uint32_t)0x000000F0) -#define CANFD_BTR_BTR_TS1_FD ((uint32_t)0x00001F00) -#define CANFD_BTR_BTR_BRP_FD ((uint32_t)0x001F0000) -#define CANFD_BTR_BTR_TDCE ((uint32_t)0x00800000) - -/******************** Bit definition for CANFD_TDCT register *******************/ -#define CANFD_TDCT_TDCO ((uint32_t)0x0000003F) -#define CANFD_TDCT_TDC_FILTER ((uint32_t)0x00003F00) - -/******************** Bit definition for CANFD_PSR register *******************/ -#define CANFD_PSR_TDCV ((uint32_t)0x00FF0000) - -/******************** Bit definition for CAN_DMA_T0 register *******************/ -#define CANFD_DMA_T0 ((uint32_t)0x00007FFF) - -/******************** Bit definition for CAN_DMA_T1 register *******************/ -#define CANFD_DMA_T1 ((uint32_t)0x00007FFF) - -/******************** Bit definition for CAN_DMA_T2 register *******************/ -#define CANFD_DMA_T2 ((uint32_t)0x00007FFF) - -/******************** Bit definition for CAN_DMA_R0 register *******************/ -#define CANFD_DMA_R0 ((uint32_t)0x00007FFF) - -/******************** Bit definition for CAN_DMA_R1 register *******************/ -#define CANFD_DMA_R1 ((uint32_t)0x00007FFF) - -/****************** Bit definition for CAN_TXMI0R register ********************/ -#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ -#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/****************** Bit definition for CAN_TXMDT0R register *******************/ -#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ -#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/****************** Bit definition for CAN_TXMDL0R register *******************/ -#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/****************** Bit definition for CAN_TXMDH0R register *******************/ -#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_TXMI1R register *******************/ -#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ -#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TXMDT1R register ******************/ -#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ -#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_TXMDL1R register ******************/ -#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_TXMDH1R register ******************/ -#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_TXMI2R register *******************/ -#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ -#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TXMDT2R register ******************/ -#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ -#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_TXMDL2R register ******************/ -#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_TXMDH2R register ******************/ -#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_RXMI0R register *******************/ -#define CAN_RXMIOR_FDF ((uint32_t)0x00000001) -#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ -#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RXMDT0R register ******************/ -#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_RXMDT0R_BRS ((uint32_t)0x00000010) -#define CAN_RXMDT0R_ESI ((uint32_t)0x00000020) -#define CAN_RXMDH0R_RES ((uint32_t)0x00000100) -#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ -#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_RXMDL0R register ******************/ -#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_RXMDH0R register ******************/ -#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_RXMI1R register *******************/ -#define CAN_RXMI1R_FDF ((uint32_t)0x00000001) -#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ -#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RXMDT1R register ******************/ -#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_RXMDT1R_BRS ((uint32_t)0x00000010) -#define CAN_RXMDT1R_ESI ((uint32_t)0x00000020) -#define CAN_RXMDH1R_RES ((uint32_t)0x00000100) -#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ -#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_RXMDL1R register ******************/ -#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_RXMDH1R register ******************/ -#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_FCTLR register ********************/ -#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ - -/******************* Bit definition for CAN_FMCFGR register *******************/ -#define CAN_FMCFGR_FBM ((uint32_t)0x00003FFF) /* Filter Mode */ -#define CAN_FMCFGR_FBM0 ((uint32_t)0x00000001) /* Filter Init Mode bit 0 */ -#define CAN_FMCFGR_FBM1 ((uint32_t)0x00000002) /* Filter Init Mode bit 1 */ -#define CAN_FMCFGR_FBM2 ((uint32_t)0x00000004) /* Filter Init Mode bit 2 */ -#define CAN_FMCFGR_FBM3 ((uint32_t)0x00000008) /* Filter Init Mode bit 3 */ -#define CAN_FMCFGR_FBM4 ((uint32_t)0x00000010) /* Filter Init Mode bit 4 */ -#define CAN_FMCFGR_FBM5 ((uint32_t)0x00000020) /* Filter Init Mode bit 5 */ -#define CAN_FMCFGR_FBM6 ((uint32_t)0x00000040) /* Filter Init Mode bit 6 */ -#define CAN_FMCFGR_FBM7 ((uint32_t)0x00000080) /* Filter Init Mode bit 7 */ -#define CAN_FMCFGR_FBM8 ((uint32_t)0x00000100) /* Filter Init Mode bit 8 */ -#define CAN_FMCFGR_FBM9 ((uint32_t)0x00000200) /* Filter Init Mode bit 9 */ -#define CAN_FMCFGR_FBM10 ((uint32_t)0x00000400) /* Filter Init Mode bit 10 */ -#define CAN_FMCFGR_FBM11 ((uint32_t)0x00000800) /* Filter Init Mode bit 11 */ -#define CAN_FMCFGR_FBM12 ((uint32_t)0x00001000) /* Filter Init Mode bit 12 */ -#define CAN_FMCFGR_FBM13 ((uint32_t)0x00002000) /* Filter Init Mode bit 13 */ -#define CAN_FMCFGR_FBM14 ((uint32_t)0x00004000) /* Filter Init Mode bit 14 */ -#define CAN_FMCFGR_FBM15 ((uint32_t)0x00008000) /* Filter Init Mode bit 15 */ -#define CAN_FMCFGR_FBM16 ((uint32_t)0x00010000) /* Filter Init Mode bit 16 */ -#define CAN_FMCFGR_FBM17 ((uint32_t)0x00020000) /* Filter Init Mode bit 17 */ -#define CAN_FMCFGR_FBM18 ((uint32_t)0x00040000) /* Filter Init Mode bit 18 */ -#define CAN_FMCFGR_FBM19 ((uint32_t)0x00080000) /* Filter Init Mode bit 19 */ -#define CAN_FMCFGR_FBM20 ((uint32_t)0x00100000) /* Filter Init Mode bit 20 */ -#define CAN_FMCFGR_FBM21 ((uint32_t)0x00200000) /* Filter Init Mode bit 21 */ -#define CAN_FMCFGR_FBM22 ((uint32_t)0x00400000) /* Filter Init Mode bit 22 */ -#define CAN_FMCFGR_FBM23 ((uint32_t)0x00800000) /* Filter Init Mode bit 23 */ -#define CAN_FMCFGR_FBM24 ((uint32_t)0x01000000) /* Filter Init Mode bit 24 */ -#define CAN_FMCFGR_FBM25 ((uint32_t)0x02000000) /* Filter Init Mode bit 25 */ -#define CAN_FMCFGR_FBM26 ((uint32_t)0x04000000) /* Filter Init Mode bit 26 */ -#define CAN_FMCFGR_FBM27 ((uint32_t)0x08000000) /* Filter Init Mode bit 27 */ - -/******************* Bit definition for CAN_FSCFGR register *******************/ -#define CAN_FSCFGR_FSC ((uint32_t)0x00003FFF) /* Filter Scale Configuration */ -#define CAN_FSCFGR_FSC0 ((uint32_t)0x00000001) /* Filter Scale Configuration bit 0 */ -#define CAN_FSCFGR_FSC1 ((uint32_t)0x00000002) /* Filter Scale Configuration bit 1 */ -#define CAN_FSCFGR_FSC2 ((uint32_t)0x00000004) /* Filter Scale Configuration bit 2 */ -#define CAN_FSCFGR_FSC3 ((uint32_t)0x00000008) /* Filter Scale Configuration bit 3 */ -#define CAN_FSCFGR_FSC4 ((uint32_t)0x00000010) /* Filter Scale Configuration bit 4 */ -#define CAN_FSCFGR_FSC5 ((uint32_t)0x00000020) /* Filter Scale Configuration bit 5 */ -#define CAN_FSCFGR_FSC6 ((uint32_t)0x00000040) /* Filter Scale Configuration bit 6 */ -#define CAN_FSCFGR_FSC7 ((uint32_t)0x00000080) /* Filter Scale Configuration bit 7 */ -#define CAN_FSCFGR_FSC8 ((uint32_t)0x00000100) /* Filter Scale Configuration bit 8 */ -#define CAN_FSCFGR_FSC9 ((uint32_t)0x00000200) /* Filter Scale Configuration bit 9 */ -#define CAN_FSCFGR_FSC10 ((uint32_t)0x00000400) /* Filter Scale Configuration bit 10 */ -#define CAN_FSCFGR_FSC11 ((uint32_t)0x00000800) /* Filter Scale Configuration bit 11 */ -#define CAN_FSCFGR_FSC12 ((uint32_t)0x00001000) /* Filter Scale Configuration bit 12 */ -#define CAN_FSCFGR_FSC13 ((uint32_t)0x00002000) /* Filter Scale Configuration bit 13 */ -#define CAN_FSCFGR_FSC14 ((uint32_t)0x00004000) /* Filter Scale Configuration bit 14 */ -#define CAN_FSCFGR_FSC15 ((uint32_t)0x00008000) /* Filter Scale Configuration bit 15 */ -#define CAN_FSCFGR_FSC16 ((uint32_t)0x00010000) /* Filter Scale Configuration bit 16 */ -#define CAN_FSCFGR_FSC17 ((uint32_t)0x00020000) /* Filter Scale Configuration bit 17 */ -#define CAN_FSCFGR_FSC18 ((uint32_t)0x00040000) /* Filter Scale Configuration bit 18 */ -#define CAN_FSCFGR_FSC19 ((uint32_t)0x00080000) /* Filter Scale Configuration bit 19 */ -#define CAN_FSCFGR_FSC20 ((uint32_t)0x00100000) /* Filter Scale Configuration bit 20 */ -#define CAN_FSCFGR_FSC21 ((uint32_t)0x00200000) /* Filter Scale Configuration bit 21 */ -#define CAN_FSCFGR_FSC22 ((uint32_t)0x00400000) /* Filter Scale Configuration bit 22 */ -#define CAN_FSCFGR_FSC23 ((uint32_t)0x00800000) /* Filter Scale Configuration bit 23 */ -#define CAN_FSCFGR_FSC24 ((uint32_t)0x01000000) /* Filter Scale Configuration bit 24 */ -#define CAN_FSCFGR_FSC25 ((uint32_t)0x02000000) /* Filter Scale Configuration bit 25 */ -#define CAN_FSCFGR_FSC26 ((uint32_t)0x04000000) /* Filter Scale Configuration bit 26 */ -#define CAN_FSCFGR_FSC27 ((uint32_t)0x08000000) /* Filter Scale Configuration bit 27 */ - -/****************** Bit definition for CAN_FAFIFOR register *******************/ -#define CAN_FAFIFOR_FFA ((uint32_t)0x00003FFF) /* Filter FIFO Assignment */ -#define CAN_FAFIFOR_FFA0 ((uint32_t)0x00000001) /* Filter FIFO Assignment for Filter 0 */ -#define CAN_FAFIFOR_FFA1 ((uint32_t)0x00000002) /* Filter FIFO Assignment for Filter 1 */ -#define CAN_FAFIFOR_FFA2 ((uint32_t)0x00000004) /* Filter FIFO Assignment for Filter 2 */ -#define CAN_FAFIFOR_FFA3 ((uint32_t)0x00000008) /* Filter FIFO Assignment for Filter 3 */ -#define CAN_FAFIFOR_FFA4 ((uint32_t)0x00000010) /* Filter FIFO Assignment for Filter 4 */ -#define CAN_FAFIFOR_FFA5 ((uint32_t)0x00000020) /* Filter FIFO Assignment for Filter 5 */ -#define CAN_FAFIFOR_FFA6 ((uint32_t)0x00000040) /* Filter FIFO Assignment for Filter 6 */ -#define CAN_FAFIFOR_FFA7 ((uint32_t)0x00000080) /* Filter FIFO Assignment for Filter 7 */ -#define CAN_FAFIFOR_FFA8 ((uint32_t)0x00000100) /* Filter FIFO Assignment for Filter 8 */ -#define CAN_FAFIFOR_FFA9 ((uint32_t)0x00000200) /* Filter FIFO Assignment for Filter 9 */ -#define CAN_FAFIFOR_FFA10 ((uint32_t)0x00000400) /* Filter FIFO Assignment for Filter 10 */ -#define CAN_FAFIFOR_FFA11 ((uint32_t)0x00000800) /* Filter FIFO Assignment for Filter 11 */ -#define CAN_FAFIFOR_FFA12 ((uint32_t)0x00001000) /* Filter FIFO Assignment for Filter 12 */ -#define CAN_FAFIFOR_FFA13 ((uint32_t)0x00002000) /* Filter FIFO Assignment for Filter 13 */ -#define CAN_FAFIFOR_FFA14 ((uint32_t)0x00004000) /* Filter FIFO Assignment for Filter 14 */ -#define CAN_FAFIFOR_FFA15 ((uint32_t)0x00008000) /* Filter FIFO Assignment for Filter 15 */ -#define CAN_FAFIFOR_FFA16 ((uint32_t)0x00010000) /* Filter FIFO Assignment for Filter 16 */ -#define CAN_FAFIFOR_FFA17 ((uint32_t)0x00020000) /* Filter FIFO Assignment for Filter 17 */ -#define CAN_FAFIFOR_FFA18 ((uint32_t)0x00040000) /* Filter FIFO Assignment for Filter 18 */ -#define CAN_FAFIFOR_FFA19 ((uint32_t)0x00080000) /* Filter FIFO Assignment for Filter 19 */ -#define CAN_FAFIFOR_FFA20 ((uint32_t)0x00100000) /* Filter FIFO Assignment for Filter 20 */ -#define CAN_FAFIFOR_FFA21 ((uint32_t)0x00200000) /* Filter FIFO Assignment for Filter 21 */ -#define CAN_FAFIFOR_FFA22 ((uint32_t)0x00400000) /* Filter FIFO Assignment for Filter 22 */ -#define CAN_FAFIFOR_FFA23 ((uint32_t)0x00800000) /* Filter FIFO Assignment for Filter 23 */ -#define CAN_FAFIFOR_FFA24 ((uint32_t)0x01000000) /* Filter FIFO Assignment for Filter 24 */ -#define CAN_FAFIFOR_FFA25 ((uint32_t)0x02000000) /* Filter FIFO Assignment for Filter 25 */ -#define CAN_FAFIFOR_FFA26 ((uint32_t)0x04000000) /* Filter FIFO Assignment for Filter 26 */ -#define CAN_FAFIFOR_FFA27 ((uint32_t)0x08000000) /* Filter FIFO Assignment for Filter 27 */ - -/******************* Bit definition for CAN_FWR register *******************/ -#define CAN_FWR_FACT ((uint32_t)0x00003FFF) /* Filter Active */ -#define CAN_FWR_FACT0 ((uint32_t)0x00000001) /* Filter 0 Active */ -#define CAN_FWR_FACT1 ((uint32_t)0x00000002) /* Filter 1 Active */ -#define CAN_FWR_FACT2 ((uint32_t)0x00000004) /* Filter 2 Active */ -#define CAN_FWR_FACT3 ((uint32_t)0x00000008) /* Filter 3 Active */ -#define CAN_FWR_FACT4 ((uint32_t)0x00000010) /* Filter 4 Active */ -#define CAN_FWR_FACT5 ((uint32_t)0x00000020) /* Filter 5 Active */ -#define CAN_FWR_FACT6 ((uint32_t)0x00000040) /* Filter 6 Active */ -#define CAN_FWR_FACT7 ((uint32_t)0x00000080) /* Filter 7 Active */ -#define CAN_FWR_FACT8 ((uint32_t)0x00000100) /* Filter 8 Active */ -#define CAN_FWR_FACT9 ((uint32_t)0x00000200) /* Filter 9 Active */ -#define CAN_FWR_FACT10 ((uint32_t)0x00000400) /* Filter 10 Active */ -#define CAN_FWR_FACT11 ((uint32_t)0x00000800) /* Filter 11 Active */ -#define CAN_FWR_FACT12 ((uint32_t)0x00001000) /* Filter 12 Active */ -#define CAN_FWR_FACT13 ((uint32_t)0x00002000) /* Filter 13 Active */ -#define CAN_FWR_FACT14 ((uint32_t)0x00004000) /* Filter 14 Active */ -#define CAN_FWR_FACT15 ((uint32_t)0x00008000) /* Filter 15 Active */ -#define CAN_FWR_FACT16 ((uint32_t)0x00010000) /* Filter 16 Active */ -#define CAN_FWR_FACT17 ((uint32_t)0x00020000) /* Filter 17 Active */ -#define CAN_FWR_FACT18 ((uint32_t)0x00040000) /* Filter 18 Active */ -#define CAN_FWR_FACT19 ((uint32_t)0x00080000) /* Filter 19 Active */ -#define CAN_FWR_FACT20 ((uint32_t)0x00100000) /* Filter 20 Active */ -#define CAN_FWR_FACT21 ((uint32_t)0x00200000) /* Filter 21 Active */ -#define CAN_FWR_FACT22 ((uint32_t)0x00400000) /* Filter 22 Active */ -#define CAN_FWR_FACT23 ((uint32_t)0x00800000) /* Filter 23 Active */ -#define CAN_FWR_FACT24 ((uint32_t)0x01000000) /* Filter 24 Active */ -#define CAN_FWR_FACT25 ((uint32_t)0x02000000) /* Filter 25 Active */ -#define CAN_FWR_FACT26 ((uint32_t)0x04000000) /* Filter 26 Active */ -#define CAN_FWR_FACT27 ((uint32_t)0x08000000) /* Filter 27 Active */ - -/******************* Bit definition for CAN_F0R1 register *******************/ -#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F1R1 register *******************/ -#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F2R1 register *******************/ -#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F3R1 register *******************/ -#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F4R1 register *******************/ -#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F5R1 register *******************/ -#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F6R1 register *******************/ -#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F7R1 register *******************/ -#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F8R1 register *******************/ -#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F9R1 register *******************/ -#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F10R1 register ******************/ -#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F11R1 register ******************/ -#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F12R1 register ******************/ -#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F13R1 register ******************/ -#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F0R2 register *******************/ -#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F1R2 register *******************/ -#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F2R2 register *******************/ -#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F3R2 register *******************/ -#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F4R2 register *******************/ -#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F5R2 register *******************/ -#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F6R2 register *******************/ -#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F7R2 register *******************/ -#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F8R2 register *******************/ -#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F9R2 register *******************/ -#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F10R2 register ******************/ -#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F11R2 register ******************/ -#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F12R2 register ******************/ -#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F13R2 register ******************/ -#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************************************************************************/ -/* CRC Calculation Unit */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DATAR register *********************/ -#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ - -/******************* Bit definition for CRC_IDATAR register ********************/ -#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ - -/******************** Bit definition for CRC_CTLR register ********************/ -#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ - -/******************************************************************************/ -/* DMA Controller */ -/******************************************************************************/ - -/******************* Bit definition for DMA_INTFR register ********************/ -#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ -#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ -#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ -#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ -#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ -#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ -#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ -#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ -#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ -#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ -#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ -#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ -#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ -#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ -#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ -#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ -#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ -#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ -#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ -#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ -#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ -#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ -#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ -#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ -#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ -#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ -#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ -#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ -#define DMA_GIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt flag */ -#define DMA_TCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete flag */ -#define DMA_HTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer flag */ -#define DMA_TEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error flag */ - -/******************* Bit definition for DMA_INTFCR register *******************/ -#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ -#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ -#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ -#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ -#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ -#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ -#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ -#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ -#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ -#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ -#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ -#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ -#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ -#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ -#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ -#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ -#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ -#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ -#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ -#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ -#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ -#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ -#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ -#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ -#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ -#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ -#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ -#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ -#define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */ -#define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */ -#define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */ -#define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */ - -/******************* Bit definition for DMA_CFGR1 register *******************/ -#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ -#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ -#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR2 register *******************/ -#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR3 register *******************/ -#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG4 register *******************/ -#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/****************** Bit definition for DMA_CFG5 register *******************/ -#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/******************* Bit definition for DMA_CFG6 register *******************/ -#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG7 register *******************/ -#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/****************** Bit definition for DMA_CNTR1 register ******************/ -#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR2 register ******************/ -#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR3 register ******************/ -#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR4 register ******************/ -#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR5 register ******************/ -#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR6 register ******************/ -#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR7 register ******************/ -#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR8 register ******************/ -#define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_PADDR1 register *******************/ -#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR2 register *******************/ -#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR3 register *******************/ -#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR4 register *******************/ -#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR5 register *******************/ -#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR6 register *******************/ -#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR7 register *******************/ -#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR8 register *******************/ -#define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_MADDR1 register *******************/ -#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR2 register *******************/ -#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR3 register *******************/ -#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR4 register *******************/ -#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR5 register *******************/ -#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR6 register *******************/ -#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR7 register *******************/ -#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR8 register *******************/ -#define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/******************************************************************************/ -/* External Interrupt/Event Controller */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_INTENR register *******************/ -#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ -#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ -#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ -#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ -#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ -#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ -#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ -#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ -#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ -#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ -#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ -#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ -#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ -#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ -#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ -#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ -#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ -#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ -#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ -#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ -#define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */ -#define EXTI_INTENR_MR21 ((uint32_t)0x00200000) /* Interrupt Mask on line 21 */ -#define EXTI_INTENR_MR22 ((uint32_t)0x00400000) /* Interrupt Mask on line 22 */ - -/******************* Bit definition for EXTI_EVENR register *******************/ -#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ -#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ -#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ -#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ -#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ -#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ -#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ -#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ -#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ -#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ -#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ -#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ -#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ -#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ -#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ -#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ -#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ -#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ -#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ -#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ -#define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */ -#define EXTI_EVENR_MR21 ((uint32_t)0x00200000) /* Event Mask on line 21 */ -#define EXTI_EVENR_MR22 ((uint32_t)0x00400000) /* Event Mask on line 22 */ - -/****************** Bit definition for EXTI_RTENR register *******************/ -#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ -#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ -#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ -#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ -#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ -#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ -#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ -#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ -#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ -#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ -#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ -#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ -#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ -#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ -#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ -#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ -#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ -#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ -#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ -#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ -#define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */ -#define EXTI_RTENR_TR21 ((uint32_t)0x00200000) /* Rising trigger event configuration bit of line 21 */ -#define EXTI_RTENR_TR22 ((uint32_t)0x00400000) /* Rising trigger event configuration bit of line 22 */ - -/****************** Bit definition for EXTI_FTENR register *******************/ -#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ -#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ -#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ -#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ -#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ -#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ -#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ -#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ -#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ -#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ -#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ -#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ -#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ -#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ -#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ -#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ -#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ -#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ -#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ -#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ -#define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */ -#define EXTI_FTENR_TR21 ((uint32_t)0x00200000) /* Falling trigger event configuration bit of line 21 */ -#define EXTI_FTENR_TR22 ((uint32_t)0x00400000) /* Falling trigger event configuration bit of line 22 */ - -/****************** Bit definition for EXTI_SWIEVR register ******************/ -#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ -#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ -#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ -#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ -#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ -#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ -#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ -#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ -#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ -#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ -#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ -#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ -#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ -#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ -#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ -#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ -#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ -#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ -#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ -#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ -#define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */ -#define EXTI_SWIEVR_SWIEVR21 ((uint32_t)0x00200000) /* Software Interrupt on line 21 */ -#define EXTI_SWIEVR_SWIEVR22 ((uint32_t)0x00400000) /* Software Interrupt on line 22 */ - -/******************* Bit definition for EXTI_INTFR register ********************/ -#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ -#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ -#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ -#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ -#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ -#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ -#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ -#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ -#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ -#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ -#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ -#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ -#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ -#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ -#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ -#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ -#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ -#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ -#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ -#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ -#define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */ -#define EXTI_INTF_INTF21 ((uint32_t)0x00200000) /* Pending bit for line 21 */ -#define EXTI_INTF_INTF22 ((uint32_t)0x00400000) /* Pending bit for line 22 */ - -/******************************************************************************/ -/* FLASH and Option Bytes Registers */ -/******************************************************************************/ - -/******************* Bit definition for FLASH_ACTLR register ******************/ -#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[1:0] bits (Latency) */ -#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ - -/***************** Bit definition for FLASH_OBKEYR register ****************/ -#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ - -/****************** Bit definition for FLASH_STATR register *******************/ -#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ -#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ -#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ -#define FLASH_STATR_FWAKE_FLAG ((uint8_t)0x40) -#define FLASH_STATR_TURBO ((uint8_t)0x80) - -/******************* Bit definition for FLASH_CTLR register *******************/ -#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 1K */ -#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ -#define FLASH_CTLR_OBPG ((uint32_t)0x00000010) /* Option Byte Programming */ -#define FLASH_CTLR_OBER ((uint32_t)0x00000020) /* Option Byte Erase */ -#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ -#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ -#define FLASH_CTLR_OBWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ -#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ -#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ -#define FLASH_CTLR_FWAKEIE ((uint32_t)0x00002000) -#define FLASH_CTLR_FLOCK ((uint32_t)0x00008000) /* Fast Lock */ -#define FLASH_CTLR_FTPG ((uint32_t)0x00010000) /* Page Programming 256Byte */ -#define FLASH_CTLR_FTER ((uint32_t)0x00020000) /* Page Erase 256Byte */ -#define FLASH_CTLR_BUFLOAD ((uint32_t)0x00040000) -#define FLASH_CTLR_BUFRST ((uint32_t)0x00080000) -#define FLASH_CTLR_BER32 ((uint32_t)0x00800000) /* Block Erase 32K */ - -/******************* Bit definition for FLASH_ADDR register *******************/ -#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OBERR ((uint32_t)0x00000001) /* Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /* Read protection */ - -#define FLASH_OBR_USER ((uint32_t)0x000000FC) /* User Option Bytes */ -#define FLASH_OBR_iWDG_SW ((uint32_t)0x00000004) /* WDG_SW */ -#define FLASH_OBR_STOP_nRST ((uint32_t)0x00000008) /* nRST_STOP */ -#define FLASH_OBR_STANDY_nRST ((uint32_t)0x00000010) /* nRST_STDBY */ -#define FLASH_OBR_CFGCANM ((uint32_t)0x00000080) - -#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) /* DATA0 */ -#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) /* DATA1 */ - -/****************** Bit definition for FLASH_WPR register ******************/ -#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ - -/****************** Bit definition for FLASH_OBR_MODEKEYR register ******************/ -#define FLASH_OBR_MODEKEYR ((uint32_t)0xFFFFFFFF) - -/****************** Bit definition for FLASH_RDPR register *******************/ -#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ -#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_WRPR0 register ******************/ -#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR1 register ******************/ -#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR2 register ******************/ -#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR3 register ******************/ -#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ - -/******************************************************************************/ -/* General Purpose and Alternate Function I/O */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CFGLR register *******************/ -#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_CFGHR register *******************/ -#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_INDR register *******************/ -#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ -#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ -#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ -#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ -#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ -#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ -#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ -#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ -#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ -#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ -#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ -#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ -#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ -#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ -#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ -#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ - -/******************* Bit definition for GPIO_OUTDR register *******************/ -#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ -#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ -#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ -#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ -#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ -#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ -#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ -#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ -#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ -#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ -#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ -#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ -#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ -#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ -#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ -#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSHR register *******************/ -#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ -#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ -#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ -#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ -#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ -#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ -#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ -#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ -#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ -#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ -#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ -#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ -#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ -#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ -#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ -#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ - -#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ -#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ -#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ -#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ -#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ -#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ -#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ -#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ -#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ -#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ -#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ -#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ -#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ -#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ -#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ -#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BCR register *******************/ -#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ -#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ -#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ -#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ -#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ -#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ -#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ -#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ -#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ -#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ -#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ -#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ -#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ -#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ -#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ -#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ -#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ -#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ -#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ -#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ -#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ -#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ -#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ -#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ -#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ -#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ -#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ -#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ -#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ -#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ -#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ -#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ - -/****************** Bit definition for AFIO_ECR register *******************/ -#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ -#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ -#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ -#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ -#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ - -#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ -#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ -#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ -#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ -#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ -#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ -#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ -#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ -#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ -#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ -#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ -#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ -#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ -#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ -#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ -#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ - -#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ -#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ -#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ -#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ - -#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ -#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ -#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ -#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ - -#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ - -/****************** Bit definition for AFIO_PCFR1register *******************/ -#define AFIO_PCFR1_SPI1_RM ((uint32_t)0x00000001) /* SPI1 remapping */ -#define AFIO_PCFR1_I2C1_RM ((uint32_t)0x00000002) /* I2C1 remapping */ -#define AFIO_PCFR1_USART1_RM ((uint32_t)0x00000004) /* USART1 remapping */ -#define AFIO_PCFR1_USART2_RM ((uint32_t)0x00000008) /* USART2 remapping */ - -#define AFIO_PCFR1_USART3_RM ((uint32_t)0x00000030) /* USART3_RM[1:0] bits (USART3 remapping) */ -#define AFIO_PCFR1_USART3_RM_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define AFIO_PCFR1_USART3_RM_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define AFIO_PCFR1_TIM1_RM ((uint32_t)0x000000C0) /* TIM1_RM[1:0] bits (TIM1 remapping) */ -#define AFIO_PCFR1_TIM1_RM_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define AFIO_PCFR1_TIM1_RM_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define AFIO_PCFR1_TIM2_RM ((uint32_t)0x00000300) /* TIM2_RM[1:0] bits (TIM2 remapping) */ -#define AFIO_PCFR1_TIM2_RM_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define AFIO_PCFR1_TIM2_RM_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define AFIO_PCFR1_TIM3_RM ((uint32_t)0x00000400) /* TIM3_RM bits (TIM3 remapping) */ - -#define AFIO_PCFR1_TIM4_RM ((uint32_t)0x00001000) /* TIM4_RM bit (TIM4 remapping) */ - -#define AFIO_PCFR1_CAN_RM ((uint32_t)0x00006000) /* CAN_RM[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_PCFR1_CAN_RM_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define AFIO_PCFR1_CAN_RM_1 ((uint32_t)0x00004000) /* Bit 1 */ - -#define AFIO_PCFR1_PD01_RM ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ - -#define AFIO_PCFR1_SW_CFG ((uint32_t)0x07000000) /* SW_CFG[2:0] bits (SDI configuration) */ -#define AFIO_PCFR1_SW_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define AFIO_PCFR1_SW_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define AFIO_PCFR1_SW_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ - -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ - -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ - -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ - -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ - -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ - -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ - -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ - -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ - -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ - -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ - -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ - -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ - -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ - -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ - -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ - -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ - -/***************** Bit definition for AFIO_CR register *****************/ -#define AFIO_CR_USBPD_IN_HVT ((uint32_t)0x00000200) -#define AFIO_CR_UPD_BC_VSRC ((uint32_t)0x00010000) -#define AFIO_CR_UDM_BC_VSRC ((uint32_t)0x00020000) -#define AFIO_CR_UPD_BC_CMPE ((uint32_t)0x00040000) -#define AFIO_CR_UDM_BC_CMPE ((uint32_t)0x00080000) -#define AFIO_CR_UPD_BC_CMPO ((uint32_t)0x00100000) -#define AFIO_CR_UDM_BC_CMPO ((uint32_t)0x00200000) - -/***************** Bit definition for AFIO_PCFR2 register *****************/ -#define AFIO_PCFR2_USART4_RM ((uint32_t)0x00010000) -#define AFIO_PCFR2_USART2_RM_H ((uint32_t)0x00040000) - -#define AFIO_PCFR2_USART1_RM_H ((uint32_t)0x00180000) -#define AFIO_PCFR2_USART1_RM_H_0 ((uint32_t)0x00080000) -#define AFIO_PCFR2_USART1_RM_H_1 ((uint32_t)0x00100000) - -#define AFIO_PCFR2_TIM2_RM_H ((uint32_t)0x00200000) -#define AFIO_PCFR2_TIM1_RM_H ((uint32_t)0x00400000) -#define AFIO_PCFR2_I2C_RM_H ((uint32_t)0x00800000) -#define AFIO_PCFR2_SPI1_RM_H ((uint32_t)0x01000000) -#define AFIO_PCFR2_LPTIM_RM ((uint32_t)0x02000000) - -/******************************************************************************/ -/* Independent WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_CTLR register ********************/ -#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PSCR register ********************/ -#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ -#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ -#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ -#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ - -/******************* Bit definition for IWDG_RLDR register *******************/ -#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ - -/******************* Bit definition for IWDG_STATR register ********************/ -#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ -#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ - -/******************************************************************************/ -/* Inter-integrated Circuit Interface */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CTLR1 register ********************/ -#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ -#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ -#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ -#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ -#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ -#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ -#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ -#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ -#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ -#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ -#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ -#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ -#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ -#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ - -/******************* Bit definition for I2C_CTLR2 register ********************/ -#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ - -#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ -#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ -#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ -#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ -#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ - -/******************* Bit definition for I2C_OADDR1 register *******************/ -#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ -#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ - -#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ -#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ -#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ -#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ -#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ - -#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OADDR2 register *******************/ -#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ -#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ - -/******************** Bit definition for I2C_DATAR register ********************/ -#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ - -/******************* Bit definition for I2C_STAR1 register ********************/ -#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ -#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ -#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ -#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ -#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ -#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ -#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ -#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ -#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ -#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ -#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ -#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ -#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ -#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ - -/******************* Bit definition for I2C_STAR2 register ********************/ -#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ -#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ -#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ -#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ -#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ -#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ -#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ -#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ - -/******************* Bit definition for I2C_CKCFGR register ********************/ -#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ -#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ - -/****************** Bit definition for I2C_RTR register *******************/ -#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ - -/******************************************************************************/ -/* Power Control */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CTLR register ********************/ -#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ -#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ -#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ -#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ -#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ - -#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ -#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ - -#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) /* PVD level 0 */ -#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) /* PVD level 1 */ -#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) /* PVD level 2 */ -#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) /* PVD level 3 */ -#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080) /* PVD level 4 */ -#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0) /* PVD level 5 */ -#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0) /* PVD level 6 */ -#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0) /* PVD level 7 */ - -#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ - -#define PWR_CTLR_FLASH_LP_REG ((uint16_t)0x0200) - -#define PWR_CTLR_FLASH_LP ((uint16_t)0x0C00) /* FLASH_LP [1:0]*/ -#define PWR_CTLR_FLASH_LP_0 ((uint16_t)0x0400) -#define PWR_CTLR_FLASH_LP_1 ((uint16_t)0x0800) - -#define PWR_CTLR_AUTO_LDO_EC ((uint16_t)0x1000) -#define PWR_CTLR_LDO_EC ((uint16_t)0x2000) -#define PWR_CTLR_R2KSTY ((uint32_t)0x00010000) -#define PWR_CTLR_R18KSTY ((uint32_t)0x00020000) -#define PWR_CTLR_R2KVBAT ((uint32_t)0x00040000) -#define PWR_CTLR_R18KVBAT ((uint32_t)0x00080000) -#define PWR_RAMLV ((uint32_t)0x00100000) - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ - -/******************************************************************************/ -/* Reset and Clock Control */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CTLR register ********************/ -#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ -#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ -#define RCC_HSILP ((uint32_t)0x00000004) -#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ -#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ -#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ -#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ -#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ -#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ -#define RCC_HSELP ((uint32_t)0x00100000) -#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ -#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ - -/******************* Bit definition for RCC_CFGR0 register *******************/ -#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ -#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ -#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ -#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ - -#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ -#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ -#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ - -#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (HB prescaler) */ -#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ -#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ - -#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ -#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ -#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ -#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ -#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ -#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ -#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ -#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ -#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ - -#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (PB1 prescaler) */ -#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ -#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ - -#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* PPRE1 not divided */ -#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* PPRE1 divided by 2 */ -#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* PPRE1 divided by 4 */ -#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* PPRE1 divided by 8 */ -#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* PPRE1 divided by 16 */ - -#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (PB2 prescaler) */ -#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ -#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ -#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ - -#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* PPRE2 not divided */ -#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* PPRE2 divided by 2 */ -#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* PPRE2 divided by 4 */ -#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* PPRE2 divided by 8 */ -#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* PPRE2 divided by 16 */ - -#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* ADCPRE divided by 2 */ -#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* ADCPRE divided by 4 */ -#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* ADCPRE divided by 6 */ -#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* ADCPRE divided by 8 */ - -#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ - -#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ - -#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ -#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ - -#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ -#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ - -#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ -#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ - -/* for other CH32L103 */ -#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ -#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ -#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ -#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ -#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ -#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ -#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ -#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ -#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ -#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ -#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ -#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ -#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ -#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ -#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ -#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ - -#define RCC_CFGR0_USBPRE ((uint32_t)0x00C00000) /* USBPRE[1:0] bits*/ -#define RCC_USBPRE_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define RCC_USBPRE_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ -#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ -#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ -#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ - -#define RCC_ADC_DUTY_CHG ((uint32_t)0x70000000) /* DUTY_CHG[2:0] bits */ -#define RCC_ADC_DUTY_CHG_0 ((uint32_t)0x10000000) -#define RCC_ADC_DUTY_CHG_1 ((uint32_t)0x20000000) -#define RCC_ADC_DUTY_CHG_2 ((uint32_t)0x40000000) - -#define RCC_ADC_PRE_ADJ ((uint32_t)0x80000000) - -/******************* Bit definition for RCC_INTR register ********************/ -#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ -#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ -#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ -#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ -#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ -#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ -#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ -#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ -#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ -#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ -#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ -#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ -#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ -#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ -#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ -#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ -#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ - -/***************** Bit definition for RCC_PB2PRSTR register *****************/ -#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ -#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ -#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ -#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ -#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ -#define RCC_ADCRST ((uint32_t)0x00000200) /* ADC interface reset */ -#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ -#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ -#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ - -/***************** Bit definition for RCC_PB1PRSTR register *****************/ -#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ -#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ -#define RCC_TIM4RST ((uint32_t)0x00000004) -#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ -#define RCC_SPI2RST ((uint32_t)0x00004000) -#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ -#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 2 reset */ -#define RCC_USART4RST ((uint32_t)0x00080000) /* USART 2 reset */ -#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ -#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 1 reset */ -#define RCC_CANRST ((uint32_t)0x02000000) /* CAN reset */ -#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ -#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ -#define RCC_LPTIMRST ((uint32_t)0x80000000) /* USB Device reset */ - -/****************** Bit definition for RCC_HBPCENR register ******************/ -#define RCC_DMAEN ((uint16_t)0x0001) /* DMA clock enable */ -#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ -#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ -#define RCC_USBFSEN ((uint16_t)0x1000) -#define RCC_USBPDEN ((uint32_t)0x00020000) - -/****************** Bit definition for RCC_PB2PCENR register *****************/ -#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ -#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ -#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ -#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ -#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ -#define RCC_ADCEN ((uint32_t)0x00000200) /* ADC interface clock enable */ -#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ -#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ -#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ - -/***************** Bit definition for RCC_PB1PCENR register ******************/ -#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ -#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ -#define RCC_TIM4EN ((uint32_t)0x00000004) -#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ -#define RCC_SPI2EN ((uint32_t)0x00004000) -#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ -#define RCC_USART3EN ((uint32_t)0x00040000) /* USART 3 clock enable */ -#define RCC_USART4EN ((uint32_t)0x00080000) /* USART 4 clock enable */ -#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ -#define RCC_I2C2EN ((uint32_t)0x00400000) /* I2C 2 clock enable */ -#define RCC_CANEN ((uint32_t)0x02000000) -#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ -#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ -#define RCC_LPTIMEN ((uint32_t)0x80000000) - -/******************* Bit definition for RCC_BDCTLR register *******************/ -#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ -#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ -#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ - -#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ -#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ - -/******************* Bit definition for RCC_RSTSCKR register ********************/ -#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ -#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ -#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ -#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ -#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ -#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ -#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ -#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ -#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ - -/******************************************************************************/ -/* Real-Time Clock */ -/******************************************************************************/ - -/******************* Bit definition for RTC_CTLRH register ********************/ -#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ -#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ -#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ - -/******************* Bit definition for RTC_CTLRL register ********************/ -#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ -#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ -#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ -#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ -#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ -#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ - -/******************* Bit definition for RTC_PSCRH register *******************/ -#define RTC_PSCRH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ - -/******************* Bit definition for RTC_PRCRL register *******************/ -#define RTC_PRCRL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ - -/******************* Bit definition for RTC_DIVH register *******************/ -#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ - -/******************* Bit definition for RTC_DIVL register *******************/ -#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ - -/******************* Bit definition for RTC_CNTH register *******************/ -#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ - -/******************* Bit definition for RTC_CNTL register *******************/ -#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ - -/******************* Bit definition for RTC_ALRMH register *******************/ -#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ - -/******************* Bit definition for RTC_ALRML register *******************/ -#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ - -/******************************************************************************/ -/* Serial Peripheral Interface */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CTLR1 register ********************/ -#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ -#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ -#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ - -#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ -#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ -#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ -#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ - -#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ -#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ -#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ -#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ -#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ -#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ -#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ -#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ -#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ -#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CTLR2 register ********************/ -#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ -#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ -#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ -#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ -#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ -#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_STATR register ********************/ -#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ -#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ -#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ -#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ -#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ -#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ - -/******************** Bit definition for SPI_DATAR register ********************/ -#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ - -/******************* Bit definition for SPI_CRCR register ******************/ -#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ - -/****************** Bit definition for SPI_RCRCR register ******************/ -#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ - -/****************** Bit definition for SPI_TCRCR register ******************/ -#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ - -/****************** Bit definition for SPI_HSCR register ******************/ -#define SPI_HSRXEN ((uint16_t)0x0001) - - -/******************************************************************************/ -/* TIM */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CTLR1 register ********************/ -#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ -#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ -#define TIM_URS ((uint16_t)0x0004) /* Update request source */ -#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ -#define TIM_DIR ((uint16_t)0x0010) /* Direction */ - -#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ - -#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ - -#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ -#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_BKSEL ((uint16_t)0x1000) -#define TIM_TMR_CAP_OV_EN ((uint16_t)0x4000) -#define TIM_TMR_CAP_LVL_EN ((uint16_t)0x8000) - -/******************* Bit definition for TIM_CTLR2 register ********************/ -#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ -#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ -#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ - -#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ -#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ -#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ -#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ -#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ -#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ -#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ -#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ -#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIM_SMCFGR register *******************/ -#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ - -#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ -#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ - -#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ -#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ - -#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ -#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ - -/******************* Bit definition for TIM_DMAINTENR register *******************/ -#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ -#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ -#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ -#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ -#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ -#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ -#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ -#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ -#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ -#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ -#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ -#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ -#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ -#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ -#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ - -/******************** Bit definition for TIM_INTFR register ********************/ -#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ -#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ -#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ -#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ -#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ -#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ -#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ -#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ -#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ -#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ -#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ -#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIM_SWEVGR register ********************/ -#define TIM_UG ((uint8_t)0x01) /* Update Generation */ -#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ -#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ -#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ -#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ -#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ -#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ -#define TIM_BG ((uint8_t)0x80) /* Break Generation */ - -/****************** Bit definition for TIM_CHCTLR1 register *******************/ -#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ -#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ - -#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ - -#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ -#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ - -#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ - -#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/****************** Bit definition for TIM_CHCTLR2 register *******************/ -#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ -#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ - -#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ - -#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ -#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ - -#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ - -#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ -#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ -#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ -#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ -#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ -#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ -#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ -#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ -#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ -#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ -#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ -#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ -#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ -#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ - -#define TIM4_CNT ((uint32_t)0xFFFFFFFF) /* Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ - -/******************* Bit definition for TIM_ATRLR register ********************/ -#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ - -/******************* Bit definition for TIM_RPTCR register ********************/ -#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ - -/******************* Bit definition for TIM_CH1CVR register *******************/ -#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ -#define TIM_LEVEL1 ((uint32_t)0x00010000) - -/******************* Bit definition for TIM_CH2CVR register *******************/ -#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ -#define TIM_LEVEL2 ((uint32_t)0x00010000) - -/******************* Bit definition for TIM_CH3CVR register *******************/ -#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ -#define TIM_LEVEL3 ((uint32_t)0x00010000) - -/******************* Bit definition for TIM_CH4CVR register *******************/ -#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ -#define TIM_LEVEL4 ((uint32_t)0x00010000) - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ -#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ -#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ -#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ - -#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ -#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ -#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ -#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ -#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ -#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ -#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ - -/******************* Bit definition for TIM_DMACFGR register ********************/ -#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ -#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ - -#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ -#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ - -/******************* Bit definition for TIM_DMAADR register *******************/ -#define TIM_DMAR_DMAB ((uint32_t)0xFFFFFFFF) /* DMA register for burst accesses */ - -/******************************************************************************/ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/******************************************************************************/ - -/******************* Bit definition for USART_STATR register *******************/ -#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ -#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ -#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ -#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ -#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ -#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ -#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ -#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ -#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ -#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ - -/******************* Bit definition for USART_DATAR register *******************/ -#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ - -/****************** Bit definition for USART_CTLR1 register *******************/ -#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ -#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ -#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ -#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ -#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ -#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ -#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ -#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ -#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ -#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ -#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ -#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ -#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ -#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ - -/****************** Bit definition for USART_CTLR2 register *******************/ -#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ -#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ -#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ -#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ -#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ -#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ -#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ - -#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ -#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ -#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ - -/****************** Bit definition for USART_CTLR3 register *******************/ -#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ -#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ -#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ -#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ -#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ -#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ -#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ -#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ -#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ -#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ -#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ - -/****************** Bit definition for USART_GPR register ******************/ -#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ -#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ -#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ -#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ -#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ -#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ -#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ -#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ -#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ - -#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ - -/******************************************************************************/ -/* Window WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CTLR register ********************/ -#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ -#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ -#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ -#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ -#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ -#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ -#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ - -#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ - -/******************* Bit definition for WWDG_CFGR register *******************/ -#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ -#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ -#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ -#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ -#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ -#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ -#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ -#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ - -#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ -#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ - -#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_STATR register ********************/ -#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ - -/******************************************************************************/ -/* ENHANCED FUNNCTION */ -/******************************************************************************/ - -/**************************** Enhanced register *****************************/ -#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ -#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ -#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ - -#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000700) /* ULLDO_TRIM[2:0] bits */ -#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ -#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ -#define EXTEN_ULLDO_TRIM2 ((uint32_t)0x00000400) /* Bit 2 */ - -#define EXTEN_LDO_TRIM ((uint32_t)0x00003000) /* LDO_TRIM[1:0] bits */ -#define EXTEN_LDO_TRIM0 ((uint32_t)0x00001000) /* Bit 0 */ -#define EXTEN_LDO_TRIM1 ((uint32_t)0x00002000) /* Bit 1 */ - -/******************************************************************************/ -/* DEBUG SUPPORT */ -/******************************************************************************/ -/******************* Bit definition for DBGMCU_DR register *******************/ -#define DBG_DEBUGMCU_SLEEP ((uint32_t)0x00000001) -#define DBG_DEBUGMCU_STOP ((uint32_t)0x00000002) -#define DBG_DEBUGMCU_STBY ((uint32_t)0x00000004) -#define DBG_DEBUGMCU_IWDG_STOP ((uint32_t)0x00000100) -#define DBG_DEBUGMCU_WWDG_STOP ((uint32_t)0x00000200) -#define DBG_DEBUGMCU_I2C1SMBUS_TOUT ((uint32_t)0x00000400) -#define DBG_DEBUGMCU_I2C2SMBUS_TOUT ((uint32_t)0x00000800) -#define DBG_DEBUGMCU_TIM1_STOP ((uint32_t)0x00001000) -#define DBG_DEBUGMCU_TIM2_STOP ((uint32_t)0x00002000) -#define DBG_DEBUGMCU_TIM3_STOP ((uint32_t)0x00004000) -#define DBG_DEBUGMCU_TIM4_STOP ((uint32_t)0x00008000) -#define DBG_DEBUGMCU_CAN_STOP ((uint32_t)0x00010000) - -/******************************************************************************/ -/* OPTICAL PARAMETER */ -/******************************************************************************/ - -/******************* Bit definition for OPA_CFGR1 register *******************/ -#define OPA_CFGR1_POLLEN ((uint32_t)0x00000001) -#define OPA_CFGR1_BKINEN ((uint32_t)0x00000004) -#define OPA_CFGR1_RSTEN ((uint32_t)0x00000010) -#define OPA_CFGR1_OPCMLOCK ((uint32_t)0x00000080) -#define OPA_CFGR1_IEOUT ((uint32_t)0x00000100) -#define OPA_CFGR1_IECNT ((uint32_t)0x00000400) -#define OPA_CFGR1_NMIEN ((uint32_t)0x00000800) -#define OPA_CFGR1_IFOUT ((uint32_t)0x00001000) -#define OPA_CFGR1_IFCNT ((uint32_t)0x00004000) - -/******************* Bit definition for OPA_CFGR2 register *******************/ -#define OPA_CFGR2_POLL_VLU ((uint32_t)0x000001FF) -#define OPA_CFGR2_POLL_NUM ((uint32_t)0x00000E00) - -/******************* Bit definition for OPA_CTLR1 register *******************/ -#define OPA_CTLR1_EN1 ((uint32_t)0x00000001) -#define OPA_CTLR1_MODE1 ((uint32_t)0x0000000E) -#define OPA_CTLR1_PSEL1 ((uint32_t)0x00000070) -#define OPA_CTLR1_FBEN1 ((uint32_t)0x00000080) -#define OPA_CTLR1_NSEL1 ((uint32_t)0x00000F00) -#define OPA_CTLR1_LP1 ((uint32_t)0x00001000) -#define OPA_CTLR1_INTRIMP ((uint32_t)0x00010000) -#define OPA_CTLR1_ITRIMP ((uint32_t)0x003E0000) -#define OPA_CTLR1_INTRIMN ((uint32_t)0x01000000) -#define OPA_CTLR1_ITRIMN ((uint32_t)0x3E000000) - -/******************* Bit definition for OPA_CTLR2 register *******************/ -#define OPA_CTLR2_EN1 ((uint32_t)0x00000001) -#define OPA_CTLR2_MODE1 ((uint32_t)0x00000006) -#define OPA_CTLR2_NSEL1 ((uint32_t)0x00000008) -#define OPA_CTLR2_PSEL1 ((uint32_t)0x00000010) -#define OPA_CTLR2_LP1 ((uint32_t)0x00000040) -#define OPA_CTLR2_EN2 ((uint32_t)0x00000100) -#define OPA_CTLR2_MODE2 ((uint32_t)0x00000600) -#define OPA_CTLR2_NSEL2 ((uint32_t)0x00000800) -#define OPA_CTLR2_PSEL2 ((uint32_t)0x00001000) -#define OPA_CTLR2_LP2 ((uint32_t)0x00004000) -#define OPA_CTLR2_EN3 ((uint32_t)0x00010000) -#define OPA_CTLR2_MODE3 ((uint32_t)0x00060000) -#define OPA_CTLR2_NSEL3 ((uint32_t)0x00080000) -#define OPA_CTLR2_PSEL3 ((uint32_t)0x00100000) -#define OPA_CTLR2_LP3 ((uint32_t)0x00400000) - -#define OPA_CTLR2_WKUP_MD ((uint32_t)0x03000000) -#define OPA_CTLR2_WKUP_MD_0 ((uint32_t)0x01000000) -#define OPA_CTLR2_WKUP_MD_1 ((uint32_t)0x02000000) - -/******************* Bit definition for OPCMKEY register *******************/ -#define OPCM_KEY ((uint32_t)0xFFFFFFFF) - -/******************************************************************************/ -/* LOW POWER TIM */ -/******************************************************************************/ -/******************* Bit definition for LPTIM_ISR register *******************/ -#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) -#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) -#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) -#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) -#define LPTIM_ISR_ARROK ((uint32_t)0000000010) -#define LPTIM_ISR_UP ((uint32_t)0x00000020) -#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) -#define LPTIM_ISR_DIRSYNC ((uint32_t)0x00000080) - -/******************* Bit definition for LPTIM_ICR register *******************/ -#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) -#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) -#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) -#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) -#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) -#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) -#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) - -/******************* Bit definition for LPTIM_IER register *******************/ -#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) -#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) -#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) -#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) -#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) -#define LPTIM_IER_UPIE ((uint32_t)0x00000020) -#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) - -/******************* Bit definition for LPTIM_CFGR register *******************/ -#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) -#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) -#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) -#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) -#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) -#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x00006000) -#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) -#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) -#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) -#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) -#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) -#define LPTIM_CFGR_CONTMODE ((uint32_t)0x00800000) -#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) -#define LPTIM_CFGR_CLKSEL ((uint32_t)0x06000000) -#define LPTIM_CFGR_FORCEPWM ((uint32_t)0x08000000) - -/******************* Bit definition for LPTIM_CR register *******************/ -#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) -#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) -#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) -#define LPTIM_CR_OUTEN ((uint32_t)0x00000008) -#define LPTIM_CR_DIR_EXTEN ((uint32_t)0x00000010) - -/******************* Bit definition for LPTIM_CMP register *******************/ -#define LPTIM_CMP ((uint32_t)0x0000FFFF) - -/******************* Bit definition for LPTIM_ARR register *******************/ -#define LPTIM_ARR ((uint32_t)0x0000FFFF) - -/******************* Bit definition for LPTIM_CNT register *******************/ -#define LPTIM_COUNT ((uint32_t)0x0000FFFF) - -/******************************************************************************/ -/* TOUCH KEY */ -/******************************************************************************/ -/******************* Bit definition for TKEY_CHARGE register *******************/ -#define TKEY_CHGOFFSET ((uint32_t)0x000003FF) - -/******************* Bit definition for TKEY_ACT_DCG register *******************/ -#define TKEY_TKACTDCG ((uint32_t)0x000003FF) - -/******************* Bit definition for TKEY_DR register *******************/ -#define TKEY_DR ((uint32_t)0x0000FFFF) - -#include "ch32l103_conf.h" - -#ifdef __cplusplus -} -#endif - -#endif - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/06 + * Description : CH32L103 Device Peripheral Access Layer Header File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_H +#define __CH32L103_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef HSE_VALUE +#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ +#endif + +/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x1000) /* Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ + +#define HSI_LP_VALUE ((uint32_t)1000000) /* Value of the Internal oscillator in Hz for low power mode */ + +/* Standard Peripheral Library version number */ +#define __CH32L103_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ +#define __CH32L103_STDPERIPH_VERSION_SUB (0x03) /* [7:0] sub version */ +#define __CH32L103_STDPERIPH_VERSION ((__CH32L103_STDPERIPH_VERSION_MAIN << 8)\ + |(__CH32L103_STDPERIPH_VERSION_SUB << 0)) + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* Non Maskable Interrupt */ + EXC_IRQn = 3, /* Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* Break Point Interrupt */ + SysTick_IRQn = 12, /* System timer Interrupt */ + Software_IRQn = 14, /* Software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + LPTIMWakeUp_IRQn = 58, /* LPTIM WakeUp Interrupt */ + USBFS_IRQn = 59, /* USBFS global Interrupt */ + USBFSWakeUp_IRQn = 60, /* USBFS WakeUp Interrupt */ + USART4_IRQn = 61, /* USART4 global Interrupt */ + DMA1_Channel8_IRQn = 62, /* DMA1 Channel 8 global Interrupt */ + LPTIM_IRQn = 63, /* LPTIM global Interrupt */ + OPA_IRQn = 64, /* OPA global Interrupt */ + USBPD_IRQn = 65, /* USBPD global Interrupt */ + + USBPDWakeUp_IRQn = 67, /* USBPD WakeUp Interrupt */ + CMPWakeUp_IRQn = 68, /* CMP WakeUp Interrupt */ + +} IRQn_Type; + +#define HardFault_IRQn EXC_IRQn +#define ADC1_2_IRQn ADC_IRQn +#define SysTicK_IRQn SysTick_IRQn + +#include +#include "core_riscv.h" +#include "system_ch32l103.h" + +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + __IO uint32_t CFG; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13; +} BKP_TypeDef; + +/* Controller Area Network TxMailBox */ +typedef struct +{ + __IO uint32_t TXMIR; + __IO uint32_t TXMDTR; + __IO uint32_t TXMDLR; + __IO uint32_t TXMDHR; +} CAN_TxMailBox_TypeDef; + +/* Controller Area Network FIFOMailBox */ +typedef struct +{ + __IO uint32_t RXMIR; + __IO uint32_t RXMDTR; + __IO uint32_t RXMDLR; + __IO uint32_t RXMDHR; +} CAN_FIFOMailBox_TypeDef; + +/* Controller Area Network FilterRegister */ +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/* Controller Area Network */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t STATR; + __IO uint32_t TSTATR; + __IO uint32_t RFIFO0; + __IO uint32_t RFIFO1; + __IO uint32_t INTENR; + __IO uint32_t ERRSR; + __IO uint32_t BTIMR; + __IO uint32_t TTCTLR; + __IO uint32_t TTCNT; + __IO uint32_t TERR_CNT; + __IO uint32_t CANFD_CR; + __IO uint32_t CANFD_BTR; + __IO uint32_t CANFD_TDCT; + __IO uint32_t CANFD_PSR; + __IO uint32_t CANFD_DMA_T[3]; + __IO uint32_t CANFD_DMA_R[2]; + uint32_t RESERVED0[76]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FCTLR; + __IO uint32_t FMCFGR; + uint32_t RESERVED2; + __IO uint32_t FSCFGR; + uint32_t RESERVED3; + __IO uint32_t FAFIFOR; + uint32_t RESERVED4; + __IO uint32_t FWR; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + +/* DMA Channel Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + __IO uint32_t CR; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t PB2PRSTR; + __IO uint32_t PB1PRSTR; + __IO uint32_t HBPCENR; + __IO uint32_t PB2PCENR; + __IO uint32_t PB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; + __IO uint32_t HBRSTR; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + union + { + __IO uint32_t CNT_TIM4; + struct + { + __IO uint16_t CNT; + uint16_t RESERVED9; + }; + }; + __IO uint16_t PSC; + uint16_t RESERVED10; + union + { + __IO uint32_t ATRLR_TIM4; + struct + { + __IO uint16_t ATRLR; + uint16_t RESERVED11; + }; + }; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + union + { + __IO uint32_t CH1CVR_TIM4; + + __IO uint32_t CH1CVR; + }; + union + { + __IO uint32_t CH2CVR_TIM4; + + __IO uint32_t CH2CVR; + }; + union + { + __IO uint32_t CH3CVR_TIM4; + + __IO uint32_t CH3CVR; + }; + union + { + __IO uint32_t CH4CVR_TIM4; + + __IO uint32_t CH4CVR; + }; + __IO uint16_t BDTR; + uint16_t RESERVED13; + __IO uint16_t DMACFGR; + uint16_t RESERVED14; + __IO uint32_t DMAADR; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* OPA Registers */ +typedef struct +{ + __IO uint16_t CFGR1; + __IO uint16_t CFGR2; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t RESERVED0; + __IO uint32_t RESERVED1; + __IO uint32_t OPCMKEY; +} OPA_TypeDef; + +/* LPTIM Registers */ +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t CFGR; + __IO uint32_t CR; + __IO uint16_t CMP; + uint16_t RESERVED0; + __IO uint16_t ARR; + uint16_t RESERVED1; + __IO uint16_t CNT; + uint16_t RESERVED2; +} LPTIM_TypeDef; + +/* PD Registers */ +typedef struct +{ + union + { + __IO uint32_t USBPD_CONFIG; + struct + { + __IO uint16_t CONFIG; + __IO uint16_t BMC_CLK_CNT; + }; + }; + union + { + __IO uint32_t USBPD_CONTROL; + struct + { + union + { + __IO uint16_t R16_CONTROL; + struct + { + __IO uint8_t CONTROL; + __IO uint8_t TX_SEL; + }; + }; + __IO uint16_t BMC_TX_SZ; + }; + }; + union + { + __IO uint32_t USBPD_STATUS; + struct + { + union + { + __IO uint16_t R16_STATUS; + struct + { + __IO uint8_t DATA_BUF; + __IO uint8_t STATUS; + }; + }; + __IO uint16_t BMC_BYTE_CNT; + }; + }; + union + { + __IO uint32_t USBPD_PORT; + struct + { + __IO uint16_t PORT_CC1; + __IO uint16_t PORT_CC2; + }; + }; + union + { + __IO uint32_t USBPD_DMA; + struct + { + __IO uint16_t DMA; + __IO uint16_t RESERVED; + }; + }; +} USBPD_TypeDef; + +/* USBFS Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint32_t RX_LEN; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint16_t UEP0_TX_LEN; + union{ + __IO uint16_t UEP0_CTRL; + struct{ + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + }; + }; + __IO uint16_t UEP1_TX_LEN; + union{ + __IO uint16_t UEP1_CTRL; + struct{ + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + }; + }; + __IO uint16_t UEP2_TX_LEN; + union{ + __IO uint16_t UEP2_CTRL; + struct{ + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + }; + }; + __IO uint16_t UEP3_TX_LEN; + union{ + __IO uint16_t UEP3_CTRL; + struct{ + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + }; + }; + __IO uint16_t UEP4_TX_LEN; + union{ + __IO uint16_t UEP4_CTRL; + struct{ + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + }; + }; + __IO uint16_t UEP5_TX_LEN; + union{ + __IO uint16_t UEP5_CTRL; + struct{ + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + }; + }; + __IO uint16_t UEP6_TX_LEN; + union{ + __IO uint16_t UEP6_CTRL; + struct{ + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + }; + }; + __IO uint16_t UEP7_TX_LEN; + union{ + __IO uint16_t UEP7_CTRL; + struct{ + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + }; + }; + __IO uint32_t Reserve1; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBFSD_TypeDef; + +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t Reserve2; + __IO uint8_t HOST_EP_MOD; + __IO uint16_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t Reserve6; + __IO uint32_t Reserve7; + __IO uint32_t Reserve8; + __IO uint32_t Reserve9; + __IO uint32_t Reserve10; + __IO uint16_t Reserve11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + __IO uint8_t Reserve12; + __IO uint8_t Reserve13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t Reserve14; + __IO uint32_t Reserve15; + __IO uint32_t Reserve16; + __IO uint32_t Reserve17; + __IO uint32_t Reserve18; + __IO uint32_t Reserve19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBFSH_TypeDef; + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define PB1PERIPH_BASE (PERIPH_BASE) +#define PB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define HBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (PB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (PB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (PB1PERIPH_BASE + 0x0800) +#define RTC_BASE (PB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (PB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (PB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (PB1PERIPH_BASE + 0x3800) +#define USART2_BASE (PB1PERIPH_BASE + 0x4400) +#define USART3_BASE (PB1PERIPH_BASE + 0x4800) +#define USART4_BASE (PB1PERIPH_BASE + 0x4C00) +#define I2C1_BASE (PB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (PB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (PB1PERIPH_BASE + 0x6400) +#define BKP_BASE (PB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (PB1PERIPH_BASE + 0x7000) +#define LPTIM_BASE (PB1PERIPH_BASE + 0x7C00) + +#define AFIO_BASE (PB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (PB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (PB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (PB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (PB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (PB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (PB2PERIPH_BASE + 0x2400) +#define TIM1_BASE (PB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (PB2PERIPH_BASE + 0x3000) +#define USART1_BASE (PB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (HBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (HBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (HBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (HBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (HBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (HBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (HBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (HBPERIPH_BASE + 0x0080) +#define DMA1_Channel8_BASE (HBPERIPH_BASE + 0x0094) +#define RCC_BASE (HBPERIPH_BASE + 0x1000) +#define FLASH_R_BASE (HBPERIPH_BASE + 0x2000) +#define CRC_BASE (HBPERIPH_BASE + 0x3000) +#define EXTEN_BASE (HBPERIPH_BASE + 0x3800) +#define OPA_BASE (HBPERIPH_BASE + 0x6000) +#define USBPD_BASE (HBPERIPH_BASE + 0x7000) + +#define USBFS_BASE ((uint32_t)0x50000000) + +#define OB_BASE ((uint32_t)0x1FFFF800) + +#define TS_BASE ((uint32_t)0x1FFFF720) +#define OPA_TRIM_BASE ((uint32_t)0x1FFFF724) +#define ADC_TRIM_BASE ((uint32_t)0x1FFFF728) +#define HSI_LP_TRIM_BASE ((uint32_t)0x1FFFF72A) +#define CHIPID_BASE ((uint32_t)0x1FFFF704) +#define USBPD_CFG_BASE ((uint32_t)0x1FFFF730) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define USART4 ((USART_TypeDef *)USART4_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define LPTIM ((LPTIM_TypeDef *)LPTIM_BASE) + +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define TKey1 ((ADC_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) + +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE) +#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) +#define OPA ((OPA_TypeDef *)OPA_BASE) +#define USBPD ((USBPD_TypeDef *)USBPD_BASE) + +#define OB ((OB_TypeDef *)OB_BASE) + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ +#define ADC_RDISCEN ADC_DISCEN + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +#define ADC_TKENABLE ((uint32_t)0x01000000) +#define ADC_TK1TUNE ((uint32_t)0x02000000) +#define ADC_BUFEN ((uint32_t)0x04000000) + +#define ADC_PGA ((uint32_t)0x18000000) /* PGA[1:0] bits */ +#define ADC_PGA_0 ((uint32_t)0x08000000) +#define ADC_PGA_1 ((uint32_t)0x10000000) + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_RSWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP18 ((uint32_t)0x07000000) /* SMP18[2:0] bits (Channel 18 Sample time selection) */ +#define ADC_SMP18_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP18_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP18_2 ((uint32_t)0x04000000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +/******************** Bit definition for ADC_CFG register ********************/ +#define ADC_BUFTRIM ((uint32_t)0x0000000F) /* BUFTRIM[3:0] bits */ +#define ADC_BUFTRIM_0 ((uint32_t)0x00000001) +#define ADC_BUFTRIM_1 ((uint32_t)0x00000002) +#define ADC_BUFTRIM_2 ((uint32_t)0x00000004) +#define ADC_BUFTRIM_3 ((uint32_t)0x00000008) + +#define ADC_AWDRST_EN ((uint32_t)0x00000010) +#define ADC_LP ((uint32_t)0x00000020) +#define ADC_FIFO_EN ((uint32_t)0x00000040) +#define ADC_DUTY_EN ((uint32_t)0x00000080) +#define ADC_TKEY_DRV_EN ((uint32_t)0x00000100) + +#define ADC_TKEY_DRV_OUTEN ((uint32_t)0x0007FE00) /* TKEY_DRV_OUTEN[9:0] bits */ +#define ADC_TKEY_DRV_OUTEN_0 ((uint32_t)0x00000200) +#define ADC_TKEY_DRV_OUTEN_1 ((uint32_t)0x00000400) +#define ADC_TKEY_DRV_OUTEN_2 ((uint32_t)0x00000800) +#define ADC_TKEY_DRV_OUTEN_3 ((uint32_t)0x00001000) +#define ADC_TKEY_DRV_OUTEN_4 ((uint32_t)0x00002000) +#define ADC_TKEY_DRV_OUTEN_5 ((uint32_t)0x00004000) +#define ADC_TKEY_DRV_OUTEN_6 ((uint32_t)0x00008000) +#define ADC_TKEY_DRV_OUTEN_7 ((uint32_t)0x00010000) +#define ADC_TKEY_DRV_OUTEN_8 ((uint32_t)0x00020000) +#define ADC_TKEY_DRV_OUTEN_9 ((uint32_t)0x00040000) + +#define ADC_TKEY_SEL ((uint32_t)0x00180000) /* TKEY_SEL[1:0] bits */ +#define ADC_TKEY_SEL_0 ((uint32_t)0x00080000) +#define ADC_TKEY_SEL_1 ((uint32_t)0x00080000) + +#define ADC_TKEY_WAKE_EN ((uint32_t)0x8FE00000) /* TKEY_WAKE_EN[9:0] bits */ +#define ADC_TKEY_WAKE_EN_0 ((uint32_t)0x00200000) +#define ADC_TKEY_WAKE_EN_1 ((uint32_t)0x00400000) +#define ADC_TKEY_WAKE_EN_2 ((uint32_t)0x00800000) +#define ADC_TKEY_WAKE_EN_3 ((uint32_t)0x01000000) +#define ADC_TKEY_WAKE_EN_4 ((uint32_t)0x02000000) +#define ADC_TKEY_WAKE_EN_5 ((uint32_t)0x04000000) +#define ADC_TKEY_WAKE_EN_6 ((uint32_t)0x08000000) +#define ADC_TKEY_WAKE_EN_7 ((uint32_t)0x10000000) +#define ADC_TKEY_WAKE_EN_8 ((uint32_t)0x20000000) +#define ADC_TKEY_WAKE_EN_9 ((uint32_t)0x40000000) + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* Controller Area Network */ +/******************************************************************************/ + +/******************* Bit definition for CAN_CTLR register ********************/ +#define CAN_CTLR_INRQ ((uint32_t)0x00000001) /* Initialization Request */ +#define CAN_CTLR_SLEEP ((uint32_t)0x00000002) /* Sleep Mode Request */ +#define CAN_CTLR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO Priority */ +#define CAN_CTLR_RFLM ((uint32_t)0x00000008) /* Receive FIFO Locked Mode */ +#define CAN_CTLR_NART ((uint32_t)0x00000010) /* No Automatic Retransmission */ +#define CAN_CTLR_AWUM ((uint32_t)0x00000020) /* Automatic Wakeup Mode */ +#define CAN_CTLR_ABOM ((uint32_t)0x00000040) /* Automatic Bus-Off Management */ +#define CAN_CTLR_TTCM ((uint32_t)0x00000080) /* Time Triggered Communication Mode */ +#define CAN_CTLR_RESET ((uint32_t)0x00008000) /* CAN software master reset */ +#define CAN_CTLR_DBF ((uint32_t)0x00010000) /* CAN controller operating state selection during debugging */ + +/******************* Bit definition for CAN_STATR register ********************/ +#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ +#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ +#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ +#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ +#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ +#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ +#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ +#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTATR register ********************/ +#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ + +#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFIFO0 register *******************/ +#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ +#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ +#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ +#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFIFO1 register *******************/ +#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ +#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ +#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ +#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTENR register *******************/ +#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ +#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ERRSR register *******************/ +#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ +#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ +#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ + +#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ + +#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ + +/******************* Bit definition for CAN_BTIMR register ********************/ +#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) /* Baud Rate Prescaler */ +#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) /* Time Segment 1 */ +#define CAN_BTIMR_TS2 ((uint32_t)0x00700000) /* Time Segment 2 */ +#define CAN_BTIMR_SJW ((uint32_t)0x03000000) /* Resynchronization Jump Width */ +#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */ +#define CAN_BTIMR_SILM ((uint32_t)0x80000000) /* Silent Mode */ + +/******************** Bit definition for CAN_TTCTLR register *******************/ +#define CAN_TTCTLR_TIMCMV ((uint32_t)0x0000FFFF) +#define CAN_TTCTLR_TIMRST ((uint32_t)0x00010000) +#define CAN_TTCTLR_MODE ((uint32_t)0x00020000) + +/******************** Bit definition for CAN_TTCNT register *******************/ +#define CAN_TTCNT ((uint32_t)0x0000FFFF) + +/******************** Bit definition for CAN_TERR_CNT register *******************/ +#define CAN_TERR_CNT ((uint32_t)0x000001FF) + +/******************** Bit definition for CANFD_CR register *******************/ +#define CANFD_CR_TX_FD ((uint32_t)0x00000001) +#define CANFD_CR_TX_BRS_B ((uint32_t)0x0000000E) +#define CANFD_CR_USER_ESI_B ((uint32_t)0x00000070) +#define CANFD_CR_RES_EXCEPT ((uint32_t)0x00000080) +#define CANFD_CR_CLAS_LONG_TS1 ((uint32_t)0x00000100) +#define CANFD_CR_RESTRICT_MODE ((uint32_t)0x00000200) + +/******************** Bit definition for CANFD_BTR register *******************/ +#define CANFD_BTR_BTR_SJW_FD ((uint32_t)0x0000000F) +#define CANFD_BTR_BTR_TS2_FD ((uint32_t)0x000000F0) +#define CANFD_BTR_BTR_TS1_FD ((uint32_t)0x00001F00) +#define CANFD_BTR_BTR_BRP_FD ((uint32_t)0x001F0000) +#define CANFD_BTR_BTR_TDCE ((uint32_t)0x00800000) + +/******************** Bit definition for CANFD_TDCT register *******************/ +#define CANFD_TDCT_TDCO ((uint32_t)0x0000003F) +#define CANFD_TDCT_TDC_FILTER ((uint32_t)0x00003F00) + +/******************** Bit definition for CANFD_PSR register *******************/ +#define CANFD_PSR_TDCV ((uint32_t)0x00FF0000) + +/******************** Bit definition for CAN_DMA_T0 register *******************/ +#define CANFD_DMA_T0 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_T1 register *******************/ +#define CANFD_DMA_T1 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_T2 register *******************/ +#define CANFD_DMA_T2 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_R0 register *******************/ +#define CANFD_DMA_R0 ((uint32_t)0x00007FFF) + +/******************** Bit definition for CAN_DMA_R1 register *******************/ +#define CANFD_DMA_R1 ((uint32_t)0x00007FFF) + +/****************** Bit definition for CAN_TXMI0R register ********************/ +#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TXMDT0R register *******************/ +#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/****************** Bit definition for CAN_TXMDL0R register *******************/ +#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/****************** Bit definition for CAN_TXMDH0R register *******************/ +#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI1R register *******************/ +#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT1R register ******************/ +#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL1R register ******************/ +#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH1R register ******************/ +#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI2R register *******************/ +#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT2R register ******************/ +#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL2R register ******************/ +#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH2R register ******************/ +#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI0R register *******************/ +#define CAN_RXMIOR_FDF ((uint32_t)0x00000001) +#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT0R register ******************/ +#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT0R_BRS ((uint32_t)0x00000010) +#define CAN_RXMDT0R_ESI ((uint32_t)0x00000020) +#define CAN_RXMDH0R_RES ((uint32_t)0x00000100) +#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL0R register ******************/ +#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH0R register ******************/ +#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI1R register *******************/ +#define CAN_RXMI1R_FDF ((uint32_t)0x00000001) +#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT1R register ******************/ +#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT1R_BRS ((uint32_t)0x00000010) +#define CAN_RXMDT1R_ESI ((uint32_t)0x00000020) +#define CAN_RXMDH1R_RES ((uint32_t)0x00000100) +#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL1R register ******************/ +#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH1R register ******************/ +#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_FCTLR register ********************/ +#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ + +/******************* Bit definition for CAN_FMCFGR register *******************/ +#define CAN_FMCFGR_FBM ((uint32_t)0x00003FFF) /* Filter Mode */ +#define CAN_FMCFGR_FBM0 ((uint32_t)0x00000001) /* Filter Init Mode bit 0 */ +#define CAN_FMCFGR_FBM1 ((uint32_t)0x00000002) /* Filter Init Mode bit 1 */ +#define CAN_FMCFGR_FBM2 ((uint32_t)0x00000004) /* Filter Init Mode bit 2 */ +#define CAN_FMCFGR_FBM3 ((uint32_t)0x00000008) /* Filter Init Mode bit 3 */ +#define CAN_FMCFGR_FBM4 ((uint32_t)0x00000010) /* Filter Init Mode bit 4 */ +#define CAN_FMCFGR_FBM5 ((uint32_t)0x00000020) /* Filter Init Mode bit 5 */ +#define CAN_FMCFGR_FBM6 ((uint32_t)0x00000040) /* Filter Init Mode bit 6 */ +#define CAN_FMCFGR_FBM7 ((uint32_t)0x00000080) /* Filter Init Mode bit 7 */ +#define CAN_FMCFGR_FBM8 ((uint32_t)0x00000100) /* Filter Init Mode bit 8 */ +#define CAN_FMCFGR_FBM9 ((uint32_t)0x00000200) /* Filter Init Mode bit 9 */ +#define CAN_FMCFGR_FBM10 ((uint32_t)0x00000400) /* Filter Init Mode bit 10 */ +#define CAN_FMCFGR_FBM11 ((uint32_t)0x00000800) /* Filter Init Mode bit 11 */ +#define CAN_FMCFGR_FBM12 ((uint32_t)0x00001000) /* Filter Init Mode bit 12 */ +#define CAN_FMCFGR_FBM13 ((uint32_t)0x00002000) /* Filter Init Mode bit 13 */ +#define CAN_FMCFGR_FBM14 ((uint32_t)0x00004000) /* Filter Init Mode bit 14 */ +#define CAN_FMCFGR_FBM15 ((uint32_t)0x00008000) /* Filter Init Mode bit 15 */ +#define CAN_FMCFGR_FBM16 ((uint32_t)0x00010000) /* Filter Init Mode bit 16 */ +#define CAN_FMCFGR_FBM17 ((uint32_t)0x00020000) /* Filter Init Mode bit 17 */ +#define CAN_FMCFGR_FBM18 ((uint32_t)0x00040000) /* Filter Init Mode bit 18 */ +#define CAN_FMCFGR_FBM19 ((uint32_t)0x00080000) /* Filter Init Mode bit 19 */ +#define CAN_FMCFGR_FBM20 ((uint32_t)0x00100000) /* Filter Init Mode bit 20 */ +#define CAN_FMCFGR_FBM21 ((uint32_t)0x00200000) /* Filter Init Mode bit 21 */ +#define CAN_FMCFGR_FBM22 ((uint32_t)0x00400000) /* Filter Init Mode bit 22 */ +#define CAN_FMCFGR_FBM23 ((uint32_t)0x00800000) /* Filter Init Mode bit 23 */ +#define CAN_FMCFGR_FBM24 ((uint32_t)0x01000000) /* Filter Init Mode bit 24 */ +#define CAN_FMCFGR_FBM25 ((uint32_t)0x02000000) /* Filter Init Mode bit 25 */ +#define CAN_FMCFGR_FBM26 ((uint32_t)0x04000000) /* Filter Init Mode bit 26 */ +#define CAN_FMCFGR_FBM27 ((uint32_t)0x08000000) /* Filter Init Mode bit 27 */ + +/******************* Bit definition for CAN_FSCFGR register *******************/ +#define CAN_FSCFGR_FSC ((uint32_t)0x00003FFF) /* Filter Scale Configuration */ +#define CAN_FSCFGR_FSC0 ((uint32_t)0x00000001) /* Filter Scale Configuration bit 0 */ +#define CAN_FSCFGR_FSC1 ((uint32_t)0x00000002) /* Filter Scale Configuration bit 1 */ +#define CAN_FSCFGR_FSC2 ((uint32_t)0x00000004) /* Filter Scale Configuration bit 2 */ +#define CAN_FSCFGR_FSC3 ((uint32_t)0x00000008) /* Filter Scale Configuration bit 3 */ +#define CAN_FSCFGR_FSC4 ((uint32_t)0x00000010) /* Filter Scale Configuration bit 4 */ +#define CAN_FSCFGR_FSC5 ((uint32_t)0x00000020) /* Filter Scale Configuration bit 5 */ +#define CAN_FSCFGR_FSC6 ((uint32_t)0x00000040) /* Filter Scale Configuration bit 6 */ +#define CAN_FSCFGR_FSC7 ((uint32_t)0x00000080) /* Filter Scale Configuration bit 7 */ +#define CAN_FSCFGR_FSC8 ((uint32_t)0x00000100) /* Filter Scale Configuration bit 8 */ +#define CAN_FSCFGR_FSC9 ((uint32_t)0x00000200) /* Filter Scale Configuration bit 9 */ +#define CAN_FSCFGR_FSC10 ((uint32_t)0x00000400) /* Filter Scale Configuration bit 10 */ +#define CAN_FSCFGR_FSC11 ((uint32_t)0x00000800) /* Filter Scale Configuration bit 11 */ +#define CAN_FSCFGR_FSC12 ((uint32_t)0x00001000) /* Filter Scale Configuration bit 12 */ +#define CAN_FSCFGR_FSC13 ((uint32_t)0x00002000) /* Filter Scale Configuration bit 13 */ +#define CAN_FSCFGR_FSC14 ((uint32_t)0x00004000) /* Filter Scale Configuration bit 14 */ +#define CAN_FSCFGR_FSC15 ((uint32_t)0x00008000) /* Filter Scale Configuration bit 15 */ +#define CAN_FSCFGR_FSC16 ((uint32_t)0x00010000) /* Filter Scale Configuration bit 16 */ +#define CAN_FSCFGR_FSC17 ((uint32_t)0x00020000) /* Filter Scale Configuration bit 17 */ +#define CAN_FSCFGR_FSC18 ((uint32_t)0x00040000) /* Filter Scale Configuration bit 18 */ +#define CAN_FSCFGR_FSC19 ((uint32_t)0x00080000) /* Filter Scale Configuration bit 19 */ +#define CAN_FSCFGR_FSC20 ((uint32_t)0x00100000) /* Filter Scale Configuration bit 20 */ +#define CAN_FSCFGR_FSC21 ((uint32_t)0x00200000) /* Filter Scale Configuration bit 21 */ +#define CAN_FSCFGR_FSC22 ((uint32_t)0x00400000) /* Filter Scale Configuration bit 22 */ +#define CAN_FSCFGR_FSC23 ((uint32_t)0x00800000) /* Filter Scale Configuration bit 23 */ +#define CAN_FSCFGR_FSC24 ((uint32_t)0x01000000) /* Filter Scale Configuration bit 24 */ +#define CAN_FSCFGR_FSC25 ((uint32_t)0x02000000) /* Filter Scale Configuration bit 25 */ +#define CAN_FSCFGR_FSC26 ((uint32_t)0x04000000) /* Filter Scale Configuration bit 26 */ +#define CAN_FSCFGR_FSC27 ((uint32_t)0x08000000) /* Filter Scale Configuration bit 27 */ + +/****************** Bit definition for CAN_FAFIFOR register *******************/ +#define CAN_FAFIFOR_FFA ((uint32_t)0x00003FFF) /* Filter FIFO Assignment */ +#define CAN_FAFIFOR_FFA0 ((uint32_t)0x00000001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FAFIFOR_FFA1 ((uint32_t)0x00000002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FAFIFOR_FFA2 ((uint32_t)0x00000004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FAFIFOR_FFA3 ((uint32_t)0x00000008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FAFIFOR_FFA4 ((uint32_t)0x00000010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FAFIFOR_FFA5 ((uint32_t)0x00000020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FAFIFOR_FFA6 ((uint32_t)0x00000040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FAFIFOR_FFA7 ((uint32_t)0x00000080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FAFIFOR_FFA8 ((uint32_t)0x00000100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FAFIFOR_FFA9 ((uint32_t)0x00000200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FAFIFOR_FFA10 ((uint32_t)0x00000400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FAFIFOR_FFA11 ((uint32_t)0x00000800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FAFIFOR_FFA12 ((uint32_t)0x00001000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FAFIFOR_FFA13 ((uint32_t)0x00002000) /* Filter FIFO Assignment for Filter 13 */ +#define CAN_FAFIFOR_FFA14 ((uint32_t)0x00004000) /* Filter FIFO Assignment for Filter 14 */ +#define CAN_FAFIFOR_FFA15 ((uint32_t)0x00008000) /* Filter FIFO Assignment for Filter 15 */ +#define CAN_FAFIFOR_FFA16 ((uint32_t)0x00010000) /* Filter FIFO Assignment for Filter 16 */ +#define CAN_FAFIFOR_FFA17 ((uint32_t)0x00020000) /* Filter FIFO Assignment for Filter 17 */ +#define CAN_FAFIFOR_FFA18 ((uint32_t)0x00040000) /* Filter FIFO Assignment for Filter 18 */ +#define CAN_FAFIFOR_FFA19 ((uint32_t)0x00080000) /* Filter FIFO Assignment for Filter 19 */ +#define CAN_FAFIFOR_FFA20 ((uint32_t)0x00100000) /* Filter FIFO Assignment for Filter 20 */ +#define CAN_FAFIFOR_FFA21 ((uint32_t)0x00200000) /* Filter FIFO Assignment for Filter 21 */ +#define CAN_FAFIFOR_FFA22 ((uint32_t)0x00400000) /* Filter FIFO Assignment for Filter 22 */ +#define CAN_FAFIFOR_FFA23 ((uint32_t)0x00800000) /* Filter FIFO Assignment for Filter 23 */ +#define CAN_FAFIFOR_FFA24 ((uint32_t)0x01000000) /* Filter FIFO Assignment for Filter 24 */ +#define CAN_FAFIFOR_FFA25 ((uint32_t)0x02000000) /* Filter FIFO Assignment for Filter 25 */ +#define CAN_FAFIFOR_FFA26 ((uint32_t)0x04000000) /* Filter FIFO Assignment for Filter 26 */ +#define CAN_FAFIFOR_FFA27 ((uint32_t)0x08000000) /* Filter FIFO Assignment for Filter 27 */ + +/******************* Bit definition for CAN_FWR register *******************/ +#define CAN_FWR_FACT ((uint32_t)0x00003FFF) /* Filter Active */ +#define CAN_FWR_FACT0 ((uint32_t)0x00000001) /* Filter 0 Active */ +#define CAN_FWR_FACT1 ((uint32_t)0x00000002) /* Filter 1 Active */ +#define CAN_FWR_FACT2 ((uint32_t)0x00000004) /* Filter 2 Active */ +#define CAN_FWR_FACT3 ((uint32_t)0x00000008) /* Filter 3 Active */ +#define CAN_FWR_FACT4 ((uint32_t)0x00000010) /* Filter 4 Active */ +#define CAN_FWR_FACT5 ((uint32_t)0x00000020) /* Filter 5 Active */ +#define CAN_FWR_FACT6 ((uint32_t)0x00000040) /* Filter 6 Active */ +#define CAN_FWR_FACT7 ((uint32_t)0x00000080) /* Filter 7 Active */ +#define CAN_FWR_FACT8 ((uint32_t)0x00000100) /* Filter 8 Active */ +#define CAN_FWR_FACT9 ((uint32_t)0x00000200) /* Filter 9 Active */ +#define CAN_FWR_FACT10 ((uint32_t)0x00000400) /* Filter 10 Active */ +#define CAN_FWR_FACT11 ((uint32_t)0x00000800) /* Filter 11 Active */ +#define CAN_FWR_FACT12 ((uint32_t)0x00001000) /* Filter 12 Active */ +#define CAN_FWR_FACT13 ((uint32_t)0x00002000) /* Filter 13 Active */ +#define CAN_FWR_FACT14 ((uint32_t)0x00004000) /* Filter 14 Active */ +#define CAN_FWR_FACT15 ((uint32_t)0x00008000) /* Filter 15 Active */ +#define CAN_FWR_FACT16 ((uint32_t)0x00010000) /* Filter 16 Active */ +#define CAN_FWR_FACT17 ((uint32_t)0x00020000) /* Filter 17 Active */ +#define CAN_FWR_FACT18 ((uint32_t)0x00040000) /* Filter 18 Active */ +#define CAN_FWR_FACT19 ((uint32_t)0x00080000) /* Filter 19 Active */ +#define CAN_FWR_FACT20 ((uint32_t)0x00100000) /* Filter 20 Active */ +#define CAN_FWR_FACT21 ((uint32_t)0x00200000) /* Filter 21 Active */ +#define CAN_FWR_FACT22 ((uint32_t)0x00400000) /* Filter 22 Active */ +#define CAN_FWR_FACT23 ((uint32_t)0x00800000) /* Filter 23 Active */ +#define CAN_FWR_FACT24 ((uint32_t)0x01000000) /* Filter 24 Active */ +#define CAN_FWR_FACT25 ((uint32_t)0x02000000) /* Filter 25 Active */ +#define CAN_FWR_FACT26 ((uint32_t)0x04000000) /* Filter 26 Active */ +#define CAN_FWR_FACT27 ((uint32_t)0x08000000) /* Filter 27 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ +#define DMA_GIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ +#define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */ +#define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */ +#define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */ +#define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR8 register ******************/ +#define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR8 register *******************/ +#define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR8 register *******************/ +#define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ +#define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */ +#define EXTI_INTENR_MR21 ((uint32_t)0x00200000) /* Interrupt Mask on line 21 */ +#define EXTI_INTENR_MR22 ((uint32_t)0x00400000) /* Interrupt Mask on line 22 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ +#define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */ +#define EXTI_EVENR_MR21 ((uint32_t)0x00200000) /* Event Mask on line 21 */ +#define EXTI_EVENR_MR22 ((uint32_t)0x00400000) /* Event Mask on line 22 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ +#define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */ +#define EXTI_RTENR_TR21 ((uint32_t)0x00200000) /* Rising trigger event configuration bit of line 21 */ +#define EXTI_RTENR_TR22 ((uint32_t)0x00400000) /* Rising trigger event configuration bit of line 22 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ +#define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */ +#define EXTI_FTENR_TR21 ((uint32_t)0x00200000) /* Falling trigger event configuration bit of line 21 */ +#define EXTI_FTENR_TR22 ((uint32_t)0x00400000) /* Falling trigger event configuration bit of line 22 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ +#define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */ +#define EXTI_SWIEVR_SWIEVR21 ((uint32_t)0x00200000) /* Software Interrupt on line 21 */ +#define EXTI_SWIEVR_SWIEVR22 ((uint32_t)0x00400000) /* Software Interrupt on line 22 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ +#define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */ +#define EXTI_INTF_INTF21 ((uint32_t)0x00200000) /* Pending bit for line 21 */ +#define EXTI_INTF_INTF22 ((uint32_t)0x00400000) /* Pending bit for line 22 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[1:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_FWAKE_FLAG ((uint8_t)0x40) +#define FLASH_STATR_TURBO ((uint8_t)0x80) + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 1K */ +#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ +#define FLASH_CTLR_OBPG ((uint32_t)0x00000010) /* Option Byte Programming */ +#define FLASH_CTLR_OBER ((uint32_t)0x00000020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ +#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ +#define FLASH_CTLR_OBWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FWAKEIE ((uint32_t)0x00002000) +#define FLASH_CTLR_FLOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_FTPG ((uint32_t)0x00010000) /* Page Programming 256Byte */ +#define FLASH_CTLR_FTER ((uint32_t)0x00020000) /* Page Erase 256Byte */ +#define FLASH_CTLR_BUFLOAD ((uint32_t)0x00040000) +#define FLASH_CTLR_BUFRST ((uint32_t)0x00080000) +#define FLASH_CTLR_BER32 ((uint32_t)0x00800000) /* Block Erase 32K */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OBERR ((uint32_t)0x00000001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /* Read protection */ + +#define FLASH_OBR_USER ((uint32_t)0x000000FC) /* User Option Bytes */ +#define FLASH_OBR_iWDG_SW ((uint32_t)0x00000004) /* WDG_SW */ +#define FLASH_OBR_STOP_nRST ((uint32_t)0x00000008) /* nRST_STOP */ +#define FLASH_OBR_STANDY_nRST ((uint32_t)0x00000010) /* nRST_STDBY */ +#define FLASH_OBR_CFGCANM ((uint32_t)0x00000080) + +#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) /* DATA0 */ +#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) /* DATA1 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_OBR_MODEKEYR register ******************/ +#define FLASH_OBR_MODEKEYR ((uint32_t)0xFFFFFFFF) + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_RM ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_RM ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_RM ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART2_RM ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_RM ((uint32_t)0x00000030) /* USART3_RM[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_RM_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_RM_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_RM ((uint32_t)0x000000C0) /* TIM1_RM[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_RM_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_RM_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_RM ((uint32_t)0x00000300) /* TIM2_RM[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_RM_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_RM_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_RM ((uint32_t)0x00000400) /* TIM3_RM bits (TIM3 remapping) */ + +#define AFIO_PCFR1_TIM4_RM ((uint32_t)0x00001000) /* TIM4_RM bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_RM ((uint32_t)0x00006000) /* CAN_RM[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_RM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_RM_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_PD0PD1_RM ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_PD01_RM AFIO_PCFR1_PD0PD1_RM + +#define AFIO_PCFR1_SW_CFG ((uint32_t)0x07000000) /* SW_CFG[2:0] bits (SDI configuration) */ +#define AFIO_PCFR1_SW_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SW_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SW_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ + +/***************** Bit definition for AFIO_CR register *****************/ +#define AFIO_CR_USBPD_IN_HVT ((uint32_t)0x00000200) +#define AFIO_CR_UPD_BC_VSRC ((uint32_t)0x00010000) +#define AFIO_CR_UDM_BC_VSRC ((uint32_t)0x00020000) +#define AFIO_CR_UPD_BC_CMPE ((uint32_t)0x00040000) +#define AFIO_CR_UDM_BC_CMPE ((uint32_t)0x00080000) +#define AFIO_CR_UPD_BC_CMPO ((uint32_t)0x00100000) +#define AFIO_CR_UDM_BC_CMPO ((uint32_t)0x00200000) + +/***************** Bit definition for AFIO_PCFR2 register *****************/ +#define AFIO_PCFR2_USART4_RM ((uint32_t)0x00010000) +#define AFIO_PCFR2_USART2_RM_H ((uint32_t)0x00040000) + +#define AFIO_PCFR2_USART1_RM_H ((uint32_t)0x00180000) +#define AFIO_PCFR2_USART1_RM_H_0 ((uint32_t)0x00080000) +#define AFIO_PCFR2_USART1_RM_H_1 ((uint32_t)0x00100000) + +#define AFIO_PCFR2_TIM2_RM_H ((uint32_t)0x00200000) +#define AFIO_PCFR2_TIM1_RM_H ((uint32_t)0x00400000) +#define AFIO_PCFR2_I2C_RM_H ((uint32_t)0x00800000) +#define AFIO_PCFR2_SPI1_RM_H ((uint32_t)0x01000000) +#define AFIO_PCFR2_LPTIM_RM ((uint32_t)0x02000000) + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) /* PVD level 0 */ +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) /* PVD level 1 */ +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) /* PVD level 2 */ +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) /* PVD level 3 */ +#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080) /* PVD level 4 */ +#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0) /* PVD level 5 */ +#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0) /* PVD level 6 */ +#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0) /* PVD level 7 */ + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +#define PWR_CTLR_FLASH_LP_REG ((uint16_t)0x0200) + +#define PWR_CTLR_FLASH_LP ((uint16_t)0x0C00) /* FLASH_LP [1:0]*/ +#define PWR_CTLR_FLASH_LP_0 ((uint16_t)0x0400) +#define PWR_CTLR_FLASH_LP_1 ((uint16_t)0x0800) + +#define PWR_CTLR_AUTO_LDO_EC ((uint16_t)0x1000) +#define PWR_CTLR_LDO_EC ((uint16_t)0x2000) +#define PWR_CTLR_R2KSTY ((uint32_t)0x00010000) +#define PWR_CTLR_R18KSTY ((uint32_t)0x00020000) +#define PWR_CTLR_R2KVBAT ((uint32_t)0x00040000) +#define PWR_CTLR_R18KVBAT ((uint32_t)0x00080000) +#define PWR_RAMLV ((uint32_t)0x00100000) + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSILP ((uint32_t)0x00000004) +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_HSELP ((uint32_t)0x00100000) +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (HB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (PB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* PPRE1 not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* PPRE1 divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* PPRE1 divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* PPRE1 divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* PPRE1 divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (PB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* PPRE2 not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* PPRE2 divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* PPRE2 divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* PPRE2 divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* PPRE2 divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* ADCPRE divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* ADCPRE divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* ADCPRE divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* ADCPRE divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +/* for other CH32L103 */ +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ +#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ + +#define RCC_CFGR0_USBPRE ((uint32_t)0x00C00000) /* USBPRE[1:0] bits*/ +#define RCC_USBPRE_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define RCC_USBPRE_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +#define RCC_ADC_DUTY_CHG ((uint32_t)0x70000000) /* DUTY_CHG[2:0] bits */ +#define RCC_ADC_DUTY_CHG_0 ((uint32_t)0x10000000) +#define RCC_ADC_DUTY_CHG_1 ((uint32_t)0x20000000) +#define RCC_ADC_DUTY_CHG_2 ((uint32_t)0x40000000) + +#define RCC_ADC_PRE_ADJ ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_PB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADCRST ((uint32_t)0x00000200) /* ADC interface reset */ +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +/***************** Bit definition for RCC_PB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_TIM4RST ((uint32_t)0x00000004) +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 2 reset */ +#define RCC_USART4RST ((uint32_t)0x00080000) /* USART 2 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 1 reset */ +#define RCC_CANRST ((uint32_t)0x02000000) /* CAN reset */ +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ +#define RCC_LPTIMRST ((uint32_t)0x80000000) /* USB Device reset */ + +/****************** Bit definition for RCC_HBPCENR register ******************/ +#define RCC_DMAEN ((uint16_t)0x0001) /* DMA clock enable */ +#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ +#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ +#define RCC_USBFSEN ((uint16_t)0x1000) +#define RCC_USBPDEN ((uint32_t)0x00020000) + +/****************** Bit definition for RCC_PB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADCEN ((uint32_t)0x00000200) /* ADC interface clock enable */ +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_PB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_TIM4EN ((uint32_t)0x00000004) +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_SPI2EN ((uint32_t)0x00004000) +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_USART3EN ((uint32_t)0x00040000) /* USART 3 clock enable */ +#define RCC_USART4EN ((uint32_t)0x00080000) /* USART 4 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ +#define RCC_I2C2EN ((uint32_t)0x00400000) /* I2C 2 clock enable */ +#define RCC_CANEN ((uint32_t)0x02000000) +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ +#define RCC_LPTIMEN ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCRH register *******************/ +#define RTC_PSCRH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRCRL register *******************/ +#define RTC_PRCRL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register ******************/ +#define SPI_HSRXEN ((uint16_t)0x0001) + + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_BKSEL ((uint16_t)0x1000) +#define TIM_TMR_CAP_OV_EN ((uint16_t)0x4000) +#define TIM_TMR_CAP_LVL_EN ((uint16_t)0x8000) + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +#define TIM4_CNT ((uint32_t)0xFFFFFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ +#define TIM_LEVEL1 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ +#define TIM_LEVEL2 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ +#define TIM_LEVEL3 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ +#define TIM_LEVEL4 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint32_t)0xFFFFFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + +#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000700) /* ULLDO_TRIM[2:0] bits */ +#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ +#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ +#define EXTEN_ULLDO_TRIM2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define EXTEN_LDO_TRIM ((uint32_t)0x00003000) /* LDO_TRIM[1:0] bits */ +#define EXTEN_LDO_TRIM0 ((uint32_t)0x00001000) /* Bit 0 */ +#define EXTEN_LDO_TRIM1 ((uint32_t)0x00002000) /* Bit 1 */ + +/******************************************************************************/ +/* DEBUG SUPPORT */ +/******************************************************************************/ +/******************* Bit definition for DBGMCU_DR register *******************/ +#define DBG_DEBUGMCU_SLEEP ((uint32_t)0x00000001) +#define DBG_DEBUGMCU_STOP ((uint32_t)0x00000002) +#define DBG_DEBUGMCU_STBY ((uint32_t)0x00000004) +#define DBG_DEBUGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBG_DEBUGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBG_DEBUGMCU_I2C1SMBUS_TOUT ((uint32_t)0x00000400) +#define DBG_DEBUGMCU_I2C2SMBUS_TOUT ((uint32_t)0x00000800) +#define DBG_DEBUGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBG_DEBUGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBG_DEBUGMCU_TIM3_STOP ((uint32_t)0x00004000) +#define DBG_DEBUGMCU_TIM4_STOP ((uint32_t)0x00008000) +#define DBG_DEBUGMCU_CAN_STOP ((uint32_t)0x00010000) + +/******************************************************************************/ +/* OPTICAL PARAMETER */ +/******************************************************************************/ + +/******************* Bit definition for OPA_CFGR1 register *******************/ +#define OPA_CFGR1_POLLEN ((uint32_t)0x00000001) +#define OPA_CFGR1_BKINEN ((uint32_t)0x00000004) +#define OPA_CFGR1_RSTEN ((uint32_t)0x00000010) +#define OPA_CFGR1_OPCMLOCK ((uint32_t)0x00000080) +#define OPA_CFGR1_IEOUT ((uint32_t)0x00000100) +#define OPA_CFGR1_IECNT ((uint32_t)0x00000400) +#define OPA_CFGR1_NMIEN ((uint32_t)0x00000800) +#define OPA_CFGR1_IFOUT ((uint32_t)0x00001000) +#define OPA_CFGR1_IFCNT ((uint32_t)0x00004000) + +/******************* Bit definition for OPA_CFGR2 register *******************/ +#define OPA_CFGR2_POLL_VLU ((uint32_t)0x000001FF) +#define OPA_CFGR2_POLL_NUM ((uint32_t)0x00000E00) +#define OPA_CFGR2_POLL_CNT ((uint32_t)0x00007000) + +/******************* Bit definition for OPA_CTLR1 register *******************/ +#define OPA_CTLR1_EN1 ((uint32_t)0x00000001) +#define OPA_CTLR1_MODE1 ((uint32_t)0x0000000E) +#define OPA_CTLR1_PSEL1 ((uint32_t)0x00000070) +#define OPA_CTLR1_FBEN1 ((uint32_t)0x00000080) +#define OPA_CTLR1_NSEL1 ((uint32_t)0x00000F00) +#define OPA_CTLR1_LP1 ((uint32_t)0x00001000) +#define OPA_CTLR1_INTRIMP ((uint32_t)0x00010000) +#define OPA_CTLR1_ITRIMP ((uint32_t)0x003E0000) +#define OPA_CTLR1_INTRIMN ((uint32_t)0x01000000) +#define OPA_CTLR1_ITRIMN ((uint32_t)0x3E000000) + +/******************* Bit definition for OPA_CTLR2 register *******************/ +#define OPA_CTLR2_EN1 ((uint32_t)0x00000001) +#define OPA_CTLR2_MODE1 ((uint32_t)0x00000006) +#define OPA_CTLR2_NSEL1 ((uint32_t)0x00000008) +#define OPA_CTLR2_PSEL1 ((uint32_t)0x00000010) +#define OPA_CTLR2_HYEN1 ((uint32_t)0x00000020) +#define OPA_CTLR2_LP1 ((uint32_t)0x00000040) +#define OPA_CTLR2_EN2 ((uint32_t)0x00000100) +#define OPA_CTLR2_MODE2 ((uint32_t)0x00000600) +#define OPA_CTLR2_NSEL2 ((uint32_t)0x00000800) +#define OPA_CTLR2_PSEL2 ((uint32_t)0x00001000) +#define OPA_CTLR2_HYEN2 ((uint32_t)0x00002000) +#define OPA_CTLR2_LP2 ((uint32_t)0x00004000) +#define OPA_CTLR2_EN3 ((uint32_t)0x00010000) +#define OPA_CTLR2_MODE3 ((uint32_t)0x00060000) +#define OPA_CTLR2_NSEL3 ((uint32_t)0x00080000) +#define OPA_CTLR2_PSEL3 ((uint32_t)0x00100000) +#define OPA_CTLR2_HYEN3 ((uint32_t)0x00200000) +#define OPA_CTLR2_LP3 ((uint32_t)0x00400000) + +#define OPA_CTLR2_WKUP_MD ((uint32_t)0x03000000) +#define OPA_CTLR2_WKUP_MD_0 ((uint32_t)0x01000000) +#define OPA_CTLR2_WKUP_MD_1 ((uint32_t)0x02000000) + +/******************* Bit definition for OPCMKEY register *******************/ +#define OPCM_KEY ((uint32_t)0xFFFFFFFF) + +/******************************************************************************/ +/* LOW POWER TIM */ +/******************************************************************************/ +/******************* Bit definition for LPTIM_ISR register *******************/ +#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) +#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) +#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) +#define LPTIM_ISR_ARROK ((uint32_t)0000000010) +#define LPTIM_ISR_UP ((uint32_t)0x00000020) +#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) +#define LPTIM_ISR_DIRSYNC ((uint32_t)0x00000080) + +/******************* Bit definition for LPTIM_ICR register *******************/ +#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) +#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) +#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) +#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) +#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) +#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) +#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) + +/******************* Bit definition for LPTIM_IER register *******************/ +#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) +#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) +#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) +#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) +#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) +#define LPTIM_IER_UPIE ((uint32_t)0x00000020) +#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) + +/******************* Bit definition for LPTIM_CFGR register *******************/ +#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) +#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) +#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) +#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) +#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) +#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x00006000) +#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) +#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) +#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) +#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) +#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) +#define LPTIM_CFGR_CONTMODE ((uint32_t)0x00800000) +#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) +#define LPTIM_CFGR_CLKSEL ((uint32_t)0x06000000) +#define LPTIM_CFGR_FORCEPWM ((uint32_t)0x08000000) + +/******************* Bit definition for LPTIM_CR register *******************/ +#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) +#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) +#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) +#define LPTIM_CR_OUTEN ((uint32_t)0x00000008) +#define LPTIM_CR_DIR_EXTEN ((uint32_t)0x00000010) + +/******************* Bit definition for LPTIM_CMP register *******************/ +#define LPTIM_CMP ((uint32_t)0x0000FFFF) + +/******************* Bit definition for LPTIM_ARR register *******************/ +#define LPTIM_ARR ((uint32_t)0x0000FFFF) + +/******************* Bit definition for LPTIM_CNT register *******************/ +#define LPTIM_COUNT ((uint32_t)0x0000FFFF) + +/******************************************************************************/ +/* TOUCH KEY */ +/******************************************************************************/ +/******************* Bit definition for TKEY_CHARGE register *******************/ +#define TKEY_CHGOFFSET ((uint32_t)0x000003FF) + +/******************* Bit definition for TKEY_ACT_DCG register *******************/ +#define TKEY_TKACTDCG ((uint32_t)0x000003FF) + +/******************* Bit definition for TKEY_DR register *******************/ +#define TKEY_DR ((uint32_t)0x0000FFFF) + +#include "ch32l103_conf.h" + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_adc.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_adc.h index f411e1e..e539325 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_adc.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_adc.h @@ -1,218 +1,211 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_adc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * ADC firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_ADC_H -#define __CH32L103_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* ADC Init structure definition */ -typedef struct -{ - uint32_t ADC_Mode; /* Configures the ADC to operate in independent or - dual mode. - This parameter can be a value of @ref ADC_mode */ - - FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in - Scan (multichannels) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ - - uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. - This parameter can be a value of @ref ADC_OutputBuffer */ - - uint32_t ADC_Pga; /* Specifies the PGA gain multiple. - This parameter can be a value of @ref ADC_Pga */ -} ADC_InitTypeDef; - -/* ADC_mode */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) -#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) -#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) -#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) -#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) -#define ADC_Mode_RegSimult ((uint32_t)0x00060000) -#define ADC_Mode_FastInterl ((uint32_t)0x00070000) -#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) -#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) - -/* ADC_external_trigger_sources_for_regular_channels_conversion */ -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x000C0000) -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) - -/* ADC_data_align */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) - -/* ADC_channels */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) -#define ADC_Channel_18 ((uint8_t)0x12) -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) -#define ADC_Channel_CalInternal ((uint8_t)ADC_Channel_18) - -/*ADC_output_buffer*/ -#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) -#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) - -/*ADC_pga*/ -#define ADC_Pga_1 ((uint32_t)0x00000000) -#define ADC_Pga_4 ((uint32_t)0x08000000) -#define ADC_Pga_16 ((uint32_t)0x10000000) -#define ADC_Pga_64 ((uint32_t)0x18000000) - -/* ADC_sampling_time */ -#define ADC_SampleTime_CyclesMode0 ((uint8_t)0x00) -#define ADC_SampleTime_CyclesMode1 ((uint8_t)0x01) -#define ADC_SampleTime_CyclesMode2 ((uint8_t)0x02) -#define ADC_SampleTime_CyclesMode3 ((uint8_t)0x03) -#define ADC_SampleTime_CyclesMode4 ((uint8_t)0x04) -#define ADC_SampleTime_CyclesMode5 ((uint8_t)0x05) -#define ADC_SampleTime_CyclesMode6 ((uint8_t)0x06) -#define ADC_SampleTime_CyclesMode7 ((uint8_t)0x07) - -/* ADC_external_trigger_sources_for_injected_channels_conversion */ -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) -#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x00006000) -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) - -/* ADC_injected_channel_selection */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) - -/* ADC_analog_watchdog_selection */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -/* ADC_interrupts_definition */ -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) - -/* ADC_flags_definition */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) - -/* ADC_TKey_WakeUp_IO_mode_definition */ -#define ADC_TKey_WakeUp_Mode0 ((uint32_t)0x00000000) -#define ADC_TKey_WakeUp_Mode1 ((uint32_t)0x00080000) -#define ADC_TKey_WakeUp_Mode2 ((uint32_t)0x00100000) -#define ADC_TKey_WakeUp_Mode3 ((uint32_t)0x00180000) - -/* ADC_Sample_mode_definition */ -#define ADC_Sample_NoOver_1M_Mode ((uint32_t)0x00000000) -#define ADC_Sample_Over_1M_Mode ((uint32_t)0x00000020) - - -void ADC_DeInit(ADC_TypeDef *ADCx); -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); -void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); -void ADC_ResetCalibration(ADC_TypeDef *ADCx); -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); -void ADC_StartCalibration(ADC_TypeDef *ADCx); -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); -void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); -uint32_t ADC_GetDualModeConversionValue(void); -void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); -void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); -void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); -s32 TempSensor_Volt_To_Temper(s32 Value); -void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_TKey_WakeUpCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint32_t IO_Mode, FunctionalState NewState); -void ADC_TKey_ChannelxMulShieldCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState); -void ADC_TKey_MulShieldCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_FIFO_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_Sample_ModeConfig(ADC_TypeDef *ADCx, uint32_t ADC_Sample_Mode); -void ADC_OffsetCalibrationConfig(ADC_TypeDef *ADCx); -void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -int16_t Get_CalibrationValue(ADC_TypeDef *ADCx); -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_adc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/06 + * Description : This file contains all the functions prototypes for the + * ADC firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_ADC_H +#define __CH32L103_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ + + uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. + This parameter can be a value of @ref ADC_OutputBuffer */ + + uint32_t ADC_Pga; /* Specifies the PGA gain multiple. + This parameter can be a value of @ref ADC_Pga */ +} ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) +#define ADC_Channel_18 ((uint8_t)0x12) +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) +#define ADC_Channel_CalInternal ((uint8_t)ADC_Channel_18) + +/*ADC_output_buffer*/ +#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) +#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) + +/*ADC_pga*/ +#define ADC_Pga_1 ((uint32_t)0x00000000) +#define ADC_Pga_4 ((uint32_t)0x08000000) +#define ADC_Pga_16 ((uint32_t)0x10000000) +#define ADC_Pga_64 ((uint32_t)0x18000000) + +/* ADC_sampling_time */ +#define ADC_SampleTime_CyclesMode0 ((uint8_t)0x00) +#define ADC_SampleTime_CyclesMode1 ((uint8_t)0x01) +#define ADC_SampleTime_CyclesMode2 ((uint8_t)0x02) +#define ADC_SampleTime_CyclesMode3 ((uint8_t)0x03) +#define ADC_SampleTime_CyclesMode4 ((uint8_t)0x04) +#define ADC_SampleTime_CyclesMode5 ((uint8_t)0x05) +#define ADC_SampleTime_CyclesMode6 ((uint8_t)0x06) +#define ADC_SampleTime_CyclesMode7 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +/* ADC_Sample_mode_definition */ +#define ADC_Sample_NoOver_1M_Mode ((uint32_t)0x00000000) +#define ADC_Sample_Over_1M_Mode ((uint32_t)0x00000020) + + +void ADC_DeInit(ADC_TypeDef *ADCx); +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_StartCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); +s32 TempSensor_Volt_To_Temper(s32 Value); +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_TKey_ChannelxMulShieldCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState); +void ADC_TKey_MulShieldCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_FIFO_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_Sample_ModeConfig(ADC_TypeDef *ADCx, uint32_t ADC_Sample_Mode); +void ADC_OffsetCalibrationConfig(ADC_TypeDef *ADCx); +void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_bkp.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_bkp.h index ccc57d4..be02302 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_bkp.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_bkp.h @@ -1,65 +1,65 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_bkp.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * BKP firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_BKP_H -#define __CH32L103_BKP_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* Tamper_Pin_active_level */ -#define BKP_TamperPinLevel_High ((uint16_t)0x0000) -#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) - -/* RTC_output_source_to_output_on_the_Tamper_pin */ -#define BKP_RTCOutputSource_None ((uint16_t)0x0000) -#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) -#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) -#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) - -/* Data_Backup_Register */ -#define BKP_DR1 ((uint16_t)0x0004) -#define BKP_DR2 ((uint16_t)0x0008) -#define BKP_DR3 ((uint16_t)0x000C) -#define BKP_DR4 ((uint16_t)0x0010) -#define BKP_DR5 ((uint16_t)0x0014) -#define BKP_DR6 ((uint16_t)0x0018) -#define BKP_DR7 ((uint16_t)0x001C) -#define BKP_DR8 ((uint16_t)0x0020) -#define BKP_DR9 ((uint16_t)0x0024) -#define BKP_DR10 ((uint16_t)0x0028) -#define BKP_DR11 ((uint16_t)0x0040) -#define BKP_DR12 ((uint16_t)0x0044) -#define BKP_DR13 ((uint16_t)0x0048) - - -void BKP_DeInit(void); -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); -void BKP_TamperPinCmd(FunctionalState NewState); -void BKP_ITConfig(FunctionalState NewState); -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); -FlagStatus BKP_GetFlagStatus(void); -void BKP_ClearFlag(void); -ITStatus BKP_GetITStatus(void); -void BKP_ClearITPendingBit(void); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_bkp.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * BKP firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_BKP_H +#define __CH32L103_BKP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* Tamper_Pin_active_level */ +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) + +/* RTC_output_source_to_output_on_the_Tamper_pin */ +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) + +/* Data_Backup_Register */ +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) + + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_can.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_can.h index 0c0e313..c6795b0 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_can.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_can.h @@ -1,630 +1,630 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_can.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * CAN firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_CAN_H -#define __CH32L103_CAN_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* CAN init structure definition */ -typedef struct -{ - uint16_t CAN_Prescaler; /* Specifies the length of a time quantum. - It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /* Specifies the CAN operating mode. - This parameter can be a value of - @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /* Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of - @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit - Segment 2. - This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /* Enable or disable the time triggered - communication mode. This parameter can be set - either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off - management. This parameter can be set either - to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or - DISABLE. */ - - FunctionalState CAN_NART; /* Enable or disable the no-automatic - retransmission mode. This parameter can be - set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE - or DISABLE. */ - - FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE - or DISABLE. */ -} CAN_InitTypeDef; - -/* CAN filter init structure definition */ -typedef struct -{ - uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /* Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /* Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/* CAN Tx message structure definition */ -typedef struct -{ - uint32_t StdId; /* Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /* Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /* Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /* Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /* Specifies the length of the frame that will be - transmitted. This parameter can be a value between - 0 to 8 */ - - uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ -} CanTxMsg; - -/* CAN Rx message structure definition */ -typedef struct -{ - uint32_t StdId; /* Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /* Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /* Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /* Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /* Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t FMI; /* Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanRxMsg; - -/* CANFD init structure definition */ -typedef struct -{ - uint16_t CANFD_Prescaler; /* Specifies the length of a time quantum. - It ranges from 1 to 32. */ - - uint8_t CANFD_Mode; /* Specifies the CAN operating mode. - This parameter can be a value of - @ref CAN_operating_mode */ - - uint8_t CANFD_SJW; /* Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of - @ref CANFD_synchronisation_jump_width */ - - uint8_t CANFD_BS1; /* Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CANFD_time_quantum_in_bit_segment_1 */ - - uint8_t CANFD_BS2; /* Specifies the number of time quanta in Bit - Segment 2. - This parameter can be a value of - @ref CANFD_time_quantum_in_bit_segment_2 */ - - uint8_t CANFD_TDC_FILTER; /* Specifies the number of time quanta in Bit Segment - Minimum delay of internal delay counter. - It ranges from 0 to 63. */ - - uint8_t CANFD_TDC0; /* Specifies the number of time quanta in Bit Segment - transmission delay compensation offset. - It ranges from 0 to 63. */ - - FunctionalState CANFD_TDCE; /* Enable or disable transmission delay compensation offset. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CANFD_TTCM; /* Enable or disable the time triggered - communication mode. This parameter can be set - either to ENABLE or DISABLE. */ - - FunctionalState CANFD_ABOM; /* Enable or disable the automatic bus-off - management. This parameter can be set either - to ENABLE or DISABLE. */ - - FunctionalState CANFD_AWUM; /* Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or - DISABLE. */ - - FunctionalState CANFD_NART; /* Enable or disable the no-automatic - retransmission mode. This parameter can be - set either to ENABLE or DISABLE. */ - - FunctionalState CANFD_TXFP; /* Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE - or DISABLE. */ - - FunctionalState CANFD_RES_Error; /* Enable or disable the RES bit can generate error . - This parameter can be set either to ENABLE - or DISABLE. */ - - FunctionalState CANFD_ESI_Auto_TXM0; /* Enable or disable the ESI bit auto mode for Tx mailbox 0. - This parameter can be set either to ENABLE - or DISABLE. */ - - FunctionalState CANFD_ESI_Auto_TXM1; /* Enable or disable the ESI bit auto mode for Tx mailbox 1. - This parameter can be set either to ENABLE - or DISABLE. */ - - FunctionalState CANFD_ESI_Auto_TXM2; /* Enable or disable the ESI bit auto mode for Tx mailbox 2. - This parameter can be set either to ENABLE - or DISABLE. */ - - FunctionalState CANFD_BRS_TXM0; /* Enable or disable the BRS bit speed switch for Tx mailbox 0. - This parameter can be set either to ENABLE - or DISABLE. */ - - FunctionalState CANFD_BRS_TXM1; /* Enable or disable the BRS bit speed switch for Tx mailbox 1. - This parameter can be set either to ENABLE - or DISABLE. */ - - FunctionalState CANFD_BRS_TXM2; /* Enable or disable the BRS bit speed switch for Tx mailbox 2. - This parameter can be set either to ENABLE - or DISABLE. */ -} CANFD_InitTypeDef; - -/* CANFD Tx message structure definition */ -typedef struct -{ - uint32_t StdId; /* Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /* Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t Data[64]; /* Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ - - uint8_t IDE; /* Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /* Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /* Specifies the length of the frame that will be - transmitted. - This parameter can be a value of - @ref CANFD_data_length_code */ -} CanFDTxMsg; - -/* CANFD Rx message structure definition */ -typedef struct -{ - uint32_t StdId; /* Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /* Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t Data[64]; /* Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t IDE; /* Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /* Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /* Specifies the length of the frame that will be received. - This parameter can be a value of - 0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64 */ - - uint8_t BRS; /* Specifies the length of the frame that will be received. - This parameter can be a value of - @ref CANFD_data_length_code */ - - uint8_t ESI; /* Specifies the length of the frame that will be received. - This parameter can be a value of - @ref CANFD_data_length_code */ - - uint8_t RES; /* Specifies the length of the frame that will be received. - This parameter can be a value of - @ref CANFD_data_length_code */ - - uint8_t FMI; /* Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanFDRxMsg; - -/* CAN_sleep_constants */ -#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */ -#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */ - -/* CAN_Mode */ -#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */ - -/* CAN_Operating_Mode */ -#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */ -#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */ -#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */ - -/* CAN_Mode_Status */ -#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */ -#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */ - -/* CAN_synchronisation_jump_width */ -#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ - -/* CAN_time_quantum_in_bit_segment_1 */ -#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ - -/* CAN_time_quantum_in_bit_segment_2 */ -#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ - -/* CAN_filter_mode */ -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */ - -/* CAN_filter_scale */ -#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */ - -/* CAN_filter_FIFO */ -#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */ -#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */ - -/* CAN_identifier_type */ -#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */ -#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */ - -/* CAN_remote_transmission_request */ -#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */ -#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */ - -/* CAN_transmit_constants */ -#define CAN_TxStatus_Failed ((uint8_t)0x00) /* CAN transmission failed */ -#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */ -#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */ -#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ - -/* CAN_receive_FIFO_number_constants */ -#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */ - -/* CAN_sleep_constants */ -#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */ -#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */ - -/* CAN_wake_up_constants */ -#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */ -#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */ - -/* CAN_Error_Code_constants */ -#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */ -#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */ -#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */ -#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */ -#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */ -#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */ -#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */ -#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */ - -/* CAN_flags */ -/* Transmit Flags */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - * and CAN_ClearFlag() functions. - * If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. -*/ -#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */ - -/* Receive Flags */ -#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */ -#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */ -#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */ -/* Note: - *When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. - *In this case the SLAK bit can be polled. -*/ - - -/* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */ -#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */ - -/* CAN_interrupts */ -#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/ - -/* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/ -#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/ - -/* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/ -#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/ -#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/ -#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/ -#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/ - -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME - -/* CAN_Legacy */ -#define CANINITFAILED CAN_InitStatus_Failed -#define CANINITOK CAN_InitStatus_Success -#define CAN_FilterFIFO0 CAN_Filter_FIFO0 -#define CAN_FilterFIFO1 CAN_Filter_FIFO1 -#define CAN_ID_STD CAN_Id_Standard -#define CAN_ID_EXT CAN_Id_Extended -#define CAN_RTR_DATA CAN_RTR_Data -#define CAN_RTR_REMOTE CAN_RTR_Remote -#define CANTXFAILE CAN_TxStatus_Failed -#define CANTXOK CAN_TxStatus_Ok -#define CANTXPENDING CAN_TxStatus_Pending -#define CAN_NO_MB CAN_TxStatus_NoMailBox -#define CANSLEEPFAILED CAN_Sleep_Failed -#define CANSLEEPOK CAN_Sleep_Ok -#define CANWAKEUPFAILED CAN_WakeUp_Failed -#define CANWAKEUPOK CAN_WakeUp_Ok - -/* CAN_BS1_Mode */ -#define CAN_BS1_4bit ((uint32_t)0x00000000) -#define CAN_BS1_6bit ((uint32_t)0x00000100) - -/* CANFD_data_length_code */ -#define CANFD_DLC_BYTES_0 ((uint32_t)0x0000) /* 0 bytes data field */ -#define CANFD_DLC_BYTES_1 ((uint32_t)0x0001) /* 1 bytes data field */ -#define CANFD_DLC_BYTES_2 ((uint32_t)0x0002) /* 2 bytes data field */ -#define CANFD_DLC_BYTES_3 ((uint32_t)0x0003) /* 3 bytes data field */ -#define CANFD_DLC_BYTES_4 ((uint32_t)0x0004) /* 4 bytes data field */ -#define CANFD_DLC_BYTES_5 ((uint32_t)0x0005) /* 5 bytes data field */ -#define CANFD_DLC_BYTES_6 ((uint32_t)0x0006) /* 6 bytes data field */ -#define CANFD_DLC_BYTES_7 ((uint32_t)0x0007) /* 7 bytes data field */ -#define CANFD_DLC_BYTES_8 ((uint32_t)0x0008) /* 8 bytes data field */ -#define CANFD_DLC_BYTES_12 ((uint32_t)0x0009) /* 12 bytes data field */ -#define CANFD_DLC_BYTES_16 ((uint32_t)0x000A) /* 16 bytes data field */ -#define CANFD_DLC_BYTES_20 ((uint32_t)0x000B) /* 20 bytes data field */ -#define CANFD_DLC_BYTES_24 ((uint32_t)0x000C) /* 24 bytes data field */ -#define CANFD_DLC_BYTES_32 ((uint32_t)0x000D) /* 32 bytes data field */ -#define CANFD_DLC_BYTES_48 ((uint32_t)0x000E) /* 48 bytes data field */ -#define CANFD_DLC_BYTES_64 ((uint32_t)0x000F) /* 64 bytes data field */ - -/* CANFD_synchronisation_jump_width */ -#define CANFD_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ -#define CANFD_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ -#define CANFD_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ -#define CANFD_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ -#define CANFD_SJW_5tq ((uint8_t)0x04) /* 5 time quantum */ -#define CANFD_SJW_6tq ((uint8_t)0x05) /* 6 time quantum */ -#define CANFD_SJW_7tq ((uint8_t)0x06) /* 7 time quantum */ -#define CANFD_SJW_8tq ((uint8_t)0x07) /* 8 time quantum */ -#define CANFD_SJW_9tq ((uint8_t)0x08) /* 9 time quantum */ -#define CANFD_SJW_10tq ((uint8_t)0x09) /* 10 time quantum */ -#define CANFD_SJW_11tq ((uint8_t)0x0A) /* 11 time quantum */ -#define CANFD_SJW_12tq ((uint8_t)0x0B) /* 12 time quantum */ -#define CANFD_SJW_13tq ((uint8_t)0x0C) /* 13 time quantum */ -#define CANFD_SJW_14tq ((uint8_t)0x0D) /* 14 time quantum */ -#define CANFD_SJW_15tq ((uint8_t)0x0E) /* 15 time quantum */ -#define CANFD_SJW_16tq ((uint8_t)0x0F) /* 16 time quantum */ - -/* CANFD_time_quantum_in_bit_segment_1 */ -#define CANFD_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ -#define CANFD_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ -#define CANFD_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ -#define CANFD_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ -#define CANFD_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ -#define CANFD_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ -#define CANFD_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ -#define CANFD_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ -#define CANFD_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ -#define CANFD_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ -#define CANFD_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ -#define CANFD_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ -#define CANFD_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ -#define CANFD_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ -#define CANFD_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ -#define CANFD_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ -#define CANFD_BS1_17tq ((uint8_t)0x10) /* 17 time quantum */ -#define CANFD_BS1_18tq ((uint8_t)0x11) /* 18 time quantum */ -#define CANFD_BS1_19tq ((uint8_t)0x12) /* 19 time quantum */ -#define CANFD_BS1_20tq ((uint8_t)0x13) /* 20 time quantum */ -#define CANFD_BS1_21tq ((uint8_t)0x14) /* 21 time quantum */ -#define CANFD_BS1_22tq ((uint8_t)0x15) /* 22 time quantum */ -#define CANFD_BS1_23tq ((uint8_t)0x16) /* 23 time quantum */ -#define CANFD_BS1_24tq ((uint8_t)0x17) /* 24 time quantum */ -#define CANFD_BS1_25tq ((uint8_t)0x18) /* 25 time quantum */ -#define CANFD_BS1_26tq ((uint8_t)0x19) /* 26 time quantum */ -#define CANFD_BS1_27tq ((uint8_t)0x1A) /* 27 time quantum */ -#define CANFD_BS1_28tq ((uint8_t)0x1B) /* 28 time quantum */ -#define CANFD_BS1_29tq ((uint8_t)0x1C) /* 29 time quantum */ -#define CANFD_BS1_30tq ((uint8_t)0x1D) /* 30 time quantum */ -#define CANFD_BS1_31tq ((uint8_t)0x1E) /* 31 time quantum */ -#define CANFD_BS1_32tq ((uint8_t)0x1F) /* 32 time quantum */ - -/* CANFD_time_quantum_in_bit_segment_2 */ -#define CANFD_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ -#define CANFD_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ -#define CANFD_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ -#define CANFD_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ -#define CANFD_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ -#define CANFD_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ -#define CANFD_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ -#define CANFD_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ -#define CANFD_BS2_9tq ((uint8_t)0x08) /* 9 time quantum */ -#define CANFD_BS2_10tq ((uint8_t)0x09) /* 10 time quantum */ -#define CANFD_BS2_11tq ((uint8_t)0x0A) /* 11 time quantum */ -#define CANFD_BS2_12tq ((uint8_t)0x0B) /* 12 time quantum */ -#define CANFD_BS2_13tq ((uint8_t)0x0C) /* 13 time quantum */ -#define CANFD_BS2_14tq ((uint8_t)0x0D) /* 14 time quantum */ -#define CANFD_BS2_15tq ((uint8_t)0x0E) /* 15 time quantum */ -#define CANFD_BS2_16tq ((uint8_t)0x0F) /* 16 time quantum */ - -/* CAN_Transmit_Mailbox_number_constants */ -#define CAN_Transmit_Mailbox0 ((uint8_t)0x00) -#define CAN_Transmit_Mailbox1 ((uint8_t)0x01) -#define CAN_Transmit_Mailbox2 ((uint8_t)0x02) - - -void CAN_DeInit(CAN_TypeDef *CANx); -uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState); -void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState); -uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox); -void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage); -void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber); -uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode); -uint8_t CAN_Sleep(CAN_TypeDef *CANx); -uint8_t CAN_WakeUp(CAN_TypeDef *CANx); -uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx); -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx); -void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT); -void CAN_BS1_ModeConfig(CAN_TypeDef* CANx, uint32_t CAN_BS1_Mode, uint8_t CAN_BS1_tq); -void CAN_BusOff_ErrCntConfig(CAN_TypeDef *CANx, uint8_t BusOff_ErrCnt); -void CANFD_Restrict_ModeCmd(CAN_TypeDef *CANx, FunctionalState NewState); -uint8_t CANFD_Init(CAN_TypeDef *CANx, CANFD_InitTypeDef *CANFD_InitStruct); -void CANFD_StructInit(CANFD_InitTypeDef *CANFD_InitStruct); -uint8_t CANFD_Transmit(CAN_TypeDef *CANx, CanFDTxMsg *TxMessage); -ErrorStatus CANFD_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanFDRxMsg *RxMessage); -uint8_t CANFD_GetTransmitDelayOffsetVal(CAN_TypeDef *CANx); -void CANFD_TransmitMailbox_DMAAdr(CAN_TypeDef *CANx, uint8_t MailboxNumber, uint32_t Address); -void CANFD_ReceiveFIFO_DMAAdr(CAN_TypeDef *CANx, uint8_t FIFONumber, uint32_t Address); - - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_can.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * CAN firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_CAN_H +#define __CH32L103_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* CAN init structure definition */ +typedef struct +{ + uint16_t CAN_Prescaler; /* Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /* Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /* Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /* Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CAN_NART; /* Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitTypeDef; + +/* CAN filter init structure definition */ +typedef struct +{ + uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /* Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /* Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/* CAN Tx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/* CAN Rx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /* Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/* CANFD init structure definition */ +typedef struct +{ + uint16_t CANFD_Prescaler; /* Specifies the length of a time quantum. + It ranges from 1 to 32. */ + + uint8_t CANFD_Mode; /* Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CANFD_SJW; /* Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CANFD_synchronisation_jump_width */ + + uint8_t CANFD_BS1; /* Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CANFD_time_quantum_in_bit_segment_1 */ + + uint8_t CANFD_BS2; /* Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CANFD_time_quantum_in_bit_segment_2 */ + + uint8_t CANFD_TDC_FILTER; /* Specifies the number of time quanta in Bit Segment + Minimum delay of internal delay counter. + It ranges from 0 to 63. */ + + uint8_t CANFD_TDC0; /* Specifies the number of time quanta in Bit Segment + transmission delay compensation offset. + It ranges from 0 to 63. */ + + FunctionalState CANFD_TDCE; /* Enable or disable transmission delay compensation offset. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CANFD_TTCM; /* Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CANFD_ABOM; /* Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CANFD_AWUM; /* Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CANFD_NART; /* Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CANFD_TXFP; /* Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_RES_Error; /* Enable or disable the RES bit can generate error . + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_ESI_Auto_TXM0; /* Enable or disable the ESI bit auto mode for Tx mailbox 0. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_ESI_Auto_TXM1; /* Enable or disable the ESI bit auto mode for Tx mailbox 1. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_ESI_Auto_TXM2; /* Enable or disable the ESI bit auto mode for Tx mailbox 2. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_BRS_TXM0; /* Enable or disable the BRS bit speed switch for Tx mailbox 0. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_BRS_TXM1; /* Enable or disable the BRS bit speed switch for Tx mailbox 1. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CANFD_BRS_TXM2; /* Enable or disable the BRS bit speed switch for Tx mailbox 2. + This parameter can be set either to ENABLE + or DISABLE. */ +} CANFD_InitTypeDef; + +/* CANFD Tx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t Data[64]; /* Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be + transmitted. + This parameter can be a value of + @ref CANFD_data_length_code */ +} CanFDTxMsg; + +/* CANFD Rx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t Data[64]; /* Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be received. + This parameter can be a value of + 0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64 */ + + uint8_t BRS; /* Specifies the length of the frame that will be received. + This parameter can be a value of + @ref CANFD_data_length_code */ + + uint8_t ESI; /* Specifies the length of the frame that will be received. + This parameter can be a value of + @ref CANFD_data_length_code */ + + uint8_t RES; /* Specifies the length of the frame that will be received. + This parameter can be a value of + @ref CANFD_data_length_code */ + + uint8_t FMI; /* Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanFDRxMsg; + +/* CAN_sleep_constants */ +#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */ + +/* CAN_Mode */ +#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */ + +/* CAN_Operating_Mode */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */ + +/* CAN_Mode_Status */ +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */ + +/* CAN_synchronisation_jump_width */ +#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ + +/* CAN_time_quantum_in_bit_segment_1 */ +#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_time_quantum_in_bit_segment_2 */ +#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ + +/* CAN_filter_mode */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */ + +/* CAN_filter_scale */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */ + +/* CAN_filter_FIFO */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */ + +/* CAN_identifier_type */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */ + +/* CAN_remote_transmission_request */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */ + +/* CAN_transmit_constants */ +#define CAN_TxStatus_Failed ((uint8_t)0x00) /* CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ + +/* CAN_receive_FIFO_number_constants */ +#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */ + +/* CAN_sleep_constants */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */ + +/* CAN_wake_up_constants */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */ + +/* CAN_Error_Code_constants */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */ + +/* CAN_flags */ +/* Transmit Flags */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + * and CAN_ClearFlag() functions. + * If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. +*/ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */ +/* Note: + *When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + *In this case the SLAK bit can be polled. +*/ + + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */ + +/* CAN_interrupts */ +#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + +/* CAN_Legacy */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok + +/* CAN_BS1_Mode */ +#define CAN_BS1_4bit ((uint32_t)0x00000000) +#define CAN_BS1_6bit ((uint32_t)0x00000100) + +/* CANFD_data_length_code */ +#define CANFD_DLC_BYTES_0 ((uint32_t)0x0000) /* 0 bytes data field */ +#define CANFD_DLC_BYTES_1 ((uint32_t)0x0001) /* 1 bytes data field */ +#define CANFD_DLC_BYTES_2 ((uint32_t)0x0002) /* 2 bytes data field */ +#define CANFD_DLC_BYTES_3 ((uint32_t)0x0003) /* 3 bytes data field */ +#define CANFD_DLC_BYTES_4 ((uint32_t)0x0004) /* 4 bytes data field */ +#define CANFD_DLC_BYTES_5 ((uint32_t)0x0005) /* 5 bytes data field */ +#define CANFD_DLC_BYTES_6 ((uint32_t)0x0006) /* 6 bytes data field */ +#define CANFD_DLC_BYTES_7 ((uint32_t)0x0007) /* 7 bytes data field */ +#define CANFD_DLC_BYTES_8 ((uint32_t)0x0008) /* 8 bytes data field */ +#define CANFD_DLC_BYTES_12 ((uint32_t)0x0009) /* 12 bytes data field */ +#define CANFD_DLC_BYTES_16 ((uint32_t)0x000A) /* 16 bytes data field */ +#define CANFD_DLC_BYTES_20 ((uint32_t)0x000B) /* 20 bytes data field */ +#define CANFD_DLC_BYTES_24 ((uint32_t)0x000C) /* 24 bytes data field */ +#define CANFD_DLC_BYTES_32 ((uint32_t)0x000D) /* 32 bytes data field */ +#define CANFD_DLC_BYTES_48 ((uint32_t)0x000E) /* 48 bytes data field */ +#define CANFD_DLC_BYTES_64 ((uint32_t)0x000F) /* 64 bytes data field */ + +/* CANFD_synchronisation_jump_width */ +#define CANFD_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CANFD_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CANFD_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CANFD_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CANFD_SJW_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CANFD_SJW_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CANFD_SJW_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CANFD_SJW_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CANFD_SJW_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CANFD_SJW_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CANFD_SJW_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CANFD_SJW_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CANFD_SJW_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CANFD_SJW_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CANFD_SJW_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CANFD_SJW_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CANFD_time_quantum_in_bit_segment_1 */ +#define CANFD_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CANFD_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CANFD_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CANFD_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CANFD_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CANFD_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CANFD_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CANFD_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CANFD_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CANFD_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CANFD_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CANFD_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CANFD_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CANFD_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CANFD_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CANFD_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ +#define CANFD_BS1_17tq ((uint8_t)0x10) /* 17 time quantum */ +#define CANFD_BS1_18tq ((uint8_t)0x11) /* 18 time quantum */ +#define CANFD_BS1_19tq ((uint8_t)0x12) /* 19 time quantum */ +#define CANFD_BS1_20tq ((uint8_t)0x13) /* 20 time quantum */ +#define CANFD_BS1_21tq ((uint8_t)0x14) /* 21 time quantum */ +#define CANFD_BS1_22tq ((uint8_t)0x15) /* 22 time quantum */ +#define CANFD_BS1_23tq ((uint8_t)0x16) /* 23 time quantum */ +#define CANFD_BS1_24tq ((uint8_t)0x17) /* 24 time quantum */ +#define CANFD_BS1_25tq ((uint8_t)0x18) /* 25 time quantum */ +#define CANFD_BS1_26tq ((uint8_t)0x19) /* 26 time quantum */ +#define CANFD_BS1_27tq ((uint8_t)0x1A) /* 27 time quantum */ +#define CANFD_BS1_28tq ((uint8_t)0x1B) /* 28 time quantum */ +#define CANFD_BS1_29tq ((uint8_t)0x1C) /* 29 time quantum */ +#define CANFD_BS1_30tq ((uint8_t)0x1D) /* 30 time quantum */ +#define CANFD_BS1_31tq ((uint8_t)0x1E) /* 31 time quantum */ +#define CANFD_BS1_32tq ((uint8_t)0x1F) /* 32 time quantum */ + +/* CANFD_time_quantum_in_bit_segment_2 */ +#define CANFD_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CANFD_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CANFD_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CANFD_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CANFD_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CANFD_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CANFD_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CANFD_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CANFD_BS2_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CANFD_BS2_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CANFD_BS2_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CANFD_BS2_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CANFD_BS2_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CANFD_BS2_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CANFD_BS2_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CANFD_BS2_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_Transmit_Mailbox_number_constants */ +#define CAN_Transmit_Mailbox0 ((uint8_t)0x00) +#define CAN_Transmit_Mailbox1 ((uint8_t)0x01) +#define CAN_Transmit_Mailbox2 ((uint8_t)0x02) + + +void CAN_DeInit(CAN_TypeDef *CANx); +uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState); +uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox); +void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage); +void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber); +uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef *CANx); +uint8_t CAN_WakeUp(CAN_TypeDef *CANx); +uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx); +void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT); +void CAN_BS1_ModeConfig(CAN_TypeDef* CANx, uint32_t CAN_BS1_Mode, uint8_t CAN_BS1_tq); +void CAN_BusOff_ErrCntConfig(CAN_TypeDef *CANx, uint8_t BusOff_ErrCnt); +void CANFD_Restrict_ModeCmd(CAN_TypeDef *CANx, FunctionalState NewState); +uint8_t CANFD_Init(CAN_TypeDef *CANx, CANFD_InitTypeDef *CANFD_InitStruct); +void CANFD_StructInit(CANFD_InitTypeDef *CANFD_InitStruct); +uint8_t CANFD_Transmit(CAN_TypeDef *CANx, CanFDTxMsg *TxMessage); +ErrorStatus CANFD_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanFDRxMsg *RxMessage); +uint8_t CANFD_GetTransmitDelayOffsetVal(CAN_TypeDef *CANx); +void CANFD_TransmitMailbox_DMAAdr(CAN_TypeDef *CANx, uint8_t MailboxNumber, uint32_t Address); +void CANFD_ReceiveFIFO_DMAAdr(CAN_TypeDef *CANx, uint8_t FIFONumber, uint32_t Address); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_crc.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_crc.h index 114754c..7aa2f70 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_crc.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_crc.h @@ -1,33 +1,33 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_crc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * CRC firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_CRC_H -#define __CH32L103_CRC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_crc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * CRC firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_CRC_H +#define __CH32L103_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_dbgmcu.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_dbgmcu.h index 4797b18..50409fc 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_dbgmcu.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_dbgmcu.h @@ -1,46 +1,46 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_dbgmcu.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * DBGMCU firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_DBGMCU_H -#define __CH32L103_DBGMCU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) -#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) -#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) - - -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -uint32_t __get_DEBUG_CR(void); -void __set_DEBUG_CR(uint32_t value); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -uint32_t DBGMCU_GetCHIPID( void ); -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_dbgmcu.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * DBGMCU firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_DBGMCU_H +#define __CH32L103_DBGMCU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) + + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +uint32_t __get_DEBUG_CR(void); +void __set_DEBUG_CR(uint32_t value); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +uint32_t DBGMCU_GetCHIPID( void ); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_dma.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_dma.h index 7042b81..bb5638a 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_dma.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_dma.h @@ -1,184 +1,184 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_dma.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * DMA firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_DMA_H -#define __CH32L103_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* DMA Init structure definition */ -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode. - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -} DMA_InitTypeDef; - -/* DMA_data_transfer_direction */ -#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) - -/* DMA_peripheral_incremented_mode */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) - -/* DMA_memory_incremented_mode */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) - -/* DMA_peripheral_data_size */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) - -/* DMA_memory_data_size */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) - -/* DMA_circular_normal_mode */ -#define DMA_Mode_Circular ((uint32_t)0x00000020) -#define DMA_Mode_Normal ((uint32_t)0x00000000) - -/* DMA_priority_level */ -#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) -#define DMA_Priority_High ((uint32_t)0x00002000) -#define DMA_Priority_Medium ((uint32_t)0x00001000) -#define DMA_Priority_Low ((uint32_t)0x00000000) - -/* DMA_memory_to_memory */ -#define DMA_M2M_Enable ((uint32_t)0x00004000) -#define DMA_M2M_Disable ((uint32_t)0x00000000) - -/* DMA_interrupts_definition */ -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) - -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) -#define DMA1_IT_GL8 ((uint32_t)0x10000000) -#define DMA1_IT_TC8 ((uint32_t)0x20000000) -#define DMA1_IT_HT8 ((uint32_t)0x40000000) -#define DMA1_IT_TE8 ((uint32_t)0x80000000) - -/* DMA_flags_definition */ -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) -#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) -#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) -#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) -#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) - -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); -void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); -void DMA_ClearFlag(uint32_t DMAy_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMAy_IT); -void DMA_ClearITPendingBit(uint32_t DMAy_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_dma.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * DMA firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_DMA_H +#define __CH32L103_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) +#define DMA1_IT_GL8 ((uint32_t)0x10000000) +#define DMA1_IT_TC8 ((uint32_t)0x20000000) +#define DMA1_IT_HT8 ((uint32_t)0x40000000) +#define DMA1_IT_TE8 ((uint32_t)0x80000000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) + +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_exti.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_exti.h index 72841bc..536eac8 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_exti.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_exti.h @@ -1,91 +1,90 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_exti.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * EXTI firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_EXTI_H -#define __CH32L103_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* EXTI mode enumeration */ -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -} EXTIMode_TypeDef; - -/* EXTI Trigger enumeration */ -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -} EXTITrigger_TypeDef; - -/* EXTI Init Structure definition */ -typedef struct -{ - uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -} EXTI_InitTypeDef; - -/* EXTI_Lines */ -#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the Tkey Wakeup event */ -#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the USBPD Wakeup event */ -#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */ -#define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the LPTIM Wakeup event */ -#define EXTI_Line22 ((uint32_t)0x400000) /* External interrupt line 22 Connected to the COMP Wakeup event */ - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_exti.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/06 + * Description : This file contains all the functions prototypes for the + * EXTI firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_EXTI_H +#define __CH32L103_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitTypeDef; + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the USBPD Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */ +#define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the LPTIM Wakeup event */ +#define EXTI_Line22 ((uint32_t)0x400000) /* External interrupt line 22 Connected to the COMP Wakeup event */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_flash.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_flash.h index bda3664..134bc22 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_flash.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_flash.h @@ -1,142 +1,142 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_flash.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the FLASH - * firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_FLASH_H -#define __CH32L103_FLASH_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* FLASH Status */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT, - FLASH_RDP, - FLASH_OP_RANGE_ERROR = 0xFD, - FLASH_ALIGN_ERROR = 0xFE, - FLASH_ADR_RANGE_ERROR = 0xFF, -} FLASH_Status; - -/* Flash_Latency */ -#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycle */ - -/* Write Protect 1Sectors = 2KB */ -#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of sector 0 */ -#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of sector 1 */ -#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of sector 2 */ -#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of sector 3 */ -#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of sector 4 */ -#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of sector 5 */ -#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of sector 6 */ -#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of sector 7 */ -#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of sector 8 */ -#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of sector 9 */ -#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of sector 10 */ -#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of sector 11 */ -#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of sector 12 */ -#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of sector 13 */ -#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of sector 14 */ -#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of sector 15 */ -#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of sector 16 */ -#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of sector 17 */ -#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of sector 18 */ -#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of sector 19 */ -#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of sector 20 */ -#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of sector 21 */ -#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of sector 22 */ -#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of sector 23 */ -#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of sector 24 */ -#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of sector 25 */ -#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of sector 26 */ -#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of sector 27 */ -#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of sector 28 */ -#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of sector 29 */ -#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of sector 30 */ -#define FLASH_WRProt_Sectors31 ((uint32_t)0x80000000) /* Write protection of sector 31 */ - -#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ - -/* Option_Bytes_IWatchdog */ -#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ -#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ - -/* Option_Bytes_nRST_STOP */ -#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ - -/* Option_Bytes_nRST_STDBY */ -#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ - -/* Option_Bytes_OB_CAN_BusOff_MODE */ -#define OB_CAN_BusOff_MODE1 ((uint16_t)0x0020) /* Bus off recovery mode1 */ -#define OB_CAN_BusOff_MODE2 ((uint16_t)0x0000) /* Bus off recovery mode2 */ - -/* FLASH_Interrupts */ -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ - -/* FLASH_Flags */ -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ -#define FLASH_FLAG_WAKE_UP ((uint32_t)0x00000040) /* FLASH Wake up of Operation flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ - -/*Functions used for all devices*/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); -FLASH_Status FLASH_EnableReadOutProtection(void); -FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_RST); -uint32_t FLASH_GetUserOptionByte(void); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); -void FLASH_Unlock_Fast(void); -void FLASH_Lock_Fast(void); -void FLASH_BufReset(void); -void FLASH_BufLoad(uint32_t Address, uint32_t Data0); -void FLASH_ErasePage_Fast(uint32_t Page_Address); -void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); -void FLASH_ProgramPage_Fast(uint32_t Page_Address); -FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); -FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_flash.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the FLASH + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_FLASH_H +#define __CH32L103_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_RDP, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycle */ + +/* Write Protect 1Sectors = 2KB */ +#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of sector 0 */ +#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of sector 1 */ +#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of sector 2 */ +#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of sector 3 */ +#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of sector 4 */ +#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of sector 5 */ +#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of sector 6 */ +#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of sector 7 */ +#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of sector 8 */ +#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of sector 9 */ +#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of sector 10 */ +#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of sector 11 */ +#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of sector 12 */ +#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of sector 13 */ +#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of sector 14 */ +#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of sector 15 */ +#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of sector 16 */ +#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of sector 17 */ +#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of sector 18 */ +#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of sector 19 */ +#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of sector 20 */ +#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of sector 21 */ +#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of sector 22 */ +#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of sector 23 */ +#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of sector 24 */ +#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of sector 25 */ +#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of sector 26 */ +#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of sector 27 */ +#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of sector 28 */ +#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of sector 29 */ +#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of sector 30 */ +#define FLASH_WRProt_Sectors31 ((uint32_t)0x80000000) /* Write protection of sector 31 */ + +#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* Option_Bytes_OB_CAN_BusOff_MODE */ +#define OB_CAN_BusOff_MODE1 ((uint16_t)0x0020) /* Bus off recovery mode1 */ +#define OB_CAN_BusOff_MODE2 ((uint16_t)0x0000) /* Bus off recovery mode2 */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WAKE_UP ((uint32_t)0x00000040) /* FLASH Wake up of Operation flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/*Functions used for all devices*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_EnableReadOutProtection(void); +FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_RST); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_BufReset(void); +void FLASH_BufLoad(uint32_t Address, uint32_t Data0); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address); +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_gpio.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_gpio.h index f41baa2..14e2d48 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_gpio.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_gpio.h @@ -1,178 +1,178 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_gpio.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * GPIO firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_GPIO_H -#define __CH32L103_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* Output Maximum frequency selection */ -typedef enum -{ - GPIO_Speed_10MHz = 1, - GPIO_Speed_2MHz, - GPIO_Speed_50MHz -} GPIOSpeed_TypeDef; - -/* Configuration Mode enumeration */ -typedef enum -{ - GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 -} GPIOMode_TypeDef; - -/* GPIO Init structure definition */ -typedef struct -{ - uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -} GPIO_InitTypeDef; - -/* Bit_SET and Bit_RESET enumeration */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -} BitAction; - -/* GPIO_pins_define */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - -/* GPIO_Remap_define */ -//bit[31:30] = 11b - PCFR1-bit[15-0] and PCFR2-bit[26:16] -/* bit[29:27] = 000b */ -#define GPIO_PartialRemap1_SPI1 ((uint32_t)0xC0000001) /* SPI1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_SPI1 ((uint32_t)0xC1000000) /* SPI1 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_SPI1 ((uint32_t)0xC1000001) /* SPI1 Full Alternate Function mapping */ -/* bit[29:27] = 001b */ -#define GPIO_PartialRemap1_I2C1 ((uint32_t)0xC8800000) /* I2C1 Partial1 Alternate Function mapping */ -#define GPIO_FullRemap_I2C1 ((uint32_t)0xC8800002) /* I2C1 Full Alternate Function mapping */ -/* bit[29:27] = 010b */ -#define GPIO_PartialRemap1_USART1 ((uint32_t)0xD0000004) /* USART1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_USART1 ((uint32_t)0xD0080000) /* USART1 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_USART1 ((uint32_t)0xD0080004) /* USART1 Partial3 Alternate Function mapping */ -#define GPIO_PartialRemap4_USART1 ((uint32_t)0xD0100000) /* USART1 Partial4 Alternate Function mapping */ -#define GPIO_FullRemap_USART1 ((uint32_t)0xD0100004) /* USART1 Full Alternate Function mapping */ -/* bit[29:27] = 011b */ -#define GPIO_PartialRemap1_USART2 ((uint32_t)0xD8000008) /* USART2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_USART2 ((uint32_t)0xD8040000) /* USART2 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_USART2 ((uint32_t)0xD8040008) /* USART2 Full Alternate Function mapping */ -/* bit[29:27] = 100b */ -#define GPIO_PartialRemap1_TIM1 ((uint32_t)0xE0000040) /* TIM1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM1 ((uint32_t)0xE0000080) /* TIM1 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_TIM1 ((uint32_t)0xE00000C0) /* TIM1 Partial3 Alternate Function mapping */ -#define GPIO_PartialRemap4_TIM1 ((uint32_t)0xE0400000) /* TIM1 Partial4 Alternate Function mapping */ -#define GPIO_PartialRemap5_TIM1 ((uint32_t)0xE0400040) /* TIM1 Partial5 Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0xE04000C0) /* TIM1 Full Alternate Function mapping */ -/* bit[29:27] = 101b */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0xE8000100) /* TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0xE8000200) /* TIM2 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_TIM2 ((uint32_t)0xE8000300) /* TIM2 Partial3 Alternate Function mapping */ -#define GPIO_PartialRemap4_TIM2 ((uint32_t)0xE8200000) /* TIM2 Partial4 Alternate Function mapping */ -#define GPIO_PartialRemap5_TIM2 ((uint32_t)0xE8200100) /* TIM2 Partial5 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0xE8200300) /* TIM2 Full Alternate Function mapping */ - -//bit[31:30] = 00b - PCFR1 -#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140020) /* USART3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ -#define GPIO_Remap_TIM3 ((uint32_t)0x00000400) /* TIM3 Alternate Function mapping */ -#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ -#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ -#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ -#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ -#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ - -//bit[31:30] = 01b - PCFR2 -#define GPIO_Remap_USART4 ((uint32_t)0x40000001) /* USART4 Alternate Function mapping */ -#define GPIO_Remap_LPTIM ((uint32_t)0x40000200) /* LPTIM Alternate Function mapping */ - -/* GPIO_Port_Sources */ -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOB ((uint8_t)0x01) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) -#define GPIO_PortSourceGPIOD ((uint8_t)0x03) - -/* GPIO_Pin_sources */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - - -void GPIO_DeInit(GPIO_TypeDef *GPIOx); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_EventOutputCmd(FunctionalState NewState); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_IPD_Unused(void); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_gpio.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/03/01 + * Description : This file contains all the functions prototypes for the + * GPIO firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_GPIO_H +#define __CH32L103_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; + +/* Configuration Mode enumeration */ +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +} GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +//bit[31:30] = 11b - PCFR1-bit[15-0] and PCFR2-bit[26:16] +/* bit[29:27] = 000b */ +#define GPIO_PartialRemap1_SPI1 ((uint32_t)0xC0000001) /* SPI1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_SPI1 ((uint32_t)0xC1000000) /* SPI1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_SPI1 ((uint32_t)0xC1000001) /* SPI1 Full Alternate Function mapping */ +/* bit[29:27] = 001b */ +#define GPIO_PartialRemap1_I2C1 ((uint32_t)0xC8800000) /* I2C1 Partial1 Alternate Function mapping */ +#define GPIO_FullRemap_I2C1 ((uint32_t)0xC8800002) /* I2C1 Full Alternate Function mapping */ +/* bit[29:27] = 010b */ +#define GPIO_PartialRemap1_USART1 ((uint32_t)0xD0000004) /* USART1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART1 ((uint32_t)0xD0080000) /* USART1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART1 ((uint32_t)0xD0080004) /* USART1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_USART1 ((uint32_t)0xD0100000) /* USART1 Partial4 Alternate Function mapping */ +#define GPIO_FullRemap_USART1 ((uint32_t)0xD0100004) /* USART1 Full Alternate Function mapping */ +/* bit[29:27] = 011b */ +#define GPIO_PartialRemap1_USART2 ((uint32_t)0xD8000008) /* USART2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART2 ((uint32_t)0xD8040000) /* USART2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART2 ((uint32_t)0xD8040008) /* USART2 Full Alternate Function mapping */ +/* bit[29:27] = 100b */ +#define GPIO_PartialRemap1_TIM1 ((uint32_t)0xE0000040) /* TIM1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM1 ((uint32_t)0xE0000080) /* TIM1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM1 ((uint32_t)0xE00000C0) /* TIM1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM1 ((uint32_t)0xE0400000) /* TIM1 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM1 ((uint32_t)0xE0400040) /* TIM1 Partial5 Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0xE04000C0) /* TIM1 Full Alternate Function mapping */ +/* bit[29:27] = 101b */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0xE8000100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0xE8000200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM2 ((uint32_t)0xE8000300) /* TIM2 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM2 ((uint32_t)0xE8200000) /* TIM2 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM2 ((uint32_t)0xE8200100) /* TIM2 Partial5 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0xE8200300) /* TIM2 Full Alternate Function mapping */ + +//bit[31:30] = 00b - PCFR1 +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140020) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM3 ((uint32_t)0x00000400) /* TIM3 Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* GPIO_Remap_SWJ_Disable - Full SDI Disabled (SDI) */ + +//bit[31:30] = 01b - PCFR2 +#define GPIO_Remap_USART4 ((uint32_t)0x40000001) /* USART4 Alternate Function mapping */ +#define GPIO_Remap_LPTIM ((uint32_t)0x40000200) /* LPTIM Alternate Function mapping */ + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + + +void GPIO_DeInit(GPIO_TypeDef *GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_IPD_Unused(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_i2c.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_i2c.h index 1cb0424..ad253d7 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_i2c.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_i2c.h @@ -1,424 +1,424 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_i2c.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * I2C firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_I2C_H -#define __CH32L103_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* I2C Init structure definition */ -typedef struct -{ - uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /* Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /* Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /* Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -} I2C_InitTypeDef; - -/* I2C_mode */ -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) - -/* I2C_duty_cycle_in_fast_mode */ -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ - -/* I2C_acknowledgement */ -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) - -/* I2C_transfer_direction */ -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) - -/* I2C_acknowledged_address */ -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) - -/* I2C_registers */ -#define I2C_Register_CTLR1 ((uint8_t)0x00) -#define I2C_Register_CTLR2 ((uint8_t)0x04) -#define I2C_Register_OADDR1 ((uint8_t)0x08) -#define I2C_Register_OADDR2 ((uint8_t)0x0C) -#define I2C_Register_DATAR ((uint8_t)0x10) -#define I2C_Register_STAR1 ((uint8_t)0x14) -#define I2C_Register_STAR2 ((uint8_t)0x18) -#define I2C_Register_CKCFGR ((uint8_t)0x1C) -#define I2C_Register_RTR ((uint8_t)0x20) - -/* I2C_SMBus_alert_pin_level */ -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) - -/* I2C_PEC_position */ -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) - -/* I2C_NACK_position */ -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) - -/* I2C_interrupts_definition */ -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) - -/* I2C_interrupts_definition */ -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -/* SR2 register flags */ -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/* SR1 register flags */ -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -/****************I2C Master Events (Events grouped in order of communication)********************/ - -/******************************************************************************************************************** - * @brief Start communicate - * - * After master use I2C_GenerateSTART() function sending the START condition,the master - * has to wait for event 5(the Start condition has been correctly - * released on the I2C bus ). - * - */ -/* EVT5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/******************************************************************************************************************** - * @brief Address Acknowledge - * - * When start condition correctly released on the bus(check EVT5), the - * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate - * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will be set: - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (after generating the START - * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. - * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent - * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part - * of the 10-bit address (LSB) . Then master should wait for event 6. - * - * - */ - -/* EVT6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* EVT9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/******************************************************************************************************************** - * @brief Communication events - * - * If START condition has generated and slave address - * been acknowledged. then the master has to check one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EVT7 then use - * I2C_ReceiveData() function to read the data received from the slave. - * - * 2) Master Transmitter mode: The master use I2C_SendData() function to send data - * then to wait on event EVT8 or EVT8_2. - * These two events are similar: - * - EVT8 means that the data has been written in the data register and is - * being shifted out. - * - EVT8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EVT8 is sufficient for the application. - * Using EVT8_2 will leads to a slower communication speed but will more reliable . - * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission - * - * Note: - * In case the user software does not guarantee that this event EVT7 is managed before - * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. - * - * - */ - -/* Master Receive mode */ -/* EVT7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master Transmitter mode*/ -/* EVT8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* EVT8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - -/******************I2C Slave Events (Events grouped in order of communication)******************/ - -/******************************************************************************************************************** - * @brief Start Communicate events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a start condition of master device generate on the bus. - * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. - * - * a) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * b) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * c) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* EVT1 */ -/* a) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* b) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* c) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/******************************************************************************************************************** - * @brief Communication events - * - * Wait on one of these events when EVT1 has already been checked : - * - * - Slave Receiver mode: - * - EVT2--The device is expecting to receive a data byte . - * - EVT4--The device is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EVT3--When a byte has been transmitted by the slave and the Master is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee - * the EVT3 is managed before the current byte end of transfer The second one can optionally - * be used. - * - EVT3_2--When the master sends a NACK to tell slave device that data transmission - * shall end . The slave device has to stop sending - * data bytes and wait a Stop condition from bus. - * - * Note: - * If the user software does not guarantee that the event 2 is - * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time . - * In this case the communication will be slower. - * - */ - -/* Slave Receiver mode*/ -/* EVT2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* EVT4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave Transmitter mode*/ -/* EVT3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* EVT3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - - -void I2C_DeInit(I2C_TypeDef *I2Cx); -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); -void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); -void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert); -void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); -void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); - - -/***************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * profit the application requirements and constraints: - * - * - * a) First way: - * Using I2C_CheckEvent() function: - * It compares the status registers (STARR1 and STAR2) content to a given event - * (can be the combination of more flags). - * If the current status registers includes the given flags will return SUCCESS. - * and if the current status registers miss flags will returns ERROR. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (CH32FV2x-V3xRM). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs besides to the monitored error, - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * in corrupted state. it is suggeted to use error interrupts to monitor the error - * events and handle them in IRQ handler. - * - * - * Note: - * The following functions are recommended for error management: : - * - I2C_ITConfig() main function of configure and enable the error interrupts. - * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions - * to determine which error occurred. - * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() - * \ I2C_GenerateStop() will be use to clear the error flag and source, - * and return to correct communication status. - * - * - * b) Second way: - * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. - * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). - * - When to use: - * - * - This function is suitable for the same applications above but it - * don't have the limitations of I2C_GetFlagStatus() function . - * The returned value could be compared to events already defined in the - * library (CH32L103_i2c.h) or to custom values defined by user. - * - This function can be used to monitor the status of multiple flags simultaneously. - * - Contrary to the I2C_CheckEvent () function, this function can choose the time to - * accept the event according to the user's needs (when all event flags are set and - * no other flags are set, or only when the required flags are set) - * - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * c) Third way: - * Using the function I2C_GetFlagStatus() get the status of - * one single flag . - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed . - * - * - Limitations: - * - Call this function to access the status register. Some flag bits may be cleared. - * - Function may need to be called twice or more in order to monitor one single event. - */ - - - -/********************************************************* - * - * a) Basic state monitoring(First way) - ******************************************************** - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/********************************************************* - * - * b) Advanced state monitoring(Second way) - ******************************************************** - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/********************************************************* - * - * c) Flag-based state monitoring(Third way) - ********************************************************* - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - -void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_i2c.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * I2C firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_I2C_H +#define __CH32L103_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* STAR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* STAR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave. + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef *I2Cx); +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); + + +/***************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * profit the application requirements and constraints: + * + * + * a) First way: + * Using I2C_CheckEvent() function: + * It compares the status registers (STARR1 and STAR2) content to a given event + * (can be the combination of more flags). + * If the current status registers includes the given flags will return SUCCESS. + * and if the current status registers miss flags will returns ERROR. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (CH32FV2x-V3xRM). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs besides to the monitored error, + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * in corrupted state. it is suggeted to use error interrupts to monitor the error + * events and handle them in IRQ handler. + * + * + * Note: + * The following functions are recommended for error management: : + * - I2C_ITConfig() main function of configure and enable the error interrupts. + * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions + * to determine which error occurred. + * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() + * \ I2C_GenerateStop() will be use to clear the error flag and source, + * and return to correct communication status. + * + * + * b) Second way: + * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. + * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). + * - When to use: + * + * - This function is suitable for the same applications above but it + * don't have the limitations of I2C_GetFlagStatus() function . + * The returned value could be compared to events already defined in the + * library (CH32L103_i2c.h) or to custom values defined by user. + * - This function can be used to monitor the status of multiple flags simultaneously. + * - Contrary to the I2C_CheckEvent () function, this function can choose the time to + * accept the event according to the user's needs (when all event flags are set and + * no other flags are set, or only when the required flags are set) + * + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * c) Third way: + * Using the function I2C_GetFlagStatus() get the status of + * one single flag . + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed . + * + * - Limitations: + * - Call this function to access the status register. Some flag bits may be cleared. + * - Function may need to be called twice or more in order to monitor one single event. + */ + + + +/********************************************************* + * + * a) Basic state monitoring(First way) + ******************************************************** + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/********************************************************* + * + * b) Advanced state monitoring(Second way) + ******************************************************** + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/********************************************************* + * + * c) Flag-based state monitoring(Third way) + ********************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_iwdg.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_iwdg.h index b72715d..069731d 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_iwdg.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_iwdg.h @@ -1,50 +1,50 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_iwdg.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * IWDG firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_IWDG_H -#define __CH32L103_IWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* IWDG_WriteAccess */ -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) - -/* IWDG_prescaler */ -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) - -/* IWDG_Flag */ -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) - -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_Enable(void); -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_iwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * IWDG firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_IWDG_H +#define __CH32L103_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_lptim.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_lptim.h index 00f7517..fd3e619 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_lptim.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_lptim.h @@ -1,194 +1,200 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_lptim.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * TIM firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32L103_LPTIM_H -#define __CH32L103_LPTIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -typedef struct -{ - uint32_t LPTIM_ClockSource; /* Selects the clock source. - This parameter can be a value of @ref LPTIM_Clock_Source */ - - union{ - uint32_t LPTIM_ClockPolarity; /* Configures Clock Polarity(No Encoder mode). - This parameter can be a value of @ref LPTIM_ClockPolarity */ - - uint32_t LPTIM_EncoderMode; /* Configures Encoder mode. - This parameter can be a value of @ref LPTIM_EncoderMode */ - }; - - uint32_t LPTIM_ClockSampleTime; /* Configures Clock Sample Time. - This parameter can be a value of @ref LPTIM_ClockSampleTime */ - - uint32_t LPTIM_TriggerSampleTime; /* Configures Trigger Sample Time. - This parameter can be a value of @ref LPTIM_TriggerSampleTime */ - - uint32_t LPTIM_ClockPrescaler; /* Configures the clock Prescaler. - This parameter can be a value of @ref LPTIM_ClockPrescaler */ - - uint32_t LPTIM_TriggerSource; /* Configures trigger source. - This parameter can be a value of @ref LPTIM_TriggerSource */ - - uint32_t LPTIM_ExTriggerPolarity; /* Configures external trigger polarity. - This parameter can be a value of @ref LPTIM_ExTriggerPolarity */ - - FunctionalState LPTIM_TimeOut; /* Specifies whether the time out function. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState LPTIM_OnePulseMode; /* Specifies whether the PWM out one pulse. - This parameter can be set to ENABLE or DISABLE */ - - uint32_t LPYIM_OutputPolarity; /* Configures output polarity. - This parameter can be a value of @ref LPYIM_OutputPolarity */ - - uint32_t LPYIM_UpdateMode; /* Configures update mode. - This parameter can be a value of @ref LPYIM_UpdateMode */ - - uint32_t LPTIM_CountSource; /* Configures Counter Source. - This parameter can be a value of @ref LPTIM_CountSource */ - - FunctionalState LPTIM_Encoder; /* Specifies whether open Encoder function. - This parameter can be set to ENABLE or DISABLE */ - - uint32_t LPTIM_InClockSource; /* Specifies Internal clock source. - This parameter can be a value of @ref LPTIM_InClockSource */ - - FunctionalState LPTIM_ForceOutHigh; /* Specifies whether the PWM out high level. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState LPTIM_SingleMode; /* Specifies whether single mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState LPTIM_ContinuousMode; /* Specifies whether continuous mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState LPTIM_PWMOut; /* Specifies whether PWM out function. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState LPTIM_CounterDirIndicat; /* Specifies whether counter direction indicate function. - This parameter can be set to ENABLE or DISABLE */ - - uint16_t LPTIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t LPTIM_Period; /* Specifies the period value to be loaded into the active - This parameter must be a number between 0x0000 and 0xFFFF. */ -} LPTIM_TimeBaseInitTypeDef; - - -/* LPTIM_Clock_Source */ -#define LPTIM_ClockSource_In ((uint32_t)0x00000000) -#define LPTIM_ClockSource_Ex ((uint32_t)0x00000001) - -/* LPTIM_ClockPolarity */ -#define LPTIM_ClockPolarity_Rising ((uint32_t)0x00000000) -#define LPTIM_ClockPolarity_Falling ((uint32_t)0x00000002) -#define LPTIM_ClockPolarity_Rising_Falling ((uint32_t)0x00000004) - -/* LPTIM_ClockPrescalerTime */ -#define LPTIM_ClockSampleTime_0T ((uint32_t)0x00000000) -#define LPTIM_ClockSampleTime_2T ((uint32_t)0x00000008) -#define LPTIM_ClockSampleTime_4T ((uint32_t)0x00000010) -#define LPTIM_ClockSampleTime_8T ((uint32_t)0x00000018) - -/* LPTIM_TriggerSampleTime */ -#define LPTIM_TriggerSampleTime_0T ((uint32_t)0x00000000) -#define LPTIM_TriggerSampleTime_2T ((uint32_t)0x00000040) -#define LPTIM_TriggerSampleTime_4T ((uint32_t)0x00000080) -#define LPTIM_TriggerSampleTime_8T ((uint32_t)0x000000C0) - -/* LPTIM_ClockPrescaler */ -#define LPTIM_TClockPrescaler_DIV1 ((uint32_t)0x00000000) -#define LPTIM_TClockPrescaler_DIV2 ((uint32_t)0x00000200) -#define LPTIM_TClockPrescaler_DIV4 ((uint32_t)0x00000400) -#define LPTIM_TClockPrescaler_DIV8 ((uint32_t)0x00000600) -#define LPTIM_TClockPrescaler_DIV16 ((uint32_t)0x00000800) -#define LPTIM_TClockPrescaler_DIV32 ((uint32_t)0x00000A00) -#define LPTIM_TClockPrescaler_DIV64 ((uint32_t)0x00000C00) -#define LPTIM_TClockPrescaler_DIV128 ((uint32_t)0x00000E00) - -/* LPTIM_TriggerSource */ -#define LPTIM_TriggerSource_ETR ((uint32_t)0x00000000) -#define LPTIM_TriggerSource_RTC_ALARM ((uint32_t)0x00002000) -#define LPTIM_TriggerSource_TAMP ((uint32_t)0x00004000) - -/* LPTIM_ExTriggerPolarity */ -#define LPTIM_ExTriggerPolarity_Disable ((uint32_t)0x00000000) -#define LPTIM_ExTriggerPolarity_Rising ((uint32_t)0x00020000) -#define LPTIM_ExTriggerPolarity_Falling ((uint32_t)0x00040000) -#define LPTIM_ExTriggerPolarity_Rising_Falling ((uint32_t)0x00060000) - -/* LPYIM_OutputPolarity */ -#define LPYIM_OutputPolarity_High ((uint32_t)0x00000000) -#define LPYIM_OutputPolarity_Low ((uint32_t)0x00200000) - -/* LPYIM_UpdateMode */ -#define LPYIM_UpdateMode0 ((uint32_t)0x00000000) -#define LPYIM_UpdateMode1 ((uint32_t)0x00400000) - -/* LPTIM_CountSource */ -#define LPTIM_CountSource_Internal ((uint32_t)0x00000000) -#define LPTIM_CountSource_External ((uint32_t)0x00800000) - -/* LPTIM_InClockSource */ -#define LPTIM_InClockSource_PCLK1 ((uint32_t)0x00000000) -#define LPTIM_InClockSource_HSI ((uint32_t)0x02000000) -#define LPTIM_InClockSource_LSE ((uint32_t)0x04000000) -#define LPTIM_InClockSource_LSI ((uint32_t)0x06000000) - -/* LPTIM_Flag_Definition */ -#define LPTIM_FLAG_DIR_SYNC ((uint32_t)0x00000080) -#define LPTIM_FLAG_DOWN ((uint32_t)0x00000040) -#define LPTIM_FLAG_UP ((uint32_t)0x00000020) -#define LPTIM_FLAG_ARROK ((uint32_t)0x00000010) -#define LPTIM_FLAG_CMPOK ((uint32_t)0x00000008) -#define LPTIM_FLAG_EXTTRIG ((uint32_t)0x00000004) -#define LPTIM_FLAG_ARRM ((uint32_t)0x00000002) -#define LPTIM_FLAG_CMPM ((uint32_t)0x00000001) - -/* LPTIM_Interrupts_Definition */ -#define LPTIM_IT_DOWN ((uint32_t)0x00000040) -#define LPTIM_IT_UP ((uint32_t)0x00000020) -#define LPTIM_IT_ARROK ((uint32_t)0x00000010) -#define LPTIM_IT_CMPOK ((uint32_t)0x00000008) -#define LPTIM_IT_EXTTRIG ((uint32_t)0x00000004) -#define LPTIM_IT_ARRM ((uint32_t)0x00000002) -#define LPTIM_IT_CMPM ((uint32_t)0x00000001) - - -void LPTIM_DeInit(void); -void LPTIM_TimeBaseInit(LPTIM_TimeBaseInitTypeDef* LPTIM_TimeBaseInitStruct); -void LPTIM_TimeBaseStructInit(LPTIM_TimeBaseInitTypeDef* LPTIM_TimeBaseInitStruct); -void LPTIM_CounterDirIndicat_Cmd(FunctionalState NewState); -void LPTIM_OutCmd(FunctionalState NewState); -void LPTIM_Cmd(FunctionalState NewState); -uint16_t LPTIM_GetCounter(void); -void LPTIM_SetAutoreload(uint16_t Autoreload); -void LPTIM_SetCompare(uint16_t Compare); -void LPTIM_ITConfig(uint32_t LPTIM_IT, FunctionalState NewState); -FlagStatus LPTIM_GetFlagStatus(uint32_t LPTIM_FLAG); -void LPTIM_ClearFlag(uint32_t LPTIM_FLAG); -ITStatus LPTIM_GetITStatus(uint32_t LPTIM_IT); -void LPTIM_ClearITPendingBit(uint32_t LPTIM_IT); - - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_lptim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/07/15 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32L103_LPTIM_H +#define __CH32L103_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +typedef struct +{ + uint32_t LPTIM_ClockSource; /* Selects the clock source. + This parameter can be a value of @ref LPTIM_Clock_Source */ + + union{ + uint32_t LPTIM_ClockPolarity; /* Configures Clock Polarity(No Encoder mode). + This parameter can be a value of @ref LPTIM_ClockPolarity */ + + uint32_t LPTIM_EncoderMode; /* Configures Encoder mode. + This parameter can be a value of @ref LPTIM_EncoderMode */ + }; + + uint32_t LPTIM_ClockSampleTime; /* Configures Clock Sample Time. + This parameter can be a value of @ref LPTIM_ClockSampleTime */ + + uint32_t LPTIM_TriggerSampleTime; /* Configures Trigger Sample Time. + This parameter can be a value of @ref LPTIM_TriggerSampleTime */ + + uint32_t LPTIM_ClockPrescaler; /* Configures the clock Prescaler. + This parameter can be a value of @ref LPTIM_ClockPrescaler */ + + uint32_t LPTIM_TriggerSource; /* Configures trigger source. + This parameter can be a value of @ref LPTIM_TriggerSource */ + + uint32_t LPTIM_ExTriggerPolarity; /* Configures external trigger polarity. + This parameter can be a value of @ref LPTIM_ExTriggerPolarity */ + + FunctionalState LPTIM_TimeOut; /* Specifies whether the time out function. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_OnePulseMode; /* Specifies whether the PWM out one pulse. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t LPTIM_OutputPolarity; /* Configures output polarity. + This parameter can be a value of @ref LPTIM_OutputPolarity */ + + uint32_t LPTIM_UpdateMode; /* Configures update mode. + This parameter can be a value of @ref LPTIM_UpdateMode */ + + uint32_t LPTIM_CountSource; /* Configures Counter Source. + This parameter can be a value of @ref LPTIM_CountSource */ + + FunctionalState LPTIM_Encoder; /* Specifies whether open Encoder function. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t LPTIM_InClockSource; /* Specifies Internal clock source. + This parameter can be a value of @ref LPTIM_InClockSource */ + + FunctionalState LPTIM_ForceOutHigh; /* Specifies whether the PWM out high level. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_SingleMode; /* Specifies whether single mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_ContinuousMode; /* Specifies whether continuous mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_PWMOut; /* Specifies whether PWM out function. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState LPTIM_CounterDirIndicat; /* Specifies whether counter direction indicate function. + This parameter can be set to ENABLE or DISABLE */ + + uint16_t LPTIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t LPTIM_Period; /* Specifies the period value to be loaded into the active + This parameter must be a number between 0x0000 and 0xFFFF. */ +} LPTIM_TimeBaseInitTypeDef; + + +/* LPTIM_Clock_Source */ +#define LPTIM_ClockSource_In ((uint32_t)0x00000000) +#define LPTIM_ClockSource_Ex ((uint32_t)0x00000001) + +/* LPTIM_ClockPolarity */ +#define LPTIM_ClockPolarity_Rising ((uint32_t)0x00000000) +#define LPTIM_ClockPolarity_Falling ((uint32_t)0x00000002) +#define LPTIM_ClockPolarity_Rising_Falling ((uint32_t)0x00000004) + +/* LPTIM_ClockPrescalerTime */ +#define LPTIM_ClockSampleTime_0T ((uint32_t)0x00000000) +#define LPTIM_ClockSampleTime_2T ((uint32_t)0x00000008) +#define LPTIM_ClockSampleTime_4T ((uint32_t)0x00000010) +#define LPTIM_ClockSampleTime_8T ((uint32_t)0x00000018) + +/* LPTIM_TriggerSampleTime */ +#define LPTIM_TriggerSampleTime_0T ((uint32_t)0x00000000) +#define LPTIM_TriggerSampleTime_2T ((uint32_t)0x00000040) +#define LPTIM_TriggerSampleTime_4T ((uint32_t)0x00000080) +#define LPTIM_TriggerSampleTime_8T ((uint32_t)0x000000C0) + +/* LPTIM_ClockPrescaler */ +#define LPTIM_TClockPrescaler_DIV1 ((uint32_t)0x00000000) +#define LPTIM_TClockPrescaler_DIV2 ((uint32_t)0x00000200) +#define LPTIM_TClockPrescaler_DIV4 ((uint32_t)0x00000400) +#define LPTIM_TClockPrescaler_DIV8 ((uint32_t)0x00000600) +#define LPTIM_TClockPrescaler_DIV16 ((uint32_t)0x00000800) +#define LPTIM_TClockPrescaler_DIV32 ((uint32_t)0x00000A00) +#define LPTIM_TClockPrescaler_DIV64 ((uint32_t)0x00000C00) +#define LPTIM_TClockPrescaler_DIV128 ((uint32_t)0x00000E00) + +/* LPTIM_TriggerSource */ +#define LPTIM_TriggerSource_ETR ((uint32_t)0x00000000) +#define LPTIM_TriggerSource_RTC_ALARM ((uint32_t)0x00002000) +#define LPTIM_TriggerSource_TAMP ((uint32_t)0x00004000) + +/* LPTIM_ExTriggerPolarity */ +#define LPTIM_ExTriggerPolarity_Disable ((uint32_t)0x00000000) +#define LPTIM_ExTriggerPolarity_Rising ((uint32_t)0x00020000) +#define LPTIM_ExTriggerPolarity_Falling ((uint32_t)0x00040000) +#define LPTIM_ExTriggerPolarity_Rising_Falling ((uint32_t)0x00060000) + +/* LPTIM_OutputPolarity */ +#define LPTIM_OutputPolarity_High ((uint32_t)0x00000000) +#define LPTIM_OutputPolarity_Low ((uint32_t)0x00200000) + +/* LPTIM_UpdateMode */ +#define LPTIM_UpdateMode0 ((uint32_t)0x00000000) +#define LPTIM_UpdateMode1 ((uint32_t)0x00400000) + +/* LPTIM_CountSource */ +#define LPTIM_CountSource_Internal ((uint32_t)0x00000000) +#define LPTIM_CountSource_External ((uint32_t)0x00800000) + +/* LPTIM_InClockSource */ +#define LPTIM_InClockSource_PCLK1 ((uint32_t)0x00000000) +#define LPTIM_InClockSource_HSI ((uint32_t)0x02000000) +#define LPTIM_InClockSource_LSE ((uint32_t)0x04000000) +#define LPTIM_InClockSource_LSI ((uint32_t)0x06000000) + +/* LPTIM_Flag_Definition */ +#define LPTIM_FLAG_DIR_SYNC ((uint32_t)0x00000080) +#define LPTIM_FLAG_DOWN ((uint32_t)0x00000040) +#define LPTIM_FLAG_UP ((uint32_t)0x00000020) +#define LPTIM_FLAG_ARROK ((uint32_t)0x00000010) +#define LPTIM_FLAG_CMPOK ((uint32_t)0x00000008) +#define LPTIM_FLAG_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_FLAG_ARRM ((uint32_t)0x00000002) +#define LPTIM_FLAG_CMPM ((uint32_t)0x00000001) + +/* LPTIM_Interrupts_Definition */ +#define LPTIM_IT_DOWN ((uint32_t)0x00000040) +#define LPTIM_IT_UP ((uint32_t)0x00000020) +#define LPTIM_IT_ARROK ((uint32_t)0x00000010) +#define LPTIM_IT_CMPOK ((uint32_t)0x00000008) +#define LPTIM_IT_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_IT_ARRM ((uint32_t)0x00000002) +#define LPTIM_IT_CMPM ((uint32_t)0x00000001) + + +#define LPYIM_OutputPolarity_High LPTIM_OutputPolarity_High +#define LPYIM_OutputPolarity_Low LPTIM_OutputPolarity_Low +#define LPYIM_UpdateMode0 LPTIM_UpdateMode0 +#define LPYIM_UpdateMode1 LPTIM_UpdateMode1 + + +void LPTIM_DeInit(void); +void LPTIM_TimeBaseInit(LPTIM_TimeBaseInitTypeDef* LPTIM_TimeBaseInitStruct); +void LPTIM_TimeBaseStructInit(LPTIM_TimeBaseInitTypeDef* LPTIM_TimeBaseInitStruct); +void LPTIM_CounterDirIndicat_Cmd(FunctionalState NewState); +void LPTIM_OutCmd(FunctionalState NewState); +void LPTIM_Cmd(FunctionalState NewState); +uint16_t LPTIM_GetCounter(void); +void LPTIM_SetAutoreload(uint16_t Autoreload); +void LPTIM_SetCompare(uint16_t Compare); +void LPTIM_ITConfig(uint32_t LPTIM_IT, FunctionalState NewState); +FlagStatus LPTIM_GetFlagStatus(uint32_t LPTIM_FLAG); +void LPTIM_ClearFlag(uint32_t LPTIM_FLAG); +ITStatus LPTIM_GetITStatus(uint32_t LPTIM_IT); +void LPTIM_ClearITPendingBit(uint32_t LPTIM_IT); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_misc.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_misc.h index 15cd9f9..304a892 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_misc.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_misc.h @@ -1,72 +1,72 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_misc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/12/26 - * Description : This file contains all the functions prototypes for the - * miscellaneous firmware library functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_MISC_H -#define __CH32L103_MISC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* CSR_INTSYSCR_INEST_definition */ -#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ -#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ - -/* Check the configuration of CSR(0x804) in the startup file(.S) - * interrupt nesting enable(CSR-0x804 bit1 = 1) - * priority - bit[7] - Preemption Priority - * bit[6:5] - Sub priority - * bit[4:0] - Reserve - * interrupt nesting disable(CSR-0x804 bit1 = 0) - * priority - bit[7:5] - Sub priority - * bit[4:0] - Reserve - */ - -#ifndef INTSYSCR_INEST -#define INTSYSCR_INEST INTSYSCR_INEST_EN -#endif - -/* NVIC Init Structure definition - * interrupt nesting enable(CSR-0x804 bit1 = 1) - * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. - * NVIC_IRQChannelSubPriority - range from 0 to 3. - * - * interrupt nesting disable(CSR-0x804 bit1 = 0) - * NVIC_IRQChannelPreemptionPriority - range is 0. - * NVIC_IRQChannelSubPriority - range from 0 to 7. - * - */ -typedef struct -{ - uint8_t NVIC_IRQChannel; - uint8_t NVIC_IRQChannelPreemptionPriority; - uint8_t NVIC_IRQChannelSubPriority; - FunctionalState NVIC_IRQChannelCmd; -} NVIC_InitTypeDef; - -/* Preemption_Priority_Group */ -#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) -#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ -#else -#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ -#endif - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_misc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : This file contains all the functions prototypes for the + * miscellaneous firmware library functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_MISC_H +#define __CH32L103_MISC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* CSR_INTSYSCR_INEST_definition */ +#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ + +/* Check the configuration of CSR(0x804) in the startup file(.S) + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + */ + +#ifndef INTSYSCR_INEST +#define INTSYSCR_INEST INTSYSCR_INEST_EN +#endif + +/* NVIC Init Structure definition + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Preemption_Priority_Group */ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#else +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ +#endif + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_opa.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_opa.h index daf0222..af06f86 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_opa.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_opa.h @@ -1,220 +1,243 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_opa.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * OPA firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_OPA_H -#define __CH32L103_OPA_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* OPA_member_enumeration */ -typedef enum -{ - OPA1 = 0, -} OPA_Num_TypeDef; - -/* OPA_out_channel_enumeration */ -typedef enum -{ - OUT_IO_OUT0 = 0, /* PA3 */ - OUT_IO_OUT1, /* PB1 */ - OUT_IO_OUT2, /* PA2 */ - OUT_IO_OUT3, /* PA4 */ - OUT_IO_OUT4, /* PB0 */ - OUT_IO_OFF -} OPA_Mode_TypeDef; - -/* OPA_PSEL_enumeration */ -typedef enum -{ - CHP0 = 0, /* PB15 */ - CHP1, /* PB0 */ - CHP2, /* PB14 */ - CHP3, /* PA7 */ - CHP4, /* PA0 */ - CHP5, /* PA6 */ - CHP_OFF -} OPA_PSEL_TypeDef; - -/* OPA_FB_enumeration */ -typedef enum -{ - FB_OFF = 0, - FB_ON -} OPA_FB_TypeDef; - -/* OPA_NSEL_enumeration */ -typedef enum -{ - CHN0 = 0, /* PB11 */ - CHN1, /* PA6 */ - CHN2, /* PB10 */ - CHN3, /* PA5 */ - CHN4, /* PA1 */ - CHN5, /* PA7 */ - CHN2_PGA_32xIN, /* PB10 */ - CHN_PGA_8xIN, - CHN_PGA_16xIN, - CHN_PGA_32xIN, - CHN_PGA_64xIN, - CHN_OFF = 0xF -} OPA_NSEL_TypeDef; - -/* OPA_PSEL_POLL_enumeration */ -typedef enum -{ - CHP_OPA1_OFF = 0, - CHP_OPA1_ON, -} OPA_PSEL_POLL_TypeDef; - -/* OPA_BKIN_EN_enumeration */ -typedef enum -{ - BKIN_OPA1_OFF = 0, /* TIM1 braking signal source form IO input */ - BKIN_OPA1_ON, /* TIM1 braking signal source form OPA output */ -} OPA_BKIN_EN_TypeDef; - -/* OPA_RST_EN_enumeration */ -typedef enum -{ - RST_OPA1_OFF = 0, - RST_OPA1_ON, -} OPA_RST_EN_TypeDef; - -/* OPA_OUT_IE_enumeration */ -typedef enum -{ - OUT_IE_OPA1_OFF = 0, - OUT_IE_OPA1_ON, -} OPA_OUT_IE_TypeDef; - -/* OPA_CNT_IE_enumeration */ -typedef enum -{ - CNT_IE_OFF = 0, - CNT_IE_ON, -} OPA_CNT_IE_TypeDef; - -/* OPA_NMI_IE_enumeration */ -typedef enum -{ - NMI_IE_OFF = 0, - NMI_IE_ON, -} OPA_NMI_IE_TypeDef; - -/* OPA_PSEL_POLL_NUM_enumeration */ -typedef enum -{ - CHP_POLL_NUM_1 = 0, - CHP_POLL_NUM_2, - CHP_POLL_NUM_3, - CHP_POLL_NUM_4, - CHP_POLL_NUM_5, - CHP_POLL_NUM_6 -} OPA_PSEL_POLL_NUM_TypeDef; - -/* Offset_voltage_adjustment_value_polarity */ -typedef enum -{ - OPA_Vos_Ads_N = 0, - OPA_Vos_Ads_P -} OPA_Vos_ADS_POLARITY_TypeDef; - -/* OPA Init Structure definition */ -typedef struct -{ - uint16_t OPA_POLL_Interval; /* OPA polling interval = (OPA_POLL_Interval+1)*1us - This parameter must range from 0 to 0x1FF.*/ - OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ - OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ - OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ - OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ - OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ - OPA_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of OPA */ - OPA_BKIN_EN_TypeDef BKIN_EN; /* Specifies the brake input source of OPA */ - OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */ - OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */ - OPA_CNT_IE_TypeDef CNT_IE; /* Specifies the out interrupt rising edge of sampling data */ - OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NIM interrupt of OPA */ - OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of forward inputs*/ -} OPA_InitTypeDef; - -/* CMP_member_enumeration */ -typedef enum -{ - CMP1 = 0, - CMP2, - CMP3 -} CMP_Num_TypeDef; - -/* CMP_out_channel_enumeration */ -typedef enum -{ - OUT_IO0 = 0, - OUT_IO1, - OUT_IO_TIM2 -} CMP_Mode_TypeDef; - -/* CMP_NSEL_enumeration */ -typedef enum -{ - CMP_CHN0 = 0, - CMP_CHN1, -} CMP_NSEL_TypeDef; - -/* CMP_PSEL_enumeration */ -typedef enum -{ - CMP_CHP1 = 0, - CMP_CHP2, -} CMP_PSEL_TypeDef; - -/* CMP Init Structure definition */ -typedef struct -{ - CMP_Num_TypeDef CMP_NUM; /* Specifies the members of CMP */ - CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */ - CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ - CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ -} CMP_InitTypeDef; - -/* OPA_flags_definition */ -#define OPA_FLAG_OUT_OPA1 ((uint16_t)0x1000) -#define OPA_FLAG_OUT_CNT ((uint16_t)0x4000) - -/* CMP_WakeUp_IO_mode_definition */ -#define CMP_WakeUp_Rising_Falling ((uint32_t)0x01000000) -#define CMP_WakeUp_Rising ((uint32_t)0x02000000) -#define CMP_WakeUp_Falling ((uint32_t)0x03000000) - -void OPCM_Unlock(void); -void OPCM_Lock(void); -void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); -void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); -void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); -void OPA_LP_Cmd(FunctionalState NewState); -void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct); -void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct); -void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); -void OPA_CMP_LP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); -void OPA_CMP_WakeUp_ModeConfig(uint32_t CMP_WakeUP_Mode); -FlagStatus OPA_GetFlagStatus( uint16_t OPA_FLAG); -void OPA_ClearFlag(uint16_t OPA_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_opa.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/05 + * Description : This file contains all the functions prototypes for the + * OPA firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_OPA_H +#define __CH32L103_OPA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* OPA_member_enumeration */ +typedef enum +{ + OPA1 = 0, +} OPA_Num_TypeDef; + +/* OPA_out_channel_enumeration */ +typedef enum +{ + OUT_IO_OUT0 = 0, /* PA3 */ + OUT_IO_OUT1, /* PB1 */ + OUT_IO_OUT2, /* PA2 */ + OUT_IO_OUT3, /* PA4 */ + OUT_IO_OUT4, /* PB0 */ + OUT_IO_OFF +} OPA_Mode_TypeDef; + +/* OPA_PSEL_enumeration */ +typedef enum +{ + CHP0 = 0, /* PB15 */ + CHP1, /* PB0 */ + CHP2, /* PB14 */ + CHP3, /* PA7 */ + CHP4, /* PA0 */ + CHP5, /* PA6 */ + CHP_OFF +} OPA_PSEL_TypeDef; + +/* OPA_FB_enumeration */ +typedef enum +{ + FB_OFF = 0, + FB_ON +} OPA_FB_TypeDef; + +/* OPA_NSEL_enumeration */ +typedef enum +{ + CHN0 = 0, /* PB11 */ + CHN1, /* PA6 */ + CHN2, /* PB10 */ + CHN3, /* PA5 */ + CHN4, /* PA1 */ + CHN5, /* PA7 */ + CHN2_PGA_32xIN, /* PB10 */ + CHN_PGA_8xIN, + CHN_PGA_16xIN, + CHN_PGA_32xIN, + CHN_PGA_64xIN, + CHN_OFF = 0xF +} OPA_NSEL_TypeDef; + +/* OPA_PSEL_POLL_enumeration */ +typedef enum +{ + CHP_OPA1_OFF = 0, + CHP_OPA1_ON, +} OPA_PSEL_POLL_TypeDef; + +/* OPA_BKIN_EN_enumeration */ +typedef enum +{ + BKIN_OPA1_OFF = 0, /* TIM1 braking signal source form IO input */ + BKIN_OPA1_ON, /* TIM1 braking signal source form OPA output */ +} OPA_BKIN_EN_TypeDef; + +/* OPA_RST_EN_enumeration */ +typedef enum +{ + RST_OPA1_OFF = 0, + RST_OPA1_ON, +} OPA_RST_EN_TypeDef; + +/* OPA_OUT_IE_enumeration */ +typedef enum +{ + OUT_IE_OPA1_OFF = 0, + OUT_IE_OPA1_ON, +} OPA_OUT_IE_TypeDef; + +/* OPA_CNT_IE_enumeration */ +typedef enum +{ + CNT_IE_OFF = 0, + CNT_IE_ON, +} OPA_CNT_IE_TypeDef; + +/* OPA_NMI_IE_enumeration */ +typedef enum +{ + NMI_IE_OFF = 0, + NMI_IE_ON, +} OPA_NMI_IE_TypeDef; + +/* OPA_PSEL_POLL_NUM_enumeration */ +typedef enum +{ + CHP_POLL_NUM_1 = 0, + CHP_POLL_NUM_2, + CHP_POLL_NUM_3, + CHP_POLL_NUM_4, + CHP_POLL_NUM_5, + CHP_POLL_NUM_6 +} OPA_PSEL_POLL_NUM_TypeDef; + +/* Offset_voltage_adjustment_value_polarity */ +typedef enum +{ + OPA_Vos_Ads_N = 0, + OPA_Vos_Ads_P +} OPA_Vos_ADS_POLARITY_TypeDef; + +/* OPA Init Structure definition */ +typedef struct +{ + uint16_t OPA_POLL_Interval; /* OPA polling interval = (OPA_POLL_Interval+1)*1us + This parameter must range from 0 to 0x1FF.*/ + OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of OPA */ + OPA_BKIN_EN_TypeDef BKIN_EN; /* Specifies the brake input source of OPA */ + OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */ + OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */ + OPA_CNT_IE_TypeDef CNT_IE; /* Specifies the out interrupt rising edge of sampling data */ + OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NIM interrupt of OPA */ + OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of forward inputs*/ +} OPA_InitTypeDef; + +/* CMP_member_enumeration */ +typedef enum +{ + CMP1 = 0, + CMP2, + CMP3 +} CMP_Num_TypeDef; + +/* CMP_out_channel_enumeration */ +typedef enum +{ + OUT_IO0 = 0, + OUT_IO1, + OUT_IO_TIM2 +} CMP_Mode_TypeDef; + +/* CMP_NSEL_enumeration */ +typedef enum +{ + CMP_CHN0 = 0, + CMP_CHN1, +} CMP_NSEL_TypeDef; + +/* CMP_PSEL_enumeration */ +typedef enum +{ + CMP_CHP_0 = 0, + CMP_CHP_1, +} CMP_PSEL_TypeDef; + +#define CMP_CHP1 CMP_CHP_0 +#define CMP_CHP2 CMP_CHP_1 + +/* CMP_HYEN_enumeration */ +typedef enum +{ + CMP_HYEN0 = 0, + CMP_HYEN1, +} CMP_HYEN_TypeDef; + +/* CMP Init Structure definition */ +typedef struct +{ + CMP_Num_TypeDef CMP_NUM; /* Specifies the members of CMP */ + CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */ + CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ + CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ + CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */ +} CMP_InitTypeDef; + +/* Current channel for OPA polling enumeration */ +typedef enum +{ + O1P0 = 0, + O1P1, + O1P2, + O1P3, + O1P4, + O1P5, +} OPA_POLL_NUM_TypeDef; + +/* OPA_flags_definition */ +#define OPA_FLAG_OUT_OPA1 ((uint16_t)0x1000) +#define OPA_FLAG_OUT_CNT ((uint16_t)0x4000) + +/* CMP_WakeUp_IO_mode_definition */ +#define CMP_WakeUp_Rising_Falling ((uint32_t)0x01000000) +#define CMP_WakeUp_Rising ((uint32_t)0x02000000) +#define CMP_WakeUp_Falling ((uint32_t)0x03000000) + +void OPCM_Unlock(void); +void OPCM_Lock(void); +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); +void OPA_LP_Cmd(FunctionalState NewState); +void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct); +void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct); +void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); +void OPA_CMP_LP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); +void OPA_CMP_WakeUp_ModeConfig(uint32_t CMP_WakeUP_Mode); +FlagStatus OPA_GetFlagStatus( uint16_t OPA_FLAG); +void OPA_ClearFlag(uint16_t OPA_FLAG); +OPA_POLL_NUM_TypeDef OPA_POLL_CNT(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_pwr.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_pwr.h index 2607430..472f818 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_pwr.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_pwr.h @@ -1,68 +1,68 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_pwr.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the PWR - * firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_PWR_H -#define __CH32L103_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* PVD_detection_level */ -#define PWR_PVDLevel_0 ((uint32_t)0x00000000) -#define PWR_PVDLevel_1 ((uint32_t)0x00000020) -#define PWR_PVDLevel_2 ((uint32_t)0x00000040) -#define PWR_PVDLevel_3 ((uint32_t)0x00000060) -#define PWR_PVDLevel_4 ((uint32_t)0x00000080) -#define PWR_PVDLevel_5 ((uint32_t)0x000000A0) -#define PWR_PVDLevel_6 ((uint32_t)0x000000C0) -#define PWR_PVDLevel_7 ((uint32_t)0x000000E0) - -/* Regulator_state_is_STOP_mode */ -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower ((uint32_t)0x00000001) - -/* STOP_mode_entry */ -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) - -/* PWR_Flag */ -#define PWR_FLAG_WU ((uint32_t)0x00000001) -#define PWR_FLAG_SB ((uint32_t)0x00000002) -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) - -void PWR_DeInit(void); -void PWR_BackupAccessCmd(FunctionalState NewState); -void PWR_PVDCmd(FunctionalState NewState); -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_WakeUpPinCmd(FunctionalState NewState); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); -void PWR_EnterSTANDBYMode_RAM(void); -void PWR_EnterSTANDBYMode_RAM_LV(void); -void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); -void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); -void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_LDO_LP_Cmd(FunctionalState NewState); -void PWR_STOPMode_Auto_LDO_LP_Cmd(FunctionalState NewState); -void PWR_FLASH_LP_Cmd(FunctionalState NewState); - - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_pwr.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the PWR + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_PWR_H +#define __CH32L103_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* PVD_detection_level */ +#define PWR_PVDLevel_0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_4 ((uint32_t)0x00000080) +#define PWR_PVDLevel_5 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_6 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_7 ((uint32_t)0x000000E0) + +/* Regulator_state_is_STOP_mode */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); +void PWR_EnterSTANDBYMode_RAM(void); +void PWR_EnterSTANDBYMode_RAM_LV(void); +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); +void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_LDO_LP_Cmd(FunctionalState NewState); +void PWR_STOPMode_Auto_LDO_LP_Cmd(FunctionalState NewState); +void PWR_FLASH_LP_Cmd(FunctionalState NewState); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_rcc.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_rcc.h index 150e4f5..8acc09e 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_rcc.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_rcc.h @@ -1,220 +1,220 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_rcc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the RCC firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_RCC_H -#define __CH32L103_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* RCC_Exported_Types */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ - uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ -} RCC_ClocksTypeDef; - -/* HSE_configuration */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00010000) -#define RCC_HSE_Bypass ((uint32_t)0x00040000) - -/* PLL_entry_clock_source */ -#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) -#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) -#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) - -/* PLL_multiplication_factor for other CH32L103 */ -#define RCC_PLLMul_2 ((uint32_t)0x00000000) -#define RCC_PLLMul_3 ((uint32_t)0x00040000) -#define RCC_PLLMul_4 ((uint32_t)0x00080000) -#define RCC_PLLMul_5 ((uint32_t)0x000C0000) -#define RCC_PLLMul_6 ((uint32_t)0x00100000) -#define RCC_PLLMul_7 ((uint32_t)0x00140000) -#define RCC_PLLMul_8 ((uint32_t)0x00180000) -#define RCC_PLLMul_9 ((uint32_t)0x001C0000) -#define RCC_PLLMul_10 ((uint32_t)0x00200000) -#define RCC_PLLMul_11 ((uint32_t)0x00240000) -#define RCC_PLLMul_12 ((uint32_t)0x00280000) -#define RCC_PLLMul_13 ((uint32_t)0x002C0000) -#define RCC_PLLMul_14 ((uint32_t)0x00300000) -#define RCC_PLLMul_15 ((uint32_t)0x00340000) -#define RCC_PLLMul_16 ((uint32_t)0x00380000) -#define RCC_PLLMul_18 ((uint32_t)0x003C0000) - -/* System_clock_source */ -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) - -/* HB_clock_source */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) - -/* PB1_PB2_clock_source */ -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00000400) -#define RCC_HCLK_Div4 ((uint32_t)0x00000500) -#define RCC_HCLK_Div8 ((uint32_t)0x00000600) -#define RCC_HCLK_Div16 ((uint32_t)0x00000700) - -/* RCC_Interrupt_source */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) - -/* USB_Device_clock_source */ -#define RCC_USBCLKSource_PLLCLK_Div1 ((uint32_t)0x00000000) -#define RCC_USBCLKSource_PLLCLK_Div2 ((uint32_t)0x00400000) -#define RCC_USBCLKSource_PLLCLK_Div1_5 ((uint32_t)0x00800000) - -/* ADC_clock_source */ -#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) -#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) -#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) -#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) -#define RCC_HCLK_ADC ((uint32_t)0x80000000) - -/* LSE_configuration */ -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) - -/* RTC_clock_source */ -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) - -/* HB_peripheral */ -#define RCC_HBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_HBPeriph_SRAM ((uint32_t)0x00000004) -#define RCC_HBPeriph_CRC ((uint32_t)0x00000040) -#define RCC_HBPeriph_USBFS ((uint32_t)0x00001000) -#define RCC_HBPeriph_USBPD ((uint32_t)0x00020000) - -/* PB2_peripheral */ -#define RCC_PB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_PB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_PB2Periph_GPIOB ((uint32_t)0x00000008) -#define RCC_PB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_PB2Periph_GPIOD ((uint32_t)0x00000020) -#define RCC_PB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_PB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_PB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_PB2Periph_USART1 ((uint32_t)0x00004000) - -/* PB1_peripheral */ -#define RCC_PB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_PB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_PB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_PB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_PB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_PB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_PB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_PB1Periph_USART4 ((uint32_t)0x00080000) -#define RCC_PB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_PB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_PB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_PB1Periph_BKP ((uint32_t)0x08000000) -#define RCC_PB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_PB1Periph_LPTIM ((uint32_t)0x80000000) - -/* Clock_source_to_output_on_MCO_pin */ -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) -#define RCC_MCO_HSE ((uint8_t)0x06) -#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) - -/* RCC_Flag */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -/* SysTick_clock_source */ -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) - -/* ADC_clock_H_Level_Duty_Cycle */ -#define RCC_ADC_H_Level_Mode0 ((uint32_t)0x00000000) -#define RCC_ADC_H_Level_Mode1 ((uint32_t)0x10000000) -#define RCC_ADC_H_Level_Mode2 ((uint32_t)0x20000000) -#define RCC_ADC_H_Level_Mode3 ((uint32_t)0x30000000) -#define RCC_ADC_H_Level_Mode4 ((uint32_t)0x40000000) -#define RCC_ADC_H_Level_Mode5 ((uint32_t)0x50000000) -#define RCC_ADC_H_Level_Mode6 ((uint32_t)0x60000000) -#define RCC_ADC_H_Level_Mode7 ((uint32_t)0x70000000) - -void RCC_DeInit(void); -void RCC_HSEConfig(uint32_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); -void RCC_HBPeriphClockCmd(uint32_t RCC_HBPeriph, FunctionalState NewState); -void RCC_PB2PeriphClockCmd(uint32_t RCC_PB2Periph, FunctionalState NewState); -void RCC_PB1PeriphClockCmd(uint32_t RCC_PB1Periph, FunctionalState NewState); -void RCC_PB2PeriphResetCmd(uint32_t RCC_PB2Periph, FunctionalState NewState); -void RCC_PB1PeriphResetCmd(uint32_t RCC_PB1Periph, FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCO); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); -void RCC_ADCCLKDutyCycleConfig(uint32_t RCC_DutyCycle); -void RCC_HSE_LP_Cmd(FunctionalState NewState); -void RCC_HSI_LP_Cmd(FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_rcc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the RCC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_RCC_H +#define __CH32L103_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ +} RCC_ClocksTypeDef; + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + +/* PLL_multiplication_factor for other CH32L103 */ +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) +#define RCC_PLLMul_18 ((uint32_t)0x003C0000) + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* HB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) + +/* PB1_PB2_clock_source */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +/* USB_Device_clock_source */ +#define RCC_USBCLKSource_PLLCLK_Div1 ((uint32_t)0x00000000) +#define RCC_USBCLKSource_PLLCLK_Div2 ((uint32_t)0x00400000) +#define RCC_USBCLKSource_PLLCLK_Div1_5 ((uint32_t)0x00800000) + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define RCC_HCLK_ADC ((uint32_t)0x80000000) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) + +/* HB_peripheral */ +#define RCC_HBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_HBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_HBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_HBPeriph_USBFS ((uint32_t)0x00001000) +#define RCC_HBPeriph_USBPD ((uint32_t)0x00020000) + +/* PB2_peripheral */ +#define RCC_PB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_PB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_PB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_PB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_PB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_PB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_PB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_PB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_PB2Periph_USART1 ((uint32_t)0x00004000) + +/* PB1_peripheral */ +#define RCC_PB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_PB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_PB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_PB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_PB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_PB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_PB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_PB1Periph_USART4 ((uint32_t)0x00080000) +#define RCC_PB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_PB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_PB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_PB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_PB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_PB1Periph_LPTIM ((uint32_t)0x80000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +/* ADC_clock_H_Level_Duty_Cycle */ +#define RCC_ADC_H_Level_Mode0 ((uint32_t)0x00000000) +#define RCC_ADC_H_Level_Mode1 ((uint32_t)0x10000000) +#define RCC_ADC_H_Level_Mode2 ((uint32_t)0x20000000) +#define RCC_ADC_H_Level_Mode3 ((uint32_t)0x30000000) +#define RCC_ADC_H_Level_Mode4 ((uint32_t)0x40000000) +#define RCC_ADC_H_Level_Mode5 ((uint32_t)0x50000000) +#define RCC_ADC_H_Level_Mode6 ((uint32_t)0x60000000) +#define RCC_ADC_H_Level_Mode7 ((uint32_t)0x70000000) + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); +void RCC_HBPeriphClockCmd(uint32_t RCC_HBPeriph, FunctionalState NewState); +void RCC_PB2PeriphClockCmd(uint32_t RCC_PB2Periph, FunctionalState NewState); +void RCC_PB1PeriphClockCmd(uint32_t RCC_PB1Periph, FunctionalState NewState); +void RCC_PB2PeriphResetCmd(uint32_t RCC_PB2Periph, FunctionalState NewState); +void RCC_PB1PeriphResetCmd(uint32_t RCC_PB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); +void RCC_ADCCLKDutyCycleConfig(uint32_t RCC_DutyCycle); +void RCC_HSE_LP_Cmd(FunctionalState NewState); +void RCC_HSI_LP_Cmd(FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_rtc.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_rtc.h index 77ae7a0..9018cf0 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_rtc.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_rtc.h @@ -1,55 +1,55 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_rtc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the RTC - * firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_RTC_H -#define __CH32L103_RTC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - - -/* RTC_interrupts_define */ -#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ -#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ -#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ - -/* RTC_interrupts_flags */ -#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ -#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ -#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ -#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ -#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ - - -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); -void RTC_EnterConfigMode(void); -void RTC_ExitConfigMode(void); -uint32_t RTC_GetCounter(void); -void RTC_SetCounter(uint32_t CounterValue); -void RTC_SetPrescaler(uint32_t PrescalerValue); -void RTC_SetAlarm(uint32_t AlarmValue); -uint32_t RTC_GetDivider(void); -void RTC_WaitForLastTask(void); -void RTC_WaitForSynchro(void); -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); -void RTC_ClearFlag(uint16_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint16_t RTC_IT); -void RTC_ClearITPendingBit(uint16_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_rtc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the RTC + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_RTC_H +#define __CH32L103_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + + +/* RTC_interrupts_define */ +#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ + +/* RTC_interrupts_flags */ +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ + + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_spi.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_spi.h index 888734f..0f8bbb6 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_spi.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_spi.h @@ -1,157 +1,158 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_spi.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * SPI firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_SPI_H -#define __CH32L103_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* SPI Init structure definition */ -typedef struct -{ - uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /* Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /* Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /* Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ -} SPI_InitTypeDef; - -/* SPI_data_direction */ -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) - -/* SPI_mode */ -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) - -/* SPI_data_size */ -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) - -/* SPI_Clock_Polarity */ -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) - -/* SPI_Clock_Phase */ -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) - -/* SPI_Slave_Select_management */ -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) - -/* SPI_BaudRate_Prescaler */ -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) - -/* SPI_MSB_LSB_transmission */ -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) - -/* SPI_DMA_transfer_requests */ -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) - -/* SPI_NSS_internal_software_management */ -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) - -/* SPI_CRC_Transmit_Receive */ -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) - -/* SPI_direction_transmit_receive */ -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) - -/* SPI_interrupts_definition */ -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) - -/* SPI_flags_definition */ -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) - - - -void SPI_I2S_DeInit(SPI_TypeDef *SPIx); -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); -void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); -void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); -void SPI_TransmitCRC(SPI_TypeDef *SPIx); -void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); -void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); -void SPI_HighSpeedRead_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_spi.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/05 + * Description : This file contains all the functions prototypes for the + * SPI firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_SPI_H +#define __CH32L103_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity + When using SPI slave mode to send data, the CPOL bit should be set to 1 */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +} SPI_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002)//When using SPI slave mode to send data, the CPOL bit should be set to 1. + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB_transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* SPI_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) + +/* SPI_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + + +void SPI_I2S_DeInit(SPI_TypeDef *SPIx); +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef *SPIx); +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_HighSpeedRead_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_tim.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_tim.h index 9043720..eebb9dd 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_tim.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_tim.h @@ -1,517 +1,517 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_tim.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * TIM firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_TIM_H -#define __CH32L103_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* TIM Time Base Init structure definition */ -typedef struct -{ - uint32_t TIM_Period; /* Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF for TIM1-TIM2-TIM3. - This parameter must be a number between 0x00000000 and 0xFFFFFFFF for TIM4. */ - - uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /* Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint16_t TIM_ClockDivision; /* Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/* TIM Output Compare Init structure definition */ -typedef struct -{ - uint32_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF for TIM1-TIM2-TIM3. - This parameter must be a number between 0x00000000 and 0xFFFFFFFF for TIM4. */ - - uint16_t TIM_OCMode; /* Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_state - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCPolarity; /* Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/* TIM Input Capture Init structure definition */ -typedef struct -{ - uint16_t TIM_Channel; /* Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /* Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /* Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/* BDTR structure definition */ -typedef struct -{ - uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. - This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. - This parameter can be a value of @ref Lock_level */ - - uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/* TIM_Output_Compare_and_PWM_modes */ -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) - -/* TIM_One_Pulse_Mode */ -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) - -/* TIM_Channel */ -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -/* TIM_Clock_Division_CKD */ -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) - -/* TIM_Counter_Mode */ -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) - -/* TIM_Output_Compare_Polarity */ -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) - -/* TIM_Output_Compare_N_Polarity */ -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) - -/* TIM_Output_Compare_state */ -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) - -/* TIM_Output_Compare_N_state */ -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) - -/* TIM_Capture_Compare_state */ -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) - -/* TIM_Capture_Compare_N_state */ -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) - -/* Break_Input_enable_disable */ -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) - -/* Break_Polarity */ -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) - -/* TIM_AOE_Bit_Set_Reset */ -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) - -/* Lock_level */ -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) - -/* OSSI_Off_State_Selection_for_Idle_mode_state */ -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) - -/* OSSR_Off_State_Selection_for_Run_mode_state */ -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Idle_State */ -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Output_Compare_N_Idle_State */ -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Input_Capture_Polarity */ -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) - -/* TIM_Input_Capture_Selection */ -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ - -/* TIM_Input_Capture_Prescaler */ -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ - -/* TIM_interrupt_sources */ -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) - -/* TIM_DMA_Base_address */ -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) - -/* TIM_DMA_Burst_Length */ -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) - -/* TIM_DMA_sources */ -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) - -/* TIM_External_Trigger_Prescaler */ -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) - -/* TIM_Internal_Trigger_Selection */ -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) - -/* TIM_TIx_External_Clock_Source */ -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/* TIM_External_Trigger_Polarity */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) - -/* TIM_Prescaler_Reload_Mode */ -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) - -/* TIM_Forced_Action */ -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) - -/* TIM_Encoder_Mode */ -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) - -/* TIM_Event_Source */ -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) - -/* TIM_Update_Source */ -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ - or the setting of UG bit, or an update generation \ - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ - -/* TIM_Output_Compare_Preload_State */ -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Fast_State */ -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Clear_State */ -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) - -/* TIM_Trigger_Output_Source */ -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) - -/* TIM_Slave_Mode */ -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) - -/* TIM_Master_Slave_Mode */ -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) - -/* TIM_Flags */ -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) - -/* TIM_Legacy */ -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers - -/* TIM_Capture_Mode */ -#define TIM_Capture_Mode0 ((uint16_t)0x0000) -#define TIM_Capture_Mode1 ((uint16_t)0x4000) - -void TIM_DeInit(TIM_TypeDef *TIMx); -void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); -void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); -void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_InternalClockConfig(TIM_TypeDef *TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); -void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); -void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); -void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); -void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); -void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); -void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter); -void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload); -void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1); -void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2); -void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3); -void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4); -void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); -uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx); -uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx); -uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx); -uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx); -uint32_t TIM_GetCounter(TIM_TypeDef *TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); -void TIM_CaptureLevelIndicate_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_CaptureModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CaptureMode); - - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_tim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_TIM_H +#define __CH32L103_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint32_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF for TIM1-TIM2-TIM3. + This parameter must be a number between 0x00000000 and 0xFFFFFFFF for TIM4. */ + + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint32_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF for TIM1-TIM2-TIM3. + This parameter must be a number between 0x00000000 and 0xFFFFFFFF for TIM4. */ + + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + +/* TIM_Capture_Mode */ +#define TIM_Capture_Mode0 ((uint16_t)0x0000) +#define TIM_Capture_Mode1 ((uint16_t)0x4000) + +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef *TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter); +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1); +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2); +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3); +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); +uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx); +uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx); +uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx); +uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx); +uint32_t TIM_GetCounter(TIM_TypeDef *TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_CaptureLevelIndicate_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CaptureModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CaptureMode); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usart.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usart.h index c981f49..45c7094 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usart.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usart.h @@ -1,188 +1,188 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_usart.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * USART firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_USART_H -#define __CH32L103_USART_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* USART Init Structure definition */ -typedef struct -{ - uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /* Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/* USART Clock Init Structure definition */ -typedef struct -{ - uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* USART_Word_Length */ -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -/* USART_Stop_Bits */ -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) - -/* USART_Parity */ -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) - -/* USART_Mode */ -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) - -/* USART_Hardware_Flow_Control */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) - -/* USART_Clock */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) - -/* USART_Clock_Polarity */ -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) - -/* USART_Clock_Phase */ -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) - -/* USART_Last_Bit */ -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) - -/* USART_Interrupt_definition */ -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) - -#define USART_IT_ORE USART_IT_ORE_ER - -/* USART_DMA_Requests */ -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) - -/* USART_WakeUp_methods */ -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) - -/* USART_LIN_Break_Detection_Length */ -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) - -/* USART_IrDA_Low_Power */ -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) - -/* USART_Flags */ -#define USART_FLAG_RX_BUSY ((uint16_t)0x0400) -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) - -void USART_DeInit(USART_TypeDef *USARTx); -void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); -void USART_StructInit(USART_InitTypeDef *USART_InitStruct); -void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); -void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); -void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef *USARTx); -void USART_SendBreak(USART_TypeDef *USARTx); -void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); -void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_usart.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * USART firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_USART_H +#define __CH32L103_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_RX_BUSY ((uint16_t)0x0400) +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +void USART_DeInit(USART_TypeDef *USARTx); +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); +void USART_StructInit(USART_InitTypeDef *USART_InitStruct); +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef *USARTx); +void USART_SendBreak(USART_TypeDef *USARTx); +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usb.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usb.h index a3689f0..9023b51 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usb.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usb.h @@ -1,513 +1,509 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_usb.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/19 - * Description : This file contains all the functions prototypes for the USB - * firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32L103_USB_H -#define __CH32L103_USB_H - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -/*******************************************************************************/ -/* Header File */ -#include "stdint.h" - -/*******************************************************************************/ -/* USB Communication Related Macro Definition */ - -/* USB Endpoint0 Size */ -#ifndef DEFAULT_ENDP0_SIZE -#define DEFAULT_ENDP0_SIZE 8 -#endif - -/* USB Buffer Size */ -#ifndef USBFS_MAX_PACKET_SIZE -#define USBFS_MAX_PACKET_SIZE 64 -#endif - -/* USB PID */ -#ifndef USB_PID_SETUP -#define USB_PID_NULL 0x00 -#define USB_PID_SOF 0x05 -#define USB_PID_SETUP 0x0D -#define USB_PID_IN 0x09 -#define USB_PID_OUT 0x01 -#define USB_PID_NYET 0x06 -#define USB_PID_ACK 0x02 -#define USB_PID_NAK 0x0A -#define USB_PID_STALL 0x0E -#define USB_PID_DATA0 0x03 -#define USB_PID_DATA1 0x0B -#define USB_PID_PRE 0x0C -#endif - -/* USB standard device request code */ -#ifndef USB_GET_DESCRIPTOR -#define USB_GET_STATUS 0x00 -#define USB_CLEAR_FEATURE 0x01 -#define USB_SET_FEATURE 0x03 -#define USB_SET_ADDRESS 0x05 -#define USB_GET_DESCRIPTOR 0x06 -#define USB_SET_DESCRIPTOR 0x07 -#define USB_GET_CONFIGURATION 0x08 -#define USB_SET_CONFIGURATION 0x09 -#define USB_GET_INTERFACE 0x0A -#define USB_SET_INTERFACE 0x0B -#define USB_SYNCH_FRAME 0x0C -#endif - -#define DEF_STRING_DESC_LANG 0x00 -#define DEF_STRING_DESC_MANU 0x01 -#define DEF_STRING_DESC_PROD 0x02 -#define DEF_STRING_DESC_SERN 0x03 - -/* USB hub class request code */ -#ifndef HUB_GET_DESCRIPTOR -#define HUB_GET_STATUS 0x00 -#define HUB_CLEAR_FEATURE 0x01 -#define HUB_GET_STATE 0x02 -#define HUB_SET_FEATURE 0x03 -#define HUB_GET_DESCRIPTOR 0x06 -#define HUB_SET_DESCRIPTOR 0x07 -#endif - -/* USB HID class request code */ -#ifndef HID_GET_REPORT -#define HID_GET_REPORT 0x01 -#define HID_GET_IDLE 0x02 -#define HID_GET_PROTOCOL 0x03 -#define HID_SET_REPORT 0x09 -#define HID_SET_IDLE 0x0A -#define HID_SET_PROTOCOL 0x0B -#endif - -/* Bit Define for USB Request Type */ -#ifndef USB_REQ_TYP_MASK -#define USB_REQ_TYP_IN 0x80 -#define USB_REQ_TYP_OUT 0x00 -#define USB_REQ_TYP_READ 0x80 -#define USB_REQ_TYP_WRITE 0x00 -#define USB_REQ_TYP_MASK 0x60 -#define USB_REQ_TYP_STANDARD 0x00 -#define USB_REQ_TYP_CLASS 0x20 -#define USB_REQ_TYP_VENDOR 0x40 -#define USB_REQ_TYP_RESERVED 0x60 -#define USB_REQ_RECIP_MASK 0x1F -#define USB_REQ_RECIP_DEVICE 0x00 -#define USB_REQ_RECIP_INTERF 0x01 -#define USB_REQ_RECIP_ENDP 0x02 -#define USB_REQ_RECIP_OTHER 0x03 -#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 -#define USB_REQ_FEAT_ENDP_HALT 0x00 -#endif - -/* USB Descriptor Type */ -#ifndef USB_DESCR_TYP_DEVICE -#define USB_DESCR_TYP_DEVICE 0x01 -#define USB_DESCR_TYP_CONFIG 0x02 -#define USB_DESCR_TYP_STRING 0x03 -#define USB_DESCR_TYP_INTERF 0x04 -#define USB_DESCR_TYP_ENDP 0x05 -#define USB_DESCR_TYP_QUALIF 0x06 -#define USB_DESCR_TYP_SPEED 0x07 -#define USB_DESCR_TYP_OTG 0x09 -#define USB_DESCR_TYP_BOS 0X0F -#define USB_DESCR_TYP_HID 0x21 -#define USB_DESCR_TYP_REPORT 0x22 -#define USB_DESCR_TYP_PHYSIC 0x23 -#define USB_DESCR_TYP_CS_INTF 0x24 -#define USB_DESCR_TYP_CS_ENDP 0x25 -#define USB_DESCR_TYP_HUB 0x29 -#endif - -/* USB Device Class */ -#ifndef USB_DEV_CLASS_HUB -#define USB_DEV_CLASS_RESERVED 0x00 -#define USB_DEV_CLASS_AUDIO 0x01 -#define USB_DEV_CLASS_COMMUNIC 0x02 -#define USB_DEV_CLASS_HID 0x03 -#define USB_DEV_CLASS_MONITOR 0x04 -#define USB_DEV_CLASS_PHYSIC_IF 0x05 -#define USB_DEV_CLASS_POWER 0x06 -#define USB_DEV_CLASS_IMAGE 0x06 -#define USB_DEV_CLASS_PRINTER 0x07 -#define USB_DEV_CLASS_STORAGE 0x08 -#define USB_DEV_CLASS_HUB 0x09 -#define USB_DEV_CLASS_VEN_SPEC 0xFF -#endif - -/* USB Hub Class Request */ -#ifndef HUB_GET_HUB_DESCRIPTOR -#define HUB_CLEAR_HUB_FEATURE 0x20 -#define HUB_CLEAR_PORT_FEATURE 0x23 -#define HUB_GET_BUS_STATE 0xA3 -#define HUB_GET_HUB_DESCRIPTOR 0xA0 -#define HUB_GET_HUB_STATUS 0xA0 -#define HUB_GET_PORT_STATUS 0xA3 -#define HUB_SET_HUB_DESCRIPTOR 0x20 -#define HUB_SET_HUB_FEATURE 0x20 -#define HUB_SET_PORT_FEATURE 0x23 -#endif - -/* Hub Class Feature Selectors */ -#ifndef HUB_PORT_RESET -#define HUB_C_HUB_LOCAL_POWER 0 -#define HUB_C_HUB_OVER_CURRENT 1 -#define HUB_PORT_CONNECTION 0 -#define HUB_PORT_ENABLE 1 -#define HUB_PORT_SUSPEND 2 -#define HUB_PORT_OVER_CURRENT 3 -#define HUB_PORT_RESET 4 -#define HUB_PORT_POWER 8 -#define HUB_PORT_LOW_SPEED 9 -#define HUB_C_PORT_CONNECTION 16 -#define HUB_C_PORT_ENABLE 17 -#define HUB_C_PORT_SUSPEND 18 -#define HUB_C_PORT_OVER_CURRENT 19 -#define HUB_C_PORT_RESET 20 -#endif - -/* USB HID Class Request Code */ -#ifndef HID_GET_REPORT -#define HID_GET_REPORT 0x01 -#define HID_GET_IDLE 0x02 -#define HID_GET_PROTOCOL 0x03 -#define HID_SET_REPORT 0x09 -#define HID_SET_IDLE 0x0A -#define HID_SET_PROTOCOL 0x0B -#endif - -/* USB CDC Class request code */ -#ifndef CDC_GET_LINE_CODING -#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */ -#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ -#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */ -#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */ -#endif - -/* USB UDisk */ -#ifndef USB_BO_CBW_SIZE -#define USB_BO_CBW_SIZE 0x1F -#define USB_BO_CSW_SIZE 0x0D -#endif -#ifndef USB_BO_CBW_SIG0 -#define USB_BO_CBW_SIG0 0x55 -#define USB_BO_CBW_SIG1 0x53 -#define USB_BO_CBW_SIG2 0x42 -#define USB_BO_CBW_SIG3 0x43 -#define USB_BO_CSW_SIG0 0x55 -#define USB_BO_CSW_SIG1 0x53 -#define USB_BO_CSW_SIG2 0x42 -#define USB_BO_CSW_SIG3 0x53 -#endif - -/*******************************************************************************/ -/* USBFS Related Register Macro Definition */ - -/* R8_USB_CTRL */ -#define USBFS_UC_HOST_MODE 0x80 -#define USBFS_UC_LOW_SPEED 0x40 -#define USBFS_UC_SYS_CTRL_MASK 0x30 -#define USBFS_UC_SYS_CTRL0 0x00 -#define USBFS_UC_SYS_CTRL1 0x10 -#define USBFS_UC_SYS_CTRL2 0x20 -#define USBFS_UC_SYS_CTRL3 0x30 -#define USBFS_UC_DEV_PU_EN 0x20 -#define USBFS_UC_INT_BUSY 0x08 -#define USBFS_UC_RESET_SIE 0x04 -#define USBFS_UC_CLR_ALL 0x02 -#define USBFS_UC_DMA_EN 0x01 - -/* R8_USB_INT_EN */ -#define USBFS_UIE_DEV_NAK 0x40 -#define USBFS_UID_1_WIRE 0x20 -#define USBFS_UIE_FIFO_OV 0x10 -#define USBFS_UIE_HST_SOF 0x08 -#define USBFS_UIE_SUSPEND 0x04 -#define USBFS_UIE_TRANSFER 0x02 -#define USBFS_UIE_DETECT 0x01 -#define USBFS_UIE_BUS_RST 0x01 - -/* R8_USB_DEV_AD */ -#define USBFS_UDA_GP_BIT 0x80 -#define USBFS_USB_ADDR_MASK 0x7F - -/* R8_USB_MIS_ST */ -#define USBFS_UMS_SOF_PRES 0x80 -#define USBFS_UMS_SOF_ACT 0x40 -#define USBFS_UMS_SIE_FREE 0x20 -#define USBFS_UMS_R_FIFO_RDY 0x10 -#define USBFS_UMS_BUS_RESET 0x08 -#define USBFS_UMS_SUSPEND 0x04 -#define USBFS_UMS_DM_LEVEL 0x02 -#define USBFS_UMS_DEV_ATTACH 0x01 - -/* R8_USB_INT_FG */ -#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received -#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK -#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status -#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear -#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear -#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear -#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear -#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear -#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear - -/* R8_USB_INT_ST */ -#define USBFS_SETUP_ACT 0x80 // RO, indicate current SETUP transaction completed -#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK -#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode -#define USBFS_UIS_TOKEN_OUT 0x00 -#define USBFS_UIS_TOKEN_IN 0x20 -#define USBFS_UIS_TOKEN_SETUP 0x30 -// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode -// 00: OUT token PID received -// 10: IN token PID received -// 11: SETUP token PID received -#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode -#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received - -/* R8_UDEV_CTRL */ -#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable -#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level -#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level -#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed -#define USBFS_UD_GP_BIT 0x02 // general purpose bit -#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable - -/* R8_UEP4_1_MOD */ -#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) -#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) -#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 -#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) -#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) -#define USBFS_UEP4_BUF_MOD 0x01 - -/* R8_UEP2_3_MOD */ -#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) -#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) -#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 -#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) -#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) -#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 - -/* R8_UEP5_6_MOD */ -#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) -#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) -#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 -#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) -#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) -#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 - -/* R8_UEP7_MOD */ -#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) -#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) -#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 - -/* R8_UEPn_TX_CTRL */ -#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle -#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 -#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) -#define USBFS_UEP_T_RES_ACK 0x00 -#define USBFS_UEP_T_RES_NONE 0x01 -#define USBFS_UEP_T_RES_NAK 0x02 -#define USBFS_UEP_T_RES_STALL 0x03 -// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) -// 00: DATA0 or DATA1 then expecting ACK (ready) -// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions -// 10: NAK (busy) -// 11: STALL (error) -// host aux setup - -/* R8_UEPn_RX_CTRL, n=0-7 */ -#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle -#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 -#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) -#define USBFS_UEP_R_RES_ACK 0x00 -#define USBFS_UEP_R_RES_NONE 0x01 -#define USBFS_UEP_R_RES_NAK 0x02 -#define USBFS_UEP_R_RES_STALL 0x03 -// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) -// 00: ACK (ready) -// 01: no response, time out to host, for non-zero endpoint isochronous transactions -// 10: NAK (busy) -// 11: STALL (error) - -/* R8_UHOST_CTRL */ -#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable -#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level -#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level -#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed -#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset -#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached - -/* R32_UH_EP_MOD */ -#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal -#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint -#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving -#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint - -/* R16_UH_SETUP */ -#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub -#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable - -/* R8_UH_EP_PID */ -#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer -#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer - -/* R8_UH_RX_CTRL */ -#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle -#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 -#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions - -/* R8_UH_TX_CTRL */ -#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle -#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 -#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions - -/*******************************************************************************/ -/* Struct Definition */ - -/* USB Setup Request */ -typedef struct __attribute__((packed)) _USB_SETUP_REQ -{ - uint8_t bRequestType; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -} USB_SETUP_REQ, *PUSB_SETUP_REQ; - -/* USB Device Descriptor */ -typedef struct __attribute__((packed)) _USB_DEVICE_DESCR -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - uint16_t idVendor; - uint16_t idProduct; - uint16_t bcdDevice; - uint8_t iManufacturer; - uint8_t iProduct; - uint8_t iSerialNumber; - uint8_t bNumConfigurations; -} USB_DEV_DESCR, *PUSB_DEV_DESCR; - -/* USB Configuration Descriptor */ -typedef struct __attribute__((packed)) _USB_CONFIG_DESCR -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t wTotalLength; - uint8_t bNumInterfaces; - uint8_t bConfigurationValue; - uint8_t iConfiguration; - uint8_t bmAttributes; - uint8_t MaxPower; -} USB_CFG_DESCR, *PUSB_CFG_DESCR; - -/* USB Interface Descriptor */ -typedef struct __attribute__((packed)) _USB_INTERF_DESCR -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bInterfaceNumber; - uint8_t bAlternateSetting; - uint8_t bNumEndpoints; - uint8_t bInterfaceClass; - uint8_t bInterfaceSubClass; - uint8_t bInterfaceProtocol; - uint8_t iInterface; -} USB_ITF_DESCR, *PUSB_ITF_DESCR; - -/* USB Endpoint Descriptor */ -typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - uint8_t wMaxPacketSizeL; - uint8_t wMaxPacketSizeH; - uint8_t bInterval; -} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; - -/* USB Configuration Descriptor Set */ -typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG -{ - USB_CFG_DESCR cfg_descr; - USB_ITF_DESCR itf_descr; - USB_ENDP_DESCR endp_descr[ 1 ]; -} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; - -/* USB HUB Descriptor */ -typedef struct __attribute__((packed)) _USB_HUB_DESCR -{ - uint8_t bDescLength; - uint8_t bDescriptorType; - uint8_t bNbrPorts; - uint8_t wHubCharacteristicsL; - uint8_t wHubCharacteristicsH; - uint8_t bPwrOn2PwrGood; - uint8_t bHubContrCurrent; - uint8_t DeviceRemovable; - uint8_t PortPwrCtrlMask; -} USB_HUB_DESCR, *PUSB_HUB_DESCR; - -/* USB HID Descriptor */ -typedef struct __attribute__((packed)) _USB_HID_DESCR -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdHID; - uint8_t bCountryCode; - uint8_t bNumDescriptors; - uint8_t bDescriptorTypeX; - uint8_t wDescriptorLengthL; - uint8_t wDescriptorLengthH; -} USB_HID_DESCR, *PUSB_HID_DESCR; - -/* USB UDisk */ -typedef struct __attribute__((packed)) _UDISK_BOC_CBW -{ - uint32_t mCBW_Sig; - uint32_t mCBW_Tag; - uint32_t mCBW_DataLen; - uint8_t mCBW_Flag; - uint8_t mCBW_LUN; - uint8_t mCBW_CB_Len; - uint8_t mCBW_CB_Buf[ 16 ]; -} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; - -/* USB UDisk */ -typedef struct __attribute__((packed)) _UDISK_BOC_CSW -{ - uint32_t mCBW_Sig; - uint32_t mCBW_Tag; - uint32_t mCSW_Residue; - uint8_t mCSW_Status; -} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; - - -#ifdef __cplusplus -} -#endif - -#endif /*_CH32L103_USB_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_usb.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/19 + * Description : This file contains all the functions prototypes for the USB + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32L103_USB_H +#define __CH32L103_USB_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*******************************************************************************/ +/* Header File */ +#include "stdint.h" + +/*******************************************************************************/ +/* USB Communication Related Macro Definition */ + +/* USB Endpoint0 Size */ +#ifndef DEFAULT_ENDP0_SIZE +#define DEFAULT_ENDP0_SIZE 8 +#endif + +/* USB Buffer Size */ +#ifndef USBFS_MAX_PACKET_SIZE +#define USBFS_MAX_PACKET_SIZE 64 +#endif + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_NYET 0x06 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* Bit Define for USB Request Type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 +#define USB_REQ_TYP_OUT 0x00 +#define USB_REQ_TYP_READ 0x80 +#define USB_REQ_TYP_WRITE 0x00 +#define USB_REQ_TYP_MASK 0x60 +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB Descriptor Type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB Device Class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_IMAGE 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB Hub Class Request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub Class Feature Selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB HID Class Request Code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif + +/* USB UDisk */ +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + +/*******************************************************************************/ +/* USBFS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBFS_UC_HOST_MODE 0x80 +#define USBFS_UC_LOW_SPEED 0x40 +#define USBFS_UC_SYS_CTRL_MASK 0x30 +#define USBFS_UC_SYS_CTRL0 0x00 +#define USBFS_UC_SYS_CTRL1 0x10 +#define USBFS_UC_SYS_CTRL2 0x20 +#define USBFS_UC_SYS_CTRL3 0x30 +#define USBFS_UC_DEV_PU_EN 0x20 +#define USBFS_UC_INT_BUSY 0x08 +#define USBFS_UC_RESET_SIE 0x04 +#define USBFS_UC_CLR_ALL 0x02 +#define USBFS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBFS_UIE_DEV_NAK 0x40 +#define USBFS_UID_1_WIRE 0x20 +#define USBFS_UIE_FIFO_OV 0x10 +#define USBFS_UIE_HST_SOF 0x08 +#define USBFS_UIE_SUSPEND 0x04 +#define USBFS_UIE_TRANSFER 0x02 +#define USBFS_UIE_DETECT 0x01 +#define USBFS_UIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +/* R8_USB_MIS_ST */ +#define USBFS_UMS_SOF_PRES 0x80 +#define USBFS_UMS_SOF_ACT 0x40 +#define USBFS_UMS_SIE_FREE 0x20 +#define USBFS_UMS_R_FIFO_RDY 0x10 +#define USBFS_UMS_BUS_RESET 0x08 +#define USBFS_UMS_SUSPEND 0x04 +#define USBFS_UMS_DM_LEVEL 0x02 +#define USBFS_UMS_DEV_ATTACH 0x01 + +/* R8_USB_INT_FG */ +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* R8_USB_INT_ST */ +#define USBFS_SETUP_ACT 0x80 // RO, indicate current SETUP transaction completed +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +/* R8_UDEV_CTRL */ +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* R8_UEP4_1_MOD */ +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +#define USBFS_UEP4_BUF_MOD 0x01 + +/* R8_UEP2_3_MOD */ +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* R8_UEP5_6_MOD */ +#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +/* R8_UEP7_MOD */ +#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +/* R8_UEPn_TX_CTRL */ +#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK 0x00 +#define USBFS_UEP_T_RES_NONE 0x01 +#define USBFS_UEP_T_RES_NAK 0x02 +#define USBFS_UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +// host aux setup + +/* R8_UEPn_RX_CTRL, n=0-7 */ +#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK 0x00 +#define USBFS_UEP_R_RES_NONE 0x01 +#define USBFS_UEP_R_RES_NAK 0x02 +#define USBFS_UEP_R_RES_STALL 0x03 +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +/* R8_UHOST_CTRL */ +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +/* R32_UH_EP_MOD */ +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint + +/* R16_UH_SETUP */ +#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable + +/* R8_UH_EP_PID */ +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + +/* R8_UH_RX_CTRL */ +#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +/* R8_UH_TX_CTRL */ +#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + +/*******************************************************************************/ +/* Struct Definition */ + +/* USB Setup Request */ +typedef struct __attribute__((packed)) _USB_SETUP_REQ +{ + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + +/* USB Device Descriptor */ +typedef struct __attribute__((packed)) _USB_DEVICE_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + +/* USB Configuration Descriptor */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + +/* USB Interface Descriptor */ +typedef struct __attribute__((packed)) _USB_INTERF_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + +/* USB Endpoint Descriptor */ +typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSizeL; + uint8_t wMaxPacketSizeH; + uint8_t bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + +/* USB Configuration Descriptor Set */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG +{ + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[ 1 ]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + +/* USB HUB Descriptor */ +typedef struct __attribute__((packed)) _USB_HUB_DESCR +{ + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint8_t wHubCharacteristicsL; + uint8_t wHubCharacteristicsH; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + +/* USB HID Descriptor */ +typedef struct __attribute__((packed)) _USB_HID_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bDescriptorTypeX; + uint8_t wDescriptorLengthL; + uint8_t wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CBW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCBW_DataLen; + uint8_t mCBW_Flag; + uint8_t mCBW_LUN; + uint8_t mCBW_CB_Len; + uint8_t mCBW_CB_Buf[ 16 ]; +} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CSW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCSW_Residue; + uint8_t mCSW_Status; +} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; + + +#ifdef __cplusplus +} +#endif + +#endif /*_CH32L103_USB_H */ diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usbpd.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usbpd.h index f95caba..40aa939 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usbpd.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_usbpd.h @@ -1,408 +1,408 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_can.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the - * CAN firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_USBPD_H -#define __CH32L103_USBPD_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -#ifndef VOID -#define VOID void -#endif -#ifndef CONST -#define CONST const -#endif -#ifndef BOOL -typedef unsigned char BOOL; -#endif -#ifndef BOOLEAN -typedef unsigned char BOOLEAN; -#endif -#ifndef CHAR -typedef char CHAR; -#endif -#ifndef INT8 -typedef char INT8; -#endif -#ifndef INT16 -typedef short INT16; -#endif -#ifndef INT32 -typedef long INT32; -#endif -#ifndef UINT8 -typedef unsigned char UINT8; -#endif -#ifndef UINT16 -typedef unsigned short UINT16; -#endif -#ifndef UINT32 -typedef unsigned long UINT32; -#endif -#ifndef UINT8V -typedef unsigned char volatile UINT8V; -#endif -#ifndef UINT16V -typedef unsigned short volatile UINT16V; -#endif -#ifndef UINT32V -typedef unsigned long volatile UINT32V; -#endif - -#ifndef PVOID -typedef void *PVOID; -#endif -#ifndef PCHAR -typedef char *PCHAR; -#endif -#ifndef PCHAR -typedef const char *PCCHAR; -#endif -#ifndef PINT8 -typedef char *PINT8; -#endif -#ifndef PINT16 -typedef short *PINT16; -#endif -#ifndef PINT32 -typedef long *PINT32; -#endif -#ifndef PUINT8 -typedef unsigned char *PUINT8; -#endif -#ifndef PUINT16 -typedef unsigned short *PUINT16; -#endif -#ifndef PUINT32 -typedef unsigned long *PUINT32; -#endif -#ifndef PUINT8V -typedef volatile unsigned char *PUINT8V; -#endif -#ifndef PUINT16V -typedef volatile unsigned short *PUINT16V; -#endif -#ifndef PUINT32V -typedef volatile unsigned long *PUINT32V; -#endif - - /******************************************************************************/ -/* Related macro definitions */ - -/* Define the return value of the function */ -#ifndef SUCCESS -#define SUCCESS 0 -#endif -#ifndef FAIL -#define FAIL 0xFF -#endif - -/* Register Bit Definition */ -/* USBPD->CONFIG */ -#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ -#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ -#define CC_SEL (1<<2) /* Select PD communication port */ -#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ -#define PD_RST_EN (1<<4) /* PD mode reset command enable */ -#define WAKE_POLAR (1<<5) /* PD port wake-up level */ -#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ -#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ -#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ -#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ -#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ -#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ - -/* USBPD->CONTROL */ -#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ -#define BMC_START (1<<1) /* BMC send start signal */ -#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ -#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ -#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ -#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ -#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ -#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ - -/* USBPD->TX_SEL */ -#define TX_SEL1 (0<<0) -#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ -#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ -#define TX_SEL2_Mask (3<<2) -#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ -#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ -#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ -#define TX_SEL3_Mask (3<<4) -#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ -#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ -#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ -#define TX_SEL4_Mask (3<<6) -#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ -#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ -#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ - -/* USBPD->STATUS */ -#define BMC_AUX (3<<0) /* BMC auxiliary information */ -#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ -#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ -#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ -#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ -#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ -#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ -#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ -#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ -#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ -#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ - -/* USBPD->PORT_CC1 */ -/* USBPD->PORT_CC2 */ -#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ -#define CC_PD (1<<1) /* CC port pull-down resistor enable */ -#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ -#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ -#define CC_PU_330 (1<<2) /* 01-330uA */ -#define CC_PU_180 (2<<2) /* 10-180uA */ -#define CC_PU_80 (3<<2) /* 11-80uA */ -#define CC_LVE (1<<4) /* CC port output low voltage enable */ -#define CC_CE (7<<5) /* Enable the voltage comparator on port CC */ -#define CC_NO_CMP (0<<5) /* 000-closed */ -#define CC_CMP_22 (2<<5) /* 010-0.22V */ -#define CC_CMP_45 (3<<5) /* 011-0.45V */ -#define CC_CMP_55 (4<<5) /* 100-0.55V */ -#define CC_CMP_66 (5<<5) /* 101-0.66V */ -#define CC_CMP_95 (6<<5) /* 110-0.95V */ -#define CC_CMP_123 (7<<5) /* 111-1.23V */ - -#define USBPD_IN_HVT (1<<9) -/********************************************************* -* PD pin PB6/PB7 high threshold input mode: -* 1: High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication -* 0: Normal GPIO threshold input -* *******************************************************/ - -/* Control Message Types */ -#define DEF_TYPE_RESERVED 0x00 -#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ -#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ -#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ -#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ -#define DEF_TYPE_PING 0x05 /* Send By: Source */ -#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ -#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ -#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ -#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ -#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ -#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ -#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ -#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ -#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ -#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ -#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ -#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ -#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ -#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ -#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ -#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ -#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ -#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ -#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ -#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ - -/* Data Message Types */ -#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ -#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ -#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ -#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ -#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ -#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ -#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ -#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ -#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ -#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ -#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ -#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ -#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ - -/* Vendor Define Message Command */ -#define DEF_VDM_DISC_IDENT 0x01 -#define DEF_VDM_DISC_SVID 0x02 -#define DEF_VDM_DISC_MODE 0x03 -#define DEF_VDM_ENTER_MODE 0x04 -#define DEF_VDM_EXIT_MODE 0x05 -#define DEF_VDM_ATTENTION 0x06 -#define DEF_VDM_DP_S_UPDATE 0x10 -#define DEF_VDM_DP_CONFIG 0x11 - -/* PD Revision */ -#define DEF_PD_REVISION_10 0x00 -#define DEF_PD_REVISION_20 0x01 -#define DEF_PD_REVISION_30 0x02 - - -/* PD PHY Channel */ -#define DEF_PD_CC1 0x00 -#define DEF_PD_CC2 0x01 - -#define PIN_CC1 GPIO_Pin_6 -#define PIN_CC2 GPIO_Pin_7 - -/* PD Tx Status */ -#define DEF_PD_TX_OK 0x00 -#define DEF_PD_TX_FAIL 0x01 - -/* PDO INDEX */ -#define PDO_INDEX_1 1 -#define PDO_INDEX_2 2 -#define PDO_INDEX_3 3 -#define PDO_INDEX_4 4 -#define PDO_INDEX_5 5 - -/******************************************************************************/ -#define UPD_TMR_TX_96M (160-1) /* timer value for USB PD BMC transmittal @Fsys=96MHz */ -#define UPD_TMR_RX_96M (240-1) /* timer value for USB PD BMC receiving @Fsys=96MHz */ -#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ -#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ -#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ -#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ -#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ -#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ - -#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ -#define PD_RX_SOP0 0x01 /* SOP0 received */ -#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ -#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ - -#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ -#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ -#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ -#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ -#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ - - -#define bCC_CMP_22 0X01 -#define bCC_CMP_45 0X02 -#define bCC_CMP_55 0X04 -#define bCC_CMP_66 0X08 -#define bCC_CMP_95 0X10 -#define bCC_CMP_123 0X20 -#define bCC_CMP_220 0X40 - -/******************************************************************************/ -/* PD State Machine */ -typedef enum -{ - STA_IDLE = 0, /* 0: No task status */ - STA_DISCONNECT, /* 1: Disconnection */ - STA_SRC_CONNECT, /* 2: SRC connect */ - STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */ - STA_RX_SRC_CAP, /* 4: SRC_CAP received */ - STA_TX_REQ, /* 5: Send REQUEST */ - STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */ - STA_RX_ACCEPT, /* 7: ACCEPT received */ - STA_RX_REJECT, /* 8: REJECT received */ - STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */ - STA_RX_PS_RDY, /* 10: PS_RDY received */ - STA_SINK_CONNECT, /* 11: SNK access */ - STA_TX_SRC_CAP, /* 12: Send SRC_CAP */ - STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */ - STA_RX_REQ, /* 14: REQUEST received */ - STA_TX_ACCEPT, /* 15: Send ACCEPT */ - STA_TX_REJECT, /* 16: Send REJECT */ - STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */ - STA_TX_PS_RDY, /* 18: Send PS_RDY */ - STA_TX_DR_SWAP, /* 19: Send DR_SWAP */ - STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */ - STA_TX_PR_SWAP, /* 21: Send PR_SWAP */ - STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */ - STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */ - STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */ - STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */ - STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */ - STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */ - STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */ - STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */ - STA_MODE_SWITCH, /* 30: Mode switching */ - STA_TX_SOFTRST, /* 31: Sending a software reset */ - STA_TX_HRST, /* 32: Send hardware reset */ - STA_PHY_RST, /* 33: PHY reset */ - STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */ -} CC_STATUS; - -/******************************************************************************/ -/* PD Message Header Struct */ -typedef union -{ - struct _Message_Header - { - UINT8 MsgType: 5; /* Message Type */ - UINT8 PDRole: 1; /* 0-UFP; 1-DFP */ - UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */ - UINT8 PRRole: 1; /* 0-Sink; 1-Source */ - UINT8 MsgID: 3; - UINT8 NumDO: 3; - UINT8 Ext: 1; - }Message_Header; - UINT16 Data; -}_Message_Header; - -/******************************************************************************/ -/* Bit definition */ -typedef union -{ - struct _BITS_ - { - UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */ - UINT8 Connected: 1; /* PD Physical Layer Connected Flag */ - UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */ - UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */ - UINT8 PR_Role: 1; /* 0-Sink; 1-Source */ - UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */ - UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */ - UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */ - UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */ - UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */ - UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */ - UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */ - UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */ - UINT8 Recv: 3; - }Bit; - UINT16 Bit_Flag; -}_BIT_FLAG; - -/* PD control-related structures */ -typedef struct _PD_CONTROL -{ - CC_STATUS PD_State; /* PD communication status machine */ - CC_STATUS PD_State_Last; /* PD communication status machine (last value) */ - UINT8 Msg_ID; /* ID of the message sent */ - UINT8 Det_Timer; /* PD connection status detection timing */ - UINT8 Det_Cnt; /* Number of PD connection status detections */ - UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */ - UINT8 HPD_Det_Timer; /* HPD connection detection timing */ - UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */ - UINT16 PD_Comm_Timer; /* PD shared timing variables */ - UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */ - UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */ - UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */ - UINT8 Err_Op_Cnt; /* Exception operation count */ - UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */ - _BIT_FLAG Flag; /* Flag byte bit definition */ -}PD_CONTROL, *pPD_CONTROL; - - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_can.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the + * CAN firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_USBPD_H +#define __CH32L103_USBPD_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +#ifndef VOID +#define VOID void +#endif +#ifndef CONST +#define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif + + /******************************************************************************/ +/* Related macro definitions */ + +/* Define the return value of the function */ +#ifndef SUCCESS +#define SUCCESS 0 +#endif +#ifndef FAIL +#define FAIL 0xFF +#endif + +/* Register Bit Definition */ +/* USBPD->CONFIG */ +#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ +#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ +#define CC_SEL (1<<2) /* Select PD communication port */ +#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ +#define PD_RST_EN (1<<4) /* PD mode reset command enable */ +#define WAKE_POLAR (1<<5) /* PD port wake-up level */ +#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ +#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ +#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ +#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ +#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ +#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ + +/* USBPD->CONTROL */ +#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ +#define BMC_START (1<<1) /* BMC send start signal */ +#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ +#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ +#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ +#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ +#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ +#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ + +/* USBPD->TX_SEL */ +#define TX_SEL1 (0<<0) +#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ +#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ +#define TX_SEL2_Mask (3<<2) +#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ +#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ +#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ +#define TX_SEL3_Mask (3<<4) +#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ +#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ +#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ +#define TX_SEL4_Mask (3<<6) +#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ +#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ +#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ + +/* USBPD->STATUS */ +#define BMC_AUX (3<<0) /* BMC auxiliary information */ +#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ +#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ +#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ +#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ +#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ +#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ +#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ +#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ +#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ +#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ + +/* USBPD->PORT_CC1 */ +/* USBPD->PORT_CC2 */ +#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ +#define CC_PD (1<<1) /* CC port pull-down resistor enable */ +#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ +#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ +#define CC_PU_330 (1<<2) /* 01-330uA */ +#define CC_PU_180 (2<<2) /* 10-180uA */ +#define CC_PU_80 (3<<2) /* 11-80uA */ +#define CC_LVE (1<<4) /* CC port output low voltage enable */ +#define CC_CE (7<<5) /* Enable the voltage comparator on port CC */ +#define CC_NO_CMP (0<<5) /* 000-closed */ +#define CC_CMP_22 (2<<5) /* 010-0.22V */ +#define CC_CMP_45 (3<<5) /* 011-0.45V */ +#define CC_CMP_55 (4<<5) /* 100-0.55V */ +#define CC_CMP_66 (5<<5) /* 101-0.66V */ +#define CC_CMP_95 (6<<5) /* 110-0.95V */ +#define CC_CMP_123 (7<<5) /* 111-1.23V */ + +#define USBPD_IN_HVT (1<<9) +/********************************************************* +* PD pin PB6/PB7 high threshold input mode: +* 1: High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication +* 0: Normal GPIO threshold input +* *******************************************************/ + +/* Control Message Types */ +#define DEF_TYPE_RESERVED 0x00 +#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ +#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_PING 0x05 /* Send By: Source */ +#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ +#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ +#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ +#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ +#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ +#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ +#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ +#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ +#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ +#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ + +/* Data Message Types */ +#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ +#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ +#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ +#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ +#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ +#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ +#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ +#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ +#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ +#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ + +/* Vendor Define Message Command */ +#define DEF_VDM_DISC_IDENT 0x01 +#define DEF_VDM_DISC_SVID 0x02 +#define DEF_VDM_DISC_MODE 0x03 +#define DEF_VDM_ENTER_MODE 0x04 +#define DEF_VDM_EXIT_MODE 0x05 +#define DEF_VDM_ATTENTION 0x06 +#define DEF_VDM_DP_S_UPDATE 0x10 +#define DEF_VDM_DP_CONFIG 0x11 + +/* PD Revision */ +#define DEF_PD_REVISION_10 0x00 +#define DEF_PD_REVISION_20 0x01 +#define DEF_PD_REVISION_30 0x02 + + +/* PD PHY Channel */ +#define DEF_PD_CC1 0x00 +#define DEF_PD_CC2 0x01 + +#define PIN_CC1 GPIO_Pin_6 +#define PIN_CC2 GPIO_Pin_7 + +/* PD Tx Status */ +#define DEF_PD_TX_OK 0x00 +#define DEF_PD_TX_FAIL 0x01 + +/* PDO INDEX */ +#define PDO_INDEX_1 1 +#define PDO_INDEX_2 2 +#define PDO_INDEX_3 3 +#define PDO_INDEX_4 4 +#define PDO_INDEX_5 5 + +/******************************************************************************/ +#define UPD_TMR_TX_96M (160-1) /* timer value for USB PD BMC transmittal @Fsys=96MHz */ +#define UPD_TMR_RX_96M (240-1) /* timer value for USB PD BMC receiving @Fsys=96MHz */ +#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ +#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ +#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ +#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ +#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ +#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ + +#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ +#define PD_RX_SOP0 0x01 /* SOP0 received */ +#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ +#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ + +#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ +#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ +#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ +#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ +#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ + + +#define bCC_CMP_22 0X01 +#define bCC_CMP_45 0X02 +#define bCC_CMP_55 0X04 +#define bCC_CMP_66 0X08 +#define bCC_CMP_95 0X10 +#define bCC_CMP_123 0X20 +#define bCC_CMP_220 0X40 + +/******************************************************************************/ +/* PD State Machine */ +typedef enum +{ + STA_IDLE = 0, /* 0: No task status */ + STA_DISCONNECT, /* 1: Disconnection */ + STA_SRC_CONNECT, /* 2: SRC connect */ + STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */ + STA_RX_SRC_CAP, /* 4: SRC_CAP received */ + STA_TX_REQ, /* 5: Send REQUEST */ + STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */ + STA_RX_ACCEPT, /* 7: ACCEPT received */ + STA_RX_REJECT, /* 8: REJECT received */ + STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */ + STA_RX_PS_RDY, /* 10: PS_RDY received */ + STA_SINK_CONNECT, /* 11: SNK access */ + STA_TX_SRC_CAP, /* 12: Send SRC_CAP */ + STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */ + STA_RX_REQ, /* 14: REQUEST received */ + STA_TX_ACCEPT, /* 15: Send ACCEPT */ + STA_TX_REJECT, /* 16: Send REJECT */ + STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */ + STA_TX_PS_RDY, /* 18: Send PS_RDY */ + STA_TX_DR_SWAP, /* 19: Send DR_SWAP */ + STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */ + STA_TX_PR_SWAP, /* 21: Send PR_SWAP */ + STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */ + STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */ + STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */ + STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */ + STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */ + STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */ + STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */ + STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */ + STA_MODE_SWITCH, /* 30: Mode switching */ + STA_TX_SOFTRST, /* 31: Sending a software reset */ + STA_TX_HRST, /* 32: Send hardware reset */ + STA_PHY_RST, /* 33: PHY reset */ + STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */ +} CC_STATUS; + +/******************************************************************************/ +/* PD Message Header Struct */ +typedef union +{ + struct _Message_Header + { + UINT8 MsgType: 5; /* Message Type */ + UINT8 PDRole: 1; /* 0-UFP; 1-DFP */ + UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */ + UINT8 PRRole: 1; /* 0-Sink; 1-Source */ + UINT8 MsgID: 3; + UINT8 NumDO: 3; + UINT8 Ext: 1; + }Message_Header; + UINT16 Data; +}_Message_Header; + +/******************************************************************************/ +/* Bit definition */ +typedef union +{ + struct _BITS_ + { + UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */ + UINT8 Connected: 1; /* PD Physical Layer Connected Flag */ + UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */ + UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */ + UINT8 PR_Role: 1; /* 0-Sink; 1-Source */ + UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */ + UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */ + UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */ + UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */ + UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */ + UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */ + UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */ + UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */ + UINT8 Recv: 3; + }Bit; + UINT16 Bit_Flag; +}_BIT_FLAG; + +/* PD control-related structures */ +typedef struct _PD_CONTROL +{ + CC_STATUS PD_State; /* PD communication status machine */ + CC_STATUS PD_State_Last; /* PD communication status machine (last value) */ + UINT8 Msg_ID; /* ID of the message sent */ + UINT8 Det_Timer; /* PD connection status detection timing */ + UINT8 Det_Cnt; /* Number of PD connection status detections */ + UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */ + UINT8 HPD_Det_Timer; /* HPD connection detection timing */ + UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */ + UINT16 PD_Comm_Timer; /* PD shared timing variables */ + UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */ + UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */ + UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */ + UINT8 Err_Op_Cnt; /* Exception operation count */ + UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */ + _BIT_FLAG Flag; /* Flag byte bit definition */ +}PD_CONTROL, *pPD_CONTROL; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_wwdg.h b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_wwdg.h index a97fe3f..213efd2 100644 --- a/system/CH32L10x/SRC/Peripheral/inc/ch32l103_wwdg.h +++ b/system/CH32L10x/SRC/Peripheral/inc/ch32l103_wwdg.h @@ -1,41 +1,41 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_wwdg.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file contains all the functions prototypes for the WWDG - * firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_WWDG_H -#define __CH32L103_WWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32l103.h" - -/* WWDG_Prescaler */ -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) - -void WWDG_DeInit(void); -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); -void WWDG_Enable(uint8_t Counter); -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_wwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file contains all the functions prototypes for the WWDG + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_WWDG_H +#define __CH32L103_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32l103.h" + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_adc.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_adc.c index ce3919a..4c9cadf 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_adc.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_adc.c @@ -1,1384 +1,1344 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_adc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/19 - * Description : This file provides all the ADC firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_adc.h" -#include "ch32l103_rcc.h" - -/* CFG Keys */ -#define CFG_KEY1 ((uint32_t)0x45670123) -#define CFG_KEY2 ((uint32_t)0xCDEF89AB) - -/* ADC DISCNUM mask */ -#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) -#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) - -/* ADC JAUTO mask */ -#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) -#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) - -/* ADC AWDCH mask */ -#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) - -/* CTLR1 register Mask */ -#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) - -/* ADC ADON mask */ -#define CTLR2_ADON_Set ((uint32_t)0x00000001) -#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CTLR2_DMA_Set ((uint32_t)0x00000100) -#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) - -/* ADC RSTCAL mask */ -#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) - -/* ADC CAL mask */ -#define CTLR2_CAL_Set ((uint32_t)0x00000004) - -/* ADC SWSTART mask */ -#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) - -/* ADC EXTTRIG mask */ -#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) - -/* ADC JEXTSEL mask */ -#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTART mask */ -#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) - -/* ADC TSPD mask */ -#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) -#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) - -/* CTLR2 register Mask */ -#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) - -/* ADC SQx mask */ -#define RSQR3_SQ_Set ((uint32_t)0x0000001F) -#define RSQR2_SQ_Set ((uint32_t)0x0000001F) -#define RSQR1_SQ_Set ((uint32_t)0x0000001F) - -/* RSQR1 register Mask */ -#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define ISQR_JSQ_Set ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define ISQR_JL_Set ((uint32_t)0x00300000) -#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) -#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) - -/* ADC IDATARx registers offset */ -#define IDATAR_Offset ((uint8_t)0x28) - -/* ADC1 RDATAR register base address */ -#define RDATAR_ADDRESS ((uint32_t)0x4001244C) - - -/********************************************************************* - * @fn ADC_DeInit - * - * @brief Deinitializes the ADCx peripheral registers to their default - * reset values. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return none - */ -void ADC_DeInit(ADC_TypeDef *ADCx) -{ - if(ADCx == ADC1) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_ADC1, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_ADC1, DISABLE); - } -} - -/********************************************************************* - * @fn ADC_Init - * - * @brief Initializes the ADCx peripheral according to the specified - * parameters in the ADC_InitStruct. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | - (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); - ADCx->CTLR1 = tmpreg1; - - tmpreg1 = ADCx->CTLR2; - tmpreg1 &= CTLR2_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - ADCx->CTLR2 = tmpreg1; - - tmpreg1 = ADCx->RSQR1; - tmpreg1 &= RSQR1_CLEAR_Mask; - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); - tmpreg1 |= (uint32_t)tmpreg2 << 20; - ADCx->RSQR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_StructInit - * - * @brief Fills each ADC_InitStruct member with its default value. - * - * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) -{ - ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStruct->ADC_NbrOfChannel = 1; -} - -/********************************************************************* - * @fn ADC_Cmd - * - * @brief Enables or disables the specified ADC peripheral. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_ADON_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_ADON_Reset; - } -} - -/********************************************************************* - * @fn ADC_DMACmd - * - * @brief Enables or disables the specified ADC DMA request. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_DMA_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_DMA_Reset; - } -} - -/********************************************************************* - * @fn ADC_ITConfig - * - * @brief Enables or disables the specified ADC interrupts. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)ADC_IT; - - if(NewState != DISABLE) - { - ADCx->CTLR1 |= itmask; - } - else - { - ADCx->CTLR1 &= (~(uint32_t)itmask); - } -} - -/********************************************************************* - * @fn ADC_ResetCalibration - * - * @brief Resets the selected ADC calibration registers. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return none - */ -void ADC_ResetCalibration(ADC_TypeDef *ADCx) -{ - ADCx->CTLR2 |= CTLR2_RSTCAL_Set; -} - -/********************************************************************* - * @fn ADC_GetResetCalibrationStatus - * - * @brief Gets the selected ADC reset calibration registers status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_StartCalibration - * - * @brief Starts the selected ADC calibration process. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return None - */ -void ADC_StartCalibration(ADC_TypeDef *ADCx) -{ - ADCx->CTLR2 |= CTLR2_CAL_Set; -} - -/********************************************************************* - * @fn ADC_GetCalibrationStatus - * - * @brief Gets the selected ADC calibration status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_SoftwareStartConvCmd - * - * @brief Enables or disables the selected ADC software start conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartConvStatus - * - * @brief Gets the selected ADC Software start conversion Status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus - SET or RESET. - */ - -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_DiscModeChannelCountConfig - * - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * Number - specifies the discontinuous mode regular channel - * count value(1-8). - * - * @return None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_DISCNUM_Reset; - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - ADCx->CTLR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_DiscModeCmd - * - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_DISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_DISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_RegularChannelConfig - * - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_16 - ADC Channel16 selected. - * ADC_Channel_17 - ADC Channel17 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_CyclesMode0 - Sample time equal to 1.5 cycles(CFG bit[5]-ADC_LP=0). - * - Sample time equal to 7.5 cycles(CFG bit[5]-ADC_LP=1). - * ADC_SampleTime_CyclesMode1 - Sample time equal to 7.5 cycles(CFG bit[5]-ADC_LP=0). - * - Sample time equal to 11.5 cycles(CFG bit[5]-ADC_LP=1). - * ADC_SampleTime_CyclesMode2 - Sample time equal to 13.5 cycles(CFG bit[5]-ADC_LP=0). - * - Sample time equal to 17.5 cycles(CFG bit[5]-ADC_LP=1). - * ADC_SampleTime_CyclesMode3 - Sample time equal to 28.5 cycles(CFG bit[5]-ADC_LP=0). - * - Sample time equal to 27.5 cycles(CFG bit[5]-ADC_LP=1). - * ADC_SampleTime_CyclesMode4 - Sample time equal to 41.5 cycles(CFG bit[5]-ADC_LP=0). - * - Sample time equal to 47.5 cycles(CFG bit[5]-ADC_LP=1). - * ADC_SampleTime_CyclesMode5 - Sample time equal to 55.5 cycles(CFG bit[5]-ADC_LP=0). - * - Sample time equal to 55.5 cycles(CFG bit[5]-ADC_LP=1). - * ADC_SampleTime_CyclesMode6 - Sample time equal to 71.5 cycles(CFG bit[5]-ADC_LP=0). - * - Sample time equal to 71.5 cycles(CFG bit[5]-ADC_LP=1). - * ADC_SampleTime_CyclesMode7 - Sample time equal to 239.5 cycles(CFG bit[5]-ADC_LP=0). - * - Sample time equal to 239.5 cycles(CFG bit[5]-ADC_LP=1). - * - * @return None - */ -void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - if(Rank < 7) - { - tmpreg1 = ADCx->RSQR3; - tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - tmpreg1 |= tmpreg2; - ADCx->RSQR3 = tmpreg1; - } - else if(Rank < 13) - { - tmpreg1 = ADCx->RSQR2; - tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - tmpreg1 |= tmpreg2; - ADCx->RSQR2 = tmpreg1; - } - else - { - tmpreg1 = ADCx->RSQR1; - tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - tmpreg1 |= tmpreg2; - ADCx->RSQR1 = tmpreg1; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigConvCmd - * - * @brief Enables or disables the ADCx conversion through external trigger. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetConversionValue - * - * @brief Returns the last ADCx conversion result data for regular channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return ADCx->RDATAR - The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) -{ - return (uint16_t)ADCx->RDATAR; -} - -/********************************************************************* - * @fn ADC_GetDualModeConversionValue - * - * @brief Returns the last ADC1 and conversion result data in dual mode. - * - * @return RDATAR_ADDRESS - The Data conversion value. - */ -uint32_t ADC_GetDualModeConversionValue(void) -{ - return (*(__IO uint32_t *)RDATAR_ADDRESS); -} - -/********************************************************************* - * @fn ADC_AutoInjectedConvCmd - * - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JAUTO_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JAUTO_Reset; - } -} - -/********************************************************************* - * @fn ADC_InjectedDiscModeCmd - * - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JDISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvConfig - * - * @brief Configures the ADCx external trigger for injected channels conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start - * injected conversion. - * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. - * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. - * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. - * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. - * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. - * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. - * ADC_ExternalTrigInjecConv_Ext_IT15 - External interrupt - * line 15 event selected. - * ADC_ExternalTrigInjecConv_None - Injected conversion started - * by software and not by external trigger. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR2; - tmpreg &= CTLR2_JEXTSEL_Reset; - tmpreg |= ADC_ExternalTrigInjecConv; - ADCx->CTLR2 = tmpreg; -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvCmd - * - * @brief Enables or disables the ADCx injected channels conversion through - * external trigger. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_SoftwareStartInjectedConvCmd - * - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartInjectedConvCmdStatus - * - * @brief Gets the selected ADC Software start injected conversion Status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_InjectedChannelConfig - * - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_16 - ADC Channel16 selected. - * ADC_Channel_17 - ADC Channel17 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 4. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. - * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. - * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. - * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. - * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. - * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. - * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. - * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. - * - * @return None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - tmpreg1 = ADCx->ISQR; - tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; - tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 |= tmpreg2; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_InjectedSequencerLengthConfig - * - * @brief Configures the sequencer length for injected channels. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * Length - The sequencer length. - * This parameter must be a number between 1 to 4. - * - * @return None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->ISQR; - tmpreg1 &= ISQR_JL_Reset; - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_SetInjectedOffset - * - * @brief Set the injected channels conversion value offset. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InjectedChannel: the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * Offset - the offset value for the selected ADC injected channel. - * This parameter must be a 12bit value. - * - * @return None - */ -void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - *(__IO uint32_t *)tmp = (uint32_t)Offset; -} - -/********************************************************************* - * @fn ADC_GetInjectedConversionValue - * - * @brief Returns the ADC injected channel conversion result. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InjectedChannel - the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * - * @return tmp - The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + IDATAR_Offset; - - return (uint16_t)(*(__IO uint32_t *)tmp); -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogCmd - * - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_AnalogWatchdog - the ADC analog watchdog configuration. - * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a - * single regular channel. - * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a - * single injected channel. - * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog - * on a single regular or injected channel. - * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all - * regular channel. - * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all - * injected channel. - * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on - * all regular and injected channels. - * ADC_AnalogWatchdog_None - No channel guarded by the analog - * watchdog. - * - * @return none - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDMode_Reset; - tmpreg |= ADC_AnalogWatchdog; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogThresholdsConfig - * - * @brief Configures the high and low thresholds of the analog watchdog. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * HighThreshold - the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * LowThreshold - the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * - * @return none - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - ADCx->WDHTR = HighThreshold; - ADCx->WDLTR = LowThreshold; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogSingleChannelConfig - * - * @brief Configures the analog watchdog guarded single channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_16 - ADC Channel16 selected. - * ADC_Channel_17 - ADC Channel17 selected. - * - * @return None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDCH_Reset; - tmpreg |= ADC_Channel; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_TempSensorVrefintCmd - * - * @brief Enables or disables the temperature sensor and Vrefint channel. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADC1->CTLR2 |= CTLR2_TSVREFE_Set; - } - else - { - ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetFlagStatus - * - * @brief Checks whether the specified ADC flag is set or not. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to check. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearFlag - * - * @brief Clears the ADCx's pending flags. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to clear. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return none - */ -void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - ADCx->STATR = ~(uint32_t)ADC_FLAG; -} - -/********************************************************************* - * @fn ADC_GetITStatus - * - * @brief Checks whether the specified ADC interrupt has occurred or not. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt source to check. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return FlagStatus: SET or RESET. - */ -ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - itmask = ADC_IT >> 8; - enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); - - if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearITPendingBit - * - * @brief Clears the ADCx's interrupt pending bits. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt pending bit to clear. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return none - */ -void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)(ADC_IT >> 8); - ADCx->STATR = ~(uint32_t)itmask; -} - -/********************************************************************* - * @fn TempSensor_Volt_To_Temper - * - * @brief Internal Temperature Sensor Voltage to temperature. - * - * @param Value - Voltage Value(mv). - * - * @return Temper - Temperature Value. - */ -s32 TempSensor_Volt_To_Temper(s32 Value) -{ - s32 Temper, Refer_Volt, Refer_Temper; - s32 k = 42; - - Refer_Volt = (s32)((TS_Val) & 0x0000FFFF); - Refer_Temper = (s32)(((TS_Val) >> 16) & 0x0000FFFF); - - Temper = Refer_Temper - ((Value - Refer_Volt) * 10 + (k >> 1)) / k; - - return Temper; -} - -/********************************************************************* - * @fn ADC_BufferCmd - * - * @brief Enables or disables the ADCx buffer. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= (1 << 26); - } - else - { - ADCx->CTLR1 &= ~(1 << 26); - } -} - -/********************************************************************* - * @fn ADC_TKey_WakeUpCmd - * - * @brief Enables or disables TKey wake up of the selected ADC channel - * and Configures IO mode. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * IO_Mode - IO state before wake up - * ADC_TKey_WakeUp_Mode0 - * ADC_TKey_WakeUp_Mode1 - * ADC_TKey_WakeUp_Mode2 - * ADC_TKey_WakeUp_Mode3 - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_TKey_WakeUpCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint32_t IO_Mode, FunctionalState NewState) -{ - ADCx->CFG &= ~ADC_TKey_WakeUp_Mode3; - ADCx->CFG |= IO_Mode; - - if(NewState != DISABLE) - { - ADCx->CFG |= ((1<<21) << ADC_Channel); - } - else - { - ADCx->CFG &= ~((1<<21) << ADC_Channel); - } -} - -/********************************************************************* - * @fn ADC_TKey_ChannelxMulShieldCmd - * - * @brief Enables or disables TKey Multiplex shielding of the selected ADC channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_TKey_ChannelxMulShieldCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CFG |= ((1<<9)<< ADC_Channel); - } - else - { - ADCx->CFG &= ~((1<<9)<< ADC_Channel); - } -} - -/********************************************************************* - * @fn ADC_TKey_MulShieldCmd - * - * @brief Enables or disables the TKey Multiplex shielding. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_TKey_MulShieldCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CFG |= (1 << 8); - } - else - { - ADCx->CFG &= ~(1 << 8); - } -} - -/********************************************************************* - * @fn ADC_DutyDelayCmd - * - * @brief Enables or disables the Duty delay. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CFG |= (1 << 7); - } - else - { - ADCx->CFG &= ~(1 << 7); - } -} - -/********************************************************************* - * @fn ADC_FIFO_Cmd - * - * @brief Enables or disables the FIFO. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_FIFO_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CFG |= (1 << 6); - } - else - { - ADCx->CFG &= ~(1 << 6); - } -} - -/********************************************************************* - * @fn ADC_Sample_ModeConfig - * - * @brief Configures the ADC Sample Mode. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Sample_Mode - Sample Mode. - * ADC_Sample_NoOver_1M_Mode - sampling rate no over 1M(<=1M) mode. - * ADC_Sample_Over_1M_Mode - sampling rate over 1M(>1M) mode. - * - * @return none - */ -void ADC_Sample_ModeConfig(ADC_TypeDef *ADCx, uint32_t ADC_Sample_Mode) -{ - ADCx->CFG &= ~ADC_Sample_Over_1M_Mode; - ADCx->CFG |= ADC_Sample_Mode; -} - -/********************************************************************* - * @fn ADC_OffsetCalibrationConfig - * - * @brief Configures the Offset Calibration. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return None - */ -void ADC_OffsetCalibrationConfig(ADC_TypeDef *ADCx) -{ - uint16_t tmp; - - tmp = ADC_Trim; - ADCx->CFG &= ~0x0000000F; - ADCx->CFG |= (uint32_t)((tmp & 0x07) | (((tmp & 0x8000)^0x8000) >> 12)); -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogResetCmd - * - * @brief Enables or disables the analog watch dog reset function. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CFG |= (1 << 4); - } - else - { - ADCx->CFG &= ~(1 << 4); - } -} - -/********************************************************************* - * @fn Get_CalibrationValue - * - * @brief Get ADCx Calibration Value. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return CalibrationValue - */ -int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) -{ - __IO uint8_t i, j; - uint16_t buf[10]; - __IO uint16_t t; - FLASH->KEYR = CFG_KEY1; - FLASH->KEYR = CFG_KEY2; - FLASH->MODEKEYR = CFG_KEY1; - FLASH->OBKEYR = CFG_KEY2; - while((*(vu32*)0x40022034) & (1<<29)); // wait unlock - - *(vu32*)0x4002202C |= (1<<9); - (*(vu32*)0x40022034) |= (1<<29); //lock - while((*(vu32*)0x40022034) & (1<<29) == 0); //wait lock - ADC1->CTLR2|=(7<<17); - ADC_Cmd(ADC1, ENABLE); - ADC_FIFO_Cmd(ADC1, ENABLE); - ADC_ResetCalibration(ADC1); - while(ADC_GetResetCalibrationStatus(ADC1)); - ADC_StartCalibration(ADC1); - while(ADC_GetCalibrationStatus(ADC1)); - ADC_RegularChannelConfig(ADC1, ADC_Channel_CalInternal, 1, ADC_SampleTime_CyclesMode0); - for(i = 0; i < 10; i++) - { - ADC_SoftwareStartConvCmd(ADC1, ENABLE); - while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC)); - buf[i] = ADC_GetConversionValue(ADC1); - } - for(i = 0; i < 10; i++) - { - for(j = 0; j < 9; j++) - { - if(buf[j] > buf[j + 1]) - { - t = buf[j]; - buf[j] = buf[j + 1]; - buf[j + 1] = t; - } - } - } - - t = 0; - for(i = 0; i < 6; i++) - { - t += buf[i + 2]; - } - t = (t / 6) + ((t % 6) / 3); - ADC_Cmd(ADC1, DISABLE); - return (int16_t)(2048 - (int16_t)t); -} - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_adc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/06 + * Description : This file provides all the ADC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_adc.h" +#include "ch32l103_rcc.h" + +/* CFG Keys */ +#define CFG_KEY1 ((uint32_t)0x45670123) +#define CFG_KEY2 ((uint32_t)0xCDEF89AB) + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_ADC1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_ADC1, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | + (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_ResetCalibration + * + * @brief Resets the selected ADC calibration registers. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_ResetCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_RSTCAL_Set; +} + +/********************************************************************* + * @fn ADC_GetResetCalibrationStatus + * + * @brief Gets the selected ADC reset calibration registers status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_StartCalibration + * + * @brief Starts the selected ADC calibration process. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return None + */ +void ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_CAL_Set; +} + +/********************************************************************* + * @fn ADC_GetCalibrationStatus + * + * @brief Gets the selected ADC calibration status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ + +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_CyclesMode0 - Sample time equal to 1.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 7.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode1 - Sample time equal to 7.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 11.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode2 - Sample time equal to 13.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 17.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode3 - Sample time equal to 28.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 27.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode4 - Sample time equal to 41.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 47.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode5 - Sample time equal to 55.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 55.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode6 - Sample time equal to 71.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 71.5 cycles(CFG bit[5]-ADC_LP=1). + * ADC_SampleTime_CyclesMode7 - Sample time equal to 239.5 cycles(CFG bit[5]-ADC_LP=0). + * - Sample time equal to 239.5 cycles(CFG bit[5]-ADC_LP=1). + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_GetDualModeConversionValue + * + * @brief Returns the last ADC1 and conversion result data in dual mode. + * + * @return RDATAR_ADDRESS - The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + return (*(__IO uint32_t *)RDATAR_ADDRESS); +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. + * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. + * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. + * ADC_ExternalTrigInjecConv_Ext_IT15 - External interrupt + * line 15 event selected. + * ADC_ExternalTrigInjecConv_None - Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 4. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 12bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_TempSensorVrefintCmd + * + * @brief Enables or disables the temperature sensor and Vrefint channel. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADC1->CTLR2 |= CTLR2_TSVREFE_Set; + } + else + { + ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn TempSensor_Volt_To_Temper + * + * @brief Internal Temperature Sensor Voltage to temperature. + * + * @param Value - Voltage Value(mv). + * + * @return Temper - Temperature Value. + */ +s32 TempSensor_Volt_To_Temper(s32 Value) +{ + s32 Temper, Refer_Volt, Refer_Temper; + s32 k = 42; + + Refer_Volt = (s32)((TS_Val) & 0x0000FFFF); + Refer_Temper = (s32)(((TS_Val) >> 16) & 0x0000FFFF); + + Temper = Refer_Temper - ((Value - Refer_Volt) * 10 + (k >> 1)) / k; + + return Temper; +} + +/********************************************************************* + * @fn ADC_BufferCmd + * + * @brief Enables or disables the ADCx buffer. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= (1 << 26); + } + else + { + ADCx->CTLR1 &= ~(1 << 26); + } +} + +/********************************************************************* + * @fn ADC_TKey_ChannelxMulShieldCmd + * + * @brief Enables or disables TKey Multiplex shielding of the selected ADC channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TKey_ChannelxMulShieldCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CFG |= ((1<<9)<< ADC_Channel); + } + else + { + ADCx->CFG &= ~((1<<9)<< ADC_Channel); + } +} + +/********************************************************************* + * @fn ADC_TKey_MulShieldCmd + * + * @brief Enables or disables the TKey Multiplex shielding. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TKey_MulShieldCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CFG |= (1 << 8); + } + else + { + ADCx->CFG &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn ADC_DutyDelayCmd + * + * @brief Enables or disables the Duty delay. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CFG |= (1 << 7); + } + else + { + ADCx->CFG &= ~(1 << 7); + } +} + +/********************************************************************* + * @fn ADC_FIFO_Cmd + * + * @brief Enables or disables the FIFO. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_FIFO_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + FLASH->KEYR = CFG_KEY1; + FLASH->KEYR = CFG_KEY2; + FLASH->MODEKEYR = CFG_KEY1; + FLASH->OBKEYR = CFG_KEY2; + while((*(vu32*)0x40022034) & (1<<29)); // wait unlock + + *(vu32*)0x4002202C |= (1<<9); //offset calibration + (*(vu32*)0x40022034) |= (1<<29); //lock + while((*(vu32*)0x40022034) & (1<<29) == 0); //wait lock + + if(NewState != DISABLE) + { + ADCx->CFG |= (1 << 6); + } + else + { + ADCx->CFG &= ~(1 << 6); + } +} + +/********************************************************************* + * @fn ADC_Sample_ModeConfig + * + * @brief Configures the ADC Sample Mode. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Sample_Mode - Sample Mode. + * ADC_Sample_NoOver_1M_Mode - sampling rate no over 1M(<=1M) mode. + * ADC_Sample_Over_1M_Mode - sampling rate over 1M(>1M) mode. + * + * @return none + */ +void ADC_Sample_ModeConfig(ADC_TypeDef *ADCx, uint32_t ADC_Sample_Mode) +{ + ADCx->CFG &= ~ADC_Sample_Over_1M_Mode; + ADCx->CFG |= ADC_Sample_Mode; +} + +/********************************************************************* + * @fn ADC_OffsetCalibrationConfig + * + * @brief Configures the Offset Calibration. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return None + */ +void ADC_OffsetCalibrationConfig(ADC_TypeDef *ADCx) +{ + uint16_t tmp; + + tmp = ADC_Trim; + ADCx->CFG &= ~0x0000000F; + ADCx->CFG |= (uint32_t)((tmp & 0x07) | (((tmp & 0x8000)^0x8000) >> 12)); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogResetCmd + * + * @brief Enables or disables the analog watch dog reset function. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CFG |= (1 << 4); + } + else + { + ADCx->CFG &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn Get_CalibrationValue + * + * @brief Get ADCx Calibration Value. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return CalibrationValue + */ +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) +{ + __IO uint8_t i, j; + uint16_t buf[10]; + __IO uint16_t t; + + ADC1->CTLR2|=(7<<17); + ADC_Cmd(ADC1, ENABLE); + ADC_FIFO_Cmd(ADC1, ENABLE); + ADC_ResetCalibration(ADC1); + while(ADC_GetResetCalibrationStatus(ADC1)); + ADC_StartCalibration(ADC1); + while(ADC_GetCalibrationStatus(ADC1)); + ADC_RegularChannelConfig(ADC1, ADC_Channel_CalInternal, 1, ADC_SampleTime_CyclesMode0); + for(i = 0; i < 10; i++) + { + ADC_SoftwareStartConvCmd(ADC1, ENABLE); + while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC)); + buf[i] = ADC_GetConversionValue(ADC1); + } + for(i = 0; i < 10; i++) + { + for(j = 0; j < 9; j++) + { + if(buf[j] > buf[j + 1]) + { + t = buf[j]; + buf[j] = buf[j + 1]; + buf[j + 1] = t; + } + } + } + + t = 0; + for(i = 0; i < 6; i++) + { + t += buf[i + 2]; + } + t = (t / 6) + ((t % 6) / 3); + ADC_Cmd(ADC1, DISABLE); + return (int16_t)(2048 - (int16_t)t); +} + + diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_bkp.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_bkp.c index ae9869b..7690cf9 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_bkp.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_bkp.c @@ -1,244 +1,244 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_bkp.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the BKP firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_bkp.h" -#include "ch32l103_rcc.h" - -/* BKP registers bit mask */ - -/* OCTLR register bit mask */ -#define OCTLR_CAL_MASK ((uint16_t)0xFF80) -#define OCTLR_MASK ((uint16_t)0xFC7F) - -/********************************************************************* - * @fn BKP_DeInit - * - * @brief Deinitializes the BKP peripheral registers to their default reset values. - * - * @return none - */ -void BKP_DeInit(void) -{ - RCC_BackupResetCmd(ENABLE); - RCC_BackupResetCmd(DISABLE); -} - -/********************************************************************* - * @fn BKP_TamperPinLevelConfig - * - * @brief Configures the Tamper Pin active level. - * - * @param BKP_TamperPinLevel - specifies the Tamper Pin active level. - * BKP_TamperPinLevel_High - Tamper pin active on high level. - * BKP_TamperPinLevel_Low - Tamper pin active on low level. - * - * @return none - */ -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) -{ - if(BKP_TamperPinLevel) - { - BKP->TPCTLR |= (1 << 1); - } - else - { - BKP->TPCTLR &= ~(1 << 1); - } -} - -/********************************************************************* - * @fn BKP_TamperPinCmd - * - * @brief Enables or disables the Tamper Pin activation. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void BKP_TamperPinCmd(FunctionalState NewState) -{ - if(NewState) - { - BKP->TPCTLR |= (1 << 0); - } - else - { - BKP->TPCTLR &= ~(1 << 0); - } -} - -/********************************************************************* - * @fn BKP_ITConfig - * - * @brief Enables or disables the Tamper Pin Interrupt. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void BKP_ITConfig(FunctionalState NewState) -{ - if(NewState) - { - BKP->TPCSR |= (1 << 2); - } - else - { - BKP->TPCSR &= ~(1 << 2); - } -} - -/********************************************************************* - * @fn BKP_RTCOutputConfig - * - * @brief Select the RTC output source to output on the Tamper pin. - * - * @param BKP_RTCOutputSource - specifies the RTC output source. - * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. - * BKP_RTCOutputSource_CalibClock - output the RTC clock with - * frequency divided by 64 on the Tamper pin. - * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal - * on the Tamper pin. - * BKP_RTCOutputSource_Second - output the RTC Second pulse - * signal on the Tamper pin. - * - * @return none - */ -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) -{ - uint16_t tmpreg = 0; - - tmpreg = BKP->OCTLR; - tmpreg &= OCTLR_MASK; - tmpreg |= BKP_RTCOutputSource; - BKP->OCTLR = tmpreg; -} - -/********************************************************************* - * @fn BKP_SetRTCCalibrationValue - * - * @brief Sets RTC Clock Calibration value. - * - * @param CalibrationValue - specifies the RTC Clock Calibration value. - * This parameter must be a number between 0 and 0x1F. - * - * @return none - */ -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) -{ - uint16_t tmpreg = 0; - - tmpreg = BKP->OCTLR; - tmpreg &= OCTLR_CAL_MASK; - tmpreg |= CalibrationValue; - BKP->OCTLR = tmpreg; -} - -/********************************************************************* - * @fn BKP_WriteBackupRegister - * - * @brief Writes user data to the specified Data Backup Register. - * - * @param BKP_DR - specifies the Data Backup Register. - * Data - data to write. - * - * @return none - */ -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - *(__IO uint32_t *)tmp = Data; -} - -/********************************************************************* - * @fn BKP_ReadBackupRegister - * - * @brief Reads data from the specified Data Backup Register. - * - * @param BKP_DR - specifies the Data Backup Register. - * This parameter can be BKP_DRx where x=[1, 42]. - * - * @return none - */ -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - return (*(__IO uint16_t *)tmp); -} - -/********************************************************************* - * @fn BKP_GetFlagStatus - * - * @brief Checks whether the Tamper Pin Event flag is set or not. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus BKP_GetFlagStatus(void) -{ - if(BKP->TPCSR & (1 << 8)) - { - return SET; - } - else - { - return RESET; - } -} - -/********************************************************************* - * @fn BKP_ClearFlag - * - * @brief Clears Tamper Pin Event pending flag. - * - * @return none - */ -void BKP_ClearFlag(void) -{ - BKP->TPCSR |= BKP_CTE; -} - -/********************************************************************* - * @fn BKP_GetITStatus - * - * @brief Checks whether the Tamper Pin Interrupt has occurred or not. - * - * @return ITStatus - SET or RESET. - */ -ITStatus BKP_GetITStatus(void) -{ - if(BKP->TPCSR & (1 << 9)) - { - return SET; - } - else - { - return RESET; - } -} - -/********************************************************************* - * @fn BKP_ClearITPendingBit - * - * @brief Clears Tamper Pin Interrupt pending bit. - * - * @return none - */ -void BKP_ClearITPendingBit(void) -{ - BKP->TPCSR |= BKP_CTI; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_bkp.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the BKP firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_bkp.h" +#include "ch32l103_rcc.h" + +/* BKP registers bit mask */ + +/* OCTLR register bit mask */ +#define OCTLR_CAL_MASK ((uint16_t)0xFF80) +#define OCTLR_MASK ((uint16_t)0xFC7F) + +/********************************************************************* + * @fn BKP_DeInit + * + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * + * @return none + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/********************************************************************* + * @fn BKP_TamperPinLevelConfig + * + * @brief Configures the Tamper Pin active level. + * + * @param BKP_TamperPinLevel - specifies the Tamper Pin active level. + * BKP_TamperPinLevel_High - Tamper pin active on high level. + * BKP_TamperPinLevel_Low - Tamper pin active on low level. + * + * @return none + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + if(BKP_TamperPinLevel) + { + BKP->TPCTLR |= (1 << 1); + } + else + { + BKP->TPCTLR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn BKP_TamperPinCmd + * + * @brief Enables or disables the Tamper Pin activation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCTLR |= (1 << 0); + } + else + { + BKP->TPCTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn BKP_ITConfig + * + * @brief Enables or disables the Tamper Pin Interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_ITConfig(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCSR |= (1 << 2); + } + else + { + BKP->TPCSR &= ~(1 << 2); + } +} + +/********************************************************************* + * @fn BKP_RTCOutputConfig + * + * @brief Select the RTC output source to output on the Tamper pin. + * + * @param BKP_RTCOutputSource - specifies the RTC output source. + * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. + * BKP_RTCOutputSource_CalibClock - output the RTC clock with + * frequency divided by 64 on the Tamper pin. + * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal + * on the Tamper pin. + * BKP_RTCOutputSource_Second - output the RTC Second pulse + * signal on the Tamper pin. + * + * @return none + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_MASK; + tmpreg |= BKP_RTCOutputSource; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_SetRTCCalibrationValue + * + * @brief Sets RTC Clock Calibration value. + * + * @param CalibrationValue - specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_CAL_MASK; + tmpreg |= CalibrationValue; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_WriteBackupRegister + * + * @brief Writes user data to the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * Data - data to write. + * + * @return none + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn BKP_ReadBackupRegister + * + * @brief Reads data from the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * This parameter can be BKP_DRx where x=[1, 42]. + * + * @return none + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn BKP_GetFlagStatus + * + * @brief Checks whether the Tamper Pin Event flag is set or not. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus BKP_GetFlagStatus(void) +{ + if(BKP->TPCSR & (1 << 8)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearFlag + * + * @brief Clears Tamper Pin Event pending flag. + * + * @return none + */ +void BKP_ClearFlag(void) +{ + BKP->TPCSR |= BKP_CTE; +} + +/********************************************************************* + * @fn BKP_GetITStatus + * + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * + * @return ITStatus - SET or RESET. + */ +ITStatus BKP_GetITStatus(void) +{ + if(BKP->TPCSR & (1 << 9)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearITPendingBit + * + * @brief Clears Tamper Pin Interrupt pending bit. + * + * @return none + */ +void BKP_ClearITPendingBit(void) +{ + BKP->TPCSR |= BKP_CTI; +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_can.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_can.c index 67c4a1a..74bc94d 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_can.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_can.c @@ -1,1697 +1,1697 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_can.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the CAN firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_can.h" -#include "ch32l103_rcc.h" - -/* CAN CTLR Register bits */ -#define CTLR_DBF ((uint32_t)0x00010000) - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) - -/* CAN FCTLR Register bits */ -#define FCTLR_FINIT ((uint32_t)0x00000001) - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) - - -/* Flags in TSTATR register */ -#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) -/* Flags in RFIFO1 register */ -#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) -/* Flags in RFIFO0 register */ -#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) -/* Flags in STATR register */ -#define CAN_FLAGS_STATR ((uint32_t)0x01000000) -/* Flags in ERRSR register */ -#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - - -#define CAN_MODE_MASK ((uint32_t) 0x00000003) - -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - - -/********************************************************************* - * @fn CAN_DeInit - * - * @brief Deinitializes the CAN peripheral registers to their default reset - * values. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return none - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - if (CANx == CAN1) - { - RCC_PB1PeriphResetCmd(RCC_PB1Periph_CAN1, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_CAN1, DISABLE); - } -} - -/********************************************************************* - * @fn CAN_Init - * - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_InitStruct - pointer to a CAN_InitTypeDef structure that - * contains the configuration information for the CAN peripheral. - * - * @return InitStatus - CAN InitStatus state. -* CAN_InitStatus_Failed. -* CAN_InitStatus_Success. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - uint32_t wait_ack = 0x00000000; - - CANx->CANFD_CR &= ~(1); - - CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); - CANx->CTLR |= CAN_CTLR_INRQ ; - - while (((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - if ((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_TTCM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; - } - - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_ABOM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; - } - - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_AWUM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; - } - - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->CTLR |= CAN_CTLR_NART; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; - } - - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_RFLM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFLM; - } - - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->CTLR |= CAN_CTLR_TXFP; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; - } - - CANx->BTIMR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ - ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ - ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; - wait_ack = 0; - - while (((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - if ((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success ; - } - } - - return InitStatus; -} - -/********************************************************************* - * @fn CAN_FilterInit - * - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_FilterInitStruct. - * - * @param CAN_FilterInitStruct - pointer to a CAN_FilterInitTypeDef - * structure that contains the configuration information. - * - * @return none - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - CAN1->FCTLR |= FCTLR_FINIT; - CAN1->FWR &= ~(uint32_t)filter_number_bit_pos; - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - CAN1->FSCFGR &= ~(uint32_t)filter_number_bit_pos; - - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - CAN1->FSCFGR |= filter_number_bit_pos; - - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos; - } - else - { - CAN1->FMCFGR |= (uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - CAN1->FAFIFOR &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - CAN1->FAFIFOR |= (uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FWR |= filter_number_bit_pos; - } - - CAN1->FCTLR &= ~FCTLR_FINIT; -} - -/********************************************************************* - * @fn CAN_StructInit - * - * @brief Fills each CAN_InitStruct member with its default value. - * - * @param CAN_InitStruct - pointer to a CAN_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - CAN_InitStruct->CAN_TTCM = DISABLE; - CAN_InitStruct->CAN_ABOM = DISABLE; - CAN_InitStruct->CAN_AWUM = DISABLE; - CAN_InitStruct->CAN_NART = DISABLE; - CAN_InitStruct->CAN_RFLM = DISABLE; - CAN_InitStruct->CAN_TXFP = DISABLE; - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - CAN_InitStruct->CAN_Prescaler = 1; -} - -/********************************************************************* - * @fn CAN_SlaveStartBank - * - * @brief This function applies only to CH32 Connectivity line devices. - * - * @param CAN_BankNumber - Select the start slave bank filter from 1..27. - * - * @return none - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - CAN1->FCTLR |= FCTLR_FINIT; - CAN1->FCTLR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FCTLR |= (uint32_t)(CAN_BankNumber)<<8; - CAN1->FCTLR &= ~FCTLR_FINIT; -} - -/********************************************************************* - * @fn CAN_DBGFreeze - * - * @brief Enables or disables the DBG Freeze for CAN. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - CANx->CTLR |= CTLR_DBF; - } - else - { - CANx->CTLR &= ~CTLR_DBF; - } -} - -/********************************************************************* - * @fn CAN_TTComModeCmd - * - * @brief Enables or disables the CAN Time TriggerOperation communication mode. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * NewState - ENABLE or DISABLE. - * Note- - * DLC must be programmed as 8 in order Time Stamp (2 bytes) to be - * sent over the CAN bus. - * - * @return none - */ -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - CANx->CTLR |= CAN_CTLR_TTCM; - - CANx->sTxMailBox[0].TXMDTR |= ((uint32_t)CAN_TXMDT0R_TGT); - CANx->sTxMailBox[1].TXMDTR |= ((uint32_t)CAN_TXMDT1R_TGT); - CANx->sTxMailBox[2].TXMDTR |= ((uint32_t)CAN_TXMDT2R_TGT); - } - else - { - CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTCM); - - CANx->sTxMailBox[0].TXMDTR &= ((uint32_t)~CAN_TXMDT0R_TGT); - CANx->sTxMailBox[1].TXMDTR &= ((uint32_t)~CAN_TXMDT1R_TGT); - CANx->sTxMailBox[2].TXMDTR &= ((uint32_t)~CAN_TXMDT2R_TGT); - } -} - -/********************************************************************* - * @fn CAN_Transmit - * - * @brief Initiates the transmission of a message. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * TxMessage - pointer to a structure which contains CAN Id, CAN - * DLC and CAN data. - * - * @return transmit_mailbox - The number of the mailbox that is used for - * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - - CANx->CANFD_CR &= ~(1); - - if ((CANx->TSTATR&CAN_TSTATR_TME0) == CAN_TSTATR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSTATR&CAN_TSTATR_TME1) == CAN_TSTATR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSTATR&CAN_TSTATR_TME2) == CAN_TSTATR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if (transmit_mailbox != CAN_TxStatus_NoMailBox) - { - CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_Id_Standard) - { - CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | \ - TxMessage->RTR); - } - else - { - CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->IDE | \ - TxMessage->RTR); - } - - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; - - CANx->sTxMailBox[transmit_mailbox].TXMDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TXMDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; - } - - return transmit_mailbox; -} - -/********************************************************************* - * @fn CAN_TransmitStatus - * - * @brief Checks the transmission of a message. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * TransmitMailbox - the number of the mailbox that is used for - * transmission. - * - * @return state - - * CAN_TxStatus_Ok. - * CAN_TxStatus_Failed. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - switch (TransmitMailbox) - { - case (CAN_TXMAILBOX_0): - state = CANx->TSTATR & (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0); - break; - - case (CAN_TXMAILBOX_1): - state = CANx->TSTATR & (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1); - break; - - case (CAN_TXMAILBOX_2): - state = CANx->TSTATR & (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2); - break; - - default: - state = CAN_TxStatus_Failed; - break; - } - - switch (state) - { - case (0x0): - state = CAN_TxStatus_Pending; - break; - - case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TME0): - state = CAN_TxStatus_Failed; - break; - - case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TME1): - state = CAN_TxStatus_Failed; - break; - - case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TME2): - state = CAN_TxStatus_Failed; - break; - - case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0): - state = CAN_TxStatus_Ok; - break; - - case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1): - state = CAN_TxStatus_Ok; - break; - - case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2): - state = CAN_TxStatus_Ok; - break; - - default: - state = CAN_TxStatus_Failed; - break; - } - - return (uint8_t) state; -} - -/********************************************************************* - * @fn CAN_CancelTransmit - * - * @brief Cancels a transmit request. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * Mailbox - Mailbox number. - * CAN_TXMAILBOX_0. - * CAN_TXMAILBOX_1. - * CAN_TXMAILBOX_2. - * - * @return none - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - switch (Mailbox) - { - case (CAN_TXMAILBOX_0): - CANx->TSTATR |= CAN_TSTATR_ABRQ0; - break; - - case (CAN_TXMAILBOX_1): - CANx->TSTATR |= CAN_TSTATR_ABRQ1; - break; - - case (CAN_TXMAILBOX_2): - CANx->TSTATR |= CAN_TSTATR_ABRQ2; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn CAN_Receive - * - * @brief Receives a message. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * FIFONumber - Receive FIFO number. - * CAN_FIFO0. - * CAN_FIFO1. - * RxMessage - pointer to a structure receive message which contains - * CAN Id, CAN DLC, CAN datas and FMI number. - * - * @return none - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; - - if (RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 24); - - if (FIFONumber == CAN_FIFO0) - { - CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; - } - else - { - CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; - } -} - -/********************************************************************* - * @fn CAN_FIFORelease - * - * @brief Releases the specified FIFO. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * FIFONumber - Receive FIFO number. - * CAN_FIFO0. - * CAN_FIFO1. - * - * @return none - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - if (FIFONumber == CAN_FIFO0) - { - CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; - } - else - { - CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; - } -} - -/********************************************************************* - * @fn CAN_MessagePending - * - * @brief Returns the number of pending messages. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * FIFONumber - Receive FIFO number. - * CAN_FIFO0. - * CAN_FIFO1. - * - * @return message_pending: which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RFIFO0&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RFIFO1&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - - return message_pending; -} - -/********************************************************************* - * @fn CAN_OperatingModeRequest - * - * @brief Select the CAN Operation mode. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_OperatingMode - CAN Operating Mode. - * CAN_OperatingMode_Initialization. - * CAN_OperatingMode_Normal. - * CAN_OperatingMode_Sleep. - * - * @return status - - * CAN_ModeStatus_Failed - CAN failed entering the specific mode. - * CAN_ModeStatus_Success - CAN Succeed entering the specific mode. - */ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) -{ - uint8_t status = CAN_ModeStatus_Failed; - uint32_t timeout = INAK_TIMEOUT; - - if (CAN_OperatingMode == CAN_OperatingMode_Initialization) - { - CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SLEEP)) | CAN_CTLR_INRQ); - - while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) && (timeout != 0)) - { - timeout--; - } - if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Normal) - { - CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SLEEP|CAN_CTLR_INRQ)); - - while (((CANx->STATR & CAN_MODE_MASK) != 0) && (timeout!=0)) - { - timeout--; - } - if ((CANx->STATR & CAN_MODE_MASK) != 0) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) - { - CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); - - while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) && (timeout!=0)) - { - timeout--; - } - if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else - { - status = CAN_ModeStatus_Failed; - } - - return (uint8_t) status; -} - -/********************************************************************* - * @fn CAN_Sleep - * - * @brief Enters the low power mode. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return sleepstatus - - * CAN_Sleep_Ok. - * CAN_Sleep_Failed. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CAN_Sleep_Failed; - - CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); - - if ((CANx->STATR & (CAN_STATR_SLAK|CAN_STATR_INAK)) == CAN_STATR_SLAK) - { - sleepstatus = CAN_Sleep_Ok; - } - - return (uint8_t)sleepstatus; -} - -/********************************************************************* - * @fn CAN_WakeUp - * - * @brief Wakes the CAN up. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return wakeupstatus - - * CAN_WakeUp_Ok. - * CAN_WakeUp_Failed. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CAN_WakeUp_Failed; - - CANx->CTLR &= ~(uint32_t)CAN_CTLR_SLEEP; - - while(((CANx->STATR & CAN_STATR_SLAK) == CAN_STATR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->STATR & CAN_STATR_SLAK) != CAN_STATR_SLAK) - { - wakeupstatus = CAN_WakeUp_Ok; - } - - return (uint8_t)wakeupstatus; -} - -/********************************************************************* - * @fn CAN_GetLastErrorCode - * - * @brief Returns the CANx's last error code (LEC). - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return errorcode - specifies the Error code. - * CAN_ErrorCode_NoErr - No Error. - * CAN_ErrorCode_StuffErr - Stuff Error. - * CAN_ErrorCode_FormErr - Form Error. - * CAN_ErrorCode_ACKErr - Acknowledgment Error. - * CAN_ErrorCode_BitRecessiveErr - Bit Recessive Error. - * CAN_ErrorCode_BitDominantErr - Bit Dominant Error. - * CAN_ErrorCode_CRCErr - CRC Error. - * CAN_ErrorCode_SoftwareSetErr - Software Set Error. - */ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) -{ - uint8_t errorcode=0; - - errorcode = (((uint8_t)CANx->ERRSR) & (uint8_t)CAN_ERRSR_LEC); - - return errorcode; -} - -/********************************************************************* - * @fn CAN_GetReceiveErrorCounter - * - * @brief Returns the CANx Receive Error Counter (REC). - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * Note- - * In case of an error during reception, this counter is incremented - * by 1 or by 8 depending on the error condition as defined by the CAN - * standard. After every successful reception, the counter is - * decremented by 1 or reset to 120 if its value was higher than 128. - * When the counter value exceeds 127, the CAN controller enters the - * error passive state. - * @return counter - CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_REC)>> 24); - - return counter; -} - -/********************************************************************* - * @fn CAN_GetLSBTransmitErrorCounter - * - * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return counter - LSB of the 9-bit CAN Transmit Error Counter. - */ -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_TEC)>> 16); - - return counter; -} - -/********************************************************************* - * @fn CAN_ITConfig - * - * @brief Enables or disables the specified CANx interrupts. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_IT - specifies the CAN interrupt sources to be enabled or disabled. - * CAN_IT_TME. - * CAN_IT_FMP0. - * CAN_IT_FF0. - * CAN_IT_FOV0. - * CAN_IT_FMP1. - * CAN_IT_FF1. - * CAN_IT_FOV1. - * CAN_IT_EWG. - * CAN_IT_EPV. - * CAN_IT_LEC. - * CAN_IT_ERR. - * CAN_IT_WKU. - * CAN_IT_SLK. - * NewState - ENABLE or DISABLE. - * - * @return counter - LSB of the 9-bit CAN Transmit Error Counter. - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - CANx->INTENR |= CAN_IT; - } - else - { - CANx->INTENR &= ~CAN_IT; - } -} - -/********************************************************************* - * @fn CAN_GetFlagStatus - * - * @brief Checks whether the specified CAN flag is set or not. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_FLAG - specifies the flag to check. - * CAN_FLAG_EWG. - * CAN_FLAG_EPV. - * CAN_FLAG_BOF. - * CAN_FLAG_RQCP0. - * CAN_FLAG_RQCP1. - * CAN_FLAG_RQCP2. - * CAN_FLAG_FMP1. - * CAN_FLAG_FF1. - * CAN_FLAG_FOV1. - * CAN_FLAG_FMP0. - * CAN_FLAG_FF0. - * CAN_FLAG_FOV0. - * CAN_FLAG_WKU. - * CAN_FLAG_SLAK. - * CAN_FLAG_LEC. - * NewState - ENABLE or DISABLE. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((CAN_FLAG & CAN_FLAGS_ERRSR) != (uint32_t)RESET) - { - if ((CANx->ERRSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_STATR) != (uint32_t)RESET) - { - if ((CANx->STATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) - { - if ((CANx->TSTATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) - { - if ((CANx->RFIFO0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if ((uint32_t)(CANx->RFIFO1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - - return bitstatus; -} - -/********************************************************************* - * @fn CAN_ClearFlag - * - * @brief Clears the CAN's pending flags. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_FLAG - specifies the flag to clear. - * CAN_FLAG_RQCP0. - * CAN_FLAG_RQCP1. - * CAN_FLAG_RQCP2. - * CAN_FLAG_FF1. - * CAN_FLAG_FOV1. - * CAN_FLAG_FF0. - * CAN_FLAG_FOV0. - * CAN_FLAG_WKU. - * CAN_FLAG_SLAK. - * CAN_FLAG_LEC. - * - * @return none - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - uint32_t flagtmp=0; - - if (CAN_FLAG == CAN_FLAG_LEC) - { - CANx->ERRSR = (uint32_t)RESET; - } - else - { - flagtmp = CAN_FLAG & 0x000FFFFF; - - if ((CAN_FLAG & CAN_FLAGS_RFIFO0)!=(uint32_t)RESET) - { - CANx->RFIFO0 = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_RFIFO1)!=(uint32_t)RESET) - { - CANx->RFIFO1 = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_TSTATR)!=(uint32_t)RESET) - { - CANx->TSTATR = (uint32_t)(flagtmp); - } - else - { - CANx->STATR = (uint32_t)(flagtmp); - } - } -} - -/********************************************************************* - * @fn CAN_GetITStatus - * - * @brief Checks whether the specified CANx interrupt has occurred or not. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_IT - specifies the CAN interrupt source to check. - * CAN_IT_TME. - * CAN_IT_FMP0. - * CAN_IT_FF0. - * CAN_IT_FOV0. - * CAN_IT_FMP1. - * CAN_IT_FF1. - * CAN_IT_FOV1. - * CAN_IT_WKU. - * CAN_IT_SLK. - * CAN_IT_EWG. - * CAN_IT_EPV. - * CAN_IT_BOF. - * CAN_IT_LEC. - * CAN_IT_ERR. - * - * @return ITStatus - SET or RESET. - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus itstatus = RESET; - - if((CANx->INTENR & CAN_IT) != RESET) - { - switch (CAN_IT) - { - case CAN_IT_TME: - itstatus = CheckITStatus(CANx->TSTATR, CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2); - break; - - case CAN_IT_FMP0: - itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FMP0); - break; - - case CAN_IT_FF0: - itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FULL0); - break; - - case CAN_IT_FOV0: - itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FOVR0); - break; - - case CAN_IT_FMP1: - itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FMP1); - break; - - case CAN_IT_FF1: - itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FULL1); - break; - - case CAN_IT_FOV1: - itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FOVR1); - break; - - case CAN_IT_WKU: - itstatus = CheckITStatus(CANx->STATR, CAN_STATR_WKUI); - break; - - case CAN_IT_SLK: - itstatus = CheckITStatus(CANx->STATR, CAN_STATR_SLAKI); - break; - - case CAN_IT_EWG: - itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EWGF); - break; - - case CAN_IT_EPV: - itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EPVF); - break; - - case CAN_IT_BOF: - itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_BOFF); - break; - - case CAN_IT_LEC: - itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_LEC); - break; - - case CAN_IT_ERR: - itstatus = CheckITStatus(CANx->STATR, CAN_STATR_ERRI); - break; - - default : - itstatus = RESET; - break; - } - } - else - { - itstatus = RESET; - } - - return itstatus; -} - -/********************************************************************* - * @fn CAN_ClearITPendingBit - * - * @brief Clears the CANx's interrupt pending bits. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_IT - specifies the interrupt pending bit to clear. - * CAN_IT_TME. - * CAN_IT_FF0. - * CAN_IT_FOV0. - * CAN_IT_FF1. - * CAN_IT_FOV1. - * CAN_IT_WKU. - * CAN_IT_SLK. - * CAN_IT_EWG. - * CAN_IT_EPV. - * CAN_IT_BOF. - * CAN_IT_LEC. - * CAN_IT_ERR. - * - * @return none - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - switch (CAN_IT) - { - case CAN_IT_TME: - CANx->TSTATR = CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2; - break; - - case CAN_IT_FF0: - CANx->RFIFO0 = CAN_RFIFO0_FULL0; - break; - - case CAN_IT_FOV0: - CANx->RFIFO0 = CAN_RFIFO0_FOVR0; - break; - - case CAN_IT_FF1: - CANx->RFIFO1 = CAN_RFIFO1_FULL1; - break; - - case CAN_IT_FOV1: - CANx->RFIFO1 = CAN_RFIFO1_FOVR1; - break; - - case CAN_IT_WKU: - CANx->STATR = CAN_STATR_WKUI; - break; - - case CAN_IT_SLK: - CANx->STATR = CAN_STATR_SLAKI; - break; - - case CAN_IT_EWG: - CANx->STATR = CAN_STATR_ERRI; - break; - - case CAN_IT_EPV: - CANx->STATR = CAN_STATR_ERRI; - break; - - case CAN_IT_BOF: - CANx->STATR = CAN_STATR_ERRI; - break; - - case CAN_IT_LEC: - CANx->ERRSR = RESET; - CANx->STATR = CAN_STATR_ERRI; - break; - - case CAN_IT_ERR: - CANx->ERRSR = RESET; - CANx->STATR = CAN_STATR_ERRI; - break; - - default : - break; - } -} - -/********************************************************************* - * @fn CheckITStatus - * - * @brief Checks whether the CAN interrupt has occurred or not. - * - * @param CAN_Reg - specifies the CAN interrupt register to check - * It_Bit - specifies the interrupt source bit to check. - * - * @return ITStatus - SET or RESET. - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - pendingbitstatus = SET; - } - else - { - pendingbitstatus = RESET; - } - - return pendingbitstatus; -} - -/********************************************************************* - * @fn CAN_BS1_ModeConfig - * - * @brief Configures the CAN the number of time quanta in Bit and mode. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_BS1_Mode - CAN BS1 Mode - * CAN_BS1_4bit - 4bit mode - * CAN_BS1_tq = TS1[3:0];(CANx->BTIMR) - * This parameter must range from 0x00 to 0x0F. - * CAN_BS1_6bit - 6bit mode - * CAN_BS1_tq = (TS1[1:0] << 4) + BTR_TS1_T[3:0];(CANx->BTIMR) - * This parameter must range from 0x00 to 0x3F. - * - * @return none - */ -void CAN_BS1_ModeConfig(CAN_TypeDef* CANx, uint32_t CAN_BS1_Mode, uint8_t CAN_BS1_tq) -{ - CANx->CANFD_CR &= ~(CAN_BS1_6bit); - CANx->BTIMR &= ~(0x000FF000); - - if(CAN_BS1_Mode == CAN_BS1_6bit) - { - CANx->CANFD_CR |= CAN_BS1_6bit; - CANx->BTIMR |= (CAN_BS1_tq << 16); - } - else if(CAN_BS1_Mode == CAN_BS1_4bit) - { - CANx->BTIMR |= (CAN_BS1_tq << 12); - } -} - -/********************************************************************* - * @fn CAN_BusOff_ErrCntConfig - * - * @brief Configures the CAN the number of err count bus off. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * BusOff_ErrCnt - Err count bus off. - * This parameter must range from 0x00 to 0xFF. - * - * @return none - */ -void CAN_BusOff_ErrCntConfig(CAN_TypeDef *CANx, uint8_t BusOff_ErrCnt) -{ - CANx->TERR_CNT &= ~(0x000000FF); - CANx->TERR_CNT |= (uint32_t)BusOff_ErrCnt; -} - -/********************************************************************* - * @fn CANFD_Restrict_ModeCmd - * - * @brief Enables or disables the CANFD restrict mode. - * - * @param CANx - where x can be 1 to select the CANFD peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void CANFD_Restrict_ModeCmd(CAN_TypeDef *CANx, FunctionalState NewState) -{ - - if(NewState) - { - CANx->CANFD_CR |= (1<<9); - } - else - { - CANx->CANFD_CR &= ~(1<<9); - } -} - -/********************************************************************* - * @fn CANFD_Init - * - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CANFD_InitStruct. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CANFD_InitStruct - pointer to a CANFD_InitTypeDef structure that - * contains the configuration information for the CAN peripheral. - * - * @return InitStatus - CAN InitStatus state. -* CAN_InitStatus_Failed. -* CAN_InitStatus_Success. - */ -uint8_t CANFD_Init(CAN_TypeDef* CANx, CANFD_InitTypeDef* CANFD_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - uint32_t wait_ack = 0x00000000; - - CANx->CANFD_CR |= 1; - - CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); - CANx->CTLR |= CAN_CTLR_INRQ ; - - while (((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - if ((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - if (CANFD_InitStruct->CANFD_TTCM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_TTCM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; - } - - if (CANFD_InitStruct->CANFD_ABOM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_ABOM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; - } - - if (CANFD_InitStruct->CANFD_AWUM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_AWUM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; - } - - if (CANFD_InitStruct->CANFD_NART == ENABLE) - { - CANx->CTLR |= CAN_CTLR_NART; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; - } - - if (CANFD_InitStruct->CANFD_TXFP == ENABLE) - { - CANx->CTLR |= CAN_CTLR_TXFP; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; - } - - if (CANFD_InitStruct->CANFD_RES_Error == ENABLE) - { - CANx->CANFD_CR |= (1<<7); - } - else - { - CANx->CANFD_CR &= ~(1<<7); - } - - if (CANFD_InitStruct->CANFD_BRS_TXM0 == ENABLE) - { - CANx->CANFD_CR |= (1<<1); - } - else - { - CANx->CANFD_CR &= ~(1<<1); - } - - if (CANFD_InitStruct->CANFD_BRS_TXM1 == ENABLE) - { - CANx->CANFD_CR |= (1<<2); - } - else - { - CANx->CANFD_CR &= ~(1<<2); - } - - if (CANFD_InitStruct->CANFD_BRS_TXM2 == ENABLE) - { - CANx->CANFD_CR |= (1<<3); - } - else - { - CANx->CANFD_CR &= ~(1<<3); - } - - if (CANFD_InitStruct->CANFD_ESI_Auto_TXM0 == ENABLE) - { - CANx->CANFD_CR |= (1<<4); - } - else - { - CANx->CANFD_CR &= ~(1<<4); - } - - if (CANFD_InitStruct->CANFD_ESI_Auto_TXM1 == ENABLE) - { - CANx->CANFD_CR |= (1<<5); - } - else - { - CANx->CANFD_CR &= ~(1<<5); - } - - if (CANFD_InitStruct->CANFD_ESI_Auto_TXM2 == ENABLE) - { - CANx->CANFD_CR |= (1<<6); - } - else - { - CANx->CANFD_CR &= ~(1<<6); - } - - CANx->CANFD_BTR &= ~(0x009F1FFF); - CANx->CANFD_TDCT &= ~(0x00003F3F); - - CANx->CANFD_TDCT = (uint32_t)((uint32_t)CANFD_InitStruct->CANFD_TDC_FILTER << 8) | \ - ((uint32_t)CANFD_InitStruct->CANFD_TDC0); - - CANx->CANFD_BTR = (uint32_t)((uint32_t)CANFD_InitStruct->CANFD_TDCE << 23) | \ - ((uint32_t)CANFD_InitStruct->CANFD_Prescaler-1 << 16) | \ - ((uint32_t)CANFD_InitStruct->CANFD_BS1 << 8) | \ - ((uint32_t)CANFD_InitStruct->CANFD_BS2 << 4) | \ - ((uint32_t)CANFD_InitStruct->CANFD_SJW); - - CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; - wait_ack = 0; - - while (((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - if ((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success ; - } - } - - return InitStatus; -} - -/********************************************************************* - * @fn CANFD_StructInit - * - * @brief Fills each CANFD_InitStruct member with its default value. - * - * @param CANFD_InitStruct - pointer to a CANFD_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void CANFD_StructInit(CANFD_InitTypeDef* CANFD_InitStruct) -{ - CANFD_InitStruct->CANFD_TTCM = DISABLE; - CANFD_InitStruct->CANFD_ABOM = DISABLE; - CANFD_InitStruct->CANFD_AWUM = DISABLE; - CANFD_InitStruct->CANFD_NART = DISABLE; - CANFD_InitStruct->CANFD_TXFP = DISABLE; - - CANFD_InitStruct->CANFD_RES_Error = DISABLE; - CANFD_InitStruct->CANFD_ESI_Auto_TXM0 = DISABLE; - CANFD_InitStruct->CANFD_ESI_Auto_TXM1 = DISABLE; - CANFD_InitStruct->CANFD_ESI_Auto_TXM2 = DISABLE; - CANFD_InitStruct->CANFD_BRS_TXM0 = DISABLE; - CANFD_InitStruct->CANFD_BRS_TXM1 = DISABLE; - CANFD_InitStruct->CANFD_BRS_TXM2 = DISABLE; - - CANFD_InitStruct->CANFD_TDC_FILTER = 0; - CANFD_InitStruct->CANFD_TDC0 = 2; - CANFD_InitStruct->CANFD_TDCE = ENABLE; - - CANFD_InitStruct->CANFD_Mode = CAN_Mode_Normal; - CANFD_InitStruct->CANFD_SJW = CANFD_SJW_8tq; - CANFD_InitStruct->CANFD_BS1 = CANFD_BS1_7tq; - CANFD_InitStruct->CANFD_BS2 = CANFD_BS2_4tq; - CANFD_InitStruct->CANFD_Prescaler = 1; -} - -/********************************************************************* - * @fn CANFD_Transmit - * - * @brief Initiates the transmission of a message for CANFD. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * TxMessage - pointer to a structure which contains CAN Id, CAN - * DLC and CAN data. - * - * @return transmit_mailbox - The number of the mailbox that is used for - * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CANFD_Transmit(CAN_TypeDef* CANx, CanFDTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - - CANx->CANFD_CR |= (1); - - if ((CANx->TSTATR&CAN_TSTATR_TME0) == CAN_TSTATR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSTATR&CAN_TSTATR_TME1) == CAN_TSTATR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSTATR&CAN_TSTATR_TME2) == CAN_TSTATR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if (transmit_mailbox != CAN_TxStatus_NoMailBox) - { - CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_Id_Standard) - { - CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | \ - TxMessage->RTR); - } - else - { - CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->IDE | \ - TxMessage->RTR); - } - - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; - CANx->CANFD_DMA_T[transmit_mailbox] = (uint32_t)TxMessage->Data; - CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; - } - - return transmit_mailbox; -} - -/********************************************************************* - * @fn CANFD_Receive - * - * @brief Receives a message. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * FIFONumber - Receive FIFO number. - * CAN_FIFO0. - * CAN_FIFO1. - * RxMessage - pointer to a structure receive message which contains - * CAN Id, CAN DLC, CAN datas and FMI number. - * - * @return ErrorStatus - NoREADY or READY. - */ -ErrorStatus CANFD_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanFDRxMsg* RxMessage) -{ - ErrorStatus sta = NoREADY; - uint8_t len, i; - uint32_t adr; - - if((CANx->sFIFOMailBox[FIFONumber].RXMIR & 1) == 0) return sta; - - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; - - if (RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; - - len = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; - - if(len <= 8) - { - RxMessage->DLC = len; - } - else if(len <= 12) - { - RxMessage->DLC = (len - 6) * 4; - } - else if(len <= 15) - { - RxMessage->DLC = (len - 11) * 16; - } - - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); - RxMessage->BRS = (uint8_t)0x01 & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 4); - RxMessage->ESI = (uint8_t)0x01 & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 5); - RxMessage->RES = (uint8_t)0x01 & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 6); - - adr = CANx->CANFD_DMA_R[FIFONumber] + 0x20000000; - - for(i=0; iDLC; i++) - { - RxMessage->Data[i] = *((uint8_t*)adr++); - } - - if (FIFONumber == CAN_FIFO0) - { - CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; - } - else - { - CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; - } - - sta = READY; - - return sta; -} - - -/********************************************************************* - * @fn CANFD_GetTransmitDelayOffsetVal - * - * @brief Returns the CANx Transmit Delay Offset Value. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return val - CAN Transmit Delay Offset Value. - */ -uint8_t CANFD_GetTransmitDelayOffsetVal(CAN_TypeDef *CANx) -{ - uint8_t val=0; - - val = (uint8_t)((CANx->CANFD_PSR & 0x00FF0000)>> 16); - - return val; -} - -/********************************************************************* - * @fn CANFD_TransmitMailbox_DMAAdr - * - * @brief Set Transmit Mailbox DMA address. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * MailboxNumber - Transmit Mailbox. - * CAN_Transmit_Mailbox0. - * CAN_Transmit_Mailbox1. - * CAN_Transmit_Mailbox2. - * address - DMA address. - * - * @return none. - */ -void CANFD_TransmitMailbox_DMAAdr(CAN_TypeDef *CANx, uint8_t MailboxNumber, uint32_t Address) -{ - CANx->CANFD_DMA_T[MailboxNumber] = Address; -} - -/********************************************************************* - * @fn CANFD_ReceiveFIFO_DMAAdr - * - * @brief Set receives FIFO DMA address. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * FIFONumber - Receive FIFO number. - * CAN_FIFO0. - * CAN_FIFO1. - * address - DMA address. - * - * @return none. - */ -void CANFD_ReceiveFIFO_DMAAdr(CAN_TypeDef *CANx, uint8_t FIFONumber, uint32_t Address) -{ - CANx->CANFD_DMA_R[FIFONumber] = Address; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_can.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the CAN firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_can.h" +#include "ch32l103_rcc.h" + +/* CAN CTLR Register bits */ +#define CTLR_DBF ((uint32_t)0x00010000) + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) + +/* CAN FCTLR Register bits */ +#define FCTLR_FINIT ((uint32_t)0x00000001) + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + + +/* Flags in TSTATR register */ +#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) +/* Flags in RFIFO1 register */ +#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) +/* Flags in RFIFO0 register */ +#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) +/* Flags in STATR register */ +#define CAN_FLAGS_STATR ((uint32_t)0x01000000) +/* Flags in ERRSR register */ +#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + + +/********************************************************************* + * @fn CAN_DeInit + * + * @brief Deinitializes the CAN peripheral registers to their default reset + * values. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return none + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + if (CANx == CAN1) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_CAN1, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_CAN1, DISABLE); + } +} + +/********************************************************************* + * @fn CAN_Init + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_InitStruct - pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * + * @return InitStatus - CAN InitStatus state. +* CAN_InitStatus_Failed. +* CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + + CANx->CANFD_CR &= ~(1); + + CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); + CANx->CTLR |= CAN_CTLR_INRQ ; + + while (((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; + } + + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_ABOM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; + } + + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_AWUM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; + } + + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->CTLR |= CAN_CTLR_NART; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; + } + + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_RFLM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFLM; + } + + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TXFP; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; + } + + CANx->BTIMR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; + wait_ack = 0; + + while (((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + return InitStatus; +} + +/********************************************************************* + * @fn CAN_FilterInit + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * + * @param CAN_FilterInitStruct - pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration information. + * + * @return none + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FWR &= ~(uint32_t)filter_number_bit_pos; + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + CAN1->FSCFGR &= ~(uint32_t)filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + CAN1->FSCFGR |= filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos; + } + else + { + CAN1->FMCFGR |= (uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + CAN1->FAFIFOR &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + CAN1->FAFIFOR |= (uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FWR |= filter_number_bit_pos; + } + + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_StructInit + * + * @brief Fills each CAN_InitStruct member with its default value. + * + * @param CAN_InitStruct - pointer to a CAN_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + CAN_InitStruct->CAN_TTCM = DISABLE; + CAN_InitStruct->CAN_ABOM = DISABLE; + CAN_InitStruct->CAN_AWUM = DISABLE; + CAN_InitStruct->CAN_NART = DISABLE; + CAN_InitStruct->CAN_RFLM = DISABLE; + CAN_InitStruct->CAN_TXFP = DISABLE; + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + CAN_InitStruct->CAN_Prescaler = 1; +} + +/********************************************************************* + * @fn CAN_SlaveStartBank + * + * @brief This function applies only to CH32 Connectivity line devices. + * + * @param CAN_BankNumber - Select the start slave bank filter from 1..27. + * + * @return none + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FCTLR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FCTLR |= (uint32_t)(CAN_BankNumber)<<8; + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_DBGFreeze + * + * @brief Enables or disables the DBG Freeze for CAN. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CANx->CTLR |= CTLR_DBF; + } + else + { + CANx->CTLR &= ~CTLR_DBF; + } +} + +/********************************************************************* + * @fn CAN_TTComModeCmd + * + * @brief Enables or disables the CAN Time TriggerOperation communication mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * Note- + * DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * + * @return none + */ +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + + CANx->sTxMailBox[0].TXMDTR |= ((uint32_t)CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR |= ((uint32_t)CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR |= ((uint32_t)CAN_TXMDT2R_TGT); + } + else + { + CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTCM); + + CANx->sTxMailBox[0].TXMDTR &= ((uint32_t)~CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR &= ((uint32_t)~CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR &= ((uint32_t)~CAN_TXMDT2R_TGT); + } +} + +/********************************************************************* + * @fn CAN_Transmit + * + * @brief Initiates the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TxMessage - pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * + * @return transmit_mailbox - The number of the mailbox that is used for + * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + + CANx->CANFD_CR &= ~(1); + + if ((CANx->TSTATR&CAN_TSTATR_TME0) == CAN_TSTATR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME1) == CAN_TSTATR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME2) == CAN_TSTATR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; + + CANx->sTxMailBox[transmit_mailbox].TXMDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TXMDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; + } + + return transmit_mailbox; +} + +/********************************************************************* + * @fn CAN_TransmitStatus + * + * @brief Checks the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TransmitMailbox - the number of the mailbox that is used for + * transmission. + * + * @return state - + * CAN_TxStatus_Ok. + * CAN_TxStatus_Failed. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSTATR & (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0); + break; + + case (CAN_TXMAILBOX_1): + state = CANx->TSTATR & (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1); + break; + + case (CAN_TXMAILBOX_2): + state = CANx->TSTATR & (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2); + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + switch (state) + { + case (0x0): + state = CAN_TxStatus_Pending; + break; + + case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Failed; + break; + + case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Failed; + break; + + case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Failed; + break; + + case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Ok; + break; + + case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Ok; + break; + + case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Ok; + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + return (uint8_t) state; +} + +/********************************************************************* + * @fn CAN_CancelTransmit + * + * @brief Cancels a transmit request. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Mailbox - Mailbox number. + * CAN_TXMAILBOX_0. + * CAN_TXMAILBOX_1. + * CAN_TXMAILBOX_2. + * + * @return none + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): + CANx->TSTATR |= CAN_TSTATR_ABRQ0; + break; + + case (CAN_TXMAILBOX_1): + CANx->TSTATR |= CAN_TSTATR_ABRQ1; + break; + + case (CAN_TXMAILBOX_2): + CANx->TSTATR |= CAN_TSTATR_ABRQ2; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn CAN_Receive + * + * @brief Receives a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * RxMessage - pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * + * @return none + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 24); + + if (FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_FIFORelease + * + * @brief Releases the specified FIFO. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return none + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + if (FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_MessagePending + * + * @brief Returns the number of pending messages. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return message_pending: which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RFIFO0&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RFIFO1&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + + return message_pending; +} + +/********************************************************************* + * @fn CAN_OperatingModeRequest + * + * @brief Select the CAN Operation mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_OperatingMode - CAN Operating Mode. + * CAN_OperatingMode_Initialization. + * CAN_OperatingMode_Normal. + * CAN_OperatingMode_Sleep. + * + * @return status - + * CAN_ModeStatus_Failed - CAN failed entering the specific mode. + * CAN_ModeStatus_Success - CAN Succeed entering the specific mode. + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + uint32_t timeout = INAK_TIMEOUT; + + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SLEEP)) | CAN_CTLR_INRQ); + + while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Normal) + { + CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SLEEP|CAN_CTLR_INRQ)); + + while (((CANx->STATR & CAN_MODE_MASK) != 0) && (timeout!=0)) + { + timeout--; + } + if ((CANx->STATR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) && (timeout!=0)) + { + timeout--; + } + if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t) status; +} + +/********************************************************************* + * @fn CAN_Sleep + * + * @brief Enters the low power mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return sleepstatus - + * CAN_Sleep_Ok. + * CAN_Sleep_Failed. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + if ((CANx->STATR & (CAN_STATR_SLAK|CAN_STATR_INAK)) == CAN_STATR_SLAK) + { + sleepstatus = CAN_Sleep_Ok; + } + + return (uint8_t)sleepstatus; +} + +/********************************************************************* + * @fn CAN_WakeUp + * + * @brief Wakes the CAN up. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return wakeupstatus - + * CAN_WakeUp_Ok. + * CAN_WakeUp_Failed. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + CANx->CTLR &= ~(uint32_t)CAN_CTLR_SLEEP; + + while(((CANx->STATR & CAN_STATR_SLAK) == CAN_STATR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->STATR & CAN_STATR_SLAK) != CAN_STATR_SLAK) + { + wakeupstatus = CAN_WakeUp_Ok; + } + + return (uint8_t)wakeupstatus; +} + +/********************************************************************* + * @fn CAN_GetLastErrorCode + * + * @brief Returns the CANx's last error code (LEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return errorcode - specifies the Error code. + * CAN_ErrorCode_NoErr - No Error. + * CAN_ErrorCode_StuffErr - Stuff Error. + * CAN_ErrorCode_FormErr - Form Error. + * CAN_ErrorCode_ACKErr - Acknowledgment Error. + * CAN_ErrorCode_BitRecessiveErr - Bit Recessive Error. + * CAN_ErrorCode_BitDominantErr - Bit Dominant Error. + * CAN_ErrorCode_CRCErr - CRC Error. + * CAN_ErrorCode_SoftwareSetErr - Software Set Error. + */ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) +{ + uint8_t errorcode=0; + + errorcode = (((uint8_t)CANx->ERRSR) & (uint8_t)CAN_ERRSR_LEC); + + return errorcode; +} + +/********************************************************************* + * @fn CAN_GetReceiveErrorCounter + * + * @brief Returns the CANx Receive Error Counter (REC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Note- + * In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @return counter - CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_REC)>> 24); + + return counter; +} + +/********************************************************************* + * @fn CAN_GetLSBTransmitErrorCounter + * + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_TEC)>> 16); + + return counter; +} + +/********************************************************************* + * @fn CAN_ITConfig + * + * @brief Enables or disables the specified CANx interrupts. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt sources to be enabled or disabled. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_LEC. + * CAN_IT_ERR. + * CAN_IT_WKU. + * CAN_IT_SLK. + * NewState - ENABLE or DISABLE. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CANx->INTENR |= CAN_IT; + } + else + { + CANx->INTENR &= ~CAN_IT; + } +} + +/********************************************************************* + * @fn CAN_GetFlagStatus + * + * @brief Checks whether the specified CAN flag is set or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to check. + * CAN_FLAG_EWG. + * CAN_FLAG_EPV. + * CAN_FLAG_BOF. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FMP1. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FMP0. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * NewState - ENABLE or DISABLE. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((CAN_FLAG & CAN_FLAGS_ERRSR) != (uint32_t)RESET) + { + if ((CANx->ERRSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_STATR) != (uint32_t)RESET) + { + if ((CANx->STATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) + { + if ((CANx->TSTATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) + { + if ((CANx->RFIFO0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((uint32_t)(CANx->RFIFO1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/********************************************************************* + * @fn CAN_ClearFlag + * + * @brief Clears the CAN's pending flags. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to clear. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * + * @return none + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp=0; + + if (CAN_FLAG == CAN_FLAG_LEC) + { + CANx->ERRSR = (uint32_t)RESET; + } + else + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RFIFO0)!=(uint32_t)RESET) + { + CANx->RFIFO0 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RFIFO1)!=(uint32_t)RESET) + { + CANx->RFIFO1 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSTATR)!=(uint32_t)RESET) + { + CANx->TSTATR = (uint32_t)(flagtmp); + } + else + { + CANx->STATR = (uint32_t)(flagtmp); + } + } +} + +/********************************************************************* + * @fn CAN_GetITStatus + * + * @brief Checks whether the specified CANx interrupt has occurred or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt source to check. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return ITStatus - SET or RESET. + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + + if((CANx->INTENR & CAN_IT) != RESET) + { + switch (CAN_IT) + { + case CAN_IT_TME: + itstatus = CheckITStatus(CANx->TSTATR, CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2); + break; + + case CAN_IT_FMP0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FMP0); + break; + + case CAN_IT_FF0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FULL0); + break; + + case CAN_IT_FOV0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FOVR0); + break; + + case CAN_IT_FMP1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FMP1); + break; + + case CAN_IT_FF1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FULL1); + break; + + case CAN_IT_FOV1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FOVR1); + break; + + case CAN_IT_WKU: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_WKUI); + break; + + case CAN_IT_SLK: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_SLAKI); + break; + + case CAN_IT_EWG: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EWGF); + break; + + case CAN_IT_EPV: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EPVF); + break; + + case CAN_IT_BOF: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_BOFF); + break; + + case CAN_IT_LEC: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_LEC); + break; + + case CAN_IT_ERR: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_ERRI); + break; + + default : + itstatus = RESET; + break; + } + } + else + { + itstatus = RESET; + } + + return itstatus; +} + +/********************************************************************* + * @fn CAN_ClearITPendingBit + * + * @brief Clears the CANx's interrupt pending bits. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the interrupt pending bit to clear. + * CAN_IT_TME. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return none + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + switch (CAN_IT) + { + case CAN_IT_TME: + CANx->TSTATR = CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2; + break; + + case CAN_IT_FF0: + CANx->RFIFO0 = CAN_RFIFO0_FULL0; + break; + + case CAN_IT_FOV0: + CANx->RFIFO0 = CAN_RFIFO0_FOVR0; + break; + + case CAN_IT_FF1: + CANx->RFIFO1 = CAN_RFIFO1_FULL1; + break; + + case CAN_IT_FOV1: + CANx->RFIFO1 = CAN_RFIFO1_FOVR1; + break; + + case CAN_IT_WKU: + CANx->STATR = CAN_STATR_WKUI; + break; + + case CAN_IT_SLK: + CANx->STATR = CAN_STATR_SLAKI; + break; + + case CAN_IT_EWG: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_EPV: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_BOF: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_LEC: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_ERR: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + default : + break; + } +} + +/********************************************************************* + * @fn CheckITStatus + * + * @brief Checks whether the CAN interrupt has occurred or not. + * + * @param CAN_Reg - specifies the CAN interrupt register to check + * It_Bit - specifies the interrupt source bit to check. + * + * @return ITStatus - SET or RESET. + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + pendingbitstatus = SET; + } + else + { + pendingbitstatus = RESET; + } + + return pendingbitstatus; +} + +/********************************************************************* + * @fn CAN_BS1_ModeConfig + * + * @brief Configures the CAN the number of time quanta in Bit and mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_BS1_Mode - CAN BS1 Mode + * CAN_BS1_4bit - 4bit mode + * CAN_BS1_tq = TS1[3:0];(CANx->BTIMR) + * This parameter must range from 0x00 to 0x0F. + * CAN_BS1_6bit - 6bit mode + * CAN_BS1_tq = (TS1[1:0] << 4) + BTR_TS1_T[3:0];(CANx->BTIMR) + * This parameter must range from 0x00 to 0x3F. + * + * @return none + */ +void CAN_BS1_ModeConfig(CAN_TypeDef* CANx, uint32_t CAN_BS1_Mode, uint8_t CAN_BS1_tq) +{ + CANx->CANFD_CR &= ~(CAN_BS1_6bit); + CANx->BTIMR &= ~(0x000FF000); + + if(CAN_BS1_Mode == CAN_BS1_6bit) + { + CANx->CANFD_CR |= CAN_BS1_6bit; + CANx->BTIMR |= (CAN_BS1_tq << 16); + } + else if(CAN_BS1_Mode == CAN_BS1_4bit) + { + CANx->BTIMR |= (CAN_BS1_tq << 12); + } +} + +/********************************************************************* + * @fn CAN_BusOff_ErrCntConfig + * + * @brief Configures the CAN the number of err count bus off. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * BusOff_ErrCnt - Err count bus off. + * This parameter must range from 0x00 to 0xFF. + * + * @return none + */ +void CAN_BusOff_ErrCntConfig(CAN_TypeDef *CANx, uint8_t BusOff_ErrCnt) +{ + CANx->TERR_CNT &= ~(0x000000FF); + CANx->TERR_CNT |= (uint32_t)BusOff_ErrCnt; +} + +/********************************************************************* + * @fn CANFD_Restrict_ModeCmd + * + * @brief Enables or disables the CANFD restrict mode. + * + * @param CANx - where x can be 1 to select the CANFD peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void CANFD_Restrict_ModeCmd(CAN_TypeDef *CANx, FunctionalState NewState) +{ + + if(NewState) + { + CANx->CANFD_CR |= (1<<9); + } + else + { + CANx->CANFD_CR &= ~(1<<9); + } +} + +/********************************************************************* + * @fn CANFD_Init + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CANFD_InitStruct. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CANFD_InitStruct - pointer to a CANFD_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * + * @return InitStatus - CAN InitStatus state. +* CAN_InitStatus_Failed. +* CAN_InitStatus_Success. + */ +uint8_t CANFD_Init(CAN_TypeDef* CANx, CANFD_InitTypeDef* CANFD_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + + CANx->CANFD_CR |= 1; + + CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); + CANx->CTLR |= CAN_CTLR_INRQ ; + + while (((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + if (CANFD_InitStruct->CANFD_TTCM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; + } + + if (CANFD_InitStruct->CANFD_ABOM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_ABOM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; + } + + if (CANFD_InitStruct->CANFD_AWUM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_AWUM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; + } + + if (CANFD_InitStruct->CANFD_NART == ENABLE) + { + CANx->CTLR |= CAN_CTLR_NART; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; + } + + if (CANFD_InitStruct->CANFD_TXFP == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TXFP; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; + } + + if (CANFD_InitStruct->CANFD_RES_Error == ENABLE) + { + CANx->CANFD_CR |= (1<<7); + } + else + { + CANx->CANFD_CR &= ~(1<<7); + } + + if (CANFD_InitStruct->CANFD_BRS_TXM0 == ENABLE) + { + CANx->CANFD_CR |= (1<<1); + } + else + { + CANx->CANFD_CR &= ~(1<<1); + } + + if (CANFD_InitStruct->CANFD_BRS_TXM1 == ENABLE) + { + CANx->CANFD_CR |= (1<<2); + } + else + { + CANx->CANFD_CR &= ~(1<<2); + } + + if (CANFD_InitStruct->CANFD_BRS_TXM2 == ENABLE) + { + CANx->CANFD_CR |= (1<<3); + } + else + { + CANx->CANFD_CR &= ~(1<<3); + } + + if (CANFD_InitStruct->CANFD_ESI_Auto_TXM0 == ENABLE) + { + CANx->CANFD_CR |= (1<<4); + } + else + { + CANx->CANFD_CR &= ~(1<<4); + } + + if (CANFD_InitStruct->CANFD_ESI_Auto_TXM1 == ENABLE) + { + CANx->CANFD_CR |= (1<<5); + } + else + { + CANx->CANFD_CR &= ~(1<<5); + } + + if (CANFD_InitStruct->CANFD_ESI_Auto_TXM2 == ENABLE) + { + CANx->CANFD_CR |= (1<<6); + } + else + { + CANx->CANFD_CR &= ~(1<<6); + } + + CANx->CANFD_BTR &= ~(0x009F1FFF); + CANx->CANFD_TDCT &= ~(0x00003F3F); + + CANx->CANFD_TDCT = (uint32_t)((uint32_t)CANFD_InitStruct->CANFD_TDC_FILTER << 8) | \ + ((uint32_t)CANFD_InitStruct->CANFD_TDC0); + + CANx->CANFD_BTR = (uint32_t)((uint32_t)CANFD_InitStruct->CANFD_TDCE << 23) | \ + ((uint32_t)CANFD_InitStruct->CANFD_Prescaler-1 << 16) | \ + ((uint32_t)CANFD_InitStruct->CANFD_BS1 << 8) | \ + ((uint32_t)CANFD_InitStruct->CANFD_BS2 << 4) | \ + ((uint32_t)CANFD_InitStruct->CANFD_SJW); + + CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; + wait_ack = 0; + + while (((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + return InitStatus; +} + +/********************************************************************* + * @fn CANFD_StructInit + * + * @brief Fills each CANFD_InitStruct member with its default value. + * + * @param CANFD_InitStruct - pointer to a CANFD_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void CANFD_StructInit(CANFD_InitTypeDef* CANFD_InitStruct) +{ + CANFD_InitStruct->CANFD_TTCM = DISABLE; + CANFD_InitStruct->CANFD_ABOM = DISABLE; + CANFD_InitStruct->CANFD_AWUM = DISABLE; + CANFD_InitStruct->CANFD_NART = DISABLE; + CANFD_InitStruct->CANFD_TXFP = DISABLE; + + CANFD_InitStruct->CANFD_RES_Error = DISABLE; + CANFD_InitStruct->CANFD_ESI_Auto_TXM0 = DISABLE; + CANFD_InitStruct->CANFD_ESI_Auto_TXM1 = DISABLE; + CANFD_InitStruct->CANFD_ESI_Auto_TXM2 = DISABLE; + CANFD_InitStruct->CANFD_BRS_TXM0 = DISABLE; + CANFD_InitStruct->CANFD_BRS_TXM1 = DISABLE; + CANFD_InitStruct->CANFD_BRS_TXM2 = DISABLE; + + CANFD_InitStruct->CANFD_TDC_FILTER = 0; + CANFD_InitStruct->CANFD_TDC0 = 2; + CANFD_InitStruct->CANFD_TDCE = ENABLE; + + CANFD_InitStruct->CANFD_Mode = CAN_Mode_Normal; + CANFD_InitStruct->CANFD_SJW = CANFD_SJW_8tq; + CANFD_InitStruct->CANFD_BS1 = CANFD_BS1_7tq; + CANFD_InitStruct->CANFD_BS2 = CANFD_BS2_4tq; + CANFD_InitStruct->CANFD_Prescaler = 1; +} + +/********************************************************************* + * @fn CANFD_Transmit + * + * @brief Initiates the transmission of a message for CANFD. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TxMessage - pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * + * @return transmit_mailbox - The number of the mailbox that is used for + * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CANFD_Transmit(CAN_TypeDef* CANx, CanFDTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + + CANx->CANFD_CR |= (1); + + if ((CANx->TSTATR&CAN_TSTATR_TME0) == CAN_TSTATR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME1) == CAN_TSTATR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME2) == CAN_TSTATR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; + CANx->CANFD_DMA_T[transmit_mailbox] = (uint32_t)TxMessage->Data; + CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; + } + + return transmit_mailbox; +} + +/********************************************************************* + * @fn CANFD_Receive + * + * @brief Receives a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * RxMessage - pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * + * @return ErrorStatus - NoREADY or READY. + */ +ErrorStatus CANFD_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanFDRxMsg* RxMessage) +{ + ErrorStatus sta = NoREADY; + uint8_t len, i; + uint32_t adr; + + if((CANx->sFIFOMailBox[FIFONumber].RXMIR & 1) == 0) return sta; + + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + len = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; + + if(len <= 8) + { + RxMessage->DLC = len; + } + else if(len <= 12) + { + RxMessage->DLC = (len - 6) * 4; + } + else if(len <= 15) + { + RxMessage->DLC = (len - 11) * 16; + } + + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); + RxMessage->BRS = (uint8_t)0x01 & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 4); + RxMessage->ESI = (uint8_t)0x01 & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 5); + RxMessage->RES = (uint8_t)0x01 & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 6); + + adr = CANx->CANFD_DMA_R[FIFONumber] + 0x20000000; + + for(i=0; iDLC; i++) + { + RxMessage->Data[i] = *((uint8_t*)adr++); + } + + if (FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } + + sta = READY; + + return sta; +} + + +/********************************************************************* + * @fn CANFD_GetTransmitDelayOffsetVal + * + * @brief Returns the CANx Transmit Delay Offset Value. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return val - CAN Transmit Delay Offset Value. + */ +uint8_t CANFD_GetTransmitDelayOffsetVal(CAN_TypeDef *CANx) +{ + uint8_t val=0; + + val = (uint8_t)((CANx->CANFD_PSR & 0x00FF0000)>> 16); + + return val; +} + +/********************************************************************* + * @fn CANFD_TransmitMailbox_DMAAdr + * + * @brief Set Transmit Mailbox DMA address. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * MailboxNumber - Transmit Mailbox. + * CAN_Transmit_Mailbox0. + * CAN_Transmit_Mailbox1. + * CAN_Transmit_Mailbox2. + * address - DMA address. + * + * @return none. + */ +void CANFD_TransmitMailbox_DMAAdr(CAN_TypeDef *CANx, uint8_t MailboxNumber, uint32_t Address) +{ + CANx->CANFD_DMA_T[MailboxNumber] = Address; +} + +/********************************************************************* + * @fn CANFD_ReceiveFIFO_DMAAdr + * + * @brief Set receives FIFO DMA address. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * address - DMA address. + * + * @return none. + */ +void CANFD_ReceiveFIFO_DMAAdr(CAN_TypeDef *CANx, uint8_t FIFONumber, uint32_t Address) +{ + CANx->CANFD_DMA_R[FIFONumber] = Address; +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_crc.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_crc.c index d2eebe6..3f1137e 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_crc.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_crc.c @@ -1,99 +1,99 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_crc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the CRC firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_crc.h" - -/********************************************************************* - * @fn CRC_ResetDR - * - * @brief Resets the CRC Data register (DR). - * - * @return none - */ -void CRC_ResetDR(void) -{ - CRC->CTLR = CRC_CTLR_RESET; -} - -/********************************************************************* - * @fn CRC_CalcCRC - * - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * - * @param Data - data word(32-bit) to compute its CRC. - * - * @return 32-bit CRC. - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DATAR = Data; - - return (CRC->DATAR); -} - -/********************************************************************* - * @fn CRC_CalcBlockCRC - * - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * - * @param pBuffer - pointer to the buffer containing the data to be computed. - * BufferLength - length of the buffer to be computed. - * - * @return 32-bit CRC. - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++){ - CRC->DATAR = pBuffer[index]; - } - - return (CRC->DATAR); -} - -/********************************************************************* - * @fn CRC_GetCRC - * - * @brief Returns the current CRC value. - * - * @return 32-bit CRC. - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DATAR); -} - -/********************************************************************* - * @fn CRC_SetIDRegister - * - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * - * @param IDValue - 8-bit value to be stored in the ID register. - * - * @return none - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDATAR = IDValue; -} - -/********************************************************************* - * @fn CRC_GetIDRegister - * - * @brief Returns the 8-bit data stored in the Independent Data(ID) register. - * - * @return 8-bit value of the ID register. - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDATAR); -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_crc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the CRC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_crc.h" + +/********************************************************************* + * @fn CRC_ResetDR + * + * @brief Resets the CRC Data register (DR). + * + * @return none + */ +void CRC_ResetDR(void) +{ + CRC->CTLR = CRC_CTLR_RESET; +} + +/********************************************************************* + * @fn CRC_CalcCRC + * + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * + * @param Data - data word(32-bit) to compute its CRC. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DATAR = Data; + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_CalcBlockCRC + * + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * + * @param pBuffer - pointer to the buffer containing the data to be computed. + * BufferLength - length of the buffer to be computed. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++){ + CRC->DATAR = pBuffer[index]; + } + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_GetCRC + * + * @brief Returns the current CRC value. + * + * @return 32-bit CRC. + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_SetIDRegister + * + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * + * @param IDValue - 8-bit value to be stored in the ID register. + * + * @return none + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDATAR = IDValue; +} + +/********************************************************************* + * @fn CRC_GetIDRegister + * + * @brief Returns the 8-bit data stored in the Independent Data(ID) register. + * + * @return 8-bit value of the ID register. + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDATAR); +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_dbgmcu.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_dbgmcu.c index 9004d68..2a218c4 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_dbgmcu.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_dbgmcu.c @@ -1,128 +1,126 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_dbgmcu.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the DBGMCU firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_dbgmcu.h" - -#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) - - -/********************************************************************* - * @fn DBGMCU_GetREVID - * - * @brief Returns the device revision identifier. - * - * @return Revision identifier. - */ -uint32_t DBGMCU_GetREVID(void) -{ - return (CHIPID >> 16); -} - -/********************************************************************* - * @fn DBGMCU_GetDEVID - * - * @brief Returns the device identifier. - * - * @return Device identifier. - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return (CHIPID & IDCODE_DEVID_MASK); -} - -/********************************************************************* - * @fn __get_DEBUG_CR - * - * @brief Return the DEBUGE Control Register - * - * @return DEBUGE Control value - */ -uint32_t __get_DEBUG_CR(void) -{ - uint32_t result; - - __asm volatile("csrr %0,""0x7C0" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_DEBUG_CR - * - * @brief Set the DEBUGE Control Register - * - * @param value - set DEBUGE Control value - * - * @return none - */ -void __set_DEBUG_CR(uint32_t value) -{ - __asm volatile("csrw 0x7C0, %0" : : "r"(value)); -} - - -/********************************************************************* - * @fn DBGMCU_Config - * - * @brief Configures the specified peripheral and low power mode behavior - * when the MCU under Debug mode. - * - * @param DBGMCU_Periph - specifies the peripheral and low power mode. - * DBGMCU_SLEEP - Debug sleep stopped when Core is halted - * DBGMCU_STOP - Debug stop stopped when Core is halted - * DBGMCU_STANDBY - Debug standby stopped when Core is halted - * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted - * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted - * DBGMCU_I2C1_SMBUS_TIMEOUT - Debug I2C1 SMBUS time out when Core is halted - * DBGMCU_I2C2_SMBUS_TIMEOUT - Debug I2C2 SMBUS time out when Core is halted - * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted - * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted - * DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted - * DBGMCU_TIM4_STOP - TIM4 counter stopped when Core is halted - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - uint32_t val; - - if(NewState != DISABLE) - { - __set_DEBUG_CR(DBGMCU_Periph); - } - else - { - val = __get_DEBUG_CR(); - val &= ~(uint32_t)DBGMCU_Periph; - __set_DEBUG_CR(val); - } -} - -/********************************************************************* - * @fn DBGMCU_GetCHIPID - * - * @brief Returns the CHIP identifier. - * - * @return Device identifier. - * ChipID List- - * CH32L103C8U6-0x103007x0 - * CH32L103C8T6-0x103107x0 - * CH32L103F8P6-0x103A07x0 - * CH32L103G8R6-0x103B07x0 - * CH32L103K8U6-0x103207x0 - * CH32L103F8U6-0x103D07x0 - * CH32L103F7P6-0x103707x0 - * - */ -uint32_t DBGMCU_GetCHIPID( void ) -{ - return( CHIPID ); -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_dbgmcu.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/06 + * Description : This file provides all the DBGMCU firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_dbgmcu.h" + +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return (CHIPID >> 16); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return (CHIPID & IDCODE_DEVID_MASK); +} + +/********************************************************************* + * @fn __get_DEBUG_CR + * + * @brief Return the DEBUGE Control Register + * + * @return DEBUGE Control value + */ +uint32_t __get_DEBUG_CR(void) +{ + uint32_t result; + + __asm volatile("csrr %0,""0x7C0" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_DEBUG_CR + * + * @brief Set the DEBUGE Control Register + * + * @param value - set DEBUGE Control value + * + * @return none + */ +void __set_DEBUG_CR(uint32_t value) +{ + __asm volatile("csrw 0x7C0, %0" : : "r"(value)); +} + + +/********************************************************************* + * @fn DBGMCU_Config + * + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * + * @param DBGMCU_Periph - specifies the peripheral and low power mode. + * DBGMCU_SLEEP - Debug sleep stopped when Core is halted + * DBGMCU_STOP - Debug stop stopped when Core is halted + * DBGMCU_STANDBY - Debug standby stopped when Core is halted + * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted + * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted + * DBGMCU_I2C1_SMBUS_TIMEOUT - Debug I2C1 SMBUS time out when Core is halted + * DBGMCU_I2C2_SMBUS_TIMEOUT - Debug I2C2 SMBUS time out when Core is halted + * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted + * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted + * DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted + * DBGMCU_TIM4_STOP - TIM4 counter stopped when Core is halted + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + uint32_t val; + + if(NewState != DISABLE) + { + __set_DEBUG_CR(DBGMCU_Periph); + } + else + { + val = __get_DEBUG_CR(); + val &= ~(uint32_t)DBGMCU_Periph; + __set_DEBUG_CR(val); + } +} + +/********************************************************************* + * @fn DBGMCU_GetCHIPID + * + * @brief Returns the CHIP identifier. + * + * @return Device identifier. + * ChipID List- + * CH32L103C8T6-0x103107x0 + * CH32L103F8P6-0x103A07x0 + * CH32L103G8R6-0x103B07x0 + * CH32L103K8U6-0x103207x0 + * CH32L103F8U6-0x103D07x0 + * + */ +uint32_t DBGMCU_GetCHIPID( void ) +{ + return( CHIPID ); +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_dma.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_dma.c index 53feb25..72356df 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_dma.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_dma.c @@ -1,432 +1,432 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_dma.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the DMA firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_dma.h" -#include "ch32l103_rcc.h" - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) -#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) -#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) -#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) -#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) -#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) -#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) -#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) - -/* DMA registers Masks */ -#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) - -/********************************************************************* - * @fn DMA_DeInit - * - * @brief Deinitializes the DMAy Channelx registers to their default - * reset values. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * - * @return none - */ -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) -{ - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - DMAy_Channelx->CFGR = 0; - DMAy_Channelx->CNTR = 0; - DMAy_Channelx->PADDR = 0; - DMAy_Channelx->MADDR = 0; - if(DMAy_Channelx == DMA1_Channel1) - { - DMA1->INTFCR |= DMA1_Channel1_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel2) - { - DMA1->INTFCR |= DMA1_Channel2_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel3) - { - DMA1->INTFCR |= DMA1_Channel3_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel4) - { - DMA1->INTFCR |= DMA1_Channel4_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel5) - { - DMA1->INTFCR |= DMA1_Channel5_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel6) - { - DMA1->INTFCR |= DMA1_Channel6_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel7) - { - DMA1->INTFCR |= DMA1_Channel7_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel8) - { - DMA1->INTFCR |= DMA1_Channel8_IT_Mask; - } -} - -/********************************************************************* - * @fn DMA_Init - * - * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - tmpreg = DMAy_Channelx->CFGR; - tmpreg &= CFGR_CLEAR_Mask; - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - DMAy_Channelx->CFGR = tmpreg; - DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; - DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; - DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/********************************************************************* - * @fn DMA_StructInit - * - * @brief Fills each DMA_InitStruct member with its default value. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) -{ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - DMA_InitStruct->DMA_BufferSize = 0; - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/********************************************************************* - * @fn DMA_Cmd - * - * @brief Enables or disables the specified DMAy Channelx. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_CFGR1_EN; - } - else - { - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - } -} - -/********************************************************************* - * @fn DMA_ITConfig - * - * @brief Enables or disables the specified DMAy Channelx interrupts. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * DMA_IT - specifies the DMA interrupts sources to be enabled - * or disabled. - * DMA_IT_TC - Transfer complete interrupt mask - * DMA_IT_HT - Half transfer interrupt mask - * DMA_IT_TE - Transfer error interrupt mask - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_IT; - } - else - { - DMAy_Channelx->CFGR &= ~DMA_IT; - } -} - -/********************************************************************* - * @fn DMA_SetCurrDataCounter - * - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * DataNumber - The number of data units in the current DMAy Channelx - * transfer. - * - * @return none - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) -{ - DMAy_Channelx->CNTR = DataNumber; -} - -/********************************************************************* - * @fn DMA_GetCurrDataCounter - * - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * - * @return DataNumber - The number of remaining data units in the current - * DMAy Channelx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) -{ - return ((uint16_t)(DMAy_Channelx->CNTR)); -} - -/********************************************************************* - * @fn DMA_GetFlagStatus - * - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. - * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. - * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. - * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. - * - * @return The new state of DMAy_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - tmpreg = DMA1->INTFR; - - if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearFlag - * - * @brief Clears the DMAy Channelx's pending flags. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. - * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. - * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. - * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. - * - * @return none - */ -void DMA_ClearFlag(uint32_t DMAy_FLAG) -{ - DMA1->INTFCR = DMAy_FLAG; -} - -/********************************************************************* - * @fn DMA_GetITStatus - * - * @brief Checks whether the specified DMAy Channelx interrupt has - * occurred or not. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * DMA1_IT_GL8 - DMA1 Channel8 global flag. - * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. - * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. - * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. - * - * @return The new state of DMAy_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMAy_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - tmpreg = DMA1->INTFR; - - if((tmpreg & DMAy_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearITPendingBit - * - * @brief Clears the DMAy Channelx's interrupt pending bits. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * DMA1_IT_GL8 - DMA1 Channel8 global flag. - * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. - * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. - * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. - * - * @return none - */ -void DMA_ClearITPendingBit(uint32_t DMAy_IT) -{ - DMA1->INTFCR = DMAy_IT; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_dma.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the DMA firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_dma.h" +#include "ch32l103_rcc.h" + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel8) + { + DMA1->INTFCR |= DMA1_Channel8_IT_Mask; + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. + * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. + * + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. + * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. + * + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + DMA1->INTFCR = DMAy_FLAG; +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_IT_GL8 - DMA1 Channel8 global flag. + * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. + * + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_IT_GL8 - DMA1 Channel8 global flag. + * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. + * + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + DMA1->INTFCR = DMAy_IT; +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_exti.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_exti.c index 5cdc822..98a16bb 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_exti.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_exti.c @@ -1,182 +1,182 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_exti.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the EXTI firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_exti.h" - -/* No interrupt selected */ -#define EXTI_LINENONE ((uint32_t)0x000000) - -/********************************************************************* - * @fn EXTI_DeInit - * - * @brief Deinitializes the EXTI peripheral registers to their default - * reset values. - * - * @return none. - */ -void EXTI_DeInit(void) -{ - EXTI->INTENR = 0x00000000; - EXTI->EVENR = 0x00000000; - EXTI->RTENR = 0x00000000; - EXTI->FTENR = 0x00000000; - EXTI->INTFR = 0x007FFFFF; -} - -/********************************************************************* - * @fn EXTI_Init - * - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) -{ - uint32_t tmp = 0; - - tmp = (uint32_t)EXTI_BASE; - if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; - if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/********************************************************************* - * @fn EXTI_StructInit - * - * @brief Fills each EXTI_InitStruct member with its reset value. - * - * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/********************************************************************* - * @fn EXTI_GenerateSWInterrupt - * - * @brief Generates a Software interrupt. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none. - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - EXTI->SWIEVR |= EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetFlagStatus - * - * @brief Checks whether the specified EXTI line flag is set or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearFlag - * - * @brief Clears the EXTI's line pending flags. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetITStatus - * - * @brief Checks whether the specified EXTI line is asserted or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = EXTI->INTENR & EXTI_Line; - if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearITPendingBit - * - * @brief Clears the EXTI's line pending bits. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_exti.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the EXTI firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_exti.h" + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x000000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x007FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_flash.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_flash.c index e9495ec..3468792 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_flash.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_flash.c @@ -1,1011 +1,1011 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_flash.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the FLASH firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_flash.h" - -/* Flash Access Control Register bits */ -#define ACR_LATENCY_Mask ((uint32_t)0xFFFFFFFC) - -/* Flash Control Register bits */ -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) -#define CR_FLOCK_Set ((uint32_t)0x00008000) -#define CR_PAGE_PG ((uint32_t)0x00010000) -#define CR_PAGE_ER ((uint32_t)0x00020000) -#define CR_PAGE_ER_Reset ((uint32_t)0xFFFDFFFF) -#define CR_BUF_LOAD ((uint32_t)0x00040000) -#define CR_BUF_RST ((uint32_t)0x00080000) -#define CR_BER32 ((uint32_t)0x00800000) - -/* FLASH Status Register bits */ -#define SR_BSY ((uint32_t)0x00000001) -#define SR_WRPRTERR ((uint32_t)0x00000010) -#define SR_EOP ((uint32_t)0x00000020) - -/* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) - -/* FLASH Keys */ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) - -/* Delay definition */ -#define EraseTimeout ((uint32_t)0x000B0000) -#define ProgramTimeout ((uint32_t)0x00005000) - -/* Flash Program Valid Address */ -#define ValidAddrStart (FLASH_BASE) -#define ValidAddrEnd (FLASH_BASE + 0xF800) - -/* FLASH Size */ -#define Size_256B 0x100 -#define Size_1KB 0x400 -#define Size_32KB 0x8000 - -/******************************************************************************** - * @fn FLASH_SetLatency - * - * @brief Sets the code latency value. - * - * @param FLASH_Latency - specifies the FLASH Latency mode. - * FLASH_Latency_0 - FLASH Latency mode 0 - * FLASH_Latency_1 - FLASH Latency mode 1 - * FLASH_Latency_2 - FLASH Latency mode 2 - * - * @return None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - tmpreg = FLASH->ACTLR; - tmpreg &= ACR_LATENCY_Mask; - tmpreg |= FLASH_Latency; - FLASH->ACTLR = tmpreg; -} - -/******************************************************************************** - * @fn FLASH_Unlock - * - * @brief Unlocks the FLASH Program Erase Controller. - * - * @return None - */ -void FLASH_Unlock(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -/******************************************************************************** - * @fn FLASH_Lock - * - * @brief Locks the FLASH Program Erase Controller. - * - * @return None - */ -void FLASH_Lock(void) -{ - FLASH->CTLR |= CR_LOCK_Set; -} - -/******************************************************************************** - * @fn FLASH_ErasePage - * - * @brief Erases a specified FLASH page(1KB). - * - * @param Page_Address - The page address to be erased. - * - * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - FLASH->CTLR |= CR_PER_Set; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_PER_Reset; - } - - return status; -} - -/******************************************************************************** - * @fn FLASH_EraseAllPages - * - * @brief Erases all FLASH pages. - * - * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - FLASH->CTLR |= CR_MER_Set; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_MER_Reset; - } - - return status; -} - -/******************************************************************************** - * @fn FLASH_EraseOptionBytes - * - * @brief Erases the FLASH option bytes. - * - * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseOptionBytes(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH_Unlock(); - - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_OPTER_Reset; - - FLASH_Lock(); - } - return status; -} - -/********************************************************************* - * @fn FLASH_OptionBytePR - * - * @brief Programs option bytes. - * - * @param pbuf - data. - * - * @return none - */ -void FLASH_OptionBytePR(u32* pbuf) -{ - uint8_t i; - - FLASH_EraseOptionBytes(); - FLASH_Unlock_Fast(); - FLASH_BufReset(); - - for(i=0; i<4; i++) - { - FLASH_BufLoad((OB_BASE + 4*i), *pbuf++); - } - - FLASH_ProgramPage_Fast(OB_BASE); - FLASH_Lock_Fast(); -} - -/********************************************************************* - * @fn FLASH_EnableWriteProtection - * - * @brief Write protects the desired sectors - * - * @param FLASH_Sectors - specifies the address of the pages to be write protected. - * - * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. - */ -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) -{ - uint8_t WRP0_Data = 0xFF, WRP1_Data = 0xFF, WRP2_Data = 0xFF, WRP3_Data = 0xFF; - uint32_t buf[4]; - uint8_t i; - FLASH_Status status = FLASH_COMPLETE; - - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - status = FLASH_RDP; - } - else{ - FLASH_Pages = (uint32_t)(~FLASH_Pages); - WRP0_Data = (uint8_t)(FLASH_Pages & WRP0_Mask); - WRP1_Data = (uint8_t)((FLASH_Pages & WRP1_Mask) >> 8); - WRP2_Data = (uint8_t)((FLASH_Pages & WRP2_Mask) >> 16); - WRP3_Data = (uint8_t)((FLASH_Pages & WRP3_Mask) >> 24); - - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - for(i=0; i<4; i++){ - buf[i] = *(uint32_t*)(OB_BASE + 4*i); - } - - buf[2] = ((uint32_t)(((uint32_t)(WRP0_Data) & 0x00FF) + (((uint32_t)(~WRP0_Data) & 0x00FF) << 8) \ - + (((uint32_t)(WRP1_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP1_Data) & 0x00FF) << 24))); - buf[3] = ((uint32_t)(((uint32_t)(WRP2_Data) & 0x00FF) + (((uint32_t)(~WRP2_Data) & 0x00FF) << 8) \ - + (((uint32_t)(WRP3_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP3_Data) & 0x00FF) << 24))); - - FLASH_OptionBytePR(buf); - } - } - - return status; -} - -/********************************************************************* - * @fn FLASH_EnableReadOutProtection - * - * @brief Enables the read out protection. - * - * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). - * - * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT or FLASH_RDP. - */ -FLASH_Status FLASH_EnableReadOutProtection(void) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t buf[4]; - uint8_t i; - - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - status = FLASH_RDP; - } - else{ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - for(i=0; i<4; i++){ - buf[i] = *(uint32_t*)(OB_BASE + 4*i); - } - - buf[0] = 0x000000FF + (buf[0] & 0xFFFF0000); - FLASH_OptionBytePR(buf); - } - } - - return status; -} - -/********************************************************************* - * @fn FLASH_UserOptionByteConfig - * - * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY/CAN_BusOff_MODE. - * - * @param OB_IWDG - Selects the IWDG mode. - * OB_IWDG_SW - Software IWDG selected - * OB_IWDG_HW - Hardware IWDG selected - * OB_STOP - Reset event when entering STOP mode. - * OB_STOP_NoRST - No reset generated when entering in STOP - * OB_STOP_RST - Reset generated when entering in STOP - * OB_STDBY - Reset event when entering Standby mode. - * OB_STDBY_NoRST - No reset generated when entering in STANDBY - * OB_STDBY_RST - Reset generated when entering in STANDBY - * OB_CAN - Set CAN bus off recovery time. - * OB_CAN_BusOff_MODE1 - Faster recovery time from Bus off. - * OB_CAN_BusOff_MODE2 - Normal recovery time from bus off. - * - * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. - */ -FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_CAN) -{ - FLASH_Status status = FLASH_COMPLETE; - uint8_t UserByte; - uint32_t buf[4]; - uint8_t i; - - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - status = FLASH_RDP; - } - else{ - UserByte = OB_IWDG | (uint8_t)(OB_STOP | (uint8_t)(OB_STDBY | (uint8_t)(OB_CAN | (uint8_t)0xD8))); - - for(i=0; i<4; i++){ - buf[i] = *(uint32_t*)(OB_BASE + 4*i); - } - buf[0] = ((uint32_t)((((uint32_t)(UserByte) & 0x00FF) << 16) + (((uint32_t)(~UserByte) & 0x00FF) << 24))) + 0x00005AA5; - - FLASH_OptionBytePR(buf); - } - - return status; -} - -/********************************************************************* - * @fn FLASH_GetUserOptionByte - * - * @brief Returns the FLASH User Option Bytes values. - * - * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1), - * RST_STDBY(Bit2) ,CAN_BusOff_MODE(bit7) ,DATA0(bit[15:8]) and - * DATA1(bit[23:16]). - */ -uint32_t FLASH_GetUserOptionByte(void) -{ - return (uint32_t)(FLASH->OBR >> 2); -} - -/********************************************************************* - * @fn FLASH_GetWriteProtectionOptionByte - * - * @brief Returns the FLASH Write Protection Option Bytes Register value. - * - * @return The FLASH Write Protection Option Bytes Register value. - */ -uint32_t FLASH_GetWriteProtectionOptionByte(void) -{ - return (uint32_t)(FLASH->WPR); -} - -/********************************************************************* - * @fn FLASH_GetReadOutProtectionStatus - * - * @brief Checks whether the FLASH Read Out Protection Status is set or not. - * - * @return FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetReadOutProtectionStatus(void) -{ - FlagStatus readoutstatus = RESET; - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - readoutstatus = SET; - } - else - { - readoutstatus = RESET; - } - return readoutstatus; -} - -/********************************************************************* - * @fn FLASH_ITConfig - * - * @brief Enables or disables the specified FLASH interrupts. - * - * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. - * FLASH_IT_ERROR - FLASH Error Interrupt - * FLASH_IT_EOP - FLASH end of operation Interrupt - * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). - * - * @return FLASH Prefetch Buffer Status (SET or RESET). - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - FLASH->CTLR |= FLASH_IT; - } - else - { - FLASH->CTLR &= ~(uint32_t)FLASH_IT; - } -} - -/********************************************************************* - * @fn FLASH_GetFlagStatus - * - * @brief Checks whether the specified FLASH flag is set or not. - * - * @param FLASH_FLAG - specifies the FLASH flag to check. - * FLASH_FLAG_BSY - FLASH Busy flag - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * FLASH_FLAG_WAKE_UP - FLASH Wake up of Operation flag - * FLASH_FLAG_OPTERR - FLASH Option Byte error flag - * - * @return The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - return bitstatus; -} - -/********************************************************************* - * @fn FLASH_ClearFlag - * - * @brief Clears the FLASH's pending flags. - * - * @param FLASH_FLAG - specifies the FLASH flags to clear. - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * - * @return none - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - FLASH->STATR = FLASH_FLAG; -} - -/********************************************************************* - * @fn FLASH_GetStatus - * - * @brief Returns the FLASH Status. - * - * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_GetBank1Status - * - * @brief Returns the FLASH Bank1 Status. - * - * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetBank1Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_WaitForLastOperation - * - * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_WaitForLastBank1Operation - * - * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_Unlock_Fast - * - * @brief Unlocks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Unlock_Fast(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - - /* Fast program mode unlock */ - FLASH->MODEKEYR = FLASH_KEY1; - FLASH->MODEKEYR = FLASH_KEY2; -} - -/********************************************************************* - * @fn FLASH_Lock_Fast - * - * @brief Locks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Lock_Fast(void) -{ - FLASH->CTLR |= CR_FLOCK_Set; -} - -/********************************************************************* - * @fn FLASH_BufReset - * - * @brief Flash Buffer reset. - * - * @return none - */ -void FLASH_BufReset(void) -{ - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - FLASH->CTLR |= CR_PAGE_PG; - FLASH->CTLR |= CR_BUF_RST; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; -} - -/********************************************************************* - * @fn FLASH_BufLoad - * - * @brief Flash Buffer load(4Byte). - * - * @param Address - specifies the address to be programmed. - * Data0 - specifies the data0 to be programmed. - * - * @return none - */ -void FLASH_BufLoad(uint32_t Address, uint32_t Data0) -{ - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - FLASH->CTLR |= CR_PAGE_PG; - *(__IO uint32_t *)(Address) = Data0; - FLASH->CTLR |= CR_BUF_LOAD; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; -} - -/********************************************************************* - * @fn FLASH_ErasePage_Fast - * - * @brief Erases a specified FLASH page (1page = 256Byte). - * - * @param Page_Address - The page address to be erased. - * - * @return none - */ -void FLASH_ErasePage_Fast(uint32_t Page_Address) -{ - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - FLASH->CTLR |= CR_PAGE_ER; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_ER; -} - -/********************************************************************* - * @fn FLASH_EraseBlock_32K_Fast - * - * @brief Erases a specified FLASH Block (1Block = 32KByte). - * - * @param Block_Address - The block address to be erased. - * - * @return none - */ -void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) -{ - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - Block_Address &= 0xFFFF8000; - - FLASH->CTLR |= CR_BER32; - FLASH->ADDR = Block_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_BER32; -} - -/********************************************************************* - * @fn FLASH_ProgramPage_Fast - * - * @brief Program a specified FLASH page (1page = 256Byte). - * - * @param Page_Address - The page address to be programed. - * - * @return none - */ -void FLASH_ProgramPage_Fast(uint32_t Page_Address) -{ - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - FLASH->CTLR |= CR_PAGE_PG; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; -} - -/********************************************************************* - * @fn ROM_ERASE - * - * @brief Select erases a specified FLASH . - * - * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). - * Cnt - Erases count. - * Erase_Size - Erases size select.The returned value can be: - * Size_32KB, Size_1KB, Size_256B. - * - * @return none. - */ -static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) -{ - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - do{ - if(Erase_Size == Size_32KB) - { - FLASH->CTLR |= CR_BER32; - } - else if(Erase_Size == Size_1KB) - { - FLASH->CTLR |= CR_PER_Set; - } - else if(Erase_Size == Size_256B) - { - FLASH->CTLR |= CR_PAGE_ER; - } - - FLASH->ADDR = StartAddr; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - - if(Erase_Size == Size_32KB) - { - FLASH->CTLR &= ~CR_BER32; - StartAddr += Size_32KB; - } - else if(Erase_Size == Size_1KB) - { - FLASH->CTLR &= ~CR_PER_Set; - StartAddr += Size_1KB; - } - else if(Erase_Size == Size_256B) - { - FLASH->CTLR &= ~CR_PAGE_ER; - StartAddr += Size_256B; - } - }while(--Cnt); -} - -/********************************************************************* - * @fn FLASH_ROM_ERASE - * - * @brief Erases a specified FLASH . - * - * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). - * Length - Erases Flash start Length(Length%256 == 0). - * - * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, - * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length) -{ - uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; - - FLASH_Status status = FLASH_COMPLETE; - - if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) - { - return FLASH_ADR_RANGE_ERROR; - } - - if((StartAddr + Length) > ValidAddrEnd) - { - return FLASH_OP_RANGE_ERROR; - } - - if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) - { - return FLASH_ALIGN_ERROR; - } - - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - - /* Fast mode unlock */ - FLASH->MODEKEYR = FLASH_KEY1; - FLASH->MODEKEYR = FLASH_KEY2; - - Addr0 = StartAddr; - - if(Length >= Size_32KB) - { - Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); - Addr1 = StartAddr + Length0; - Length1 = Length - Length0; - } - else if(Length >= Size_1KB) - { - Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); - Addr1 = StartAddr + Length0; - Length1 = Length - Length0; - } - else if(Length >= Size_256B) - { - Length0 = Length; - } - - /* Erase 32KB */ - if(Length0 >= Size_32KB)//front - { - Length = Length0; - if(Addr0 & (Size_32KB - 1)) - { - Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); - } - else - { - Length0 = 0; - } - - ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB); - } - - if(Length1 >= Size_32KB)//back - { - StartAddr = Addr1; - Length = Length1; - - if((Addr1 + Length1) & (Size_32KB - 1)) - { - Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1))); - Length1 = (StartAddr + Length1) & (Size_32KB - 1); - } - else - { - Length1 = 0; - } - - ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB); - } - - /* Erase 1KB */ - if(Length0 >= Size_1KB) //front - { - Length = Length0; - if(Addr0 & (Size_1KB - 1)) - { - Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); - } - else - { - Length0 = 0; - } - - ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB); - } - - if(Length1 >= Size_1KB) //back - { - StartAddr = Addr1; - Length = Length1; - - if((Addr1 + Length1) & (Size_1KB - 1)) - { - Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1))); - Length1 = (StartAddr + Length1) & (Size_1KB - 1); - } - else - { - Length1 = 0; - } - - ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB); - } - - /* Erase 256B */ - if(Length0)//front - { - ROM_ERASE(Addr0, (Length0 >> 8), Size_256B); - } - - if(Length1)//back - { - ROM_ERASE(Addr1, (Length1 >> 8), Size_256B); - } - - FLASH->CTLR |= CR_FLOCK_Set; - FLASH->CTLR |= CR_LOCK_Set; - - return status; -} - -/********************************************************************* - * @fn FLASH_ROM_WRITE - * - * @brief Writes a specified FLASH . - * - * @param StartAddr - Writes Flash start address(StartAddr%256 == 0). - * Length - Writes Flash start Length(Length%256 == 0). - * pbuf - Writes Flash value buffer. - * - * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, - * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length) -{ - uint32_t i, adr; - uint8_t size; - - FLASH_Status status = FLASH_COMPLETE; - - if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) - { - return FLASH_ADR_RANGE_ERROR; - } - - if((StartAddr + Length) > ValidAddrEnd) - { - return FLASH_OP_RANGE_ERROR; - } - - if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) - { - return FLASH_ALIGN_ERROR; - } - adr = StartAddr; - i = Length >> 8; - - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - - /* Fast program mode unlock */ - FLASH->MODEKEYR = FLASH_KEY1; - FLASH->MODEKEYR = FLASH_KEY2; - - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - do{ - FLASH->CTLR |= CR_PAGE_PG; - FLASH->CTLR |= CR_BUF_RST; - while(FLASH->STATR & SR_BSY) - ; - size = 64; - while(size) - { - *(uint32_t *)StartAddr = *(uint32_t *)pbuf; - FLASH->CTLR |= CR_BUF_LOAD; - while(FLASH->STATR & SR_BSY) - ; - StartAddr += 4; - pbuf += 1; - size -= 1; - } - - FLASH->ADDR = adr; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; - adr += 256; - }while(--i); - - FLASH->CTLR |= CR_FLOCK_Set; - FLASH->CTLR |= CR_LOCK_Set; - - return status; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_flash.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/04/26 + * Description : This file provides all the FLASH firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_flash.h" + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0xFFFFFFFC) + +/* Flash Control Register bits */ +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FLOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_PAGE_ER_Reset ((uint32_t)0xFFFDFFFF) +#define CR_BUF_LOAD ((uint32_t)0x00040000) +#define CR_BUF_RST ((uint32_t)0x00080000) +#define CR_BER32 ((uint32_t)0x00800000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00005000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x10000) + +/* FLASH Size */ +#define Size_256B 0x100 +#define Size_1KB 0x400 +#define Size_32KB 0x8000 + +/******************************************************************************** + * @fn FLASH_SetLatency + * + * @brief Sets the code latency value. + * + * @param FLASH_Latency - specifies the FLASH Latency mode. + * FLASH_Latency_0 - FLASH Latency mode 0 + * FLASH_Latency_1 - FLASH Latency mode 1 + * FLASH_Latency_2 - FLASH Latency mode 2 + * + * @return None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + tmpreg = FLASH->ACTLR; + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + FLASH->ACTLR = tmpreg; +} + +/******************************************************************************** + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/******************************************************************************** + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/******************************************************************************** + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page(1KB). + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH_Unlock(); + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_OPTER_Reset; + + FLASH_Lock(); + } + return status; +} + +/********************************************************************* + * @fn FLASH_OptionBytePR + * + * @brief Programs option bytes. + * + * @param pbuf - data. + * + * @return none + */ +void FLASH_OptionBytePR(u32* pbuf) +{ + uint8_t i; + + FLASH_EraseOptionBytes(); + FLASH_Unlock_Fast(); + FLASH_BufReset(); + + for(i=0; i<4; i++) + { + FLASH_BufLoad((OB_BASE + 4*i), *pbuf++); + } + + FLASH_ProgramPage_Fast(OB_BASE); + FLASH_Lock_Fast(); +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Sectors - specifies the address of the pages to be write protected. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint8_t WRP0_Data = 0xFF, WRP1_Data = 0xFF, WRP2_Data = 0xFF, WRP3_Data = 0xFF; + uint32_t buf[4]; + uint8_t i; + FLASH_Status status = FLASH_COMPLETE; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint8_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint8_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint8_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint8_t)((FLASH_Pages & WRP3_Mask) >> 24); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + + buf[2] = ((uint32_t)(((uint32_t)(WRP0_Data) & 0x00FF) + (((uint32_t)(~WRP0_Data) & 0x00FF) << 8) \ + + (((uint32_t)(WRP1_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP1_Data) & 0x00FF) << 24))); + buf[3] = ((uint32_t)(((uint32_t)(WRP2_Data) & 0x00FF) + (((uint32_t)(~WRP2_Data) & 0x00FF) << 8) \ + + (((uint32_t)(WRP3_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP3_Data) & 0x00FF) << 24))); + + FLASH_OptionBytePR(buf); + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EnableReadOutProtection + * + * @brief Enables the read out protection. + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_EnableReadOutProtection(void) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t buf[4]; + uint8_t i; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + + buf[0] = 0x000000FF + (buf[0] & 0xFFFF0000); + FLASH_OptionBytePR(buf); + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY/CAN_BusOff_MODE. + * + * @param OB_IWDG - Selects the IWDG mode. + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STOP - Reset event when entering STOP mode. + * OB_STOP_NoRST - No reset generated when entering in STOP + * OB_STOP_RST - Reset generated when entering in STOP + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY + * OB_STDBY_RST - Reset generated when entering in STANDBY + * OB_CAN - Set CAN bus off recovery time. + * OB_CAN_BusOff_MODE1 - Faster recovery time from Bus off. + * OB_CAN_BusOff_MODE2 - Normal recovery time from bus off. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_CAN) +{ + FLASH_Status status = FLASH_COMPLETE; + uint8_t UserByte; + uint32_t buf[4]; + uint8_t i; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + UserByte = OB_IWDG | (uint8_t)(OB_STOP | (uint8_t)(OB_STDBY | (uint8_t)(OB_CAN | (uint8_t)0xD8))); + + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + buf[0] = ((uint32_t)((((uint32_t)(UserByte) & 0x00FF) << 16) + (((uint32_t)(~UserByte) & 0x00FF) << 24))) + 0x00005AA5; + + FLASH_OptionBytePR(buf); + } + + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1), + * RST_STDBY(Bit2) ,CAN_BusOff_MODE(bit7) ,DATA0(bit[15:8]) and + * DATA1(bit[23:16]). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt + * FLASH_IT_EOP - FLASH end of operation Interrupt + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_WAKE_UP - FLASH Wake up of Operation flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + FLASH->STATR = FLASH_FLAG; +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_FLOCK_Set; +} + +/********************************************************************* + * @fn FLASH_BufReset + * + * @brief Flash Buffer reset. + * + * @return none + */ +void FLASH_BufReset(void) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_BufLoad + * + * @brief Flash Buffer load(4Byte). + * + * @param Address - specifies the address to be programmed. + * Data0 - specifies the data0 to be programmed. + * + * @return none + */ +void FLASH_BufLoad(uint32_t Address, uint32_t Data0) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + *(__IO uint32_t *)(Address) = Data0; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_ER; +} + +/********************************************************************* + * @fn FLASH_EraseBlock_32K_Fast + * + * @brief Erases a specified FLASH Block (1Block = 32KByte). + * + * @param Block_Address - The block address to be erased. + * + * @return none + */ +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + Block_Address &= 0xFFFF8000; + + FLASH->CTLR |= CR_BER32; + FLASH->ADDR = Block_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_BER32; +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn ROM_ERASE + * + * @brief Select erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Cnt - Erases count. + * Erase_Size - Erases size select.The returned value can be: + * Size_32KB, Size_1KB, Size_256B. + * + * @return none. + */ +static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + do{ + if(Erase_Size == Size_32KB) + { + FLASH->CTLR |= CR_BER32; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR |= CR_PER_Set; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR |= CR_PAGE_ER; + } + + FLASH->ADDR = StartAddr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + + if(Erase_Size == Size_32KB) + { + FLASH->CTLR &= ~CR_BER32; + StartAddr += Size_32KB; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR &= ~CR_PER_Set; + StartAddr += Size_1KB; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR &= ~CR_PAGE_ER; + StartAddr += Size_256B; + } + }while(--Cnt); +} + +/********************************************************************* + * @fn FLASH_ROM_ERASE + * + * @brief Erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Length - Erases Flash start Length(Length%256 == 0). + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length) +{ + uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + Addr0 = StartAddr; + + if(Length >= Size_32KB) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_1KB) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_256B) + { + Length0 = Length; + } + + /* Erase 32KB */ + if(Length0 >= Size_32KB)//front + { + Length = Length0; + if(Addr0 & (Size_32KB - 1)) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB); + } + + if(Length1 >= Size_32KB)//back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_32KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1))); + Length1 = (StartAddr + Length1) & (Size_32KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB); + } + + /* Erase 1KB */ + if(Length0 >= Size_1KB) //front + { + Length = Length0; + if(Addr0 & (Size_1KB - 1)) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB); + } + + if(Length1 >= Size_1KB) //back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_1KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1))); + Length1 = (StartAddr + Length1) & (Size_1KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB); + } + + /* Erase 256B */ + if(Length0)//front + { + ROM_ERASE(Addr0, (Length0 >> 8), Size_256B); + } + + if(Length1)//back + { + ROM_ERASE(Addr1, (Length1 >> 8), Size_256B); + } + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + +/********************************************************************* + * @fn FLASH_ROM_WRITE + * + * @brief Writes a specified FLASH . + * + * @param StartAddr - Writes Flash start address(StartAddr%256 == 0). + * Length - Writes Flash start Length(Length%256 == 0). + * pbuf - Writes Flash value buffer. + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length) +{ + uint32_t i, adr; + uint8_t size; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + adr = StartAddr; + i = Length >> 8; + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + do{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + size = 64; + while(size) + { + *(uint32_t *)StartAddr = *(uint32_t *)pbuf; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + StartAddr += 4; + pbuf += 1; + size -= 1; + } + + FLASH->ADDR = adr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + adr += 256; + }while(--i); + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_gpio.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_gpio.c index 8769f7d..708f735 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_gpio.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_gpio.c @@ -1,716 +1,696 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_gpio.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the GPIO firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_gpio.h" -#include "ch32l103_rcc.h" - -/* MASK */ -#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF8FFFFFF) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) -#define REMAP_MASK ((uint32_t)0xC0000000) -#define REMAP_NUM_MASK ((uint32_t)0x38000000) - -uint32_t OPA_Trim = 0; -uint16_t ADC_Trim = 0; -uint32_t TS_Val = 0; -uint32_t CHIPID = 0; - -/********************************************************************* - * @fn GPIO_DeInit - * - * @brief Deinitializes the GPIOx peripheral registers to their default - * reset values. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * - * @return none - */ -void GPIO_DeInit(GPIO_TypeDef *GPIOx) -{ - if(GPIOx == GPIOA) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOA, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOA, DISABLE); - } - else if(GPIOx == GPIOB) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOB, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOB, DISABLE); - } - else if(GPIOx == GPIOC) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOC, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOC, DISABLE); - } - else if(GPIOx == GPIOD) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOD, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOD, DISABLE); - } -} - -/********************************************************************* - * @fn GPIO_AFIODeInit - * - * @brief Deinitializes the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * - * @return none - */ -void GPIO_AFIODeInit(void) -{ - RCC_PB2PeriphResetCmd(RCC_PB2Periph_AFIO, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_AFIO, DISABLE); -} - -/********************************************************************* - * @fn GPIO_Init - * - * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. - * - * @return none - */ -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - - if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - { - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } - - if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) - { - tmpreg = GPIOx->CFGLR; - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << pinpos); - } - else - { - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CFGLR = tmpreg; - } - - if(GPIO_InitStruct->GPIO_Pin > 0x00FF) - { - tmpreg = GPIOx->CFGHR; - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x08)); - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - } - } - GPIOx->CFGHR = tmpreg; - } -} - -/********************************************************************* - * @fn GPIO_StructInit - * - * @brief Fills each GPIO_InitStruct member with its default - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) -{ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/********************************************************************* - * @fn GPIO_ReadInputDataBit - * - * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. - * - * @param GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * - * @return The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadInputData - * - * @brief Reads the specified GPIO input data port. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * - * @return The output port pin value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) -{ - uint16_t val; - - val = ( uint16_t )GPIOx->INDR; - - return ( val ); -} - -/********************************************************************* - * @fn GPIO_ReadOutputDataBit - * - * @brief Reads the specified output data port bit. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadOutputData - * - * @brief Reads the specified GPIO output data port. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * - * @return GPIO output port pin value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) -{ - uint16_t val; - - val = ( uint16_t )GPIOx->OUTDR; - - return ( val ); -} - -/********************************************************************* - * @fn GPIO_SetBits - * - * @brief Sets the selected data port bits. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BSHR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_ResetBits - * - * @brief Clears the selected data port bits. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BCR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_WriteBit - * - * @brief Sets or clears the selected data port bit. - * - * @param GPIO_Pin - specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * BitVal - specifies the value to be written to the selected bit. - * Bit_RESET - to clear the port pin. - * Bit_SET - to set the port pin. - * - * @return none - */ -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - if(BitVal != Bit_RESET) - { - GPIOx->BSHR = GPIO_Pin; - } - else - { - GPIOx->BCR = GPIO_Pin; - } -} - -/********************************************************************* - * @fn GPIO_Write - * - * @brief Writes data to the specified GPIO data port. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * PortVal - specifies the value to be written to the port output data register. - * - * @return none - */ -void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) -{ - GPIOx->OUTDR = PortVal; -} - -/********************************************************************* - * @fn GPIO_PinLockConfig - * - * @brief Locks GPIO Pins configuration registers. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - - tmp |= GPIO_Pin; - GPIOx->LCKR = tmp; - GPIOx->LCKR = GPIO_Pin; - GPIOx->LCKR = tmp; - tmp = GPIOx->LCKR; - tmp = GPIOx->LCKR; -} - -/********************************************************************* - * @fn GPIO_EventOutputConfig - * - * @brief Selects the GPIO pin used as Event output. - * - * @param GPIO_PortSource - selects the GPIO port to be used as source - * for Event output. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). - * GPIO_PinSource - specifies the pin for the Event output. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * - * @return none - */ -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmpreg = 0x00; - - tmpreg = AFIO->ECR; - tmpreg &= ECR_PORTPINCONFIG_MASK; - tmpreg |= (uint32_t)GPIO_PortSource << 0x04; - tmpreg |= GPIO_PinSource; - AFIO->ECR = tmpreg; -} - -/********************************************************************* - * @fn GPIO_EventOutputCmd - * - * @brief Enables or disables the Event Output. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void GPIO_EventOutputCmd(FunctionalState NewState) -{ - if(NewState) - { - AFIO->ECR |= (1 << 7); - } - else - { - AFIO->ECR &= ~(1 << 7); - } -} - -/********************************************************************* - * @fn GPIO_PinRemapConfig - * - * @brief Changes the mapping of the specified pin. - * - * @param GPIO_Remap - selects the pin to remap. - * GPIO_PartialRemap1_SPI1 - SPI1 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_SPI1 - SPI1 Partial2 Alternate Function mapping - * GPIO_FullRemap_SPI1 - SPI1 Full Alternate Function mapping - * GPIO_PartialRemap1_I2C1 - I2C1 Partial1 Alternate Function mapping - * GPIO_FullRemap_I2C1 - I2C1 Full Alternate Function mapping - * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping - * GPIO_PartialRemap3_USART1 - USART1 Partial3 Alternate Function mapping - * GPIO_PartialRemap4_USART1 - USART1 Partial4 Alternate Function mapping - * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping - * GPIO_PartialRemap1_USART2 - USART2 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_USART2 - USART2 Partial2 Alternate Function mapping - * GPIO_FullRemap_USART2 - USART2 Full Alternate Function mapping - * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping - * GPIO_PartialRemap3_TIM1 - TIM1 Partial3 Alternate Function mapping - * GPIO_PartialRemap4_TIM1 - TIM1 Partial4 Alternate Function mapping - * GPIO_PartialRemap5_TIM1 - TIM1 Partial5 Alternate Function mapping - * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping - * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping - * GPIO_PartialRemap3_TIM2 - TIM2 Partial3 Alternate Function mapping - * GPIO_PartialRemap4_TIM2 - TIM2 Partial4 Alternate Function mapping - * GPIO_PartialRemap5_TIM2 - TIM2 Partial5 Alternate Function mapping - * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping - * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping - * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping - * GPIO_Remap_TIM3 - TIM3 Alternate Function mapping - * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping - * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping - * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping - * GPIO_Remap_PD01 - PD01 Alternate Function mapping - * GPIO_Remap_SWJ_Disable - Full SDI Disabled (SDI) - * GPIO_Remap_USART4 - USART4 Alternate Function mapping - * GPIO_Remap_LPTIM - LPTIM Alternate Function mapping - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) -{ - uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg1 = 0x00, tmpreg2 = 0x00, tmpmask = 0x00; - - if((GPIO_Remap & 0xC0000000) == 0xC0000000) /* PCFR1 + PCFR2 */ - { - tmpreg1 = AFIO->PCFR1; - tmpreg2 = AFIO->PCFR2; - - /* Clear bit */ - tmp1 = ((GPIO_Remap & REMAP_NUM_MASK) >> 27); - - if(tmp1 == 0) - { - tmpreg1 &= ~(1<<0); - tmpreg2 &= ~(1<<24); - } - else if(tmp1 == 1) - { - tmpreg1 &= ~(1<<1); - tmpreg2 &= ~(1<<23); - } - else if(tmp1 == 2) - { - tmpreg1 &= ~(1<<2); - tmpreg2 &= ~(3<<19); - } - else if(tmp1 == 3) - { - tmpreg1 &= ~(1<<3); - tmpreg2 &= ~(1<<18); - } - else if(tmp1 == 4) - { - tmpreg1 &= ~(3<<6); - tmpreg2 &= ~(1<<22); - } - else if(tmp1 == 5) - { - tmpreg1 &= ~(3<<8); - tmpreg2 &= ~(1<<21); - } - - /* Set bit */ - if(NewState != DISABLE) - { - tmpreg1 |= (GPIO_Remap & 0x0000FFFF); - tmpreg2 |= (GPIO_Remap & 0x01FF0000); - } - - tmpreg1 |= ~DBGAFR_SWJCFG_MASK; - - AFIO->PCFR1 = tmpreg1; - AFIO->PCFR2 = tmpreg2; - } - else if((GPIO_Remap & 0xC0000000) == 0x40000000) /* PCFR2 */ - { - tmpreg2 = AFIO->PCFR2; - - /* Clear bit */ - tmp1 = ((GPIO_Remap & (~REMAP_MASK)) << 0x10); - tmpreg2 &= ~tmp1; - - /* Set bit */ - if(NewState != DISABLE) - { - tmpreg2 |= tmp1; - } - - AFIO->PCFR2 = tmpreg2; - } - else if((GPIO_Remap & 0xC0000000) == 0x00000000) /* PCFR1 */ - { - tmpreg1 = AFIO->PCFR1; - - /* Clear bit */ - tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - tmp = GPIO_Remap & LSB_MASK; - - if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SW_CFG */ - { - tmpreg1 &= DBGAFR_SWJCFG_MASK; - AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; - } - else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg1 &= ~tmp1; - tmpreg1 |= ~DBGAFR_SWJCFG_MASK; - } - else /* [31:0] 1bit */ - { - tmpreg1 &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); - tmpreg1 |= ~DBGAFR_SWJCFG_MASK; - } - - /* Set bit */ - if(NewState != DISABLE) - { - tmpreg1 |= (tmp << (((GPIO_Remap & 0x7FFFFFFF )>> 0x15) * 0x10)); - } - - AFIO->PCFR1 = tmpreg1; - } -} - -/********************************************************************* - * @fn GPIO_EXTILineConfig - * - * @brief Selects the GPIO pin used as EXTI Line. - * - * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). - * GPIO_PinSource - specifies the EXTI line to be configured. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * - * @return none - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmp = 0x00; - - tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); - AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; - AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); -} - -/********************************************************************* - * @fn GPIO_IPD_Unused - * - * @brief Configure unused GPIO as input pull-down. - * - * @param none - * - * @return none - */ -void GPIO_IPD_Unused(void) -{ - GPIO_InitTypeDef GPIO_InitStructure = {0}; - uint32_t chip = 0; - - OPA_Trim = (((*(uint32_t *)OPA_TRIM_BASE & 0x0000001F) << 25) | (((*(uint32_t *)OPA_TRIM_BASE & 0x00008000)^0x00008000) << 9)) \ - | (((*(uint32_t *)OPA_TRIM_BASE & 0x001F0000) << 1) | (((*(uint32_t *)OPA_TRIM_BASE & 0x80000000)^0x80000000) >> 15)); - ADC_Trim = (*(uint16_t *)ADC_TRIM_BASE); - TS_Val = (*(uint32_t *)TS_BASE); - CHIPID = (*(uint32_t *)CHIPID_BASE); - - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_GPIOB | RCC_PB2Periph_GPIOC |RCC_PB2Periph_GPIOD |RCC_PB2Periph_AFIO,ENABLE); - chip = *( uint32_t * )CHIPID_BASE & (~0x000000F0); - switch(chip) - { - case 0x10320700: //CH32L103K8U6 - { - GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_10\ - |GPIO_Pin_11|GPIO_Pin_12\ - |GPIO_Pin_13|GPIO_Pin_14\ - |GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOD, &GPIO_InitStructure); - break; - } - case 0x103D0700: //CH32L103F8U6 - { - GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ - |GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_8|GPIO_Pin_9\ - |GPIO_Pin_12; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ - |GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOD, &GPIO_InitStructure); - break; - } - case 0x10370700: //CH32L103F7P6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\ - |GPIO_Pin_10|GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_4\ - |GPIO_Pin_5|GPIO_Pin_9\ - |GPIO_Pin_10|GPIO_Pin_11\ - |GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14\ - |GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ - |GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOC, &GPIO_InitStructure); - break; - } - case 0x103B0700: //CH32L103G8R6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ - |GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOD, &GPIO_InitStructure); - break; - } - case 0x103A0700: //CH32L103F8P6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_4\ - |GPIO_Pin_5|GPIO_Pin_6\ - |GPIO_Pin_7 |GPIO_Pin_8\ - |GPIO_Pin_9|GPIO_Pin_10\ - |GPIO_Pin_11|GPIO_Pin_12; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ - |GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOD, &GPIO_InitStructure); - break; - } - case 0x10310700: //CH32L103C8T6 - { - break; - } - case 0x10300700: //CH32L103C8U6 - { - break; - } - default: - { - break; - } - - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_gpio.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/06 + * Description : This file provides all the GPIO firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_gpio.h" +#include "ch32l103_rcc.h" + +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) +#define REMAP_MASK ((uint32_t)0xC0000000) +#define REMAP_NUM_MASK ((uint32_t)0x38000000) + +uint32_t OPA_Trim = 0; +uint16_t ADC_Trim = 0; +uint32_t TS_Val = 0; +uint32_t CHIPID = 0; +uint16_t USBPD_CFG = 0; +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOA, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOB, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOC, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOD, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOD, DISABLE); + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_PB2PeriphResetCmd(RCC_PB2Periph_AFIO, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } + + if(GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CFGHR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CFGHR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return The output port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + uint16_t val; + + val = ( uint16_t )GPIOx->INDR; + + return ( val ); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + uint16_t val; + + val = ( uint16_t )GPIOx->OUTDR; + + return ( val ); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BSHR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * BitVal - specifies the value to be written to the selected bit. + * Bit_RESET - to clear the port pin. + * Bit_SET - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = GPIO_Pin; + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_EventOutputConfig + * + * @brief Selects the GPIO pin used as Event output. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * GPIO_PinSource - specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + + tmpreg = AFIO->ECR; + tmpreg &= ECR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->ECR = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EventOutputCmd + * + * @brief Enables or disables the Event Output. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + if(NewState) + { + AFIO->ECR |= (1 << 7); + } + else + { + AFIO->ECR &= ~(1 << 7); + } +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_PartialRemap1_SPI1 - SPI1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_SPI1 - SPI1 Partial2 Alternate Function mapping + * GPIO_FullRemap_SPI1 - SPI1 Full Alternate Function mapping + * GPIO_PartialRemap1_I2C1 - I2C1 Partial1 Alternate Function mapping + * GPIO_FullRemap_I2C1 - I2C1 Full Alternate Function mapping + * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_USART1 - USART1 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_USART1 - USART1 Partial4 Alternate Function mapping + * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping + * GPIO_PartialRemap1_USART2 - USART2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART2 - USART2 Partial2 Alternate Function mapping + * GPIO_FullRemap_USART2 - USART2 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_TIM1 - TIM1 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_TIM1 - TIM1 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_TIM1 - TIM1 Partial5 Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_TIM2 - TIM2 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_TIM2 - TIM2 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_TIM2 - TIM2 Partial5 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping + * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping + * GPIO_Remap_TIM3 - TIM3 Alternate Function mapping + * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping + * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap_PD01 - PD01 Alternate Function mapping + * GPIO_Remap_SWJ_Disable - Full SDI Disabled (SDI) + * GPIO_Remap_USART4 - USART4 Alternate Function mapping + * GPIO_Remap_LPTIM - LPTIM Alternate Function mapping + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg1 = 0x00, tmpreg2 = 0x00, tmpmask = 0x00; + + if((GPIO_Remap & 0xC0000000) == 0xC0000000) /* PCFR1 + PCFR2 */ + { + tmpreg1 = AFIO->PCFR1; + tmpreg2 = AFIO->PCFR2; + + /* Clear bit */ + tmp1 = ((GPIO_Remap & REMAP_NUM_MASK) >> 27); + + if(tmp1 == 0) + { + tmpreg1 &= ~(1<<0); + tmpreg2 &= ~(1<<24); + } + else if(tmp1 == 1) + { + tmpreg1 &= ~(1<<1); + tmpreg2 &= ~(1<<23); + } + else if(tmp1 == 2) + { + tmpreg1 &= ~(1<<2); + tmpreg2 &= ~(3<<19); + } + else if(tmp1 == 3) + { + tmpreg1 &= ~(1<<3); + tmpreg2 &= ~(1<<18); + } + else if(tmp1 == 4) + { + tmpreg1 &= ~(3<<6); + tmpreg2 &= ~(1<<22); + } + else if(tmp1 == 5) + { + tmpreg1 &= ~(3<<8); + tmpreg2 &= ~(1<<21); + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg1 |= (GPIO_Remap & 0x0000FFFF); + tmpreg2 |= (GPIO_Remap & 0x01FF0000); + } + + tmpreg1 |= ~DBGAFR_SWJCFG_MASK; + + AFIO->PCFR1 = tmpreg1; + AFIO->PCFR2 = tmpreg2; + } + else if((GPIO_Remap & 0xC0000000) == 0x40000000) /* PCFR2 */ + { + tmpreg2 = AFIO->PCFR2; + + /* Clear bit */ + tmp1 = ((GPIO_Remap & (~REMAP_MASK)) << 0x10); + tmpreg2 &= ~tmp1; + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg2 |= tmp1; + } + + AFIO->PCFR2 = tmpreg2; + } + else if((GPIO_Remap & 0xC0000000) == 0x00000000) /* PCFR1 */ + { + tmpreg1 = AFIO->PCFR1; + + /* Clear bit */ + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SW_CFG */ + { + tmpreg1 &= DBGAFR_SWJCFG_MASK; + AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg1 &= ~tmp1; + tmpreg1 |= ~DBGAFR_SWJCFG_MASK; + } + else /* [31:0] 1bit */ + { + tmpreg1 &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + tmpreg1 |= ~DBGAFR_SWJCFG_MASK; + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg1 |= (tmp << (((GPIO_Remap & 0x7FFFFFFF )>> 0x15) * 0x10)); + } + + AFIO->PCFR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-down. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + + OPA_Trim = (((*(uint32_t *)OPA_TRIM_BASE & 0x0000001F) << 25) | (((*(uint32_t *)OPA_TRIM_BASE & 0x00008000)^0x00008000) << 9)) \ + | (((*(uint32_t *)OPA_TRIM_BASE & 0x001F0000) << 1) | (((*(uint32_t *)OPA_TRIM_BASE & 0x80000000)^0x80000000) >> 15)); + ADC_Trim = (*(uint16_t *)ADC_TRIM_BASE); + TS_Val = (*(uint32_t *)TS_BASE); + CHIPID = (*(uint32_t *)CHIPID_BASE); + USBPD_CFG = (*(uint16_t *)USBPD_CFG_BASE); + + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_GPIOB | RCC_PB2Periph_GPIOC |RCC_PB2Periph_GPIOD |RCC_PB2Periph_AFIO,ENABLE); + chip = *( uint32_t * )CHIPID_BASE & (~0x000000F0); + switch(chip) + { + case 0x10320700: //CH32L103K8U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x103D0700: //CH32L103F8U6 + { + GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x103B0700: //CH32L103G8R6 + { + GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4|GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x103A0700: //CH32L103F8P6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x10310700: //CH32L103C8T6 + { + break; + } + default: + { + break; + } + + } +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_i2c.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_i2c.c index 238badd..f573d7b 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_i2c.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_i2c.c @@ -1,1013 +1,1013 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_i2c.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/19 - * Description : This file provides all the I2C firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_i2c.h" -#include "ch32l103_rcc.h" - -/* I2C SPE mask */ -#define CTLR1_PE_Set ((uint16_t)0x0001) -#define CTLR1_PE_Reset ((uint16_t)0xFFFE) - -/* I2C START mask */ -#define CTLR1_START_Set ((uint16_t)0x0100) -#define CTLR1_START_Reset ((uint16_t)0xFEFF) - -/* I2C STOP mask */ -#define CTLR1_STOP_Set ((uint16_t)0x0200) -#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) - -/* I2C ACK mask */ -#define CTLR1_ACK_Set ((uint16_t)0x0400) -#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) - -/* I2C ENGC mask */ -#define CTLR1_ENGC_Set ((uint16_t)0x0040) -#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) - -/* I2C SWRST mask */ -#define CTLR1_SWRST_Set ((uint16_t)0x8000) -#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) - -/* I2C PEC mask */ -#define CTLR1_PEC_Set ((uint16_t)0x1000) -#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) - -/* I2C ENPEC mask */ -#define CTLR1_ENPEC_Set ((uint16_t)0x0020) -#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) - -/* I2C ENARP mask */ -#define CTLR1_ENARP_Set ((uint16_t)0x0010) -#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) - -/* I2C NOSTRETCH mask */ -#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) -#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) - -/* I2C registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) - -/* I2C DMAEN mask */ -#define CTLR2_DMAEN_Set ((uint16_t)0x0800) -#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) - -/* I2C LAST mask */ -#define CTLR2_LAST_Set ((uint16_t)0x1000) -#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) - -/* I2C FREQ mask */ -#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) - -/* I2C ADD0 mask */ -#define OADDR1_ADD0_Set ((uint16_t)0x0001) -#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) - -/* I2C ENDUAL mask */ -#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) -#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) - -/* I2C ADD2 mask */ -#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) - -/* I2C F/S mask */ -#define CKCFGR_FS_Set ((uint16_t)0x8000) - -/* I2C CCR mask */ -#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) - -/* I2C FLAG mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) - -/* I2C Interrupt Enable mask */ -#define ITEN_Mask ((uint32_t)0x07000000) - -/********************************************************************* - * @fn I2C_DeInit - * - * @brief Deinitializes the I2Cx peripheral registers to their default - * reset values. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return none - */ -void I2C_DeInit(I2C_TypeDef *I2Cx) -{ - if(I2Cx == I2C1) - { - RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C1, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C1, DISABLE); - } - else - { - RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C2, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C2, DISABLE); - } -} - -/********************************************************************* - * @fn I2C_Init - * - * @brief Initializes the I2Cx peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified I2C peripheral. - * - * @return none - */ -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) -{ - uint16_t tmpreg = 0, freqrange = 0; - uint16_t result = 0x04; - uint32_t pclk1 = 8000000; - - RCC_ClocksTypeDef rcc_clocks; - - tmpreg = I2Cx->CTLR2; - tmpreg &= CTLR2_FREQ_Reset; - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - freqrange = (uint16_t)(pclk1 / 1000000); - if(freqrange > 60){ - freqrange =60; - } - tmpreg |= freqrange; - I2Cx->CTLR2 = tmpreg; - - I2Cx->CTLR1 &= CTLR1_PE_Reset; - tmpreg = 0; - - if(I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - - if(result < 0x04) - { - result = 0x04; - } - - tmpreg |= result; - I2Cx->RTR = freqrange + 1; - } - else - { - if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - result |= I2C_DutyCycle_16_9; - } - - if((result & CKCFGR_CCR_Set) == 0) - { - result |= (uint16_t)0x0001; - } - - tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); - I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - I2Cx->CKCFGR = tmpreg; - I2Cx->CTLR1 |= CTLR1_PE_Set; - - tmpreg = I2Cx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - I2Cx->CTLR1 = tmpreg; - - I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/********************************************************************* - * @fn I2C_StructInit - * - * @brief Fills each I2C_InitStruct member with its default value. - * - * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) -{ - I2C_InitStruct->I2C_ClockSpeed = 5000; - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStruct->I2C_OwnAddress1 = 0; - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/********************************************************************* - * @fn I2C_Cmd - * - * @brief Enables or disables the specified I2C peripheral. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PE_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PE_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMACmd - * - * @brief Enables or disables the specified I2C DMA requests. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_DMAEN_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMALastTransferCmd - * - * @brief Specifies if the next DMA transfer will be the last one. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_LAST_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_LAST_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTART - * - * @brief Generates I2Cx communication START condition. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_START_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_START_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTOP - * - * @brief Generates I2Cx communication STOP condition. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_STOP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_STOP_Reset; - } -} - -/********************************************************************* - * @fn I2C_AcknowledgeConfig - * - * @brief Enables or disables the specified I2C acknowledge feature. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ACK_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ACK_Reset; - } -} - -/********************************************************************* - * @fn I2C_OwnAddress2Config - * - * @brief Configures the specified I2C own address2. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * Address - specifies the 7bit I2C own address2. - * - * @return none - */ -void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - tmpreg = I2Cx->OADDR2; - tmpreg &= OADDR2_ADD2_Reset; - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - I2Cx->OADDR2 = tmpreg; -} - -/********************************************************************* - * @fn I2C_DualAddressCmd - * - * @brief Enables or disables the specified I2C dual addressing mode. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; - } - else - { - I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; - } -} - -/********************************************************************* - * @fn I2C_GeneralCallCmd - * - * @brief Enables or disables the specified I2C general call feature. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENGC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENGC_Reset; - } -} - -/********************************************************************* - * @fn I2C_ITConfig - * - * @brief Enables or disables the specified I2C interrupts. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. - * I2C_IT_BUF - Buffer interrupt mask. - * I2C_IT_EVT - Event interrupt mask. - * I2C_IT_ERR - Error interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= I2C_IT; - } - else - { - I2Cx->CTLR2 &= (uint16_t)~I2C_IT; - } -} - -/********************************************************************* - * @fn I2C_SendData - * - * @brief Sends a data byte through the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * Data - Byte to be transmitted. - * - * @return none - */ -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) -{ - I2Cx->DATAR = Data; -} - -/********************************************************************* - * @fn I2C_ReceiveData - * - * @brief Returns the most recent received data by the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) -{ - return (uint8_t)I2Cx->DATAR; -} - -/********************************************************************* - * @fn I2C_Send7bitAddress - * - * @brief Transmits the address byte to select the slave device. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * Address - specifies the slave address which will be transmitted. - * I2C_Direction - specifies whether the I2C device will be a - * Transmitter or a Receiver. - * I2C_Direction_Transmitter - Transmitter mode. - * I2C_Direction_Receiver - Receiver mode. - * - * @return none - */ -void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - if(I2C_Direction != I2C_Direction_Transmitter) - { - Address |= OADDR1_ADD0_Set; - } - else - { - Address &= OADDR1_ADD0_Reset; - } - - I2Cx->DATAR = Address; -} - -/********************************************************************* - * @fn I2C_ReadRegister - * - * @brief Reads the specified I2C register and returns its value. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_Register - specifies the register to read. - * I2C_Register_CTLR1. - * I2C_Register_CTLR2. - * I2C_Register_OADDR1. - * I2C_Register_OADDR2. - * I2C_Register_DATAR. - * I2C_Register_STAR1. - * I2C_Register_STAR2. - * I2C_Register_CKCFGR. - * I2C_Register_RTR. - * - * @return none - */ -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)I2Cx; - tmp += I2C_Register; - - return (*(__IO uint16_t *)tmp); -} - -/********************************************************************* - * @fn I2C_SoftwareResetCmd - * - * @brief Enables or disables the specified I2C software reset. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_SWRST_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_SWRST_Reset; - } -} - -/********************************************************************* - * @fn I2C_NACKPositionConfig - * - * @brief Selects the specified I2C NACK position in master receiver mode. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_NACKPosition - specifies the NACK position. - * I2C_NACKPosition_Next - indicates that the next byte will be - * the last received byte. - * I2C_NACKPosition_Current - indicates that current byte is the - * last received byte. - * Note- - * This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * - * @return none - */ -void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) -{ - if(I2C_NACKPosition == I2C_NACKPosition_Next) - { - I2Cx->CTLR1 |= I2C_NACKPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_NACKPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_SMBusAlertConfig - * - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_SMBusAlert - specifies SMBAlert pin level. - * I2C_SMBusAlert_Low - SMBAlert pin driven low. - * I2C_SMBusAlert_High - SMBAlert pin driven high. - * - * @return none - */ -void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert) -{ - if(I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - I2Cx->CTLR1 |= I2C_SMBusAlert_Low; - } - else - { - I2Cx->CTLR1 &= I2C_SMBusAlert_High; - } -} - -/********************************************************************* - * @fn I2C_TransmitPEC - * - * @brief Enables or disables the specified I2C PEC transfer. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_PECPositionConfig - * - * @brief Selects the specified I2C PEC position. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_PECPosition - specifies the PEC position. - * I2C_PECPosition_Next - indicates that the next byte is PEC. - * I2C_PECPosition_Current - indicates that current byte is PEC. - * - * @return none - */ -void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) -{ - if(I2C_PECPosition == I2C_PECPosition_Next) - { - I2Cx->CTLR1 |= I2C_PECPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_PECPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_CalculatePEC - * - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * - * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENPEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_GetPEC - * - * @brief Returns the PEC value for the specified I2C. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) -{ - return ((I2Cx->STAR2) >> 8); -} - -/********************************************************************* - * @fn I2C_ARPCmd - * - * @brief Enables or disables the specified I2C ARP. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return The PEC value. - */ -void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENARP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENARP_Reset; - } -} - -/********************************************************************* - * @fn I2C_StretchClockCmd - * - * @brief Enables or disables the specified I2C Clock stretching. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState == DISABLE) - { - I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; - } -} - -/********************************************************************* - * @fn I2C_FastModeDutyCycleConfig - * - * @brief Selects the specified I2C fast mode duty cycle. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_DutyCycle - specifies the fast mode duty cycle. - * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. - * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. - * - * @return none - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) -{ - if(I2C_DutyCycle != I2C_DutyCycle_16_9) - { - I2Cx->CKCFGR &= I2C_DutyCycle_2; - } - else - { - I2Cx->CKCFGR |= I2C_DutyCycle_16_9; - } -} - -/********************************************************************* - * @fn I2C_CheckEvent - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. - * I2C_EVENT: specifies the event to be checked. - * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. - * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. - * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. - * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. - * I2C_EVENT_MASTER_MODE_SELECT - EVT5. - * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. - * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. - * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. - * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. - * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. - * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. - * - * @return ErrorStatus - READY or NoREADY. - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = NoREADY; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - - lastevent = (flag1 | flag2) & FLAG_Mask; - - if((lastevent & I2C_EVENT) == I2C_EVENT) - { - status = READY; - } - else - { - status = NoREADY; - } - - return status; -} - -/********************************************************************* - * @fn I2C_GetLastEvent - * - * @brief Returns the last I2Cx Event. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return none - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - lastevent = (flag1 | flag2) & FLAG_Mask; - - return lastevent; -} - -/********************************************************************* - * @fn I2C_GetFlagStatus - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to check. - * I2C_FLAG_DUALF - Dual flag (Slave mode). - * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). - * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). - * I2C_FLAG_GENCALL - General call header flag (Slave mode). - * I2C_FLAG_TRA - Transmitter/Receiver flag. - * I2C_FLAG_BUSY - Bus busy flag. - * I2C_FLAG_MSL - Master/Slave flag. - * I2C_FLAG_SMBALERT - SMBus Alert flag. - * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * I2C_FLAG_TXE - Data register empty flag (Transmitter). - * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. - * I2C_FLAG_STOPF - Stop detection flag (Slave mode). - * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). - * I2C_FLAG_BTF - Byte transfer finished flag. - * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDA". - * I2C_FLAG_SB - Start bit flag (Master mode). - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - i2cxbase = (uint32_t)I2Cx; - i2creg = I2C_FLAG >> 28; - I2C_FLAG &= FLAG_Mask; - - if(i2creg != 0) - { - i2cxbase += 0x14; - } - else - { - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearFlag - * - * @brief Clears the I2Cx's pending flags. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to clear. - * I2C_FLAG_SMBALERT - SMBus Alert flag. - * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * Note- - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DATAR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DATAR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SATR2 register ((void)(I2Cx->STAR2)). - * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR - * register (I2C_SendData()). - * - * @return none - */ -void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - - flagpos = I2C_FLAG & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} - -/********************************************************************* - * @fn I2C_GetITStatus - * - * @brief Checks whether the specified I2C interrupt has occurred or not. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * II2C_IT - specifies the interrupt source to check. - * I2C_IT_SMBALERT - SMBus Alert flag. - * I2C_IT_TIMEOUT - Timeout or Tlow error flag. - * I2C_IT_PECERR - PEC error in reception flag. - * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). - * I2C_IT_AF - Acknowledge failure flag. - * I2C_IT_ARLO - Arbitration lost flag (Master mode). - * I2C_IT_BERR - Bus error flag. - * I2C_IT_TXE - Data register empty flag (Transmitter). - * I2C_IT_RXNE - Data register not empty (Receiver) flag. - * I2C_IT_STOPF - Stop detection flag (Slave mode). - * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). - * I2C_IT_BTF - Byte transfer finished flag. - * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched - * flag (Slave mode)"ENDAD". - * I2C_IT_SB - Start bit flag (Master mode). - * - * @return none - */ -ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); - I2C_IT &= FLAG_Mask; - - if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearITPendingBit - * - * @brief Clears the I2Cx interrupt pending bits. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_IT - specifies the interrupt pending bit to clear. - * I2C_IT_SMBALERT - SMBus Alert interrupt. - * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. - * I2C_IT_PECERR - PEC error in reception interrupt. - * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). - * I2C_IT_AF - Acknowledge failure interrupt. - * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). - * I2C_IT_BERR - Bus error interrupt. - * Note- - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DATAR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DATAR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_STAR2 register ((void)(I2Cx->STAR2)). - * - SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DATAR register (I2C_SendData()). - * - * @return none - */ -void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - - flagpos = I2C_IT & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_i2c.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/19 + * Description : This file provides all the I2C firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_i2c.h" +#include "ch32l103_rcc.h" + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C1, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C1, DISABLE); + } + else + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C2, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C2, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + if(freqrange > 60){ + freqrange =60; + } + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + I2Cx->RTR = freqrange + 1; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * I2C_Register_RTR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * Note- + * This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_SMBusAlertConfig + * + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_SMBusAlert - specifies SMBAlert pin level. + * I2C_SMBusAlert_Low - SMBAlert pin driven low. + * I2C_SMBusAlert_High - SMBAlert pin driven high. + * + * @return none + */ +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert) +{ + if(I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + I2Cx->CTLR1 |= I2C_SMBusAlert_Low; + } + else + { + I2Cx->CTLR1 &= I2C_SMBusAlert_High; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. + * I2C_EVENT_MASTER_MODE_SELECT - EVT5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. + * + * @return ErrorStatus - READY or NoREADY. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = NoREADY; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = READY; + } + else + { + status = NoREADY; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). + * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SATR2 register ((void)(I2Cx->STAR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR + * register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_SMBALERT - SMBus Alert flag. + * I2C_IT_TIMEOUT - Timeout or Tlow error flag. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_SMBALERT - SMBus Alert interrupt. + * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_STAR2 register ((void)(I2Cx->STAR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DATAR register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_iwdg.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_iwdg.c index 83e4353..2948998 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_iwdg.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_iwdg.c @@ -1,124 +1,123 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_iwdg.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/12/26 - * Description : This file provides all the IWDG firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_iwdg.h" - -/* CTLR register bit mask */ -#define CTLR_KEY_Reload ((uint16_t)0xAAAA) -#define CTLR_KEY_Enable ((uint16_t)0xCCCC) - -/********************************************************************* - * @fn IWDG_WriteAccessCmd - * - * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. - * - * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR - * and IWDG_RLDR registers. - * - * @return none - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - IWDG->CTLR = IWDG_WriteAccess; -} - -/********************************************************************* - * @fn IWDG_SetPrescaler - * - * @brief Sets IWDG Prescaler value. - * - * @param IWDG_Prescaler - specifies the IWDG Prescaler value. - * IWDG_Prescaler_4 - IWDG prescaler set to 4. - * IWDG_Prescaler_8 - IWDG prescaler set to 8. - * IWDG_Prescaler_16 - IWDG prescaler set to 16. - * IWDG_Prescaler_32 - IWDG prescaler set to 32. - * IWDG_Prescaler_64 - IWDG prescaler set to 64. - * IWDG_Prescaler_128 - IWDG prescaler set to 128. - * IWDG_Prescaler_256 - IWDG prescaler set to 256. - * - * @return none - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - IWDG->PSCR = IWDG_Prescaler; -} - -/********************************************************************* - * @fn IWDG_SetReload - * - * @brief Sets IWDG Reload value. - * - * @param Reload - specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * - * @return none - */ -void IWDG_SetReload(uint16_t Reload) -{ - IWDG->RLDR = Reload; -} - -/********************************************************************* - * @fn IWDG_ReloadCounter - * - * @brief Reloads IWDG counter with value defined in the reload register. - * - * @return none - */ -void IWDG_ReloadCounter(void) -{ - IWDG->CTLR = CTLR_KEY_Reload; -} - -/********************************************************************* - * @fn IWDG_Enable - * - * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). - * - * @return none - */ -void IWDG_Enable(void) -{ - IWDG->CTLR = CTLR_KEY_Enable; - while(RCC->RSTSCKR | 0x02 != SET) - ; -} - -/********************************************************************* - * @fn IWDG_GetFlagStatus - * - * @brief Checks whether the specified IWDG flag is set or not. - * - * @param IWDG_FLAG - specifies the flag to check. - * IWDG_FLAG_PVU - Prescaler Value Update on going. - * IWDG_FLAG_RVU - Reload Value Update on going. - * - * @return none - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_iwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/03/26 + * Description : This file provides all the IWDG firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_iwdg.h" + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; + while((RCC->RSTSCKR & 0x2) == RESET); +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_lptim.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_lptim.c index ac7ae7e..7231aa0 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_lptim.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_lptim.c @@ -1,364 +1,363 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_lptim.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the TIM firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_lptim.h" -#include "ch32l103_rcc.h" - - -/********************************************************************* - * @fn LPTIM_DeInit - * - * @brief Deinitializes the LPTIM peripheral registers to their default - * reset values. - * - * @param none - * - * @return none - */ -void LPTIM_DeInit(void) -{ - RCC_PB1PeriphResetCmd(RCC_PB1Periph_LPTIM, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_LPTIM, DISABLE); -} - -/********************************************************************* - * @fn LPTIM_TimeBaseInit - * - * @brief Initializes the LPTIM Time Base Unit peripheral according to - * the specified parameters in the LPTIM_TimeBaseInitStruct. - * - * @param LPTIM_TimeBaseInitStruct - pointer to a LPTIM_TimeBaseInitTypeDef - * structure. - * - * @return none - */ -void LPTIM_TimeBaseInit(LPTIM_TimeBaseInitTypeDef *LPTIM_TimeBaseInitStruct) -{ - uint32_t temp1 = 0, temp2 = 0; - - temp2 = (LPTIM->CR & 0x00000001); - - if(LPTIM_TimeBaseInitStruct->LPTIM_Encoder == ENABLE) - { - temp1 |= LPTIM_TimeBaseInitStruct->LPTIM_EncoderMode; - } - else - { - temp1 |= LPTIM_TimeBaseInitStruct->LPTIM_ClockPolarity; - } - - temp1 |= LPTIM_TimeBaseInitStruct->LPTIM_ClockSource | LPTIM_TimeBaseInitStruct->LPTIM_ClockSampleTime \ - | LPTIM_TimeBaseInitStruct->LPTIM_TriggerSampleTime | LPTIM_TimeBaseInitStruct->LPTIM_ClockPrescaler \ - | LPTIM_TimeBaseInitStruct->LPTIM_TriggerSource | LPTIM_TimeBaseInitStruct->LPTIM_ExTriggerPolarity \ - | LPTIM_TimeBaseInitStruct->LPYIM_OutputPolarity | LPTIM_TimeBaseInitStruct->LPYIM_UpdateMode \ - | LPTIM_TimeBaseInitStruct->LPYIM_UpdateMode | LPTIM_TimeBaseInitStruct->LPTIM_CountSource \ - | LPTIM_TimeBaseInitStruct->LPTIM_InClockSource | LPTIM_TimeBaseInitStruct->LPTIM_CountSource \ - | (LPTIM_TimeBaseInitStruct->LPTIM_TimeOut << 19) | (LPTIM_TimeBaseInitStruct->LPTIM_OnePulseMode << 20) \ - | (LPTIM_TimeBaseInitStruct->LPTIM_Encoder << 24) | (LPTIM_TimeBaseInitStruct->LPTIM_ForceOutHigh << 27); - - temp2 |= (LPTIM_TimeBaseInitStruct->LPTIM_SingleMode << 1) | (LPTIM_TimeBaseInitStruct->LPTIM_ContinuousMode << 2) \ - | (LPTIM_TimeBaseInitStruct->LPTIM_PWMOut << 3) | (LPTIM_TimeBaseInitStruct->LPTIM_CounterDirIndicat << 4); - - LPTIM->CFGR = temp1; - LPTIM->CR = temp2; - LPTIM->CMP = LPTIM_TimeBaseInitStruct->LPTIM_Pulse; - LPTIM->ARR = LPTIM_TimeBaseInitStruct->LPTIM_Period; -} - -/********************************************************************* - * @fn LPTIM_TimeBaseStructInit - * - * @brief Fills each LPTIM_TimeBaseInitStruct member with its default value. - * - * @param TIM_TimeBaseInitStruct - pointer to a LPTIM_TimeBaseInitTypeDef structure. - * - * @return none - */ -void LPTIM_TimeBaseStructInit(LPTIM_TimeBaseInitTypeDef *LPTIM_TimeBaseInitStruct) -{ - LPTIM_TimeBaseInitStruct->LPTIM_ClockSource = LPTIM_ClockSource_In; - LPTIM_TimeBaseInitStruct->LPTIM_ClockPolarity = LPTIM_ClockPolarity_Rising; - LPTIM_TimeBaseInitStruct->LPTIM_ClockSampleTime = LPTIM_ClockSampleTime_0T; - LPTIM_TimeBaseInitStruct->LPTIM_TriggerSampleTime = LPTIM_TriggerSampleTime_0T; - LPTIM_TimeBaseInitStruct->LPTIM_ClockPrescaler = LPTIM_TClockPrescaler_DIV1; - LPTIM_TimeBaseInitStruct->LPTIM_TriggerSource = LPTIM_TriggerSource_ETR; - LPTIM_TimeBaseInitStruct->LPTIM_ExTriggerPolarity = LPTIM_ExTriggerPolarity_Disable; - LPTIM_TimeBaseInitStruct->LPTIM_TimeOut = DISABLE; - LPTIM_TimeBaseInitStruct->LPTIM_OnePulseMode = DISABLE; - LPTIM_TimeBaseInitStruct->LPYIM_OutputPolarity = LPYIM_OutputPolarity_High; - LPTIM_TimeBaseInitStruct->LPYIM_UpdateMode = LPYIM_UpdateMode0; - LPTIM_TimeBaseInitStruct->LPTIM_CountSource = LPTIM_CountSource_Internal; - LPTIM_TimeBaseInitStruct->LPTIM_Encoder = DISABLE; - LPTIM_TimeBaseInitStruct->LPTIM_InClockSource = LPTIM_InClockSource_PCLK1; - LPTIM_TimeBaseInitStruct->LPTIM_ForceOutHigh = DISABLE; - LPTIM_TimeBaseInitStruct->LPTIM_SingleMode = DISABLE; - LPTIM_TimeBaseInitStruct->LPTIM_ContinuousMode = DISABLE; - LPTIM_TimeBaseInitStruct->LPTIM_PWMOut = DISABLE; - LPTIM_TimeBaseInitStruct->LPTIM_CounterDirIndicat = DISABLE; - LPTIM_TimeBaseInitStruct->LPTIM_Pulse = 0; - LPTIM_TimeBaseInitStruct->LPTIM_Period = 0x0001; -} - -/********************************************************************* - * @fn LPTIM_CounterDirIndicat_Cmd - * - * @brief Enable or Disable counter direction indicate function. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void LPTIM_CounterDirIndicat_Cmd(FunctionalState NewState) -{ - if(NewState) - { - LPTIM->CR |= (1<<3); - } - else{ - LPTIM->CR &= ~(1<<3); - } -} - -/********************************************************************* - * @fn LPTIM_OutCmd - * - * @brief Enable or Disable PWM out function. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void LPTIM_OutCmd(FunctionalState NewState) -{ - if(NewState) - { - LPTIM->CR |= (1<<3); - } - else{ - LPTIM->CR &= ~(1<<3); - } -} - -/********************************************************************* - * @fn LPTIM_Cmd - * - * @brief Enable or Disable LPTIM. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void LPTIM_Cmd(FunctionalState NewState) -{ - if(NewState) - { - LPTIM->CR |= (1<<0); - } - else{ - LPTIM->CR &= ~(1<<0); - } -} - -/********************************************************************* - * @fn LPTIM_GetCounter - * - * @brief Gets the LPTIM Counter value. - * - * @param none - * - * @return LPTIM->CNT - Counter Register value. - */ -uint16_t LPTIM_GetCounter(void) -{ - return LPTIM->CNT; -} - -/********************************************************************* - * @fn LPTIM_SetAutoreload - * - * @brief Sets the LPTIM Autoreload Register value. - * - * @param Autoreload - specifies the Autoreload register new value. - * - * @return none - */ -void LPTIM_SetAutoreload(uint16_t Autoreload) -{ - LPTIM->ARR = Autoreload; -} - -/********************************************************************* - * @fn LPTIM_SetCompare - * - * @brief Sets the LPTIM Capture Compare Register value. - * - * @param Compare - specifies the Capture Compare1 register new value. - * - * @return none - */ -void LPTIM_SetCompare(uint16_t Compare) -{ - LPTIM->CMP = Compare; -} - -/********************************************************************* - * @fn LPTIM_GetCapture - * - * @brief Gets the LPTIM Input Capture value. - * - * @param none - * - * @return LPTIM->CMP - Capture Compare Register value. - */ -uint16_t LPTIM_GetCapture(void) -{ - return LPTIM->CMP; -} - -/********************************************************************* - * @fn LPTIM_ITConfig - * - * @brief Enables or disables the specified LPTIM interrupts. - * - * @param LPTIM_IT - specifies the LPTIM interrupts sources to be enabled or disabled. - * LPTIM_IT_DOWN - LPTIM counter down Interrupt source. - * LPTIM_IT_UP - LPTIM counter up Interrupt source. - * LPTIM_IT_ARROK - LPTIM be loaded success Interrupt source. - * LPTIM_IT_CMPOK - LPTIM Capture Compare success Interrupt source. - * LPTIM_IT_EXTTRIG - TIM Trigger Interrupt source. - * LPTIM_IT_ARRM - TIM counter Count to ARR register Interrupt source. - * LPTIM_IT_CMPM - TIM counter Count to CMP register Interrupt source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void LPTIM_ITConfig(uint32_t LPTIM_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - LPTIM->IER |= LPTIM_IT; - } - else - { - LPTIM->IER &= (uint32_t)~LPTIM_IT; - } -} - -/********************************************************************* - * @fn LPTIM_GetFlagStatus - * - * @brief Checks whether the specified LPTIM flag is set or not. - * - * @param LPTIM_FLAG - specifies the flag to check. - * LPTIM_FLAG_DIR_SYNC - LPTIM counter direction indicate Flag. - * LPTIM_FLAG_DOWN - LPTIM counter down Flag. - * LPTIM_FLAG_UP - LPTIM counter up Flag. - * LPTIM_FLAG_ARROK - LPTIM be loaded success Flag. - * LPTIM_FLAG_CMPOK - LPTIM Capture Compare success Flag. - * LPTIM_FLAG_EXTTRIG - TIM Trigger Flag. - * LPTIM_FLAG_ARRM - TIM counter Count to ARR register Flag. - * LPTIM_FLAG_CMPM - TIM counter Count to CMP register Flag. - * - * @return none - */ -FlagStatus LPTIM_GetFlagStatus(uint32_t LPTIM_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((LPTIM->ISR & LPTIM_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn LPTIM_ClearFlag - * - * @brief Clears the LPTIM's pending flags. - * - * @param LPTIM_FLAG - specifies the flag to check. - * LPTIM_FLAG_DOWN - LPTIM counter down Flag. - * LPTIM_FLAG_UP - LPTIM counter up Flag. - * LPTIM_FLAG_ARROK - LPTIM be loaded success Flag. - * LPTIM_FLAG_CMPOK - LPTIM Capture Compare success Flag. - * LPTIM_FLAG_EXTTRIG - TIM Trigger Flag. - * LPTIM_FLAG_ARRM - TIM counter Count to ARR register Flag. - * LPTIM_FLAG_CMPM - TIM counter Count to CMP register Flag. - * - * @return none - */ -void LPTIM_ClearFlag(uint32_t LPTIM_FLAG) -{ - LPTIM->ICR |= (uint32_t)LPTIM_FLAG; -} - -/********************************************************************* - * @fn LPTIM_GetITStatus - * - * @brief Checks whether the LPTIM interrupt has occurred or not. - * - * @param LPTIM_IT - specifies the LPTIM interrupt source to check. - * LPTIM_FLAG_DIR_SYNC - LPTIM counter direction indicate Interrupt source. - * LPTIM_IT_DOWN - LPTIM counter down Interrupt source. - * LPTIM_IT_UP - LPTIM counter up Interrupt source. - * LPTIM_IT_ARROK - LPTIM be loaded success Interrupt source. - * LPTIM_IT_CMPOK - LPTIM Capture Compare success Interrupt source. - * LPTIM_IT_EXTTRIG - TIM Trigger Interrupt source. - * LPTIM_IT_ARRM - TIM counter Count to ARR register Interrupt source. - * LPTIM_IT_CMPM - TIM counter Count to CMP register Interrupt source. - * - * @return none - */ -ITStatus LPTIM_GetITStatus(uint32_t LPTIM_IT) -{ - ITStatus bitstatus = RESET; - - if((LPTIM->ISR & LPTIM_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn LPTIM_ClearITPendingBit - * - * @brief Clears the LPTIM's interrupt pending bits. - * - * @param LPTIM_IT - specifies the LPTIM interrupt source to check. - * LPTIM_IT_DOWN - LPTIM counter down Interrupt source. - * LPTIM_IT_UP - LPTIM counter up Interrupt source. - * LPTIM_IT_ARROK - LPTIM be loaded success Interrupt source. - * LPTIM_IT_CMPOK - LPTIM Capture Compare success Interrupt source. - * LPTIM_IT_EXTTRIG - TIM Trigger Interrupt source. - * LPTIM_IT_ARRM - TIM counter Count to ARR register Interrupt source. - * LPTIM_IT_CMPM - TIM counter Count to CMP register Interrupt source. - * - * @return none - */ -void LPTIM_ClearITPendingBit(uint32_t LPTIM_IT) -{ - LPTIM->ICR |= (uint32_t)LPTIM_IT; -} - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_lptim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/08/29 + * Description : This file provides all the TIM firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_lptim.h" +#include "ch32l103_rcc.h" + + +/********************************************************************* + * @fn LPTIM_DeInit + * + * @brief Deinitializes the LPTIM peripheral registers to their default + * reset values. + * + * @param none + * + * @return none + */ +void LPTIM_DeInit(void) +{ + RCC_PB1PeriphResetCmd(RCC_PB1Periph_LPTIM, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_LPTIM, DISABLE); +} + +/********************************************************************* + * @fn LPTIM_TimeBaseInit + * + * @brief Initializes the LPTIM Time Base Unit peripheral according to + * the specified parameters in the LPTIM_TimeBaseInitStruct. + * + * @param LPTIM_TimeBaseInitStruct - pointer to a LPTIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void LPTIM_TimeBaseInit(LPTIM_TimeBaseInitTypeDef *LPTIM_TimeBaseInitStruct) +{ + uint32_t temp1 = 0, temp2 = 0; + + temp2 = (LPTIM->CR & 0x00000001); + + if(LPTIM_TimeBaseInitStruct->LPTIM_Encoder == ENABLE) + { + temp1 |= LPTIM_TimeBaseInitStruct->LPTIM_EncoderMode; + } + else + { + temp1 |= LPTIM_TimeBaseInitStruct->LPTIM_ClockPolarity; + } + + temp1 |= LPTIM_TimeBaseInitStruct->LPTIM_ClockSource | LPTIM_TimeBaseInitStruct->LPTIM_ClockSampleTime \ + | LPTIM_TimeBaseInitStruct->LPTIM_TriggerSampleTime | LPTIM_TimeBaseInitStruct->LPTIM_ClockPrescaler \ + | LPTIM_TimeBaseInitStruct->LPTIM_TriggerSource | LPTIM_TimeBaseInitStruct->LPTIM_ExTriggerPolarity \ + | LPTIM_TimeBaseInitStruct->LPTIM_OutputPolarity | LPTIM_TimeBaseInitStruct->LPTIM_UpdateMode \ + | LPTIM_TimeBaseInitStruct->LPTIM_CountSource | LPTIM_TimeBaseInitStruct->LPTIM_InClockSource \ + | (LPTIM_TimeBaseInitStruct->LPTIM_TimeOut << 19) | (LPTIM_TimeBaseInitStruct->LPTIM_OnePulseMode << 20) \ + | (LPTIM_TimeBaseInitStruct->LPTIM_Encoder << 24) | (LPTIM_TimeBaseInitStruct->LPTIM_ForceOutHigh << 27); + + temp2 |= (LPTIM_TimeBaseInitStruct->LPTIM_SingleMode << 1) | (LPTIM_TimeBaseInitStruct->LPTIM_ContinuousMode << 2) \ + | (LPTIM_TimeBaseInitStruct->LPTIM_PWMOut << 3) | (LPTIM_TimeBaseInitStruct->LPTIM_CounterDirIndicat << 4); + + LPTIM->CFGR = temp1; + LPTIM->CR = temp2; + LPTIM->CMP = LPTIM_TimeBaseInitStruct->LPTIM_Pulse; + LPTIM->ARR = LPTIM_TimeBaseInitStruct->LPTIM_Period; +} + +/********************************************************************* + * @fn LPTIM_TimeBaseStructInit + * + * @brief Fills each LPTIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a LPTIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void LPTIM_TimeBaseStructInit(LPTIM_TimeBaseInitTypeDef *LPTIM_TimeBaseInitStruct) +{ + LPTIM_TimeBaseInitStruct->LPTIM_ClockSource = LPTIM_ClockSource_In; + LPTIM_TimeBaseInitStruct->LPTIM_ClockPolarity = LPTIM_ClockPolarity_Rising; + LPTIM_TimeBaseInitStruct->LPTIM_ClockSampleTime = LPTIM_ClockSampleTime_0T; + LPTIM_TimeBaseInitStruct->LPTIM_TriggerSampleTime = LPTIM_TriggerSampleTime_0T; + LPTIM_TimeBaseInitStruct->LPTIM_ClockPrescaler = LPTIM_TClockPrescaler_DIV1; + LPTIM_TimeBaseInitStruct->LPTIM_TriggerSource = LPTIM_TriggerSource_ETR; + LPTIM_TimeBaseInitStruct->LPTIM_ExTriggerPolarity = LPTIM_ExTriggerPolarity_Disable; + LPTIM_TimeBaseInitStruct->LPTIM_TimeOut = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_OnePulseMode = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_OutputPolarity = LPTIM_OutputPolarity_High; + LPTIM_TimeBaseInitStruct->LPTIM_UpdateMode = LPTIM_UpdateMode0; + LPTIM_TimeBaseInitStruct->LPTIM_CountSource = LPTIM_CountSource_Internal; + LPTIM_TimeBaseInitStruct->LPTIM_Encoder = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_InClockSource = LPTIM_InClockSource_PCLK1; + LPTIM_TimeBaseInitStruct->LPTIM_ForceOutHigh = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_SingleMode = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_ContinuousMode = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_PWMOut = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_CounterDirIndicat = DISABLE; + LPTIM_TimeBaseInitStruct->LPTIM_Pulse = 0; + LPTIM_TimeBaseInitStruct->LPTIM_Period = 0x0001; +} + +/********************************************************************* + * @fn LPTIM_CounterDirIndicat_Cmd + * + * @brief Enable or Disable counter direction indicate function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void LPTIM_CounterDirIndicat_Cmd(FunctionalState NewState) +{ + if(NewState) + { + LPTIM->CR |= (1<<3); + } + else{ + LPTIM->CR &= ~(1<<3); + } +} + +/********************************************************************* + * @fn LPTIM_OutCmd + * + * @brief Enable or Disable PWM out function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void LPTIM_OutCmd(FunctionalState NewState) +{ + if(NewState) + { + LPTIM->CR |= (1<<3); + } + else{ + LPTIM->CR &= ~(1<<3); + } +} + +/********************************************************************* + * @fn LPTIM_Cmd + * + * @brief Enable or Disable LPTIM. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void LPTIM_Cmd(FunctionalState NewState) +{ + if(NewState) + { + LPTIM->CR |= (1<<0); + } + else{ + LPTIM->CR &= ~(1<<0); + } +} + +/********************************************************************* + * @fn LPTIM_GetCounter + * + * @brief Gets the LPTIM Counter value. + * + * @param none + * + * @return LPTIM->CNT - Counter Register value. + */ +uint16_t LPTIM_GetCounter(void) +{ + return LPTIM->CNT; +} + +/********************************************************************* + * @fn LPTIM_SetAutoreload + * + * @brief Sets the LPTIM Autoreload Register value. + * + * @param Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void LPTIM_SetAutoreload(uint16_t Autoreload) +{ + LPTIM->ARR = Autoreload; +} + +/********************************************************************* + * @fn LPTIM_SetCompare + * + * @brief Sets the LPTIM Capture Compare Register value. + * + * @param Compare - specifies the Capture Compare1 register new value. + * + * @return none + */ +void LPTIM_SetCompare(uint16_t Compare) +{ + LPTIM->CMP = Compare; +} + +/********************************************************************* + * @fn LPTIM_GetCapture + * + * @brief Gets the LPTIM Input Capture value. + * + * @param none + * + * @return LPTIM->CMP - Capture Compare Register value. + */ +uint16_t LPTIM_GetCapture(void) +{ + return LPTIM->CMP; +} + +/********************************************************************* + * @fn LPTIM_ITConfig + * + * @brief Enables or disables the specified LPTIM interrupts. + * + * @param LPTIM_IT - specifies the LPTIM interrupts sources to be enabled or disabled. + * LPTIM_IT_DOWN - LPTIM counter down Interrupt source. + * LPTIM_IT_UP - LPTIM counter up Interrupt source. + * LPTIM_IT_ARROK - LPTIM be loaded success Interrupt source. + * LPTIM_IT_CMPOK - LPTIM Capture Compare success Interrupt source. + * LPTIM_IT_EXTTRIG - TIM Trigger Interrupt source. + * LPTIM_IT_ARRM - TIM counter Count to ARR register Interrupt source. + * LPTIM_IT_CMPM - TIM counter Count to CMP register Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void LPTIM_ITConfig(uint32_t LPTIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + LPTIM->IER |= LPTIM_IT; + } + else + { + LPTIM->IER &= (uint32_t)~LPTIM_IT; + } +} + +/********************************************************************* + * @fn LPTIM_GetFlagStatus + * + * @brief Checks whether the specified LPTIM flag is set or not. + * + * @param LPTIM_FLAG - specifies the flag to check. + * LPTIM_FLAG_DIR_SYNC - LPTIM counter direction indicate Flag. + * LPTIM_FLAG_DOWN - LPTIM counter down Flag. + * LPTIM_FLAG_UP - LPTIM counter up Flag. + * LPTIM_FLAG_ARROK - LPTIM be loaded success Flag. + * LPTIM_FLAG_CMPOK - LPTIM Capture Compare success Flag. + * LPTIM_FLAG_EXTTRIG - TIM Trigger Flag. + * LPTIM_FLAG_ARRM - TIM counter Count to ARR register Flag. + * LPTIM_FLAG_CMPM - TIM counter Count to CMP register Flag. + * + * @return none + */ +FlagStatus LPTIM_GetFlagStatus(uint32_t LPTIM_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((LPTIM->ISR & LPTIM_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn LPTIM_ClearFlag + * + * @brief Clears the LPTIM's pending flags. + * + * @param LPTIM_FLAG - specifies the flag to check. + * LPTIM_FLAG_DOWN - LPTIM counter down Flag. + * LPTIM_FLAG_UP - LPTIM counter up Flag. + * LPTIM_FLAG_ARROK - LPTIM be loaded success Flag. + * LPTIM_FLAG_CMPOK - LPTIM Capture Compare success Flag. + * LPTIM_FLAG_EXTTRIG - TIM Trigger Flag. + * LPTIM_FLAG_ARRM - TIM counter Count to ARR register Flag. + * LPTIM_FLAG_CMPM - TIM counter Count to CMP register Flag. + * + * @return none + */ +void LPTIM_ClearFlag(uint32_t LPTIM_FLAG) +{ + LPTIM->ICR |= (uint32_t)LPTIM_FLAG; +} + +/********************************************************************* + * @fn LPTIM_GetITStatus + * + * @brief Checks whether the LPTIM interrupt has occurred or not. + * + * @param LPTIM_IT - specifies the LPTIM interrupt source to check. + * LPTIM_FLAG_DIR_SYNC - LPTIM counter direction indicate Interrupt source. + * LPTIM_IT_DOWN - LPTIM counter down Interrupt source. + * LPTIM_IT_UP - LPTIM counter up Interrupt source. + * LPTIM_IT_ARROK - LPTIM be loaded success Interrupt source. + * LPTIM_IT_CMPOK - LPTIM Capture Compare success Interrupt source. + * LPTIM_IT_EXTTRIG - TIM Trigger Interrupt source. + * LPTIM_IT_ARRM - TIM counter Count to ARR register Interrupt source. + * LPTIM_IT_CMPM - TIM counter Count to CMP register Interrupt source. + * + * @return none + */ +ITStatus LPTIM_GetITStatus(uint32_t LPTIM_IT) +{ + ITStatus bitstatus = RESET; + + if((LPTIM->ISR & LPTIM_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn LPTIM_ClearITPendingBit + * + * @brief Clears the LPTIM's interrupt pending bits. + * + * @param LPTIM_IT - specifies the LPTIM interrupt source to check. + * LPTIM_IT_DOWN - LPTIM counter down Interrupt source. + * LPTIM_IT_UP - LPTIM counter up Interrupt source. + * LPTIM_IT_ARROK - LPTIM be loaded success Interrupt source. + * LPTIM_IT_CMPOK - LPTIM Capture Compare success Interrupt source. + * LPTIM_IT_EXTTRIG - TIM Trigger Interrupt source. + * LPTIM_IT_ARRM - TIM counter Count to ARR register Interrupt source. + * LPTIM_IT_CMPM - TIM counter Count to CMP register Interrupt source. + * + * @return none + */ +void LPTIM_ClearITPendingBit(uint32_t LPTIM_IT) +{ + LPTIM->ICR |= (uint32_t)LPTIM_IT; +} + + + diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_misc.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_misc.c index 498f247..d18e287 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_misc.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_misc.c @@ -1,81 +1,81 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_misc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/12/26 - * Description : This file provides all the miscellaneous firmware functions . - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_misc.h" - -__IO uint32_t NVIC_Priority_Group = 0; - -/********************************************************************* - * @fn NVIC_PriorityGroupConfig - * - * @brief Configures the priority grouping - pre-emption priority and subpriority. - * - * @param NVIC_PriorityGroup - specifies the priority grouping bits length. - * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority - * 3 bits for subpriority - * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority - * 2 bits for subpriority - * - * @return none - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - NVIC_Priority_Group = NVIC_PriorityGroup; -} - -/********************************************************************* - * @fn NVIC_Init - * - * @brief Initializes the NVIC peripheral according to the specified parameters in - * the NVIC_InitStruct. - * - * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the - * configuration information for the specified NVIC peripheral. - * interrupt nesting enable(CSR-0x804 bit1 = 1) - * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. - * NVIC_IRQChannelSubPriority - range from 0 to 3. - * - * interrupt nesting disable(CSR-0x804 bit1 = 0) - * NVIC_IRQChannelPreemptionPriority - range is 0. - * NVIC_IRQChannelSubPriority - range from 0 to 7. - * - * @return none - */ -void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) -{ -#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) - if(NVIC_Priority_Group == NVIC_PriorityGroup_0) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); - } -#else - if(NVIC_Priority_Group == NVIC_PriorityGroup_1) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); - } - else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); - } - } -#endif - - if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } - else - { - NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_misc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : This file provides all the miscellaneous firmware functions . + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_misc.h" + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 3 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 2 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); + } +#else + if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + } +#endif + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_opa.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_opa.c index 0c767ba..b98e925 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_opa.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_opa.c @@ -1,323 +1,343 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_opa.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the OPA firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_opa.h" - -/* FLASH Keys */ -#define OPCM_KEY1 ((uint32_t)0x45670123) -#define OPCM_KEY2 ((uint32_t)0xCDEF89AB) - -volatile uint32_t CTLR2_tmp = 0; - -/******************************************************************************** - * @fn OPCM_Unlock - * - * @brief Unlocks the OPCM Controller. - * - * @return none - */ -void OPCM_Unlock(void) -{ - OPA->OPCMKEY = OPCM_KEY1; - OPA->OPCMKEY = OPCM_KEY2; -} - -/******************************************************************************** - * @fn OPCM_Lock - * - * @brief Locks the OPCM Controller. - * - * @return none - */ -void OPCM_Lock(void) -{ - OPA->CTLR1 |= (1<<7); -} - -/********************************************************************* - * @fn OPA_Init - * - * @brief Initializes the OPA peripheral according to the specified - * parameters in the OPA_InitStruct. - * - * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure - * - * @return none - */ -void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) -{ - uint16_t tmp0 = 0, tmp1 = 0; - uint32_t tmp2 = 0; - - tmp0 = OPA->CFGR1; - tmp1 = OPA->CFGR2; - tmp2 = OPA->CTLR1; - - if(OPA_InitStruct->OPA_NUM == OPA1) - { - tmp1 &= 0xF800; - tmp2 &= 0x80000001; - - tmp1 |= (OPA_InitStruct->POLL_NUM << 9); - tmp2 |= (OPA_InitStruct->Mode << 1) | (OPA_InitStruct->PSEL << 4) \ - | (OPA_InitStruct->FB << 7) | (OPA_InitStruct->NSEL << 8) \ - | OPA_Trim; - } - - tmp0 |= (OPA_InitStruct->PSEL_POLL) | (OPA_InitStruct->BKIN_EN << 2) - | (OPA_InitStruct->RST_EN << 4) | (OPA_InitStruct->OUT_IE << 8) - | (OPA_InitStruct->CNT_IE << 10) | (OPA_InitStruct->NMI_IE << 11); - tmp1 |= OPA_InitStruct->OPA_POLL_Interval; - - OPA->CFGR1 = tmp0; - OPA->CFGR2 = tmp1; - OPA->CTLR1 = tmp2; -} - -/********************************************************************* - * @fn OPA_StructInit - * - * @brief Fills each OPA_StructInit member with its reset value. - * - * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure - * - * @return none - */ -void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) -{ - OPA_InitStruct->OPA_POLL_Interval = 0; - OPA_InitStruct->OPA_NUM = OPA1; - OPA_InitStruct->Mode = OUT_IO_OFF; - OPA_InitStruct->PSEL = CHP_OFF; - OPA_InitStruct->FB = FB_OFF; - OPA_InitStruct->NSEL = CHN_OFF; - OPA_InitStruct->PSEL_POLL = CHP_OPA1_OFF; - OPA_InitStruct->BKIN_EN = BKIN_OPA1_OFF; - OPA_InitStruct->RST_EN = RST_OPA1_OFF; - OPA_InitStruct->OUT_IE = OUT_IE_OPA1_OFF; - OPA_InitStruct->CNT_IE = CNT_IE_OFF; - OPA_InitStruct->NMI_IE = NMI_IE_OFF; - OPA_InitStruct->POLL_NUM = CHP_POLL_NUM_1; -} - -/********************************************************************* - * @fn OPA_Cmd - * - * @brief Enables or disables the specified OPA peripheral. - * - * @param OPA_NUM - Select OPA - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - OPA->CTLR1 |= (uint32_t)(1 << (OPA_NUM*16)); - } - else - { - OPA->CTLR1 &= ~(uint32_t)(1 << (OPA_NUM*16)); - } -} - -/********************************************************************* - * @fn OPA_LP_Cmd - * - * @brief Enables or disables the OPA enter low power mode. - * - * @param NewState - new state of the OPA enter low power mode - * (ENABLE or DISABLE). - * - * @return none - */ -void OPA_LP_Cmd(FunctionalState NewState) -{ - if(NewState) - { - OPA->CTLR1 |= (1 << 12); - } - else - { - OPA->CTLR1 &= ~(1 << 12); - } -} - -/********************************************************************* - * @fn OPA_CMP_Init - * - * @brief Initializes the CMP peripheral according to the specified - * parameters in the CMP_InitTypeDef. - * - * @param CMP_InitStruct - pointer to a CMP_InitTypeDef structure - * - * @return none - */ -void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct) -{ - uint32_t tmp1 = 0; - - tmp1 = CTLR2_tmp; - - if(CMP_InitStruct->CMP_NUM == CMP1) - { - tmp1 &= 0xFFFFFFC1; - tmp1 |= (CMP_InitStruct->Mode << 1) | (CMP_InitStruct->NSEL << 3) - | (CMP_InitStruct->PSEL << 4); - } - else if(CMP_InitStruct->CMP_NUM == CMP2) - { - tmp1 &= 0xFFFFC1FF; - tmp1 |= (CMP_InitStruct->Mode << 9) | (CMP_InitStruct->NSEL << 11) - | (CMP_InitStruct->PSEL << 12); - } - else if(CMP_InitStruct->CMP_NUM == CMP3) - { - tmp1 &= 0xFFC1FFFF; - tmp1 |= (CMP_InitStruct->Mode << 17) | (CMP_InitStruct->NSEL << 19) - | (CMP_InitStruct->PSEL << 20); - } - - CTLR2_tmp = tmp1; - OPA->CTLR2 = tmp1; -} - -/********************************************************************* - * @fn OPA_CMP_StructInit - * - * @brief Fills each OPA_CMP_StructInit member with its reset value. - * - * @param CMP_StructInit - pointer to a OPA_CMP_StructInit structure - * - * @return none - */ -void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct) -{ - CMP_InitStruct->CMP_NUM = CMP1; - CMP_InitStruct->Mode = OUT_IO0; - CMP_InitStruct->NSEL = CMP_CHN0; - CMP_InitStruct->PSEL = CMP_CHP1; -} - -/********************************************************************* - * @fn OPA_CMP_Cmd - * - * @brief Enables or disables the specified CMP peripheral. - * - * @param CMP_NUM - Select CMP - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - CTLR2_tmp |= (uint32_t)(1 << (CMP_NUM*8)); - } - else - { - CTLR2_tmp &= ~(uint32_t)(1 << (CMP_NUM*8)); - } - - OPA->CTLR2 = CTLR2_tmp; -} - -/********************************************************************* - * @fn OPA_CMP_LP_Cmd - * - * @brief Enables or disables the CMP enter low power mode. - * - * @param CMP_NUM - Select CMP - * NewState - new state of the CMP enter low power mode - * (ENABLE or DISABLE). - * - * @return none - */ -void OPA_CMP_LP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) -{ - uint8_t tmp1 = 0; - - tmp1 = 6 + CMP_NUM * 8; - - if(NewState) - { - OPA->CTLR2 |= (1 << tmp1); - } - else - { - OPA->CTLR2 &= ~(1 << tmp1); - } -} - -/********************************************************************* - * @fn OPA_CMP_WakeUp_ModeConfig - * - * @brief Configures the CMP wake up Mode. - * - * @param CMP_WakeUP_Mode - Specifies the trigger signal active edge for wake up of the CMP. - * CMP_WakeUp_Rising_Falling - the trigger signal rise and fall edge for wake up. - * CMP_WakeUp_Rising - the trigger signal rise edge for wake up. - * CMP_WakeUp_Falling - the trigger signal fall edge for wake up. - * - * @return none - */ -void OPA_CMP_WakeUp_ModeConfig(uint32_t CMP_WakeUP_Mode) -{ - OPA->CTLR2 &= ~CMP_WakeUp_Falling; - OPA->CTLR2 |= CMP_WakeUP_Mode; -} - -/********************************************************************* - * @fn OPA_GetFlagStatus - * - * @brief Checks whether the OPA flag is set or not. - * - * @param OPA_FLAG - specifies the OPA flag to check. - * OPA_FLAG_OUT_OPA1 - OPA1 out flag - * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus OPA_GetFlagStatus(uint16_t OPA_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((OPA->CFGR1 & OPA_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn OPA_ClearFlag - * - * @brief Clears the OPA flag. - * - * @param OPA_FLAG - specifies the OPA flag to clear. - * OPA_FLAG_OUT_OPA1 - OPA1 out flag - * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data - * - * @return none - */ -void OPA_ClearFlag(uint16_t OPA_FLAG) -{ - OPA->CFGR1 &= (uint16_t)~OPA_FLAG; -} - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_opa.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/05 + * Description : This file provides all the OPA firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_opa.h" + +/* FLASH Keys */ +#define OPCM_KEY1 ((uint32_t)0x45670123) +#define OPCM_KEY2 ((uint32_t)0xCDEF89AB) + +/* mask definition*/ +#define POLL_CNT_MASK ((uint16_t)0x7000) + +volatile uint32_t CTLR2_tmp = 0; + + +/******************************************************************************** + * @fn OPCM_Unlock + * + * @brief Unlocks the OPCM Controller. + * + * @return none + */ +void OPCM_Unlock(void) +{ + OPA->OPCMKEY = OPCM_KEY1; + OPA->OPCMKEY = OPCM_KEY2; +} + +/******************************************************************************** + * @fn OPCM_Lock + * + * @brief Locks the OPCM Controller. + * + * @return none + */ +void OPCM_Lock(void) +{ + OPA->CTLR1 |= (1<<7); +} + +/********************************************************************* + * @fn OPA_Init + * + * @brief Initializes the OPA peripheral according to the specified + * parameters in the OPA_InitStruct. + * + * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) +{ + uint16_t tmp0 = 0, tmp1 = 0; + uint32_t tmp2 = 0; + + tmp0 = OPA->CFGR1; + tmp1 = OPA->CFGR2; + tmp2 = OPA->CTLR1; + + if(OPA_InitStruct->OPA_NUM == OPA1) + { + tmp1 &= 0xF800; + tmp2 &= 0x80000001; + + tmp1 |= (OPA_InitStruct->POLL_NUM << 9); + tmp2 |= (OPA_InitStruct->Mode << 1) | (OPA_InitStruct->PSEL << 4) \ + | (OPA_InitStruct->FB << 7) | (OPA_InitStruct->NSEL << 8) \ + | OPA_Trim; + } + + tmp0 |= (OPA_InitStruct->PSEL_POLL) | (OPA_InitStruct->BKIN_EN << 2) + | (OPA_InitStruct->RST_EN << 4) | (OPA_InitStruct->OUT_IE << 8) + | (OPA_InitStruct->CNT_IE << 10) | (OPA_InitStruct->NMI_IE << 11); + tmp1 |= OPA_InitStruct->OPA_POLL_Interval; + + OPA->CFGR1 = tmp0; + OPA->CFGR2 = tmp1; + OPA->CTLR1 = tmp2; +} + +/********************************************************************* + * @fn OPA_StructInit + * + * @brief Fills each OPA_StructInit member with its reset value. + * + * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) +{ + OPA_InitStruct->OPA_POLL_Interval = 0; + OPA_InitStruct->OPA_NUM = OPA1; + OPA_InitStruct->Mode = OUT_IO_OFF; + OPA_InitStruct->PSEL = CHP_OFF; + OPA_InitStruct->FB = FB_OFF; + OPA_InitStruct->NSEL = CHN_OFF; + OPA_InitStruct->PSEL_POLL = CHP_OPA1_OFF; + OPA_InitStruct->BKIN_EN = BKIN_OPA1_OFF; + OPA_InitStruct->RST_EN = RST_OPA1_OFF; + OPA_InitStruct->OUT_IE = OUT_IE_OPA1_OFF; + OPA_InitStruct->CNT_IE = CNT_IE_OFF; + OPA_InitStruct->NMI_IE = NMI_IE_OFF; + OPA_InitStruct->POLL_NUM = CHP_POLL_NUM_1; +} + +/********************************************************************* + * @fn OPA_Cmd + * + * @brief Enables or disables the specified OPA peripheral. + * + * @param OPA_NUM - Select OPA + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CTLR1 |= (uint32_t)(1 << (OPA_NUM*16)); + } + else + { + OPA->CTLR1 &= ~(uint32_t)(1 << (OPA_NUM*16)); + } +} + +/********************************************************************* + * @fn OPA_LP_Cmd + * + * @brief Enables or disables the OPA enter low power mode. + * + * @param NewState - new state of the OPA enter low power mode + * (ENABLE or DISABLE). + * + * @return none + */ +void OPA_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + OPA->CTLR1 |= (1 << 12); + } + else + { + OPA->CTLR1 &= ~(1 << 12); + } +} + +/********************************************************************* + * @fn OPA_CMP_Init + * + * @brief Initializes the CMP peripheral according to the specified + * parameters in the CMP_InitTypeDef. + * + * @param CMP_InitStruct - pointer to a CMP_InitTypeDef structure + * + * @return none + */ +void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct) +{ + uint32_t tmp1 = 0; + + tmp1 = CTLR2_tmp; + + if(CMP_InitStruct->CMP_NUM == CMP1) + { + tmp1 &= 0xFFFFFFC1; + tmp1 |= (CMP_InitStruct->Mode << 1) | (CMP_InitStruct->NSEL << 3) + | (CMP_InitStruct->PSEL << 4) | (CMP_InitStruct->HYEN <<5); + } + else if(CMP_InitStruct->CMP_NUM == CMP2) + { + tmp1 &= 0xFFFFC1FF; + tmp1 |= (CMP_InitStruct->Mode << 9) | (CMP_InitStruct->NSEL << 11) + | (CMP_InitStruct->PSEL << 12) | (CMP_InitStruct->HYEN <<13); + } + else if(CMP_InitStruct->CMP_NUM == CMP3) + { + tmp1 &= 0xFFC1FFFF; + tmp1 |= (CMP_InitStruct->Mode << 17) | (CMP_InitStruct->NSEL << 19) + | (CMP_InitStruct->PSEL << 20) | (CMP_InitStruct->HYEN <<21); + } + + CTLR2_tmp = tmp1; + OPA->CTLR2 = tmp1; +} + +/********************************************************************* + * @fn OPA_CMP_StructInit + * + * @brief Fills each OPA_CMP_StructInit member with its reset value. + * + * @param CMP_StructInit - pointer to a OPA_CMP_StructInit structure + * + * @return none + */ +void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct) +{ + CMP_InitStruct->CMP_NUM = CMP1; + CMP_InitStruct->Mode = OUT_IO0; + CMP_InitStruct->NSEL = CMP_CHN0; + CMP_InitStruct->PSEL = CMP_CHP_0; +} + +/********************************************************************* + * @fn OPA_CMP_Cmd + * + * @brief Enables or disables the specified CMP peripheral. + * + * @param CMP_NUM - Select CMP + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + CTLR2_tmp |= (uint32_t)(1 << (CMP_NUM*8)); + } + else + { + CTLR2_tmp &= ~(uint32_t)(1 << (CMP_NUM*8)); + } + + OPA->CTLR2 = CTLR2_tmp; +} + +/********************************************************************* + * @fn OPA_CMP_LP_Cmd + * + * @brief Enables or disables the CMP enter low power mode. + * + * @param CMP_NUM - Select CMP + * NewState - new state of the CMP enter low power mode + * (ENABLE or DISABLE). + * + * @return none + */ +void OPA_CMP_LP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) +{ + uint8_t tmp1 = 0; + + tmp1 = 6 + CMP_NUM * 8; + + if(NewState) + { + OPA->CTLR2 |= (1 << tmp1); + } + else + { + OPA->CTLR2 &= ~(1 << tmp1); + } +} + +/********************************************************************* + * @fn OPA_CMP_WakeUp_ModeConfig + * + * @brief Configures the CMP wake up Mode. + * + * @param CMP_WakeUP_Mode - Specifies the trigger signal active edge for wake up of the CMP. + * CMP_WakeUp_Rising_Falling - the trigger signal rise and fall edge for wake up. + * CMP_WakeUp_Rising - the trigger signal rise edge for wake up. + * CMP_WakeUp_Falling - the trigger signal fall edge for wake up. + * + * @return none + */ +void OPA_CMP_WakeUp_ModeConfig(uint32_t CMP_WakeUP_Mode) +{ + OPA->CTLR2 &= ~CMP_WakeUp_Falling; + OPA->CTLR2 |= CMP_WakeUP_Mode; +} + +/********************************************************************* + * @fn OPA_GetFlagStatus + * + * @brief Checks whether the OPA flag is set or not. + * + * @param OPA_FLAG - specifies the OPA flag to check. + * OPA_FLAG_OUT_OPA1 - OPA1 out flag + * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus OPA_GetFlagStatus(uint16_t OPA_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((OPA->CFGR1 & OPA_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn OPA_ClearFlag + * + * @brief Clears the OPA flag. + * + * @param OPA_FLAG - specifies the OPA flag to clear. + * OPA_FLAG_OUT_OPA1 - OPA1 out flag + * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data + * + * @return none + */ +void OPA_ClearFlag(uint16_t OPA_FLAG) +{ + OPA->CFGR1 &= (uint16_t)~OPA_FLAG; +} + +/********************************************************************* + * @fn OPA_POLL_CNT + * + * @brief Displays the current channel being polled by the OPA + * + * @param none + * + * @return OPA_POLL_NUM_TypeDef - Current channel for OPA polling + */ +OPA_POLL_NUM_TypeDef OPA_POLL_CNT(void) +{ + uint16_t tmp1 = 0; + tmp1 = OPA->CFGR2; + tmp1 &= POLL_CNT_MASK; + tmp1 = tmp1 >> 12; + return tmp1; +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_pwr.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_pwr.c index 550fd6d..ef2a46b 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_pwr.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_pwr.c @@ -1,466 +1,466 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_pwr.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/22 - * Description : This file provides all the PWR firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_pwr.h" -#include "ch32l103_rcc.h" - -/* PWR registers bit mask */ -/* CTLR register bit mask */ -#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) - -/********************************************************************* - * @fn PWR_DeInit - * - * @brief Deinitializes the PWR peripheral registers to their default - * reset values. - * - * @return none - */ -void PWR_DeInit(void) -{ - RCC_PB1PeriphResetCmd(RCC_PB1Periph_PWR, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_PWR, DISABLE); -} - -/********************************************************************* - * @fn PWR_BackupAccessCmd - * - * @brief Enables or disables access to the RTC and backup registers. - * - * @param NewState - new state of the access to the RTC and backup registers, - * This parameter can be: ENABLE or DISABLE. - * - * @return none - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (1 << 8); - } - else - { - PWR->CTLR &= ~(1 << 8); - } -} - -/********************************************************************* - * @fn PWR_PVDCmd - * - * @brief Enables or disables the Power Voltage Detector(PVD). - * - * @param NewState - new state of the PVD(ENABLE or DISABLE). - * - * @return none - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (1 << 4); - } - else - { - PWR->CTLR &= ~(1 << 4); - } -} - -/********************************************************************* - * @fn PWR_PVDLevelConfig - * - * @brief Configures the voltage threshold detected by the Power Voltage - * Detector(PVD). - * - * @param PWR_PVDLevel - specifies the PVD detection level - * PWR_PVDLevel_0 - PVD detection level set to mode 0. - * PWR_PVDLevel_1 - PVD detection level set to mode 1. - * PWR_PVDLevel_2 - PVD detection level set to mode 2. - * PWR_PVDLevel_3 - PVD detection level set to mode 3. - * PWR_PVDLevel_4 - PVD detection level set to mode 4. - * PWR_PVDLevel_5 - PVD detection level set to mode 5. - * PWR_PVDLevel_6 - PVD detection level set to mode 6. - * PWR_PVDLevel_7 - PVD detection level set to mode 7. - * - * @return none - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_PLS_MASK; - tmpreg |= PWR_PVDLevel; - PWR->CTLR = tmpreg; -} - -/********************************************************************* - * @fn PWR_WakeUpPinCmd - * - * @brief Enables or disables the WakeUp Pin functionality. - * - * @param NewState - new state of the WakeUp Pin functionality - * (ENABLE or DISABLE). - * - * @return none - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CSR |= (1 << 8); - } - else - { - PWR->CSR &= ~(1 << 8); - } -} - -/********************************************************************* - * @fn PWR_EnterSTOPMode - * - * @brief Enters STOP mode. - * - * @param PWR_Regulator - specifies the regulator state in STOP mode. - * PWR_Regulator_ON - STOP mode with regulator ON - * PWR_Regulator_LowPower - STOP mode with regulator in low power mode - * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. - * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction - * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction - * - * @return none - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_DS_MASK; - tmpreg |= PWR_Regulator; - if(PWR_Regulator==PWR_Regulator_LowPower) - { - tmpreg &= ~(3 << 10); - tmpreg |= (1 <<11); - } - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - __WFI(); - } - else - { - __WFE(); - } - - NVIC->SCTLR &= ~(1 << 2); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode - * - * @brief Enters STANDBY mode. - * - * @return none - */ -void PWR_EnterSTANDBYMode(void) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - /* flash low power mode 1 */ - tmpreg &= ~(3 << 10); - tmpreg |= (1 << 11); - - tmpreg |= PWR_CTLR_CWUF; - tmpreg |= PWR_CTLR_PDDS; - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_GetFlagStatus - * - * @brief Checks whether the specified PWR flag is set or not. - * - * @param PWR_FLAG - specifies the flag to check. - * PWR_FLAG_WU - Wake Up flag - * PWR_FLAG_SB - StandBy flag - * PWR_FLAG_PVDO - PVD Output - * - * @return none - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn PWR_ClearFlag - * - * @brief Clears the PWR's pending flags. - * - * @param PWR_FLAG - specifies the flag to clear. - * PWR_FLAG_WU - Wake Up flag - * PWR_FLAG_SB - StandBy flag - * - * @return none - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - PWR->CTLR |= PWR_FLAG << 2; -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode_RAM - * - * @brief Enters STANDBY mode with RAM data retention function on. - * - * @return none - */ -void PWR_EnterSTANDBYMode_RAM(void) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - - /* flash low power mode 1 */ - tmpreg &= ~(3 << 10); - tmpreg |= (1 << 11); - - tmpreg |= PWR_CTLR_CWUF; - tmpreg |= PWR_CTLR_PDDS; - - //2K+18K in standby power. - tmpreg |= (0x1 << 16) | (0x1 << 17); - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode_RAM_LV - * - * @brief Enters STANDBY mode with RAM data retention function and LV mode on. - * - * @return none - */ -void PWR_EnterSTANDBYMode_RAM_LV(void) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - - /* flash low power mode 1 */ - tmpreg &= ~(3 << 10); - tmpreg |= (1 << 11); - - tmpreg |= PWR_CTLR_CWUF; - tmpreg |= PWR_CTLR_PDDS; - - //2K+18K in standby power. - tmpreg |= (0x1 << 16) | (0x1 << 17); - //2K+18K in standby LV . - tmpreg |= (0x1 << 20); - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN - * - * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable). - * - * @return none - */ -void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - - /* flash low power mode 1 */ - tmpreg &= ~(3 << 10); - tmpreg |= (1 << 11); - - tmpreg |= PWR_CTLR_CWUF; - tmpreg |= PWR_CTLR_PDDS; - - //2K+18K in standby power (VBAT Enable). - tmpreg |= (0x1 << 18) | (0x1 << 19); - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN - * - * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable). - * - * @return none - */ -void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - - /* flash low power mode 1 */ - tmpreg &= ~(3 << 10); - tmpreg |= (1 << 11); - - tmpreg |= PWR_CTLR_CWUF; - tmpreg |= PWR_CTLR_PDDS; - - //2K+18K in standby power (VBAT Enable). - tmpreg |= (0x1 << 18) | (0x1 << 19); - //2K+18K in standby LV . - tmpreg |= (0x1 << 20); - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - - -/********************************************************************* - * @fn PWR_EnterSTOPMode_RAM_LV - * - * @brief Enters STOP mode with RAM data retention function and LV mode on. - * - * @param PWR_Regulator - specifies the regulator state in STOP mode. - * PWR_Regulator_ON - STOP mode with regulator ON - * PWR_Regulator_LowPower - STOP mode with regulator in low power mode - * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. - * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction - * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction - * - * @return none - */ -void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_DS_MASK; - tmpreg |= PWR_Regulator; - tmpreg |= (0x1 << 20); - - if(PWR_Regulator==PWR_Regulator_LowPower) - { - tmpreg &= ~(3 << 10); - tmpreg |= (1 << 11); - } - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - __WFI(); - } - else - { - __WFE(); - } - - NVIC->SCTLR &= ~(1 << 2); -} - -/********************************************************************* - * @fn PWR_LDO_LP_Cmd - * - * @brief Enables or disables the LDO low power mode. - * - * @param NewState - new state of the LDO low power mode(ENABLE or DISABLE). - * - * @return none - */ -void PWR_LDO_LP_Cmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (1 << 13); - } - else - { - PWR->CTLR &= ~(1 << 13); - } -} - -/********************************************************************* - * @fn PWR_STOPMode_Auto_LDO_LP_Cmd - * - * @brief Enables or disables the LDO auto enter low power mode in - * stop mode. - * - * @param NewState - new state of the LDO auto enter low power mode - * in stop mode(ENABLE or DISABLE). - * - * @return none - */ -void PWR_STOPMode_Auto_LDO_LP_Cmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (1 << 12); - } - else - { - PWR->CTLR &= ~(1 << 12); - } -} - -/********************************************************************* - * @fn PWR_FLASH_LP_Cmd - * - * @brief Enables or disables the FLASH enter low power mode 0. - * - * @param NewState - new state of the FLASH enter low power mode 0. - * (ENABLE or DISABLE). - * - * @return none - */ -void PWR_FLASH_LP_Cmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (7 << 9); - } - else - { - PWR->CTLR &= ~(1 << 9); - } -} - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_pwr.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/22 + * Description : This file provides all the PWR firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_pwr.h" +#include "ch32l103_rcc.h" + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_PB1PeriphResetCmd(RCC_PB1Periph_PWR, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_BackupAccessCmd + * + * @brief Enables or disables access to the RTC and backup registers. + * + * @param NewState - new state of the access to the RTC and backup registers, + * This parameter can be: ENABLE or DISABLE. + * + * @return none + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 8); + } + else + { + PWR->CTLR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_PVDCmd + * + * @brief Enables or disables the Power Voltage Detector(PVD). + * + * @param NewState - new state of the PVD(ENABLE or DISABLE). + * + * @return none + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 4); + } + else + { + PWR->CTLR &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_0 - PVD detection level set to mode 0. + * PWR_PVDLevel_1 - PVD detection level set to mode 1. + * PWR_PVDLevel_2 - PVD detection level set to mode 2. + * PWR_PVDLevel_3 - PVD detection level set to mode 3. + * PWR_PVDLevel_4 - PVD detection level set to mode 4. + * PWR_PVDLevel_5 - PVD detection level set to mode 5. + * PWR_PVDLevel_6 - PVD detection level set to mode 6. + * PWR_PVDLevel_7 - PVD detection level set to mode 7. + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_WakeUpPinCmd + * + * @brief Enables or disables the WakeUp Pin functionality. + * + * @param NewState - new state of the WakeUp Pin functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CSR |= (1 << 8); + } + else + { + PWR->CSR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_EnterSTOPMode + * + * @brief Enters STOP mode. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_ON - STOP mode with regulator ON + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + if(PWR_Regulator==PWR_Regulator_LowPower) + { + tmpreg &= ~(3 << 10); + tmpreg |= (1 <<11); + } + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @return none + */ +void PWR_EnterSTANDBYMode(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * PWR_FLAG_PVDO - PVD Output + * + * @return none + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn PWR_ClearFlag + * + * @brief Clears the PWR's pending flags. + * + * @param PWR_FLAG - specifies the flag to clear. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * + * @return none + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + PWR->CTLR |= PWR_FLAG << 2; +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM + * + * @brief Enters STANDBY mode with RAM data retention function on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+18K in standby power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+18K in standby power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + //2K+18K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+18K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + /* flash low power mode 1 */ + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+18K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + //2K+18K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + + +/********************************************************************* + * @fn PWR_EnterSTOPMode_RAM_LV + * + * @brief Enters STOP mode with RAM data retention function and LV mode on. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_ON - STOP mode with regulator ON + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + tmpreg |= (0x1 << 20); + + if(PWR_Regulator==PWR_Regulator_LowPower) + { + tmpreg &= ~(3 << 10); + tmpreg |= (1 << 11); + } + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_LDO_LP_Cmd + * + * @brief Enables or disables the LDO low power mode. + * + * @param NewState - new state of the LDO low power mode(ENABLE or DISABLE). + * + * @return none + */ +void PWR_LDO_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 13); + } + else + { + PWR->CTLR &= ~(1 << 13); + } +} + +/********************************************************************* + * @fn PWR_STOPMode_Auto_LDO_LP_Cmd + * + * @brief Enables or disables the LDO auto enter low power mode in + * stop mode. + * + * @param NewState - new state of the LDO auto enter low power mode + * in stop mode(ENABLE or DISABLE). + * + * @return none + */ +void PWR_STOPMode_Auto_LDO_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 12); + } + else + { + PWR->CTLR &= ~(1 << 12); + } +} + +/********************************************************************* + * @fn PWR_FLASH_LP_Cmd + * + * @brief Enables or disables the FLASH enter low power mode 0. + * + * @param NewState - new state of the FLASH enter low power mode 0. + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_FLASH_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (7 << 9); + } + else + { + PWR->CTLR &= ~(1 << 9); + } +} + + diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_rcc.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_rcc.c index 53287fb..e0a0a85 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_rcc.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_rcc.c @@ -1,1045 +1,1045 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_rcc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the RCC firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_rcc.h" - -/* RCC registers bit address in the alias region */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* BDCTLR Register */ -#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) - -/* RCC registers bit mask */ - -/* CTLR register bit mask */ -#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) -#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CTLR_HSEON_Set ((uint32_t)0x00010000) -#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -/* CFGR0 register bit mask */ -#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) -#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) -#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) -#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) -#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) -#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) -#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) -#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0x7FFF3FFF) -#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) -#define CFGR0_ADCDUTY_Reset_Mask ((uint32_t)0x8FFFFFFF) - -/* RSTSCKR register bit mask */ -#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -/* INTR register byte 2 (Bits[15:8]) base address */ -#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* INTR register byte 3 (Bits[23:16]) base address */ -#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CFGR0 register byte 4 (Bits[31:24]) base address */ -#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) - -/* BDCTLR register base address */ -#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) - - -static __I uint8_t PBHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; - -/********************************************************************* - * @fn RCC_DeInit - * - * @brief Resets the RCC clock configuration to the default reset state. - * Note- - * HSE can not be stopped if it is used directly or through the PLL as system clock. - * @return none - */ -void RCC_DeInit(void) -{ - RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0x08FF0000; - RCC->CTLR &= (uint32_t)0xFEF6FFFB; - RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF00FFFF; - RCC->INTR = 0x009F0000; -} - -/********************************************************************* - * @fn RCC_HSEConfig - * - * @brief Configures the External High Speed oscillator (HSE). - * - * @param RCC_HSE - - * RCC_HSE_OFF - HSE oscillator OFF. - * RCC_HSE_ON - HSE oscillator ON. - * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. - * Note - - * HSE can not be stopped if it is used directly or through the PLL as system clock. - * @return none - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - RCC->CTLR &= CTLR_HSEON_Reset; - RCC->CTLR &= CTLR_HSEBYP_Reset; - - switch(RCC_HSE) - { - case RCC_HSE_ON: - RCC->CTLR |= CTLR_HSEON_Set; - break; - - case RCC_HSE_Bypass: - RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn RCC_WaitForHSEStartUp - * - * @brief Waits for HSE start-up. - * - * @return READY - HSE oscillator is stable and ready to use. - * NoREADY - HSE oscillator not yet ready. - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - - ErrorStatus status = NoREADY; - FlagStatus HSEStatus = RESET; - - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = READY; - } - else - { - status = NoREADY; - } - - return (status); -} - -/********************************************************************* - * @fn RCC_AdjustHSICalibrationValue - * - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * - * @param HSICalibrationValue - specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * - * @return none - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CTLR; - tmpreg &= CTLR_HSITRIM_Mask; - tmpreg |= (uint32_t)HSICalibrationValue << 3; - RCC->CTLR = tmpreg; -} - -/********************************************************************* - * @fn RCC_HSICmd - * - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_HSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<0); - } - else - { - RCC->CTLR &= ~(1<<0); - } -} - -/********************************************************************* - * @fn RCC_PLLConfig - * - * @brief Configures the PLL clock source and multiplication factor. - * - * @param RCC_PLLSource - specifies the PLL entry clock source. - * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 - * selected as PLL clock entry. - * RCC_PLLSource_HSE_Div1 - HSI oscillator clock as PLL clock - * entry. - * RCC_PLLSource_HSE_Div2 - HSI oscillator clock divided by 2 - * as PLL clock entry. - * RCC_PLLMul - specifies the PLL multiplication factor. - * This parameter can be RCC_PLLMul_x where x:[2,16]. - * RCC_PLLMul_2 - * RCC_PLLMul_3 - * RCC_PLLMul_4 - * RCC_PLLMul_5 - * RCC_PLLMul_6 - * RCC_PLLMul_7 - * RCC_PLLMul_8 - * RCC_PLLMul_9 - * RCC_PLLMul_10 - * RCC_PLLMul_11 - * RCC_PLLMul_12 - * RCC_PLLMul_13 - * RCC_PLLMul_14 - * RCC_PLLMul_15 - * RCC_PLLMul_16 - * RCC_PLLMul_18 - * - * @return none - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - - tmpreg &= CFGR0_PLL_Mask; - tmpreg |= RCC_PLLSource | RCC_PLLMul; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PLLCmd - * - * @brief Enables or disables the PLL. - * Note-The PLL can not be disabled if it is used as system clock. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<24); - } - else - { - RCC->CTLR &= ~(1<<24); - } -} - -/********************************************************************* - * @fn RCC_SYSCLKConfig - * - * @brief Configures the system clock (SYSCLK). - * - * @param RCC_SYSCLKSource - specifies the clock source used as system clock. - * RCC_SYSCLKSource_HSI - HSI selected as system clock. - * RCC_SYSCLKSource_HSE - HSE selected as system clock. - * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. - * - * @return none - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_SW_Mask; - tmpreg |= RCC_SYSCLKSource; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_GetSYSCLKSource - * - * @brief Returns the clock source used as system clock. - * - * @return 0x00 - HSI used as system clock. - * 0x04 - HSE used as system clock. - * 0x08 - PLL used as system clock. - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); -} - -/********************************************************************* - * @fn RCC_HCLKConfig - * - * @brief Configures the HB clock (HCLK). - * - * @param RCC_SYSCLK - defines the HB clock divider. This clock is derived from - * the system clock (SYSCLK). - * RCC_SYSCLK_Div1 - HB clock = SYSCLK. - * RCC_SYSCLK_Div2 - HB clock = SYSCLK/2. - * RCC_SYSCLK_Div4 - HB clock = SYSCLK/4. - * RCC_SYSCLK_Div8 - HB clock = SYSCLK/8. - * RCC_SYSCLK_Div16 - HB clock = SYSCLK/16. - * RCC_SYSCLK_Div64 - HB clock = SYSCLK/64. - * RCC_SYSCLK_Div128 - HB clock = SYSCLK/128. - * RCC_SYSCLK_Div256 - HB clock = SYSCLK/256. - * RCC_SYSCLK_Div512 - HB clock = SYSCLK/512. - * - * @return none - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_HPRE_Reset_Mask; - tmpreg |= RCC_SYSCLK; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PCLK1Config - * - * @brief Configures the Low Speed PB clock (PCLK1). - * - * @param RCC_HCLK - defines the PB1 clock divider. This clock is derived from - * the HB clock (HCLK). - * RCC_HCLK_Div1 - PB1 clock = HCLK. - * RCC_HCLK_Div2 - PB1 clock = HCLK/2. - * RCC_HCLK_Div4 - PB1 clock = HCLK/4. - * RCC_HCLK_Div8 - PB1 clock = HCLK/8. - * RCC_HCLK_Div16 - PB1 clock = HCLK/16. - * - * @return none - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_PPRE1_Reset_Mask; - tmpreg |= RCC_HCLK; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PCLK2Config - * - * @brief Configures the High Speed PB clock (PCLK2). - * - * @param RCC_HCLK - defines the PB2 clock divider. This clock is derived from - * the HB clock (HCLK). - * RCC_HCLK_Div1 - PB2 clock = HCLK. - * RCC_HCLK_Div2 - PB2 clock = HCLK/2. - * RCC_HCLK_Div4 - PB2 clock = HCLK/4. - * RCC_HCLK_Div8 - PB2 clock = HCLK/8. - * RCC_HCLK_Div16 - PB2 clock = HCLK/16. - * @return none - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_PPRE2_Reset_Mask; - tmpreg |= RCC_HCLK << 3; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_ITConfig - * - * @brief Enables or disables the specified RCC interrupts. - * - * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - *(__IO uint8_t *) INTR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - *(__IO uint8_t *) INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/********************************************************************* - * @fn RCC_USBCLKConfig - * - * @brief Configures the USB clock (USBCLK). - * - * @param RCC_USBCLKSource: specifies the USB clock source. This clock is - * derived from the PLL output. - * RCC_USBCLKSource_PLLCLK_Div1 - PLL clock selected as USB clock source(48Mhz). - * RCC_USBCLKSource_PLLCLK_Div2 - PLL clock selected as USB clock source(96MHz). - * RCC_USBCLKSource_PLLCLK_Div1_5 - PLL clock selected as USB clock source(72MHz). - * - * @return none - */ -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) -{ - RCC->CFGR0 &= ~((uint32_t)3<<22); - RCC->CFGR0 |= RCC_USBCLKSource; -} - -/********************************************************************* - * @fn RCC_ADCCLKConfig - * - * @brief Configures the ADC clock (ADCCLK). - * - * @param ADC_CLK_S - defines the ADC clock. - * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. - * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. - * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. - * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. - * RCC_HCLK_ADC - ADC clock = HCLK. - * - * @return none - */ -void RCC_ADCCLKConfig(uint32_t ADC_CLK_S) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_ADCPRE_Reset_Mask; - tmpreg |= ADC_CLK_S; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_LSEConfig - * - * @brief Configures the External Low Speed oscillator (LSE). - * - * @param RCC_LSE - specifies the new state of the LSE. - * RCC_LSE_OFF - LSE oscillator OFF. - * RCC_LSE_ON - LSE oscillator ON. - * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. - * - * @return none - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; - *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; - - switch(RCC_LSE) - { - case RCC_LSE_ON: - *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_ON; - break; - - case RCC_LSE_Bypass: - *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn RCC_LSICmd - * - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * Note- - * LSI can not be disabled if the IWDG is running. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_LSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->RSTSCKR |= (1<<0); - } - else{ - RCC->RSTSCKR &= ~(1<<0); - } -} - -/********************************************************************* - * @fn RCC_RTCCLKConfig - * - * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. - * - * @param RCC_RTCCLKSource - specifies the RTC clock source. - * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. - * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. - * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. - * Note- - * Once the RTC clock is selected it can't be changed unless the Backup domain is reset. - * - * @return none - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - RCC->BDCTLR |= RCC_RTCCLKSource; -} - -/********************************************************************* - * @fn RCC_RTCCLKCmd - * - * @brief This function must be used only after the RTC clock was selected - * using the RCC_RTCCLKConfig function. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->BDCTLR |= (1<<15); - } - else - { - RCC->BDCTLR &= ~(1<<15); - } -} - -/********************************************************************* - * @fn RCC_GetClocksFreq - * - * @brief The result of this function could be not correct when using - * fractional value for HSE crystal. - * - * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @return none - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; - - tmp = RCC->CFGR0 & CFGR0_SWS_Mask; - - switch (tmp) - { - case 0x00: - if(RCC->CTLR & (1<<2)) - { - RCC_Clocks->SYSCLK_Frequency = HSI_LP_VALUE; - } - else - { - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - } - break; - - case 0x04: - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - - case 0x08: - pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; - pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; - - pllmull = ( pllmull >> 18) + 2; - - if(pllmull == 17) pllmull = 18; - - - if (pllsource == 0x00) - { - if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE) * pllmull; - } - else{ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >>1) * pllmull; - } - } - else - { - if ((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) - { - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; - } - else - { - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; - - } - } - - break; - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - - tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = PBHBPrescTable[tmp]; - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; - tmp = tmp >> 8; - presc = PBHBPrescTable[tmp]; - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; - tmp = tmp >> 11; - presc = PBHBPrescTable[tmp]; - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - - if(RCC->CFGR0 & (1<<31)) - { - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->HCLK_Frequency; - } - else - { - tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; - tmp = tmp >> 14; - presc = ADCPrescTable[tmp]; - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; - } -} - -/********************************************************************* - * @fn RCC_HBPeriphClockCmd - * - * @brief Enables or disables the HB peripheral clock. - * - * @param RCC_HBPeriph - specifies the HB peripheral to gates its clock. - * RCC_HBPeriph_DMA1. - * RCC_HBPeriph_SRAM. - * RCC_HBPeriph_CRC. - * RCC_HBPeriph_USBFS. - * RCC_HBPeriph_USBPD. - * Note- - * SRAM clock can be disabled only during sleep mode. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void RCC_HBPeriphClockCmd(uint32_t RCC_HBPeriph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->HBPCENR |= RCC_HBPeriph; - } - else - { - RCC->HBPCENR &= ~RCC_HBPeriph; - } -} - -/********************************************************************* - * @fn RCC_PB2PeriphClockCmd - * - * @brief Enables or disables the High Speed PB (PB2) peripheral clock. - * - * @param RCC_PB2Periph - specifies the PB2 peripheral to gates its clock. - * RCC_PB2Periph_AFIO. - * RCC_PB2Periph_GPIOA. - * RCC_PB2Periph_GPIOB. - * RCC_PB2Periph_GPIOC. - * RCC_PB2Periph_GPIOD. - * RCC_PB2Periph_ADC1. - * RCC_PB2Periph_TIM1. - * RCC_PB2Periph_SPI1. - * RCC_PB2Periph_TIM8 - * RCC_PB2Periph_USART1. - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_PB2PeriphClockCmd(uint32_t RCC_PB2Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->PB2PCENR |= RCC_PB2Periph; - } - else - { - RCC->PB2PCENR &= ~RCC_PB2Periph; - } -} - -/********************************************************************* - * @fn RCC_PB1PeriphClockCmd - * - * @brief Enables or disables the Low Speed PB (PB1) peripheral clock. - * - * @param RCC_PB1Periph - specifies the PB1 peripheral to gates its clock. - * RCC_PB1Periph_TIM2. - * RCC_PB1Periph_TIM3. - * RCC_PB1Periph_TIM4. - * RCC_PB1Periph_WWDG. - * RCC_PB1Periph_SPI2. - * RCC_PB1Periph_USART2. - * RCC_PB1Periph_USART3. - * RCC_PB1Periph_USART4 - * RCC_PB1Periph_I2C1. - * RCC_PB1Periph_I2C2. - * RCC_PB1Periph_CAN1. - * RCC_PB1Periph_BKP. - * RCC_PB1Periph_PWR. - * RCC_PB1Periph_LPTIM. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_PB1PeriphClockCmd(uint32_t RCC_PB1Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->PB1PCENR |= RCC_PB1Periph; - } - else - { - RCC->PB1PCENR &= ~RCC_PB1Periph; - } -} - -/********************************************************************* - * @fn RCC_PB2PeriphResetCmd - * - * @brief Forces or releases High Speed PB (PB2) peripheral reset. - * - * @param RCC_PB2Periph - specifies the PB2 peripheral to reset. - * RCC_PB2Periph_AFIO. - * RCC_PB2Periph_GPIOA. - * RCC_PB2Periph_GPIOB. - * RCC_PB2Periph_GPIOC. - * RCC_PB2Periph_GPIOD. - * RCC_PB2Periph_ADC1. - * RCC_PB2Periph_TIM1. - * RCC_PB2Periph_SPI1. - * RCC_PB2Periph_TIM8 - * RCC_PB2Periph_USART1. - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_PB2PeriphResetCmd(uint32_t RCC_PB2Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->PB2PRSTR |= RCC_PB2Periph; - } - else - { - RCC->PB2PRSTR &= ~RCC_PB2Periph; - } -} - -/********************************************************************* - * @fn RCC_PB1PeriphResetCmd - * - * @brief Forces or releases Low Speed PB (PB1) peripheral reset. - * - * @param RCC_PB1Periph - specifies the PB1 peripheral to reset. - * RCC_PB1Periph_TIM2. - * RCC_PB1Periph_TIM3. - * RCC_PB1Periph_TIM4. - * RCC_PB1Periph_WWDG. - * RCC_PB1Periph_SPI2. - * RCC_PB1Periph_USART2. - * RCC_PB1Periph_USART3. - * RCC_PB1Periph_USART4 - * RCC_PB1Periph_I2C1. - * RCC_PB1Periph_I2C2. - * RCC_PB1Periph_CAN1. - * RCC_PB1Periph_BKP. - * RCC_PB1Periph_PWR. - * RCC_PB1Periph_LPTIM. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_PB1PeriphResetCmd(uint32_t RCC_PB1Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->PB1PRSTR |= RCC_PB1Periph; - } - else - { - RCC->PB1PRSTR &= ~RCC_PB1Periph; - } -} - -/********************************************************************* - * @fn RCC_BackupResetCmd - * - * @brief Forces or releases the Backup domain reset. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->BDCTLR |= (1<<16); - } - else{ - RCC->BDCTLR &= ~(1<<16); - } -} - -/******************************************************************************* -* Function Name : RCC_ClockSecuritySystemCmd -* Description : Enables or disables the Clock Security System. -* Input : NewState: ENABLE or DISABLE. -* Return : None -*******************************************************************************/ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<19); - } - else{ - RCC->CTLR &= ~(1<<19); - } -} - -/********************************************************************* - * @fn RCC_MCOConfig - * - * @brief Selects the clock source to output on MCO pin. - * - * @param RCC_MCO - specifies the clock source to output. - * RCC_MCO_NoClock - No clock selected. - * RCC_MCO_SYSCLK - System clock selected. - * RCC_MCO_HSI - HSI oscillator clock selected. - * RCC_MCO_HSE - HSE oscillator clock selected. - * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. - * - * @return none - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO; -} - -/********************************************************************* - * @fn RCC_GetFlagStatus - * - * @brief Checks whether the specified RCC flag is set or not. - * - * @param RCC_FLAG - specifies the flag to check. - * RCC_FLAG_HSIRDY - HSI oscillator clock ready. - * RCC_FLAG_HSERDY - HSE oscillator clock ready. - * RCC_FLAG_PLLRDY - PLL clock ready. - * RCC_FLAG_LSERDY - LSE oscillator clock ready. - * RCC_FLAG_LSIRDY - LSI oscillator clock ready. - * RCC_FLAG_PINRST - Pin reset. - * RCC_FLAG_PORRST - POR/PDR reset. - * RCC_FLAG_SFTRST - Software reset. - * RCC_FLAG_IWDGRST - Independent Watchdog reset. - * RCC_FLAG_WWDGRST - Window Watchdog reset. - * RCC_FLAG_LPWRRST - Low Power reset. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - - FlagStatus bitstatus = RESET; - tmp = RCC_FLAG >> 5; - - if (tmp == 1) - { - statusreg = RCC->CTLR; - } - else if (tmp == 2) - { - statusreg = RCC->BDCTLR; - } - else - { - statusreg = RCC->RSTSCKR; - } - - tmp = RCC_FLAG & FLAG_Mask; - - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearFlag - * - * @brief Clears the RCC reset flags. - * Note- - * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * - * @return none - */ -void RCC_ClearFlag(void) -{ - RCC->RSTSCKR |= RSTSCKR_RMVF_Set; -} - -/********************************************************************* - * @fn RCC_GetITStatus - * - * @brief Checks whether the specified RCC interrupt has occurred or not. - * - * @param RCC_IT - specifies the RCC interrupt source to check. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * - * @return ITStatus - SET or RESET. - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - if ((RCC->INTR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearITPendingBit - * - * @brief Clears the RCC's interrupt pending bits. - * - * @param RCC_IT - specifies the interrupt pending bit to clear. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * - * @return none - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - *(__IO uint8_t *) INTR_BYTE3_ADDRESS = RCC_IT; -} - -/********************************************************************* - * @fn RCC_ADCCLKDutyCycleConfig - * - * @brief Configures the ADC clock high level duty cycle. - * - * @param RCC_DutyCycle - high level duty cycle. - * RCC_ADC_H_Level_Mode0 - ADC clock high-level duty cycle is mode 0. - * RCC_ADC_H_Level_Mode1 - ADC clock high-level duty cycle is mode 1. - * RCC_ADC_H_Level_Mode2 - ADC clock high-level duty cycle is mode 2. - * RCC_ADC_H_Level_Mode3 - ADC clock high-level duty cycle is mode 3. - * RCC_ADC_H_Level_Mode4 - ADC clock high-level duty cycle is mode 4. - * RCC_ADC_H_Level_Mode5 - ADC clock high-level duty cycle is mode 5. - * RCC_ADC_H_Level_Mode6 - ADC clock high-level duty cycle is mode 6. - * RCC_ADC_H_Level_Mode7 - ADC clock high-level duty cycle is mode 7. - * - * @return none - */ -void RCC_ADCCLKDutyCycleConfig(uint32_t RCC_DutyCycle) -{ - RCC->CFGR0 &= CFGR0_ADCDUTY_Reset_Mask; - RCC->CFGR0 |= RCC_DutyCycle; -} - -/********************************************************************* - * @fn RCC_HSE_LP_Cmd - * - * @brief Enables or disables low power mode of the External High Speed - * oscillator (HSI). - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_HSE_LP_Cmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<20); - } - else - { - RCC->CTLR &= ~(1<<20); - } -} - -/********************************************************************* - * @fn RCC_HSI_LP_Cmd - * - * @brief Enables or disables low power mode of the Internal High Speed - * oscillator (HSI) . - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_HSI_LP_Cmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<2); - } - else - { - RCC->CTLR &= ~(1<<2); - } -} - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_rcc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the RCC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_rcc.h" + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR0 register bit mask */ +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0x7FFF3FFF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) +#define CFGR0_ADCDUTY_Reset_Mask ((uint32_t)0x8FFFFFFF) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + + +static __I uint8_t PBHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0x08FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFB; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; + RCC->INTR = 0x009F0000; +} + +/********************************************************************* + * @fn RCC_HSEConfig + * + * @brief Configures the External High Speed oscillator (HSE). + * + * @param RCC_HSE - + * RCC_HSE_OFF - HSE oscillator OFF. + * RCC_HSE_ON - HSE oscillator ON. + * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. + * Note - + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + RCC->CTLR &= CTLR_HSEON_Reset; + RCC->CTLR &= CTLR_HSEBYP_Reset; + + switch(RCC_HSE) + { + case RCC_HSE_ON: + RCC->CTLR |= CTLR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_WaitForHSEStartUp + * + * @brief Waits for HSE start-up. + * + * @return READY - HSE oscillator is stable and ready to use. + * NoREADY - HSE oscillator not yet ready. + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + + ErrorStatus status = NoREADY; + FlagStatus HSEStatus = RESET; + + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = READY; + } + else + { + status = NoREADY; + } + + return (status); +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<0); + } + else + { + RCC->CTLR &= ~(1<<0); + } +} + +/********************************************************************* + * @fn RCC_PLLConfig + * + * @brief Configures the PLL clock source and multiplication factor. + * + * @param RCC_PLLSource - specifies the PLL entry clock source. + * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 + * selected as PLL clock entry. + * RCC_PLLSource_HSE_Div1 - HSI oscillator clock as PLL clock + * entry. + * RCC_PLLSource_HSE_Div2 - HSI oscillator clock divided by 2 + * as PLL clock entry. + * RCC_PLLMul - specifies the PLL multiplication factor. + * This parameter can be RCC_PLLMul_x where x:[2,16]. + * RCC_PLLMul_2 + * RCC_PLLMul_3 + * RCC_PLLMul_4 + * RCC_PLLMul_5 + * RCC_PLLMul_6 + * RCC_PLLMul_7 + * RCC_PLLMul_8 + * RCC_PLLMul_9 + * RCC_PLLMul_10 + * RCC_PLLMul_11 + * RCC_PLLMul_12 + * RCC_PLLMul_13 + * RCC_PLLMul_14 + * RCC_PLLMul_15 + * RCC_PLLMul_16 + * RCC_PLLMul_18 + * + * @return none + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + + tmpreg &= CFGR0_PLL_Mask; + tmpreg |= RCC_PLLSource | RCC_PLLMul; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLLCmd + * + * @brief Enables or disables the PLL. + * Note-The PLL can not be disabled if it is used as system clock. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<24); + } + else + { + RCC->CTLR &= ~(1<<24); + } +} + +/********************************************************************* + * @fn RCC_SYSCLKConfig + * + * @brief Configures the system clock (SYSCLK). + * + * @param RCC_SYSCLKSource - specifies the clock source used as system clock. + * RCC_SYSCLKSource_HSI - HSI selected as system clock. + * RCC_SYSCLKSource_HSE - HSE selected as system clock. + * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. + * + * @return none + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_SW_Mask; + tmpreg |= RCC_SYSCLKSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetSYSCLKSource + * + * @brief Returns the clock source used as system clock. + * + * @return 0x00 - HSI used as system clock. + * 0x04 - HSE used as system clock. + * 0x08 - PLL used as system clock. + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the HB clock (HCLK). + * + * @param RCC_SYSCLK - defines the HB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - HB clock = SYSCLK. + * RCC_SYSCLK_Div2 - HB clock = SYSCLK/2. + * RCC_SYSCLK_Div4 - HB clock = SYSCLK/4. + * RCC_SYSCLK_Div8 - HB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - HB clock = SYSCLK/16. + * RCC_SYSCLK_Div64 - HB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - HB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - HB clock = SYSCLK/256. + * RCC_SYSCLK_Div512 - HB clock = SYSCLK/512. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK1Config + * + * @brief Configures the Low Speed PB clock (PCLK1). + * + * @param RCC_HCLK - defines the PB1 clock divider. This clock is derived from + * the HB clock (HCLK). + * RCC_HCLK_Div1 - PB1 clock = HCLK. + * RCC_HCLK_Div2 - PB1 clock = HCLK/2. + * RCC_HCLK_Div4 - PB1 clock = HCLK/4. + * RCC_HCLK_Div8 - PB1 clock = HCLK/8. + * RCC_HCLK_Div16 - PB1 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE1_Reset_Mask; + tmpreg |= RCC_HCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK2Config + * + * @brief Configures the High Speed PB clock (PCLK2). + * + * @param RCC_HCLK - defines the PB2 clock divider. This clock is derived from + * the HB clock (HCLK). + * RCC_HCLK_Div1 - PB2 clock = HCLK. + * RCC_HCLK_Div2 - PB2 clock = HCLK/2. + * RCC_HCLK_Div4 - PB2 clock = HCLK/4. + * RCC_HCLK_Div8 - PB2 clock = HCLK/8. + * RCC_HCLK_Div16 - PB2 clock = HCLK/16. + * @return none + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE2_Reset_Mask; + tmpreg |= RCC_HCLK << 3; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_ITConfig + * + * @brief Enables or disables the specified RCC interrupts. + * + * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + *(__IO uint8_t *) INTR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + *(__IO uint8_t *) INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/********************************************************************* + * @fn RCC_USBCLKConfig + * + * @brief Configures the USB clock (USBCLK). + * + * @param RCC_USBCLKSource: specifies the USB clock source. This clock is + * derived from the PLL output. + * RCC_USBCLKSource_PLLCLK_Div1 - PLL clock selected as USB clock source(48Mhz). + * RCC_USBCLKSource_PLLCLK_Div2 - PLL clock selected as USB clock source(96MHz). + * RCC_USBCLKSource_PLLCLK_Div1_5 - PLL clock selected as USB clock source(72MHz). + * + * @return none + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + RCC->CFGR0 &= ~((uint32_t)3<<22); + RCC->CFGR0 |= RCC_USBCLKSource; +} + +/********************************************************************* + * @fn RCC_ADCCLKConfig + * + * @brief Configures the ADC clock (ADCCLK). + * + * @param ADC_CLK_S - defines the ADC clock. + * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. + * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. + * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. + * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. + * RCC_HCLK_ADC - ADC clock = HCLK. + * + * @return none + */ +void RCC_ADCCLKConfig(uint32_t ADC_CLK_S) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_ADCPRE_Reset_Mask; + tmpreg |= ADC_CLK_S; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_LSEConfig + * + * @brief Configures the External Low Speed oscillator (LSE). + * + * @param RCC_LSE - specifies the new state of the LSE. + * RCC_LSE_OFF - LSE oscillator OFF. + * RCC_LSE_ON - LSE oscillator ON. + * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. + * + * @return none + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; + + switch(RCC_LSE) + { + case RCC_LSE_ON: + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_LSICmd + * + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * Note- + * LSI can not be disabled if the IWDG is running. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_LSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->RSTSCKR |= (1<<0); + } + else{ + RCC->RSTSCKR &= ~(1<<0); + } +} + +/********************************************************************* + * @fn RCC_RTCCLKConfig + * + * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * + * @param RCC_RTCCLKSource - specifies the RTC clock source. + * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. + * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. + * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. + * Note- + * Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * + * @return none + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + RCC->BDCTLR |= RCC_RTCCLKSource; +} + +/********************************************************************* + * @fn RCC_RTCCLKCmd + * + * @brief This function must be used only after the RTC clock was selected + * using the RCC_RTCCLKConfig function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1<<15); + } + else + { + RCC->BDCTLR &= ~(1<<15); + } +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + + tmp = RCC->CFGR0 & CFGR0_SWS_Mask; + + switch (tmp) + { + case 0x00: + if(RCC->CTLR & (1<<2)) + { + RCC_Clocks->SYSCLK_Frequency = HSI_LP_VALUE; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + } + break; + + case 0x04: + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: + pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; + pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; + + pllmull = ( pllmull >> 18) + 2; + + if(pllmull == 17) pllmull = 18; + + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE) * pllmull; + } + else{ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >>1) * pllmull; + } + } + else + { + if ((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) + { + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; + + } + } + + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = PBHBPrescTable[tmp]; + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = PBHBPrescTable[tmp]; + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = PBHBPrescTable[tmp]; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + if(RCC->CFGR0 & (1<<31)) + { + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->HCLK_Frequency; + } + else + { + tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; + } +} + +/********************************************************************* + * @fn RCC_HBPeriphClockCmd + * + * @brief Enables or disables the HB peripheral clock. + * + * @param RCC_HBPeriph - specifies the HB peripheral to gates its clock. + * RCC_HBPeriph_DMA1. + * RCC_HBPeriph_SRAM. + * RCC_HBPeriph_CRC. + * RCC_HBPeriph_USBFS. + * RCC_HBPeriph_USBPD. + * Note- + * SRAM clock can be disabled only during sleep mode. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_HBPeriphClockCmd(uint32_t RCC_HBPeriph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->HBPCENR |= RCC_HBPeriph; + } + else + { + RCC->HBPCENR &= ~RCC_HBPeriph; + } +} + +/********************************************************************* + * @fn RCC_PB2PeriphClockCmd + * + * @brief Enables or disables the High Speed PB (PB2) peripheral clock. + * + * @param RCC_PB2Periph - specifies the PB2 peripheral to gates its clock. + * RCC_PB2Periph_AFIO. + * RCC_PB2Periph_GPIOA. + * RCC_PB2Periph_GPIOB. + * RCC_PB2Periph_GPIOC. + * RCC_PB2Periph_GPIOD. + * RCC_PB2Periph_ADC1. + * RCC_PB2Periph_TIM1. + * RCC_PB2Periph_SPI1. + * RCC_PB2Periph_TIM8 + * RCC_PB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_PB2PeriphClockCmd(uint32_t RCC_PB2Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->PB2PCENR |= RCC_PB2Periph; + } + else + { + RCC->PB2PCENR &= ~RCC_PB2Periph; + } +} + +/********************************************************************* + * @fn RCC_PB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed PB (PB1) peripheral clock. + * + * @param RCC_PB1Periph - specifies the PB1 peripheral to gates its clock. + * RCC_PB1Periph_TIM2. + * RCC_PB1Periph_TIM3. + * RCC_PB1Periph_TIM4. + * RCC_PB1Periph_WWDG. + * RCC_PB1Periph_SPI2. + * RCC_PB1Periph_USART2. + * RCC_PB1Periph_USART3. + * RCC_PB1Periph_USART4 + * RCC_PB1Periph_I2C1. + * RCC_PB1Periph_I2C2. + * RCC_PB1Periph_CAN1. + * RCC_PB1Periph_BKP. + * RCC_PB1Periph_PWR. + * RCC_PB1Periph_LPTIM. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PB1PeriphClockCmd(uint32_t RCC_PB1Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->PB1PCENR |= RCC_PB1Periph; + } + else + { + RCC->PB1PCENR &= ~RCC_PB1Periph; + } +} + +/********************************************************************* + * @fn RCC_PB2PeriphResetCmd + * + * @brief Forces or releases High Speed PB (PB2) peripheral reset. + * + * @param RCC_PB2Periph - specifies the PB2 peripheral to reset. + * RCC_PB2Periph_AFIO. + * RCC_PB2Periph_GPIOA. + * RCC_PB2Periph_GPIOB. + * RCC_PB2Periph_GPIOC. + * RCC_PB2Periph_GPIOD. + * RCC_PB2Periph_ADC1. + * RCC_PB2Periph_TIM1. + * RCC_PB2Periph_SPI1. + * RCC_PB2Periph_TIM8 + * RCC_PB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_PB2PeriphResetCmd(uint32_t RCC_PB2Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->PB2PRSTR |= RCC_PB2Periph; + } + else + { + RCC->PB2PRSTR &= ~RCC_PB2Periph; + } +} + +/********************************************************************* + * @fn RCC_PB1PeriphResetCmd + * + * @brief Forces or releases Low Speed PB (PB1) peripheral reset. + * + * @param RCC_PB1Periph - specifies the PB1 peripheral to reset. + * RCC_PB1Periph_TIM2. + * RCC_PB1Periph_TIM3. + * RCC_PB1Periph_TIM4. + * RCC_PB1Periph_WWDG. + * RCC_PB1Periph_SPI2. + * RCC_PB1Periph_USART2. + * RCC_PB1Periph_USART3. + * RCC_PB1Periph_USART4 + * RCC_PB1Periph_I2C1. + * RCC_PB1Periph_I2C2. + * RCC_PB1Periph_CAN1. + * RCC_PB1Periph_BKP. + * RCC_PB1Periph_PWR. + * RCC_PB1Periph_LPTIM. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PB1PeriphResetCmd(uint32_t RCC_PB1Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->PB1PRSTR |= RCC_PB1Periph; + } + else + { + RCC->PB1PRSTR &= ~RCC_PB1Periph; + } +} + +/********************************************************************* + * @fn RCC_BackupResetCmd + * + * @brief Forces or releases the Backup domain reset. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1<<16); + } + else{ + RCC->BDCTLR &= ~(1<<16); + } +} + +/******************************************************************************* +* Function Name : RCC_ClockSecuritySystemCmd +* Description : Enables or disables the Clock Security System. +* Input : NewState: ENABLE or DISABLE. +* Return : None +*******************************************************************************/ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<19); + } + else{ + RCC->CTLR &= ~(1<<19); + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * RCC_MCO_HSE - HSE oscillator clock selected. + * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_HSERDY - HSE oscillator clock ready. + * RCC_FLAG_PLLRDY - PLL clock ready. + * RCC_FLAG_LSERDY - LSE oscillator clock ready. + * RCC_FLAG_LSIRDY - LSI oscillator clock ready. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if (tmp == 1) + { + statusreg = RCC->CTLR; + } + else if (tmp == 2) + { + statusreg = RCC->BDCTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * Note- + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + +/********************************************************************* + * @fn RCC_GetITStatus + * + * @brief Checks whether the specified RCC interrupt has occurred or not. + * + * @param RCC_IT - specifies the RCC interrupt source to check. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return ITStatus - SET or RESET. + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + if ((RCC->INTR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearITPendingBit + * + * @brief Clears the RCC's interrupt pending bits. + * + * @param RCC_IT - specifies the interrupt pending bit to clear. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return none + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + *(__IO uint8_t *) INTR_BYTE3_ADDRESS = RCC_IT; +} + +/********************************************************************* + * @fn RCC_ADCCLKDutyCycleConfig + * + * @brief Configures the ADC clock high level duty cycle. + * + * @param RCC_DutyCycle - high level duty cycle. + * RCC_ADC_H_Level_Mode0 - ADC clock high-level duty cycle is mode 0. + * RCC_ADC_H_Level_Mode1 - ADC clock high-level duty cycle is mode 1. + * RCC_ADC_H_Level_Mode2 - ADC clock high-level duty cycle is mode 2. + * RCC_ADC_H_Level_Mode3 - ADC clock high-level duty cycle is mode 3. + * RCC_ADC_H_Level_Mode4 - ADC clock high-level duty cycle is mode 4. + * RCC_ADC_H_Level_Mode5 - ADC clock high-level duty cycle is mode 5. + * RCC_ADC_H_Level_Mode6 - ADC clock high-level duty cycle is mode 6. + * RCC_ADC_H_Level_Mode7 - ADC clock high-level duty cycle is mode 7. + * + * @return none + */ +void RCC_ADCCLKDutyCycleConfig(uint32_t RCC_DutyCycle) +{ + RCC->CFGR0 &= CFGR0_ADCDUTY_Reset_Mask; + RCC->CFGR0 |= RCC_DutyCycle; +} + +/********************************************************************* + * @fn RCC_HSE_LP_Cmd + * + * @brief Enables or disables low power mode of the External High Speed + * oscillator (HSE). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSE_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<20); + } + else + { + RCC->CTLR &= ~(1<<20); + } +} + +/********************************************************************* + * @fn RCC_HSI_LP_Cmd + * + * @brief Enables or disables low power mode of the Internal High Speed + * oscillator (HSI) . + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSI_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<2); + } + else + { + RCC->CTLR &= ~(1<<2); + } +} + + diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_rtc.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_rtc.c index f4d6b8e..2e59c4f 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_rtc.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_rtc.c @@ -1,281 +1,281 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_rtc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the RTC firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_rtc.h" - -/* RTC_Private_Defines */ -#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ -#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ - -/********************************************************************* - * @fn RTC_ITConfig - * - * @brief Enables or disables the specified RTC interrupts. - * - * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. - * RTC_IT_OW - Overflow interrupt - * RTC_IT_ALR - Alarm interrupt - * RTC_IT_SEC - Second interrupt - * - * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). - */ -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RTC->CTLRH |= RTC_IT; - } - else - { - RTC->CTLRH &= (uint16_t)~RTC_IT; - } -} - -/********************************************************************* - * @fn RTC_EnterConfigMode - * - * @brief Enters the RTC configuration mode. - * - * @return none - */ -void RTC_EnterConfigMode(void) -{ - RTC->CTLRL |= RTC_CTLRL_CNF; -} - -/********************************************************************* - * @fn RTC_ExitConfigMode - * - * @brief Exits from the RTC configuration mode. - * - * @return none - */ -void RTC_ExitConfigMode(void) -{ - RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); -} - -/********************************************************************* - * @fn RTC_GetCounter - * - * @brief Gets the RTC counter value - * - * @return RTC counter value - */ -uint32_t RTC_GetCounter(void) -{ - uint16_t high1 = 0, high2 = 0, low = 0; - - high1 = RTC->CNTH; - low = RTC->CNTL; - high2 = RTC->CNTH; - - if(high1 != high2) - { - return (((uint32_t)high2 << 16) | RTC->CNTL); - } - else - { - return (((uint32_t)high1 << 16) | low); - } -} - -/********************************************************************* - * @fn RTC_SetCounter - * - * @brief Sets the RTC counter value. - * - * @param CounterValue - RTC counter new value. - * - * @return RTC counter value - */ -void RTC_SetCounter(uint32_t CounterValue) -{ - RTC_EnterConfigMode(); - RTC->CNTH = CounterValue >> 16; - RTC->CNTL = (CounterValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/********************************************************************* - * @fn RTC_SetPrescaler - * - * @brief Sets the RTC prescaler value - * - * @param PrescalerValue - RTC prescaler new value - * - * @return none - */ -void RTC_SetPrescaler(uint32_t PrescalerValue) -{ - RTC_EnterConfigMode(); - RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; - RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/********************************************************************* - * @fn RTC_SetAlarm - * - * @brief Sets the RTC alarm value - * - * @param AlarmValue - RTC alarm new value - * - * @return none - */ -void RTC_SetAlarm(uint32_t AlarmValue) -{ - RTC_EnterConfigMode(); - RTC->ALRMH = AlarmValue >> 16; - RTC->ALRML = (AlarmValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/********************************************************************* - * @fn RTC_GetDivider - * - * @brief Gets the RTC divider value - * - * @return RTC Divider value - */ -uint32_t RTC_GetDivider(void) -{ - uint32_t tmp = 0x00; - tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; - tmp |= RTC->DIVL; - return tmp; -} - -/********************************************************************* - * @fn RTC_WaitForLastTask - * - * @brief Waits until last write operation on RTC registers has finished - * Note- - * This function must be called before any write to RTC registers. - * @return none - */ -void RTC_WaitForLastTask(void) -{ - while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) - { - } -} - -/********************************************************************* - * @fn RTC_WaitForSynchro - * - * @brief Waits until the RTC registers are synchronized with RTC PB clock - * Note- - * This function must be called before any read operation after an PB reset - * or an PB clock stop. - * - * @return none - */ -void RTC_WaitForSynchro(void) -{ - RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; - while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) - { - } -} - -/********************************************************************* - * @fn RTC_GetFlagStatus - * - * @brief Checks whether the specified RTC flag is set or not - * - * @param RTC_FLAG- specifies the flag to check - * RTC_FLAG_RTOFF - RTC Operation OFF flag - * RTC_FLAG_RSF - Registers Synchronized flag - * RTC_FLAG_OW - Overflow flag - * RTC_FLAG_ALR - Alarm flag - * RTC_FLAG_SEC - Second flag - * - * @return The new state of RTC_FLAG (SET or RESET) - */ -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn RTC_ClearFlag - * - * @brief Clears the RTC's pending flags - * - * @param RTC_FLAG - specifies the flag to clear - * RTC_FLAG_RSF - Registers Synchronized flag - * RTC_FLAG_OW - Overflow flag - * RTC_FLAG_ALR - Alarm flag - * RTC_FLAG_SEC - Second flag - * - * @return none - */ -void RTC_ClearFlag(uint16_t RTC_FLAG) -{ - RTC->CTLRL &= (uint16_t)~RTC_FLAG; -} - -/********************************************************************* - * @fn RTC_GetITStatus - * - * @brief Checks whether the specified RTC interrupt has occurred or not - * - * @param RTC_IT - specifies the RTC interrupts sources to check - * RTC_FLAG_OW - Overflow interrupt - * RTC_FLAG_ALR - Alarm interrupt - * RTC_FLAG_SEC - Second interrupt - * - * @return The new state of the RTC_IT (SET or RESET) - */ -ITStatus RTC_GetITStatus(uint16_t RTC_IT) -{ - ITStatus bitstatus = RESET; - - bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); - if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn RTC_ClearITPendingBit - * - * @brief Clears the RTC's interrupt pending bits - * - * @param RTC_IT - specifies the interrupt pending bit to clear - * RTC_FLAG_OW - Overflow interrupt - * RTC_FLAG_ALR - Alarm interrupt - * RTC_FLAG_SEC - Second interrupt - * - * @return none - */ -void RTC_ClearITPendingBit(uint16_t RTC_IT) -{ - RTC->CTLRL &= (uint16_t)~RTC_IT; -} - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_rtc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the RTC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_rtc.h" + +/* RTC_Private_Defines */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ + +/********************************************************************* + * @fn RTC_ITConfig + * + * @brief Enables or disables the specified RTC interrupts. + * + * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. + * RTC_IT_OW - Overflow interrupt + * RTC_IT_ALR - Alarm interrupt + * RTC_IT_SEC - Second interrupt + * + * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RTC->CTLRH |= RTC_IT; + } + else + { + RTC->CTLRH &= (uint16_t)~RTC_IT; + } +} + +/********************************************************************* + * @fn RTC_EnterConfigMode + * + * @brief Enters the RTC configuration mode. + * + * @return none + */ +void RTC_EnterConfigMode(void) +{ + RTC->CTLRL |= RTC_CTLRL_CNF; +} + +/********************************************************************* + * @fn RTC_ExitConfigMode + * + * @brief Exits from the RTC configuration mode. + * + * @return none + */ +void RTC_ExitConfigMode(void) +{ + RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); +} + +/********************************************************************* + * @fn RTC_GetCounter + * + * @brief Gets the RTC counter value + * + * @return RTC counter value + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t high1 = 0, high2 = 0, low = 0; + + high1 = RTC->CNTH; + low = RTC->CNTL; + high2 = RTC->CNTH; + + if(high1 != high2) + { + return (((uint32_t)high2 << 16) | RTC->CNTL); + } + else + { + return (((uint32_t)high1 << 16) | low); + } +} + +/********************************************************************* + * @fn RTC_SetCounter + * + * @brief Sets the RTC counter value. + * + * @param CounterValue - RTC counter new value. + * + * @return RTC counter value + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + RTC->CNTH = CounterValue >> 16; + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetPrescaler + * + * @brief Sets the RTC prescaler value + * + * @param PrescalerValue - RTC prescaler new value + * + * @return none + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + RTC_EnterConfigMode(); + RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetAlarm + * + * @brief Sets the RTC alarm value + * + * @param AlarmValue - RTC alarm new value + * + * @return none + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + RTC->ALRMH = AlarmValue >> 16; + RTC->ALRML = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_GetDivider + * + * @brief Gets the RTC divider value + * + * @return RTC Divider value + */ +uint32_t RTC_GetDivider(void) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; + tmp |= RTC->DIVL; + return tmp; +} + +/********************************************************************* + * @fn RTC_WaitForLastTask + * + * @brief Waits until last write operation on RTC registers has finished + * Note- + * This function must be called before any write to RTC registers. + * @return none + */ +void RTC_WaitForLastTask(void) +{ + while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_WaitForSynchro + * + * @brief Waits until the RTC registers are synchronized with RTC PB clock + * Note- + * This function must be called before any read operation after an PB reset + * or an PB clock stop. + * + * @return none + */ +void RTC_WaitForSynchro(void) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; + while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_GetFlagStatus + * + * @brief Checks whether the specified RTC flag is set or not + * + * @param RTC_FLAG- specifies the flag to check + * RTC_FLAG_RTOFF - RTC Operation OFF flag + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return The new state of RTC_FLAG (SET or RESET) + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearFlag + * + * @brief Clears the RTC's pending flags + * + * @param RTC_FLAG - specifies the flag to clear + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return none + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG; +} + +/********************************************************************* + * @fn RTC_GetITStatus + * + * @brief Checks whether the specified RTC interrupt has occurred or not + * + * @param RTC_IT - specifies the RTC interrupts sources to check + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return The new state of the RTC_IT (SET or RESET) + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + + bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); + if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearITPendingBit + * + * @brief Clears the RTC's interrupt pending bits + * + * @param RTC_IT - specifies the interrupt pending bit to clear + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return none + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + RTC->CTLRL &= (uint16_t)~RTC_IT; +} + + diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_spi.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_spi.c index 3ce5f96..2cd4ce6 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_spi.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_spi.c @@ -1,535 +1,536 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_spi.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the SPI firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_spi.h" -#include "ch32l103_rcc.h" - -/* SPI SPE mask */ -#define CTLR1_SPE_Set ((uint16_t)0x0040) -#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) - -/* SPI CRCNext mask */ -#define CTLR1_CRCNext_Set ((uint16_t)0x1000) - -/* SPI CRCEN mask */ -#define CTLR1_CRCEN_Set ((uint16_t)0x2000) -#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) - -/* SPI SSOE mask */ -#define CTLR2_SSOE_Set ((uint16_t)0x0004) -#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) - -/* SPI registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) - -/********************************************************************* - * @fn SPI_I2S_DeInit - * - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values. - * - * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. - * - * @return none - */ -void SPI_I2S_DeInit(SPI_TypeDef *SPIx) -{ - if(SPIx == SPI1) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_SPI1, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_SPI1, DISABLE); - } - else if(SPIx == SPI2) - { - RCC_PB1PeriphResetCmd(RCC_PB1Periph_SPI2, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_SPI2, DISABLE); - } -} - -/********************************************************************* - * @fn SPI_Init - * - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * - * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. - * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * - * @return none - */ -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - tmpreg = SPIx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - - SPIx->CTLR1 = tmpreg; - SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/********************************************************************* - * @fn SPI_StructInit - * - * @brief Fills each SPI_InitStruct member with its default value. - * - * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) -{ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/********************************************************************* - * @fn SPI_Cmd - * - * @brief Enables or disables the specified SPI peripheral. - * - * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_SPE_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_SPE_Reset; - } -} - -/********************************************************************* - * @fn SPI_I2S_ITConfig - * - * @brief Enables or disables the specified SPI interrupts. - * - * @param SPIx - where x can be - * - 1 or 2 in SPI mode. - * SPI_I2S_IT - specifies the SPI/I2S interrupt source to be - * enabled or disabled. - * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. - * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. - * SPI_I2S_IT_ERR - Error interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0; - - itpos = SPI_I2S_IT >> 4; - itmask = (uint16_t)1 << (uint16_t)itpos; - - if(NewState != DISABLE) - { - SPIx->CTLR2 |= itmask; - } - else - { - SPIx->CTLR2 &= (uint16_t)~itmask; - } -} - -/********************************************************************* - * @fn SPI_I2S_DMACmd - * - * @brief Enables or disables the SPIx DMA interface. - * - * @param SPIx - where x can be - * - 1 or 2 in SPI mode. - * SPI_I2S_DMAReq - specifies the SPI DMA transfer request to - * be enabled or disabled. - * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. - * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= SPI_I2S_DMAReq; - } - else - { - SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/********************************************************************* - * @fn SPI_I2S_SendData - * - * @brief Transmits a Data through the SPIx peripheral. - * - * @param SPIx - where x can be - * - 1 or 2 in SPI mode. - * Data - Data to be transmitted. - * - * @return none - */ -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) -{ - SPIx->DATAR = Data; -} - -/********************************************************************* - * @fn SPI_I2S_ReceiveData - * - * @brief Returns the most recent received data by the SPIx peripheral. - * - * @param SPIx - where x can be - * - 1 or 2 in SPI mode. - * Data - Data to be transmitted. - * - * @return SPIx->DATAR - The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) -{ - return SPIx->DATAR; -} - -/********************************************************************* - * @fn SPI_NSSInternalSoftwareConfig - * - * @brief Configures internally by software the NSS pin for the selected SPI. - * - * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. - * SPI_NSSInternalSoft - - * SPI_NSSInternalSoft_Set - Set NSS pin internally. - * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. - * - * @return none - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) -{ - if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; - } - else - { - SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/********************************************************************* - * @fn SPI_SSOutputCmd - * - * @brief Enables or disables the SS output for the selected SPI. - * - * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. - * NewState - new state of the SPIx SS output. - * - * @return none - */ -void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= CTLR2_SSOE_Set; - } - else - { - SPIx->CTLR2 &= CTLR2_SSOE_Reset; - } -} - -/********************************************************************* - * @fn SPI_DataSizeConfig - * - * @brief Configures the data size for the selected SPI. - * - * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. - * SPI_DataSize - specifies the SPI data size. - * SPI_DataSize_16b - Set data frame format to 16bit. - * SPI_DataSize_8b - Set data frame format to 8bit. - * - * @return none - */ -void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) -{ - SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; - SPIx->CTLR1 |= SPI_DataSize; -} - -/********************************************************************* - * @fn SPI_TransmitCRC - * - * @brief Transmit the SPIx CRC value. - * - * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. - * - * @return none - */ -void SPI_TransmitCRC(SPI_TypeDef *SPIx) -{ - SPIx->CTLR1 |= CTLR1_CRCNext_Set; -} - -/********************************************************************* - * @fn SPI_CalculateCRC - * - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * - * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. - * NewState - new state of the SPIx CRC value calculation. - * - * @return none - */ -void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_CRCEN_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_CRCEN_Reset; - } -} - -/********************************************************************* - * @fn SPI_GetCRC - * - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * - * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. - * SPI_CRC - specifies the CRC register to be read. - * SPI_CRC_Tx - Selects Tx CRC register. - * SPI_CRC_Rx - Selects Rx CRC register. - * - * @return crcreg - The selected CRC register value. - */ -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - - if(SPI_CRC != SPI_CRC_Rx) - { - crcreg = SPIx->TCRCR; - } - else - { - crcreg = SPIx->RCRCR; - } - - return crcreg; -} - -/********************************************************************* - * @fn SPI_GetCRCPolynomial - * - * @brief Returns the CRC Polynomial register value for the specified SPI. - * - * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. - * - * @return SPIx->CRCR - The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) -{ - return SPIx->CRCR; -} - -/********************************************************************* - * @fn SPI_BiDirectionalLineConfig - * - * @brief Selects the data transfer direction in bi-directional mode - * for the specified SPI. - * - * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. - * SPI_Direction - specifies the data transfer direction in - * bi-directional mode. - * SPI_Direction_Tx - Selects Tx transmission direction. - * SPI_Direction_Rx - Selects Rx receive direction. - * - * @return none - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) -{ - if(SPI_Direction == SPI_Direction_Tx) - { - SPIx->CTLR1 |= SPI_Direction_Tx; - } - else - { - SPIx->CTLR1 &= SPI_Direction_Rx; - } -} - -/********************************************************************* - * @fn SPI_I2S_GetFlagStatus - * - * @brief Checks whether the specified SPI flag is set or not. - * - * @param SPIx - where x can be - * - 1 or 2 in SPI mode. - * SPI_I2S_FLAG - specifies the SPI flag to check. - * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. - * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. - * SPI_I2S_FLAG_BSY - Busy flag. - * SPI_I2S_FLAG_OVR - Overrun flag. - * SPI_FLAG_MODF - Mode Fault flag. - * SPI_FLAG_CRCERR - CRC Error flag. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearFlag - * - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * - * @param SPIx - where x can be - * - 1 or 2 in SPI mode. - * SPI_I2S_FLAG - specifies the SPI flag to clear. - * SPI_FLAG_CRCERR - CRC Error flag. - * Note- - * - OVR (OverRun error) flag is cleared by software sequence - a read - * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). - * - MODF (Mode Fault) flag is cleared by software sequence - a read/write - * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). - * @return FlagStatus - SET or RESET. - */ -void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; -} - -/********************************************************************* - * @fn SPI_I2S_GetITStatus - * - * @brief Checks whether the specified SPI interrupt has occurred or not. - * - * @param SPIx - where x can be - * - 1 or 2 in SPI mode. - * SPI_I2S_IT - specifies the SPI interrupt source to check.. - * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. - * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. - * SPI_I2S_IT_OVR - Overrun interrupt. - * SPI_IT_MODF - Mode Fault interrupt. - * SPI_IT_CRCERR - CRC Error interrupt. - * - * @return FlagStatus - SET or RESET. - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - itmask = SPI_I2S_IT >> 4; - itmask = 0x01 << itmask; - enablestatus = (SPIx->CTLR2 & itmask); - - if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearITPendingBit - * - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * - * @param SPIx - where x can be - * - 1 or 2 in SPI mode. - * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. - * SPI_IT_CRCERR - CRC Error interrupt. - * Note- - * - OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence - a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). - * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable - * the SPI). - * - * @return none - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - SPIx->STATR = (uint16_t)~itpos; -} - -/********************************************************************* - * @fn SPI_HighSpeedRead_Cmd - * - * @brief Enables or disables the SPI high speed read mode. - * Note - - * Read enable in SPI high-speed mode (CLK is more than - * or equal to 36MHz). This mode is valid only when clock - * is divided by 2 (BR in CTLR1 = 000). - * - * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_HighSpeedRead_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->HSCR |= (1 << 0); - } - else - { - SPIx->HSCR &= ~(1 << 0); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_spi.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/05 + * Description : This file provides all the SPI firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_spi.h" +#include "ch32l103_rcc.h" + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_SPI1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_SPI1, DISABLE); + } + else if(SPIx == SPI2) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_SPI2, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_SPI2, DISABLE); + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * When using SPI slave mode to send data, the CPOL bit should be set to 1. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI interrupts. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIx DMA interface. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_DMAReq - specifies the SPI DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg - The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI flag is set or not. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * Note- + * - OVR (OverRun error) flag is cleared by software sequence - a read + * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence - a read/write + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). + * @return FlagStatus - SET or RESET. + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * + * @return FlagStatus - SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1 or 2 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * Note- + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence - a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable + * the SPI). + * + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} + +/********************************************************************* + * @fn SPI_HighSpeedRead_Cmd + * + * @brief Enables or disables the SPI high speed read mode. + * Note - + * Read enable in SPI high-speed mode (CLK is more than + * or equal to 36MHz). This mode is valid only when clock + * is divided by 2 (BR in CTLR1 = 000). + * + * @param SPIx - where x can be 1 or 2 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_HighSpeedRead_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->HSCR |= (1 << 0); + } + else + { + SPIx->HSCR &= ~(1 << 0); + } +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_tim.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_tim.c index b16233f..0098d88 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_tim.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_tim.c @@ -1,2412 +1,2412 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_tim.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the TIM firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_tim.h" -#include "ch32l103_rcc.h" - -/* TIM registers bit mask */ -#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) -#define CHCTLR_Offset ((uint16_t)0x0018) -#define CCER_CCE_Set ((uint16_t)0x0001) -#define CCER_CCNE_Set ((uint16_t)0x0004) - -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/********************************************************************* - * @fn TIM_DeInit - * - * @brief Deinitializes the TIMx peripheral registers to their default - * reset values. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * - * @return none - */ -void TIM_DeInit(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM1) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_TIM1, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_TIM1, DISABLE); - } - else if(TIMx == TIM2) - { - RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM2, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM2, DISABLE); - } - else if(TIMx == TIM3) - { - RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM3, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM3, DISABLE); - } - else if(TIMx == TIM4) - { - RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM4, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM4, DISABLE); - } -} - -/********************************************************************* - * @fn TIM_TimeBaseInit - * - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef - * structure. - * - * @return none - */ -void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - tmpcr1 = TIMx->CTLR1; - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) - { - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - - TIMx->CTLR1 = tmpcr1; - - if(TIMx == TIM4) TIMx->ATRLR_TIM4 = TIM_TimeBaseInitStruct->TIM_Period; - else TIMx->ATRLR = (uint16_t)TIM_TimeBaseInitStruct->TIM_Period; - - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if((TIMx == TIM1)) - { - TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; -} - -/********************************************************************* - * @fn TIM_OC1Init - * - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1)) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); - - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - if(TIMx == TIM4) TIMx->CH1CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; - else TIMx->CH1CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2Init - * - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1)) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - if(TIMx == TIM4) TIMx->CH2CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; - else TIMx->CH2CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3Init - * - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1)) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - if(TIMx == TIM4) TIMx->CH3CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; - else TIMx->CH3CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4Init - * - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1)) - { - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - if(TIMx == TIM4) TIMx->CH4CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; - else TIMx->CH4CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ICInit - * - * @brief IInitializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_PWMIConfig - * - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external - * PWM signal. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - - if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_BDTRConfig - * - * @brief Configures the: Break feature, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable). - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/********************************************************************* - * @fn TIM_TimeBaseStructInit - * - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * - * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. - * - * @return none - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/********************************************************************* - * @fn TIM_OCStructInit - * - * @brief Fills each TIM_OCInitStruct member with its default value. - * - * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/********************************************************************* - * @fn TIM_ICStructInit - * - * @brief Fills each TIM_ICInitStruct member with its default value. - * - * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/********************************************************************* - * @fn TIM_BDTRStructInit - * - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * - * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/********************************************************************* - * @fn TIM_Cmd - * - * @brief Enables or disables the specified TIM peripheral. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_CEN; - } - else - { - TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); - } -} - -/********************************************************************* - * @fn TIM_CtrlPWMOutputs - * - * @brief Enables or disables the TIM peripheral Main Outputs. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->BDTR |= TIM_MOE; - } - else - { - TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); - } -} - -/********************************************************************* - * @fn TIM_ITConfig - * - * @brief Enables or disables the specified TIM interrupts. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->DMAINTENR |= TIM_IT; - } - else - { - TIMx->DMAINTENR &= (uint16_t)~TIM_IT; - } -} - -/******************************************************************************* - * @fn TIM_GenerateEvent - * - * @brief Configures the TIMx event to be generate by software. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_EventSource - specifies the event source. - * TIM_EventSource_Update - Timer update Event source. - * TIM_EventSource_CC1 - Timer Capture Compare 1 Event source. - * TIM_EventSource_CC2 - Timer Capture Compare 2 Event source. - * TIM_EventSource_CC3 - Timer Capture Compare 3 Event source. - * TIM_EventSource_CC4 - Timer Capture Compare 4 Event source. - * TIM_EventSource_COM - Timer COM event source. - * TIM_EventSource_Trigger - Timer Trigger Event source. - * TIM_EventSource_Break - Timer Break event source. - * - * @return None - */ -void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) -{ - TIMx->SWEVGR = TIM_EventSource; -} - -/********************************************************************* - * @fn TIM_DMAConfig - * - * @brief Configures the TIMx's DMA interface. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_DMABase - DMA Base address. - * TIM_DMABase_CR. - * TIM_DMABase_CR2. - * TIM_DMABase_SMCR. - * TIM_DMABase_DIER. - * TIM1_DMABase_SR. - * TIM_DMABase_EGR. - * TIM_DMABase_CCMR1. - * TIM_DMABase_CCMR2. - * TIM_DMABase_CCER. - * TIM_DMABase_CNT. - * TIM_DMABase_PSC. - * TIM_DMABase_CCR1. - * TIM_DMABase_CCR2. - * TIM_DMABase_CCR3. - * TIM_DMABase_CCR4. - * TIM_DMABase_BDTR. - * TIM_DMABase_DCR. - * TIM_DMABurstLength - DMA Burst length. - * TIM_DMABurstLength_1Transfer. - * TIM_DMABurstLength_18Transfers. - * - * @return none - */ -void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; -} - -/********************************************************************* - * @fn TIM_DMACmd - * - * @brief Enables or disables the TIMx's DMA Requests. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_DMASource - specifies the DMA Request sources. - * TIM_DMA_Update - TIM update Interrupt source. - * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. - * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. - * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. - * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. - * TIM_DMA_COM - TIM Commutation DMA source. - * TIM_DMA_Trigger - TIM Trigger DMA source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->DMAINTENR |= TIM_DMASource; - } - else - { - TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; - } -} - -/********************************************************************* - * @fn TIM_InternalClockConfig - * - * @brief Configures the TIMx internal Clock. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * - * @return none - */ -void TIM_InternalClockConfig(TIM_TypeDef *TIMx) -{ - TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); -} - -/********************************************************************* - * @fn TIM_ITRxExternalClockConfig - * - * @brief Configures the TIMx Internal Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_InputTriggerSource: Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * - * @return none - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_TIxExternalClockConfig - * - * @brief Configures the TIMx Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_TIxExternalCLKSource - Trigger source. - * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. - * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. - * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. - * TIM_ICPolarity - specifies the TIx Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_DMA_COM - TIM Commutation DMA source. - * TIM_DMA_Trigger - TIM Trigger DMA source. - * ICFilter - specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_ETRClockMode1Config - * - * @brief Configures the External clock Mode1. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_SlaveMode_External1; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_TS_ETRF; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_ETRClockMode2Config - * - * @brief Configures the External clock Mode2. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - TIMx->SMCFGR |= TIM_ECE; -} - -/********************************************************************* - * @fn TIM_ETRConfig - * - * @brief Configures the TIMx External Trigger (ETR). - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= SMCFGR_ETR_Mask; - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_PrescalerConfig - * - * @brief Configures the TIMx Prescaler. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * Prescaler - specifies the Prescaler Register value. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. - * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. - * - * @return none - */ -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - TIMx->PSC = Prescaler; - TIMx->SWEVGR = TIM_PSCReloadMode; -} - -/********************************************************************* - * @fn TIM_CounterModeConfig - * - * @brief Specifies the TIMx Counter Mode to be used. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_CounterMode - specifies the Counter Mode to be used. - * TIM_CounterMode_Up - TIM Up Counting Mode. - * TIM_CounterMode_Down - TIM Down Counting Mode. - * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. - * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. - * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. - * - * @return none - */ -void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - tmpcr1 = TIMx->CTLR1; - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= TIM_CounterMode; - TIMx->CTLR1 = tmpcr1; -} - -/********************************************************************* - * @fn TIM_SelectInputTrigger - * - * @brief Selects the Input Trigger source. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_InputTriggerSource - The Input Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * TIM_TS_TI1F_ED - TI1 Edge Detector. - * TIM_TS_TI1FP1 - Filtered Timer Input 1. - * TIM_TS_TI2FP2 - Filtered Timer Input 2. - * TIM_TS_ETRF - External Trigger input. - * - * @return none - */ -void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_InputTriggerSource; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_EncoderInterfaceConfig - * - * @brief Configures the TIMx Encoder Interface. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_EncoderMode - specifies the TIMx Encoder Mode. - * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending - * on TI2FP2 level. - * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending - * on TI1FP1 level. - * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and - * TI2FP2 edges depending. - * TIM_IC1Polarity - specifies the IC1 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TTIM_ICPolarity_Rising - IC Rising edge. - * TIM_IC2Polarity - specifies the IC2 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TIM_ICPolarity_Rising - IC Rising edge. - * - * @return none - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_EncoderMode; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); - tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; - tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - TIMx->SMCFGR = tmpsmcr; - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ForcedOC1Config - * - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC1REF. - * TIM_ForcedAction_InActive - Force inactive level on OC1REF. - * - * @return none - */ -void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); - tmpccmr1 |= TIM_ForcedAction; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC2Config - * - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC2REF. - * TIM_ForcedAction_InActive - Force inactive level on OC2REF. - * - * @return none - */ -void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC3Config - * - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC3REF. - * TIM_ForcedAction_InActive - Force inactive level on OC3REF. - * - * @return none - */ -void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); - tmpccmr2 |= TIM_ForcedAction; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ForcedOC4Config - * - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC4REF. - * TIM_ForcedAction_InActive - Force inactive level on OC4REF. - * - * @return none - */ -void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ARRPreloadConfig - * - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_ARPE; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); - } -} - -/********************************************************************* - * @fn TIM_SelectCOM - * - * @brief Selects the TIM peripheral Commutation event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCUS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); - } -} - -/********************************************************************* - * @fn TIM_SelectCCDMA - * - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCDS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); - } -} - -/********************************************************************* - * @fn TIM_CCPreloadControl - * - * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. - * reset values. - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCPC; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); - } -} - -/********************************************************************* - * @fn TIM_OC1PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); - tmpccmr1 |= TIM_OCPreload; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC2PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC3PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); - tmpccmr2 |= TIM_OCPreload; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC4PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC1FastConfig - * - * @brief Configures the TIMx Output Compare 1 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); - tmpccmr1 |= TIM_OCFast; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC2FastConfig - * - * @brief Configures the TIMx Output Compare 2 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC3FastConfig - * - * @brief Configures the TIMx Output Compare 3 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); - tmpccmr2 |= TIM_OCFast; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC4FastConfig - * - * @brief Configures the TIMx Output Compare 4 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC1Ref - * - * @brief Clears or safeguards the OCREF1 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); - tmpccmr1 |= TIM_OCClear; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC2Ref - * - * @brief Clears or safeguards the OCREF2 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC3Ref - * - * @brief Clears or safeguards the OCREF3 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); - tmpccmr2 |= TIM_OCClear; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC4Ref - * - * @brief Clears or safeguards the OCREF4 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC1PolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC1 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); - tmpccer |= TIM_OCPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC1NPolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); - tmpccer |= TIM_OCNPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2PolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC2 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2NPolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3PolarityConfig - * - * @brief Configures the TIMx Channel 3 polarity. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3NPolarityConfig - * - * @brief Configures the TIMx Channel 3N polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC2N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4PolarityConfig - * - * @brief Configures the TIMx Channel 4 polarity. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_CCxCmd - * - * @brief Enables or disables the TIM Capture Compare Channel x. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_CCx - specifies the TIM Channel CCxE bit new state. - * TIM_CCx_Enable. - * TIM_CCx_Disable. - * - * @return none - */ -void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - tmp = CCER_CCE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_CCxNCmd - * - * @brief Enables or disables the TIM Capture Compare Channel xN. - * - * @param TIMx - where x can be 1 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. - * TIM_CCxN_Enable. - * TIM_CCxN_Disable. - * - * @return none - */ -void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - tmp = CCER_CCNE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_SelectOCxM - * - * @brief Selects the TIM Output Compare Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_OCMode - specifies the TIM Output Compare Mode. - * TIM_OCMode_Timing. - * TIM_OCMode_Active. - * TIM_OCMode_Toggle. - * TIM_OCMode_PWM1. - * TIM_OCMode_PWM2. - * TIM_ForcedAction_Active. - * TIM_ForcedAction_InActive. - * - * @return none - */ -void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - tmp = (uint32_t)TIMx; - tmp += CHCTLR_Offset; - tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp1; - - if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel >> 1); - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); - *(__IO uint32_t *)tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); - *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/********************************************************************* - * @fn TIM_UpdateDisableConfig - * - * @brief Enables or Disables the TIMx Update event. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_UDIS; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); - } -} - -/********************************************************************* - * @fn TIM_UpdateRequestConfig - * - * @brief Configures the TIMx Update Request Interrupt source. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_UpdateSource - specifies the Update source. - * TIM_UpdateSource_Regular. - * TIM_UpdateSource_Global. - * - * @return none - */ -void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) -{ - if(TIM_UpdateSource != TIM_UpdateSource_Global) - { - TIMx->CTLR1 |= TIM_URS; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); - } -} - -/********************************************************************* - * @fn TIM_SelectHallSensor - * - * @brief Enables or disables the TIMx's Hall sensor interface. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_TI1S; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); - } -} - -/********************************************************************* - * @fn TIM_SelectOnePulseMode - * - * @brief Selects the TIMx's One Pulse Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OPMode - specifies the OPM Mode to be used. - * TIM_OPMode_Single. - * TIM_OPMode_Repetitive. - * - * @return none - */ -void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); - TIMx->CTLR1 |= TIM_OPMode; -} - -/********************************************************************* - * @fn TIM_SelectOutputTrigger - * - * @brief Selects the TIMx Trigger Output Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_TRGOSource - specifies the Trigger Output source. - * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is - * used as the trigger output (TRGO). - * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the - * trigger output (TRGO). - * TIM_TRGOSource_Update - The update event is selected as the - * trigger output (TRGO). - * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse - * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). - * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). - * - * @return none - */ -void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) -{ - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); - TIMx->CTLR2 |= TIM_TRGOSource; -} - -/********************************************************************* - * @fn TIM_SelectSlaveMode - * - * @brief Selects the TIMx Slave Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_SlaveMode - specifies the Timer Slave Mode. - * TIM_SlaveMode_Reset - Rising edge of the selected trigger - * signal (TRGI) re-initializes. - * TIM_SlaveMode_Gated - The counter clock is enabled when the - * trigger signal (TRGI) is high. - * TIM_SlaveMode_Trigger - The counter starts at a rising edge - * of the trigger TRGI. - * TIM_SlaveMode_External1 - Rising edges of the selected trigger - * (TRGI) clock the counter. - * - * @return none - */ -void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) -{ - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); - TIMx->SMCFGR |= TIM_SlaveMode; -} - -/********************************************************************* - * @fn TIM_SelectMasterSlaveMode - * - * @brief Sets or Resets the TIMx Master/Slave Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. - * TIM_MasterSlaveMode_Enable - synchronization between the current - * timer and its slaves (through TRGO). - * TIM_MasterSlaveMode_Disable - No action. - * - * @return none - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) -{ - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); - TIMx->SMCFGR |= TIM_MasterSlaveMode; -} - -/********************************************************************* - * @fn TIM_SetCounter - * - * @brief Sets the TIMx Counter Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Counter - specifies the Counter register new value. - * - * @return none - */ -void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) -{ - if(TIMx == TIM4) TIMx->CNT_TIM4 = Counter; - else TIMx->CNT = (uint16_t)Counter; -} - -/********************************************************************* - * @fn TIM_SetAutoreload - * - * @brief Sets the TIMx Autoreload Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Autoreload - specifies the Autoreload register new value. - * - * @return none - */ -void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload) -{ - if(TIMx == TIM4) TIMx->ATRLR_TIM4 = Autoreload; - else TIMx->ATRLR = (uint16_t)Autoreload; -} - -/********************************************************************* - * @fn TIM_SetCompare1 - * - * @brief Sets the TIMx Capture Compare1 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1) -{ - if(TIMx == TIM4) TIMx->CH1CVR_TIM4 = Compare1; - else TIMx->CH1CVR = (uint16_t)Compare1; -} - -/********************************************************************* - * @fn TIM_SetCompare2 - * - * @brief Sets the TIMx Capture Compare2 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2) -{ - if(TIMx == TIM4) TIMx->CH2CVR_TIM4 = Compare2; - else TIMx->CH2CVR = (uint16_t)Compare2; -} - -/********************************************************************* - * @fn TIM_SetCompare3 - * - * @brief Sets the TIMx Capture Compare3 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3) -{ - if(TIMx == TIM4) TIMx->CH3CVR_TIM4 = Compare3; - else TIMx->CH3CVR = (uint16_t)Compare3; -} - -/********************************************************************* - * @fn TIM_SetCompare4 - * - * @brief Sets the TIMx Capture Compare4 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4) -{ - if(TIMx == TIM4) TIMx->CH4CVR_TIM4 = Compare4; - else TIMx->CH4CVR = (uint16_t)Compare4; -} - -/********************************************************************* - * @fn TIM_SetIC1Prescaler - * - * @brief Sets the TIMx Input Capture 1 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); - TIMx->CHCTLR1 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC2Prescaler - * - * @brief Sets the TIMx Input Capture 2 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); - TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetIC3Prescaler - * - * @brief Sets the TIMx Input Capture 3 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); - TIMx->CHCTLR2 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC4Prescaler - * - * @brief Sets the TIMx Input Capture 4 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); - TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetClockDivision - * - * @brief Sets the TIMx Clock Division value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_CKD - specifies the clock division value. - * TIM_CKD_DIV1 - TDTS = Tck_tim. - * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. - * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. - * - * @return none - */ -void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); - TIMx->CTLR1 |= TIM_CKD; -} - -/********************************************************************* - * @fn TIM_GetCapture1 - * - * @brief Gets the TIMx Input Capture 1 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH1CVR - Capture Compare 1 Register value. - */ -uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM4) return TIMx->CH1CVR_TIM4; - else return TIMx->CH1CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture2 - * - * @brief Gets the TIMx Input Capture 2 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH2CVR - Capture Compare 2 Register value. - */ -uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM4) return TIMx->CH2CVR_TIM4; - else return TIMx->CH2CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture3 - * - * @brief Gets the TIMx Input Capture 3 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH3CVR - Capture Compare 3 Register value. - */ -uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM4) return TIMx->CH3CVR_TIM4; - else return TIMx->CH3CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture4 - * - * @brief Gets the TIMx Input Capture 4 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH4CVR - Capture Compare 4 Register value. - */ -uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM4) return TIMx->CH4CVR_TIM4; - else return TIMx->CH4CVR; -} - -/********************************************************************* - * @fn TIM_GetCounter - * - * @brief Gets the TIMx Counter value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CNT - Counter Register value. - */ -uint32_t TIM_GetCounter(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM4) return TIMx->CNT_TIM4; - else return TIMx->CNT; -} - -/********************************************************************* - * @fn TIM_GetPrescaler - * - * @brief Gets the TIMx Prescaler value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->PSC - Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) -{ - return TIMx->PSC; -} - -/********************************************************************* - * @fn TIM_GetFlagStatus - * - * @brief Checks whether the specified TIM flag is set or not. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return none - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - - if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearFlag - * - * @brief Clears the TIMx's pending flags. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return none - */ -void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - TIMx->INTFR = (uint16_t)~TIM_FLAG; -} - -/********************************************************************* - * @fn TIM_GetITStatus - * - * @brief Checks whether the TIM interrupt has occurred or not. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - - itstatus = TIMx->INTFR & TIM_IT; - - itenable = TIMx->DMAINTENR & TIM_IT; - if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearITPendingBit - * - * @brief Clears the TIMx's interrupt pending bits. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - TIMx->INTFR = (uint16_t)~TIM_IT; -} - -/********************************************************************* - * @fn TI1_Config - * - * @brief Configure the TI1 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI2_Config - * - * @brief Configure the TI2 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI3_Config - * - * @brief Configure the TI3 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI4_Config - * - * @brief Configure the TI4 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_CaptureLevelIndicate_Cmd - * - * @brief Enables or disables the TIMx Capture Level Indicate function. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CaptureLevelIndicate_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= (1 << 15); - } - else - { - TIMx->CTLR1 &= ~(1 << 15); - } -} - -/********************************************************************* - * @fn TIM_CaptureModeConfig - * - * @brief Configures the TIMx capture mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_CaptureMode - the TIMx capture mode. - * TIM_Capture_Mode0 - When the counter overflows, capture count - * as actual count value. - * TIM_Capture_Mode1 - When the counter overflows, capture count - * as 0xFFFF. - * - * @return none - */ -void TIM_CaptureModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CaptureMode) -{ - TIMx->CTLR1 &= ~(TIM_Capture_Mode1); - - if(TIM_CaptureMode == TIM_Capture_Mode1) - { - TIMx->CTLR1 |= TIM_Capture_Mode1; - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_tim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the TIM firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_tim.h" +#include "ch32l103_rcc.h" + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_TIM1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM2, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM2, DISABLE); + } + else if(TIMx == TIM3) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM3, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM3, DISABLE); + } + else if(TIMx == TIM4) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM4, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM4, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + + TIMx->CTLR1 = tmpcr1; + + if(TIMx == TIM4) TIMx->ATRLR_TIM4 = TIM_TimeBaseInitStruct->TIM_Period; + else TIMx->ATRLR = (uint16_t)TIM_TimeBaseInitStruct->TIM_Period; + + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if((TIMx == TIM1)) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + if(TIMx == TIM4) TIMx->CH1CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; + else TIMx->CH1CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + if(TIMx == TIM4) TIMx->CH2CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; + else TIMx->CH2CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + if(TIMx == TIM4) TIMx->CH3CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; + else TIMx->CH3CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1)) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + if(TIMx == TIM4) TIMx->CH4CVR_TIM4 = TIM_OCInitStruct->TIM_Pulse; + else TIMx->CH4CVR = (uint16_t)TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +/******************************************************************************* + * @fn TIM_GenerateEvent + * + * @brief Configures the TIMx event to be generate by software. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_EventSource - specifies the event source. + * TIM_EventSource_Update - Timer update Event source. + * TIM_EventSource_CC1 - Timer Capture Compare 1 Event source. + * TIM_EventSource_CC2 - Timer Capture Compare 2 Event source. + * TIM_EventSource_CC3 - Timer Capture Compare 3 Event source. + * TIM_EventSource_CC4 - Timer Capture Compare 4 Event source. + * TIM_EventSource_COM - Timer COM event source. + * TIM_EventSource_Trigger - Timer Trigger Event source. + * TIM_EventSource_Break - Timer Break event source. + * + * @return None + */ +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMABase - DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values. + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 4 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + if(TIMx == TIM4) TIMx->CNT_TIM4 = Counter; + else TIMx->CNT = (uint16_t)Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload) +{ + if(TIMx == TIM4) TIMx->ATRLR_TIM4 = Autoreload; + else TIMx->ATRLR = (uint16_t)Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1) +{ + if(TIMx == TIM4) TIMx->CH1CVR_TIM4 = Compare1; + else TIMx->CH1CVR = (uint16_t)Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2) +{ + if(TIMx == TIM4) TIMx->CH2CVR_TIM4 = Compare2; + else TIMx->CH2CVR = (uint16_t)Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3) +{ + if(TIMx == TIM4) TIMx->CH3CVR_TIM4 = Compare3; + else TIMx->CH3CVR = (uint16_t)Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4) +{ + if(TIMx == TIM4) TIMx->CH4CVR_TIM4 = Compare4; + else TIMx->CH4CVR = (uint16_t)Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CH1CVR_TIM4; + else return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CH2CVR_TIM4; + else return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture3 + * + * @brief Gets the TIMx Input Capture 3 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH3CVR - Capture Compare 3 Register value. + */ +uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CH3CVR_TIM4; + else return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CH4CVR_TIM4; + else return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint32_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM4) return TIMx->CNT_TIM4; + else return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CaptureLevelIndicate_Cmd + * + * @brief Enables or disables the TIMx Capture Level Indicate function. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CaptureLevelIndicate_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= (1 << 15); + } + else + { + TIMx->CTLR1 &= ~(1 << 15); + } +} + +/********************************************************************* + * @fn TIM_CaptureModeConfig + * + * @brief Configures the TIMx capture mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_CaptureMode - the TIMx capture mode. + * TIM_Capture_Mode0 - When the counter overflows, capture count + * as actual count value. + * TIM_Capture_Mode1 - When the counter overflows, capture count + * as 0xFFFF. + * + * @return none + */ +void TIM_CaptureModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CaptureMode) +{ + TIMx->CTLR1 &= ~(TIM_Capture_Mode1); + + if(TIM_CaptureMode == TIM_Capture_Mode1) + { + TIMx->CTLR1 |= TIM_Capture_Mode1; + } +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_usart.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_usart.c index 07d0dca..c05f661 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_usart.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_usart.c @@ -1,816 +1,816 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_usart.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the USART firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_usart.h" -#include "ch32l103_rcc.h" - -/* USART_Private_Defines */ -#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ -#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ - -#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ - -#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ -#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ -#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ -#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ - -#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ -#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ - -#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ -#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ -#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ - -#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ -#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ - -#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ -#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ - -#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ -#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ - -#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ -#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ - -#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ -#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ -#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ -#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ -#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ - -/* USART OverSampling-8 Mask */ -#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ -#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ - -/* USART One Bit Sampling Mask */ -#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ -#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ - -/********************************************************************* - * @fn USART_DeInit - * - * @brief Deinitializes the USARTx peripheral registers to their default - * reset values. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the UART peripheral. - * - * @return none - */ -void USART_DeInit(USART_TypeDef *USARTx) -{ - if(USARTx == USART1) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART1, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART1, DISABLE); - } - else if(USARTx == USART2) - { - RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART2, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART2, DISABLE); - } - else if(USARTx == USART3) - { - RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART3, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART3, DISABLE); - } - else if(USARTx == USART4) - { - RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART4, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART4, DISABLE); - } -} - -/********************************************************************* - * @fn USART_Init - * - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the UART peripheral. - * USART_InitStruct - pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified - * USART peripheral. - * - * @return none - */ -void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) -{ - uint32_t tmpreg = 0x00, PBclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - uint32_t usartxbase = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - - if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - } - - usartxbase = (uint32_t)USARTx; - tmpreg = USARTx->CTLR2; - tmpreg &= CTLR2_STOP_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - USARTx->CTLR2 = (uint16_t)tmpreg; - tmpreg = USARTx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - USARTx->CTLR1 = (uint16_t)tmpreg; - - tmpreg = USARTx->CTLR3; - tmpreg &= CTLR3_CLEAR_Mask; - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - USARTx->CTLR3 = (uint16_t)tmpreg; - - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if(usartxbase == USART1_BASE) - { - PBclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - PBclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) - { - integerdivider = ((25 * PBclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else - { - integerdivider = ((25 * PBclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - USARTx->BRR = (uint16_t)tmpreg; -} - -/********************************************************************* - * @fn USART_StructInit - * - * @brief Fills each USART_InitStruct member with its default value. - * - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void USART_StructInit(USART_InitTypeDef *USART_InitStruct) -{ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/********************************************************************* - * @fn USART_ClockInit - * - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * - * @return none - */ -void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - - tmpreg = USARTx->CTLR2; - tmpreg &= CTLR2_CLOCK_CLEAR_Mask; - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - USARTx->CTLR2 = (uint16_t)tmpreg; -} - -/********************************************************************* - * @fn USART_ClockStructInit - * - * @brief Fills each USART_ClockStructInit member with its default value. - * - * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * - * @return none - */ -void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/********************************************************************* - * @fn USART_Cmd - * - * @brief Enables or disables the specified USART peripheral. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_UE_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_UE_Reset; - } -} - -/********************************************************************* - * @fn USART_ITConfig - * - * @brief Enables or disables the specified USART interrupts. - * reset values. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_IT - specifies the USART interrupt sources to be enabled or disabled. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Transmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_PE - Parity Error interrupt. - * USART_IT_ERR - Error interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - - usartxbase = (uint32_t)USARTx; - usartreg = (((uint8_t)USART_IT) >> 0x05); - itpos = USART_IT & IT_Mask; - itmask = (((uint32_t)0x01) << itpos); - - if(usartreg == 0x01) - { - usartxbase += 0x0C; - } - else if(usartreg == 0x02) - { - usartxbase += 0x10; - } - else - { - usartxbase += 0x14; - } - - if(NewState != DISABLE) - { - *(__IO uint32_t *)usartxbase |= itmask; - } - else - { - *(__IO uint32_t *)usartxbase &= ~itmask; - } -} - -/********************************************************************* - * @fn USART_DMACmd - * - * @brief Enables or disables the USART DMA interface. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_DMAReq - specifies the DMA request. - * USART_DMAReq_Tx - USART DMA transmit request. - * USART_DMAReq_Rx - USART DMA receive request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= USART_DMAReq; - } - else - { - USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; - } -} - -/********************************************************************* - * @fn USART_SetAddress - * - * @brief Sets the address of the USART node. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_Address - Indicates the address of the USART node. - * - * @return none - */ -void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) -{ - USARTx->CTLR2 &= CTLR2_Address_Mask; - USARTx->CTLR2 |= USART_Address; -} - -/********************************************************************* - * @fn USART_WakeUpConfig - * - * @brief Selects the USART WakeUp method. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_WakeUp - specifies the USART wakeup method. - * USART_WakeUp_IdleLine - WakeUp by an idle line detection. - * USART_WakeUp_AddressMark - WakeUp by an address mark. - * - * @return none - */ -void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) -{ - USARTx->CTLR1 &= CTLR1_WAKE_Mask; - USARTx->CTLR1 |= USART_WakeUp; -} - -/********************************************************************* - * @fn USART_ReceiverWakeUpCmd - * - * @brief Determines if the USART is in mute mode or not. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_RWU_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_RWU_Reset; - } -} - -/********************************************************************* - * @fn USART_LINBreakDetectLengthConfig - * - * @brief Sets the USART LIN Break detection length. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_LINBreakDetectLength - specifies the LIN break detection length. - * USART_LINBreakDetectLength_10b - 10-bit break detection. - * USART_LINBreakDetectLength_11b - 11-bit break detection. - * - * @return none - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) -{ - USARTx->CTLR2 &= CTLR2_LBDL_Mask; - USARTx->CTLR2 |= USART_LINBreakDetectLength; -} - -/********************************************************************* - * @fn USART_LINCmd - * - * @brief Enables or disables the USART LIN mode. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR2 |= CTLR2_LINEN_Set; - } - else - { - USARTx->CTLR2 &= CTLR2_LINEN_Reset; - } -} - -/********************************************************************* - * @fn USART_SendData - * - * @brief Transmits single data through the USARTx peripheral. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * Data - the data to transmit. - * - * @return none - */ -void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) -{ - USARTx->DATAR = (Data & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_ReceiveData - * - * @brief Returns the most recent received data by the USARTx peripheral. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * - * @return The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef *USARTx) -{ - return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_SendBreak - * - * @brief Transmits break characters. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * - * @return none - */ -void USART_SendBreak(USART_TypeDef *USARTx) -{ - USARTx->CTLR1 |= CTLR1_SBK_Set; -} - -/********************************************************************* - * @fn USART_SetGuardTime - * - * @brief Sets the specified USART guard time. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_GuardTime - specifies the guard time. - * - * @return none - */ -void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) -{ - USARTx->GPR &= GPR_LSB_Mask; - USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/********************************************************************* - * @fn USART_SetPrescaler - * - * @brief Sets the system clock prescaler. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_Prescaler - specifies the prescaler clock. - * - * @return none - */ -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) -{ - USARTx->GPR &= GPR_MSB_Mask; - USARTx->GPR |= USART_Prescaler; -} - -/********************************************************************* - * @fn USART_SmartCardCmd - * - * @brief Enables or disables the USART Smart Card mode. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_SCEN_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_SCEN_Reset; - } -} - -/********************************************************************* - * @fn USART_SmartCardNACKCmd - * - * @brief Enables or disables NACK transmission. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_NACK_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_NACK_Reset; - } -} - -/********************************************************************* - * @fn USART_HalfDuplexCmd - * - * @brief Enables or disables the USART Half Duplex communication. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_HDSEL_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_HDSEL_Reset; - } -} - -/********************************************************************* - * @fn USART_OverSampling8Cmd - * - * @brief Enables or disables the USART's 8x oversampling mode. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * Note- - * This function has to be called before calling USART_Init() - * function in order to have correct baudrate Divider value. - * @return none - */ -void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_OVER8_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_OVER8_Reset; - } -} - -/********************************************************************* - * @fn USART_OneBitMethodCmd - * - * @brief Enables or disables the USART's one bit sampling method. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_ONEBITE_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_ONEBITE_Reset; - } -} - -/********************************************************************* - * @fn USART_IrDAConfig - * - * @brief Configures the USART's IrDA interface. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_IrDAMode - specifies the IrDA mode. - * USART_IrDAMode_LowPower. - * USART_IrDAMode_Normal. - * - * @return none - */ -void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) -{ - USARTx->CTLR3 &= CTLR3_IRLP_Mask; - USARTx->CTLR3 |= USART_IrDAMode; -} - -/********************************************************************* - * @fn USART_IrDACmd - * - * @brief Enables or disables the USART's IrDA interface. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_IREN_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_IREN_Reset; - } -} - -/********************************************************************* - * @fn USART_GetFlagStatus - * - * @brief Checks whether the specified USART flag is set or not. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_FLAG - specifies the flag to check. - * USART_FLAG_RX_BUSY - Receive data busy flag. - * USART_FLAG_CTS - CTS state detection flag. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TXE - Transmit data register empty flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * USART_FLAG_IDLE - Idle Line detection flag. - * USART_FLAG_ORE - OverRun Error flag. - * USART_FLAG_NE - Noise Error flag. - * USART_FLAG_FE - Framing Error flag. - * USART_FLAG_PE - Parity Error flag. - * - * @return bitstatus: SET or RESET - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - - - if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearFlag - * - * @brief Clears the USARTx's pending flags. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_FLAG - specifies the flag to clear. - * USART_FLAG_CTS - CTS state detection flag. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * Note- - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DATAR register (USART_ReceiveData()). - * - RXNE flag can be also cleared by a read to the USART_DATAR register - * (USART_ReceiveData()). - * - TC flag can be also cleared by software sequence: a read operation to - * USART_STATR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DATAR register (USART_SendData()). - * - TXE flag is cleared only by a write to the USART_DATAR register - * (USART_SendData()). - * @return none - */ -void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - USARTx->STATR = (uint16_t)~USART_FLAG; -} - -/********************************************************************* - * @fn USART_GetITStatus - * - * @brief Checks whether the specified USART interrupt has occurred or not. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_IT - specifies the USART interrupt source to check. - * USART_IT_CTS - CTS state detection interrupt. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Tansmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. - * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. - * USART_IT_NE - Noise Error interrupt. - * USART_IT_FE - Framing Error interrupt. - * USART_IT_PE - Parity Error interrupt. - * - * @return bitstatus - SET or RESET. - */ -ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - - usartreg = (((uint8_t)USART_IT) >> 0x05); - itmask = USART_IT & IT_Mask; - itmask = (uint32_t)0x01 << itmask; - - if(usartreg == 0x01) - { - itmask &= USARTx->CTLR1; - } - else if(usartreg == 0x02) - { - itmask &= USARTx->CTLR2; - } - else - { - itmask &= USARTx->CTLR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->STATR; - - if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearITPendingBit - * - * @brief Clears the USARTx's interrupt pending bits. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_IT - specifies the interrupt pending bit to clear. - * USART_IT_CTS - CTS state detection interrupt. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * Note- - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_STATR register - * (USART_GetITStatus()) followed by a read operation to USART_DATAR register - * (USART_ReceiveData()). - * - RXNE pending bit can be also cleared by a read to the USART_DATAR register - * (USART_ReceiveData()). - * - TC pending bit can be also cleared by software sequence: a read - * operation to USART_STATR register (USART_GetITStatus()) followed by a write - * operation to USART_DATAR register (USART_SendData()). - * - TXE pending bit is cleared only by a write to the USART_DATAR register - * (USART_SendData()). - * - * @return none - */ -void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->STATR = (uint16_t)~itmask; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_usart.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the USART firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_usart.h" +#include "ch32l103_rcc.h" + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART1, DISABLE); + } + else if(USARTx == USART2) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART2, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART2, DISABLE); + } + else if(USARTx == USART3) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART3, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART3, DISABLE); + } + else if(USARTx == USART4) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART4, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_USART4, DISABLE); + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, PBclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + PBclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + PBclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + integerdivider = ((25 * PBclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else + { + integerdivider = ((25 * PBclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_OverSampling8Cmd + * + * @brief Enables or disables the USART's 8x oversampling mode. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * Note- + * This function has to be called before calling USART_Init() + * function in order to have correct baudrate Divider value. + * @return none + */ +void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_OVER8_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_OVER8_Reset; + } +} + +/********************************************************************* + * @fn USART_OneBitMethodCmd + * + * @brief Enables or disables the USART's one bit sampling method. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_ONEBITE_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_ONEBITE_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_RX_BUSY - Receive data busy flag. + * USART_FLAG_CTS - CTS state detection flag. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return bitstatus: SET or RESET + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_CTS - CTS state detection flag. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DATAR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_STATR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DATAR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_CTS - CTS state detection interrupt. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return bitstatus - SET or RESET. + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_CTS - CTS state detection interrupt. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_STATR register + * (USART_GetITStatus()) followed by a read operation to USART_DATAR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_STATR register (USART_GetITStatus()) followed by a write + * operation to USART_DATAR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/system/CH32L10x/SRC/Peripheral/src/ch32l103_wwdg.c b/system/CH32L10x/SRC/Peripheral/src/ch32l103_wwdg.c index 566a71c..b7098dc 100644 --- a/system/CH32L10x/SRC/Peripheral/src/ch32l103_wwdg.c +++ b/system/CH32L10x/SRC/Peripheral/src/ch32l103_wwdg.c @@ -1,142 +1,142 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_wwdg.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : This file provides all the WWDG firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_wwdg.h" -#include "ch32l103_rcc.h" - -/* CTLR register bit mask */ -#define CTLR_WDGA_Set ((uint32_t)0x00000080) - -/* CFGR register bit mask */ -#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) -#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) -#define BIT_Mask ((uint8_t)0x7F) - -/********************************************************************* - * @fn WWDG_DeInit - * - * @brief Deinitializes the WWDG peripheral registers to their default reset values - * - * @return none - */ -void WWDG_DeInit(void) -{ - RCC_PB1PeriphResetCmd(RCC_PB1Periph_WWDG, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_WWDG, DISABLE); -} - -/********************************************************************* - * @fn WWDG_SetPrescaler - * - * @brief Sets the WWDG Prescaler - * - * @param WWDG_Prescaler - specifies the WWDG Prescaler - * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 - * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 - * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 - * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 - * - * @return none - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; - tmpreg |= WWDG_Prescaler; - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_SetWindowValue - * - * @brief Sets the WWDG window value - * - * @param WindowValue - specifies the window value to be compared to the - * downcounter,which must be lower than 0x80 - * - * @return none - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - tmpreg = WWDG->CFGR & CFGR_W_Mask; - - tmpreg |= WindowValue & (uint32_t)BIT_Mask; - - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_EnableIT - * - * @brief Enables the WWDG Early Wakeup interrupt(EWI) - * - * @return none - */ -void WWDG_EnableIT(void) -{ - WWDG->CFGR |= (1 << 9); -} - -/********************************************************************* - * @fn WWDG_SetCounter - * - * @brief Sets the WWDG counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * - * @return none - */ -void WWDG_SetCounter(uint8_t Counter) -{ - WWDG->CTLR = Counter & BIT_Mask; -} - -/********************************************************************* - * @fn WWDG_Enable - * - * @brief Enables WWDG and load the counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * - * @return none - */ -void WWDG_Enable(uint8_t Counter) -{ - WWDG->CTLR = CTLR_WDGA_Set | Counter; -} - -/********************************************************************* - * @fn WWDG_GetFlagStatus - * - * @brief Checks whether the Early Wakeup interrupt flag is set or not - * - * @return The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - return (FlagStatus)(WWDG->STATR); -} - -/********************************************************************* - * @fn WWDG_ClearFlag - * - * @brief Clears Early Wakeup interrupt flag - * - * @return none - */ -void WWDG_ClearFlag(void) -{ - WWDG->STATR = (uint32_t)RESET; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_wwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : This file provides all the WWDG firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_wwdg.h" +#include "ch32l103_rcc.h" + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_PB1PeriphResetCmd(RCC_PB1Periph_WWDG, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/system/CH32L10x/SRC/Startup/startup_ch32l103.S b/system/CH32L10x/SRC/Startup/startup_ch32l103.S index eef1c5b..fbe5f97 100644 --- a/system/CH32L10x/SRC/Startup/startup_ch32l103.S +++ b/system/CH32L10x/SRC/Startup/startup_ch32l103.S @@ -2,7 +2,7 @@ ;* File Name : startup_ch32l103.s ;* Author : WCH ;* Version : V1.0.0 -;* Date : 2023/11/11 +;* Date : 2024/05/06 ;* Description : CH32L103 vector table for eclipse toolchain. ;********************************************************************************* ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -87,7 +87,7 @@ _vector_base: .word LPTIM_IRQHandler /* LPTIM */ .word OPA_IRQHandler /* OPA */ .word USBPD_IRQHandler /* USBPD */ - .word TKeyWakeUp_IRQHandler /* TKey Wake Up */ + .word 0 .word USBPDWakeUp_IRQHandler /* USBPD Wake Up */ .word CMPWakeUp_IRQHandler /* CMP Wake Up */ @@ -150,7 +150,6 @@ _vector_base: .weak LPTIM_IRQHandler /* LPTIM */ .weak OPA_IRQHandler /* OPA */ .weak USBPD_IRQHandler /* USBPD */ - .weak TKeyWakeUp_IRQHandler /* TKey Wake Up */ .weak USBPDWakeUp_IRQHandler /* USBPD Wake Up */ .weak CMPWakeUp_IRQHandler /* CMP Wake Up */ @@ -211,7 +210,6 @@ DMA1_Channel8_IRQHandler: LPTIM_IRQHandler: OPA_IRQHandler: USBPD_IRQHandler: -TKeyWakeUp_IRQHandler: USBPDWakeUp_IRQHandler: CMPWakeUp_IRQHandler: 1: diff --git a/system/CH32L10x/USER/ch32l103_conf.h b/system/CH32L10x/USER/ch32l103_conf.h index 70a29b3..9dbbfa8 100644 --- a/system/CH32L10x/USER/ch32l103_conf.h +++ b/system/CH32L10x/USER/ch32l103_conf.h @@ -1,38 +1,38 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_conf.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : Library configuration file. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32L103_CONF_H -#define __CH32L103_CONF_H - -#include "ch32l103_adc.h" -#include "ch32l103_bkp.h" -#include "ch32l103_can.h" -#include "ch32l103_crc.h" -#include "ch32l103_dbgmcu.h" -#include "ch32l103_dma.h" -#include "ch32l103_exti.h" -#include "ch32l103_flash.h" -#include "ch32l103_gpio.h" -#include "ch32l103_i2c.h" -#include "ch32l103_iwdg.h" -#include "ch32l103_pwr.h" -#include "ch32l103_rcc.h" -#include "ch32l103_rtc.h" -#include "ch32l103_spi.h" -#include "ch32l103_tim.h" -#include "ch32l103_usart.h" -#include "ch32l103_wwdg.h" -#include "ch32l103_it.h" -#include "ch32l103_misc.h" -#include "ch32l103_lptim.h" -#include "ch32l103_opa.h" - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : Library configuration file. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32L103_CONF_H +#define __CH32L103_CONF_H + +#include "ch32l103_adc.h" +#include "ch32l103_bkp.h" +#include "ch32l103_can.h" +#include "ch32l103_crc.h" +#include "ch32l103_dbgmcu.h" +#include "ch32l103_dma.h" +#include "ch32l103_exti.h" +#include "ch32l103_flash.h" +#include "ch32l103_gpio.h" +#include "ch32l103_i2c.h" +#include "ch32l103_iwdg.h" +#include "ch32l103_pwr.h" +#include "ch32l103_rcc.h" +#include "ch32l103_rtc.h" +#include "ch32l103_spi.h" +#include "ch32l103_tim.h" +#include "ch32l103_usart.h" +#include "ch32l103_wwdg.h" +#include "ch32l103_it.h" +#include "ch32l103_misc.h" +#include "ch32l103_lptim.h" +#include "ch32l103_opa.h" + +#endif diff --git a/system/CH32L10x/USER/ch32l103_it.c b/system/CH32L10x/USER/ch32l103_it.c index b4040b8..192b36a 100644 --- a/system/CH32L10x/USER/ch32l103_it.c +++ b/system/CH32L10x/USER/ch32l103_it.c @@ -1,46 +1,47 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32l103_it.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : Main Interrupt Service Routines. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103_it.h" - -void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); - -/********************************************************************* - * @fn NMI_Handler - * - * @brief This function handles NMI exception. - * - * @return none - */ -void NMI_Handler(void) -{ - while (1) - { - } -} - - -/********************************************************************* - * @fn HardFault_Handler - * - * @brief This function handles Hard Fault exception. - * - * @return none - */ -void HardFault_Handler(void) -{ - while (1) - { - } -} - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32l103_it.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/10/30 + * Description : Main Interrupt Service Routines. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103_it.h" + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ + while (1) + { + } +} + + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + NVIC_SystemReset(); + while (1) + { + } +} + + diff --git a/system/CH32L10x/USER/system_ch32l103.c b/system/CH32L10x/USER/system_ch32l103.c index 4f79c42..396f3ef 100644 --- a/system/CH32L10x/USER/system_ch32l103.c +++ b/system/CH32L10x/USER/system_ch32l103.c @@ -1,754 +1,754 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : system_ch32l103.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/22 - * Description : Device Peripheral Access Layer System Source File. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32l103.h" - -/* -* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after -* reset the HSI is used as SYSCLK source). -* If none of the define below is enabled, the HSI is used as System clock source. -*/ -//#define SYSCLK_FREQ_HSE HSE_VALUE -//#define SYSCLK_FREQ_48MHz_HSE 48000000 -//#define SYSCLK_FREQ_56MHz_HSE 56000000 -//#define SYSCLK_FREQ_72MHz_HSE 72000000 -//#define SYSCLK_FREQ_96MHz_HSE 96000000 -//#define SYSCLK_FREQ_HSI HSI_VALUE -//#define SYSCLK_FREQ_48MHz_HSI 48000000 -//#define SYSCLK_FREQ_56MHz_HSI 56000000 -//#define SYSCLK_FREQ_72MHz_HSI 72000000 -// #define SYSCLK_FREQ_96MHz_HSI 96000000 -//#define SYSCLK_FREQ_HSI_LP HSI_LP_VALUE /* Baud rate support less than 62.5Kbps when using UART */ - -/* Clock Definitions */ -#ifdef SYSCLK_FREQ_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_96MHz_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_96MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_HSI_LP -uint32_t SystemCoreClock = SYSCLK_FREQ_HSI_LP; /* System Clock Frequency (Core Clock) */ -#else -uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ - -#endif - -__I uint8_t HBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - - -/* system_private_function_proto_types */ -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE -static void SetSysClockToHSE( void ); -#elif defined SYSCLK_FREQ_48MHz_HSE -static void SetSysClockTo48_HSE( void ); -#elif defined SYSCLK_FREQ_56MHz_HSE -static void SetSysClockTo56_HSE( void ); -#elif defined SYSCLK_FREQ_72MHz_HSE -static void SetSysClockTo72_HSE( void ); -#elif defined SYSCLK_FREQ_96MHz_HSE -static void SetSysClockTo96_HSE( void ); -#elif defined SYSCLK_FREQ_48MHz_HSI -static void SetSysClockTo48_HSI( void ); -#elif defined SYSCLK_FREQ_56MHz_HSI -static void SetSysClockTo56_HSI( void ); -#elif defined SYSCLK_FREQ_72MHz_HSI -static void SetSysClockTo72_HSI( void ); -#elif defined SYSCLK_FREQ_96MHz_HSI -static void SetSysClockTo96_HSI( void ); -#elif defined SYSCLK_FREQ_HSI_LP -static void SetSysClockToHSI_LP( void ); - -#endif - -/********************************************************************* - * @fn SystemInit - * - * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, - * the PLL and update the SystemCoreClock variable. - * - * @return none - */ -void SystemInit (void) -{ - RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0x08FF0000; - RCC->CTLR &= (uint32_t)0xFEF6FFFB; - RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF00FFFF; - RCC->INTR = 0x009F0000; - SetSysClock(); -} - -/********************************************************************* - * @fn SystemCoreClockUpdate - * - * @brief Update SystemCoreClock variable according to Clock Register Values. - * - * @return none - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0; - - tmp = RCC->CFGR0 & RCC_SWS; - - switch (tmp) - { - case 0x00: - if(RCC->CTLR & (1<<2)) - { - SystemCoreClock = HSI_LP_VALUE; - } - else { - SystemCoreClock = HSI_VALUE; - } - break; - case 0x04: - SystemCoreClock = HSE_VALUE; - break; - case 0x08: - pllmull = RCC->CFGR0 & RCC_PLLMULL; - pllsource = RCC->CFGR0 & RCC_PLLSRC; - pllmull = ( pllmull >> 18) + 2; - - if(pllmull == 17) pllmull = 18; - - if (pllsource == 0x00) - { - if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ - SystemCoreClock = HSI_VALUE * pllmull; - } - else{ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - } - else - { - if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) - { - SystemCoreClock = (HSE_VALUE >> 1) * pllmull; - } - else - { - SystemCoreClock = HSE_VALUE * pllmull; - } - } - - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - - tmp = HBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; - SystemCoreClock >>= tmp; -} - -/********************************************************************* - * @fn SetSysClock - * - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClock(void) -{ - GPIO_IPD_Unused(); - -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_48MHz_HSE - SetSysClockTo48_HSE(); -#elif defined SYSCLK_FREQ_56MHz_HSE - SetSysClockTo56_HSE(); -#elif defined SYSCLK_FREQ_72MHz_HSE - SetSysClockTo72_HSE(); -#elif defined SYSCLK_FREQ_96MHz_HSE - SetSysClockTo96_HSE(); -#elif defined SYSCLK_FREQ_48MHz_HSI - SetSysClockTo48_HSI(); -#elif defined SYSCLK_FREQ_56MHz_HSI - SetSysClockTo56_HSI(); -#elif defined SYSCLK_FREQ_72MHz_HSI - SetSysClockTo72_HSI(); -#elif defined SYSCLK_FREQ_96MHz_HSI - SetSysClockTo96_HSI(); -#elif defined SYSCLK_FREQ_HSI_LP - SetSysClockToHSI_LP(); - -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - * source (default after reset) - */ -} - - -#ifdef SYSCLK_FREQ_HSE - -/********************************************************************* - * @fn SetSysClockToHSE - * - * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Flash 0 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) - { - } - } - else - { - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - - /* If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_48MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo48_HSE - * - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo48_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Flash 1 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ) */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - - /* If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_56MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo56_HSE - * - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo56_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Flash 1 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ) */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - - /* If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_72MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo72_HSE - * - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo72_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Flash 1 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ) */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - - /* If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - - -#elif defined SYSCLK_FREQ_96MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo96_HSE - * - * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo96_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Flash 2 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ) */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - - /* If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_48MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo48_HSI - * - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo48_HSI(void) -{ - /* Flash 1 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; - - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - -#elif defined SYSCLK_FREQ_56MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo56_HSI - * - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo56_HSI(void) -{ - /* Flash 1 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; - - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - -#elif defined SYSCLK_FREQ_72MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo72_HSI - * - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo72_HSI(void) -{ - /* Flash 1 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; - - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - -#elif defined SYSCLK_FREQ_96MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo96_HSI - * - * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo96_HSI(void) -{ - /* Flash 2 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; - - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - -#elif defined SYSCLK_FREQ_HSI_LP - -/********************************************************************* - * @fn SetSysClockToHSI_LP - * - * @brief Sets HSI as System clock source of Low power and configure HCLK, PCLK2 and PCLK1 prescalers. - * In this mode, HSI is 1MHz and Baud rate support less than 62.5Kbps when using UART. - * - * @return none - */ -static void SetSysClockToHSI_LP(void) -{ - RCC_HSI_LP_Cmd(ENABLE); - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; - /* Low power mode HSI */ - RCC_AdjustHSICalibrationValue((*(uint8_t*)HSI_LP_TRIM_BASE)&0x1F); -} - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32l103.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/22 + * Description : Device Peripheral Access Layer System Source File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32l103.h" + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ +//#define SYSCLK_FREQ_HSE HSE_VALUE +//#define SYSCLK_FREQ_48MHz_HSE 48000000 +//#define SYSCLK_FREQ_56MHz_HSE 56000000 +//#define SYSCLK_FREQ_72MHz_HSE 72000000 +//#define SYSCLK_FREQ_96MHz_HSE 96000000 +//#define SYSCLK_FREQ_HSI HSI_VALUE +//#define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_56MHz_HSI 56000000 +//#define SYSCLK_FREQ_72MHz_HSI 72000000 +// #define SYSCLK_FREQ_96MHz_HSI 96000000 +//#define SYSCLK_FREQ_HSI_LP HSI_LP_VALUE /* Baud rate support less than 62.5Kbps when using UART */ + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_HSI_LP +uint32_t SystemCoreClock = SYSCLK_FREQ_HSI_LP; /* System Clock Frequency (Core Clock) */ +#else +uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ + +#endif + +__I uint8_t HBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE +static void SetSysClockToHSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSE +static void SetSysClockTo48_HSE( void ); +#elif defined SYSCLK_FREQ_56MHz_HSE +static void SetSysClockTo56_HSE( void ); +#elif defined SYSCLK_FREQ_72MHz_HSE +static void SetSysClockTo72_HSE( void ); +#elif defined SYSCLK_FREQ_96MHz_HSE +static void SetSysClockTo96_HSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSI +static void SetSysClockTo48_HSI( void ); +#elif defined SYSCLK_FREQ_56MHz_HSI +static void SetSysClockTo56_HSI( void ); +#elif defined SYSCLK_FREQ_72MHz_HSI +static void SetSysClockTo72_HSI( void ); +#elif defined SYSCLK_FREQ_96MHz_HSI +static void SetSysClockTo96_HSI( void ); +#elif defined SYSCLK_FREQ_HSI_LP +static void SetSysClockToHSI_LP( void ); + +#endif + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0x08FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFB; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; + RCC->INTR = 0x009F0000; + SetSysClock(); +} + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + if(RCC->CTLR & (1<<2)) + { + SystemCoreClock = HSI_LP_VALUE; + } + else { + SystemCoreClock = HSI_VALUE; + } + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if(pllmull == 17) pllmull = 18; + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ + SystemCoreClock = HSI_VALUE * pllmull; + } + else{ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + } + else + { + if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + } + + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = HBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ + GPIO_IPD_Unused(); + +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo48_HSE(); +#elif defined SYSCLK_FREQ_56MHz_HSE + SetSysClockTo56_HSE(); +#elif defined SYSCLK_FREQ_72MHz_HSE + SetSysClockTo72_HSE(); +#elif defined SYSCLK_FREQ_96MHz_HSE + SetSysClockTo96_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); +#elif defined SYSCLK_FREQ_56MHz_HSI + SetSysClockTo56_HSI(); +#elif defined SYSCLK_FREQ_72MHz_HSI + SetSysClockTo72_HSI(); +#elif defined SYSCLK_FREQ_96MHz_HSI + SetSysClockTo96_HSI(); +#elif defined SYSCLK_FREQ_HSI_LP + SetSysClockToHSI_LP(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 0 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo48_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHz) */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo56_HSE + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHz) */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo72_HSE + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHz) */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo96_HSE + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Flash 2 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHz) */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo56_HSI + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSI(void) +{ + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo72_HSI + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSI(void) +{ + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_96MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo96_HSI + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSI(void) +{ + /* Flash 2 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; + + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_HSI_LP + +/********************************************************************* + * @fn SetSysClockToHSI_LP + * + * @brief Sets HSI as System clock source of Low power and configure HCLK, PCLK2 and PCLK1 prescalers. + * In this mode, HSI is 1MHz and Baud rate support less than 62.5Kbps when using UART. + * + * @return none + */ +static void SetSysClockToHSI_LP(void) +{ + RCC_HSI_LP_Cmd(ENABLE); + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + /* Low power mode HSI */ + RCC_AdjustHSICalibrationValue((*(uint8_t*)HSI_LP_TRIM_BASE)&0x1F); +} + +#endif diff --git a/system/CH32L10x/USER/system_ch32l103.h b/system/CH32L10x/USER/system_ch32l103.h index 0143c56..3d7713a 100644 --- a/system/CH32L10x/USER/system_ch32l103.h +++ b/system/CH32L10x/USER/system_ch32l103.h @@ -1,29 +1,29 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : system_ch32l103.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/07/08 - * Description : CH32L103 Device Peripheral Access Layer System Header File. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __SYSTEM_ch32l103_H -#define __SYSTEM_ch32l103_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ - -/* System_Exported_Functions */ -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32l103.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/07/08 + * Description : CH32L103 Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_ch32l103_H +#define __SYSTEM_ch32l103_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V00x/SRC/Core/core_riscv.c b/system/CH32V00x/SRC/Core/core_riscv.c index 33bcd72..6b89b94 100644 --- a/system/CH32V00x/SRC/Core/core_riscv.c +++ b/system/CH32V00x/SRC/Core/core_riscv.c @@ -1,276 +1,276 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : core_riscv.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : RISC-V Core Peripheral Access Layer Source File - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -/* define compiler specific symbols */ -#if defined(__CC_ARM) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined(__ICCARM__) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined(__GNUC__) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined(__TASKING__) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/********************************************************************* - * @fn __get_MSTATUS - * - * @brief Return the Machine Status Register - * - * @return mstatus value - */ -uint32_t __get_MSTATUS(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mstatus": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MSTATUS - * - * @brief Set the Machine Status Register - * - * @param value - set mstatus value - * - * @return none - */ -void __set_MSTATUS(uint32_t value) -{ - __ASM volatile("csrw mstatus, %0" : : "r"(value)); -} - -/********************************************************************* - * @fn __get_MISA - * - * @brief Return the Machine ISA Register - * - * @return misa value - */ -uint32_t __get_MISA(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""misa" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MISA - * - * @brief Set the Machine ISA Register - * - * @param value - set misa value - * - * @return none - */ -void __set_MISA(uint32_t value) -{ - __ASM volatile("csrw misa, %0" : : "r"(value)); -} - -/********************************************************************* - * @fn __get_MTVEC - * - * @brief Return the Machine Trap-Vector Base-Address Register - * - * @return mtvec value - */ -uint32_t __get_MTVEC(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mtvec": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MTVEC - * - * @brief Set the Machine Trap-Vector Base-Address Register - * - * @param value - set mtvec value - * - * @return none - */ -void __set_MTVEC(uint32_t value) -{ - __ASM volatile("csrw mtvec, %0":: "r"(value)); -} - -/********************************************************************* - * @fn __get_MSCRATCH - * - * @brief Return the Machine Seratch Register - * - * @return mscratch value - */ -uint32_t __get_MSCRATCH(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mscratch" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MSCRATCH - * - * @brief Set the Machine Seratch Register - * - * @param value - set mscratch value - * - * @return none - */ -void __set_MSCRATCH(uint32_t value) -{ - __ASM volatile("csrw mscratch, %0" : : "r"(value)); -} - -/********************************************************************* - * @fn __get_MEPC - * - * @brief Return the Machine Exception Program Register - * - * @return mepc value - */ -uint32_t __get_MEPC(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mepc" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Exception Program Register - * - * @return mepc value - */ -void __set_MEPC(uint32_t value) -{ - __ASM volatile("csrw mepc, %0" : : "r"(value)); -} - -/********************************************************************* - * @fn __get_MCAUSE - * - * @brief Return the Machine Cause Register - * - * @return mcause value - */ -uint32_t __get_MCAUSE(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mcause": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Cause Register - * - * @return mcause value - */ -void __set_MCAUSE(uint32_t value) -{ - __ASM volatile("csrw mcause, %0":: "r"(value)); -} - -/********************************************************************* - * @fn __get_MVENDORID - * - * @brief Return Vendor ID Register - * - * @return mvendorid value - */ -uint32_t __get_MVENDORID(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""mvendorid": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __get_MARCHID - * - * @brief Return Machine Architecture ID Register - * - * @return marchid value - */ -uint32_t __get_MARCHID(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""marchid": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __get_MIMPID - * - * @brief Return Machine Implementation ID Register - * - * @return mimpid value - */ -uint32_t __get_MIMPID(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""mimpid": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __get_MHARTID - * - * @brief Return Hart ID Register - * - * @return mhartid value - */ -uint32_t __get_MHARTID(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""mhartid": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __get_SP - * - * @brief Return SP Register - * - * @return SP value - */ -uint32_t __get_SP(void) -{ - uint32_t result; - - __ASM volatile("mv %0,""sp": "=r"(result):); - return (result); -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.c + * Author : WCH + * Version : V1.0.1 + * Date : 2023/11/11 + * Description : RISC-V V2 Core Peripheral Access Layer Source File for CH32V003 + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined(__CC_ARM) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined(__ICCARM__) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined(__GNUC__) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined(__TASKING__) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mstatus": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile("csrw mstatus, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""misa" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile("csrw misa, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mtvec": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile("csrw mtvec, %0":: "r"(value)); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mscratch" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile("csrw mscratch, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mepc" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile("csrw mepc, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mcause": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile("csrw mcause, %0":: "r"(value)); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mvendorid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""marchid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mimpid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mhartid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile("mv %0,""sp": "=r"(result):); + return (result); +} diff --git a/system/CH32V00x/SRC/Core/core_riscv.h b/system/CH32V00x/SRC/Core/core_riscv.h index 85a4184..4e42098 100644 --- a/system/CH32V00x/SRC/Core/core_riscv.h +++ b/system/CH32V00x/SRC/Core/core_riscv.h @@ -1,377 +1,401 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : core_riscv.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : RISC-V Core Peripheral Access Layer Header File - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CORE_RISCV_H__ -#define __CORE_RISCV_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* IO definitions */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/* Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef __I uint32_t vuc32; /* Read Only */ -typedef __I uint16_t vuc16; /* Read Only */ -typedef __I uint8_t vuc8; /* Read Only */ - -typedef const uint32_t uc32; /* Read Only */ -typedef const uint16_t uc16; /* Read Only */ -typedef const uint8_t uc8; /* Read Only */ - -typedef __I int32_t vsc32; /* Read Only */ -typedef __I int16_t vsc16; /* Read Only */ -typedef __I int8_t vsc8; /* Read Only */ - -typedef const int32_t sc32; /* Read Only */ -typedef const int16_t sc16; /* Read Only */ -typedef const int8_t sc8; /* Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -#define RV_STATIC_INLINE static inline - -/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ -typedef struct{ - __I uint32_t ISR[8]; - __I uint32_t IPR[8]; - __IO uint32_t ITHRESDR; - __IO uint32_t RESERVED; - __IO uint32_t CFGR; - __I uint32_t GISR; - __IO uint8_t VTFIDR[4]; - uint8_t RESERVED0[12]; - __IO uint32_t VTFADDR[4]; - uint8_t RESERVED1[0x90]; - __O uint32_t IENR[8]; - uint8_t RESERVED2[0x60]; - __O uint32_t IRER[8]; - uint8_t RESERVED3[0x60]; - __O uint32_t IPSR[8]; - uint8_t RESERVED4[0x60]; - __O uint32_t IPRR[8]; - uint8_t RESERVED5[0x60]; - __IO uint32_t IACTR[8]; - uint8_t RESERVED6[0xE0]; - __IO uint8_t IPRIOR[256]; - uint8_t RESERVED7[0x810]; - __IO uint32_t SCTLR; -}PFIC_Type; - -/* memory mapped structure for SysTick */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t SR; - __IO uint32_t CNT; - uint32_t RESERVED0; - __IO uint32_t CMP; - uint32_t RESERVED1; -}SysTick_Type; - - -#define PFIC ((PFIC_Type *) 0xE000E000 ) -#define NVIC PFIC -#define NVIC_KEY1 ((uint32_t)0xFA050000) -#define NVIC_KEY2 ((uint32_t)0xBCAF0000) -#define NVIC_KEY3 ((uint32_t)0xBEEF0000) - -#define SysTick ((SysTick_Type *) 0xE000F000) - - -/********************************************************************* - * @fn __enable_irq - * - * @brief Enable Global Interrupt - * - * @return none - */ -RV_STATIC_INLINE void __enable_irq() -{ - uint32_t result; - - __asm volatile("csrr %0," "mstatus": "=r"(result)); - result |= 0x88; - __asm volatile ("csrw mstatus, %0" : : "r" (result) ); -} - -/********************************************************************* - * @fn __disable_irq - * - * @brief Disable Global Interrupt - * - * @return none - */ -RV_STATIC_INLINE void __disable_irq() -{ - uint32_t result; - - __asm volatile("csrr %0," "mstatus": "=r"(result)); - result &= ~0x88; - __asm volatile ("csrw mstatus, %0" : : "r" (result) ); -} - -/********************************************************************* - * @fn __NOP - * - * @brief nop - * - * @return none - */ -RV_STATIC_INLINE void __NOP() -{ - __asm volatile ("nop"); -} - -/********************************************************************* - * @fn NVIC_EnableIRQ - * - * @brief Disable Interrupt - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_DisableIRQ - * - * @brief Disable Interrupt - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_GetStatusIRQ - * - * @brief Get Interrupt Enable State - * - * @param IRQn - Interrupt Numbers - * - * @return 1 - 1: Interrupt Pending Enable - * 0 - Interrupt Pending Disable - */ -RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_GetPendingIRQ - * - * @brief Get Interrupt Pending State - * - * @param IRQn - Interrupt Numbers - * - * @return 1 - 1: Interrupt Pending Enable - * 0 - Interrupt Pending Disable - */ -RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_SetPendingIRQ - * - * @brief Set Interrupt Pending - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_ClearPendingIRQ - * - * @brief Clear Interrupt Pending - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_GetActive - * - * @brief Get Interrupt Active State - * - * @param IRQn - Interrupt Numbers - * - * @return 1 - Interrupt Active - * 0 - Interrupt No Active - */ -RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_SetPriority - * - * @brief Set Interrupt Priority - * - * @param IRQn - Interrupt Numbers - * priority: bit7 - pre-emption priority - * bit6 - subpriority - * bit[5-0] - reserved - * - * @return none - */ -RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) -{ - NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; -} - -/********************************************************************* - * @fn __WFI - * - * @brief Wait for Interrupt - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) -{ - NVIC->SCTLR &= ~(1<<3); // wfi - asm volatile ("wfi"); -} - -/********************************************************************* - * @fn __WFE - * - * @brief Wait for Events - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) -{ - uint32_t t; - - t = NVIC->SCTLR; - NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev) - NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); - asm volatile ("wfi"); - asm volatile ("wfi"); -} - -/********************************************************************* - * @fn SetVTFIRQ - * - * @brief Set VTF Interrupt - * - * @param addr - VTF interrupt service function base address. - * IRQn - Interrupt Numbers - * num - VTF Interrupt Numbers - * NewState - DISABLE or ENABLE - * - * @return none - */ -RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ - if(num > 1) return ; - - if (NewState != DISABLE) - { - NVIC->VTFIDR[num] = IRQn; - NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); - } - else{ - NVIC->VTFIDR[num] = IRQn; - NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); - } -} - -/********************************************************************* - * @fn NVIC_SystemReset - * - * @brief Initiate a system reset request - * - * @return none - */ -RV_STATIC_INLINE void NVIC_SystemReset(void) -{ - NVIC->CFGR = NVIC_KEY3|(1<<7); -} - - -/* Core_Exported_Functions */ -extern uint32_t __get_MSTATUS(void); -extern void __set_MSTATUS(uint32_t value); -extern uint32_t __get_MISA(void); -extern void __set_MISA(uint32_t value); -extern uint32_t __get_MTVEC(void); -extern void __set_MTVEC(uint32_t value); -extern uint32_t __get_MSCRATCH(void); -extern void __set_MSCRATCH(uint32_t value); -extern uint32_t __get_MEPC(void); -extern void __set_MEPC(uint32_t value); -extern uint32_t __get_MCAUSE(void); -extern void __set_MCAUSE(uint32_t value); -extern uint32_t __get_MVENDORID(void); -extern uint32_t __get_MARCHID(void); -extern uint32_t __get_MIMPID(void); -extern uint32_t __get_MHARTID(void); -extern uint32_t __get_SP(void); - -#ifdef __cplusplus -} -#endif - -#endif/* __CORE_RISCV_H__ */ - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.h + * Author : WCH + * Version : V1.0.1 + * Date : 2023/12/21 + * Description : RISC-V V2 Core Peripheral Access Layer Header File for CH32V003 + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint32_t CNT; + uint32_t RESERVED0; + __IO uint32_t CMP; + uint32_t RESERVED1; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000 ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + +#define SysTick ((SysTick_Type *) 0xE000F000) + + +/********************************************************************* + * @fn __enable_irq + * This function is only used for Machine mode. + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrs mstatus, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __disable_irq + * This function is only used for Machine mode. + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrc mstatus, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6] - Sub priority + * bit[5:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:6] - Sub priority + * bit[5:0] - Reserve + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + uint32_t t; + + t = NVIC->SCTLR; + NVIC->SCTLR |= (1<<3)|(1<<5); + NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + NVIC->SCTLR |= (1<<3); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param addr - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState) +{ + if(num > 1) return ; + + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + + +/* Core_Exported_Functions */ +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + +#ifdef __cplusplus +} +#endif + +#endif/* __CORE_RISCV_H__ */ + + + + + diff --git a/system/CH32V00x/SRC/Debug/debug.c b/system/CH32V00x/SRC/Debug/debug.c index b85c046..7b542b5 100644 --- a/system/CH32V00x/SRC/Debug/debug.c +++ b/system/CH32V00x/SRC/Debug/debug.c @@ -1,158 +1,246 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : debug.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for UART - * Printf , Delay functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -static uint8_t p_us = 0; -static uint16_t p_ms = 0; - -/********************************************************************* - * @fn Delay_Init - * - * @brief Initializes Delay Funcation. - * - * @return none - */ -void Delay_Init(void) -{ - p_us = SystemCoreClock / 8000000; - p_ms = (uint16_t)p_us * 1000; -} - -/********************************************************************* - * @fn Delay_Us - * - * @brief Microsecond Delay Time. - * - * @param n - Microsecond number. - * - * @return None - */ -void Delay_Us(uint32_t n) -{ - uint32_t i; - - SysTick->SR &= ~(1 << 0); - i = (uint32_t)n * p_us; - - SysTick->CMP = i; - SysTick->CNT = 0; - SysTick->CTLR |=(1 << 0); - - while((SysTick->SR & (1 << 0)) != (1 << 0)); - SysTick->CTLR &= ~(1 << 0); -} - -/********************************************************************* - * @fn Delay_Ms - * - * @brief Millisecond Delay Time. - * - * @param n - Millisecond number. - * - * @return None - */ -void Delay_Ms(uint32_t n) -{ - uint32_t i; - - SysTick->SR &= ~(1 << 0); - i = (uint32_t)n * p_ms; - - SysTick->CMP = i; - SysTick->CNT = 0; - SysTick->CTLR |=(1 << 0); - - while((SysTick->SR & (1 << 0)) != (1 << 0)); - SysTick->CTLR &= ~(1 << 0); -} - -/********************************************************************* - * @fn USART_Printf_Init - * - * @brief Initializes the USARTx peripheral. - * - * @param baudrate - USART communication baud rate. - * - * @return None - */ -void USART_Printf_Init(uint32_t baudrate) -{ - GPIO_InitTypeDef GPIO_InitStructure; - USART_InitTypeDef USART_InitStructure; - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - USART_InitStructure.USART_BaudRate = baudrate; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_No; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Tx; - - USART_Init(USART1, &USART_InitStructure); - USART_Cmd(USART1, ENABLE); -} - -/********************************************************************* - * @fn _write - * - * @brief Support Printf Function - * - * @param *buf - UART send Data. - * size - Data length. - * - * @return size - Data length - */ -#if 0 -__attribute__((used)) -int _write(int fd, char *buf, int size) -{ - int i; - - for(i = 0; i < size; i++){ - while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); - USART_SendData(USART1, *buf++); - } - - return size; -} -#endif -/********************************************************************* - * @fn _sbrk - * - * @brief Change the spatial position of data segment. - * - * @return size: Data length - */ -void *_sbrk(ptrdiff_t incr) -{ - extern char _end[]; - extern char _heap_end[]; - static char *curbrk = _end; - - if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) - return NULL - 1; - - curbrk += incr; - return curbrk - incr; -} - -void _fini() {} -void _init() {} - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +static uint8_t p_us = 0; +static uint16_t p_ms = 0; + +#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE00000F4) +#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE00000F8) + +/********************************************************************* + * @fn Delay_Init + * + * @brief Initializes Delay Funcation. + * + * @return none + */ +void Delay_Init(void) +{ + p_us = SystemCoreClock / 8000000; + p_ms = (uint16_t)p_us * 1000; +} + +/********************************************************************* + * @fn Delay_Us + * + * @brief Microsecond Delay Time. + * + * @param n - Microsecond number. + * + * @return None + */ +void Delay_Us(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_us; + + SysTick->CMP = i; + SysTick->CNT = 0; + SysTick->CTLR |=(1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn Delay_Ms + * + * @brief Millisecond Delay Time. + * + * @param n - Millisecond number. + * + * @return None + */ +void Delay_Ms(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_ms; + + SysTick->CMP = i; + SysTick->CNT = 0; + SysTick->CTLR |=(1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn USART_Printf_Init + * + * @brief Initializes the USARTx peripheral. + * + * @param baudrate - USART communication baud rate. + * + * @return None + */ +void USART_Printf_Init(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + +#if (DEBUG == DEBUG_UART1_NoRemap) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap1) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap1_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap2) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap2_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap3) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_FullRemap_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOC, &GPIO_InitStructure); + +#endif + + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx; + + USART_Init(USART1, &USART_InitStructure); + USART_Cmd(USART1, ENABLE); +} + +/********************************************************************* + * @fn SDI_Printf_Enable + * + * @brief Initializes the SDI printf Function. + * + * @param None + * + * @return None + */ +void SDI_Printf_Enable(void) +{ + *(DEBUG_DATA0_ADDRESS) = 0; + Delay_Init(); + Delay_Ms(1); +} + +/********************************************************************* + * @fn _write + * + * @brief Support Printf Function + * + * @param *buf - UART send Data. + * size - Data length. + * + * @return size - Data length + */ +#if 0 +__attribute__((used)) +int _write(int fd, char *buf, int size) +{ + int i = 0; + int writeSize = size; +#if (SDI_PRINT == SDI_PR_OPEN) + do + { + + /** + * data0 data1 8 bytes + * data0 The lowest byte storage length, the maximum is 7 + * + */ + + while( (*(DEBUG_DATA0_ADDRESS) != 0u)) + { + + } + + if(writeSize>7) + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + i += 7; + writeSize -= 7; + } + else + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + writeSize = 0; + } + + } while (writeSize); + +#else + + for(i = 0; i < size; i++){ + while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); + USART_SendData(USART1, *buf++); + } + + +#endif + return writeSize; +} +#endif + +/********************************************************************* + * @fn _sbrk + * + * @brief Change the spatial position of data segment. + * + * @return size: Data length + */ +__attribute__((used)) +void *_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} + +void _fini() {} +void _init() {} + + diff --git a/system/CH32V00x/SRC/Debug/debug.h b/system/CH32V00x/SRC/Debug/debug.h index f5f91c2..a522082 100644 --- a/system/CH32V00x/SRC/Debug/debug.h +++ b/system/CH32V00x/SRC/Debug/debug.h @@ -1,40 +1,52 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : debug.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for UART - * Printf , Delay functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __DEBUG_H -#define __DEBUG_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include -#include - -/* UART Printf Definition */ -#define DEBUG_UART1 1 - -/* DEBUG UATR Definition */ -#ifndef DEBUG -#define DEBUG DEBUG_UART1 -#endif - -void Delay_Init(void); -void Delay_Us(uint32_t n); -void Delay_Ms(uint32_t n); -void USART_Printf_Init(uint32_t baudrate); - -#ifdef __cplusplus -} -#endif - -#endif /* __DEBUG_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __DEBUG_H +#define __DEBUG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include +#include + +/* UART Printf Definition */ +#define DEBUG_UART1_NoRemap 1 //Tx-PD5 +#define DEBUG_UART1_Remap1 2 //Tx-PD0 +#define DEBUG_UART1_Remap2 3 //Tx-PD6 +#define DEBUG_UART1_Remap3 4 //Tx-PC0 + +/* DEBUG UATR Definition */ +#ifndef DEBUG +#define DEBUG DEBUG_UART1_NoRemap +#endif + +/* SDI Printf Definition */ +#define SDI_PR_CLOSE 0 +#define SDI_PR_OPEN 1 + +#ifndef SDI_PRINT +#define SDI_PRINT SDI_PR_CLOSE +#endif + +void Delay_Init(void); +void Delay_Us(uint32_t n); +void Delay_Ms(uint32_t n); +void USART_Printf_Init(uint32_t baudrate); +void SDI_Printf_Enable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DEBUG_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x.h index 915968b..9dfa743 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x.h @@ -1,2402 +1,2201 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : CH32V00x Device Peripheral Access Layer Header File. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_H -#define __CH32V00x_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ - -#define HSE_VALUE ((uint32_t)24000000) /* Value of the External oscillator in Hz */ - -/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x2000) /* Time out for HSE start up */ - -#define HSI_VALUE ((uint32_t)24000000) /* Value of the Internal oscillator in Hz */ - - -/* Interrupt Number Definition, according to the selected device */ -typedef enum IRQn -{ - /****** RISC-V Processor Exceptions Numbers *******************************************************/ - NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ - EXC_IRQn = 3, /* 3 Exception Interrupt */ - SysTicK_IRQn = 12, /* 12 System timer Interrupt */ - Software_IRQn = 14, /* 14 software Interrupt */ - - /****** RISC-V specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 16, /* Window WatchDog Interrupt */ - PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ - FLASH_IRQn = 18, /* FLASH global Interrupt */ - RCC_IRQn = 19, /* RCC global Interrupt */ - EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ - AWU_IRQn = 21, /* AWU global Interrupt */ - DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ - ADC_IRQn = 29, /* ADC global Interrupt */ - I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ - I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ - USART1_IRQn = 32, /* USART1 global Interrupt */ - SPI1_IRQn = 33, /* SPI1 global Interrupt */ - TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ - TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 38, /* TIM2 global Interrupt */ - -} IRQn_Type; - -#define HardFault_IRQn EXC_IRQn - -#include -#include -#include - -/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSI_Value HSI_VALUE -#define HSE_Value HSE_VALUE -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT - -/* Analog to Digital Converter */ -typedef struct -{ - __IO uint32_t STATR; - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t SAMPTR1; - __IO uint32_t SAMPTR2; - __IO uint32_t IOFR1; - __IO uint32_t IOFR2; - __IO uint32_t IOFR3; - __IO uint32_t IOFR4; - __IO uint32_t WDHTR; - __IO uint32_t WDLTR; - __IO uint32_t RSQR1; - __IO uint32_t RSQR2; - __IO uint32_t RSQR3; - __IO uint32_t ISQR; - __IO uint32_t IDATAR1; - __IO uint32_t IDATAR2; - __IO uint32_t IDATAR3; - __IO uint32_t IDATAR4; - __IO uint32_t RDATAR; - __IO uint32_t DLYR; -} ADC_TypeDef; - -/* Debug MCU */ -typedef struct -{ - __IO uint32_t CFGR0; - __IO uint32_t CFGR1; -} DBGMCU_TypeDef; - -/* DMA Controller */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t CNTR; - __IO uint32_t PADDR; - __IO uint32_t MADDR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t INTFR; - __IO uint32_t INTFCR; -} DMA_TypeDef; - -/* External Interrupt/Event Controller */ -typedef struct -{ - __IO uint32_t INTENR; - __IO uint32_t EVENR; - __IO uint32_t RTENR; - __IO uint32_t FTENR; - __IO uint32_t SWIEVR; - __IO uint32_t INTFR; -} EXTI_TypeDef; - -/* FLASH Registers */ -typedef struct -{ - __IO uint32_t ACTLR; - __IO uint32_t KEYR; - __IO uint32_t OBKEYR; - __IO uint32_t STATR; - __IO uint32_t CTLR; - __IO uint32_t ADDR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WPR; - __IO uint32_t MODEKEYR; - __IO uint32_t BOOT_MODEKEYR; -} FLASH_TypeDef; - -/* Option Bytes Registers */ -typedef struct -{ - __IO uint16_t RDPR; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRPR0; - __IO uint16_t WRPR1; -} OB_TypeDef; - -/* General Purpose I/O */ -typedef struct -{ - __IO uint32_t CFGLR; - __IO uint32_t CFGHR; - __IO uint32_t INDR; - __IO uint32_t OUTDR; - __IO uint32_t BSHR; - __IO uint32_t BCR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/* Alternate Function I/O */ -typedef struct -{ - uint32_t RESERVED0; - __IO uint32_t PCFR1; - __IO uint32_t EXTICR; -} AFIO_TypeDef; - -/* Inter Integrated Circuit Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t OADDR1; - uint16_t RESERVED2; - __IO uint16_t OADDR2; - uint16_t RESERVED3; - __IO uint16_t DATAR; - uint16_t RESERVED4; - __IO uint16_t STAR1; - uint16_t RESERVED5; - __IO uint16_t STAR2; - uint16_t RESERVED6; - __IO uint16_t CKCFGR; - uint16_t RESERVED7; -} I2C_TypeDef; - -/* Independent WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t PSCR; - __IO uint32_t RLDR; - __IO uint32_t STATR; -} IWDG_TypeDef; - -/* Power Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CSR; - __IO uint32_t AWUCSR; - __IO uint32_t AWUWR; - __IO uint32_t AWUPSC; -} PWR_TypeDef; - -/* Reset and Clock Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR0; - __IO uint32_t INTR; - __IO uint32_t APB2PRSTR; - __IO uint32_t APB1PRSTR; - __IO uint32_t AHBPCENR; - __IO uint32_t APB2PCENR; - __IO uint32_t APB1PCENR; - __IO uint32_t RESERVED0; - __IO uint32_t RSTSCKR; -} RCC_TypeDef; - -/* Serial Peripheral Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t STATR; - uint16_t RESERVED2; - __IO uint16_t DATAR; - uint16_t RESERVED3; - __IO uint16_t CRCR; - uint16_t RESERVED4; - __IO uint16_t RCRCR; - uint16_t RESERVED5; - __IO uint16_t TCRCR; - uint16_t RESERVED6; - uint32_t RESERVED7; - uint32_t RESERVED8; - __IO uint16_t HSCR; - uint16_t RESERVED9; -} SPI_TypeDef; - -/* TIM */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t SMCFGR; - uint16_t RESERVED2; - __IO uint16_t DMAINTENR; - uint16_t RESERVED3; - __IO uint16_t INTFR; - uint16_t RESERVED4; - __IO uint16_t SWEVGR; - uint16_t RESERVED5; - __IO uint16_t CHCTLR1; - uint16_t RESERVED6; - __IO uint16_t CHCTLR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ATRLR; - uint16_t RESERVED11; - __IO uint16_t RPTCR; - uint16_t RESERVED12; - __IO uint32_t CH1CVR; - __IO uint32_t CH2CVR; - __IO uint32_t CH3CVR; - __IO uint32_t CH4CVR; - __IO uint16_t BDTR; - uint16_t RESERVED13; - __IO uint16_t DMACFGR; - uint16_t RESERVED14; - __IO uint16_t DMAADR; - uint16_t RESERVED15; -} TIM_TypeDef; - -/* Universal Synchronous Asynchronous Receiver Transmitter */ -typedef struct -{ - __IO uint16_t STATR; - uint16_t RESERVED0; - __IO uint16_t DATAR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CTLR1; - uint16_t RESERVED3; - __IO uint16_t CTLR2; - uint16_t RESERVED4; - __IO uint16_t CTLR3; - uint16_t RESERVED5; - __IO uint16_t GPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/* Window WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR; - __IO uint32_t STATR; -} WWDG_TypeDef; - -/* Enhanced Registers */ -typedef struct -{ - __IO uint32_t EXTEN_CTR; -} EXTEN_TypeDef; - -/* Peripheral memory map */ -#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ - -#define APB1PERIPH_BASE (PERIPH_BASE) -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ -#define EXTEN_BASE ((uint32_t)0x40023800) - -/* Peripheral declaration */ -#define TIM2 ((TIM_TypeDef *)TIM2_BASE) -#define WWDG ((WWDG_TypeDef *)WWDG_BASE) -#define IWDG ((IWDG_TypeDef *)IWDG_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define PWR ((PWR_TypeDef *)PWR_BASE) -#define AFIO ((AFIO_TypeDef *)AFIO_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#define TIM1 ((TIM_TypeDef *)TIM1_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#define RCC ((RCC_TypeDef *)RCC_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#define OB ((OB_TypeDef *)OB_BASE) -#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) - -/******************************************************************************/ -/* Peripheral Registers Bits Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* Analog to Digital Converter */ -/******************************************************************************/ - -/******************** Bit definition for ADC_STATR register ********************/ -#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ -#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ -#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ -#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ -#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ - -/******************* Bit definition for ADC_CTLR1 register ********************/ -#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ -#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ -#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ -#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ -#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ -#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ -#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ -#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ - -#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ -#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ - -#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ -#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ -#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ - -#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ -#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ - -/******************* Bit definition for ADC_CTLR2 register ********************/ -#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ -#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ -#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ -#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ -#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ -#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ - -#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ - -#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ -#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ -#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ - -#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ -#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ -#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ -#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ - -/****************** Bit definition for ADC_SAMPTR1 register *******************/ -#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ - -/****************** Bit definition for ADC_SAMPTR2 register *******************/ -#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ - -#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ -#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ -#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ - -/****************** Bit definition for ADC_IOFR1 register *******************/ -#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_IOFR2 register *******************/ -#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_IOFR3 register *******************/ -#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_IOFR4 register *******************/ -#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_WDHTR register ********************/ -#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ - -/******************* Bit definition for ADC_WDLTR register ********************/ -#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ - -/******************* Bit definition for ADC_RSQR1 register *******************/ -#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ -#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ - -/******************* Bit definition for ADC_RSQR2 register *******************/ -#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_RSQR3 register *******************/ -#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_ISQR register *******************/ -#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ -#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ - -/******************* Bit definition for ADC_IDATAR1 register *******************/ -#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR2 register *******************/ -#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR3 register *******************/ -#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR4 register *******************/ -#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************** Bit definition for ADC_RDATAR register ********************/ -#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ -#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ - -/******************************************************************************/ -/* DMA Controller */ -/******************************************************************************/ - -/******************* Bit definition for DMA_INTFR register ********************/ -#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ -#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ -#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ -#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ -#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ -#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ -#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ -#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ -#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ -#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ -#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ -#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ -#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ -#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ -#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ -#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ -#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ -#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ -#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ -#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ -#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ -#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ -#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ -#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ -#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ -#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ -#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ -#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_INTFCR register *******************/ -#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ -#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ -#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ -#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ -#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ -#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ -#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ -#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ -#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ -#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ -#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ -#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ -#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ -#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ -#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ -#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ -#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ -#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ -#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ -#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ -#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ -#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ -#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ -#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ -#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ -#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ -#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ -#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CFGR1 register *******************/ -#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ -#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ -#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR2 register *******************/ -#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR3 register *******************/ -#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG4 register *******************/ -#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/****************** Bit definition for DMA_CFG5 register *******************/ -#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/******************* Bit definition for DMA_CFG6 register *******************/ -#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG7 register *******************/ -#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/****************** Bit definition for DMA_CNTR1 register ******************/ -#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR2 register ******************/ -#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR3 register ******************/ -#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR4 register ******************/ -#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR5 register ******************/ -#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR6 register ******************/ -#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR7 register ******************/ -#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_PADDR1 register *******************/ -#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR2 register *******************/ -#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR3 register *******************/ -#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR4 register *******************/ -#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR5 register *******************/ -#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR6 register *******************/ -#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR7 register *******************/ -#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_MADDR1 register *******************/ -#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR2 register *******************/ -#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR3 register *******************/ -#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR4 register *******************/ -#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR5 register *******************/ -#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR6 register *******************/ -#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR7 register *******************/ -#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/******************************************************************************/ -/* External Interrupt/Event Controller */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_INTENR register *******************/ -#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ -#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ -#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ -#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ -#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ -#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ -#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ -#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ -#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ -#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ - -/******************* Bit definition for EXTI_EVENR register *******************/ -#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ -#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ -#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ -#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ -#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ -#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ -#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ -#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ -#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ -#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ - -/****************** Bit definition for EXTI_RTENR register *******************/ -#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ -#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ -#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ -#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ -#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ -#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ -#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ -#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ -#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ -#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ - -/****************** Bit definition for EXTI_FTENR register *******************/ -#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ -#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ -#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ -#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ -#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ -#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ -#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ -#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ -#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ -#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ - -/****************** Bit definition for EXTI_SWIEVR register ******************/ -#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ -#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ -#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ -#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ -#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ -#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ -#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ -#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ -#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ -#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ - -/******************* Bit definition for EXTI_INTFR register ********************/ -#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ -#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ -#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ -#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ -#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ -#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ -#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ -#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ -#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ -#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ - -/******************************************************************************/ -/* FLASH and Option Bytes Registers */ -/******************************************************************************/ - -/******************* Bit definition for FLASH_ACTLR register ******************/ -#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ -#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ - -/***************** Bit definition for FLASH_OBKEYR register ****************/ -#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ - -/****************** Bit definition for FLASH_STATR register *******************/ -#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ -#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ -#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ - -/******************* Bit definition for FLASH_CTLR register *******************/ -#define FLASH_CTLR_PG ((uint16_t)0x0001) /* Programming */ -#define FLASH_CTLR_PER ((uint16_t)0x0002) /* Page Erase 1KByte*/ -#define FLASH_CTLR_MER ((uint16_t)0x0004) /* Mass Erase */ -#define FLASH_CTLR_OPTPG ((uint16_t)0x0010) /* Option Byte Programming */ -#define FLASH_CTLR_OPTER ((uint16_t)0x0020) /* Option Byte Erase */ -#define FLASH_CTLR_STRT ((uint16_t)0x0040) /* Start */ -#define FLASH_CTLR_LOCK ((uint16_t)0x0080) /* Lock */ -#define FLASH_CTLR_OPTWRE ((uint16_t)0x0200) /* Option Bytes Write Enable */ -#define FLASH_CTLR_ERRIE ((uint16_t)0x0400) /* Error Interrupt Enable */ -#define FLASH_CTLR_EOPIE ((uint16_t)0x1000) /* End of operation interrupt enable */ -#define FLASH_CTLR_PAGE_PG ((uint16_t)0x00010000) /* Page Programming 64Byte */ -#define FLASH_CTLR_PAGE_ER ((uint16_t)0x00020000) /* Page Erase 64Byte */ -#define FLASH_CTLR_BUF_LOAD ((uint16_t)0x00040000) /* Buffer Load */ -#define FLASH_CTLR_BUF_RST ((uint16_t)0x00080000) /* Buffer Reset */ - -/******************* Bit definition for FLASH_ADDR register *******************/ -#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ - -#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ -#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ -#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */ - -/****************** Bit definition for FLASH_WPR register ******************/ -#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ - -/****************** Bit definition for FLASH_RDPR register *******************/ -#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ -#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_WRPR0 register ******************/ -#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR1 register ******************/ -#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ - - -/******************************************************************************/ -/* General Purpose and Alternate Function I/O */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CFGLR register *******************/ -#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_CFGHR register *******************/ -#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_INDR register *******************/ -#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ -#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ -#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ -#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ -#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ -#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ -#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ -#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ -#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ -#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ -#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ -#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ -#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ -#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ -#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ -#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ - -/******************* Bit definition for GPIO_OUTDR register *******************/ -#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ -#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ -#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ -#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ -#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ -#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ -#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ -#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ -#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ -#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ -#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ -#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ -#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ -#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ -#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ -#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSHR register *******************/ -#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ -#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ -#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ -#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ -#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ -#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ -#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ -#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ -#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ -#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ -#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ -#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ -#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ -#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ -#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ -#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ - -#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ -#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ -#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ -#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ -#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ -#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ -#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ -#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ -#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ -#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ -#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ -#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ -#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ -#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ -#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ -#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BCR register *******************/ -#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ -#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ -#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ -#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ -#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ -#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ -#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ -#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ -#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ -#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ -#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ -#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ -#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ -#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ -#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ -#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ -#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ -#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ -#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ -#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ -#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ -#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ -#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ -#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ -#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ -#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ -#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ -#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ -#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ -#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ -#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ -#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ - -/****************** Bit definition for AFIO_PCFR1register *******************/ -#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ -#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ -#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ -#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ - -#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ - -#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_PCFR1_PA12_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ -#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ - -#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ - -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ - -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ - -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ - -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ - -/******************************************************************************/ -/* Independent WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_CTLR register ********************/ -#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PSCR register ********************/ -#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ -#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ -#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ -#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ - -/******************* Bit definition for IWDG_RLDR register *******************/ -#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ - -/******************* Bit definition for IWDG_STATR register ********************/ -#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ -#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ - -/******************************************************************************/ -/* Inter-integrated Circuit Interface */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CTLR1 register ********************/ -#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ -#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ -#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ -#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ -#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ -#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ -#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ -#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ -#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ -#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ -#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ -#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ -#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ -#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ - -/******************* Bit definition for I2C_CTLR2 register ********************/ -#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ - -#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ -#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ -#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ -#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ -#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ - -/******************* Bit definition for I2C_OADDR1 register *******************/ -#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ -#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ - -#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ -#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ -#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ -#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ -#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ - -#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OADDR2 register *******************/ -#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ -#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ - -/******************** Bit definition for I2C_DATAR register ********************/ -#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ - -/******************* Bit definition for I2C_STAR1 register ********************/ -#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ -#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ -#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ -#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ -#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ -#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ -#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ -#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ -#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ -#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ -#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ -#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ -#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ -#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ - -/******************* Bit definition for I2C_STAR2 register ********************/ -#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ -#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ -#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ -#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ -#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ -#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ -#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ -#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ - -/******************* Bit definition for I2C_CKCFGR register ********************/ -#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ -#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ - -/******************************************************************************/ -/* Power Control */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CTLR register ********************/ -#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ -#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ -#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ -#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ -#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ - -#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ -#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ - -#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */ -#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */ -#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */ -#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */ -#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */ -#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */ -#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */ -#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */ - -#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ - -/******************************************************************************/ -/* Reset and Clock Control */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CTLR register ********************/ -#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ -#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ -#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ -#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ -#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ -#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ -#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ -#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ -#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ -#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ - -/******************* Bit definition for RCC_CFGR0 register *******************/ -#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ -#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ -#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ -#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ - -#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ -#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ -#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ - -#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ -#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ -#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ - -#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ -#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ -#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ -#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ -#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ -#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ -#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ -#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ -#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ -#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ -#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ -#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ -#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ - -#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ -#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ - -#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ -#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ -#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ -#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ -#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ - -#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ -#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ -#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ - -#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ -#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ -#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ -#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ -#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ - -#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ -#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ -#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ -#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ - -#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ - -#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ - -#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ -#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ - -#define RCC_PLLSRC_HSI_Mul2 ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */ -#define RCC_PLLSRC_HSE_Mul2 ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */ - -#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ -#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ - -#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ -#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ -#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ -#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ -#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ -#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ -#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ -#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ -#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ -#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ -#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ -#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ -#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ -#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ -#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ -#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ - -#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ -#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ -#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ -#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ - -/******************* Bit definition for RCC_INTR register ********************/ -#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ -#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ -#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ -#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ -#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ -#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ -#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ -#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ -#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ -#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ -#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ -#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ -#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ -#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ -#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ -#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ -#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ - -/***************** Bit definition for RCC_APB2PRSTR register *****************/ -#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ -#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ -#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ -#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ -#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ -#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ - -#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ - -#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ -#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ -#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ - -#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ - -/***************** Bit definition for RCC_APB1PRSTR register *****************/ -#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ -#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ -#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ -#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ -#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ - -#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ - -#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ -#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ - -#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ -#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ -#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ -#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ - -#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ - -/****************** Bit definition for RCC_AHBPCENR register ******************/ -#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ -#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ -#define RCC_FLITFEN ((uint16_t)0x0010) /* FLITF clock enable */ -#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ -#define RCC_USBHD ((uint16_t)0x1000) - -/****************** Bit definition for RCC_APB2PCENR register *****************/ -#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ -#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ -#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ -#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ -#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ -#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ - -#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ - -#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ -#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ -#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ - -/***************** Bit definition for RCC_APB1PCENR register ******************/ -#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ -#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ -#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ -#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ -#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ - -#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ -#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ - -#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ - -/******************* Bit definition for RCC_RSTSCKR register ********************/ -#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ -#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ -#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ -#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ -#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ -#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ -#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ -#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ -#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ - -/******************************************************************************/ -/* Serial Peripheral Interface */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CTLR1 register ********************/ -#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ -#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ -#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ - -#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ -#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ -#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ -#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ - -#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ -#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ -#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ -#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ -#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ -#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ -#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ -#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ -#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CTLR2 register ********************/ -#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ -#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ -#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ -#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ -#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ -#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_STATR register ********************/ -#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ -#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ -#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ -#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ -#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ -#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ -#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ -#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ - -/******************** Bit definition for SPI_DATAR register ********************/ -#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ - -/******************* Bit definition for SPI_CRCR register ******************/ -#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ - -/****************** Bit definition for SPI_RCRCR register ******************/ -#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ - -/****************** Bit definition for SPI_TCRCR register ******************/ -#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ - -/******************************************************************************/ -/* TIM */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CTLR1 register ********************/ -#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ -#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ -#define TIM_URS ((uint16_t)0x0004) /* Update request source */ -#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ -#define TIM_DIR ((uint16_t)0x0010) /* Direction */ - -#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ - -#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ - -#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ -#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ - -/******************* Bit definition for TIM_CTLR2 register ********************/ -#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ -#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ -#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ - -#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ -#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ -#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ -#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ -#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ -#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ -#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ -#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ -#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIM_SMCFGR register *******************/ -#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ - -#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ -#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ - -#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ -#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ - -#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ -#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ - -/******************* Bit definition for TIM_DMAINTENR register *******************/ -#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ -#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ -#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ -#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ -#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ -#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ -#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ -#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ -#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ -#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ -#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ -#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ -#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ -#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ -#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ - -/******************** Bit definition for TIM_INTFR register ********************/ -#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ -#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ -#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ -#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ -#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ -#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ -#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ -#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ -#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ -#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ -#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ -#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIM_SWEVGR register ********************/ -#define TIM_UG ((uint8_t)0x01) /* Update Generation */ -#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ -#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ -#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ -#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ -#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ -#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ -#define TIM_BG ((uint8_t)0x80) /* Break Generation */ - -/****************** Bit definition for TIM_CHCTLR1 register *******************/ -#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ -#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ - -#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ - -#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ -#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ - -#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ - -#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/****************** Bit definition for TIM_CHCTLR2 register *******************/ -#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ -#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ - -#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ - -#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ -#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ - -#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ - -#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ -#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ -#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ -#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ -#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ -#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ -#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ -#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ -#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ -#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ -#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ -#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ -#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ -#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ -#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ - -/******************* Bit definition for TIM_ATRLR register ********************/ -#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ - -/******************* Bit definition for TIM_RPTCR register ********************/ -#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ - -/******************* Bit definition for TIM_CH1CVR register *******************/ -#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ - -/******************* Bit definition for TIM_CH2CVR register *******************/ -#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ - -/******************* Bit definition for TIM_CH3CVR register *******************/ -#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ - -/******************* Bit definition for TIM_CH4CVR register *******************/ -#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ -#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ -#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ -#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ - -#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ -#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ -#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ -#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ -#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ -#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ -#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ - -/******************* Bit definition for TIM_DMACFGR register ********************/ -#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ -#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ - -#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ -#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ - -/******************* Bit definition for TIM_DMAADR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ - -/******************************************************************************/ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/******************************************************************************/ - -/******************* Bit definition for USART_STATR register *******************/ -#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ -#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ -#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ -#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ -#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ -#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ -#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ -#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ -#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ -#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ - -/******************* Bit definition for USART_DATAR register *******************/ -#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ - -/****************** Bit definition for USART_CTLR1 register *******************/ -#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ -#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ -#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ -#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ -#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ -#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ -#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ -#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ -#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ -#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ -#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ -#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ -#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ -#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ -#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ - -/****************** Bit definition for USART_CTLR2 register *******************/ -#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ -#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ -#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ -#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ -#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ -#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ -#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ - -#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ -#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ -#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ - -/****************** Bit definition for USART_CTLR3 register *******************/ -#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ -#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ -#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ -#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ -#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ -#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ -#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ -#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ -#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ -#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ -#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ -#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ - -/****************** Bit definition for USART_GPR register ******************/ -#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ -#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ -#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ -#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ -#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ -#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ -#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ -#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ -#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ - -#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ - -/******************************************************************************/ -/* Window WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CTLR register ********************/ -#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ -#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ -#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ -#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ -#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ -#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ -#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ - -#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ - -/******************* Bit definition for WWDG_CFGR register *******************/ -#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ -#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ -#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ -#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ -#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ -#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ -#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ -#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ - -#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ -#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ - -#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_STATR register ********************/ -#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ - -/******************************************************************************/ -/* ENHANCED FUNNCTION */ -/******************************************************************************/ - -/**************************** Enhanced register *****************************/ -#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 6 */ -#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ - -#define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */ - -#define EXTEN_OPA_EN ((uint32_t)0x00010000) -#define EXTEN_OPA_NSEL ((uint32_t)0x00020000) -#define EXTEN_OPA_PSEL ((uint32_t)0x00040000) - -#include - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00x_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/28 + * Description : CH32V00x Device Peripheral Access Layer Header File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_H +#define __CH32V00x_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define HSE_VALUE ((uint32_t)24000000) /* Value of the External oscillator in Hz */ + +/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x2000) /* Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)24000000) /* Value of the Internal oscillator in Hz */ + +/* CH32V00x Standard Peripheral Library version number */ +#define __CH32V00x_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ +#define __CH32V00x_STDPERIPH_VERSION_SUB (0x09) /* [7:0] sub version */ +#define __CH32V00x_STDPERIPH_VERSION ( (__CH32V00x_STDPERIPH_VERSION_MAIN << 8)\ + |(__CH32V00x_STDPERIPH_VERSION_SUB << 0)) + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + SysTicK_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + FLASH_IRQn = 18, /* FLASH global Interrupt */ + RCC_IRQn = 19, /* RCC global Interrupt */ + EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ + AWU_IRQn = 21, /* AWU global Interrupt */ + DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 29, /* ADC global Interrupt */ + I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ + USART1_IRQn = 32, /* USART1 global Interrupt */ + SPI1_IRQn = 33, /* SPI1 global Interrupt */ + TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 38, /* TIM2 global Interrupt */ + +} IRQn_Type; + +#define HardFault_IRQn EXC_IRQn + +#include +#include +#include + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + __IO uint32_t DLYR; +} ADC_TypeDef; + +/* Debug MCU */ +typedef struct +{ + __IO uint32_t CFGR0; + __IO uint32_t CFGR1; +} DBGMCU_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; + __IO uint32_t BOOT_MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; +} OB_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + uint32_t RESERVED0; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; + __IO uint32_t AWUCSR; + __IO uint32_t AWUWR; + __IO uint32_t AWUPSC; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t RESERVED0; + __IO uint32_t RSTSCKR; +} RCC_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint32_t CH1CVR; + __IO uint32_t CH2CVR; + __IO uint32_t CH3CVR; + __IO uint32_t CH4CVR; + __IO uint16_t BDTR; + uint16_t RESERVED13; + __IO uint16_t DMACFGR; + uint16_t RESERVED14; + __IO uint16_t DMAADR; + uint16_t RESERVED15; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ +#define EXTEN_BASE ((uint32_t)0x40023800) + +#define VENDOR_CFG0_BASE ((uint32_t)0x1FFFF7D4) +#define CFG0_PLL_TRIM (VENDOR_CFG0_BASE) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ +#define ADC_CALVOLSELECT ((uint32_t)0x06000000) +#define ADC_CALVOLSELECT_0 ((uint32_t)0x02000000) +#define ADC_CALVOLSELECT_1 ((uint32_t)0x04000000) + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x03FF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x03FF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x03FF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x03FF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x03FF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x03FF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0xFFFFFFFF) /* Regular data */ + +/******************** Bit definition for ADC_DLYR register ********************/ +#define ADC_DLYR_DLYVLU ((uint32_t)0x1FF) +#define ADC_DLYR_DLYSRC ((uint32_t)0x200) + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_MODE ((uint16_t)0x4000) +#define FLASH_STATR_LOCK ((uint16_t)0x8000) + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG ((uint16_t)0x0001) /* Programming */ +#define FLASH_CTLR_PER ((uint16_t)0x0002) /* Page Erase 1KByte*/ +#define FLASH_CTLR_MER ((uint16_t)0x0004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG ((uint16_t)0x0010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint16_t)0x0020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint16_t)0x0040) /* Start */ +#define FLASH_CTLR_LOCK ((uint16_t)0x0080) /* Lock */ +#define FLASH_CTLR_OPTWRE ((uint16_t)0x0200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint16_t)0x0400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint16_t)0x1000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FLOCK ((uint16_t)0x8000) +#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 64Byte */ +#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 64Byte */ +#define FLASH_CTLR_BUF_LOAD ((uint32_t)0x00040000) /* Buffer Load */ +#define FLASH_CTLR_BUF_RST ((uint32_t)0x00080000) /* Buffer Reset */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) +#define FLASH_OBR_STANDY_RST ((uint16_t)0x0010) +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) +#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */ +#define FLASH_OBR_STATR_MODE ((uint16_t)0x0080) +#define FLASH_OBR_FIX_11 ((uint16_t)0x0300) + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_MODEKEYR register ******************/ +#define FLASH_MODEKEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for FLASH__BOOT_MODEKEYR register ******************/ +#define FLASH_BOOT_MODEKEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_BOOT_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCKK ((uint32_t)0x00000100) + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP_1 ((uint32_t)0x00000080) +#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_PCFR1_PA12_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ + +#define AFIO_PCFR1_USART1_HIGH_BIT_REMAP ((uint32_t)0x00200000) +#define AFIO_PCFR1_I2C1_HIGH_BIT_REMAP ((uint32_t)0x00400000) +#define AFIO_PCFR1_TIM1_1_RM ((uint32_t)0x00800000) + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) +#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) +#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x0003) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x000C) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0030) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0x00C0) /* EXTI 3 configuration */ +#define AFIO_EXTICR1_EXTI4 ((uint16_t)0x0300) +#define AFIO_EXTICR1_EXTI5 ((uint16_t)0x0C00) +#define AFIO_EXTICR1_EXTI6 ((uint16_t)0x3000) +#define AFIO_EXTICR1_EXTI7 ((uint16_t)0xC000) + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0008) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x000C) /* PD[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0020) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0030) /* PD[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x0080) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x00C0) /* PD[3] pin */ + +#define AFIO_EXTICR1_EXTI4_PA ((uint16_t)0x0000) +#define AFIO_EXTICR1_EXTI4_PC ((uint16_t)0x0200) +#define AFIO_EXTICR1_EXTI4_PD ((uint16_t)0x0300) + +#define AFIO_EXTICR1_EXTI5_PA ((uint16_t)0x0000) +#define AFIO_EXTICR1_EXTI5_PC ((uint16_t)0x0800) +#define AFIO_EXTICR1_EXTI5_PD ((uint16_t)0x0C00) + +#define AFIO_EXTICR1_EXTI6_PA ((uint16_t)0x0000) +#define AFIO_EXTICR1_EXTI6_PC ((uint16_t)0x2000) +#define AFIO_EXTICR1_EXTI6_PD ((uint16_t)0x3000) + +#define AFIO_EXTICR1_EXTI7_PA ((uint16_t)0x0000) +#define AFIO_EXTICR1_EXTI7_PC ((uint16_t)0x8000) +#define AFIO_EXTICR1_EXTI7_PD ((uint16_t)0xC000) + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_PVDLevel_0 ((uint16_t)0x0000) +#define PWR_PVDLevel_1 ((uint16_t)0x0020) +#define PWR_PVDLevel_2 ((uint16_t)0x0040) +#define PWR_PVDLevel_3 ((uint16_t)0x0060) +#define PWR_PVDLevel_4 ((uint16_t)0x0080) +#define PWR_PVDLevel_5 ((uint16_t)0x00A0) +#define PWR_PVDLevel_6 ((uint16_t)0x00C0) +#define PWR_PVDLevel_7 ((uint16_t)0x00E0) + +/******************* Bit definition for PWR_AWUCSR register ********************/ +#define PWR_AWUCSR_AWUEN ((uint16_t)0x0002) + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ + +/******************* Bit definition for PWR_AWUWR register ********************/ +#define PWR_AWUWR ((uint16_t)0x003F) + +/******************* Bit definition for PWR_AWUWR register ********************/ +#define PWR_AWUPSC ((uint16_t)0x000F) +#define PWR_AWUPSC_0 ((uint16_t)0x0000) +#define PWR_AWUPSC_2 ((uint16_t)0x0002) +#define PWR_AWUPSC_4 ((uint16_t)0x0003) +#define PWR_AWUPSC_8 ((uint16_t)0x0004) +#define PWR_AWUPSC_16 ((uint16_t)0x0005) +#define PWR_AWUPSC_32 ((uint16_t)0x0006) +#define PWR_AWUPSC_64 ((uint16_t)0x0007) +#define PWR_AWUPSC_128 ((uint16_t)0x0008) +#define PWR_AWUPSC_256 ((uint16_t)0x0009) +#define PWR_AWUPSC_512 ((uint16_t)0x000A) +#define PWR_AWUPSC_1024 ((uint16_t)0x000B) +#define PWR_AWUPSC_2048 ((uint16_t)0x000C) +#define PWR_AWUPSC_4096 ((uint16_t)0x000D) +#define PWR_AWUPSC_10240 ((uint16_t)0x000E) +#define PWR_AWUPSC_61440 ((uint16_t)0x000F) + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ +#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ +#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ + +#define RCC_ADCPRE ((uint32_t)0x0000F800) /* ADCPRE[4:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_ADCPRE_2 ((uint32_t)0x00002000) +#define RCC_ADCPRE_3 ((uint32_t)0x00004000) +#define RCC_ADCPRE_4 ((uint32_t)0x00008000) + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ +#define RCC_PLLSRC_HSI_Mul2 ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE_Mul2 ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ + +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ + +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ + +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ + +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register ******************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 6 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + +#define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */ + +#define EXTEN_OPA_EN ((uint32_t)0x00010000) +#define EXTEN_OPA_NSEL ((uint32_t)0x00020000) +#define EXTEN_OPA_PSEL ((uint32_t)0x00040000) + +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_adc.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_adc.h index dd47ffa..acbc37b 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_adc.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_adc.h @@ -1,176 +1,175 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_adc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the - * ADC firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_ADC_H -#define __CH32V00x_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* ADC Init structure definition */ -typedef struct -{ - uint32_t ADC_Mode; /* Configures the ADC to operate in independent or - dual mode. - This parameter can be a value of @ref ADC_mode */ - - FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in - Scan (multichannels) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ -} ADC_InitTypeDef; - -/* ADC_mode */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) - -/* ADC_external_trigger_sources_for_regular_channels_conversion */ -#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) -#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) -#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000) -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) - -/* ADC_data_align */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) - -/* ADC_channels */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) - -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8) -#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9) - -/* ADC_sampling_time */ -#define ADC_SampleTime_3Cycles ((uint8_t)0x00) -#define ADC_SampleTime_9Cycles ((uint8_t)0x01) -#define ADC_SampleTime_15Cycles ((uint8_t)0x02) -#define ADC_SampleTime_30Cycles ((uint8_t)0x03) -#define ADC_SampleTime_43Cycles ((uint8_t)0x04) -#define ADC_SampleTime_57Cycles ((uint8_t)0x05) -#define ADC_SampleTime_73Cycles ((uint8_t)0x06) -#define ADC_SampleTime_241Cycles ((uint8_t)0x07) - -/* ADC_external_trigger_sources_for_injected_channels_conversion */ -#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) -#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) -#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) -#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000) -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) - -/* ADC_injected_channel_selection */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) - -/* ADC_analog_watchdog_selection */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -/* ADC_interrupts_definition */ -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) - -/* ADC_flags_definition */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) - -/* ADC_calibration_voltage_definition */ -#define ADC_CALVOL_50PERCENT ((uint32_t)0x02000000) -#define ADC_CALVOL_75PERCENT ((uint32_t)0x04000000) - -/* ADC_external_trigger_sources_delay_channels_definition */ -#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00020000) - - -void ADC_DeInit(ADC_TypeDef *ADCx); -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); -void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); -void ADC_ResetCalibration(ADC_TypeDef *ADCx); -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); -void ADC_StartCalibration(ADC_TypeDef *ADCx); -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); -void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); -void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); -void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); -void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); -void ADC_Calibration_Vol(ADC_TypeDef *ADCx, uint32_t ADC_CALVOL); -void ADC_ExternalTrig_DLY(ADC_TypeDef *ADCx, uint32_t channel, uint16_t DelayTim); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V00x_ADC_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_adc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/20 + * Description : This file contains all the functions prototypes for the + * ADC firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_ADC_H +#define __CH32V00x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +} ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) + +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8) +#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9) + +/* ADC_sampling_time */ +#define ADC_SampleTime_3Cycles ((uint8_t)0x00) +#define ADC_SampleTime_9Cycles ((uint8_t)0x01) +#define ADC_SampleTime_15Cycles ((uint8_t)0x02) +#define ADC_SampleTime_30Cycles ((uint8_t)0x03) +#define ADC_SampleTime_43Cycles ((uint8_t)0x04) +#define ADC_SampleTime_57Cycles ((uint8_t)0x05) +#define ADC_SampleTime_73Cycles ((uint8_t)0x06) +#define ADC_SampleTime_241Cycles ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +/* ADC_calibration_voltage_definition */ +#define ADC_CALVOL_50PERCENT ((uint32_t)0x02000000) +#define ADC_CALVOL_75PERCENT ((uint32_t)0x04000000) + +/* ADC_external_trigger_sources_delay_channels_definition */ +#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00000200) + +void ADC_DeInit(ADC_TypeDef *ADCx); +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_StartCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_Calibration_Vol(ADC_TypeDef *ADCx, uint32_t ADC_CALVOL); +void ADC_ExternalTrig_DLY(ADC_TypeDef *ADCx, uint32_t channel, uint16_t DelayTim); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00x_ADC_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_dbgmcu.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_dbgmcu.h index a2cf9e2..2c84dc8 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_dbgmcu.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_dbgmcu.h @@ -1,38 +1,38 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_dbgmcu.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the - * DBGMCU firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_DBGMCU_H -#define __CH32V00x_DBGMCU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* CFGR0 Register */ -#define DBGMCU_IWDG_STOP ((uint32_t)0x00000001) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM1_STOP ((uint32_t)0x00000010) -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000020) - -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -uint32_t __get_DEBUG_CR(void); -void __set_DEBUG_CR(uint32_t value); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00x_DBGMCU_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_dbgmcu.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * DBGMCU firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_DBGMCU_H +#define __CH32V00x_DBGMCU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* CFGR0 Register */ +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000001) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000002) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000010) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000020) + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +uint32_t __get_DEBUG_CR(void); +void __set_DEBUG_CR(uint32_t value); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +uint32_t DBGMCU_GetCHIPID( void ); +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_DBGMCU_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_dma.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_dma.h index a4964f0..c18459b 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_dma.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_dma.h @@ -1,177 +1,177 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_dma.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the - * DMA firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_DMA_H -#define __CH32V00x_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* DMA Init structure definition */ -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode. - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -} DMA_InitTypeDef; - -/* DMA_data_transfer_direction */ -#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) - -/* DMA_peripheral_incremented_mode */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) - -/* DMA_memory_incremented_mode */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) - -/* DMA_peripheral_data_size */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) - -/* DMA_memory_data_size */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) - -/* DMA_circular_normal_mode */ -#define DMA_Mode_Circular ((uint32_t)0x00000020) -#define DMA_Mode_Normal ((uint32_t)0x00000000) - -/* DMA_priority_level */ -#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) -#define DMA_Priority_High ((uint32_t)0x00002000) -#define DMA_Priority_Medium ((uint32_t)0x00001000) -#define DMA_Priority_Low ((uint32_t)0x00000000) - -/* DMA_memory_to_memory */ -#define DMA_M2M_Enable ((uint32_t)0x00004000) -#define DMA_M2M_Disable ((uint32_t)0x00000000) - -/* DMA_interrupts_definition */ -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) - -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) - -/* DMA_flags_definition */ -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) - - -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); -void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); -void DMA_ClearFlag(uint32_t DMAy_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMAy_IT); -void DMA_ClearITPendingBit(uint32_t DMAy_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V00x_DMA_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_dma.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * DMA firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_DMA_H +#define __CH32V00x_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + + +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00x_DMA_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_exti.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_exti.h index f371e3c..5be616d 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_exti.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_exti.h @@ -1,78 +1,78 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_exti.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the - * EXTI firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_EXTI_H -#define __CH32V00x_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* EXTI mode enumeration */ -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -} EXTIMode_TypeDef; - -/* EXTI Trigger enumeration */ -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -} EXTITrigger_TypeDef; - -/* EXTI Init Structure definition */ -typedef struct -{ - uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -} EXTI_InitTypeDef; - -/* EXTI_Lines */ -#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */ -#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/ - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00x_EXTI_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_exti.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * EXTI firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_EXTI_H +#define __CH32V00x_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitTypeDef; + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_EXTI_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_flash.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_flash.h index cb709ba..1525f8f 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_flash.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_flash.h @@ -1,129 +1,138 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_flash.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the FLASH - * firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_FLASH_H -#define __CH32V00x_FLASH_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* FLASH Status */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT -} FLASH_Status; - -/* Flash_Latency */ -#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ - -/* Values to be used with CH32V00x devices (1page = 64Byte) */ -#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */ -#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */ -#define FLASH_WRProt_Pages32to47 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 32 to 47 */ -#define FLASH_WRProt_Pages48to63 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 48 to 63 */ -#define FLASH_WRProt_Pages64to79 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 64 to 79 */ -#define FLASH_WRProt_Pages80to95 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 80 to 95 */ -#define FLASH_WRProt_Pages96to111 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 96 to 111 */ -#define FLASH_WRProt_Pages112to127 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 112 to 127 */ -#define FLASH_WRProt_Pages128to143 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 128 to 143 */ -#define FLASH_WRProt_Pages144to159 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 144 to 159 */ -#define FLASH_WRProt_Pages160to175 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 160 to 175 */ -#define FLASH_WRProt_Pages176to191 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 176 to 191 */ -#define FLASH_WRProt_Pages192to207 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 192 to 207 */ -#define FLASH_WRProt_Pages208to223 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 208 to 223 */ -#define FLASH_WRProt_Pages224to239 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 224 to 239 */ -#define FLASH_WRProt_Pages240to255 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 240 to 255 */ - -#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */ - -/* Option_Bytes_IWatchdog */ -#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ -#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ - -/* Option_Bytes_nRST_STOP */ -#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ - -/* Option_Bytes_nRST_STDBY */ -#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ - -/* Option_Bytes_RST_ENandDT */ -#define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/ -#define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */ -#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */ -#define OB_RST_EN_DT128ms ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128ms */ - -/* FLASH_Interrupts */ -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ - -/* FLASH_Flags */ -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ - -/* System_Reset_Start_Mode */ -#define Start_Mode_USER ((uint32_t)0x00000000) -#define Start_Mode_BOOT ((uint32_t)0x00004000) - - -/*Functions used for all CH32V00x devices*/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY, uint16_t OB_RST); -uint32_t FLASH_GetUserOptionByte(void); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); -void FLASH_Unlock_Fast(void); -void FLASH_Lock_Fast(void); -void FLASH_BufReset(void); -void FLASH_BufLoad(uint32_t Address, uint32_t Data0); -void FLASH_ErasePage_Fast(uint32_t Page_Address); -void FLASH_ProgramPage_Fast(uint32_t Page_Address); -void SystemReset_StartMode(uint32_t Mode); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00x_FLASH_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_flash.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/25 + * Description : This file contains all the functions prototypes for the FLASH + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_FLASH_H +#define __CH32V00x_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ + +/* Values to be used with CH32V00x devices (1page = 64Byte) */ +#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */ +#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */ +#define FLASH_WRProt_Pages32to47 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 32 to 47 */ +#define FLASH_WRProt_Pages48to63 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 48 to 63 */ +#define FLASH_WRProt_Pages64to79 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 64 to 79 */ +#define FLASH_WRProt_Pages80to95 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 80 to 95 */ +#define FLASH_WRProt_Pages96to111 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 96 to 111 */ +#define FLASH_WRProt_Pages112to127 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 112 to 127 */ +#define FLASH_WRProt_Pages128to143 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 128 to 143 */ +#define FLASH_WRProt_Pages144to159 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 144 to 159 */ +#define FLASH_WRProt_Pages160to175 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 160 to 175 */ +#define FLASH_WRProt_Pages176to191 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 176 to 191 */ +#define FLASH_WRProt_Pages192to207 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 192 to 207 */ +#define FLASH_WRProt_Pages208to223 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 208 to 223 */ +#define FLASH_WRProt_Pages224to239 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 224 to 239 */ +#define FLASH_WRProt_Pages240to255 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 240 to 255 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* Option_Bytes_RST_ENandDT */ +#define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/ +#define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */ +#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */ +#define OB_RST_EN_DT128us ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128us */ + +/* Option_Bytes_Power_ON_Start_Mode */ +#define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* from Boot after power on */ +#define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* from User after power on */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/* System_Reset_Start_Mode */ +#define Start_Mode_USER ((uint32_t)0x00000000) +#define Start_Mode_BOOT ((uint32_t)0x00004000) + + +/*Functions used for all CH32V00x devices*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STDBY, uint16_t OB_RST, uint16_t OB_PowerON_Start_Mode); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_BufReset(void); +void FLASH_BufLoad(uint32_t Address, uint32_t Data0); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address); +void SystemReset_StartMode(uint32_t Mode); +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_FLASH_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_gpio.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_gpio.h index 28c5112..db1aafe 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_gpio.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_gpio.h @@ -1,130 +1,132 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_gpio.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the - * GPIO firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_GPIO_H -#define __CH32V00x_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* Output Maximum frequency selection */ -typedef enum -{ - GPIO_Speed_10MHz = 1, - GPIO_Speed_2MHz, - GPIO_Speed_50MHz -} GPIOSpeed_TypeDef; - -/* Configuration Mode enumeration */ -typedef enum -{ - GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 -} GPIOMode_TypeDef; - -/* GPIO Init structure definition */ -typedef struct -{ - uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -} GPIO_InitTypeDef; - -/* Bit_SET and Bit_RESET enumeration */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -} BitAction; - -/* GPIO_pins_define */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - -/* GPIO_Remap_define */ -#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ -#define GPIO_PartialRemap_I2C1 ((uint32_t)0x10000002) /* I2C1 Partial Alternate Function mapping */ -#define GPIO_FullRemap_I2C1 ((uint32_t)0x10400002) /* I2C1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_USART1 ((uint32_t)0x80000004) /* USART1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_USART1 ((uint32_t)0x80200000) /* USART1 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_USART1 ((uint32_t)0x80200004) /* USART1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x00160080) /* TIM1 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ -#define GPIO_Remap_PA1_2 ((uint32_t)0x00008000) /* PA1 and PA2 Alternate Function mapping */ -#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */ -#define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */ - -/* GPIO_Port_Sources */ -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) -#define GPIO_PortSourceGPIOD ((uint8_t)0x03) - -/* GPIO_Pin_sources */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) - -void GPIO_DeInit(GPIO_TypeDef *GPIOx); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_EventOutputCmd(FunctionalState NewState); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00x_GPIO_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_gpio.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/02/27 + * Description : This file contains all the functions prototypes for the + * GPIO firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_GPIO_H +#define __CH32V00x_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_30MHz +} GPIOSpeed_TypeDef; + +#define GPIO_Speed_50MHz GPIO_Speed_30MHz + +/* Configuration Mode enumeration */ +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +} GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_PartialRemap_I2C1 ((uint32_t)0x10000002) /* I2C1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_I2C1 ((uint32_t)0x10400002) /* I2C1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART1 ((uint32_t)0x80000004) /* USART1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART1 ((uint32_t)0x80200000) /* USART1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART1 ((uint32_t)0x80200004) /* USART1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x00160080) /* TIM1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_Remap_PA1_2 ((uint32_t)0x00008000) /* PA1 and PA2 Alternate Function mapping */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */ +#define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */ + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) + +void GPIO_DeInit(GPIO_TypeDef *GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_GPIO_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_i2c.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_i2c.h index cb1e629..3494f51 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_i2c.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_i2c.h @@ -1,415 +1,415 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_i2c.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the - * I2C firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_I2C_H -#define __CH32V00x_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* I2C Init structure definition */ -typedef struct -{ - uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /* Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /* Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /* Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -} I2C_InitTypeDef; - -/* I2C_mode */ -#define I2C_Mode_I2C ((uint16_t)0x0000) - -/* I2C_duty_cycle_in_fast_mode */ -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ - -/* I2C_acknowledgement */ -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) - -/* I2C_transfer_direction */ -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) - -/* I2C_acknowledged_address */ -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) - -/* I2C_registers */ -#define I2C_Register_CTLR1 ((uint8_t)0x00) -#define I2C_Register_CTLR2 ((uint8_t)0x04) -#define I2C_Register_OADDR1 ((uint8_t)0x08) -#define I2C_Register_OADDR2 ((uint8_t)0x0C) -#define I2C_Register_DATAR ((uint8_t)0x10) -#define I2C_Register_STAR1 ((uint8_t)0x14) -#define I2C_Register_STAR2 ((uint8_t)0x18) -#define I2C_Register_CKCFGR ((uint8_t)0x1C) - -/* I2C_PEC_position */ -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) - -/* I2C_NACK_position */ -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) - -/* I2C_interrupts_definition */ -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) - -/* I2C_interrupts_definition */ -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -/* SR2 register flags */ -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/* SR1 register flags */ -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -/****************I2C Master Events (Events grouped in order of communication)********************/ - -/******************************************************************************************************************** - * @brief Start communicate - * - * After master use I2C_GenerateSTART() function sending the START condition,the master - * has to wait for event 5(the Start condition has been correctly - * released on the I2C bus ). - * - */ -/* EVT5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/******************************************************************************************************************** - * @brief Address Acknowledge - * - * When start condition correctly released on the bus(check EVT5), the - * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate - * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will be set: - * - * - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (after generating the START - * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. - * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent - * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part - * of the 10-bit address (LSB) . Then master should wait for event 6. - * - * - */ - -/* EVT6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/*EVT9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/******************************************************************************************************************** - * @brief Communication events - * - * If START condition has generated and slave address - * been acknowledged. then the master has to check one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EVT7 then use - * I2C_ReceiveData() function to read the data received from the slave . - * - * 2) Master Transmitter mode: The master use I2C_SendData() function to send data - * then to wait on event EVT8 or EVT8_2. - * These two events are similar: - * - EVT8 means that the data has been written in the data register and is - * being shifted out. - * - EVT8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EVT8 is sufficient for the application. - * Using EVT8_2 will leads to a slower communication speed but will more reliable . - * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission - * - * - * Note: - * In case the user software does not guarantee that this event EVT7 is managed before - * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. - * - * - */ - -/* Master Receive mode */ -/* EVT7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master Transmitter mode*/ -/* EVT8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* EVT8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - -/******************I2C Slave Events (Events grouped in order of communication)******************/ - -/******************************************************************************************************************** - * @brief Start Communicate events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a start condition of master device generate on the bus. - * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. - * - * - * - * a) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * b) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * c) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* EVT1 */ -/* a) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* b) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* c) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/******************************************************************************************************************** - * @brief Communication events - * - * Wait on one of these events when EVT1 has already been checked : - * - * - Slave Receiver mode: - * - EVT2--The device is expecting to receive a data byte . - * - EVT4--The device is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EVT3--When a byte has been transmitted by the slave and the Master is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee - * the EVT3 is managed before the current byte end of transfer The second one can optionally - * be used. - * - EVT3_2--When the master sends a NACK to tell slave device that data transmission - * shall end . The slave device has to stop sending - * data bytes and wait a Stop condition from bus. - * - * Note: - * If the user software does not guarantee that the event 2 is - * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time . - * In this case the communication will be slower. - * - */ - -/* Slave Receiver mode*/ -/* EVT2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* EVT4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave Transmitter mode -----------------------*/ -/* EVT3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/*EVT3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - - -void I2C_DeInit(I2C_TypeDef *I2Cx); -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); -void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); -void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); -void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); -void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); - - -/***************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * profit the application requirements and constraints: - * - * - * a) First way: - * Using I2C_CheckEvent() function: - * It compares the status registers (STARR1 and STAR2) content to a given event - * (can be the combination of more flags). - * If the current status registers includes the given flags will return SUCCESS. - * and if the current status registers miss flags will returns ERROR. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (CH32V03RM). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs besides to the monitored error, - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * in corrupted state. it is suggeted to use error interrupts to monitor the error - * events and handle them in IRQ handler. - * - * - * Note: - * The following functions are recommended for error management: : - * - I2C_ITConfig() main function of configure and enable the error interrupts. - * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions - * to determine which error occurred. - * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() - * \ I2C_GenerateStop() will be use to clear the error flag and source, - * and return to correct communication status. - * - * - * b) Second way: - * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. - * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). - * - When to use: - * - * - This function is suitable for the same applications above but it - * don't have the limitations of I2C_GetFlagStatus() function . - * The returned value could be compared to events already defined in the - * library (CH32V00x_i2c.h) or to custom values defined by user. - * - This function can be used to monitor the status of multiple flags simultaneously. - * - Contrary to the I2C_CheckEvent () function, this function can choose the time to - * accept the event according to the user's needs (when all event flags are set and - * no other flags are set, or only when the required flags are set) - * - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * c) Third way: - * Using the function I2C_GetFlagStatus() get the status of - * one single flag . - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed . - * - * - Limitations: - * - Call this function to access the status register. Some flag bits may be cleared. - * - Function may need to be called twice or more in order to monitor one single event. - */ - - - -/********************************************************* - * - * a) Basic state monitoring(First way) - ******************************************************** - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/********************************************************* - * - * b) Advanced state monitoring(Second way:) - ******************************************************** - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/********************************************************* - * - * c) Flag-based state monitoring(Third way) - ********************************************************* - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - -void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V00x_I2C_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_i2c.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * I2C firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_I2C_H +#define __CH32V00x_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode -----------------------*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef *I2Cx); +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); + + +/***************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * profit the application requirements and constraints: + * + * + * a) First way: + * Using I2C_CheckEvent() function: + * It compares the status registers (STARR1 and STAR2) content to a given event + * (can be the combination of more flags). + * If the current status registers includes the given flags will return SUCCESS. + * and if the current status registers miss flags will returns ERROR. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (CH32V03RM). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs besides to the monitored error, + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * in corrupted state. it is suggeted to use error interrupts to monitor the error + * events and handle them in IRQ handler. + * + * + * Note: + * The following functions are recommended for error management: : + * - I2C_ITConfig() main function of configure and enable the error interrupts. + * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions + * to determine which error occurred. + * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() + * \ I2C_GenerateStop() will be use to clear the error flag and source, + * and return to correct communication status. + * + * + * b) Second way: + * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. + * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). + * - When to use: + * + * - This function is suitable for the same applications above but it + * don't have the limitations of I2C_GetFlagStatus() function . + * The returned value could be compared to events already defined in the + * library (CH32V00x_i2c.h) or to custom values defined by user. + * - This function can be used to monitor the status of multiple flags simultaneously. + * - Contrary to the I2C_CheckEvent () function, this function can choose the time to + * accept the event according to the user's needs (when all event flags are set and + * no other flags are set, or only when the required flags are set) + * + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * c) Third way: + * Using the function I2C_GetFlagStatus() get the status of + * one single flag . + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed . + * + * - Limitations: + * - Call this function to access the status register. Some flag bits may be cleared. + * - Function may need to be called twice or more in order to monitor one single event. + */ + + + +/********************************************************* + * + * a) Basic state monitoring(First way) + ******************************************************** + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/********************************************************* + * + * b) Advanced state monitoring(Second way:) + ******************************************************** + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/********************************************************* + * + * c) Flag-based state monitoring(Third way) + ********************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00x_I2C_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_iwdg.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_iwdg.h index 3fd8fbb..ffa0fdc 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_iwdg.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_iwdg.h @@ -1,50 +1,50 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_iwdg.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the - * IWDG firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_IWDG_H -#define __CH32V00x_IWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* IWDG_WriteAccess */ -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) - -/* IWDG_prescaler */ -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) - -/* IWDG_Flag */ -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) - -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_Enable(void); -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00x_IWDG_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_iwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * IWDG firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_IWDG_H +#define __CH32V00x_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_IWDG_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_misc.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_misc.h index f1a3ae3..8f12113 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_misc.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_misc.h @@ -1,48 +1,74 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_misc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the - * miscellaneous firmware library functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_MISC_H -#define __CH32V00X_MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include - -/* NVIC Init Structure definition */ -typedef struct -{ - uint8_t NVIC_IRQChannel; - uint8_t NVIC_IRQChannelPreemptionPriority; - uint8_t NVIC_IRQChannelSubPriority; - FunctionalState NVIC_IRQChannelCmd; -} NVIC_InitTypeDef; - - -/* Preemption_Priority_Group */ -#define NVIC_PriorityGroup_0 ((uint32_t)0x00) -#define NVIC_PriorityGroup_1 ((uint32_t)0x01) -#define NVIC_PriorityGroup_2 ((uint32_t)0x02) -#define NVIC_PriorityGroup_3 ((uint32_t)0x03) -#define NVIC_PriorityGroup_4 ((uint32_t)0x04) - - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00x_MISC_H */ - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_misc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : This file contains all the functions prototypes for the + * miscellaneous firmware library functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_MISC_H +#define __CH32V00X_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include + +/* CSR_INTSYSCR_INEST_definition */ +#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ + +/* Check the configuration of CSR(0x804) in the startup file(.S) +* interrupt nesting enable(CSR-0x804 bit1 = 1) +* priority - bit[7] - Preemption Priority +* bit[6] - Sub priority +* bit[5:0] - Reserve +* interrupt nesting disable(CSR-0x804 bit1 = 0) +* priority - bit[7:6] - Sub priority +* bit[5:0] - Reserve +*/ + +#ifndef INTSYSCR_INEST +#define INTSYSCR_INEST INTSYSCR_INEST_EN +#endif + +/* NVIC Init Structure definition + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 1. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Preemption_Priority_Group */ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ +#else +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#endif + + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_MISC_H */ + diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_opa.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_opa.h index cfdd6bd..9661d7a 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_opa.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_opa.h @@ -1,53 +1,53 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_opa.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the - * OPA firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_OPA_H -#define __CH32V00x_OPA_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v00x.h" - -/* OPA PSEL enumeration */ -typedef enum -{ - CHP0 = 0, - CHP1 -} OPA_PSEL_TypeDef; - -/* OPA NSEL enumeration */ -typedef enum -{ - CHN0 = 0, - CHN1 -} OPA_NSEL_TypeDef; - - -/* OPA Init Structure definition */ -typedef struct -{ - OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ - OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ -} OPA_InitTypeDef; - -void OPA_DeInit(void); -void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); -void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); -void OPA_Cmd(FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_opa.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * OPA firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_OPA_H +#define __CH32V00x_OPA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v00x.h" + +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0 = 0, + CHP1 +} OPA_PSEL_TypeDef; + +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0 = 0, + CHN1 +} OPA_NSEL_TypeDef; + + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ +} OPA_InitTypeDef; + +void OPA_DeInit(void); +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); +void OPA_Cmd(FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_pwr.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_pwr.h index 89c1b34..9bb3b6d 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_pwr.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_pwr.h @@ -1,69 +1,78 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_pwr.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the PWR - * firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_PWR_H -#define __CH32V00x_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* PVD_detection_level */ -#define PWR_PVDLevel_2V9 ((uint32_t)0x00000000) -#define PWR_PVDLevel_3V1 ((uint32_t)0x00000020) -#define PWR_PVDLevel_3V3 ((uint32_t)0x00000040) -#define PWR_PVDLevel_3V5 ((uint32_t)0x00000060) -#define PWR_PVDLevel_3V7 ((uint32_t)0x00000080) -#define PWR_PVDLevel_3V9 ((uint32_t)0x000000A0) -#define PWR_PVDLevel_4V1 ((uint32_t)0x000000C0) -#define PWR_PVDLevel_4V4 ((uint32_t)0x000000E0) - -/* PWR_AWU_Prescaler */ -#define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000) -#define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002) -#define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003) -#define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004) -#define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005) -#define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006) -#define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007) -#define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008) -#define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009) -#define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A) -#define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B) -#define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C) -#define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D) -#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E) -#define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F) - -/* STOP_mode_entry */ -#define PWR_STANDBYEntry_WFI ((uint8_t)0x01) -#define PWR_STANDBYEntry_WFE ((uint8_t)0x02) - -/* PWR_Flag */ -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) - -void PWR_DeInit(void); -void PWR_PVDCmd(FunctionalState NewState); -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_AutoWakeUpCmd(FunctionalState NewState); -void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler); -void PWR_AWU_SetWindowValue(uint8_t WindowValue); -void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00x_PWR_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_pwr.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the PWR + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_PWR_H +#define __CH32V00x_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* PVD_detection_level */ +#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080) +#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0) + +#define PWR_PVDLevel_2V9 PWR_PVDLevel_MODE0 +#define PWR_PVDLevel_3V1 PWR_PVDLevel_MODE1 +#define PWR_PVDLevel_3V3 PWR_PVDLevel_MODE2 +#define PWR_PVDLevel_3V5 PWR_PVDLevel_MODE3 +#define PWR_PVDLevel_3V7 PWR_PVDLevel_MODE4 +#define PWR_PVDLevel_3V9 PWR_PVDLevel_MODE5 +#define PWR_PVDLevel_4V1 PWR_PVDLevel_MODE6 +#define PWR_PVDLevel_4V4 PWR_PVDLevel_MODE7 + +/* PWR_AWU_Prescaler */ +#define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000) +#define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002) +#define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003) +#define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004) +#define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005) +#define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006) +#define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007) +#define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008) +#define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009) +#define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A) +#define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B) +#define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C) +#define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D) +#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E) +#define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F) + +/* STOP_mode_entry */ +#define PWR_STANDBYEntry_WFI ((uint8_t)0x01) +#define PWR_STANDBYEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + +void PWR_DeInit(void); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_AutoWakeUpCmd(FunctionalState NewState); +void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler); +void PWR_AWU_SetWindowValue(uint8_t WindowValue); +void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_PWR_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_rcc.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_rcc.h index 7c87405..44e0cfc 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_rcc.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_rcc.h @@ -1,154 +1,154 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_rcc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the RCC firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_RCC_H -#define __CH32V00x_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* RCC_Exported_Types */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ - uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ -} RCC_ClocksTypeDef; - -/* HSE_configuration */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00010000) -#define RCC_HSE_Bypass ((uint32_t)0x00040000) - -/* PLL_entry_clock_source */ -#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000) -#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000) - -/* System_clock_source */ -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) - -/* AHB_clock_source */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) -#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) -#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) -#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) -#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) -#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) - -/* RCC_Interrupt_source */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) - -/* ADC_clock_source */ -#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) -#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) -#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) -#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) -#define RCC_PCLK2_Div12 ((uint32_t)0x0000A000) -#define RCC_PCLK2_Div16 ((uint32_t)0x0000E000) -#define RCC_PCLK2_Div24 ((uint32_t)0x0000A800) -#define RCC_PCLK2_Div32 ((uint32_t)0x0000E800) -#define RCC_PCLK2_Div48 ((uint32_t)0x0000B000) -#define RCC_PCLK2_Div64 ((uint32_t)0x0000F000) -#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800) -#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800) - -/* AHB_peripheral */ -#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) - -/* APB2_peripheral */ -#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) - -/* APB1_peripheral */ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) - -/* Clock_source_to_output_on_MCO_pin */ -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) -#define RCC_MCO_HSE ((uint8_t)0x06) -#define RCC_MCO_PLLCLK ((uint8_t)0x07) - -/* RCC_Flag */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -/* SysTick_clock_source */ -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) - -void RCC_DeInit(void); -void RCC_HSEConfig(uint32_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); -void RCC_LSICmd(FunctionalState NewState); -void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCO); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00x_RCC_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_rcc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the RCC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_RCC_H +#define __CH32V00x_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ +} RCC_ClocksTypeDef; + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00010000) + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) +#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) +#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) +#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) +#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) +#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define RCC_PCLK2_Div12 ((uint32_t)0x0000A000) +#define RCC_PCLK2_Div16 ((uint32_t)0x0000E000) +#define RCC_PCLK2_Div24 ((uint32_t)0x0000A800) +#define RCC_PCLK2_Div32 ((uint32_t)0x0000E800) +#define RCC_PCLK2_Div48 ((uint32_t)0x0000B000) +#define RCC_PCLK2_Div64 ((uint32_t)0x0000F000) +#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800) +#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800) + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK ((uint8_t)0x07) + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSICmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_RCC_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_spi.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_spi.h index ad3bac7..babd093 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_spi.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_spi.h @@ -1,154 +1,156 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_spi.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the - * SPI firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_SPI_H -#define __CH32V00x_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* SPI Init structure definition */ -typedef struct -{ - uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /* Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /* Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /* Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB bit. */ - - uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ -} SPI_InitTypeDef; - -/* SPI_data_direction */ -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) - -/* SPI_mode */ -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) - -/* SPI_data_size */ -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) - -/* SPI_Clock_Polarity */ -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) - -/* SPI_Clock_Phase */ -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) - -/* SPI_Slave_Select_management */ -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) - -/* SPI_BaudRate_Prescaler */ -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) - -/* SPI_MSB transmission */ -#define SPI_FirstBit_MSB ((uint16_t)0x0000) - -/* SPI_I2S_DMA_transfer_requests */ -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) - -/* SPI_NSS_internal_software_management */ -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) - -/* SPI_CRC_Transmit_Receive */ -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) - -/* SPI_direction_transmit_receive */ -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) - -/* SPI_I2S_interrupts_definition */ -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) -#define I2S_IT_UDR ((uint8_t)0x53) - -/* SPI_I2S_flags_definition */ -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) - -void SPI_I2S_DeInit(SPI_TypeDef *SPIx); -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); -void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); -void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); -void SPI_TransmitCRC(SPI_TypeDef *SPIx); -void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); -void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V00x_SPI_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_spi.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/01 + * Description : This file contains all the functions prototypes for the + * SPI firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_SPI_H +#define __CH32V00x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity + When using SPI slave mode to send data, the CPOL bit should be set to 1 */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB bit. */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +} SPI_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002)//When using SPI slave mode to send data, the CPOL bit should be set to 1. + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080)//not support SPI slave mode + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + +void SPI_I2S_DeInit(SPI_TypeDef *SPIx); +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef *SPIx); +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00x_SPI_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_tim.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_tim.h index 81a3d89..aca978e 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_tim.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_tim.h @@ -1,508 +1,509 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_tim.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the - * TIM firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_TIM_H -#define __CH32V00x_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* TIM Time Base Init structure definition */ -typedef struct -{ - uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /* Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint16_t TIM_Period; /* Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /* Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/* TIM Output Compare Init structure definition */ -typedef struct -{ - uint16_t TIM_OCMode; /* Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_state - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /* Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/* TIM Input Capture Init structure definition */ -typedef struct -{ - uint16_t TIM_Channel; /* Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /* Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /* Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/* BDTR structure definition */ -typedef struct -{ - uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. - This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. - This parameter can be a value of @ref Lock_level */ - - uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/* TIM_Output_Compare_and_PWM_modes */ -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) - -/* TIM_One_Pulse_Mode */ -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) - -/* TIM_Channel */ -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -/* TIM_Clock_Division_CKD */ -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) - -/* TIM_Counter_Mode */ -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) - -/* TIM_Output_Compare_Polarity */ -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) - -/* TIM_Output_Compare_N_Polarity */ -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) - -/* TIM_Output_Compare_state */ -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) - -/* TIM_Output_Compare_N_state */ -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) - -/* TIM_Capture_Compare_state */ -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) - -/* TIM_Capture_Compare_N_state */ -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) - -/* Break_Input_enable_disable */ -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) - -/* Break_Polarity */ -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) - -/* TIM_AOE_Bit_Set_Reset */ -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) - -/* Lock_level */ -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) - -/* OSSI_Off_State_Selection_for_Idle_mode_state */ -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) - -/* OSSR_Off_State_Selection_for_Run_mode_state */ -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Idle_State */ -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Output_Compare_N_Idle_State */ -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Input_Capture_Polarity */ -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) - -/* TIM_Input_Capture_Selection */ -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ - -/* TIM_Input_Capture_Prescaler */ -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ - -/* TIM_interrupt_sources */ -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) - -/* TIM_DMA_Base_address */ -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) - -/* TIM_DMA_Burst_Length */ -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) - -/* TIM_DMA_sources */ -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) - -/* TIM_External_Trigger_Prescaler */ -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) - -/* TIM_Internal_Trigger_Selection */ -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) - -/* TIM_TIx_External_Clock_Source */ -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/* TIM_External_Trigger_Polarity */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) - -/* TIM_Prescaler_Reload_Mode */ -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) - -/* TIM_Forced_Action */ -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) - -/* TIM_Encoder_Mode */ -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) - -/* TIM_Event_Source */ -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) - -/* TIM_Update_Source */ -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ - or the setting of UG bit, or an update generation \ - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ - -/* TIM_Output_Compare_Preload_State */ -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Fast_State */ -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Clear_State */ -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) - -/* TIM_Trigger_Output_Source */ -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) - -/* TIM_Slave_Mode */ -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) - -/* TIM_Master_Slave_Mode */ -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) - -/* TIM_Flags */ -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) - -/* TIM_Legacy */ -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers - -void TIM_DeInit(TIM_TypeDef *TIMx); -void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); -void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); -void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_InternalClockConfig(TIM_TypeDef *TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); -void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); -void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); -void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); -void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); -void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); -void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); -void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); -void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); -void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); -void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); -void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); -void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); -uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); -uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V00x_TIM_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_tim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_TIM_H +#define __CH32V00x_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef *TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00x_TIM_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_usart.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_usart.h index a6be0db..47487a8 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_usart.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_usart.h @@ -1,187 +1,187 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_usart.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the - * USART firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_USART_H -#define __CH32V00x_USART_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* USART Init Structure definition */ -typedef struct -{ - uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /* Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/* USART Clock Init Structure definition */ -typedef struct -{ - uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* USART_Word_Length */ -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -/* USART_Stop_Bits */ -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) - -/* USART_Parity */ -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) - -/* USART_Mode */ -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) - -/* USART_Hardware_Flow_Control */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) - -/* USART_Clock */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) - -/* USART_Clock_Polarity */ -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) - -/* USART_Clock_Phase */ -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) - -/* USART_Last_Bit */ -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) - -/* USART_Interrupt_definition */ -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) - -#define USART_IT_ORE USART_IT_ORE_ER - -/* USART_DMA_Requests */ -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) - -/* USART_WakeUp_methods */ -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) - -/* USART_LIN_Break_Detection_Length */ -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) - -/* USART_IrDA_Low_Power */ -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) - -/* USART_Flags */ -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) - -void USART_DeInit(USART_TypeDef *USARTx); -void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); -void USART_StructInit(USART_InitTypeDef *USART_InitStruct); -void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); -void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); -void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef *USARTx); -void USART_SendBreak(USART_TypeDef *USARTx); -void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); -void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00x_USART_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_usart.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * USART firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_USART_H +#define __CH32V00x_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +void USART_DeInit(USART_TypeDef *USARTx); +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); +void USART_StructInit(USART_InitTypeDef *USART_InitStruct); +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef *USARTx); +void USART_SendBreak(USART_TypeDef *USARTx); +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_USART_H */ diff --git a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_wwdg.h b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_wwdg.h index ebe3b37..30755ba 100644 --- a/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_wwdg.h +++ b/system/CH32V00x/SRC/Peripheral/inc/ch32v00x_wwdg.h @@ -1,41 +1,41 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_wwdg.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file contains all the functions prototypes for the WWDG - * firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00x_WWDG_H -#define __CH32V00x_WWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* WWDG_Prescaler */ -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) - -void WWDG_DeInit(void); -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); -void WWDG_Enable(uint8_t Counter); -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00x_WWDG_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_wwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the WWDG + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_WWDG_H +#define __CH32V00x_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_WWDG_H */ diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_adc.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_adc.c index 7c4bc87..7e732fc 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_adc.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_adc.c @@ -1,1060 +1,1060 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_adc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the ADC firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* ADC DISCNUM mask */ -#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) -#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) - -/* ADC JAUTO mask */ -#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) -#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) - -/* ADC AWDCH mask */ -#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) - -/* CTLR1 register Mask */ -#define CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) - -/* ADC ADON mask */ -#define CTLR2_ADON_Set ((uint32_t)0x00000001) -#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CTLR2_DMA_Set ((uint32_t)0x00000100) -#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) - -/* ADC RSTCAL mask */ -#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) - -/* ADC CAL mask */ -#define CTLR2_CAL_Set ((uint32_t)0x00000004) - -/* ADC SWSTART mask */ -#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) - -/* ADC EXTTRIG mask */ -#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) - -/* ADC JEXTSEL mask */ -#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTART mask */ -#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) - -/* ADC TSPD mask */ -#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) -#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) - -/* CTLR2 register Mask */ -#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) - -/* ADC SQx mask */ -#define RSQR3_SQ_Set ((uint32_t)0x0000001F) -#define RSQR2_SQ_Set ((uint32_t)0x0000001F) -#define RSQR1_SQ_Set ((uint32_t)0x0000001F) - -/* RSQR1 register Mask */ -#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define ISQR_JSQ_Set ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define ISQR_JL_Set ((uint32_t)0x00300000) -#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) -#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) - -/* ADC IDATARx registers offset */ -#define IDATAR_Offset ((uint8_t)0x28) - -/********************************************************************* - * @fn ADC_DeInit - * - * @brief Deinitializes the ADCx peripheral registers to their default - * reset values. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return none - */ -void ADC_DeInit(ADC_TypeDef *ADCx) -{ - if(ADCx == ADC1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); - } -} - -/********************************************************************* - * @fn ADC_Init - * - * @brief Initializes the ADCx peripheral according to the specified - * parameters in the ADC_InitStruct. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); - ADCx->CTLR1 = tmpreg1; - - tmpreg1 = ADCx->CTLR2; - tmpreg1 &= CTLR2_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - ADCx->CTLR2 = tmpreg1; - - tmpreg1 = ADCx->RSQR1; - tmpreg1 &= RSQR1_CLEAR_Mask; - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); - tmpreg1 |= (uint32_t)tmpreg2 << 20; - ADCx->RSQR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_StructInit - * - * @brief Fills each ADC_InitStruct member with its default value. - * - * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) -{ - ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO; - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStruct->ADC_NbrOfChannel = 1; -} - -/********************************************************************* - * @fn ADC_Cmd - * - * @brief Enables or disables the specified ADC peripheral. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_ADON_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_ADON_Reset; - } -} - -/********************************************************************* - * @fn ADC_DMACmd - * - * @brief Enables or disables the specified ADC DMA request. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_DMA_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_DMA_Reset; - } -} - -/********************************************************************* - * @fn ADC_ITConfig - * - * @brief Enables or disables the specified ADC interrupts. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)ADC_IT; - - if(NewState != DISABLE) - { - ADCx->CTLR1 |= itmask; - } - else - { - ADCx->CTLR1 &= (~(uint32_t)itmask); - } -} - -/********************************************************************* - * @fn ADC_ResetCalibration - * - * @brief Resets the selected ADC calibration registers. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return none - */ -void ADC_ResetCalibration(ADC_TypeDef *ADCx) -{ - ADCx->CTLR2 |= CTLR2_RSTCAL_Set; -} - -/********************************************************************* - * @fn ADC_GetResetCalibrationStatus - * - * @brief Gets the selected ADC reset calibration registers status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_StartCalibration - * - * @brief Starts the selected ADC calibration process. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return None - */ -void ADC_StartCalibration(ADC_TypeDef *ADCx) -{ - ADCx->CTLR2 |= CTLR2_CAL_Set; -} - -/********************************************************************* - * @fn ADC_GetCalibrationStatus - * - * @brief Gets the selected ADC calibration status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_SoftwareStartConvCmd - * - * @brief Enables or disables the selected ADC software start conversion. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartConvStatus - * - * @brief Gets the selected ADC Software start conversion Status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_DiscModeChannelCountConfig - * - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * Number - specifies the discontinuous mode regular channel - * count value(1-8). - * - * @return None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_DISCNUM_Reset; - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - ADCx->CTLR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_DiscModeCmd - * - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_DISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_DISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_RegularChannelConfig - * - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_Vrefint - ADC Channel8 selected. - * ADC_Channel_Vcalint - ADC Channel9 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_3Cycles - Sample time equal to 3 cycles. - * ADC_SampleTime_9Cycles - Sample time equal to 9 cycles. - * ADC_SampleTime_15Cycles - Sample time equal to 15 cycles. - * ADC_SampleTime_30Cycles - Sample time equal to 30 cycles. - * ADC_SampleTime_43Cycles - Sample time equal to 43 cycles. - * ADC_SampleTime_57Cycles - Sample time equal to 57 cycles. - * ADC_SampleTime_73Cycles - Sample time equal to 73 cycles. - * ADC_SampleTime_241Cycles - Sample time equal to 241 cycles. - * - * @return None - */ -void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - if(Rank < 7) - { - tmpreg1 = ADCx->RSQR3; - tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - tmpreg1 |= tmpreg2; - ADCx->RSQR3 = tmpreg1; - } - else if(Rank < 13) - { - tmpreg1 = ADCx->RSQR2; - tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - tmpreg1 |= tmpreg2; - ADCx->RSQR2 = tmpreg1; - } - else - { - tmpreg1 = ADCx->RSQR1; - tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - tmpreg1 |= tmpreg2; - ADCx->RSQR1 = tmpreg1; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigConvCmd - * - * @brief Enables or disables the ADCx conversion through external trigger. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetConversionValue - * - * @brief Returns the last ADCx conversion result data for regular channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return ADCx->RDATAR - The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) -{ - return (uint16_t)ADCx->RDATAR; -} - -/********************************************************************* - * @fn ADC_AutoInjectedConvCmd - * - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JAUTO_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JAUTO_Reset; - } -} - -/********************************************************************* - * @fn ADC_InjectedDiscModeCmd - * - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JDISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvConfig - * - * @brief Configures the ADCx external trigger for injected channels conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start - * injected conversion. - * ADC_ExternalTrigInjecConv_T1_CC3 - Timer1 capture compare3 selected. - * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. - * ADC_ExternalTrigInjecConv_T2_CC3 - Timer2 capture compare3 selected. - * ADC_ExternalTrigInjecConv_T2_CC4 - Timer2 capture compare4 selected. - * ADC_ExternalTrigInjecConv_Ext_PD1_PA2 - PD1 or PA2 selected. - * line 15 event selected. - * ADC_ExternalTrigInjecConv_None: Injected conversion started - * by software and not by external trigger. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR2; - tmpreg &= CTLR2_JEXTSEL_Reset; - tmpreg |= ADC_ExternalTrigInjecConv; - ADCx->CTLR2 = tmpreg; -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvCmd - * - * @brief Enables or disables the ADCx injected channels conversion through - * external trigger. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_SoftwareStartInjectedConvCmd - * - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartInjectedConvCmdStatus - * - * @brief Gets the selected ADC Software start injected conversion Status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_InjectedChannelConfig - * - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_Vrefint - ADC Channel8 selected. - * ADC_Channel_Vcalint - ADC Channel9 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_3Cycles - Sample time equal to 3 cycles. - * ADC_SampleTime_9Cycles - Sample time equal to 9 cycles. - * ADC_SampleTime_15Cycles - Sample time equal to 15 cycles. - * ADC_SampleTime_30Cycles - Sample time equal to 30 cycles. - * ADC_SampleTime_43Cycles - Sample time equal to 43 cycles. - * ADC_SampleTime_57Cycles - Sample time equal to 57 cycles. - * ADC_SampleTime_73Cycles - Sample time equal to 73 cycles. - * ADC_SampleTime_241Cycles - Sample time equal to 241 cycles. - * - * @return None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - tmpreg1 = ADCx->ISQR; - tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; - tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 |= tmpreg2; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_InjectedSequencerLengthConfig - * - * @brief Configures the sequencer length for injected channels. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * Length - The sequencer length. - * This parameter must be a number between 1 to 4. - * - * @return None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->ISQR; - tmpreg1 &= ISQR_JL_Reset; - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_SetInjectedOffset - * - * @brief Set the injected channels conversion value offset. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InjectedChannel: the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * Offset - the offset value for the selected ADC injected channel. - * This parameter must be a 12bit value. - * - * @return None - */ -void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - *(__IO uint32_t *)tmp = (uint32_t)Offset; -} - -/********************************************************************* - * @fn ADC_GetInjectedConversionValue - * - * @brief Returns the ADC injected channel conversion result. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InjectedChannel - the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * - * @return tmp - The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + IDATAR_Offset; - - return (uint16_t)(*(__IO uint32_t *)tmp); -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogCmd - * - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_AnalogWatchdog - the ADC analog watchdog configuration. - * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a - * single regular channel. - * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a - * single injected channel. - * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog - * on a single regular or injected channel. - * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all - * regular channel. - * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all - * injected channel. - * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on - * all regular and injected channels. - * ADC_AnalogWatchdog_None - No channel guarded by the analog - * watchdog. - * - * @return none - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDMode_Reset; - tmpreg |= ADC_AnalogWatchdog; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogThresholdsConfig - * - * @brief Configures the high and low thresholds of the analog watchdog. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * HighThreshold - the ADC analog watchdog High threshold value. - * This parameter must be a 10bit value. - * LowThreshold - the ADC analog watchdog Low threshold value. - * This parameter must be a 10bit value. - * - * @return none - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - ADCx->WDHTR = HighThreshold; - ADCx->WDLTR = LowThreshold; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogSingleChannelConfig - * - * @brief Configures the analog watchdog guarded single channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_Vrefint - ADC Channel8 selected. - * ADC_Channel_Vcalint - ADC Channel9 selected. - * - * @return None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDCH_Reset; - tmpreg |= ADC_Channel; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_GetFlagStatus - * - * @brief Checks whether the specified ADC flag is set or not. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to check. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearFlag - * - * @brief Clears the ADCx's pending flags. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to clear. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return none - */ -void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - ADCx->STATR = ~(uint32_t)ADC_FLAG; -} - -/********************************************************************* - * @fn ADC_GetITStatus - * - * @brief Checks whether the specified ADC interrupt has occurred or not. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt source to check. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return ITStatus: SET or RESET. - */ -ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - itmask = ADC_IT >> 8; - enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); - - if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearITPendingBit - * - * @brief Clears the ADCx's interrupt pending bits. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt pending bit to clear. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return none - */ -void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)(ADC_IT >> 8); - ADCx->STATR = ~(uint32_t)itmask; -} - -/********************************************************************* - * @fn ADC_Calibration_Vol - * - * @brief ADC calibration voltage. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_CALVOL - ADC calibration voltage. - * ADC_CALVOL_50PERCENT - 50% VDD. - * ADC_CALVOL_75PERCENT - 75% VDD. - * - * @return none - */ -void ADC_Calibration_Vol(ADC_TypeDef *ADCx, uint32_t ADC_CALVOL) -{ - ADCx->CTLR1 &= ~(uint32_t)(3<<25); - ADCx->CTLR1 |= ADC_CALVOL; -} - -/********************************************************************* - * @fn ADC_ExternalTrig_DLY - * - * @brief ADC external trigger sources delay channels and time. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * channel - ADC external trigger sources delay channels. - * ADC_ExternalTrigRegul_DLY - External trigger sources regular. - * ADC_ExternalTrigInjec_DLY - External trigger sources injected. - * DelayTim - ADC external trigger sources delay time - * This parameter must range from 0 to 0x1FF. - * - * @return none - */ -void ADC_ExternalTrig_DLY(ADC_TypeDef *ADCx, uint32_t channel, uint16_t DelayTim) -{ - ADCx->DLYR &= ~(uint32_t)(0x2FF); - ADCx->DLYR |= channel; - ADCx->DLYR |= DelayTim; -} - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_adc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the ADC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_ResetCalibration + * + * @brief Resets the selected ADC calibration registers. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_ResetCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_RSTCAL_Set; +} + +/********************************************************************* + * @fn ADC_GetResetCalibrationStatus + * + * @brief Gets the selected ADC reset calibration registers status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_StartCalibration + * + * @brief Starts the selected ADC calibration process. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return None + */ +void ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_CAL_Set; +} + +/********************************************************************* + * @fn ADC_GetCalibrationStatus + * + * @brief Gets the selected ADC calibration status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_Vrefint - ADC Channel8 selected. + * ADC_Channel_Vcalint - ADC Channel9 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_3Cycles - Sample time equal to 3 cycles. + * ADC_SampleTime_9Cycles - Sample time equal to 9 cycles. + * ADC_SampleTime_15Cycles - Sample time equal to 15 cycles. + * ADC_SampleTime_30Cycles - Sample time equal to 30 cycles. + * ADC_SampleTime_43Cycles - Sample time equal to 43 cycles. + * ADC_SampleTime_57Cycles - Sample time equal to 57 cycles. + * ADC_SampleTime_73Cycles - Sample time equal to 73 cycles. + * ADC_SampleTime_241Cycles - Sample time equal to 241 cycles. + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_CC3 - Timer1 capture compare3 selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_CC3 - Timer2 capture compare3 selected. + * ADC_ExternalTrigInjecConv_T2_CC4 - Timer2 capture compare4 selected. + * ADC_ExternalTrigInjecConv_Ext_PD1_PA2 - PD1 or PA2 selected. + * line 15 event selected. + * ADC_ExternalTrigInjecConv_None: Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_Vrefint - ADC Channel8 selected. + * ADC_Channel_Vcalint - ADC Channel9 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_3Cycles - Sample time equal to 3 cycles. + * ADC_SampleTime_9Cycles - Sample time equal to 9 cycles. + * ADC_SampleTime_15Cycles - Sample time equal to 15 cycles. + * ADC_SampleTime_30Cycles - Sample time equal to 30 cycles. + * ADC_SampleTime_43Cycles - Sample time equal to 43 cycles. + * ADC_SampleTime_57Cycles - Sample time equal to 57 cycles. + * ADC_SampleTime_73Cycles - Sample time equal to 73 cycles. + * ADC_SampleTime_241Cycles - Sample time equal to 241 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 10bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 10bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 10bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_Vrefint - ADC Channel8 selected. + * ADC_Channel_Vcalint - ADC Channel9 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return ITStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn ADC_Calibration_Vol + * + * @brief ADC calibration voltage. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_CALVOL - ADC calibration voltage. + * ADC_CALVOL_50PERCENT - 50% VDD. + * ADC_CALVOL_75PERCENT - 75% VDD. + * + * @return none + */ +void ADC_Calibration_Vol(ADC_TypeDef *ADCx, uint32_t ADC_CALVOL) +{ + ADCx->CTLR1 &= ~(uint32_t)(3<<25); + ADCx->CTLR1 |= ADC_CALVOL; +} + +/********************************************************************* + * @fn ADC_ExternalTrig_DLY + * + * @brief ADC external trigger sources delay channels and time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * channel - ADC external trigger sources delay channels. + * ADC_ExternalTrigRegul_DLY - External trigger sources regular. + * ADC_ExternalTrigInjec_DLY - External trigger sources injected. + * DelayTim - ADC external trigger sources delay time + * This parameter must range from 0 to 0x1FF. + * + * @return none + */ +void ADC_ExternalTrig_DLY(ADC_TypeDef *ADCx, uint32_t channel, uint16_t DelayTim) +{ + ADCx->DLYR &= ~(uint32_t)(0x3FF); + ADCx->DLYR |= channel; + ADCx->DLYR |= DelayTim; +} + diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_dbgmcu.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_dbgmcu.c index 301dfa5..92965cb 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_dbgmcu.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_dbgmcu.c @@ -1,101 +1,116 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_dbgmcu.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the DBGMCU firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - - -#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) - -/********************************************************************* - * @fn DBGMCU_GetREVID - * - * @brief Returns the device revision identifier. - * - * @return Revision identifier. - */ -uint32_t DBGMCU_GetREVID(void) -{ - return ((*(uint32_t *)0x1FFFF7C4) >> 16); -} - -/********************************************************************* - * @fn DBGMCU_GetDEVID - * - * @brief Returns the device identifier. - * - * @return Device identifier. - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return ((*(uint32_t *)0x1FFFF7C4) & IDCODE_DEVID_MASK); -} - -/********************************************************************* - * @fn __get_DEBUG_CR - * - * @brief Return the DEBUGE Control Register - * - * @return DEBUGE Control value - */ -uint32_t __get_DEBUG_CR(void) -{ - uint32_t result; - - __asm volatile("csrr %0,""0x7C0" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_DEBUG_CR - * - * @brief Set the DEBUGE Control Register - * - * @param value - set DEBUGE Control value - * - * @return none - */ -void __set_DEBUG_CR(uint32_t value) -{ - __asm volatile("csrw 0x7C0, %0" : : "r"(value)); -} - - -/********************************************************************* - * @fn DBGMCU_Config - * - * @brief Configures the specified peripheral and low power mode behavior - * when the MCU under Debug mode. - * - * @param DBGMCU_Periph - specifies the peripheral and low power mode. - * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted - * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted - * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted - * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - uint32_t val; - - if(NewState != DISABLE) - { - __set_DEBUG_CR(DBGMCU_Periph); - } - else - { - val = __get_DEBUG_CR(); - val &= ~(uint32_t)DBGMCU_Periph; - __set_DEBUG_CR(val); - } - -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_dbgmcu.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the DBGMCU firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + + +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return ((*(uint32_t *)0x1FFFF7C4) >> 16); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return ((*(uint32_t *)0x1FFFF7C4) & IDCODE_DEVID_MASK); +} + +/********************************************************************* + * @fn __get_DEBUG_CR + * + * @brief Return the DEBUGE Control Register + * + * @return DEBUGE Control value + */ +uint32_t __get_DEBUG_CR(void) +{ + uint32_t result; + + __asm volatile("csrr %0,""0x7C0" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_DEBUG_CR + * + * @brief Set the DEBUGE Control Register + * + * @param value - set DEBUGE Control value + * + * @return none + */ +void __set_DEBUG_CR(uint32_t value) +{ + __asm volatile("csrw 0x7C0, %0" : : "r"(value)); +} + + +/********************************************************************* + * @fn DBGMCU_Config + * + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * + * @param DBGMCU_Periph - specifies the peripheral and low power mode. + * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted + * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted + * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted + * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + uint32_t val; + + if(NewState != DISABLE) + { + __set_DEBUG_CR(DBGMCU_Periph); + } + else + { + val = __get_DEBUG_CR(); + val &= ~(uint32_t)DBGMCU_Periph; + __set_DEBUG_CR(val); + } +} +/********************************************************************* + * @fn DBGMCU_GetCHIPID + * + * @brief Returns the CHIP identifier. + * + * @return Device identifier. + * ChipID List- + * CH32V003F4P6-0x003005x0 + * CH32V003F4U6-0x003105x0 + * CH32V003A4M6-0x003205x0 + * CH32V003J4M6-0x003305x0 + */ +uint32_t DBGMCU_GetCHIPID( void ) +{ + return( *( uint32_t * )0x1FFFF7C4 ); +} diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_dma.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_dma.c index 0605284..d1342a2 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_dma.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_dma.c @@ -1,416 +1,416 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_dma.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the DMA firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) -#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) -#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) -#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) -#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) -#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) -#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) - -/* DMA2 FLAG mask */ -#define FLAG_Mask ((uint32_t)0x10000000) - -/* DMA registers Masks */ -#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) - -/********************************************************************* - * @fn DMA_DeInit - * - * @brief Deinitializes the DMAy Channelx registers to their default - * reset values. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * - * @return none - */ -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) -{ - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - DMAy_Channelx->CFGR = 0; - DMAy_Channelx->CNTR = 0; - DMAy_Channelx->PADDR = 0; - DMAy_Channelx->MADDR = 0; - if(DMAy_Channelx == DMA1_Channel1) - { - DMA1->INTFCR |= DMA1_Channel1_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel2) - { - DMA1->INTFCR |= DMA1_Channel2_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel3) - { - DMA1->INTFCR |= DMA1_Channel3_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel4) - { - DMA1->INTFCR |= DMA1_Channel4_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel5) - { - DMA1->INTFCR |= DMA1_Channel5_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel6) - { - DMA1->INTFCR |= DMA1_Channel6_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel7) - { - DMA1->INTFCR |= DMA1_Channel7_IT_Mask; - } -} - -/********************************************************************* - * @fn DMA_Init - * - * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - tmpreg = DMAy_Channelx->CFGR; - tmpreg &= CFGR_CLEAR_Mask; - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - DMAy_Channelx->CFGR = tmpreg; - DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; - DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; - DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/********************************************************************* - * @fn DMA_StructInit - * - * @brief Fills each DMA_InitStruct member with its default value. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) -{ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - DMA_InitStruct->DMA_BufferSize = 0; - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/********************************************************************* - * @fn DMA_Cmd - * - * @brief Enables or disables the specified DMAy Channelx. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_CFGR1_EN; - } - else - { - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - } -} - -/********************************************************************* - * @fn DMA_ITConfig - * - * @brief Enables or disables the specified DMAy Channelx interrupts. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * DMA_IT - specifies the DMA interrupts sources to be enabled - * or disabled. - * DMA_IT_TC - Transfer complete interrupt mask - * DMA_IT_HT - Half transfer interrupt mask - * DMA_IT_TE - Transfer error interrupt mask - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_IT; - } - else - { - DMAy_Channelx->CFGR &= ~DMA_IT; - } -} - -/********************************************************************* - * @fn DMA_SetCurrDataCounter - * - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * DataNumber - The number of data units in the current DMAy Channelx - * transfer. - * - * @return none - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) -{ - DMAy_Channelx->CNTR = DataNumber; -} - -/********************************************************************* - * @fn DMA_GetCurrDataCounter - * - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * - * @return DataNumber - The number of remaining data units in the current - * DMAy Channelx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) -{ - return ((uint16_t)(DMAy_Channelx->CNTR)); -} - -/********************************************************************* - * @fn DMA_GetFlagStatus - * - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * - * @return The new state of DMAy_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - tmpreg = DMA1->INTFR; - - if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearFlag - * - * @brief Clears the DMAy Channelx's pending flags. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * - * @return none - */ -void DMA_ClearFlag(uint32_t DMAy_FLAG) -{ - - DMA1->INTFCR = DMAy_FLAG; - -} - -/********************************************************************* - * @fn DMA_GetITStatus - * - * @brief Checks whether the specified DMAy Channelx interrupt has - * occurred or not. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * - * @return The new state of DMAy_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMAy_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - tmpreg = DMA1->INTFR; - - if((tmpreg & DMAy_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearITPendingBit - * - * @brief Clears the DMAy Channelx's interrupt pending bits. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * - * @return none - */ -void DMA_ClearITPendingBit(uint32_t DMAy_IT) -{ - DMA1->INTFCR = DMAy_IT; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_dma.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the DMA firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + + DMA1->INTFCR = DMAy_FLAG; + +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + DMA1->INTFCR = DMAy_IT; +} diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_exti.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_exti.c index b3fd8ff..b23da14 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_exti.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_exti.c @@ -1,182 +1,182 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_exti.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the EXTI firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -/* No interrupt selected */ -#define EXTI_LINENONE ((uint32_t)0x00000) - -/********************************************************************* - * @fn EXTI_DeInit - * - * @brief Deinitializes the EXTI peripheral registers to their default - * reset values. - * - * @return none. - */ -void EXTI_DeInit(void) -{ - EXTI->INTENR = 0x00000000; - EXTI->EVENR = 0x00000000; - EXTI->RTENR = 0x00000000; - EXTI->FTENR = 0x00000000; - EXTI->INTFR = 0x000FFFFF; -} - -/********************************************************************* - * @fn EXTI_Init - * - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) -{ - uint32_t tmp = 0; - - tmp = (uint32_t)EXTI_BASE; - if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; - if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/********************************************************************* - * @fn EXTI_StructInit - * - * @brief Fills each EXTI_InitStruct member with its reset value. - * - * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/********************************************************************* - * @fn EXTI_GenerateSWInterrupt - * - * @brief Generates a Software interrupt. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none. - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - EXTI->SWIEVR |= EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetFlagStatus - * - * @brief Checks whether the specified EXTI line flag is set or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearFlag - * - * @brief Clears the EXTI's line pending flags. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetITStatus - * - * @brief Checks whether the specified EXTI line is asserted or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = EXTI->INTENR & EXTI_Line; - if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearITPendingBit - * - * @brief Clears the EXTI's line pending bits. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_exti.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the EXTI firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x000FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_flash.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_flash.c index 2ebb99d..238c3f2 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_flash.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_flash.c @@ -1,837 +1,1066 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_flash.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the FLASH firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -/* Flash Access Control Register bits */ -#define ACR_LATENCY_Mask ((uint32_t)0x00000038) - -/* Flash Control Register bits */ -#define CR_PG_Set ((uint32_t)0x00000001) -#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) -#define CR_PAGE_PG ((uint32_t)0x00010000) -#define CR_PAGE_ER ((uint32_t)0x00020000) -#define CR_BUF_LOAD ((uint32_t)0x00040000) -#define CR_BUF_RST ((uint32_t)0x00080000) - -/* FLASH Status Register bits */ -#define SR_BSY ((uint32_t)0x00000001) -#define SR_WRPRTERR ((uint32_t)0x00000010) -#define SR_EOP ((uint32_t)0x00000020) - -/* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) - -/* FLASH Keys */ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) - -/* FLASH BANK address */ -#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) - -/* Delay definition */ -#define EraseTimeout ((uint32_t)0x000B0000) -#define ProgramTimeout ((uint32_t)0x00002000) - -/* Flash Program Vaild Address */ -#define ValidAddrStart (FLASH_BASE) -#define ValidAddrEnd (FLASH_BASE + 0x4000) - -/******************************************************************************** - * @fn FLASH_SetLatency - * - * @brief Sets the code latency value. - * - * @param FLASH_Latency - specifies the FLASH Latency value. - * FLASH_Latency_0 - FLASH Zero Latency cycle - * FLASH_Latency_1 - FLASH One Latency cycle - * FLASH_Latency_2 - FLASH Two Latency cycles - * - * @return None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - tmpreg = FLASH->ACTLR; - tmpreg &= ACR_LATENCY_Mask; - tmpreg |= FLASH_Latency; - FLASH->ACTLR = tmpreg; -} - -/******************************************************************************** - * @fn FLASH_Unlock - * - * @brief Unlocks the FLASH Program Erase Controller. - * - * @return None - */ -void FLASH_Unlock(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -/******************************************************************************** - * @fn FLASH_Lock - * - * @brief Locks the FLASH Program Erase Controller. - * - * @return None - */ -void FLASH_Lock(void) -{ - FLASH->CTLR |= CR_LOCK_Set; -} - -/******************************************************************************** - * @fn FLASH_ErasePage - * - * @brief Erases a specified FLASH page(1KB). - * - * @param Page_Address - The page address to be erased. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_PER_Set; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_PER_Reset; - } - - return status; -} - -/******************************************************************************** - * @fn FLASH_EraseAllPages - * - * @brief Erases all FLASH pages. - * - * @return FLASH Status - The returned value can be:FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_MER_Set; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_MER_Reset; - } - - return status; -} - -/******************************************************************************** - * @fn FLASH_EraseOptionBytes - * - * @brief Erases the FLASH option bytes. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseOptionBytes(void) -{ - uint16_t rdptmp = RDP_Key; - - FLASH_Status status = FLASH_COMPLETE; - if(FLASH_GetReadOutProtectionStatus() != RESET) - { - rdptmp = 0x00; - } - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR &= CR_OPTER_Reset; - FLASH->CTLR |= CR_OPTPG_Set; - OB->RDPR = (uint16_t)rdptmp; - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - } - return status; -} - -/********************************************************************* - * @fn FLASH_ProgramWord - * - * @brief Programs a word at a specified address. - * - * @param Address - specifies the address to be programmed. - * Data - specifies the data to be programmed. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_PG_Set; - - *(__IO uint16_t *)Address = (uint16_t)Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - tmp = Address + 2; - *(__IO uint16_t *)tmp = Data >> 16; - status = FLASH_WaitForLastOperation(ProgramTimeout); - FLASH->CTLR &= CR_PG_Reset; - } - else - { - FLASH->CTLR &= CR_PG_Reset; - } - } - - return status; -} - -/********************************************************************* - * @fn FLASH_ProgramHalfWord - * - * @brief Programs a half word at a specified address. - * - * @param Address - specifies the address to be programmed. - * Data - specifies the data to be programmed. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_PG_Set; - *(__IO uint16_t *)Address = Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - FLASH->CTLR &= CR_PG_Reset; - } - - return status; -} - -/********************************************************************* - * @fn FLASH_ProgramOptionByteData - * - * @brief Programs a half word at a specified Option Byte Data address. - * - * @param Address - specifies the address to be programmed. - * Data - specifies the data to be programmed. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - FLASH->CTLR |= CR_OPTPG_Set; - *(__IO uint16_t *)Address = Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - - return status; -} - -/********************************************************************* - * @fn FLASH_EnableWriteProtection - * - * @brief Write protects the desired sectors - * - * @param FLASH_Sectors - specifies the address of the pages to be write protected. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) -{ - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF; - - FLASH_Status status = FLASH_COMPLETE; - - FLASH_Pages = (uint32_t)(~FLASH_Pages); - WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); - WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); - - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - FLASH->CTLR |= CR_OPTPG_Set; - if(WRP0_Data != 0xFF) - { - OB->WRPR0 = WRP0_Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) - { - OB->WRPR1 = WRP1_Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - return status; -} - -/********************************************************************* - * @fn FLASH_ReadOutProtection - * - * @brief Enables or disables the read out protection. - * - * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->CTLR &= CR_OPTER_Reset; - FLASH->CTLR |= CR_OPTPG_Set; - if(NewState != DISABLE) - { - OB->RDPR = 0x00; - } - else - { - OB->RDPR = RDP_Key; - } - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTER_Reset; - } - } - } - return status; -} - -/********************************************************************* - * @fn FLASH_UserOptionByteConfig - * - * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. - * - * @param OB_IWDG - Selects the IWDG mode - * OB_IWDG_SW - Software IWDG selected - * OB_IWDG_HW - Hardware IWDG selected - * OB_STOP - Reset event when entering STOP mode. - * OB_STOP_NoRST - No reset generated when entering in STOP - * OB_STOP_RST - Reset generated when entering in STOP - * OB_STDBY - Reset event when entering Standby mode. - * OB_STDBY_NoRST - No reset generated when entering in STANDBY - * OB_STDBY_RST - Reset generated when entering in STANDBY - * OB_RST - Selects the reset IO mode and Ignore delay time - * OB_RST_NoEN - Reset IO disable (PD7) - * OB_RST_EN_DT12ms - Reset IO enable (PD7) and Ignore delay time 12ms - * OB_RST_EN_DT1ms - Reset IO enable (PD7) and Ignore delay time 1ms - * OB_RST_EN_DT128ms - Reset IO enable (PD7) and Ignore delay time 128ms - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY, uint16_t OB_RST) -{ - FLASH_Status status = FLASH_COMPLETE; - - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_OPTPG_Set; - - OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | (uint16_t)(OB_RST | (uint16_t)0xE0))); - - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - return status; -} - -/********************************************************************* - * @fn FLASH_GetUserOptionByte - * - * @brief Returns the FLASH User Option Bytes values. - * - * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint32_t FLASH_GetUserOptionByte(void) -{ - return (uint32_t)(FLASH->OBR >> 2); -} - -/********************************************************************* - * @fn FLASH_GetWriteProtectionOptionByte - * - * @brief Returns the FLASH Write Protection Option Bytes Register value. - * - * @return The FLASH Write Protection Option Bytes Register value. - */ -uint32_t FLASH_GetWriteProtectionOptionByte(void) -{ - return (uint32_t)(FLASH->WPR); -} - -/********************************************************************* - * @fn FLASH_GetReadOutProtectionStatus - * - * @brief Checks whether the FLASH Read Out Protection Status is set or not. - * - * @return FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetReadOutProtectionStatus(void) -{ - FlagStatus readoutstatus = RESET; - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - readoutstatus = SET; - } - else - { - readoutstatus = RESET; - } - return readoutstatus; -} - -/********************************************************************* - * @fn FLASH_ITConfig - * - * @brief Enables or disables the specified FLASH interrupts. - * - * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. - * FLASH_IT_ERROR - FLASH Error Interrupt - * FLASH_IT_EOP - FLASH end of operation Interrupt - * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). - * - * @return FLASH Prefetch Buffer Status (SET or RESET). - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - FLASH->CTLR |= FLASH_IT; - } - else - { - FLASH->CTLR &= ~(uint32_t)FLASH_IT; - } -} - -/********************************************************************* - * @fn FLASH_GetFlagStatus - * - * @brief Checks whether the specified FLASH flag is set or not. - * - * @param FLASH_FLAG - specifies the FLASH flag to check. - * FLASH_FLAG_BSY - FLASH Busy flag - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * FLASH_FLAG_OPTERR - FLASH Option Byte error flag - * - * @return The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - return bitstatus; -} - -/********************************************************************* - * @fn FLASH_ClearFlag - * - * @brief Clears the FLASH's pending flags. - * - * @param FLASH_FLAG - specifies the FLASH flags to clear. - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * - * @return none - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - FLASH->STATR = FLASH_FLAG; -} - -/********************************************************************* - * @fn FLASH_GetStatus - * - * @brief Returns the FLASH Status. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_GetBank1Status - * - * @brief Returns the FLASH Bank1 Status. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetBank1Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_WaitForLastOperation - * - * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_WaitForLastBank1Operation - * - * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_Unlock_Fast - * - * @brief Unlocks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Unlock_Fast(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - - /* Fast program mode unlock */ - FLASH->MODEKEYR = FLASH_KEY1; - FLASH->MODEKEYR = FLASH_KEY2; -} - -/********************************************************************* - * @fn FLASH_Unlock_Fast - * - * @brief Unlocks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Lock_Fast(void) -{ - FLASH->CTLR |= CR_LOCK_Set; -} - -/********************************************************************* - * @fn FLASH_BufReset - * - * @brief Flash Buffer reset. - * - * @return none - */ -void FLASH_BufReset(void) -{ - FLASH->CTLR |= CR_PAGE_PG; - FLASH->CTLR |= CR_BUF_RST; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; -} - -/********************************************************************* - * @fn FLASH_BufLoad - * - * @brief Flash Buffer load(4Byte). - * - * @param Address - specifies the address to be programmed. - * Data0 - specifies the data0 to be programmed. - * - * @return none - */ -void FLASH_BufLoad(uint32_t Address, uint32_t Data0) -{ - if((Address >= ValidAddrStart) && (Address < ValidAddrEnd)) - { - FLASH->CTLR |= CR_PAGE_PG; - *(__IO uint32_t *)(Address) = Data0; - FLASH->CTLR |= CR_BUF_LOAD; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; - } -} - -/********************************************************************* - * @fn FLASH_ErasePage_Fast - * - * @brief Erases a specified FLASH page (1page = 64Byte). - * - * @param Page_Address - The page address to be erased. - * - * @return none - */ -void FLASH_ErasePage_Fast(uint32_t Page_Address) -{ - if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) - { - FLASH->CTLR |= CR_PAGE_ER; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_ER; - } -} - -/********************************************************************* - * @fn FLASH_ProgramPage_Fast - * - * @brief Program a specified FLASH page (1page = 64Byte). - * - * @param Page_Address - The page address to be programed. - * - * @return none - */ -void FLASH_ProgramPage_Fast(uint32_t Page_Address) -{ - if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) - { - FLASH->CTLR |= CR_PAGE_PG; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; - } -} - -/********************************************************************* - * @fn SystemReset_StartMode - * - * @brief Start mode after system reset. - * - * @param Mode - Start mode. - * Start_Mode_USER - USER start after system reset - * Start_Mode_BOOT - Boot start after system reset - * @return none - */ -void SystemReset_StartMode(uint32_t Mode) -{ - FLASH_Unlock(); - - FLASH->BOOT_MODEKEYR = FLASH_KEY1; - FLASH->BOOT_MODEKEYR = FLASH_KEY2; - - FLASH->STATR &= ~(1<<14); - if(Mode == Start_Mode_BOOT){ - FLASH->STATR |= (1<<14); - } - - FLASH_Lock(); -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_flash.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/03/15 + * Description : This file provides all the FLASH firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0xFFFFFFFC) + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FLOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BUF_LOAD ((uint32_t)0x00040000) +#define CR_BUF_RST ((uint32_t)0x00080000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x4000) + +/* FLASH Size */ +#define Size_64B 0x40 +#define Size_1KB 0x400 + +/******************************************************************************** + * @fn FLASH_SetLatency + * + * @brief Sets the code latency value. + * + * @param FLASH_Latency - specifies the FLASH Latency value. + * FLASH_Latency_0 - FLASH Zero Latency cycle + * FLASH_Latency_1 - FLASH One Latency cycle + * FLASH_Latency_2 - FLASH Two Latency cycles + * + * @return None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + tmpreg = FLASH->ACTLR; + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + FLASH->ACTLR = tmpreg; +} + +/******************************************************************************** + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/******************************************************************************** + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/******************************************************************************** + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page(1KB). + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - The returned value can be:FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + + FLASH_Status status = FLASH_COMPLETE; + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= CR_OPTER_Reset; + FLASH->CTLR |= CR_OPTPG_Set; + OB->RDPR = (uint16_t)rdptmp; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + } + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramWord + * + * @brief Programs a word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + + *(__IO uint16_t *)Address = (uint16_t)Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + tmp = Address + 2; + *(__IO uint16_t *)tmp = Data >> 16; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + else + { + FLASH->CTLR &= CR_PG_Reset; + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramHalfWord + * + * @brief Programs a half word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + *(__IO uint16_t *)Address = Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramOptionByteData + * + * @brief Programs a half word at a specified Option Byte Data address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + FLASH->CTLR |= CR_OPTPG_Set; + *(__IO uint16_t *)Address = Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Sectors - specifies the address of the pages to be write protected. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + FLASH->CTLR |= CR_OPTPG_Set; + if(WRP0_Data != 0xFF) + { + OB->WRPR0 = WRP0_Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRPR1 = WRP1_Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + return status; +} + +/********************************************************************* + * @fn FLASH_ReadOutProtection + * + * @brief Enables or disables the read out protection. + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= CR_OPTER_Reset; + FLASH->CTLR |= CR_OPTPG_Set; + if(NewState != DISABLE) + { + OB->RDPR = 0x00; + } + else + { + OB->RDPR = RDP_Key; + } + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTER_Reset; + } + } + } + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. + * + * @param OB_IWDG - Selects the IWDG mode + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY + * OB_STDBY_RST - Reset generated when entering in STANDBY + * OB_RST - Selects the reset IO mode and Ignore delay time + * OB_RST_NoEN - Reset IO disable (PD7) + * OB_RST_EN_DT12ms - Reset IO enable (PD7) and Ignore delay time 12ms + * OB_RST_EN_DT1ms - Reset IO enable (PD7) and Ignore delay time 1ms + * OB_RST_EN_DT128us - Reset IO enable (PD7) and Ignore delay time 128us + * OB_PowerON_Start_Mode - Selects start mode after power on. + * OB_PowerON_Start_Mode_BOOT - from Boot after power on. + * OB_PowerON_Start_Mode_USER - from User after power on. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STDBY, uint16_t OB_RST, uint16_t OB_PowerON_Start_Mode) +{ + FLASH_Status status = FLASH_COMPLETE; + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_OPTPG_Set; + + OB->USER = OB_IWDG | (uint16_t)(OB_STDBY | (uint16_t)(OB_RST | (uint16_t)(OB_PowerON_Start_Mode| (uint16_t)0xC2))); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt + * FLASH_IT_EOP - FLASH end of operation Interrupt + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + FLASH->STATR = FLASH_FLAG; +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_FLOCK_Set; +} + +/********************************************************************* + * @fn FLASH_BufReset + * + * @brief Flash Buffer reset. + * + * @return none + */ +void FLASH_BufReset(void) +{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_BufLoad + * + * @brief Flash Buffer load(4Byte). + * + * @param Address - specifies the address to be programmed. + * Data0 - specifies the data0 to be programmed. + * + * @return none + */ +void FLASH_BufLoad(uint32_t Address, uint32_t Data0) +{ + if((Address >= ValidAddrStart) && (Address < ValidAddrEnd)) + { + FLASH->CTLR |= CR_PAGE_PG; + *(__IO uint32_t *)(Address) = Data0; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + } +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 64Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) + { + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_ER; + } +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 64Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address) +{ + if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) + { + FLASH->CTLR |= CR_PAGE_PG; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + } +} + +/********************************************************************* + * @fn SystemReset_StartMode + * + * @brief Start mode after system reset. + * + * @param Mode - Start mode. + * Start_Mode_USER - USER start after system reset + * Start_Mode_BOOT - Boot start after system reset + * @return none + */ +void SystemReset_StartMode(uint32_t Mode) +{ + FLASH_Unlock(); + + FLASH->BOOT_MODEKEYR = FLASH_KEY1; + FLASH->BOOT_MODEKEYR = FLASH_KEY2; + + FLASH->STATR &= ~(1<<14); + if(Mode == Start_Mode_BOOT){ + FLASH->STATR |= (1<<14); + } + + FLASH_Lock(); +} + +/********************************************************************* + * @fn ROM_ERASE + * + * @brief Select erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%64 == 0). + * Cnt - Erases count. + * Erase_Size - Erases size select.The returned value can be: + * Size_1KB, Size_64B. + * + * @return none. + */ +static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) +{ + do{ + if(Erase_Size == Size_1KB) + { + FLASH->CTLR |= CR_PER_Set; + } + else if(Erase_Size == Size_64B) + { + FLASH->CTLR |= CR_PAGE_ER; + } + + FLASH->ADDR = StartAddr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + + if(Erase_Size == Size_1KB) + { + FLASH->CTLR &= ~CR_PER_Set; + StartAddr += Size_1KB; + } + else if(Erase_Size == Size_64B) + { + FLASH->CTLR &= ~CR_PAGE_ER; + StartAddr += Size_64B; + } + }while(--Cnt); +} + +/********************************************************************* + * @fn FLASH_ROM_ERASE + * + * @brief Erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%64 == 0). + * Length - Erases Flash start Length(Length%64 == 0). + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_ERASE( uint32_t StartAddr, uint32_t Length ) +{ + uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_64B-1)) || (Length & (Size_64B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + Addr0 = StartAddr; + + if(Length >= Size_1KB) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_64B) + { + Length0 = Length; + } + + /* Erase 1KB */ + if(Length0 >= Size_1KB) //front + { + Length = Length0; + if(Addr0 & (Size_1KB - 1)) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB); + } + + if(Length1 >= Size_1KB) //back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_1KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1))); + Length1 = (StartAddr + Length1) & (Size_1KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB); + } + + /* Erase 64B */ + if(Length0)//front + { + ROM_ERASE(Addr0, (Length0 >> 6), Size_64B); + } + + if(Length1)//back + { + ROM_ERASE(Addr1, (Length1 >> 6), Size_64B); + } + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + +/********************************************************************* + * @fn FLASH_ROM_WRITE + * + * @brief Writes a specified FLASH . + * + * @param StartAddr - Writes Flash start address(StartAddr%64 == 0). + * Length - Writes Flash start Length(Length%64 == 0). + * pbuf - Writes Flash value buffer. + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_WRITE( uint32_t StartAddr, uint32_t *pbuf, uint32_t Length ) +{ + uint32_t i, adr; + uint8_t size; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_64B-1)) || (Length & (Size_64B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + adr = StartAddr; + i = Length >> 6; + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + do{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + size = 16; + while(size) + { + *(__IO uint32_t *)(StartAddr) = *(uint32_t *)pbuf; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + + StartAddr += 4; + pbuf += 1; + size -= 1; + } + + FLASH->CTLR |= CR_PAGE_PG; + FLASH->ADDR = adr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + + adr += 64; + }while(--i); + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_gpio.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_gpio.c index c1168f0..dfa297e 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_gpio.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_gpio.c @@ -1,458 +1,477 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_gpio.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the GPIO firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* MASK */ -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) - -/********************************************************************* - * @fn GPIO_DeInit - * - * @brief Deinitializes the GPIOx peripheral registers to their default - * reset values. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @return none - */ -void GPIO_DeInit(GPIO_TypeDef *GPIOx) -{ - if(GPIOx == GPIOA) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); - } - else if(GPIOx == GPIOC) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); - } - else if(GPIOx == GPIOD) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); - } -} - -/********************************************************************* - * @fn GPIO_AFIODeInit - * - * @brief Deinitializes the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * - * @return none - */ -void GPIO_AFIODeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); -} - -/********************************************************************* - * @fn GPIO_Init - * - * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. - * - * @return none - */ -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - - if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - { - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } - - if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) - { - tmpreg = GPIOx->CFGLR; - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << pinpos); - } - else - { - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CFGLR = tmpreg; - } - - if(GPIO_InitStruct->GPIO_Pin > 0x00FF) - { - tmpreg = GPIOx->CFGHR; - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x08)); - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - } - } - GPIOx->CFGHR = tmpreg; - } -} - -/********************************************************************* - * @fn GPIO_StructInit - * - * @brief Fills each GPIO_InitStruct member with its default - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) -{ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/********************************************************************* - * @fn GPIO_ReadInputDataBit - * - * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @param GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * - * @return The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadInputData - * - * @brief Reads the specified GPIO input data port. - * - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * - * @return The input port pin value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) -{ - return ((uint16_t)GPIOx->INDR); -} - -/********************************************************************* - * @fn GPIO_ReadOutputDataBit - * - * @brief Reads the specified output data port bit. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadOutputData - * - * @brief Reads the specified GPIO output data port. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @return GPIO output port pin value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) -{ - return ((uint16_t)GPIOx->OUTDR); -} - -/********************************************************************* - * @fn GPIO_SetBits - * - * @brief Sets the selected data port bits. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BSHR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_ResetBits - * - * @brief Clears the selected data port bits. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BCR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_WriteBit - * - * @brief Sets or clears the selected data port bit. - * - * @param GPIO_Pin - specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * BitVal - specifies the value to be written to the selected bit. - * Bit_SetL - to clear the port pin. - * Bit_SetH - to set the port pin. - * - * @return none - */ -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - if(BitVal != Bit_RESET) - { - GPIOx->BSHR = GPIO_Pin; - } - else - { - GPIOx->BCR = GPIO_Pin; - } -} - -/********************************************************************* - * @fn GPIO_Write - * - * @brief Writes data to the specified GPIO data port. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * PortVal - specifies the value to be written to the port output data register. - * - * @return none - */ -void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) -{ - GPIOx->OUTDR = PortVal; -} - -/********************************************************************* - * @fn GPIO_PinLockConfig - * - * @brief Locks GPIO Pins configuration registers. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - - tmp |= GPIO_Pin; - GPIOx->LCKR = tmp; - GPIOx->LCKR = GPIO_Pin; - GPIOx->LCKR = tmp; - tmp = GPIOx->LCKR; - tmp = GPIOx->LCKR; -} - -/********************************************************************* - * @fn GPIO_PinRemapConfig - * - * @brief Changes the mapping of the specified pin. - * - * @param GPIO_Remap - selects the pin to remap. - * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping - * GPIO_PartialRemap_I2C1 - I2C1 Partial Alternate Function mapping - * GPIO_PartialRemap_I2C1 - I2C1 Full Alternate Function mapping - * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping - * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping - * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping - * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping - * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping - * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping - * GPIO_Remap_PA12 - PA12 Alternate Function mapping - * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping - * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping - * GPIO_Remap_LSI_CAL - LSI calibration Alternate Function mapping - * GPIO_Remap_SDI_Disable - SDI Disabled - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) -{ - uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; - - tmpreg = AFIO->PCFR1; - - tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - tmp = GPIO_Remap & LSB_MASK; - - if((GPIO_Remap & 0x10000000) == 0x10000000) - { - tmpreg &= ~((1<<1) | (1<<22)); - tmpreg |= ~DBGAFR_SDI_MASK; - if(NewState != DISABLE) - { - tmpreg |= (GPIO_Remap & 0xEFFFFFFF); - } - - } - else if((GPIO_Remap & 0x80000000) == 0x80000000) - { - tmpreg &= ~((1<<2) | (1<<21)); - tmpreg |= ~DBGAFR_SDI_MASK; - if(NewState != DISABLE) - { - tmpreg |= (GPIO_Remap & 0x7FFFFFFF); - } - - } - else if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))/* SDI */ - { - tmpreg &= DBGAFR_SDI_MASK; - AFIO->PCFR1 &= DBGAFR_SDI_MASK; - - if(NewState != DISABLE) - { - tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); - } - } - else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)/* [15:0] 2bit */ - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - tmpreg |= ~DBGAFR_SDI_MASK; - - if(NewState != DISABLE) - { - tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); - } - } - else/* [31:0] 1bit */ - { - tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); - tmpreg |= ~DBGAFR_SDI_MASK; - - if(NewState != DISABLE) - { - tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); - } - } - - - AFIO->PCFR1 = tmpreg; -} - -/********************************************************************* - * @fn GPIO_EXTILineConfig - * - * @brief Selects the GPIO pin used as EXTI Line. - * - * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). - * GPIO_PinSource - specifies the EXTI line to be configured. - * This parameter can be GPIO_PinSourcex where x can be (0..7). - * - * @return none - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmp = 0x00; - - tmp = ((uint32_t)(3<<(GPIO_PinSource<<1))); - AFIO->EXTICR &= ~tmp; - AFIO->EXTICR |= ((uint32_t)(GPIO_PortSource<<(GPIO_PinSource<<1))); -} - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_gpio.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/09 + * Description : This file provides all the GPIO firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* MASK */ +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..7). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx: where x can be (A..D) to select the GPIO peripheral. + * + * @return The input port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->INDR); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..7). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->OUTDR); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BSHR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..7). + * BitVal - specifies the value to be written to the selected bit. + * Bit_RESET - to clear the port pin. + * Bit_SET - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = GPIO_Pin; + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping + * GPIO_PartialRemap_I2C1 - I2C1 Partial Alternate Function mapping + * GPIO_FullRemap_I2C1 - I2C1 Full Alternate Function mapping + * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping + * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_Remap_PA1_2 - PA1_2 Alternate Function mapping + * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping + * GPIO_Remap_LSI_CAL - LSI calibration Alternate Function mapping + * GPIO_Remap_SDI_Disable - SDI Disabled + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + tmpreg = AFIO->PCFR1; + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if((GPIO_Remap & 0x10000000) == 0x10000000) + { + tmpreg &= ~((1<<1) | (1<<22)); + tmpreg |= ~DBGAFR_SDI_MASK; + if(NewState != DISABLE) + { + tmpreg |= (GPIO_Remap & 0xEFFFFFFF); + } + + } + else if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg &= ~((1<<2) | (1<<21)); + tmpreg |= ~DBGAFR_SDI_MASK; + if(NewState != DISABLE) + { + tmpreg |= (GPIO_Remap & 0x7FFFFFFF); + } + + } + else if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))/* SDI */ + { + tmpreg &= DBGAFR_SDI_MASK; + AFIO->PCFR1 &= DBGAFR_SDI_MASK; + + if(NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); + } + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)/* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SDI_MASK; + + if(NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); + } + } + else/* [31:0] 1bit */ + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + tmpreg |= ~DBGAFR_SDI_MASK; + + if(NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); + } + } + + + AFIO->PCFR1 = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..7). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)(3<<(GPIO_PinSource<<1))); + AFIO->EXTICR &= ~tmp; + AFIO->EXTICR |= ((uint32_t)(GPIO_PortSource<<(GPIO_PinSource<<1))); +} + +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-up. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC, ENABLE); + chip = *( uint32_t * )0x1FFFF7C4 & (~0x000000F0); + switch(chip) + { + case 0x00320500: //CH32V003A4M6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\ + |GPIO_Pin_3; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x00330500: //CH32V003J4M6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + default: + { + break; + } + + } + +} + + + diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_i2c.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_i2c.c index 0bb0c82..cb905ea 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_i2c.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_i2c.c @@ -1,975 +1,975 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_i2c.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the I2C firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* I2C SPE mask */ -#define CTLR1_PE_Set ((uint16_t)0x0001) -#define CTLR1_PE_Reset ((uint16_t)0xFFFE) - -/* I2C START mask */ -#define CTLR1_START_Set ((uint16_t)0x0100) -#define CTLR1_START_Reset ((uint16_t)0xFEFF) - -/* I2C STOP mask */ -#define CTLR1_STOP_Set ((uint16_t)0x0200) -#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) - -/* I2C ACK mask */ -#define CTLR1_ACK_Set ((uint16_t)0x0400) -#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) - -/* I2C ENGC mask */ -#define CTLR1_ENGC_Set ((uint16_t)0x0040) -#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) - -/* I2C SWRST mask */ -#define CTLR1_SWRST_Set ((uint16_t)0x8000) -#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) - -/* I2C PEC mask */ -#define CTLR1_PEC_Set ((uint16_t)0x1000) -#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) - -/* I2C ENPEC mask */ -#define CTLR1_ENPEC_Set ((uint16_t)0x0020) -#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) - -/* I2C ENARP mask */ -#define CTLR1_ENARP_Set ((uint16_t)0x0010) -#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) - -/* I2C NOSTRETCH mask */ -#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) -#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) - -/* I2C registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) - -/* I2C DMAEN mask */ -#define CTLR2_DMAEN_Set ((uint16_t)0x0800) -#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) - -/* I2C LAST mask */ -#define CTLR2_LAST_Set ((uint16_t)0x1000) -#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) - -/* I2C FREQ mask */ -#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) - -/* I2C ADD0 mask */ -#define OADDR1_ADD0_Set ((uint16_t)0x0001) -#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) - -/* I2C ENDUAL mask */ -#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) -#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) - -/* I2C ADD2 mask */ -#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) - -/* I2C F/S mask */ -#define CKCFGR_FS_Set ((uint16_t)0x8000) - -/* I2C CCR mask */ -#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) - -/* I2C FLAG mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) - -/* I2C Interrupt Enable mask */ -#define ITEN_Mask ((uint32_t)0x07000000) - -/********************************************************************* - * @fn I2C_DeInit - * - * @brief Deinitializes the I2Cx peripheral registers to their default - * reset values. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * - * @return none - */ -void I2C_DeInit(I2C_TypeDef *I2Cx) -{ - if(I2Cx == I2C1) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); - } -} - -/********************************************************************* - * @fn I2C_Init - * - * @brief Initializes the I2Cx peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified I2C peripheral. - * - * @return none - */ -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) -{ - uint16_t tmpreg = 0, freqrange = 0; - uint16_t result = 0x04; - uint32_t pclk1 = 8000000; - - RCC_ClocksTypeDef rcc_clocks; - - tmpreg = I2Cx->CTLR2; - tmpreg &= CTLR2_FREQ_Reset; - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - I2Cx->CTLR2 = tmpreg; - - I2Cx->CTLR1 &= CTLR1_PE_Reset; - tmpreg = 0; - - if(I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - - if(result < 0x04) - { - result = 0x04; - } - - tmpreg |= result; - } - else - { - if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - result |= I2C_DutyCycle_16_9; - } - - if((result & CKCFGR_CCR_Set) == 0) - { - result |= (uint16_t)0x0001; - } - - tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); - } - - I2Cx->CKCFGR = tmpreg; - I2Cx->CTLR1 |= CTLR1_PE_Set; - - tmpreg = I2Cx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - I2Cx->CTLR1 = tmpreg; - - I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/********************************************************************* - * @fn I2C_StructInit - * - * @brief Fills each I2C_InitStruct member with its default value. - * - * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) -{ - I2C_InitStruct->I2C_ClockSpeed = 5000; - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStruct->I2C_OwnAddress1 = 0; - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/********************************************************************* - * @fn I2C_Cmd - * - * @brief Enables or disables the specified I2C peripheral. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PE_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PE_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMACmd - * - * @brief Enables or disables the specified I2C DMA requests. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_DMAEN_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMALastTransferCmd - * - * @brief Specifies if the next DMA transfer will be the last one. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_LAST_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_LAST_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTART - * - * @brief Generates I2Cx communication START condition. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_START_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_START_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTOP - * - * @brief Generates I2Cx communication STOP condition. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_STOP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_STOP_Reset; - } -} - -/********************************************************************* - * @fn I2C_AcknowledgeConfig - * - * @brief Enables or disables the specified I2C acknowledge feature. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ACK_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ACK_Reset; - } -} - -/********************************************************************* - * @fn I2C_OwnAddress2Config - * - * @brief Configures the specified I2C own address2. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * Address - specifies the 7bit I2C own address2. - * - * @return none - */ -void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - tmpreg = I2Cx->OADDR2; - tmpreg &= OADDR2_ADD2_Reset; - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - I2Cx->OADDR2 = tmpreg; -} - -/********************************************************************* - * @fn I2C_DualAddressCmd - * - * @brief Enables or disables the specified I2C dual addressing mode. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; - } - else - { - I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; - } -} - -/********************************************************************* - * @fn I2C_GeneralCallCmd - * - * @brief Enables or disables the specified I2C general call feature. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENGC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENGC_Reset; - } -} - -/********************************************************************* - * @fn I2C_ITConfig - * - * @brief Enables or disables the specified I2C interrupts. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. - * I2C_IT_BUF - Buffer interrupt mask. - * I2C_IT_EVT - Event interrupt mask. - * I2C_IT_ERR - Error interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= I2C_IT; - } - else - { - I2Cx->CTLR2 &= (uint16_t)~I2C_IT; - } -} - -/********************************************************************* - * @fn I2C_SendData - * - * @brief Sends a data byte through the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * Data - Byte to be transmitted. - * - * @return none - */ -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) -{ - I2Cx->DATAR = Data; -} - -/********************************************************************* - * @fn I2C_ReceiveData - * - * @brief Returns the most recent received data by the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * - * @return The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) -{ - return (uint8_t)I2Cx->DATAR; -} - -/********************************************************************* - * @fn I2C_Send7bitAddress - * - * @brief Transmits the address byte to select the slave device. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * Address - specifies the slave address which will be transmitted. - * I2C_Direction - specifies whether the I2C device will be a - * Transmitter or a Receiver. - * I2C_Direction_Transmitter - Transmitter mode. - * I2C_Direction_Receiver - Receiver mode. - * - * @return none - */ -void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - if(I2C_Direction != I2C_Direction_Transmitter) - { - Address |= OADDR1_ADD0_Set; - } - else - { - Address &= OADDR1_ADD0_Reset; - } - - I2Cx->DATAR = Address; -} - -/********************************************************************* - * @fn I2C_ReadRegister - * - * @brief Reads the specified I2C register and returns its value. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_Register - specifies the register to read. - * I2C_Register_CTLR1. - * I2C_Register_CTLR2. - * I2C_Register_OADDR1. - * I2C_Register_OADDR2. - * I2C_Register_DATAR. - * I2C_Register_STAR1. - * I2C_Register_STAR2. - * I2C_Register_CKCFGR. - * - * @return none - */ -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)I2Cx; - tmp += I2C_Register; - - return (*(__IO uint16_t *)tmp); -} - -/********************************************************************* - * @fn I2C_SoftwareResetCmd - * - * @brief Enables or disables the specified I2C software reset. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_SWRST_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_SWRST_Reset; - } -} - -/********************************************************************* - * @fn I2C_NACKPositionConfig - * - * @brief Selects the specified I2C NACK position in master receiver mode. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_NACKPosition - specifies the NACK position. - * I2C_NACKPosition_Next - indicates that the next byte will be - * the last received byte. - * I2C_NACKPosition_Current - indicates that current byte is the - * last received byte. - * Note- - * This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * @return none - */ -void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) -{ - if(I2C_NACKPosition == I2C_NACKPosition_Next) - { - I2Cx->CTLR1 |= I2C_NACKPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_NACKPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_TransmitPEC - * - * @brief Enables or disables the specified I2C PEC transfer. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_PECPositionConfig - * - * @brief Selects the specified I2C PEC position. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_PECPosition - specifies the PEC position. - * I2C_PECPosition_Next - indicates that the next byte is PEC. - * I2C_PECPosition_Current - indicates that current byte is PEC. - * - * @return none - */ -void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) -{ - if(I2C_PECPosition == I2C_PECPosition_Next) - { - I2Cx->CTLR1 |= I2C_PECPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_PECPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_CalculatePEC - * - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * - * @param I2Cx- where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENPEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_GetPEC - * - * @brief Returns the PEC value for the specified I2C. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * - * @return The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) -{ - return ((I2Cx->STAR2) >> 8); -} - -/********************************************************************* - * @fn I2C_ARPCmd - * - * @brief Enables or disables the specified I2C ARP. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return The PEC value. - */ -void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENARP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENARP_Reset; - } -} - -/********************************************************************* - * @fn I2C_StretchClockCmd - * - * @brief Enables or disables the specified I2C Clock stretching. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState == DISABLE) - { - I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; - } -} - -/********************************************************************* - * @fn I2C_FastModeDutyCycleConfig - * - * @brief Selects the specified I2C fast mode duty cycle. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_DutyCycle - specifies the fast mode duty cycle. - * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. - * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. - * - * @return none - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) -{ - if(I2C_DutyCycle != I2C_DutyCycle_16_9) - { - I2Cx->CKCFGR &= I2C_DutyCycle_2; - } - else - { - I2Cx->CKCFGR |= I2C_DutyCycle_16_9; - } -} - -/********************************************************************* - * @fn I2C_CheckEvent - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx- where x can be 1 to select the I2C peripheral. - * I2C_EVENT: specifies the event to be checked. - * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. - * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. - * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. - * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. - * I2C_EVENT_MASTER_MODE_SELECT - EVT5. - * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. - * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. - * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. - * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. - * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. - * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. - * - * @return ErrorStatus - READY or NoREADY. - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = NoREADY; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - - lastevent = (flag1 | flag2) & FLAG_Mask; - - if((lastevent & I2C_EVENT) == I2C_EVENT) - { - status = READY; - } - else - { - status = NoREADY; - } - - return status; -} - -/********************************************************************* - * @fn I2C_GetLastEvent - * - * @brief Returns the last I2Cx Event. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * - * @return none - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - lastevent = (flag1 | flag2) & FLAG_Mask; - - return lastevent; -} - -/********************************************************************* - * @fn I2C_GetFlagStatus - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to check. - * I2C_FLAG_DUALF - Dual flag (Slave mode). - * I2C_FLAG_GENCALL - General call header flag (Slave mode). - * I2C_FLAG_TRA - Transmitter/Receiver flag. - * I2C_FLAG_BUSY - Bus busy flag. - * I2C_FLAG_MSL - Master/Slave flag. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * I2C_FLAG_TXE - Data register empty flag (Transmitter). - * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. - * I2C_FLAG_STOPF - Stop detection flag (Slave mode). - * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). - * I2C_FLAG_BTF - Byte transfer finished flag. - * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDA". - * I2C_FLAG_SB - Start bit flag (Master mode). - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - i2cxbase = (uint32_t)I2Cx; - i2creg = I2C_FLAG >> 28; - I2C_FLAG &= FLAG_Mask; - - if(i2creg != 0) - { - i2cxbase += 0x14; - } - else - { - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearFlag - * - * @brief Clears the I2Cx's pending flags. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to clear. - * I2C_FLAG_SMBALERT - SMBus Alert flag. - * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * Note- - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DATAR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DATAR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SATR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR - * register (I2C_SendData()). - * @return none - */ -void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - - flagpos = I2C_FLAG & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} - -/********************************************************************* - * @fn I2C_GetITStatus - * - * @brief Checks whether the specified I2C interrupt has occurred or not. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * II2C_IT - specifies the interrupt source to check. - * I2C_IT_PECERR - PEC error in reception flag. - * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). - * I2C_IT_AF - Acknowledge failure flag. - * I2C_IT_ARLO - Arbitration lost flag (Master mode). - * I2C_IT_BERR - Bus error flag. - * I2C_IT_TXE - Data register empty flag (Transmitter). - * I2C_IT_RXNE - Data register not empty (Receiver) flag. - * I2C_IT_STOPF - Stop detection flag (Slave mode). - * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). - * I2C_IT_BTF - Byte transfer finished flag. - * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched - * flag (Slave mode)"ENDAD". - * I2C_IT_SB - Start bit flag (Master mode). - * - * @return none - */ -ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); - I2C_IT &= FLAG_Mask; - - if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearITPendingBit - * - * @brief Clears the I2Cx interrupt pending bits. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_IT - specifies the interrupt pending bit to clear. - * I2C_IT_PECERR - PEC error in reception interrupt. - * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). - * I2C_IT_AF - Acknowledge failure interrupt. - * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). - * I2C_IT_BERR - Bus error interrupt. - * Note- - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DATAR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DATAR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_STAR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DATAR register (I2C_SendData()). - * - * @return none - */ -void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - - flagpos = I2C_IT & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} - - - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_i2c.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the I2C firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * Note- + * This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. + * I2C_EVENT_MASTER_MODE_SELECT - EVT5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. + * + * @return ErrorStatus - READY or NoREADY. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = NoREADY; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = READY; + } + else + { + status = NoREADY; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SATR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR + * register (I2C_SendData()). + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_STAR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DATAR register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + + + + + + + diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_iwdg.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_iwdg.c index 0e79f13..9379c8f 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_iwdg.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_iwdg.c @@ -1,125 +1,126 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_iwdg.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the IWDG firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -/* CTLR register bit mask */ -#define CTLR_KEY_Reload ((uint16_t)0xAAAA) -#define CTLR_KEY_Enable ((uint16_t)0xCCCC) - -/********************************************************************* - * @fn IWDG_WriteAccessCmd - * - * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. - * - * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR - * and IWDG_RLDR registers. - * - * @return none - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - IWDG->CTLR = IWDG_WriteAccess; -} - -/********************************************************************* - * @fn IWDG_SetPrescaler - * - * @brief Sets IWDG Prescaler value. - * - * @param IWDG_Prescaler - specifies the IWDG Prescaler value. - * IWDG_Prescaler_4 - IWDG prescaler set to 4. - * IWDG_Prescaler_8 - IWDG prescaler set to 8. - * IWDG_Prescaler_16 - IWDG prescaler set to 16. - * IWDG_Prescaler_32 - IWDG prescaler set to 32. - * IWDG_Prescaler_64 - IWDG prescaler set to 64. - * IWDG_Prescaler_128 - IWDG prescaler set to 128. - * IWDG_Prescaler_256 - IWDG prescaler set to 256. - * - * @return none - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - IWDG->PSCR = IWDG_Prescaler; -} - -/********************************************************************* - * @fn IWDG_SetReload - * - * @brief Sets IWDG Reload value. - * - * @param Reload - specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * - * @return none - */ -void IWDG_SetReload(uint16_t Reload) -{ - IWDG->RLDR = Reload; -} - -/********************************************************************* - * @fn IWDG_ReloadCounter - * - * @brief Reloads IWDG counter with value defined in the reload register. - * - * @return none - */ -void IWDG_ReloadCounter(void) -{ - IWDG->CTLR = CTLR_KEY_Reload; -} - -/********************************************************************* - * @fn IWDG_Enable - * - * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). - * - * @return none - */ -void IWDG_Enable(void) -{ - IWDG->CTLR = CTLR_KEY_Enable; -} - -/********************************************************************* - * @fn IWDG_GetFlagStatus - * - * @brief Checks whether the specified IWDG flag is set or not. - * - * @param IWDG_FLAG - specifies the flag to check. - * IWDG_FLAG_PVU - Prescaler Value Update on going. - * IWDG_FLAG_RVU - Reload Value Update on going. - * - * @return none - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_iwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/25 + * Description : This file provides all the IWDG firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; + while ((RCC->RSTSCKR & 0x2) == RESET); +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + + diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_misc.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_misc.c index 92f4f44..dabd40f 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_misc.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_misc.c @@ -1,109 +1,81 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_misc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the miscellaneous firmware functions . - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -__IO uint32_t NVIC_Priority_Group = 0; - -/********************************************************************* - * @fn NVIC_PriorityGroupConfig - * - * @brief Configures the priority grouping - pre-emption priority and subpriority. - * - * @param NVIC_PriorityGroup - specifies the priority grouping bits length. - * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority - * 4 bits for subpriority - * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority - * 3 bits for subpriority - * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority - * 2 bits for subpriority - * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority - * 1 bits for subpriority - * NVIC_PriorityGroup_4 - 4 bits for pre-emption priority - * 0 bits for subpriority - * - * @return none - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - NVIC_Priority_Group = NVIC_PriorityGroup; -} - -/********************************************************************* - * @fn NVIC_Init - * - * @brief Initializes the NVIC peripheral according to the specified parameters in - * the NVIC_InitStruct. - * - * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the - * configuration information for the specified NVIC peripheral. - * - * @return none - */ -void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) -{ - uint8_t tmppre = 0; - - if(NVIC_Priority_Group == NVIC_PriorityGroup_0) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); - } - else - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); - } - else - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3) - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); - } - else - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4)); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_4) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4); - } - - if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } - else - { - NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_misc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/25 + * Description : This file provides all the miscellaneous firmware functions . + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 2 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 1 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 1. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6); + } +#else + if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6)); + } + else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6)); + } + } +#endif + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_opa.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_opa.c index 24179ae..3d6c70c 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_opa.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_opa.c @@ -1,82 +1,82 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_opa.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the OPA firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - - -/********************************************************************* - * @fn OPA_DeInit - * - * @brief Deinitializes the OPA peripheral registers to their default - * reset values. - * - * @return none - */ -void OPA_DeInit(void) -{ - EXTEN->EXTEN_CTR &= ~(uint32_t)(7 << 16); -} - -/********************************************************************* - * @fn OPA_Init - * - * @brief Initializes the OPA peripheral according to the specified - * parameters in the OPA_InitStruct. - * - * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure - * - * @return none - */ -void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) -{ - uint32_t tmp = 0; - tmp = EXTEN->EXTEN_CTR; - tmp &= ~(uint32_t)(3<<17); - tmp |= (OPA_InitStruct->PSEL << 18) | (OPA_InitStruct->NSEL << 17); - EXTEN->EXTEN_CTR = tmp; -} - -/********************************************************************* - * @fn OPA_StructInit - * - * @brief Fills each OPA_StructInit member with its reset value. - * - * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure - * - * @return none - */ -void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) -{ - OPA_InitStruct->PSEL = CHP0; - OPA_InitStruct->NSEL = CHN0; -} - -/********************************************************************* - * @fn OPA_Cmd - * - * @brief Enables or disables the specified OPA peripheral. - * - * @param OPA_NUM - Select OPA - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void OPA_Cmd(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - EXTEN->EXTEN_CTR |= (uint32_t)(1 << 16); - } - else - { - EXTEN->EXTEN_CTR &= ~(uint32_t)(1 << 16); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_opa.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the OPA firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + + +/********************************************************************* + * @fn OPA_DeInit + * + * @brief Deinitializes the OPA peripheral registers to their default + * reset values. + * + * @return none + */ +void OPA_DeInit(void) +{ + EXTEN->EXTEN_CTR &= ~(uint32_t)(7 << 16); +} + +/********************************************************************* + * @fn OPA_Init + * + * @brief Initializes the OPA peripheral according to the specified + * parameters in the OPA_InitStruct. + * + * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) +{ + uint32_t tmp = 0; + tmp = EXTEN->EXTEN_CTR; + tmp &= ~(uint32_t)(3<<17); + tmp |= (OPA_InitStruct->PSEL << 18) | (OPA_InitStruct->NSEL << 17); + EXTEN->EXTEN_CTR = tmp; +} + +/********************************************************************* + * @fn OPA_StructInit + * + * @brief Fills each OPA_StructInit member with its reset value. + * + * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) +{ + OPA_InitStruct->PSEL = CHP0; + OPA_InitStruct->NSEL = CHN0; +} + +/********************************************************************* + * @fn OPA_Cmd + * + * @brief Enables or disables the specified OPA peripheral. + * + * @param OPA_NUM - Select OPA + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_Cmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + EXTEN->EXTEN_CTR |= (uint32_t)(1 << 16); + } + else + { + EXTEN->EXTEN_CTR &= ~(uint32_t)(1 << 16); + } +} diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_pwr.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_pwr.c index 49832c0..1d2f94d 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_pwr.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_pwr.c @@ -1,213 +1,213 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_pwr.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the PWR firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* PWR registers bit mask */ -/* CTLR register bit mask */ -#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) -#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) -#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) -#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) - -/********************************************************************* - * @fn PWR_DeInit - * - * @brief Deinitializes the PWR peripheral registers to their default - * reset values. - * - * @return none - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/********************************************************************* - * @fn PWR_PVDCmd - * - * @brief Enables or disables the Power Voltage Detector(PVD). - * - * @param NewState - new state of the PVD(ENABLE or DISABLE). - * - * @return none - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (1 << 4); - } - else - { - PWR->CTLR &= ~(1 << 4); - } -} - -/********************************************************************* - * @fn PWR_PVDLevelConfig - * - * @brief Configures the voltage threshold detected by the Power Voltage - * Detector(PVD). - * - * @param PWR_PVDLevel - specifies the PVD detection level - * PWR_PVDLevel_2V2 - PVD detection level set to 2.2V - * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V - * PWR_PVDLevel_2V4 - PVD detection level set to 2.4V - * PWR_PVDLevel_2V5 - PVD detection level set to 2.5V - * PWR_PVDLevel_2V6 - PVD detection level set to 2.6V - * PWR_PVDLevel_2V7 - PVD detection level set to 2.7V - * PWR_PVDLevel_2V8 - PVD detection level set to 2.8V - * PWR_PVDLevel_2V9 - PVD detection level set to 2.9V - * - * @return none - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_PLS_MASK; - tmpreg |= PWR_PVDLevel; - PWR->CTLR = tmpreg; -} - -/********************************************************************* - * @fn PWR_AutoWakeUpCmd - * - * @brief Enables or disables the Auto WakeUp functionality. - * - * @param NewState - new state of the Auto WakeUp functionality - * (ENABLE or DISABLE). - * - * @return none - */ -void PWR_AutoWakeUpCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->AWUCSR |= (1 << 1); - } - else - { - PWR->AWUCSR &= ~(1 << 1); - } -} - -/********************************************************************* - * @fn PWR_AWU_SetPrescaler - * - * @brief Sets the Auto Wake up Prescaler - * - * @param AWU_Prescaler - specifies the Auto Wake up Prescaler - * PWR_AWU_Prescaler_1 - AWU counter clock = LSI/1 - * PWR_AWU_Prescaler_2 - AWU counter clock = LSI/2 - * PWR_AWU_Prescaler_4 - AWU counter clock = LSI/4 - * PWR_AWU_Prescaler_8 - AWU counter clock = LSI/8 - * PWR_AWU_Prescaler_16 - AWU counter clock = LSI/16 - * PWR_AWU_Prescaler_32 - AWU counter clock = LSI/32 - * PWR_AWU_Prescaler_64 - AWU counter clock = LSI/64 - * PWR_AWU_Prescaler_128 - AWU counter clock = LSI/128 - * PWR_AWU_Prescaler_256 - AWU counter clock = LSI/256 - * PWR_AWU_Prescaler_512 - AWU counter clock = LSI/512 - * PWR_AWU_Prescaler_1024 - AWU counter clock = LSI/1024 - * PWR_AWU_Prescaler_2048 - AWU counter clock = LSI/2048 - * PWR_AWU_Prescaler_4096 - AWU counter clock = LSI/4096 - * PWR_AWU_Prescaler_10240 - AWU counter clock = LSI/10240 - * PWR_AWU_Prescaler_61440 - AWU counter clock = LSI/61440 - * - * @return none - */ -void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->AWUPSC & AWUPSC_MASK; - tmpreg |= AWU_Prescaler; - PWR->AWUPSC = tmpreg; -} - -/********************************************************************* - * @fn PWR_AWU_SetWindowValue - * - * @brief Sets the WWDG window value - * - * @param WindowValue - specifies the window value to be compared to the - * downcounter,which must be lower than 0x3F - * - * @return none - */ -void PWR_AWU_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - tmpreg = PWR->AWUWR & AWUWR_MASK; - - tmpreg |= WindowValue; - - PWR->AWUWR = tmpreg; -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode - * - * @brief Enters STANDBY mode. - * - * @param PWR_STANDBYEntry - specifies if STANDBY mode in entered with WFI or WFE instruction. - * PWR_STANDBYEntry_WFI - enter STANDBY mode with WFI instruction - * PWR_STANDBYEntry_WFE - enter STANDBY mode with WFE instruction - * - * @return none - */ -void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry) -{ - PWR->CTLR &= CTLR_DS_MASK; - PWR->CTLR |= PWR_CTLR_PDDS; - - NVIC->SCTLR |= (1 << 2); - - if(PWR_STANDBYEntry == PWR_STANDBYEntry_WFI) - { - __WFI(); - } - else - { - __WFE(); - } - - NVIC->SCTLR &= ~(1 << 2); -} - -/********************************************************************* - * @fn PWR_GetFlagStatus - * - * @brief Checks whether the specified PWR flag is set or not. - * - * @param PWR_FLAG - specifies the flag to check. - * PWR_FLAG_PVDO - PVD Output - * - * @return The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_pwr.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the PWR firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) +#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) +#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_PVDCmd + * + * @brief Enables or disables the Power Voltage Detector(PVD). + * + * @param NewState - new state of the PVD(ENABLE or DISABLE). + * + * @return none + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 4); + } + else + { + PWR->CTLR &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_MODE0 - PVD detection level set to mode 0. + * PWR_PVDLevel_MODE1 - PVD detection level set to mode 1. + * PWR_PVDLevel_MODE2 - PVD detection level set to mode 2. + * PWR_PVDLevel_MODE3 - PVD detection level set to mode 3. + * PWR_PVDLevel_MODE4 - PVD detection level set to mode 4. + * PWR_PVDLevel_MODE5 - PVD detection level set to mode 5. + * PWR_PVDLevel_MODE6 - PVD detection level set to mode 6. + * PWR_PVDLevel_MODE7 - PVD detection level set to mode 7. + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_AutoWakeUpCmd + * + * @brief Enables or disables the Auto WakeUp functionality. + * + * @param NewState - new state of the Auto WakeUp functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_AutoWakeUpCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->AWUCSR |= (1 << 1); + } + else + { + PWR->AWUCSR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn PWR_AWU_SetPrescaler + * + * @brief Sets the Auto Wake up Prescaler + * + * @param AWU_Prescaler - specifies the Auto Wake up Prescaler + * PWR_AWU_Prescaler_1 - AWU counter clock = LSI/1 + * PWR_AWU_Prescaler_2 - AWU counter clock = LSI/2 + * PWR_AWU_Prescaler_4 - AWU counter clock = LSI/4 + * PWR_AWU_Prescaler_8 - AWU counter clock = LSI/8 + * PWR_AWU_Prescaler_16 - AWU counter clock = LSI/16 + * PWR_AWU_Prescaler_32 - AWU counter clock = LSI/32 + * PWR_AWU_Prescaler_64 - AWU counter clock = LSI/64 + * PWR_AWU_Prescaler_128 - AWU counter clock = LSI/128 + * PWR_AWU_Prescaler_256 - AWU counter clock = LSI/256 + * PWR_AWU_Prescaler_512 - AWU counter clock = LSI/512 + * PWR_AWU_Prescaler_1024 - AWU counter clock = LSI/1024 + * PWR_AWU_Prescaler_2048 - AWU counter clock = LSI/2048 + * PWR_AWU_Prescaler_4096 - AWU counter clock = LSI/4096 + * PWR_AWU_Prescaler_10240 - AWU counter clock = LSI/10240 + * PWR_AWU_Prescaler_61440 - AWU counter clock = LSI/61440 + * + * @return none + */ +void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->AWUPSC & AWUPSC_MASK; + tmpreg |= AWU_Prescaler; + PWR->AWUPSC = tmpreg; +} + +/********************************************************************* + * @fn PWR_AWU_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x3F + * + * @return none + */ +void PWR_AWU_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = PWR->AWUWR & AWUWR_MASK; + + tmpreg |= WindowValue; + + PWR->AWUWR = tmpreg; +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @param PWR_STANDBYEntry - specifies if STANDBY mode in entered with WFI or WFE instruction. + * PWR_STANDBYEntry_WFI - enter STANDBY mode with WFI instruction + * PWR_STANDBYEntry_WFE - enter STANDBY mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry) +{ + PWR->CTLR &= CTLR_DS_MASK; + PWR->CTLR |= PWR_CTLR_PDDS; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STANDBYEntry == PWR_STANDBYEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_PVDO - PVD Output + * + * @return The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_rcc.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_rcc.c index 283be69..097a090 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_rcc.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_rcc.c @@ -1,750 +1,771 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_rcc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the RCC firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -/* RCC registers bit address in the alias region */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* BDCTLR Register */ -#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) - -/* RCC registers bit mask */ - -/* CTLR register bit mask */ -#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) -#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CTLR_HSEON_Set ((uint32_t)0x00010000) -#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) -#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) -#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) -#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) -#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) -#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) -#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) -#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF07FF) -#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800) - -/* RSTSCKR register bit mask */ -#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -/* INTR register byte 2 (Bits[15:8]) base address */ -#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* INTR register byte 3 (Bits[23:16]) base address */ -#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CFGR0 register byte 4 (Bits[31:24]) base address */ -#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) - -/* BDCTLR register base address */ -#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) - -static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; -static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128}; - -/********************************************************************* - * @fn RCC_DeInit - * - * @brief Resets the RCC clock configuration to the default reset state. - * - * @return none - */ -void RCC_DeInit(void) -{ - RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xFCFF0000; - RCC->CTLR &= (uint32_t)0xFEF6FFFF; - RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFFFEFFFF; - RCC->INTR = 0x009F0000; -} - -/********************************************************************* - * @fn RCC_HSEConfig - * - * @brief Configures the External High Speed oscillator (HSE). - * - * @param RCC_HSE - - * RCC_HSE_OFF - HSE oscillator OFF. - * RCC_HSE_ON - HSE oscillator ON. - * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. - * Note- - * HSE can not be stopped if it is used directly or through the PLL as system clock. - * @return none - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - RCC->CTLR &= CTLR_HSEON_Reset; - RCC->CTLR &= CTLR_HSEBYP_Reset; - - switch(RCC_HSE) - { - case RCC_HSE_ON: - RCC->CTLR |= CTLR_HSEON_Set; - break; - - case RCC_HSE_Bypass: - RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn RCC_WaitForHSEStartUp - * - * @brief Waits for HSE start-up. - * - * @return READY - HSE oscillator is stable and ready to use. - * NoREADY - HSE oscillator not yet ready. - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - - ErrorStatus status = NoREADY; - FlagStatus HSEStatus = RESET; - - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = READY; - } - else - { - status = NoREADY; - } - - return (status); -} - -/********************************************************************* - * @fn RCC_AdjustHSICalibrationValue - * - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * - * @param HSICalibrationValue - specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * - * @return none - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CTLR; - tmpreg &= CTLR_HSITRIM_Mask; - tmpreg |= (uint32_t)HSICalibrationValue << 3; - RCC->CTLR = tmpreg; -} - -/********************************************************************* - * @fn RCC_HSICmd - * - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_HSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 0); - } - else - { - RCC->CTLR &= ~(1 << 0); - } -} - -/********************************************************************* - * @fn RCC_PLLConfig - * - * @brief Configures the PLL clock source and multiplication factor. - * - * @param RCC_PLLSource - specifies the PLL entry clock source. - * RCC_PLLSource_HSI_MUL2 - HSI oscillator clock*2 - * selected as PLL clock entry. - * RCC_PLLSource_HSE_MUL2 - HSE oscillator clock*2 - * selected as PLL clock entry. - * - * @return none - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_PLL_Mask; - tmpreg |= RCC_PLLSource; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PLLCmd - * - * @brief Enables or disables the PLL. - * Note-The PLL can not be disabled if it is used as system clock. - * - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 24); - } - else - { - RCC->CTLR &= ~(1 << 24); - } -} - -/********************************************************************* - * @fn RCC_SYSCLKConfig - * - * @brief Configures the system clock (SYSCLK). - * - * @param RCC_SYSCLKSource - specifies the clock source used as system clock. - * RCC_SYSCLKSource_HSI - HSI selected as system clock. - * RCC_SYSCLKSource_HSE - HSE selected as system clock. - * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. - * - * @return none - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_SW_Mask; - tmpreg |= RCC_SYSCLKSource; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_GetSYSCLKSource - * - * @brief Returns the clock source used as system clock. - * - * @return 0x00 - HSI used as system clock. - * 0x04 - HSE used as system clock. - * 0x08 - PLL used as system clock. - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); -} - -/********************************************************************* - * @fn RCC_HCLKConfig - * - * @brief Configures the AHB clock (HCLK). - * - * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. - * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. - * RCC_SYSCLK_Div3 - AHB clock = SYSCLK/3. - * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. - * RCC_SYSCLK_Div5 - AHB clock = SYSCLK/5. - * RCC_SYSCLK_Div6 - AHB clock = SYSCLK/6. - * RCC_SYSCLK_Div7 - AHB clock = SYSCLK/7. - * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. - * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. - * RCC_SYSCLK_Div32 - AHB clock = SYSCLK/32. - * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. - * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. - * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. - * - * @return none - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_HPRE_Reset_Mask; - tmpreg |= RCC_SYSCLK; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_ITConfig - * - * @brief Enables or disables the specified RCC interrupts. - * - * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/********************************************************************* - * @fn RCC_ADCCLKConfig - * - * @brief Configures the ADC clock (ADCCLK). - * - * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from - * the APB2 clock (PCLK2). - * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. - * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. - * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. - * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. - * RCC_PCLK2_Div12 - ADC clock = PCLK2/12. - * RCC_PCLK2_Div16 - ADC clock = PCLK2/16. - * RCC_PCLK2_Div24 - ADC clock = PCLK2/24. - * RCC_PCLK2_Div32 - ADC clock = PCLK2/32. - * RCC_PCLK2_Div48 - ADC clock = PCLK2/48. - * RCC_PCLK2_Div64 - ADC clock = PCLK2/64. - * RCC_PCLK2_Div96 - ADC clock = PCLK2/96. - * RCC_PCLK2_Div128 - ADC clock = PCLK2/128. - * - * @return none - */ -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_ADCPRE_Reset_Mask; - tmpreg |= RCC_PCLK2; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_LSICmd - * - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * Note- - * LSI can not be disabled if the IWDG is running. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_LSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->RSTSCKR |= (1 << 0); - } - else - { - RCC->RSTSCKR &= ~(1 << 0); - } -} - -/********************************************************************* - * @fn RCC_GetClocksFreq - * - * @brief The result of this function could be not correct when using - * fractional value for HSE crystal. - * - * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @return none - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks) -{ - uint32_t tmp = 0, pllsource = 0, presc = 0; - - tmp = RCC->CFGR0 & CFGR0_SWS_Mask; - - switch(tmp) - { - case 0x00: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - - case 0x04: - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - - case 0x08: - pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; - - if(pllsource == 0x00) - { - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE * 2; - } - else - { - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * 2; - } - break; - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - - tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - - if(((RCC->CFGR0 & CFGR0_HPRE_Set_Mask) >> 4) < 8) - { - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency / presc; - } - else - { - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - } - - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency; - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency; - tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; - tmp = tmp >> 11; - tmp = ((tmp & 0x18) >> 3) | ((tmp & 0x7) << 2); - - if((tmp & 0x13) >= 4) - { - tmp -= 12; - } - - presc = ADCPrescTable[tmp]; - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; -} - -/********************************************************************* - * @fn RCC_AHBPeriphClockCmd - * - * @brief Enables or disables the AHB peripheral clock. - * - * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. - * RCC_AHBPeriph_DMA1. - * RCC_AHBPeriph_SRAM. - * Note- - * SRAM clock can be disabled only during sleep mode. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->AHBPCENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBPCENR &= ~RCC_AHBPeriph; - } -} - -/********************************************************************* - * @fn RCC_APB2PeriphClockCmd - * - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * - * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. - * RCC_APB2Periph_AFIO. - * RCC_APB2Periph_GPIOA. - * RCC_APB2Periph_GPIOC. - * RCC_APB2Periph_GPIOD. - * RCC_APB2Periph_ADC1. - * RCC_APB2Periph_TIM1. - * RCC_APB2Periph_SPI1. - * RCC_APB2Periph_USART1. - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->APB2PCENR |= RCC_APB2Periph; - } - else - { - RCC->APB2PCENR &= ~RCC_APB2Periph; - } -} - -/********************************************************************* - * @fn RCC_APB1PeriphClockCmd - * - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * - * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. - * RCC_APB1Periph_TIM2. - * RCC_APB1Periph_WWDG. - * RCC_APB1Periph_I2C1. - * RCC_APB1Periph_PWR. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->APB1PCENR |= RCC_APB1Periph; - } - else - { - RCC->APB1PCENR &= ~RCC_APB1Periph; - } -} - -/********************************************************************* - * @fn RCC_APB2PeriphResetCmd - * - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * - * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. - * RCC_APB2Periph_AFIO. - * RCC_APB2Periph_GPIOA. - * RCC_APB2Periph_GPIOC. - * RCC_APB2Periph_GPIOD. - * RCC_APB2Periph_ADC1. - * RCC_APB2Periph_TIM1. - * RCC_APB2Periph_SPI1. - * RCC_APB2Periph_USART1. - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->APB2PRSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2PRSTR &= ~RCC_APB2Periph; - } -} - -/********************************************************************* - * @fn RCC_APB1PeriphResetCmd - * - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * - * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. - * RCC_APB1Periph_TIM2. - * RCC_APB1Periph_WWDG. - * RCC_APB1Periph_I2C1. - * RCC_APB1Periph_PWR. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->APB1PRSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1PRSTR &= ~RCC_APB1Periph; - } -} - -/********************************************************************* - * @fn RCC_ClockSecuritySystemCmd - * - * @brief Enables or disables the Clock Security System. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 19); - } - else - { - RCC->CTLR &= ~(1 << 19); - } -} - -/********************************************************************* - * @fn RCC_MCOConfig - * - * @brief Selects the clock source to output on MCO pin. - * - * @param RCC_MCO - specifies the clock source to output. - * RCC_MCO_NoClock - No clock selected. - * RCC_MCO_SYSCLK - System clock selected. - * RCC_MCO_HSI - HSI oscillator clock selected. - * RCC_MCO_HSE - HSE oscillator clock selected. - * RCC_MCO_PLLCLK - PLL clock selected. - * - * @return none - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO; -} - -/********************************************************************* - * @fn RCC_GetFlagStatus - * - * @brief Checks whether the specified RCC flag is set or not. - * - * @param RCC_FLAG - specifies the flag to check. - * RCC_FLAG_HSIRDY - HSI oscillator clock ready. - * RCC_FLAG_HSERDY - HSE oscillator clock ready. - * RCC_FLAG_PLLRDY - PLL clock ready. - * RCC_FLAG_LSIRDY - LSI oscillator clock ready. - * RCC_FLAG_PINRST - Pin reset. - * RCC_FLAG_PORRST - POR/PDR reset. - * RCC_FLAG_SFTRST - Software reset. - * RCC_FLAG_IWDGRST - Independent Watchdog reset. - * RCC_FLAG_WWDGRST - Window Watchdog reset. - * RCC_FLAG_LPWRRST - Low Power reset. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - - FlagStatus bitstatus = RESET; - tmp = RCC_FLAG >> 5; - - if(tmp == 1) - { - statusreg = RCC->CTLR; - } - else - { - statusreg = RCC->RSTSCKR; - } - - tmp = RCC_FLAG & FLAG_Mask; - - if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearFlag - * - * @brief Clears the RCC reset flags. - * Note- - * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @return none - */ -void RCC_ClearFlag(void) -{ - RCC->RSTSCKR |= RSTSCKR_RMVF_Set; -} - -/********************************************************************* - * @fn RCC_GetITStatus - * - * @brief Checks whether the specified RCC interrupt has occurred or not. - * - * @param RCC_IT - specifies the RCC interrupt source to check. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * - * @return ITStatus - SET or RESET. - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - if((RCC->INTR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearITPendingBit - * - * @brief Clears the RCC's interrupt pending bits. - * - * @param RCC_IT - specifies the interrupt pending bit to clear. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * - * @return none - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT; -} - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_rcc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/03/18 + * Description : This file provides all the RCC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFFEFFFF) +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF07FF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; +static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFFFEFFFF; + RCC->INTR = 0x009F0000; + + RCC_AdjustHSICalibrationValue(0x10); +} + +/********************************************************************* + * @fn RCC_HSEConfig + * + * @brief Configures the External High Speed oscillator (HSE). + * + * @param RCC_HSE - + * RCC_HSE_OFF - HSE oscillator OFF. + * RCC_HSE_ON - HSE oscillator ON. + * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + RCC->CTLR &= CTLR_HSEON_Reset; + RCC->CTLR &= CTLR_HSEBYP_Reset; + + switch(RCC_HSE) + { + case RCC_HSE_ON: + RCC->CTLR |= CTLR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_WaitForHSEStartUp + * + * @brief Waits for HSE start-up. + * + * @return READY - HSE oscillator is stable and ready to use. + * NoREADY - HSE oscillator not yet ready. + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + + ErrorStatus status = NoREADY; + FlagStatus HSEStatus = RESET; + + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = READY; + } + else + { + status = NoREADY; + } + + return (status); +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 0); + } + else + { + RCC->CTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_PLLConfig + * + * @brief Configures the PLL clock source and multiplication factor. + * + * @param RCC_PLLSource - specifies the PLL entry clock source. + * RCC_PLLSource_HSI_MUL2 - HSI oscillator clock*2 + * selected as PLL clock entry. + * RCC_PLLSource_HSE_MUL2 - HSE oscillator clock*2 + * selected as PLL clock entry. + * + * @return none + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PLL_Mask; + tmpreg |= RCC_PLLSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLLCmd + * + * @brief Enables or disables the PLL. + * Note-The PLL can not be disabled if it is used as system clock. + * + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 24); + } + else + { + RCC->CTLR &= ~(1 << 24); + } +} + +/********************************************************************* + * @fn RCC_SYSCLKConfig + * + * @brief Configures the system clock (SYSCLK). + * + * @param RCC_SYSCLKSource - specifies the clock source used as system clock. + * RCC_SYSCLKSource_HSI - HSI selected as system clock. + * RCC_SYSCLKSource_HSE - HSE selected as system clock. + * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. + * + * @return none + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + uint8_t tmp = 0; + + tmp = *( uint8_t * )CFG0_PLL_TRIM; + + if(tmp != 0xFF) + { + if((RCC_SYSCLKSource == RCC_SYSCLKSource_PLLCLK) && ((RCC->CFGR0 & (1<<16)) == RCC_PLLSource_HSI_MUL2)) + { + RCC_AdjustHSICalibrationValue((tmp & 0x1F)); + } + else + { + RCC_AdjustHSICalibrationValue(0x10); + } + } + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_SW_Mask; + tmpreg |= RCC_SYSCLKSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetSYSCLKSource + * + * @brief Returns the clock source used as system clock. + * + * @return 0x00 - HSI used as system clock. + * 0x04 - HSE used as system clock. + * 0x08 - PLL used as system clock. + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the AHB clock (HCLK). + * + * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. + * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. + * RCC_SYSCLK_Div3 - AHB clock = SYSCLK/3. + * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. + * RCC_SYSCLK_Div5 - AHB clock = SYSCLK/5. + * RCC_SYSCLK_Div6 - AHB clock = SYSCLK/6. + * RCC_SYSCLK_Div7 - AHB clock = SYSCLK/7. + * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. + * RCC_SYSCLK_Div32 - AHB clock = SYSCLK/32. + * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_ITConfig + * + * @brief Enables or disables the specified RCC interrupts. + * + * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/********************************************************************* + * @fn RCC_ADCCLKConfig + * + * @brief Configures the ADC clock (ADCCLK). + * + * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. + * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. + * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. + * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. + * RCC_PCLK2_Div12 - ADC clock = PCLK2/12. + * RCC_PCLK2_Div16 - ADC clock = PCLK2/16. + * RCC_PCLK2_Div24 - ADC clock = PCLK2/24. + * RCC_PCLK2_Div32 - ADC clock = PCLK2/32. + * RCC_PCLK2_Div48 - ADC clock = PCLK2/48. + * RCC_PCLK2_Div64 - ADC clock = PCLK2/64. + * RCC_PCLK2_Div96 - ADC clock = PCLK2/96. + * RCC_PCLK2_Div128 - ADC clock = PCLK2/128. + * + * @return none + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_ADCPRE_Reset_Mask; + tmpreg |= RCC_PCLK2; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_LSICmd + * + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * Note- + * LSI can not be disabled if the IWDG is running. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_LSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->RSTSCKR |= (1 << 0); + } + else + { + RCC->RSTSCKR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks) +{ + uint32_t tmp = 0, pllsource = 0, presc = 0; + + tmp = RCC->CFGR0 & CFGR0_SWS_Mask; + + switch(tmp) + { + case 0x00: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + + case 0x04: + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: + pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; + + if(pllsource == 0x00) + { + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE * 2; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * 2; + } + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + + if(((RCC->CFGR0 & CFGR0_HPRE_Set_Mask) >> 4) < 8) + { + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency / presc; + } + else + { + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + } + + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency; + tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; + tmp = tmp >> 11; + tmp = ((tmp & 0x18) >> 3) | ((tmp & 0x7) << 2); + + if((tmp & 0x13) >= 4) + { + tmp -= 12; + } + else + { + tmp &= 0x3; + } + + presc = ADCPrescTable[tmp]; + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/********************************************************************* + * @fn RCC_AHBPeriphClockCmd + * + * @brief Enables or disables the AHB peripheral clock. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. + * RCC_AHBPeriph_DMA1. + * RCC_AHBPeriph_SRAM. + * Note- + * SRAM clock can be disabled only during sleep mode. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->AHBPCENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCENR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphClockCmd + * + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PCENR |= RCC_APB2Periph; + } + else + { + RCC->APB2PCENR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_PWR. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PCENR |= RCC_APB1Periph; + } + else + { + RCC->APB1PCENR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphResetCmd + * + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PRSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2PRSTR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphResetCmd + * + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_PWR. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PRSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1PRSTR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_ClockSecuritySystemCmd + * + * @brief Enables or disables the Clock Security System. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 19); + } + else + { + RCC->CTLR &= ~(1 << 19); + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * RCC_MCO_HSE - HSE oscillator clock selected. + * RCC_MCO_PLLCLK - PLL clock selected. + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_HSERDY - HSE oscillator clock ready. + * RCC_FLAG_PLLRDY - PLL clock ready. + * RCC_FLAG_LSIRDY - LSI oscillator clock ready. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if(tmp == 1) + { + statusreg = RCC->CTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * Note- + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + +/********************************************************************* + * @fn RCC_GetITStatus + * + * @brief Checks whether the specified RCC interrupt has occurred or not. + * + * @param RCC_IT - specifies the RCC interrupt source to check. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return ITStatus - SET or RESET. + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + if((RCC->INTR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearITPendingBit + * + * @brief Clears the RCC's interrupt pending bits. + * + * @param RCC_IT - specifies the interrupt pending bit to clear. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return none + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT; +} + + + diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_spi.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_spi.c index 0c31046..525e197 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_spi.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_spi.c @@ -1,515 +1,517 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_spi.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the SPI firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* SPI SPE mask */ -#define CTLR1_SPE_Set ((uint16_t)0x0040) -#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) - -/* SPI CRCNext mask */ -#define CTLR1_CRCNext_Set ((uint16_t)0x1000) - -/* SPI CRCEN mask */ -#define CTLR1_CRCEN_Set ((uint16_t)0x2000) -#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) - -/* SPI SSOE mask */ -#define CTLR2_SSOE_Set ((uint16_t)0x0004) -#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) - -/* SPI registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) - - -/********************************************************************* - * @fn SPI_I2S_DeInit - * - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values. - * @param SPIx - where x can be 1 to select the SPI peripheral. - * - * @return none - */ -void SPI_I2S_DeInit(SPI_TypeDef *SPIx) -{ - if(SPIx == SPI1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } -} - -/********************************************************************* - * @fn SPI_Init - * - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * - * @return none - */ -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - tmpreg = SPIx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - - SPIx->CTLR1 = tmpreg; - SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/********************************************************************* - * @fn SPI_StructInit - * - * @brief Fills each SPI_InitStruct member with its default value. - * - * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) -{ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/********************************************************************* - * @fn SPI_Cmd - * - * @brief Enables or disables the specified SPI peripheral. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_SPE_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_SPE_Reset; - } -} - -/********************************************************************* - * @fn SPI_I2S_ITConfig - * - * @brief Enables or disables the specified SPI interrupts. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_IT - specifies the SPI interrupt source to be - * enabled or disabled. - * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. - * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. - * SPI_I2S_IT_ERR - Error interrupt mask. - * NewState: ENABLE or DISABLE. - * @return none - */ -void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0; - - itpos = SPI_I2S_IT >> 4; - itmask = (uint16_t)1 << (uint16_t)itpos; - - if(NewState != DISABLE) - { - SPIx->CTLR2 |= itmask; - } - else - { - SPIx->CTLR2 &= (uint16_t)~itmask; - } -} - -/********************************************************************* - * @fn SPI_I2S_DMACmd - * - * @brief Enables or disables the SPIx DMA interface. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_DMAReq - specifies the SPI DMA transfer request to - * be enabled or disabled. - * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. - * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= SPI_I2S_DMAReq; - } - else - { - SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/********************************************************************* - * @fn SPI_I2S_SendData - * - * @brief Transmits a Data through the SPIx peripheral. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * Data - Data to be transmitted. - * - * @return none - */ -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) -{ - SPIx->DATAR = Data; -} - -/********************************************************************* - * @fn SPI_I2S_ReceiveData - * - * @brief Returns the most recent received data by the SPIx peripheral. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * Data - Data to be transmitted. - * - * @return SPIx->DATAR - The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) -{ - return SPIx->DATAR; -} - -/********************************************************************* - * @fn SPI_NSSInternalSoftwareConfig - * - * @brief Configures internally by software the NSS pin for the selected SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_NSSInternalSoft - - * SPI_NSSInternalSoft_Set - Set NSS pin internally. - * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. - * - * @return none - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) -{ - if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; - } - else - { - SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/********************************************************************* - * @fn SPI_SSOutputCmd - * - * @brief Enables or disables the SS output for the selected SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * NewState - new state of the SPIx SS output. - * - * @return none - */ -void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= CTLR2_SSOE_Set; - } - else - { - SPIx->CTLR2 &= CTLR2_SSOE_Reset; - } -} - -/********************************************************************* - * @fn SPI_DataSizeConfig - * - * @brief Configures the data size for the selected SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_DataSize - specifies the SPI data size. - * SPI_DataSize_16b - Set data frame format to 16bit. - * SPI_DataSize_8b - Set data frame format to 8bit. - * - * @return none - */ -void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) -{ - SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; - SPIx->CTLR1 |= SPI_DataSize; -} - -/********************************************************************* - * @fn SPI_TransmitCRC - * - * @brief Transmit the SPIx CRC value. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * - * @return none - */ -void SPI_TransmitCRC(SPI_TypeDef *SPIx) -{ - SPIx->CTLR1 |= CTLR1_CRCNext_Set; -} - -/********************************************************************* - * @fn SPI_CalculateCRC - * - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * NewState - new state of the SPIx CRC value calculation. - * - * @return none - */ -void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_CRCEN_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_CRCEN_Reset; - } -} - -/********************************************************************* - * @fn SPI_GetCRC - * - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_CRC - specifies the CRC register to be read. - * SPI_CRC_Tx - Selects Tx CRC register. - * SPI_CRC_Rx - Selects Rx CRC register. - * - * @return crcreg: The selected CRC register value. - */ -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - - if(SPI_CRC != SPI_CRC_Rx) - { - crcreg = SPIx->TCRCR; - } - else - { - crcreg = SPIx->RCRCR; - } - - return crcreg; -} - -/********************************************************************* - * @fn SPI_GetCRCPolynomial - * - * @brief Returns the CRC Polynomial register value for the specified SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * - * @return SPIx->CRCR - The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) -{ - return SPIx->CRCR; -} - -/********************************************************************* - * @fn SPI_BiDirectionalLineConfig - * - * @brief Selects the data transfer direction in bi-directional mode - * for the specified SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_Direction - specifies the data transfer direction in - * bi-directional mode. - * SPI_Direction_Tx - Selects Tx transmission direction. - * SPI_Direction_Rx - Selects Rx receive direction. - * - * @return none - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) -{ - if(SPI_Direction == SPI_Direction_Tx) - { - SPIx->CTLR1 |= SPI_Direction_Tx; - } - else - { - SPIx->CTLR1 &= SPI_Direction_Rx; - } -} - -/********************************************************************* - * @fn SPI_I2S_GetFlagStatus - * - * @brief Checks whether the specified SPI flag is set or not. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. - * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. - * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. - * SPI_I2S_FLAG_BSY - Busy flag. - * SPI_I2S_FLAG_OVR - Overrun flag. - * SPI_FLAG_MODF - Mode Fault flag. - * SPI_FLAG_CRCERR - CRC Error flag. - * I2S_FLAG_UDR - Underrun Error flag. - * I2S_FLAG_CHSIDE - Channel Side flag. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearFlag - * - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_FLAG - specifies the SPI flag to clear. - * SPI_FLAG_CRCERR - CRC Error flag. - * Note- - * - OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). - * - UDR (UnderRun error) flag is cleared by a read operation to - * SPI_STATR register (SPI_I2S_GetFlagStatus()). - * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). - * @return FlagStatus: SET or RESET. - */ -void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; -} - -/********************************************************************* - * @fn SPI_I2S_GetITStatus - * - * @brief Checks whether the specified SPI interrupt has occurred or not. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_IT - specifies the SPI interrupt source to check.. - * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. - * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. - * SPI_I2S_IT_OVR - Overrun interrupt. - * SPI_IT_MODF - Mode Fault interrupt. - * SPI_IT_CRCERR - CRC Error interrupt. - * I2S_IT_UDR - Underrun Error interrupt. - * - * @return FlagStatus: SET or RESET. - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - itmask = SPI_I2S_IT >> 4; - itmask = 0x01 << itmask; - enablestatus = (SPIx->CTLR2 & itmask); - - if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearITPendingBit - * - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. - * SPI_IT_CRCERR - CRC Error interrupt. - * Note- - * - OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). - * - UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_STATR register (SPI_I2S_GetITStatus()). - * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable - * the SPI). - * @return none - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - SPIx->STATR = (uint16_t)~itpos; -} - - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_spi.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the SPI firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values. + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * When using SPI slave mode to send data, the CPOL bit should be set to 1. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /*"SPI_FirstBit_LSB" not support SPI slave mode*/ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI interrupts. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState: ENABLE or DISABLE. + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIx DMA interface. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_DMAReq - specifies the SPI DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg: The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI flag is set or not. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * I2S_FLAG_UDR - Underrun Error flag. + * I2S_FLAG_CHSIDE - Channel Side flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * Note- + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). + * @return FlagStatus: SET or RESET. + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * I2S_IT_UDR - Underrun Error interrupt. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * Note- + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable + * the SPI). + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} + + + + + + diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_tim.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_tim.c index f5b1d87..5fc5514 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_tim.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_tim.c @@ -1,2345 +1,2367 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_tim.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the TIM firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* TIM registers bit mask */ -#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) -#define CHCTLR_Offset ((uint16_t)0x0018) -#define CCER_CCE_Set ((uint16_t)0x0001) -#define CCER_CCNE_Set ((uint16_t)0x0004) - -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/********************************************************************* - * @fn TIM_DeInit - * - * @brief Deinitializes the TIMx peripheral registers to their default - * reset values. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * - * @return none - */ -void TIM_DeInit(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if(TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } -} - -/********************************************************************* - * @fn TIM_TimeBaseInit - * - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef - * structure. - * - * @return none - */ -void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - tmpcr1 = TIMx->CTLR1; - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - - TIMx->CTLR1 = tmpcr1; - TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if(TIMx == TIM1) - { - TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; -} - -/********************************************************************* - * @fn TIM_OC1Init - * - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if(TIMx == TIM1) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); - - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2Init - * - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if(TIMx == TIM1) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3Init - * - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if(TIMx == TIM1) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4Init - * - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if(TIMx == TIM1) - { - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ICInit - * - * @brief IInitializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_PWMIConfig - * - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external - * PWM signal. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - - if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_BDTRConfig - * - * @brief Configures the: Break feature, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable). - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/********************************************************************* - * @fn TIM_TimeBaseStructInit - * - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * - * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. - * - * @return none - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/********************************************************************* - * @fn TIM_OCStructInit - * - * @brief Fills each TIM_OCInitStruct member with its default value. - * - * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/********************************************************************* - * @fn TIM_ICStructInit - * - * @brief Fills each TIM_ICInitStruct member with its default value. - * - * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/********************************************************************* - * @fn TIM_BDTRStructInit - * - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * - * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/********************************************************************* - * @fn TIM_Cmd - * - * @brief Enables or disables the specified TIM peripheral. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_CEN; - } - else - { - TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); - } -} - -/********************************************************************* - * @fn TIM_CtrlPWMOutputs - * - * @brief Enables or disables the TIM peripheral Main Outputs. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->BDTR |= TIM_MOE; - } - else - { - TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); - } -} - -/********************************************************************* - * @fn TIM_ITConfig - * - * @brief Enables or disables the specified TIM interrupts. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->DMAINTENR |= TIM_IT; - } - else - { - TIMx->DMAINTENR &= (uint16_t)~TIM_IT; - } -} - -/********************************************************************* - * @fn TIM_GenerateEvent - * - * @brief Configures the TIMx event to be generate by software. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) -{ - TIMx->SWEVGR = TIM_EventSource; -} - -/********************************************************************* - * @fn TIM_DMAConfig - * - * @brief Configures the TIMx's DMA interface. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_DMABase: DMA Base address. - * TIM_DMABase_CR. - * TIM_DMABase_CR2. - * TIM_DMABase_SMCR. - * TIM_DMABase_DIER. - * TIM1_DMABase_SR. - * TIM_DMABase_EGR. - * TIM_DMABase_CCMR1. - * TIM_DMABase_CCMR2. - * TIM_DMABase_CCER. - * TIM_DMABase_CNT. - * TIM_DMABase_PSC. - * TIM_DMABase_CCR1. - * TIM_DMABase_CCR2. - * TIM_DMABase_CCR3. - * TIM_DMABase_CCR4. - * TIM_DMABase_BDTR. - * TIM_DMABase_DCR. - * TIM_DMABurstLength - DMA Burst length. - * TIM_DMABurstLength_1Transfer. - * TIM_DMABurstLength_18Transfers. - * - * @return none - */ -void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; -} - -/********************************************************************* - * @fn TIM_DMACmd - * - * @brief Enables or disables the TIMx's DMA Requests. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_DMASource - specifies the DMA Request sources. - * TIM_DMA_Update - TIM update Interrupt source. - * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. - * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. - * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. - * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. - * TIM_DMA_COM - TIM Commutation DMA source. - * TIM_DMA_Trigger - TIM Trigger DMA source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->DMAINTENR |= TIM_DMASource; - } - else - { - TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; - } -} - -/********************************************************************* - * @fn TIM_InternalClockConfig - * - * @brief Configures the TIMx internal Clock. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * - * @return none - */ -void TIM_InternalClockConfig(TIM_TypeDef *TIMx) -{ - TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); -} - -/********************************************************************* - * @fn TIM_ITRxExternalClockConfig - * - * @brief Configures the TIMx Internal Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_InputTriggerSource: Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * - * @return none - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_TIxExternalClockConfig - * - * @brief Configures the TIMx Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_TIxExternalCLKSource - Trigger source. - * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. - * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. - * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. - * TIM_ICPolarity - specifies the TIx Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_DMA_COM - TIM Commutation DMA source. - * TIM_DMA_Trigger - TIM Trigger DMA source. - * ICFilter - specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_ETRClockMode1Config - * - * @brief Configures the External clock Mode1. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_SlaveMode_External1; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_TS_ETRF; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_ETRClockMode2Config - * - * @brief Configures the External clock Mode2. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - TIMx->SMCFGR |= TIM_ECE; -} - -/********************************************************************* - * @fn TIM_ETRConfig - * - * @brief Configures the TIMx External Trigger (ETR). - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= SMCFGR_ETR_Mask; - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_PrescalerConfig - * - * @brief Configures the TIMx Prescaler. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * Prescaler - specifies the Prescaler Register value. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. - * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. - * - * @return none - */ -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - TIMx->PSC = Prescaler; - TIMx->SWEVGR = TIM_PSCReloadMode; -} - -/********************************************************************* - * @fn TIM_CounterModeConfig - * - * @brief Specifies the TIMx Counter Mode to be used. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_CounterMode - specifies the Counter Mode to be used. - * TIM_CounterMode_Up - TIM Up Counting Mode. - * TIM_CounterMode_Down - TIM Down Counting Mode. - * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. - * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. - * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. - * - * @return none - */ -void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - tmpcr1 = TIMx->CTLR1; - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= TIM_CounterMode; - TIMx->CTLR1 = tmpcr1; -} - -/********************************************************************* - * @fn TIM_SelectInputTrigger - * - * @brief Selects the Input Trigger source. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_InputTriggerSource - The Input Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * TIM_TS_TI1F_ED - TI1 Edge Detector. - * TIM_TS_TI1FP1 - Filtered Timer Input 1. - * TIM_TS_TI2FP2 - Filtered Timer Input 2. - * TIM_TS_ETRF - External Trigger input. - * - * @return none - */ -void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_InputTriggerSource; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_EncoderInterfaceConfig - * - * @brief Configures the TIMx Encoder Interface. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_EncoderMode - specifies the TIMx Encoder Mode. - * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending - * on TI2FP2 level. - * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending - * on TI1FP1 level. - * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and - * TI2FP2 edges depending. - * TIM_IC1Polarity - specifies the IC1 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TTIM_ICPolarity_Rising - IC Rising edge. - * TIM_IC2Polarity - specifies the IC2 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TIM_ICPolarity_Rising - IC Rising edge. - * - * @return none - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_EncoderMode; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); - tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; - tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - TIMx->SMCFGR = tmpsmcr; - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ForcedOC1Config - * - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC1REF. - * TIM_ForcedAction_InActive - Force inactive level on OC1REF. - * - * @return none - */ -void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); - tmpccmr1 |= TIM_ForcedAction; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC2Config - * - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC2REF. - * TIM_ForcedAction_InActive - Force inactive level on OC2REF. - * - * @return none - */ -void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC3Config - * - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC3REF. - * TIM_ForcedAction_InActive - Force inactive level on OC3REF. - * - * @return none - */ -void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); - tmpccmr2 |= TIM_ForcedAction; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ForcedOC4Config - * - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC4REF. - * TIM_ForcedAction_InActive - Force inactive level on OC4REF. - * - * @return none - */ -void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ARRPreloadConfig - * - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_ARPE; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); - } -} - -/********************************************************************* - * @fn TIM_SelectCOM - * - * @brief Selects the TIM peripheral Commutation event. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCUS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); - } -} - -/********************************************************************* - * @fn TIM_SelectCCDMA - * - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCDS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); - } -} - -/********************************************************************* - * @fn TIM_CCPreloadControl - * - * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. - * reset values (Affects also the I2Ss). - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCPC; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); - } -} - -/********************************************************************* - * @fn TIM_OC1PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); - tmpccmr1 |= TIM_OCPreload; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC2PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC3PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); - tmpccmr2 |= TIM_OCPreload; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC4PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC1FastConfig - * - * @brief Configures the TIMx Output Compare 1 Fast feature. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); - tmpccmr1 |= TIM_OCFast; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC2FastConfig - * - * @brief Configures the TIMx Output Compare 2 Fast feature. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC3FastConfig - * - * @brief Configures the TIMx Output Compare 3 Fast feature. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); - tmpccmr2 |= TIM_OCFast; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC4FastConfig - * - * @brief Configures the TIMx Output Compare 4 Fast feature. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC1Ref - * - * @brief Clears or safeguards the OCREF1 signal on an external event. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); - tmpccmr1 |= TIM_OCClear; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC2Ref - * - * @brief Clears or safeguards the OCREF2 signal on an external event. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC3Ref - * - * @brief Clears or safeguards the OCREF3 signal on an external event. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); - tmpccmr2 |= TIM_OCClear; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC4Ref - * - * @brief Clears or safeguards the OCREF4 signal on an external event. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC1PolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC1 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); - tmpccer |= TIM_OCPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC1NPolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); - tmpccer |= TIM_OCNPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2PolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC2 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2NPolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3PolarityConfig - * - * @brief Configures the TIMx Channel 3 polarity. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3NPolarityConfig - * - * @brief Configures the TIMx Channel 3N polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC2N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4PolarityConfig - * - * @brief Configures the TIMx Channel 2 polarity. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_CCxCmd - * - * @brief Enables or disables the TIM Capture Compare Channel x. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_CCx - specifies the TIM Channel CCxE bit new state. - * TIM_CCx_Enable. - * TIM_CCx_Disable. - * - * @return none - */ -void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - tmp = CCER_CCE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_CCxNCmd - * - * @brief Enables or disables the TIM Capture Compare Channel xN. - * - * @param TIMx - where x can be 1 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. - * TIM_CCxN_Enable. - * TIM_CCxN_Disable. - * - * @return none - */ -void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - tmp = CCER_CCNE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_SelectOCxM - * - * @brief Selects the TIM Output Compare Mode. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_OCMode - specifies the TIM Output Compare Mode. - * TIM_OCMode_Timing. - * TIM_OCMode_Active. - * TIM_OCMode_Toggle. - * TIM_OCMode_PWM1. - * TIM_OCMode_PWM2. - * TIM_ForcedAction_Active. - * TIM_ForcedAction_InActive. - * - * @return none - */ -void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - tmp = (uint32_t)TIMx; - tmp += CHCTLR_Offset; - tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp1; - - if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel >> 1); - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); - *(__IO uint32_t *)tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); - *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/********************************************************************* - * @fn TIM_UpdateDisableConfig - * - * @brief Enables or Disables the TIMx Update event. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_UDIS; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); - } -} - -/********************************************************************* - * @fn TIM_UpdateRequestConfig - * - * @brief Configures the TIMx Update Request Interrupt source. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_UpdateSource - specifies the Update source. - * TIM_UpdateSource_Regular. - * TIM_UpdateSource_Global. - * - * @return none - */ -void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) -{ - if(TIM_UpdateSource != TIM_UpdateSource_Global) - { - TIMx->CTLR1 |= TIM_URS; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); - } -} - -/********************************************************************* - * @fn TIM_SelectHallSensor - * - * @brief Enables or disables the TIMx's Hall sensor interface. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_TI1S; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); - } -} - -/********************************************************************* - * @fn TIM_SelectOnePulseMode - * - * @brief Selects the TIMx's One Pulse Mode. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_OPMode - specifies the OPM Mode to be used. - * TIM_OPMode_Single. - * TIM_OPMode_Repetitive. - * - * @return none - */ -void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); - TIMx->CTLR1 |= TIM_OPMode; -} - -/********************************************************************* - * @fn TIM_SelectOutputTrigger - * - * @brief Selects the TIMx Trigger Output Mode. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_TRGOSource - specifies the Trigger Output source. - * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is - * used as the trigger output (TRGO). - * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the - * trigger output (TRGO). - * TIM_TRGOSource_Update - The update event is selected as the - * trigger output (TRGO). - * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse - * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). - * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). - * - * @return none - */ -void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) -{ - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); - TIMx->CTLR2 |= TIM_TRGOSource; -} - -/********************************************************************* - * @fn TIM_SelectSlaveMode - * - * @brief Selects the TIMx Slave Mode. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_SlaveMode - specifies the Timer Slave Mode. - * TIM_SlaveMode_Reset - Rising edge of the selected trigger - * signal (TRGI) re-initializes. - * TIM_SlaveMode_Gated - The counter clock is enabled when the - * trigger signal (TRGI) is high. - * TIM_SlaveMode_Trigger - The counter starts at a rising edge - * of the trigger TRGI. - * TIM_SlaveMode_External1 - Rising edges of the selected trigger - * (TRGI) clock the counter. - * - * @return none - */ -void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) -{ - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); - TIMx->SMCFGR |= TIM_SlaveMode; -} - -/********************************************************************* - * @fn TIM_SelectMasterSlaveMode - * - * @brief Sets or Resets the TIMx Master/Slave Mode. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. - * TIM_MasterSlaveMode_Enable - synchronization between the current - * timer and its slaves (through TRGO). - * TIM_MasterSlaveMode_Disable - No action. - * - * @return none - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) -{ - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); - TIMx->SMCFGR |= TIM_MasterSlaveMode; -} - -/********************************************************************* - * @fn TIM_SetCounter - * - * @brief Sets the TIMx Counter Register value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * Counter - specifies the Counter register new value. - * - * @return none - */ -void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) -{ - TIMx->CNT = Counter; -} - -/********************************************************************* - * @fn TIM_SetAutoreload - * - * @brief Sets the TIMx Autoreload Register value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * Autoreload - specifies the Autoreload register new value. - * - * @return none - */ -void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) -{ - TIMx->ATRLR = Autoreload; -} - -/********************************************************************* - * @fn TIM_SetCompare1 - * - * @brief Sets the TIMx Capture Compare1 Register value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) -{ - TIMx->CH1CVR = Compare1; -} - -/********************************************************************* - * @fn TIM_SetCompare2 - * - * @brief Sets the TIMx Capture Compare2 Register value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) -{ - TIMx->CH2CVR = Compare2; -} - -/********************************************************************* - * @fn TIM_SetCompare3 - * - * @brief Sets the TIMx Capture Compare3 Register value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) -{ - TIMx->CH3CVR = Compare3; -} - -/********************************************************************* - * @fn TIM_SetCompare4 - * - * @brief Sets the TIMx Capture Compare4 Register value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) -{ - TIMx->CH4CVR = Compare4; -} - -/********************************************************************* - * @fn TIM_SetIC1Prescaler - * - * @brief Sets the TIMx Input Capture 1 prescaler. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); - TIMx->CHCTLR1 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC2Prescaler - * - * @brief Sets the TIMx Input Capture 2 prescaler. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); - TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetIC3Prescaler - * - * @brief Sets the TIMx Input Capture 3 prescaler. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); - TIMx->CHCTLR2 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC4Prescaler - * - * @brief Sets the TIMx Input Capture 4 prescaler. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); - TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetClockDivision - * - * @brief Sets the TIMx Clock Division value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_CKD - specifies the clock division value. - * TIM_CKD_DIV1 - TDTS = Tck_tim. - * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. - * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. - * - * @return none - */ -void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); - TIMx->CTLR1 |= TIM_CKD; -} - -/********************************************************************* - * @fn TIM_GetCapture1 - * - * @brief Gets the TIMx Input Capture 1 value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * - * @return TIMx->CH1CVR - Capture Compare 1 Register value. - */ -uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) -{ - return TIMx->CH1CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture2 - * - * @brief Gets the TIMx Input Capture 2 value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * - * @return TIMx->CH2CVR - Capture Compare 2 Register value. - */ -uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) -{ - return TIMx->CH2CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture3 - * - * @brief Gets the TIMx Input Capture 3 value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * - * @return TIMx->CH2CVR - Capture Compare 2 Register value. - */ -uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) -{ - return TIMx->CH3CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture4 - * - * @brief Gets the TIMx Input Capture 4 value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * - * @return TIMx->CH4CVR - Capture Compare 4 Register value. - */ -uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) -{ - return TIMx->CH4CVR; -} - -/********************************************************************* - * @fn TIM_GetCounter - * - * @brief Gets the TIMx Counter value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * - * @return TIMx->CNT - Counter Register value. - */ -uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) -{ - return TIMx->CNT; -} - -/********************************************************************* - * @fn TIM_GetPrescaler - * - * @brief Gets the TIMx Prescaler value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * - * @return TIMx->PSC - Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) -{ - return TIMx->PSC; -} - -/********************************************************************* - * @fn TIM_GetFlagStatus - * - * @brief Checks whether the specified TIM flag is set or not. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return SET or RESET. - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - - if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearFlag - * - * @brief Clears the TIMx's pending flags. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return none - */ -void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - TIMx->INTFR = (uint16_t)~TIM_FLAG; -} - -/********************************************************************* - * @fn TIM_GetITStatus - * - * @brief Checks whether the TIM interrupt has occurred or not. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - - itstatus = TIMx->INTFR & TIM_IT; - - itenable = TIMx->DMAINTENR & TIM_IT; - if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearITPendingBit - * - * @brief Clears the TIMx's interrupt pending bits. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - TIMx->INTFR = (uint16_t)~TIM_IT; -} - -/********************************************************************* - * @fn TI1_Config - * - * @brief Configure the TI1 as Input. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); - - TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI2_Config - * - * @brief Configure the TI2 as Input. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 2 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 2 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 2 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); - - TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI3_Config - * - * @brief Configure the TI3 as Input. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 3 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 3 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 3 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); - - TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI4_Config - * - * @brief Configure the TI4 as Input. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 4 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 4 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 4 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); - - TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC4NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_tim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/25 + * Description : This file provides all the TIM firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + + TIMx->CTLR1 = tmpcr1; + TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if(TIMx == TIM1) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if(TIMx == TIM1) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +/********************************************************************* + * @fn TIM_GenerateEvent + * + * @brief Configures the TIMx event to be generate by software. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_DMABase: DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values . + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 2 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) +{ + TIMx->CNT = Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) +{ + TIMx->ATRLR = Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) +{ + TIMx->CH1CVR = Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) +{ + TIMx->CH2CVR = Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) +{ + TIMx->CH3CVR = Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) +{ + TIMx->CH4CVR = Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture3 + * + * @brief Gets the TIMx Input Capture 3 value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CH3CVR - Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return SET or RESET. + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 2 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 2 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 2 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 3 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 3 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 3 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 4 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 4 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 4 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_IndicateCaptureLevelCmd + * + * @brief Enables or disables the TIMx capture level indication. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState) + { + TIMx->CTLR1 |= (1<<15); + } + else{ + TIMx->CTLR1 &= ~(1<<15); + } +} + diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_usart.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_usart.c index 246e8e7..d332988 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_usart.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_usart.c @@ -1,796 +1,796 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_usart.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the USART firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* USART_Private_Defines */ -#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ -#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ - -#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ - -#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ -#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ -#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ -#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ - -#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ -#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ - -#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ -#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ -#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ - -#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ -#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ - -#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ -#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ - -#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ -#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ - -#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ -#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ - -#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ -#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ -#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ -#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ -#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ - -/* USART OverSampling-8 Mask */ -#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ -#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ - -/* USART One Bit Sampling Mask */ -#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ -#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ - -/********************************************************************* - * @fn USART_DeInit - * - * @brief Deinitializes the USARTx peripheral registers to their default - * reset values. - * - * @param USARTx - where x can be 1 to select the UART peripheral. - * - * @return none - */ -void USART_DeInit(USART_TypeDef *USARTx) -{ - if(USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } -} - -/********************************************************************* - * @fn USART_Init - * - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct. - * - * @param USARTx - where x can be 1 to select the UART peripheral. - * USART_InitStruct - pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified - * USART peripheral. - * - * @return none - */ -void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - uint32_t usartxbase = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - - if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - } - - usartxbase = (uint32_t)USARTx; - tmpreg = USARTx->CTLR2; - tmpreg &= CTLR2_STOP_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - USARTx->CTLR2 = (uint16_t)tmpreg; - tmpreg = USARTx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - USARTx->CTLR1 = (uint16_t)tmpreg; - - tmpreg = USARTx->CTLR3; - tmpreg &= CTLR3_CLEAR_Mask; - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - USARTx->CTLR3 = (uint16_t)tmpreg; - - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if(usartxbase == USART1_BASE) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) - { - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else - { - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - USARTx->BRR = (uint16_t)tmpreg; -} - -/********************************************************************* - * @fn USART_StructInit - * - * @brief Fills each USART_InitStruct member with its default value. - * - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void USART_StructInit(USART_InitTypeDef *USART_InitStruct) -{ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/********************************************************************* - * @fn USART_ClockInit - * - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * - * @return none - */ -void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - - tmpreg = USARTx->CTLR2; - tmpreg &= CTLR2_CLOCK_CLEAR_Mask; - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - USARTx->CTLR2 = (uint16_t)tmpreg; -} - -/********************************************************************* - * @fn USART_ClockStructInit - * - * @brief Fills each USART_ClockStructInit member with its default value. - * - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * - * @return none - */ -void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/********************************************************************* - * @fn USART_Cmd - * - * @brief Enables or disables the specified USART peripheral. - * reset values (Affects also the I2Ss). - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_UE_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_UE_Reset; - } -} - -/********************************************************************* - * @fn USART_ITConfig - * - * @brief Enables or disables the specified USART interrupts. - * reset values (Affects also the I2Ss). - * - * @param USARTx - where x can be to select the USART peripheral. - * USART_IT - specifies the USART interrupt sources to be enabled or disabled. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Transmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_PE - Parity Error interrupt. - * USART_IT_ERR - Error interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - - - usartxbase = (uint32_t)USARTx; - usartreg = (((uint8_t)USART_IT) >> 0x05); - itpos = USART_IT & IT_Mask; - itmask = (((uint32_t)0x01) << itpos); - - if(usartreg == 0x01) - { - usartxbase += 0x0C; - } - else if(usartreg == 0x02) - { - usartxbase += 0x10; - } - else - { - usartxbase += 0x14; - } - - if(NewState != DISABLE) - { - *(__IO uint32_t *)usartxbase |= itmask; - } - else - { - *(__IO uint32_t *)usartxbase &= ~itmask; - } -} - -/********************************************************************* - * @fn USART_DMACmd - * - * @brief Enables or disables the USART DMA interface. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * USART_DMAReq - specifies the DMA request. - * USART_DMAReq_Tx - USART DMA transmit request. - * USART_DMAReq_Rx - USART DMA receive request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= USART_DMAReq; - } - else - { - USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; - } -} - -/********************************************************************* - * @fn USART_SetAddress - * - * @brief Sets the address of the USART node. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * USART_Address - Indicates the address of the USART node. - * - * @return none - */ -void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) -{ - USARTx->CTLR2 &= CTLR2_Address_Mask; - USARTx->CTLR2 |= USART_Address; -} - -/********************************************************************* - * @fn USART_WakeUpConfig - * - * @brief Selects the USART WakeUp method. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * USART_WakeUp - specifies the USART wakeup method. - * USART_WakeUp_IdleLine - WakeUp by an idle line detection. - * USART_WakeUp_AddressMark - WakeUp by an address mark. - * - * @return none - */ -void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) -{ - USARTx->CTLR1 &= CTLR1_WAKE_Mask; - USARTx->CTLR1 |= USART_WakeUp; -} - -/********************************************************************* - * @fn USART_ReceiverWakeUpCmd - * - * @brief Determines if the USART is in mute mode or not. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_RWU_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_RWU_Reset; - } -} - -/********************************************************************* - * @fn USART_LINBreakDetectLengthConfig - * - * @brief Sets the USART LIN Break detection length. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * USART_LINBreakDetectLength - specifies the LIN break detection length. - * USART_LINBreakDetectLength_10b - 10-bit break detection. - * USART_LINBreakDetectLength_11b - 11-bit break detection. - * - * @return none - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) -{ - USARTx->CTLR2 &= CTLR2_LBDL_Mask; - USARTx->CTLR2 |= USART_LINBreakDetectLength; -} - -/********************************************************************* - * @fn USART_LINCmd - * - * @brief Enables or disables the USART LIN mode. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR2 |= CTLR2_LINEN_Set; - } - else - { - USARTx->CTLR2 &= CTLR2_LINEN_Reset; - } -} - -/********************************************************************* - * @fn USART_SendData - * - * @brief Transmits single data through the USARTx peripheral. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * Data - the data to transmit. - * - * @return none - */ -void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) -{ - USARTx->DATAR = (Data & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_ReceiveData - * - * @brief Returns the most recent received data by the USARTx peripheral. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * - * @return The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef *USARTx) -{ - return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_SendBreak - * - * @brief Transmits break characters. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * - * @return none - */ -void USART_SendBreak(USART_TypeDef *USARTx) -{ - USARTx->CTLR1 |= CTLR1_SBK_Set; -} - -/********************************************************************* - * @fn USART_SetGuardTime - * - * @brief Sets the specified USART guard time. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * USART_GuardTime - specifies the guard time. - * - * @return none - */ -void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) -{ - USARTx->GPR &= GPR_LSB_Mask; - USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/********************************************************************* - * @fn USART_SetPrescaler - * - * @brief Sets the system clock prescaler. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * USART_Prescaler - specifies the prescaler clock. - * - * @return none - */ -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) -{ - USARTx->GPR &= GPR_MSB_Mask; - USARTx->GPR |= USART_Prescaler; -} - -/********************************************************************* - * @fn USART_SmartCardCmd - * - * @brief Enables or disables the USART Smart Card mode. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_SCEN_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_SCEN_Reset; - } -} - -/********************************************************************* - * @fn USART_SmartCardNACKCmd - * - * @brief Enables or disables NACK transmission. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_NACK_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_NACK_Reset; - } -} - -/********************************************************************* - * @fn USART_HalfDuplexCmd - * - * @brief Enables or disables the USART Half Duplex communication. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_HDSEL_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_HDSEL_Reset; - } -} - -/********************************************************************* - * @fn USART_OverSampling8Cmd - * - * @brief Enables or disables the USART's 8x oversampling mode. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * Note- - * This function has to be called before calling USART_Init() - * function in order to have correct baudrate Divider value. - * @return none - */ -void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_OVER8_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_OVER8_Reset; - } -} - -/********************************************************************* - * @fn USART_OneBitMethodCmd - * - * @brief Enables or disables the USART's one bit sampling method. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_ONEBITE_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_ONEBITE_Reset; - } -} - -/********************************************************************* - * @fn USART_IrDAConfig - * - * @brief Configures the USART's IrDA interface. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * USART_IrDAMode - specifies the IrDA mode. - * USART_IrDAMode_LowPower. - * USART_IrDAMode_Normal. - * - * @return none - */ -void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) -{ - USARTx->CTLR3 &= CTLR3_IRLP_Mask; - USARTx->CTLR3 |= USART_IrDAMode; -} - -/********************************************************************* - * @fn USART_IrDACmd - * - * @brief Enables or disables the USART's IrDA interface. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_IREN_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_IREN_Reset; - } -} - -/********************************************************************* - * @fn USART_GetFlagStatus - * - * @brief Checks whether the specified USART flag is set or not. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * USART_FLAG - specifies the flag to check. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TXE - Transmit data register empty flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * USART_FLAG_IDLE - Idle Line detection flag. - * USART_FLAG_ORE - OverRun Error flag. - * USART_FLAG_NE - Noise Error flag. - * USART_FLAG_FE - Framing Error flag. - * USART_FLAG_PE - Parity Error flag. - * - * @return bitstatus: SET or RESET - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearFlag - * - * @brief Clears the USARTx's pending flags. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * USART_FLAG - specifies the flag to clear. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * Note- - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DATAR register (USART_ReceiveData()). - * - RXNE flag can be also cleared by a read to the USART_DATAR register - * (USART_ReceiveData()). - * - TC flag can be also cleared by software sequence: a read operation to - * USART_STATR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DATAR register (USART_SendData()). - * - TXE flag is cleared only by a write to the USART_DATAR register - * (USART_SendData()). - * @return none - */ -void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - - USARTx->STATR = (uint16_t)~USART_FLAG; -} - -/********************************************************************* - * @fn USART_GetITStatus - * - * @brief Checks whether the specified USART interrupt has occurred or not. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * USART_IT - specifies the USART interrupt source to check. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Tansmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. - * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. - * USART_IT_NE - Noise Error interrupt. - * USART_IT_FE - Framing Error interrupt. - * USART_IT_PE - Parity Error interrupt. - * - * @return bitstatus: SET or RESET. - */ -ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - - usartreg = (((uint8_t)USART_IT) >> 0x05); - itmask = USART_IT & IT_Mask; - itmask = (uint32_t)0x01 << itmask; - - if(usartreg == 0x01) - { - itmask &= USARTx->CTLR1; - } - else if(usartreg == 0x02) - { - itmask &= USARTx->CTLR2; - } - else - { - itmask &= USARTx->CTLR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->STATR; - - if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearITPendingBit - * - * @brief Clears the USARTx's interrupt pending bits. - * - * @param USARTx - where x can be 1 to select the USART peripheral. - * USART_IT - specifies the interrupt pending bit to clear. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * Note- - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_STATR register - * (USART_GetITStatus()) followed by a read operation to USART_DATAR register - * (USART_ReceiveData()). - * - RXNE pending bit can be also cleared by a read to the USART_DATAR register - * (USART_ReceiveData()). - * - TC pending bit can be also cleared by software sequence: a read - * operation to USART_STATR register (USART_GetITStatus()) followed by a write - * operation to USART_DATAR register (USART_SendData()). - * - TXE pending bit is cleared only by a write to the USART_DATAR register - * (USART_SendData()). - * @return none - */ -void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->STATR = (uint16_t)~itmask; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_usart.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the USART firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else + { + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * reset values . + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values . + * + * @param USARTx - where x can be to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_OverSampling8Cmd + * + * @brief Enables or disables the USART's 8x oversampling mode. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * Note- + * This function has to be called before calling USART_Init() + * function in order to have correct baudrate Divider value. + * @return none + */ +void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_OVER8_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_OVER8_Reset; + } +} + +/********************************************************************* + * @fn USART_OneBitMethodCmd + * + * @brief Enables or disables the USART's one bit sampling method. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_ONEBITE_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_ONEBITE_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return bitstatus: SET or RESET + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DATAR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_STATR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DATAR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return bitstatus: SET or RESET. + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_STATR register + * (USART_GetITStatus()) followed by a read operation to USART_DATAR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_STATR register (USART_GetITStatus()) followed by a write + * operation to USART_DATAR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_wwdg.c b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_wwdg.c index dea550e..80c6872 100644 --- a/system/CH32V00x/SRC/Peripheral/src/ch32v00x_wwdg.c +++ b/system/CH32V00x/SRC/Peripheral/src/ch32v00x_wwdg.c @@ -1,141 +1,141 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_wwdg.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : This file provides all the WWDG firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* CTLR register bit mask */ -#define CTLR_WDGA_Set ((uint32_t)0x00000080) - -/* CFGR register bit mask */ -#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) -#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) -#define BIT_Mask ((uint8_t)0x7F) - -/********************************************************************* - * @fn WWDG_DeInit - * - * @brief Deinitializes the WWDG peripheral registers to their default reset values - * - * @return none - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/********************************************************************* - * @fn WWDG_SetPrescaler - * - * @brief Sets the WWDG Prescaler - * - * @param WWDG_Prescaler - specifies the WWDG Prescaler - * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 - * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 - * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 - * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 - * - * @return none - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; - tmpreg |= WWDG_Prescaler; - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_SetWindowValue - * - * @brief Sets the WWDG window value - * - * @param WindowValue - specifies the window value to be compared to the - * downcounter,which must be lower than 0x80 - * - * @return none - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - tmpreg = WWDG->CFGR & CFGR_W_Mask; - - tmpreg |= WindowValue & (uint32_t)BIT_Mask; - - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_EnableIT - * - * @brief Enables the WWDG Early Wakeup interrupt(EWI) - * - * @return none - */ -void WWDG_EnableIT(void) -{ - WWDG->CFGR |= (1 << 9); -} - -/********************************************************************* - * @fn WWDG_SetCounter - * - * @brief Sets the WWDG counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * - * @return none - */ -void WWDG_SetCounter(uint8_t Counter) -{ - WWDG->CTLR = Counter & BIT_Mask; -} - -/********************************************************************* - * @fn WWDG_Enable - * - * @brief Enables WWDG and load the counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * @return none - */ -void WWDG_Enable(uint8_t Counter) -{ - WWDG->CTLR = CTLR_WDGA_Set | Counter; -} - -/********************************************************************* - * @fn WWDG_GetFlagStatus - * - * @brief Checks whether the Early Wakeup interrupt flag is set or not - * - * @return The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - return (FlagStatus)(WWDG->STATR); -} - -/********************************************************************* - * @fn WWDG_ClearFlag - * - * @brief Clears Early Wakeup interrupt flag - * - * @return none - */ -void WWDG_ClearFlag(void) -{ - WWDG->STATR = (uint32_t)RESET; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_wwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the WWDG firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/system/CH32V00x/SRC/Startup/startup_ch32v00x.S b/system/CH32V00x/SRC/Startup/startup_ch32v00x.S index 200b50e..da170db 100644 --- a/system/CH32V00x/SRC/Startup/startup_ch32v00x.S +++ b/system/CH32V00x/SRC/Startup/startup_ch32v00x.S @@ -1,8 +1,8 @@ ;/********************************** (C) COPYRIGHT ******************************* ;* File Name : startup_ch32v00x.s ;* Author : WCH -;* Version : V1.0.0 -;* Date : 2022/08/08 +;* Version : V1.0.1 +;* Date : 2023/12/11 ;* Description : vector table for eclipse toolchain. ;********************************************************************************* ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -86,34 +86,35 @@ _start: .weak TIM1_CC_IRQHandler .weak TIM2_IRQHandler -NMI_Handler: 1: j 1b -HardFault_Handler: 1: j 1b -SysTick_Handler: 1: j 1b -SW_Handler: 1: j 1b -WWDG_IRQHandler: 1: j 1b -PVD_IRQHandler: 1: j 1b -FLASH_IRQHandler: 1: j 1b -RCC_IRQHandler: 1: j 1b -EXTI7_0_IRQHandler: 1: j 1b -AWU_IRQHandler: 1: j 1b -DMA1_Channel1_IRQHandler: 1: j 1b -DMA1_Channel2_IRQHandler: 1: j 1b -DMA1_Channel3_IRQHandler: 1: j 1b -DMA1_Channel4_IRQHandler: 1: j 1b -DMA1_Channel5_IRQHandler: 1: j 1b -DMA1_Channel6_IRQHandler: 1: j 1b -DMA1_Channel7_IRQHandler: 1: j 1b -ADC1_IRQHandler: 1: j 1b -I2C1_EV_IRQHandler: 1: j 1b -I2C1_ER_IRQHandler: 1: j 1b -USART1_IRQHandler: 1: j 1b -SPI1_IRQHandler: 1: j 1b -TIM1_BRK_IRQHandler: 1: j 1b -TIM1_UP_IRQHandler: 1: j 1b -TIM1_TRG_COM_IRQHandler: 1: j 1b -TIM1_CC_IRQHandler: 1: j 1b -TIM2_IRQHandler: 1: j 1b - +NMI_Handler: +HardFault_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI7_0_IRQHandler: +AWU_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +USART1_IRQHandler: +SPI1_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +1: + j 1b .section .text.handle_reset, "ax", @progbits .weak handle_reset @@ -126,7 +127,7 @@ handle_reset: 1: la sp, _eusrstack 2: - /* Load data section from flash to RAM */ +/* Load data section from flash to RAM */ la a0, _data_lma la a1, _data_vma la a2, _edata @@ -138,7 +139,7 @@ handle_reset: addi a1, a1, 4 bltu a1, a2, 1b 2: - /* clear bss section */ +/* Clear bss section */ la a0, _sbss la a1, _ebss bgeu a0, a1, 2f @@ -147,20 +148,17 @@ handle_reset: addi a0, a0, 4 bltu a0, a1, 1b 2: - li t0, 0x80 +/* Enable global interrupt and configure privileged mode */ + li t0, 0x1880 csrw mstatus, t0 - +/* Enable interrupt nesting and hardware stack */ li t0, 0x3 csrw 0x804, t0 - +/* Configure the interrupt vector table recognition mode and entry address mode */ la t0, _start ori t0, t0, 3 csrw mtvec, t0 - la a0, __libc_fini_array - call atexit - call __libc_init_array - jal SystemInit la t0, main csrw mepc, t0 diff --git a/system/CH32V00x/USER/ch32v00x_conf.h b/system/CH32V00x/USER/ch32v00x_conf.h index 1d4a287..b2161d5 100644 --- a/system/CH32V00x/USER/ch32v00x_conf.h +++ b/system/CH32V00x/USER/ch32v00x_conf.h @@ -1,40 +1,40 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_conf.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/08/08 - * Description : Library configuration file. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V00x_CONF_H -#define __CH32V00x_CONF_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - - -#endif /* __CH32V00x_CONF_H */ - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/08/08 + * Description : Library configuration file. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V00x_CONF_H +#define __CH32V00x_CONF_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + + +#endif /* __CH32V00x_CONF_H */ + + + + + diff --git a/system/CH32V00x/USER/ch32v00x_it.c b/system/CH32V00x/USER/ch32v00x_it.c index aa21166..a64a993 100644 --- a/system/CH32V00x/USER/ch32v00x_it.c +++ b/system/CH32V00x/USER/ch32v00x_it.c @@ -1,42 +1,45 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00x_it.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : Main Interrupt Service Routines. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include - -void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); - -/********************************************************************* - * @fn NMI_Handler - * - * @brief This function handles NMI exception. - * - * @return none - */ -void NMI_Handler(void) -{ -} - -/********************************************************************* - * @fn HardFault_Handler - * - * @brief This function handles Hard Fault exception. - * - * @return none - */ -void HardFault_Handler(void) -{ - while (1) - { - } -} - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_it.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/25 + * Description : Main Interrupt Service Routines. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ + while (1) + { + } +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + while (1) + { + } +} + + diff --git a/system/CH32V00x/USER/system_ch32v00x.c b/system/CH32V00x/USER/system_ch32v00x.c index 112159f..de12d32 100644 --- a/system/CH32V00x/USER/system_ch32v00x.c +++ b/system/CH32V00x/USER/system_ch32v00x.c @@ -1,443 +1,453 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : system_ch32v00x.c - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : CH32V00x Device Peripheral Access Layer System Source File. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include - -/* -* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after -* reset the HSI is used as SYSCLK source). -* If none of the define below is enabled, the HSI is used as System clock source. -*/ - -//#define SYSCLK_FREQ_8MHz_HSI 8000000 -// #define SYSCLK_FREQ_24MHZ_HSI HSI_VALUE -// #define SYSCLK_FREQ_48MHZ_HSI 48000000 -//#define SYSCLK_FREQ_8MHz_HSE 8000000 -// #define SYSCLK_FREQ_24MHz_HSE HSE_VALUE -// #define SYSCLK_FREQ_48MHz_HSE 48000000 - -/* Clock Definitions */ -#ifdef SYSCLK_FREQ_8MHz_HSI - uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz_HSI - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz_HSI - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_8MHz_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ -#else - uint32_t SystemCoreClock = HSI_VALUE; -#endif - -__I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; - - -/* system_private_function_proto_types */ -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_8MHz_HSI - static void SetSysClockTo_8MHz_HSI(void); -#elif defined SYSCLK_FREQ_24MHz_HSI - static void SetSysClockTo_24MHz_HSI(void); -#elif defined SYSCLK_FREQ_48MHz_HSI - static void SetSysClockTo_48MHz_HSI(void); -#elif defined SYSCLK_FREQ_8MHz_HSE - static void SetSysClockTo_8MHz_HSE(void); -#elif defined SYSCLK_FREQ_24MHz_HSE - static void SetSysClockTo_24MHz_HSE(void); -#elif defined SYSCLK_FREQ_48MHz_HSE - static void SetSysClockTo_48MHz_HSE(void); -#endif - - -/********************************************************************* - * @fn SystemInit - * - * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, - * the PLL and update the SystemCoreClock variable. - * - * @return none - */ -void SystemInit (void) -{ - RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xFCFF0000; - RCC->CTLR &= (uint32_t)0xFEF6FFFF; - RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFFFEFFFF; - RCC->INTR = 0x009F0000; - - SetSysClock(); -} - - -/********************************************************************* - * @fn SystemCoreClockUpdate - * - * @brief Update SystemCoreClock variable according to Clock Register Values. - * - * @return none - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllsource = 0; - - tmp = RCC->CFGR0 & RCC_SWS; - - switch (tmp) - { - case 0x00: - SystemCoreClock = HSI_VALUE; - break; - case 0x04: - SystemCoreClock = HSE_VALUE; - break; - case 0x08: - pllsource = RCC->CFGR0 & RCC_PLLSRC; - if (pllsource == 0x00) - { - SystemCoreClock = HSI_VALUE * 2; - } - else - { - SystemCoreClock = HSE_VALUE * 2; - } - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - - tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; - - if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8) - { - SystemCoreClock /= tmp; - } - else - { - SystemCoreClock >>= tmp; - } -} - - -/********************************************************************* - * @fn SetSysClock - * - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_8MHz_HSI - SetSysClockTo_8MHz_HSI(); -#elif defined SYSCLK_FREQ_24MHz_HSI - SetSysClockTo_24MHz_HSI(); -#elif defined SYSCLK_FREQ_48MHz_HSI - SetSysClockTo_48MHz_HSI(); -#elif defined SYSCLK_FREQ_8MHz_HSE - SetSysClockTo_8MHz_HSE(); -#elif defined SYSCLK_FREQ_24MHz_HSE - SetSysClockTo_24MHz_HSE(); -#elif defined SYSCLK_FREQ_48MHz_HSE - SetSysClockTo_48MHz_HSE(); -#endif - - /* If none of the define above is enabled, the HSI is used as System clock. - * source (default after reset) - */ -} - - -#ifdef SYSCLK_FREQ_8MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo_8MHz_HSI - * - * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo_8MHz_HSI(void) -{ - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; - - /* HCLK = SYSCLK = APB1 */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; -} - -#elif defined SYSCLK_FREQ_24MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo_24MHZ_HSI - * - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo_24MHz_HSI(void) -{ - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; - - /* HCLK = SYSCLK = APB1 */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; -} - - -#elif defined SYSCLK_FREQ_48MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo_48MHZ_HSI - * - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo_48MHz_HSI(void) -{ - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; - - /* HCLK = SYSCLK = APB1 */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - - /* PLL configuration: PLLCLK = HSI * 2 = 48 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Mul2); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - -#elif defined SYSCLK_FREQ_8MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo_8MHz_HSE - * - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo_8MHz_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Close PA0-PA1 GPIO function */ - RCC->APB2PCENR |= RCC_AFIOEN; - AFIO->PCFR1 |= (1<<15); - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - RCC->APB2PCENR |= RCC_AFIOEN; - AFIO->PCFR1 |= (1<<15); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; - - /* HCLK = SYSCLK = APB1 */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; - - /* Select HSE as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_24MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo_24MHz_HSE - * - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo_24MHz_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Close PA0-PA1 GPIO function */ - RCC->APB2PCENR |= RCC_AFIOEN; - AFIO->PCFR1 |= (1<<15); - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - RCC->APB2PCENR |= RCC_AFIOEN; - AFIO->PCFR1 |= (1<<15); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; - - /* HCLK = SYSCLK = APB1 */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_48MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo_48MHz_HSE - * - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo_48MHz_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Close PA0-PA1 GPIO function */ - RCC->APB2PCENR |= RCC_AFIOEN; - AFIO->PCFR1 |= (1<<15); - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; - - /* HCLK = SYSCLK = APB1 */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - - /* PLL configuration: PLLCLK = HSE * 2 = 48 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE_Mul2); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} -#endif - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v00x.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : CH32V00x Device Peripheral Access Layer System Source File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ + +//#define SYSCLK_FREQ_8MHz_HSI 8000000 +//#define SYSCLK_FREQ_24MHz_HSI HSI_VALUE +//#define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_8MHz_HSE 8000000 +//#define SYSCLK_FREQ_24MHz_HSE HSE_VALUE +// #define SYSCLK_FREQ_48MHz_HSE 48000000 + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_8MHz_HSI + uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz_HSI + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSI + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_8MHz_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#else + uint32_t SystemCoreClock = HSI_VALUE; +#endif + +__I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_8MHz_HSI + static void SetSysClockTo_8MHz_HSI(void); +#elif defined SYSCLK_FREQ_24MHz_HSI + static void SetSysClockTo_24MHz_HSI(void); +#elif defined SYSCLK_FREQ_48MHz_HSI + static void SetSysClockTo_48MHz_HSI(void); +#elif defined SYSCLK_FREQ_8MHz_HSE + static void SetSysClockTo_8MHz_HSE(void); +#elif defined SYSCLK_FREQ_24MHz_HSE + static void SetSysClockTo_24MHz_HSE(void); +#elif defined SYSCLK_FREQ_48MHz_HSE + static void SetSysClockTo_48MHz_HSE(void); +#endif + + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFFFEFFFF; + RCC->INTR = 0x009F0000; + + RCC_AdjustHSICalibrationValue(0x10); + + SetSysClock(); +} + + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllsource = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllsource = RCC->CFGR0 & RCC_PLLSRC; + if (pllsource == 0x00) + { + SystemCoreClock = HSI_VALUE * 2; + } + else + { + SystemCoreClock = HSE_VALUE * 2; + } + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + + if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8) + { + SystemCoreClock /= tmp; + } + else + { + SystemCoreClock >>= tmp; + } +} + + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ +RCC->APB2PCENR |= RCC_APB2Periph_GPIOD; +GPIOD->CFGLR&=(~0xF0); +GPIOD->CFGLR|=0x80; +GPIOD->BSHR =0x2; +//GPIO_IPD_Unused(); +#ifdef SYSCLK_FREQ_8MHz_HSI + SetSysClockTo_8MHz_HSI(); +#elif defined SYSCLK_FREQ_24MHz_HSI + SetSysClockTo_24MHz_HSI(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo_48MHz_HSI(); +#elif defined SYSCLK_FREQ_8MHz_HSE + SetSysClockTo_8MHz_HSE(); +#elif defined SYSCLK_FREQ_24MHz_HSE + SetSysClockTo_24MHz_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo_48MHz_HSE(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock. + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_8MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo_8MHz_HSI + * + * @brief Sets HSI as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_8MHz_HSI(void) +{ + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; +} + +#elif defined SYSCLK_FREQ_24MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo_24MHz_HSI + * + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_24MHz_HSI(void) +{ + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; +} + + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo_48MHz_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_48MHz_HSI(void) +{ + uint8_t tmp = 0; + + tmp = *( uint8_t * )CFG0_PLL_TRIM; + + if(tmp != 0xFF) + { + RCC_AdjustHSICalibrationValue((tmp & 0x1F)); + } + + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + + /* PLL configuration: PLLCLK = HSI * 2 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Mul2); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_8MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo_8MHz_HSE + * + * @brief Sets System clock frequency to 8MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_8MHz_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Close PA0-PA1 GPIO function */ + RCC->APB2PCENR |= RCC_AFIOEN; + AFIO->PCFR1 |= (1<<15); + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_24MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo_24MHz_HSE + * + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_24MHz_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Close PA0-PA1 GPIO function */ + RCC->APB2PCENR |= RCC_AFIOEN; + AFIO->PCFR1 |= (1<<15); + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo_48MHz_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_48MHz_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Close PA0-PA1 GPIO function */ + RCC->APB2PCENR |= RCC_AFIOEN; + AFIO->PCFR1 |= (1<<15); + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + + /* PLL configuration: PLLCLK = HSE * 2 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE_Mul2); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} +#endif + + + + diff --git a/system/CH32V00x/USER/system_ch32v00x.h b/system/CH32V00x/USER/system_ch32v00x.h index 5f681a9..97433b3 100644 --- a/system/CH32V00x/USER/system_ch32v00x.h +++ b/system/CH32V00x/USER/system_ch32v00x.h @@ -1,32 +1,32 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : system_ch32v00x.h - * Author : WCH - * Version : V1.0.0 - * Date : 2022/08/08 - * Description : CH32V00x Device Peripheral Access Layer System Header File. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __SYSTEM_CH32V00x_H -#define __SYSTEM_CH32V00x_H - -#ifdef __cplusplus - extern "C" { -#endif - -extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ - -/* System_Exported_Functions */ -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V00x_SYSTEM_H */ - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v00x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : CH32V00x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_CH32V00x_H +#define __SYSTEM_CH32V00x_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00x_SYSTEM_H */ + + + diff --git a/system/CH32V10x/SRC/Core/core_riscv.c b/system/CH32V10x/SRC/Core/core_riscv.c index 5f8aeb3..89aa0bf 100644 --- a/system/CH32V10x/SRC/Core/core_riscv.c +++ b/system/CH32V10x/SRC/Core/core_riscv.c @@ -1,303 +1,303 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : core_riscv.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : RISC-V Core Peripheral Access Layer Source File -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include - -/* define compiler specific symbols */ -#if defined(__CC_ARM) - #define __ASM __asm /* asm keyword for ARM Compiler */ - #define __INLINE __inline /* inline keyword for ARM Compiler */ - -#elif defined(__ICCARM__) - #define __ASM __asm /* asm keyword for IAR Compiler */ - #define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined(__GNUC__) - #define __ASM __asm /* asm keyword for GNU Compiler */ - #define __INLINE inline /* inline keyword for GNU Compiler */ - -#elif defined(__TASKING__) - #define __ASM __asm /* asm keyword for TASKING Compiler */ - #define __INLINE inline /* inline keyword for TASKING Compiler */ - -#endif - -/********************************************************************* - * @fn __get_MSTATUS - * - * @brief Return the Machine Status Register - * - * @return mstatus value - */ -uint32_t __get_MSTATUS(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mstatus": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MSTATUS - * - * @brief Set the Machine Status Register - * - * @param value - set mstatus value - * - * @return none - */ -void __set_MSTATUS(uint32_t value) -{ - __ASM volatile("csrw mstatus, %0" : : "r"(value)); -} - -/********************************************************************* - * @fn __get_MISA - * - * @brief Return the Machine ISA Register - * - * @return misa value - */ -uint32_t __get_MISA(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""misa" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MISA - * - * @brief Set the Machine ISA Register - * - * @param value - set misa value - * - * @return none - */ -void __set_MISA(uint32_t value) -{ - __ASM volatile("csrw misa, %0" : : "r"(value)); -} - -/********************************************************************* - * @fn __get_MTVEC - * - * @brief Return the Machine Trap-Vector Base-Address Register - * - * @return mtvec value - */ -uint32_t __get_MTVEC(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mtvec": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MTVEC - * - * @brief Set the Machine Trap-Vector Base-Address Register - * - * @param value - set mtvec value - * - * @return none - */ -void __set_MTVEC(uint32_t value) -{ - __ASM volatile("csrw mtvec, %0":: "r"(value)); -} - -/********************************************************************* - * @fn __get_MSCRATCH - * - * @brief Return the Machine Seratch Register - * - * @return mscratch value - */ -uint32_t __get_MSCRATCH(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mscratch" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MSCRATCH - * - * @brief Set the Machine Seratch Register - * - * @param value - set mscratch value - * - * @return none - */ -void __set_MSCRATCH(uint32_t value) -{ - __ASM volatile("csrw mscratch, %0" : : "r"(value)); -} - -/********************************************************************* - * @fn __get_MEPC - * - * @brief Return the Machine Exception Program Register - * - * @return mepc value - */ -uint32_t __get_MEPC(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mepc" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Exception Program Register - * - * @return mepc value - */ -void __set_MEPC(uint32_t value) -{ - __ASM volatile("csrw mepc, %0" : : "r"(value)); -} - -/********************************************************************* - * @fn __get_MCAUSE - * - * @brief Return the Machine Cause Register - * - * @return mcause value - */ -uint32_t __get_MCAUSE(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mcause": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Cause Register - * - * @return mcause value - */ -void __set_MCAUSE(uint32_t value) -{ - __ASM volatile("csrw mcause, %0":: "r"(value)); -} - -/********************************************************************* - * @fn __get_MTVAL - * - * @brief Return the Machine Trap Value Register - * - * @return mtval value - */ -uint32_t __get_MTVAL(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mtval" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MTVAL - * - * @brief Set the Machine Trap Value Register - * - * @return mtval value - */ -void __set_MTVAL(uint32_t value) -{ - __ASM volatile("csrw mtval, %0":: "r"(value)); -} - -/********************************************************************* - * @fn __get_MVENDORID - * - * @brief Return Vendor ID Register - * - * @return mvendorid value - */ -uint32_t __get_MVENDORID(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""mvendorid": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __get_MARCHID - * - * @brief Return Machine Architecture ID Register - * - * @return marchid value - */ -uint32_t __get_MARCHID(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""marchid": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __get_MIMPID - * - * @brief Return Machine Implementation ID Register - * - * @return mimpid value - */ -uint32_t __get_MIMPID(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""mimpid": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __get_MHARTID - * - * @brief Return Hart ID Register - * - * @return mhartid value - */ -uint32_t __get_MHARTID(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""mhartid": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __get_SP - * - * @brief Return SP Register - * - * @return SP value - */ -uint32_t __get_SP(void) -{ - uint32_t result; - - __ASM volatile("mv %0,""sp": "=r"(result):); - return (result); -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.c + * Author : WCH + * Version : V1.0.1 + * Date : 2023/11/11 + * Description : RISC-V V3 Core Peripheral Access Layer Source File for CH32V10x +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined(__CC_ARM) + #define __ASM __asm /* asm keyword for ARM Compiler */ + #define __INLINE __inline /* inline keyword for ARM Compiler */ + +#elif defined(__ICCARM__) + #define __ASM __asm /* asm keyword for IAR Compiler */ + #define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined(__GNUC__) + #define __ASM __asm /* asm keyword for GNU Compiler */ + #define __INLINE inline /* inline keyword for GNU Compiler */ + +#elif defined(__TASKING__) + #define __ASM __asm /* asm keyword for TASKING Compiler */ + #define __INLINE inline /* inline keyword for TASKING Compiler */ + +#endif + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mstatus": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile("csrw mstatus, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""misa" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile("csrw misa, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mtvec": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile("csrw mtvec, %0":: "r"(value)); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mscratch" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile("csrw mscratch, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mepc" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile("csrw mepc, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mcause": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile("csrw mcause, %0":: "r"(value)); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mtval" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile("csrw mtval, %0":: "r"(value)); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mvendorid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""marchid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mimpid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mhartid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile("mv %0,""sp": "=r"(result):); + return (result); +} diff --git a/system/CH32V10x/SRC/Core/core_riscv.h b/system/CH32V10x/SRC/Core/core_riscv.h index e3b7fac..a9fdae4 100644 --- a/system/CH32V10x/SRC/Core/core_riscv.h +++ b/system/CH32V10x/SRC/Core/core_riscv.h @@ -1,598 +1,629 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : core_riscv.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : RISC-V Core Peripheral Access Layer Header File for CH32V20x -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CORE_RISCV_H__ -#define __CORE_RISCV_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -/* IO definitions */ -#ifdef __cplusplus - #define __I volatile /* defines 'read only' permissions */ -#else - #define __I volatile const /* defines 'read only' permissions */ -#endif -#define __O volatile /* defines 'write only' permissions */ -#define __IO volatile /* defines 'read / write' permissions */ - -/* Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef __I uint32_t vuc32; /* Read Only */ -typedef __I uint16_t vuc16; /* Read Only */ -typedef __I uint8_t vuc8; /* Read Only */ - -typedef const uint32_t uc32; /* Read Only */ -typedef const uint16_t uc16; /* Read Only */ -typedef const uint8_t uc8; /* Read Only */ - -typedef __I int32_t vsc32; /* Read Only */ -typedef __I int16_t vsc16; /* Read Only */ -typedef __I int8_t vsc8; /* Read Only */ - -typedef const int32_t sc32; /* Read Only */ -typedef const int16_t sc16; /* Read Only */ -typedef const int8_t sc8; /* Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -#define RV_STATIC_INLINE static inline - -/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ -typedef struct{ - __I uint32_t ISR[8]; - __I uint32_t IPR[8]; - __IO uint32_t ITHRESDR; - __IO uint32_t VTFBADDRR; - __IO uint32_t CFGR; - __I uint32_t GISR; - uint8_t RESERVED0[0x10]; - __IO uint32_t VTFADDRR[4]; - uint8_t RESERVED1[0x90]; - __O uint32_t IENR[8]; - uint8_t RESERVED2[0x60]; - __O uint32_t IRER[8]; - uint8_t RESERVED3[0x60]; - __O uint32_t IPSR[8]; - uint8_t RESERVED4[0x60]; - __O uint32_t IPRR[8]; - uint8_t RESERVED5[0x60]; - __IO uint32_t IACTR[8]; - uint8_t RESERVED6[0xE0]; - __IO uint8_t IPRIOR[256]; - uint8_t RESERVED7[0x810]; - __IO uint32_t SCTLR; -}PFIC_Type; - -#define FIBADDRR VTFBADDRR -#define FIOFADDRR VTFADDRR - - -/* memory mapped structure for SysTick */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint8_t CNTL0; - __IO uint8_t CNTL1; - __IO uint8_t CNTL2; - __IO uint8_t CNTL3; - __IO uint8_t CNTH0; - __IO uint8_t CNTH1; - __IO uint8_t CNTH2; - __IO uint8_t CNTH3; - __IO uint8_t CMPLR0; - __IO uint8_t CMPLR1; - __IO uint8_t CMPLR2; - __IO uint8_t CMPLR3; - __IO uint8_t CMPHR0; - __IO uint8_t CMPHR1; - __IO uint8_t CMPHR2; - __IO uint8_t CMPHR3; -}SysTick_Type; - - -#define PFIC ((PFIC_Type *) 0xE000E000 ) -#define NVIC PFIC -#define NVIC_KEY1 ((uint32_t)0xFA050000) -#define NVIC_KEY2 ((uint32_t)0xBCAF0000) -#define NVIC_KEY3 ((uint32_t)0xBEEF0000) - -#define SysTick ((SysTick_Type *) 0xE000F000) - - -/********************************************************************* - * @fn __NOP - * - * @brief nop - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() -{ - __asm volatile ("nop"); -} - -/********************************************************************* - * @fn NVIC_EnableIRQ - * - * @brief Enable Interrupt - * - * @param IRQn: Interrupt Numbers - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn){ - NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_DisableIRQ - * - * @brief Disable Interrupt - * - * @param IRQn: Interrupt Numbers - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - uint32_t t; - - t = NVIC->ITHRESDR; - NVIC->ITHRESDR = 0x10; - NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); - NVIC->ITHRESDR = t; -} - -/********************************************************************* - * @fn NVIC_GetStatusIRQ - * - * @brief Get Interrupt Enable State - * - * @param IRQn: Interrupt Numbers - * - * @return 1 - Interrupt Enable - * 0 - Interrupt Disable - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_GetPendingIRQ - * - * @brief Get Interrupt Pending State - * - * @param IRQn: Interrupt Numbers - * - * @return 1 - Interrupt Pending Enable - * 0 - Interrupt Pending Disable - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_SetPendingIRQ - * - * @brief Set Interrupt Pending - * - * @param IRQn: Interrupt Numbers - * - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_ClearPendingIRQ - * - * @brief Clear Interrupt Pending - * - * @param IRQn: Interrupt Numbers - * - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_GetActive - * - * @brief Get Interrupt Active State - * - * @param IRQn: Interrupt Numbers - * - * @return 1 - Interrupt Active - * 0 - Interrupt No Active - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_SetPriority - * - * @brief Set Interrupt Priority - * - * @param IRQn - Interrupt Numbers - * priority -bit[7] - Pre-emption Priority - * bit[6:4] - Subpriority - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) -{ - NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; -} - -/********************************************************************* - * @fn __WFI - * - * @brief Wait for Interrupt - * - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) -{ - NVIC->SCTLR &= ~(1<<3); // wfi - asm volatile ("wfi"); -} - -/********************************************************************* - * @fn _SEV - * - * @brief Set Event - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) -{ - - NVIC->SCTLR |= (1<<3)|(1<<5); - -} - -/********************************************************************* - * @fn _WFE - * - * @brief Wait for Events - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) -{ - NVIC->SCTLR |= (1<<3); - asm volatile ("wfi"); -} - -/********************************************************************* - * @fn __WFE - * - * @brief Wait for Events - * - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) -{ - _SEV(); - _WFE(); - _WFE(); -} - -/********************************************************************* - * @fn NVIC_SetFastIRQ - * - * @brief Set VTF Interrupt - * - * @param add - VTF interrupt service function base address. - * IRQn -Interrupt Numbers - * num - VTF Interrupt Numbers - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetFastIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num) -{ - if(num > 3) return ; - NVIC->VTFBADDRR = addr; - NVIC->VTFADDRR[num] = ((uint32_t)IRQn<<24)|(addr&0xfffff); -} - -/********************************************************************* - * @fn NVIC_SystemReset - * - * @brief Initiate a system reset request - * - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) -{ - NVIC->CFGR = NVIC_KEY3|(1<<7); -} - -/********************************************************************* - * @fn NVIC_HaltPushCfg - * - * @brief Enable Hardware Stack - * - * @param NewState - DISABLE or ENABLE - - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_HaltPushCfg(FunctionalState NewState) -{ - if (NewState != DISABLE) - { - NVIC->CFGR = NVIC_KEY1; - } - else{ - NVIC->CFGR = NVIC_KEY1|(1<<0); - } -} - -/********************************************************************* - * @fn NVIC_INTNestCfg - * - * @brief Enable Interrupt Nesting - * - * @param NewState - DISABLE or ENABLE - * - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_INTNestCfg(FunctionalState NewState) -{ - if (NewState != DISABLE) - { - NVIC->CFGR = NVIC_KEY1; - } - else - { - NVIC->CFGR = NVIC_KEY1|(1<<1); - } -} - -/********************************************************************* - * @fn __AMOADD_W - * - * @brief Atomic Add with 32bit value - * Atomically ADD 32bit value with value in memory using amoadd.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be ADDed - * - * @return return memory value + add value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amoadd.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOAND_W - * - * @brief Atomic And with 32bit value - * Atomically AND 32bit value with value in memory using amoand.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be ANDed - * - * @return return memory value & and value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amoand.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOMAX_W - * - * @brief Atomic signed MAX with 32bit value - * Atomically signed max compare 32bit value with value in memory using amomax.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared - * - * @return return the bigger value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amomax.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOMAXU_W - * - * @brief Atomic unsigned MAX with 32bit value - * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared - * - * @return return the bigger value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) -{ - uint32_t result; - - __asm volatile ("amomaxu.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOMIN_W - * - * @brief Atomic signed MIN with 32bit value - * Atomically signed min compare 32bit value with value in memory using amomin.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared - * - * @return return the smaller value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amomin.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOMINU_W - * - * @brief Atomic unsigned MIN with 32bit value - * Atomically unsigned min compare 32bit value with value in memory using amominu.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared - * - * @return return the smaller value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) -{ - uint32_t result; - - __asm volatile ("amominu.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOOR_W - * - * @brief Atomic OR with 32bit value - * Atomically OR 32bit value with value in memory using amoor.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be ORed - * - * @return return memory value | and value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amoor.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOSWAP_W - * - * @brief Atomically swap new 32bit value into memory using amoswap.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * newval - New value to be stored into the address - * - * @return return the original value in memory - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) -{ - uint32_t result; - - __asm volatile ("amoswap.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); - return result; -} - -/********************************************************************* - * @fn __AMOXOR_W - * - * @brief Atomic XOR with 32bit value - * Atomically XOR 32bit value with value in memory using amoxor.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be XORed - * - * @return return memory value ^ and value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amoxor.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/* Core_Exported_Functions */ -extern uint32_t __get_MSTATUS(void); -extern void __set_MSTATUS(uint32_t value); -extern uint32_t __get_MISA(void); -extern void __set_MISA(uint32_t value); -extern uint32_t __get_MTVEC(void); -extern void __set_MTVEC(uint32_t value); -extern uint32_t __get_MSCRATCH(void); -extern void __set_MSCRATCH(uint32_t value); -extern uint32_t __get_MEPC(void); -extern void __set_MEPC(uint32_t value); -extern uint32_t __get_MCAUSE(void); -extern void __set_MCAUSE(uint32_t value); -extern uint32_t __get_MTVAL(void); -extern void __set_MTVAL(uint32_t value); -extern uint32_t __get_MVENDORID(void); -extern uint32_t __get_MARCHID(void); -extern uint32_t __get_MIMPID(void); -extern uint32_t __get_MHARTID(void); -extern uint32_t __get_SP(void); - - -#ifdef __cplusplus -} -#endif - -#endif/* __CORE_RISCV_H__ */ - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.h + * Author : WCH + * Version : V1.0.1 + * Date : 2023/11/11 + * Description : RISC-V V3 Core Peripheral Access Layer Header File for CH32V10x +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t VTFBADDRR; + __IO uint32_t CFGR; + __I uint32_t GISR; + uint8_t RESERVED0[0x10]; + __IO uint32_t VTFADDRR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +#define FIBADDRR VTFBADDRR +#define FIOFADDRR VTFADDRR + + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint8_t CNTL0; + __IO uint8_t CNTL1; + __IO uint8_t CNTL2; + __IO uint8_t CNTL3; + __IO uint8_t CNTH0; + __IO uint8_t CNTH1; + __IO uint8_t CNTH2; + __IO uint8_t CNTH3; + __IO uint8_t CMPLR0; + __IO uint8_t CMPLR1; + __IO uint8_t CMPLR2; + __IO uint8_t CMPLR3; + __IO uint8_t CMPHR0; + __IO uint8_t CMPHR1; + __IO uint8_t CMPHR2; + __IO uint8_t CMPHR3; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000 ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + +#define SysTick ((SysTick_Type *) 0xE000F000) + +/********************************************************************* + * @fn __enable_irq + * This function is only used for Machine mode. + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrs mstatus, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __disable_irq + * This function is only used for Machine mode. + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrc mstatus, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + uint32_t t; + + t = NVIC->ITHRESDR; + NVIC->ITHRESDR = 0x10; + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ITHRESDR = t; +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Enable + * 0 - Interrupt Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * interrupt nesting enable(PFIC->CFGR bit1 = 0) + * priority - bit[7] - Preemption Priority + * bit[6:4] - Sub priority + * bit[3:0] - Reserve + * interrupt nesting disable(PFIC->CFGR bit1 = 1) + * priority - bit[7:4] - Sub priority + * bit[3:0] - Reserve + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + NVIC->SCTLR |= (1<<3)|(1<<5); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + NVIC->SCTLR |= (1<<3); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn NVIC_SetFastIRQ + * + * @brief Set VTF Interrupt + * + * @param add - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetFastIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num) +{ + if(num > 3) return ; + NVIC->VTFBADDRR = addr; + NVIC->VTFADDRR[num] = ((uint32_t)IRQn<<24)|(addr&0xfffff); +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + +/********************************************************************* + * @fn NVIC_HaltPushCfg + * + * @brief Enable Hardware Stack + * + * @param NewState - DISABLE or ENABLE + + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_HaltPushCfg(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + NVIC->CFGR = NVIC_KEY1; + } + else + { + NVIC->CFGR = NVIC_KEY1|(1<<0); + } +} + +/********************************************************************* + * @fn NVIC_INTNestCfg + * + * @brief Enable Interrupt Nesting + * + * @param NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_INTNestCfg(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + NVIC->CFGR = NVIC_KEY1; + } + else + { + NVIC->CFGR = NVIC_KEY1|(1<<1); + } +} + +/********************************************************************* + * @fn __AMOADD_W + * + * @brief Atomic Add with 32bit value + * Atomically ADD 32bit value with value in memory using amoadd.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ADDed + * + * @return return memory value + add value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoadd.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOAND_W + * + * @brief Atomic And with 32bit value + * Atomically AND 32bit value with value in memory using amoand.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ANDed + * + * @return return memory value & and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoand.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAX_W + * + * @brief Atomic signed MAX with 32bit value + * Atomically signed max compare 32bit value with value in memory using amomax.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomax.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAXU_W + * + * @brief Atomic unsigned MAX with 32bit value + * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amomaxu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMIN_W + * + * @brief Atomic signed MIN with 32bit value + * Atomically signed min compare 32bit value with value in memory using amomin.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomin.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMINU_W + * + * @brief Atomic unsigned MIN with 32bit value + * Atomically unsigned min compare 32bit value with value in memory using amominu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amominu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOOR_W + * + * @brief Atomic OR with 32bit value + * Atomically OR 32bit value with value in memory using amoor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ORed + * + * @return return memory value | and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOSWAP_W + * + * @brief Atomically swap new 32bit value into memory using amoswap.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * newval - New value to be stored into the address + * + * @return return the original value in memory + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) +{ + uint32_t result; + + __asm volatile ("amoswap.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); + return result; +} + +/********************************************************************* + * @fn __AMOXOR_W + * + * @brief Atomic XOR with 32bit value + * Atomically XOR 32bit value with value in memory using amoxor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be XORed + * + * @return return memory value ^ and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoxor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/* Core_Exported_Functions */ +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MTVAL(void); +extern void __set_MTVAL(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + + +#ifdef __cplusplus +} +#endif + +#endif/* __CORE_RISCV_H__ */ + + + + + diff --git a/system/CH32V10x/SRC/Debug/debug.c b/system/CH32V10x/SRC/Debug/debug.c index f73761e..ff542cc 100644 --- a/system/CH32V10x/SRC/Debug/debug.c +++ b/system/CH32V10x/SRC/Debug/debug.c @@ -1,202 +1,257 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : debug.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for UART - * Printf , Delay functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "debug.h" - -static uint8_t p_us = 0; -static uint16_t p_ms = 0; - -/********************************************************************* - * @fn Delay_Init - * - * @brief Initializes Delay Funcation. - * - * @return none - */ -void Delay_Init(void) -{ - p_us = SystemCoreClock / 8000000; - p_ms = (uint16_t)p_us * 1000; -} - -/********************************************************************* - * @fn Delay_Us - * - * @brief Microsecond Delay Time. - * - * @param n - Microsecond number. - * - * @return None - */ -void Delay_Us(uint32_t n) -{ - uint32_t i; - - SysTick->CTLR = 0; - i = (uint32_t)n * p_us; - - SysTick->CNTL0 = 0; - SysTick->CNTL1 = 0; - SysTick->CNTL2 = 0; - SysTick->CNTL3 = 0; - SysTick->CTLR = 1; - - while((*(__IO uint32_t *)0xE000F004) <= i) - ; -} - -/********************************************************************* - * @fn Delay_Ms - * - * @brief Millisecond Delay Time. - * - * @param n - Millisecond number. - * - * @return None - */ -void Delay_Ms(uint32_t n) -{ - uint32_t i; - - SysTick->CTLR = 0; - i = (uint32_t)n * p_ms; - - SysTick->CNTL0 = 0; - SysTick->CNTL1 = 0; - SysTick->CNTL2 = 0; - SysTick->CNTL3 = 0; - SysTick->CTLR = 1; - - while((*(__IO uint32_t *)0xE000F004) <= i) ; -} - -/********************************************************************* - * @fn USART_Printf_Init - * - * @brief Initializes the USARTx peripheral. - * - * @param baudrate - USART communication baud rate. - * - * @return None - */ -void USART_Printf_Init(uint32_t baudrate) -{ - GPIO_InitTypeDef GPIO_InitStructure; - USART_InitTypeDef USART_InitStructure; - -#if(DEBUG == DEBUG_UART1) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - -#elif(DEBUG == DEBUG_UART2) - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - -#elif(DEBUG == DEBUG_UART3) - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOB, &GPIO_InitStructure); - -#endif - - USART_InitStructure.USART_BaudRate = baudrate; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_No; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Tx; - -#if(DEBUG == DEBUG_UART1) - USART_Init(USART1, &USART_InitStructure); - USART_Cmd(USART1, ENABLE); - -#elif(DEBUG == DEBUG_UART2) - USART_Init(USART2, &USART_InitStructure); - USART_Cmd(USART2, ENABLE); - -#elif(DEBUG == DEBUG_UART3) - USART_Init(USART3, &USART_InitStructure); - USART_Cmd(USART3, ENABLE); - -#endif -} - -/********************************************************************* - * @fn _write - * - * @brief Support Printf Function - * - * @param *buf - UART send Data. - * size - Data length. - * - * @return size - Data length - */ -#if 0 -__attribute__((used)) -int _write(int fd, char *buf, int size) -{ - int i; - - for(i = 0; i < size; i++){ -#if(DEBUG == DEBUG_UART1) - while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); - USART_SendData(USART1, *buf++); -#elif(DEBUG == DEBUG_UART2) - while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); - USART_SendData(USART2, *buf++); -#elif(DEBUG == DEBUG_UART3) - while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); - USART_SendData(USART3, *buf++); -#endif - } - - return size; -} -#endif - -/********************************************************************* - * @fn _sbrk - * - * @brief Change the spatial position of data segment. - * - * @return size: Data length - */ -__attribute__((used)) -void *_sbrk(ptrdiff_t incr) -{ - extern char _end[]; - extern char _heap_end[]; - static char *curbrk = _end; - - if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) - return NULL - 1; - - curbrk += incr; - return curbrk - incr; -} - -void _fini() {} -void _init() {} - +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "debug.h" + +static uint8_t p_us = 0; +static uint16_t p_ms = 0; + +#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE0000380) +#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE0000384) + +/********************************************************************* + * @fn Delay_Init + * + * @brief Initializes Delay Funcation. + * + * @return none + */ +void Delay_Init(void) +{ + p_us = SystemCoreClock / 8000000; + p_ms = (uint16_t)p_us * 1000; +} + +/********************************************************************* + * @fn Delay_Us + * + * @brief Microsecond Delay Time. + * + * @param n - Microsecond number. + * + * @return None + */ +void Delay_Us(uint32_t n) +{ + uint32_t i; + + SysTick->CTLR = 0; + i = (uint32_t)n * p_us; + + SysTick->CNTL0 = 0; + SysTick->CNTL1 = 0; + SysTick->CNTL2 = 0; + SysTick->CNTL3 = 0; + SysTick->CTLR = 1; + + while((*(__IO uint32_t *)0xE000F004) <= i) + ; +} + +/********************************************************************* + * @fn Delay_Ms + * + * @brief Millisecond Delay Time. + * + * @param n - Millisecond number. + * + * @return None + */ +void Delay_Ms(uint32_t n) +{ + uint32_t i; + + SysTick->CTLR = 0; + i = (uint32_t)n * p_ms; + + SysTick->CNTL0 = 0; + SysTick->CNTL1 = 0; + SysTick->CNTL2 = 0; + SysTick->CNTL3 = 0; + SysTick->CTLR = 1; + + while((*(__IO uint32_t *)0xE000F004) <= i) ; +} + +/********************************************************************* + * @fn USART_Printf_Init + * + * @brief Initializes the USARTx peripheral. + * + * @param baudrate - USART communication baud rate. + * + * @return None + */ +void USART_Printf_Init(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + +#if(DEBUG == DEBUG_UART1) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART2) + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART3) + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + +#endif + + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx; + +#if(DEBUG == DEBUG_UART1) + USART_Init(USART1, &USART_InitStructure); + USART_Cmd(USART1, ENABLE); + +#elif(DEBUG == DEBUG_UART2) + USART_Init(USART2, &USART_InitStructure); + USART_Cmd(USART2, ENABLE); + +#elif(DEBUG == DEBUG_UART3) + USART_Init(USART3, &USART_InitStructure); + USART_Cmd(USART3, ENABLE); + +#endif +} + +/********************************************************************* + * @fn SDI_Printf_Enable + * + * @brief Initializes the SDI printf Function. + * + * @param None + * + * @return None + */ +void SDI_Printf_Enable(void) +{ + *(DEBUG_DATA0_ADDRESS) = 0; + Delay_Init(); + Delay_Ms(1); +} + +/********************************************************************* + * @fn _write + * + * @brief Support Printf Function + * + * @param *buf - UART send Data. + * size - Data length. + * + * @return size - Data length + */ +#if 0 +__attribute__((used)) +int _write(int fd, char *buf, int size) +{ + int i = 0; + +#if (SDI_PRINT == SDI_PR_OPEN) + int writeSize = size; + + do + { + + /** + * data0 data1 8 bytes + * data0 The lowest byte storage length, the maximum is 7 + * + */ + + while( (*(DEBUG_DATA0_ADDRESS) != 0u)) + { + + } + + if(writeSize>7) + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + i += 7; + writeSize -= 7; + } + else + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + writeSize = 0; + } + + } while (writeSize); + +#else + for(i = 0; i < size; i++){ +#if(DEBUG == DEBUG_UART1) + while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); + USART_SendData(USART1, *buf++); +#elif(DEBUG == DEBUG_UART2) + while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); + USART_SendData(USART2, *buf++); +#elif(DEBUG == DEBUG_UART3) + while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); + USART_SendData(USART3, *buf++); +#endif + } +#endif + + return size; +} +#endif + +/********************************************************************* + * @fn _sbrk + * + * @brief Change the spatial position of data segment. + * + * @return size: Data length + */ +void *_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} + +void _fini() {} +void _init() {} + diff --git a/system/CH32V10x/SRC/Debug/debug.h b/system/CH32V10x/SRC/Debug/debug.h index 2b895c3..5481b11 100644 --- a/system/CH32V10x/SRC/Debug/debug.h +++ b/system/CH32V10x/SRC/Debug/debug.h @@ -1,45 +1,54 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : debug.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for UART - * Printf , Delay functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __DEBUG_H -#define __DEBUG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "stdio.h" -#include "ch32v10x.h" - -/* HID function switch, 1 is to turn off HID function, 0 is to turn on HID function */ -#define ch32v10x_usb_hid 0 - -/* UART Printf Definition */ -#define DEBUG_UART1 1 -#define DEBUG_UART2 2 -#define DEBUG_UART3 3 - -/* DEBUG UATR Definition */ -#ifndef DEBUG -#define DEBUG DEBUG_UART1 -#endif - -void Delay_Init(void); -void Delay_Us(uint32_t n); -void Delay_Ms(uint32_t n); -void USART_Printf_Init(uint32_t baudrate); - -#ifdef __cplusplus -} -#endif - -#endif /* __DEBUG_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __DEBUG_H +#define __DEBUG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stdio.h" +#include "ch32v10x.h" + +/* HID function ,1 close HID function ,0 open HID function */ +#define ch32v10x_usb_hid 0 + +/* UART Printf Definition */ +#define DEBUG_UART1 1 +#define DEBUG_UART2 2 +#define DEBUG_UART3 3 + +/* DEBUG UATR Definition */ +#ifndef DEBUG +#define DEBUG DEBUG_UART1 +#endif + +/* SDI Printf Definition */ +#define SDI_PR_CLOSE 0 +#define SDI_PR_OPEN 1 + +#ifndef SDI_PRINT +#define SDI_PRINT SDI_PR_CLOSE +#endif + +void Delay_Init(void); +void Delay_Us(uint32_t n); +void Delay_Ms(uint32_t n); +void USART_Printf_Init(uint32_t baudrate); +void SDI_Printf_Enable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DEBUG_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x.h index 9aa61e1..87801aa 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x.h @@ -1,3223 +1,3236 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : CH32V10x Device Peripheral Access Layer Header File. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V10x_H -#define __CH32V10x_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ - -#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ - -/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x500) /* Time out for HSE start up */ - -#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ - -/* CH32V10x Standard Peripheral Library version number */ -#define __CH32V10x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */ -#define __CH32V10x_STDPERIPH_VERSION_SUB (0x00) /* [7:0] sub version */ -#define __CH32V10x_STDPERIPH_VERSION ( (__CH32V10x_STDPERIPH_VERSION_MAIN << 8)\ - |(__CH32V10x_STDPERIPH_VERSION_SUB << 0)) - -/* Interrupt Number Definition, according to the selected device */ -typedef enum IRQn -{ - /****** RISC-V Processor Exceptions Numbers *******************************************************/ - NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ - EXC_IRQn = 3, /* 4 Exception Interrupt */ - SysTicK_IRQn = 12, /* 12 System timer Interrupt */ - Software_IRQn = 14, /* 14 software Interrupt */ - - /****** RISC-V specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 16, /* Window WatchDog Interrupt */ - PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 18, /* Tamper Interrupt */ - RTC_IRQn = 19, /* RTC global Interrupt */ - FLASH_IRQn = 20, /* FLASH global Interrupt */ - RCC_IRQn = 21, /* RCC global Interrupt */ - EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ - EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ - EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ - EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ - EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ - ADC_IRQn = 34, /* ADC1 global Interrupt */ - EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ - TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 44, /* TIM2 global Interrupt */ - TIM3_IRQn = 45, /* TIM3 global Interrupt */ - TIM4_IRQn = 46, /* TIM4 global Interrupt */ - I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ - I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ - I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ - I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ - SPI1_IRQn = 51, /* SPI1 global Interrupt */ - SPI2_IRQn = 52, /* SPI2 global Interrupt */ - USART1_IRQn = 53, /* USART1 global Interrupt */ - USART2_IRQn = 54, /* USART2 global Interrupt */ - USART3_IRQn = 55, /* USART3 global Interrupt */ - EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 58, /* USB WakeUp from suspend through EXTI Line Interrupt */ - USBHD_IRQn = 59, /* USBHD Interrupt */ - -} IRQn_Type; - -#define HardFault_IRQn EXC_IRQn -#define ADC1_2_IRQn ADC_IRQn - -#include -#include "core_riscv.h" -#include "system_ch32v10x.h" - -/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSI_Value HSI_VALUE -#define HSE_Value HSE_VALUE -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT - -/* Analog to Digital Converter */ -typedef struct -{ - __IO uint32_t STATR; - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t SAMPTR1; - __IO uint32_t SAMPTR2; - __IO uint32_t IOFR1; - __IO uint32_t IOFR2; - __IO uint32_t IOFR3; - __IO uint32_t IOFR4; - __IO uint32_t WDHTR; - __IO uint32_t WDLTR; - __IO uint32_t RSQR1; - __IO uint32_t RSQR2; - __IO uint32_t RSQR3; - __IO uint32_t ISQR; - __IO uint32_t IDATAR1; - __IO uint32_t IDATAR2; - __IO uint32_t IDATAR3; - __IO uint32_t IDATAR4; - __IO uint32_t RDATAR; -} ADC_TypeDef; - -/* Backup Registers */ -typedef struct -{ - uint32_t RESERVED0; - __IO uint16_t DATAR1; - uint16_t RESERVED1; - __IO uint16_t DATAR2; - uint16_t RESERVED2; - __IO uint16_t DATAR3; - uint16_t RESERVED3; - __IO uint16_t DATAR4; - uint16_t RESERVED4; - __IO uint16_t DATAR5; - uint16_t RESERVED5; - __IO uint16_t DATAR6; - uint16_t RESERVED6; - __IO uint16_t DATAR7; - uint16_t RESERVED7; - __IO uint16_t DATAR8; - uint16_t RESERVED8; - __IO uint16_t DATAR9; - uint16_t RESERVED9; - __IO uint16_t DATAR10; - uint16_t RESERVED10; - __IO uint16_t OCTLR; - uint16_t RESERVED11; - __IO uint16_t TPCTLR; - uint16_t RESERVED12; - __IO uint16_t TPCSR; - uint16_t RESERVED13[5]; - __IO uint16_t DATAR11; - uint16_t RESERVED14; - __IO uint16_t DATAR12; - uint16_t RESERVED15; - __IO uint16_t DATAR13; - uint16_t RESERVED16; - __IO uint16_t DATAR14; - uint16_t RESERVED17; - __IO uint16_t DATAR15; - uint16_t RESERVED18; - __IO uint16_t DATAR16; - uint16_t RESERVED19; - __IO uint16_t DATAR17; - uint16_t RESERVED20; - __IO uint16_t DATAR18; - uint16_t RESERVED21; - __IO uint16_t DATAR19; - uint16_t RESERVED22; - __IO uint16_t DATAR20; - uint16_t RESERVED23; - __IO uint16_t DATAR21; - uint16_t RESERVED24; - __IO uint16_t DATAR22; - uint16_t RESERVED25; - __IO uint16_t DATAR23; - uint16_t RESERVED26; - __IO uint16_t DATAR24; - uint16_t RESERVED27; - __IO uint16_t DATAR25; - uint16_t RESERVED28; - __IO uint16_t DATAR26; - uint16_t RESERVED29; - __IO uint16_t DATAR27; - uint16_t RESERVED30; - __IO uint16_t DATAR28; - uint16_t RESERVED31; - __IO uint16_t DATAR29; - uint16_t RESERVED32; - __IO uint16_t DATAR30; - uint16_t RESERVED33; - __IO uint16_t DATAR31; - uint16_t RESERVED34; - __IO uint16_t DATAR32; - uint16_t RESERVED35; - __IO uint16_t DATAR33; - uint16_t RESERVED36; - __IO uint16_t DATAR34; - uint16_t RESERVED37; - __IO uint16_t DATAR35; - uint16_t RESERVED38; - __IO uint16_t DATAR36; - uint16_t RESERVED39; - __IO uint16_t DATAR37; - uint16_t RESERVED40; - __IO uint16_t DATAR38; - uint16_t RESERVED41; - __IO uint16_t DATAR39; - uint16_t RESERVED42; - __IO uint16_t DATAR40; - uint16_t RESERVED43; - __IO uint16_t DATAR41; - uint16_t RESERVED44; - __IO uint16_t DATAR42; - uint16_t RESERVED45; -} BKP_TypeDef; - -/* CRC Calculation Unit */ -typedef struct -{ - __IO uint32_t DATAR; - __IO uint8_t IDATAR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CTLR; -} CRC_TypeDef; - -/* Digital to Analog Converter */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t SWTR; - __IO uint32_t R12BDHR1; - __IO uint32_t L12BDHR1; - __IO uint32_t R8BDHR1; - __IO uint32_t R12BDHR2; - __IO uint32_t L12BDHR2; - __IO uint32_t R8BDHR2; - __IO uint32_t RD12BDHR; - __IO uint32_t LD12BDHR; - __IO uint32_t RD8BDHR; - __IO uint32_t DOR1; - __IO uint32_t DOR2; -} DAC_TypeDef; - -/* Debug MCU */ -typedef struct -{ - __IO uint32_t CFGR0; - __IO uint32_t CFGR1; -} DBGMCU_TypeDef; - -/* DMA Controller */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t CNTR; - __IO uint32_t PADDR; - __IO uint32_t MADDR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t INTFR; - __IO uint32_t INTFCR; -} DMA_TypeDef; - -/* External Interrupt/Event Controller */ -typedef struct -{ - __IO uint32_t INTENR; - __IO uint32_t EVENR; - __IO uint32_t RTENR; - __IO uint32_t FTENR; - __IO uint32_t SWIEVR; - __IO uint32_t INTFR; -} EXTI_TypeDef; - -/* FLASH Registers */ -typedef struct -{ - __IO uint32_t ACTLR; - __IO uint32_t KEYR; - __IO uint32_t OBKEYR; - __IO uint32_t STATR; - __IO uint32_t CTLR; - __IO uint32_t ADDR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WPR; - __IO uint32_t MODEKEYR; -} FLASH_TypeDef; - -/* Option Bytes Registers */ -typedef struct -{ - __IO uint16_t RDPR; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRPR0; - __IO uint16_t WRPR1; - __IO uint16_t WRPR2; - __IO uint16_t WRPR3; -} OB_TypeDef; - -/* General Purpose I/O */ -typedef struct -{ - __IO uint32_t CFGLR; - __IO uint32_t CFGHR; - __IO uint32_t INDR; - __IO uint32_t OUTDR; - __IO uint32_t BSHR; - __IO uint32_t BCR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/* Alternate Function I/O */ -typedef struct -{ - __IO uint32_t ECR; - __IO uint32_t PCFR1; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t PCFR2; -} AFIO_TypeDef; - -/* Inter Integrated Circuit Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t OADDR1; - uint16_t RESERVED2; - __IO uint16_t OADDR2; - uint16_t RESERVED3; - __IO uint16_t DATAR; - uint16_t RESERVED4; - __IO uint16_t STAR1; - uint16_t RESERVED5; - __IO uint16_t STAR2; - uint16_t RESERVED6; - __IO uint16_t CKCFGR; - uint16_t RESERVED7; - __IO uint16_t RTR; - uint16_t RESERVED8; -} I2C_TypeDef; - -/* Independent WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t PSCR; - __IO uint32_t RLDR; - __IO uint32_t STATR; -} IWDG_TypeDef; - -/* Power Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/* Reset and Clock Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR0; - __IO uint32_t INTR; - __IO uint32_t APB2PRSTR; - __IO uint32_t APB1PRSTR; - __IO uint32_t AHBPCENR; - __IO uint32_t APB2PCENR; - __IO uint32_t APB1PCENR; - __IO uint32_t BDCTLR; - __IO uint32_t RSTSCKR; -} RCC_TypeDef; - -/* Real-Time Clock */ -typedef struct -{ - __IO uint16_t CTLRH; - uint16_t RESERVED0; - __IO uint16_t CTLRL; - uint16_t RESERVED1; - __IO uint16_t PSCRH; - uint16_t RESERVED2; - __IO uint16_t PSCRL; - uint16_t RESERVED3; - __IO uint16_t DIVH; - uint16_t RESERVED4; - __IO uint16_t DIVL; - uint16_t RESERVED5; - __IO uint16_t CNTH; - uint16_t RESERVED6; - __IO uint16_t CNTL; - uint16_t RESERVED7; - __IO uint16_t ALRMH; - uint16_t RESERVED8; - __IO uint16_t ALRML; - uint16_t RESERVED9; -} RTC_TypeDef; - -/* Serial Peripheral Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t STATR; - uint16_t RESERVED2; - __IO uint16_t DATAR; - uint16_t RESERVED3; - __IO uint16_t CRCR; - uint16_t RESERVED4; - __IO uint16_t RCRCR; - uint16_t RESERVED5; - __IO uint16_t TCRCR; - uint16_t RESERVED6; - __IO uint16_t I2SCFGR; - uint16_t RESERVED7; - __IO uint16_t I2SPR; - uint16_t RESERVED8; -} SPI_TypeDef; - -/* TIM */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t SMCFGR; - uint16_t RESERVED2; - __IO uint16_t DMAINTENR; - uint16_t RESERVED3; - __IO uint16_t INTFR; - uint16_t RESERVED4; - __IO uint16_t SWEVGR; - uint16_t RESERVED5; - __IO uint16_t CHCTLR1; - uint16_t RESERVED6; - __IO uint16_t CHCTLR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ATRLR; - uint16_t RESERVED11; - __IO uint16_t RPTCR; - uint16_t RESERVED12; - __IO uint16_t CH1CVR; - uint16_t RESERVED13; - __IO uint16_t CH2CVR; - uint16_t RESERVED14; - __IO uint16_t CH3CVR; - uint16_t RESERVED15; - __IO uint16_t CH4CVR; - uint16_t RESERVED16; - __IO uint16_t BDTR; - uint16_t RESERVED17; - __IO uint16_t DMACFGR; - uint16_t RESERVED18; - __IO uint16_t DMAADR; - uint16_t RESERVED19; -} TIM_TypeDef; - -/* Universal Synchronous Asynchronous Receiver Transmitter */ -typedef struct -{ - __IO uint16_t STATR; - uint16_t RESERVED0; - __IO uint16_t DATAR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CTLR1; - uint16_t RESERVED3; - __IO uint16_t CTLR2; - uint16_t RESERVED4; - __IO uint16_t CTLR3; - uint16_t RESERVED5; - __IO uint16_t GPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/* Window WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR; - __IO uint32_t STATR; -} WWDG_TypeDef; - -/* Enhanced Registers */ -typedef struct -{ - __IO uint32_t EXTEN_CTR; -} EXTEN_TypeDef; - -/* Peripheral memory map */ -#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ - -#define APB1PERIPH_BASE (PERIPH_BASE) -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) -#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) -#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ -#define DBGMCU_BASE ((uint32_t)0xE000D000) -#define EXTEN_BASE ((uint32_t)0x40023800) - -/* Peripheral declaration */ -#define TIM2 ((TIM_TypeDef *)TIM2_BASE) -#define TIM3 ((TIM_TypeDef *)TIM3_BASE) -#define TIM4 ((TIM_TypeDef *)TIM4_BASE) -#define TIM5 ((TIM_TypeDef *)TIM5_BASE) -#define TIM6 ((TIM_TypeDef *)TIM6_BASE) -#define TIM7 ((TIM_TypeDef *)TIM7_BASE) -#define TIM12 ((TIM_TypeDef *)TIM12_BASE) -#define TIM13 ((TIM_TypeDef *)TIM13_BASE) -#define TIM14 ((TIM_TypeDef *)TIM14_BASE) -#define RTC ((RTC_TypeDef *)RTC_BASE) -#define WWDG ((WWDG_TypeDef *)WWDG_BASE) -#define IWDG ((IWDG_TypeDef *)IWDG_BASE) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) -#define SPI3 ((SPI_TypeDef *)SPI3_BASE) -#define USART2 ((USART_TypeDef *)USART2_BASE) -#define USART3 ((USART_TypeDef *)USART3_BASE) -#define UART4 ((USART_TypeDef *)UART4_BASE) -#define UART5 ((USART_TypeDef *)UART5_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define I2C2 ((I2C_TypeDef *)I2C2_BASE) -#define BKP ((BKP_TypeDef *)BKP_BASE) -#define PWR ((PWR_TypeDef *)PWR_BASE) -#define DAC ((DAC_TypeDef *)DAC_BASE) -#define AFIO ((AFIO_TypeDef *)AFIO_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#define ADC2 ((ADC_TypeDef *)ADC2_BASE) -#define TIM1 ((TIM_TypeDef *)TIM1_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define TIM8 ((TIM_TypeDef *)TIM8_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) -#define ADC3 ((ADC_TypeDef *)ADC3_BASE) -#define TIM15 ((TIM_TypeDef *)TIM15_BASE) -#define TIM16 ((TIM_TypeDef *)TIM16_BASE) -#define TIM17 ((TIM_TypeDef *)TIM17_BASE) -#define TIM9 ((TIM_TypeDef *)TIM9_BASE) -#define TIM10 ((TIM_TypeDef *)TIM10_BASE) -#define TIM11 ((TIM_TypeDef *)TIM11_BASE) -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA2 ((DMA_TypeDef *)DMA2_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) -#define RCC ((RCC_TypeDef *)RCC_BASE) -#define CRC ((CRC_TypeDef *)CRC_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#define OB ((OB_TypeDef *)OB_BASE) -#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) -#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) - -/******************************************************************************/ -/* Peripheral Registers Bits Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* Analog to Digital Converter */ -/******************************************************************************/ - -/******************** Bit definition for ADC_STATR register ********************/ -#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ -#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ -#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ -#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ -#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ - -/******************* Bit definition for ADC_CTLR1 register ********************/ -#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ -#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ -#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ -#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ -#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ -#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ -#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ -#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ - -#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ -#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ - -#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ -#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ -#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ - -#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ -#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ - -/******************* Bit definition for ADC_CTLR2 register ********************/ -#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ -#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ -#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ -#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ -#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ -#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ - -#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ - -#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ -#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ -#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ - -#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ -#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ -#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ -#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ - -/****************** Bit definition for ADC_SAMPTR1 register *******************/ -#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ - -/****************** Bit definition for ADC_SAMPTR2 register *******************/ -#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ - -#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ -#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ -#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ - -/****************** Bit definition for ADC_IOFR1 register *******************/ -#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_IOFR2 register *******************/ -#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_IOFR3 register *******************/ -#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_IOFR4 register *******************/ -#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_WDHTR register ********************/ -#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ - -/******************* Bit definition for ADC_WDLTR register ********************/ -#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ - -/******************* Bit definition for ADC_RSQR1 register *******************/ -#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ -#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ - -/******************* Bit definition for ADC_RSQR2 register *******************/ -#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_RSQR3 register *******************/ -#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_ISQR register *******************/ -#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ -#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ - -/******************* Bit definition for ADC_IDATAR1 register *******************/ -#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR2 register *******************/ -#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR3 register *******************/ -#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR4 register *******************/ -#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************** Bit definition for ADC_RDATAR register ********************/ -#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ -#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ - -/******************************************************************************/ -/* Backup registers */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DATAR1 register ********************/ -#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR2 register ********************/ -#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR3 register ********************/ -#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR4 register ********************/ -#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR5 register ********************/ -#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR6 register ********************/ -#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR7 register ********************/ -#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR8 register ********************/ -#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR9 register ********************/ -#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR10 register *******************/ -#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR11 register *******************/ -#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR12 register *******************/ -#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR13 register *******************/ -#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR14 register *******************/ -#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR15 register *******************/ -#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR16 register *******************/ -#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR17 register *******************/ -#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ - -/****************** Bit definition for BKP_DATAR18 register ********************/ -#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR19 register *******************/ -#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR20 register *******************/ -#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR21 register *******************/ -#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR22 register *******************/ -#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR23 register *******************/ -#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR24 register *******************/ -#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR25 register *******************/ -#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR26 register *******************/ -#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR27 register *******************/ -#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR28 register *******************/ -#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR29 register *******************/ -#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR30 register *******************/ -#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR31 register *******************/ -#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR32 register *******************/ -#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR33 register *******************/ -#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR34 register *******************/ -#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR35 register *******************/ -#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR36 register *******************/ -#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR37 register *******************/ -#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR38 register *******************/ -#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR39 register *******************/ -#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR40 register *******************/ -#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR41 register *******************/ -#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR42 register *******************/ -#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ - -/****************** Bit definition for BKP_OCTLR register *******************/ -#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ -#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ -#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ -#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_TPCTLR register ********************/ -#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ -#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ - -/******************* Bit definition for BKP_TPCSR register ********************/ -#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ -#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ -#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ -#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ -#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ - -/******************************************************************************/ -/* CRC Calculation Unit */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DATAR register *********************/ -#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ - -/******************* Bit definition for CRC_IDATAR register ********************/ -#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ - -/******************** Bit definition for CRC_CTLR register ********************/ -#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ - -/******************************************************************************/ -/* Digital to Analog Converter */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CTLR register ********************/ -#define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */ -#define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */ -#define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */ - -#define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */ -#define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */ -#define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */ - -#define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */ -#define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */ -#define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */ -#define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */ - -#define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */ -#define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */ -#define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */ - -#define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */ -#define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */ - -#define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */ - -/***************** Bit definition for DAC_SWTR register ******************/ -#define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */ -#define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */ - -/***************** Bit definition for DAC_R12BDHR1 register ******************/ -#define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */ - -/***************** Bit definition for DAC_L12BDHR1 register ******************/ -#define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */ - -/****************** Bit definition for DAC_R8BDHR1 register ******************/ -#define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */ - -/***************** Bit definition for DAC_R12BDHR2 register ******************/ -#define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_L12BDHR2 register ******************/ -#define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_R8BDHR2 register ******************/ -#define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */ - -/***************** Bit definition for DAC_RD12BDHR register ******************/ -#define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ -#define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_LD12BDHR register ******************/ -#define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ -#define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_RD8BDHR register ******************/ -#define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */ -#define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */ - -/******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */ - -/******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */ - -/******************************************************************************/ -/* DMA Controller */ -/******************************************************************************/ - -/******************* Bit definition for DMA_INTFR register ********************/ -#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ -#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ -#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ -#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ -#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ -#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ -#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ -#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ -#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ -#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ -#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ -#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ -#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ -#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ -#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ -#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ -#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ -#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ -#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ -#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ -#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ -#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ -#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ -#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ -#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ -#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ -#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ -#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_INTFCR register *******************/ -#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ -#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ -#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ -#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ -#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ -#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ -#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ -#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ -#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ -#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ -#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ -#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ -#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ -#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ -#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ -#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ -#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ -#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ -#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ -#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ -#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ -#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ -#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ -#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ -#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ -#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ -#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ -#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CFGR1 register *******************/ -#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ -#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ -#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR2 register *******************/ -#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR3 register *******************/ -#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG4 register *******************/ -#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/****************** Bit definition for DMA_CFG5 register *******************/ -#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/******************* Bit definition for DMA_CFG6 register *******************/ -#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG7 register *******************/ -#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/****************** Bit definition for DMA_CNTR1 register ******************/ -#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR2 register ******************/ -#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR3 register ******************/ -#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR4 register ******************/ -#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR5 register ******************/ -#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR6 register ******************/ -#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR7 register ******************/ -#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_PADDR1 register *******************/ -#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR2 register *******************/ -#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR3 register *******************/ -#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR4 register *******************/ -#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR5 register *******************/ -#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR6 register *******************/ -#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR7 register *******************/ -#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_MADDR1 register *******************/ -#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR2 register *******************/ -#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR3 register *******************/ -#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR4 register *******************/ -#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR5 register *******************/ -#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR6 register *******************/ -#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR7 register *******************/ -#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/******************************************************************************/ -/* External Interrupt/Event Controller */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_INTENR register *******************/ -#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ -#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ -#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ -#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ -#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ -#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ -#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ -#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ -#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ -#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ -#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ -#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ -#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ -#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ -#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ -#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ -#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ -#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ -#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ -#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ - -/******************* Bit definition for EXTI_EVENR register *******************/ -#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ -#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ -#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ -#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ -#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ -#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ -#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ -#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ -#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ -#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ -#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ -#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ -#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ -#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ -#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ -#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ -#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ -#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ -#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ -#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ - -/****************** Bit definition for EXTI_RTENR register *******************/ -#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ -#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ -#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ -#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ -#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ -#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ -#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ -#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ -#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ -#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ -#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ -#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ -#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ -#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ -#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ -#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ -#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ -#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ -#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ -#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_FTENR register *******************/ -#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ -#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ -#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ -#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ -#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ -#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ -#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ -#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ -#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ -#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ -#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ -#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ -#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ -#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ -#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ -#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ -#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ -#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ -#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ -#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_SWIEVR register ******************/ -#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ -#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ -#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ -#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ -#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ -#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ -#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ -#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ -#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ -#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ -#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ -#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ -#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ -#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ -#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ -#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ -#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ -#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ -#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ -#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ - -/******************* Bit definition for EXTI_INTFR register ********************/ -#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ -#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ -#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ -#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ -#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ -#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ -#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ -#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ -#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ -#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ -#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ -#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ -#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ -#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ -#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ -#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ -#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ -#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ -#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ -#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ - -/******************************************************************************/ -/* FLASH and Option Bytes Registers */ -/******************************************************************************/ - -/******************* Bit definition for FLASH_ACTLR register ******************/ -#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ -#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ - -#define FLASH_ACTLR_HLFCYA ((uint8_t)0x08) /* Flash Half Cycle Access Enable */ -#define FLASH_ACTLR_PRFTBE ((uint8_t)0x10) /* Prefetch Buffer Enable */ -#define FLASH_ACTLR_PRFTBS ((uint8_t)0x20) /* Prefetch Buffer Status */ - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ - -/***************** Bit definition for FLASH_OBKEYR register ****************/ -#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ - -/****************** Bit definition for FLASH_STATR register *******************/ -#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ -#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ -#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ -#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ - -/******************* Bit definition for FLASH_CTLR register *******************/ -#define FLASH_CTLR_PG ((uint16_t)0x0001) /* Programming */ -#define FLASH_CTLR_PER ((uint16_t)0x0002) /* Page Erase */ -#define FLASH_CTLR_MER ((uint16_t)0x0004) /* Mass Erase */ -#define FLASH_CTLR_OPTPG ((uint16_t)0x0010) /* Option Byte Programming */ -#define FLASH_CTLR_OPTER ((uint16_t)0x0020) /* Option Byte Erase */ -#define FLASH_CTLR_STRT ((uint16_t)0x0040) /* Start */ -#define FLASH_CTLR_LOCK ((uint16_t)0x0080) /* Lock */ -#define FLASH_CTLR_OPTWRE ((uint16_t)0x0200) /* Option Bytes Write Enable */ -#define FLASH_CTLR_ERRIE ((uint16_t)0x0400) /* Error Interrupt Enable */ -#define FLASH_CTLR_EOPIE ((uint16_t)0x1000) /* End of operation interrupt enable */ -#define FLASH_CTLR_PAGE_PG ((uint16_t)0x00010000) /* Page Programming 128Byte */ -#define FLASH_CTLR_PAGE_ER ((uint16_t)0x00020000) /* Page Erase 128Byte */ -#define FLASH_CTLR_BUF_LOAD ((uint16_t)0x00040000) /* Buffer Load */ -#define FLASH_CTLR_BUF_RST ((uint16_t)0x00080000) /* Buffer Reset */ - -/******************* Bit definition for FLASH_ADDR register *******************/ -#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ - -#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ -#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ -#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /* BFB2 */ - -/****************** Bit definition for FLASH_WPR register ******************/ -#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ - -/****************** Bit definition for FLASH_RDPR register *******************/ -#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ -#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_WRPR0 register ******************/ -#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR1 register ******************/ -#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR2 register ******************/ -#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR3 register ******************/ -#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ - -/******************************************************************************/ -/* General Purpose and Alternate Function I/O */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CFGLR register *******************/ -#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_CFGHR register *******************/ -#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_INDR register *******************/ -#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ -#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ -#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ -#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ -#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ -#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ -#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ -#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ -#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ -#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ -#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ -#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ -#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ -#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ -#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ -#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ - -/******************* Bit definition for GPIO_OUTDR register *******************/ -#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ -#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ -#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ -#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ -#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ -#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ -#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ -#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ -#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ -#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ -#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ -#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ -#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ -#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ -#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ -#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSHR register *******************/ -#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ -#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ -#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ -#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ -#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ -#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ -#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ -#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ -#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ -#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ -#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ -#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ -#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ -#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ -#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ -#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ - -#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ -#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ -#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ -#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ -#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ -#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ -#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ -#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ -#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ -#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ -#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ -#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ -#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ -#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ -#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ -#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BCR register *******************/ -#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ -#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ -#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ -#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ -#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ -#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ -#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ -#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ -#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ -#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ -#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ -#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ -#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ -#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ -#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ -#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ -#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ -#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ -#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ -#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ -#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ -#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ -#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ -#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ -#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ -#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ -#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ -#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ -#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ -#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ -#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ -#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ - -/****************** Bit definition for AFIO_ECR register *******************/ -#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ -#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ -#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ -#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ -#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ - -#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ -#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ -#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ -#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ -#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ -#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ -#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ -#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ -#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ -#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ -#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ -#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ -#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ -#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ -#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ -#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ - -#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ -#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ -#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ -#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ - -#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ -#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ -#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ -#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ -#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ - -#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ - -/****************** Bit definition for AFIO_PCFR1register *******************/ -#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ -#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ -#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ -#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ - -#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ - -#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ -#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ - -#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ - -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ - -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ - -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ - -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ - -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ - -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ - -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ - -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ - -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ - -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ - -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ - -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ - -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ - -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ - -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ - -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ - -/******************************************************************************/ -/* Independent WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_CTLR register ********************/ -#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PSCR register ********************/ -#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ -#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ -#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ -#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ - -/******************* Bit definition for IWDG_RLDR register *******************/ -#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ - -/******************* Bit definition for IWDG_STATR register ********************/ -#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ -#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ - -/******************************************************************************/ -/* Inter-integrated Circuit Interface */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CTLR1 register ********************/ -#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ -#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ -#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ -#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ -#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ -#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ -#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ -#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ -#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ -#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ -#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ -#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ -#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ -#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ - -/******************* Bit definition for I2C_CTLR2 register ********************/ -#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ - -#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ -#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ -#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ -#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ -#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ - -/******************* Bit definition for I2C_OADDR1 register *******************/ -#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ -#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ - -#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ -#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ -#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ -#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ -#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ - -#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OADDR2 register *******************/ -#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ -#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ - -/******************** Bit definition for I2C_DATAR register ********************/ -#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ - -/******************* Bit definition for I2C_STAR1 register ********************/ -#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ -#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ -#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ -#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ -#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ -#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ -#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ -#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ -#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ -#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ -#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ -#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ -#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ -#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ - -/******************* Bit definition for I2C_STAR2 register ********************/ -#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ -#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ -#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ -#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ -#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ -#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ -#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ -#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ - -/******************* Bit definition for I2C_CKCFGR register ********************/ -#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ -#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ - -/****************** Bit definition for I2C_RTR register *******************/ -#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ - -/******************************************************************************/ -/* Power Control */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CTLR register ********************/ -#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ -#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ -#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ -#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ -#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ - -#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ -#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ - -#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */ -#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */ -#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */ -#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */ -#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */ -#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */ -#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */ -#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */ - -#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ - -/******************************************************************************/ -/* Reset and Clock Control */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CTLR register ********************/ -#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ -#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ -#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ -#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ -#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ -#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ -#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ -#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ -#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ -#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ - -/******************* Bit definition for RCC_CFGR0 register *******************/ -#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ -#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ -#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ -#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ - -#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ -#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ -#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ - -#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ -#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ -#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ - -#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ -#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ -#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ -#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ -#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ -#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ -#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ -#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ -#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ - -#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ -#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ - -#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ -#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ -#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ -#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ -#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ - -#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ -#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ -#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ - -#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ -#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ -#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ -#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ -#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ - -#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ -#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ -#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ -#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ - -#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ - -#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ - -#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ -#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ - -#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ -#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ - -#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ -#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ - -#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ -#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ -#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ -#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ -#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ -#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ -#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ -#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ -#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ -#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ -#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ -#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ -#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ -#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ -#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ -#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ - -#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ -#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ -#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ -#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ - -/******************* Bit definition for RCC_INTR register ********************/ -#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ -#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ -#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ -#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ -#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ -#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ -#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ -#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ -#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ -#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ -#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ -#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ -#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ -#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ -#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ -#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ -#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ - -/***************** Bit definition for RCC_APB2PRSTR register *****************/ -#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ -#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ -#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ -#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ -#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ -#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ - -#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ - -#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ -#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ -#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ - -#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ - -/***************** Bit definition for RCC_APB1PRSTR register *****************/ -#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ -#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ -#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ -#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ -#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ - -#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ - -#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ -#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ - -#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ -#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ -#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ -#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ - -#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ - -/****************** Bit definition for RCC_AHBPCENR register ******************/ -#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ -#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ -#define RCC_FLITFEN ((uint16_t)0x0010) /* FLITF clock enable */ -#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ -#define RCC_USBHD ((uint16_t)0x1000) - -/****************** Bit definition for RCC_APB2PCENR register *****************/ -#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ -#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ -#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ -#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ -#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ -#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ - -#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ - -#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ -#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ -#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ - -/***************** Bit definition for RCC_APB1PCENR register ******************/ -#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ -#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ -#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ -#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ -#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ - -#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ -#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ - -#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ - -/******************* Bit definition for RCC_BDCTLR register *******************/ -#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ -#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ -#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ - -#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ -#define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */ -#define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */ -#define RCC_RTCSEL_HSE ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ -#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ - -/******************* Bit definition for RCC_RSTSCKR register ********************/ -#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ -#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ -#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ -#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ -#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ -#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ -#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ -#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ -#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ - -/******************************************************************************/ -/* Real-Time Clock */ -/******************************************************************************/ - -/******************* Bit definition for RTC_CTLRH register ********************/ -#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ -#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ -#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ - -/******************* Bit definition for RTC_CTLRL register ********************/ -#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ -#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ -#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ -#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ -#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ -#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ - -/******************* Bit definition for RTC_PSCH register *******************/ -#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ - -/******************* Bit definition for RTC_PRLL register *******************/ -#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ - -/******************* Bit definition for RTC_DIVH register *******************/ -#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ - -/******************* Bit definition for RTC_DIVL register *******************/ -#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ - -/******************* Bit definition for RTC_CNTH register *******************/ -#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ - -/******************* Bit definition for RTC_CNTL register *******************/ -#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ - -/******************* Bit definition for RTC_ALRMH register *******************/ -#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ - -/******************* Bit definition for RTC_ALRML register *******************/ -#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ - -/******************************************************************************/ -/* Serial Peripheral Interface */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CTLR1 register ********************/ -#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ -#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ -#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ - -#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ -#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ -#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ -#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ - -#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ -#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ -#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ -#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ -#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ -#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ -#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ -#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ -#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ -#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CTLR2 register ********************/ -#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ -#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ -#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ -#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ -#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ -#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_STATR register ********************/ -#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ -#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ -#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ -#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ -#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ -#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ -#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ -#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ - -/******************** Bit definition for SPI_DATAR register ********************/ -#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ - -/******************* Bit definition for SPI_CRCR register ******************/ -#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ - -/****************** Bit definition for SPI_RCRCR register ******************/ -#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ - -/****************** Bit definition for SPI_TCRCR register ******************/ -#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ - -/****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ - -#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ -#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ - -/****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ -#define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ - -/******************************************************************************/ -/* TIM */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CTLR1 register ********************/ -#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ -#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ -#define TIM_URS ((uint16_t)0x0004) /* Update request source */ -#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ -#define TIM_DIR ((uint16_t)0x0010) /* Direction */ - -#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ - -#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ - -#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ -#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ - -/******************* Bit definition for TIM_CTLR2 register ********************/ -#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ -#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ -#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ - -#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ -#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ -#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ -#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ -#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ -#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ -#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ -#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ -#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIM_SMCFGR register *******************/ -#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ - -#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ -#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ - -#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ -#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ - -#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ -#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ - -/******************* Bit definition for TIM_DMAINTENR register *******************/ -#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ -#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ -#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ -#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ -#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ -#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ -#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ -#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ -#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ -#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ -#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ -#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ -#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ -#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ -#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ - -/******************** Bit definition for TIM_INTFR register ********************/ -#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ -#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ -#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ -#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ -#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ -#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ -#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ -#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ -#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ -#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ -#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ -#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIM_SWEVGR register ********************/ -#define TIM_UG ((uint8_t)0x01) /* Update Generation */ -#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ -#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ -#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ -#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ -#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ -#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ -#define TIM_BG ((uint8_t)0x80) /* Break Generation */ - -/****************** Bit definition for TIM_CHCTLR1 register *******************/ -#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ -#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ - -#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ - -#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ -#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ - -#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ - -#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/****************** Bit definition for TIM_CHCTLR2 register *******************/ -#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ -#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ - -#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ - -#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ -#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ - -#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ - -#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ -#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ -#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ -#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ -#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ -#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ -#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ -#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ -#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ -#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ -#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ -#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ -#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ -#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ -#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ - -/******************* Bit definition for TIM_ATRLR register ********************/ -#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ - -/******************* Bit definition for TIM_RPTCR register ********************/ -#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ - -/******************* Bit definition for TIM_CH1CVR register *******************/ -#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ - -/******************* Bit definition for TIM_CH2CVR register *******************/ -#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ - -/******************* Bit definition for TIM_CH3CVR register *******************/ -#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ - -/******************* Bit definition for TIM_CH4CVR register *******************/ -#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ -#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ -#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ -#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ - -#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ -#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ -#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ -#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ -#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ -#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ -#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ - -/******************* Bit definition for TIM_DMACFGR register ********************/ -#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ -#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ - -#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ -#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ - -/******************* Bit definition for TIM_DMAADR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ - -/******************************************************************************/ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/******************************************************************************/ - -/******************* Bit definition for USART_STATR register *******************/ -#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ -#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ -#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ -#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ -#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ -#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ -#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ -#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ -#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ -#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ - -/******************* Bit definition for USART_DATAR register *******************/ -#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ - -/****************** Bit definition for USART_CTLR1 register *******************/ -#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ -#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ -#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ -#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ -#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ -#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ -#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ -#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ -#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ -#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ -#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ -#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ -#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ -#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ -#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ - -/****************** Bit definition for USART_CTLR2 register *******************/ -#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ -#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ -#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ -#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ -#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ -#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ -#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ - -#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ -#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ -#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ - -/****************** Bit definition for USART_CTLR3 register *******************/ -#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ -#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ -#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ -#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ -#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ -#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ -#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ -#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ -#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ -#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ -#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ -#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ - -/****************** Bit definition for USART_GPR register ******************/ -#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ -#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ -#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ -#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ -#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ -#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ -#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ -#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ -#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ - -#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ - -/******************************************************************************/ -/* Window WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CTLR register ********************/ -#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ -#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ -#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ -#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ -#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ -#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ -#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ - -#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ - -/******************* Bit definition for WWDG_CFGR register *******************/ -#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ -#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ -#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ -#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ -#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ -#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ -#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ -#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ - -#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ -#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ - -#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_STATR register ********************/ -#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ - -/******************************************************************************/ -/* ENHANCED FUNNCTION */ -/******************************************************************************/ - -/**************************** Enhanced register *****************************/ -#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */ -#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */ -#define EXTEN_USBHD_IO_EN ((uint32_t)0x00000004) /* Bit 2 */ -#define EXTEN_USB_5V_SEL ((uint32_t)0x00000008) /* Bit 3 */ -#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ -#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ -#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ - -#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */ -#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ -#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define EXTEN_IDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */ -#define EXTEN_WRITE_EN ((uint32_t)0x00004000) /* Bit 14 */ -#define EXTEN_SHORT_WAKE ((uint32_t)0x00008000) /* Bit 15 */ - -#define EXTEN_FLASH_CLK_TRIM ((uint32_t)0x00070000) /* FLASH_CLK_TRIM[2:0] bits */ -#define EXTEN_FLASH_CLK_TRIM0 ((uint32_t)0x00010000) /* Bit 0 */ -#define EXTEN_FLASH_CLK_TRIM1 ((uint32_t)0x00020000) /* Bit 1 */ -#define EXTEN_FLASH_CLK_TRIM2 ((uint32_t)0x00040000) /* Bit 2 */ - -#include "ch32v10x_conf.h" - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/14 + * Description : CH32V10x Device Peripheral Access Layer Header File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V10x_H +#define __CH32V10x_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ + +/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x500) /* Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ + +/* CH32V10x Standard Peripheral Library version number */ +#define __CH32V10x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */ +#define __CH32V10x_STDPERIPH_VERSION_SUB (0x06) /* [7:0] sub version */ +#define __CH32V10x_STDPERIPH_VERSION ( (__CH32V10x_STDPERIPH_VERSION_MAIN << 8)\ + |(__CH32V10x_STDPERIPH_VERSION_SUB << 0)) + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 4 Exception Interrupt */ + SysTicK_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 global Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 58, /* USB WakeUp from suspend through EXTI Line Interrupt */ + USBFS_IRQn = 59, /* USBFS Interrupt */ + +} IRQn_Type; + +#define USBHD_IRQn USBFS_IRQn +#define USBHD_IRQHandler USBFS_IRQHandler + +#define HardFault_IRQn EXC_IRQn +#define ADC1_2_IRQn ADC_IRQn + +#include +#include "core_riscv.h" +#include "system_ch32v10x.h" + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13[5]; + __IO uint16_t DATAR11; + uint16_t RESERVED14; + __IO uint16_t DATAR12; + uint16_t RESERVED15; + __IO uint16_t DATAR13; + uint16_t RESERVED16; + __IO uint16_t DATAR14; + uint16_t RESERVED17; + __IO uint16_t DATAR15; + uint16_t RESERVED18; + __IO uint16_t DATAR16; + uint16_t RESERVED19; + __IO uint16_t DATAR17; + uint16_t RESERVED20; + __IO uint16_t DATAR18; + uint16_t RESERVED21; + __IO uint16_t DATAR19; + uint16_t RESERVED22; + __IO uint16_t DATAR20; + uint16_t RESERVED23; + __IO uint16_t DATAR21; + uint16_t RESERVED24; + __IO uint16_t DATAR22; + uint16_t RESERVED25; + __IO uint16_t DATAR23; + uint16_t RESERVED26; + __IO uint16_t DATAR24; + uint16_t RESERVED27; + __IO uint16_t DATAR25; + uint16_t RESERVED28; + __IO uint16_t DATAR26; + uint16_t RESERVED29; + __IO uint16_t DATAR27; + uint16_t RESERVED30; + __IO uint16_t DATAR28; + uint16_t RESERVED31; + __IO uint16_t DATAR29; + uint16_t RESERVED32; + __IO uint16_t DATAR30; + uint16_t RESERVED33; + __IO uint16_t DATAR31; + uint16_t RESERVED34; + __IO uint16_t DATAR32; + uint16_t RESERVED35; + __IO uint16_t DATAR33; + uint16_t RESERVED36; + __IO uint16_t DATAR34; + uint16_t RESERVED37; + __IO uint16_t DATAR35; + uint16_t RESERVED38; + __IO uint16_t DATAR36; + uint16_t RESERVED39; + __IO uint16_t DATAR37; + uint16_t RESERVED40; + __IO uint16_t DATAR38; + uint16_t RESERVED41; + __IO uint16_t DATAR39; + uint16_t RESERVED42; + __IO uint16_t DATAR40; + uint16_t RESERVED43; + __IO uint16_t DATAR41; + uint16_t RESERVED44; + __IO uint16_t DATAR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + +/* Digital to Analog Converter */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SWTR; + __IO uint32_t R12BDHR1; + __IO uint32_t L12BDHR1; + __IO uint32_t R8BDHR1; + __IO uint32_t R12BDHR2; + __IO uint32_t L12BDHR2; + __IO uint32_t R8BDHR2; + __IO uint32_t RD12BDHR; + __IO uint32_t LD12BDHR; + __IO uint32_t RD8BDHR; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + +/* Debug MCU */ +typedef struct +{ + __IO uint32_t CFGR0; + __IO uint32_t CFGR1; +} DBGMCU_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DMACFGR; + uint16_t RESERVED18; + __IO uint16_t DMAADR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ +#define DBGMCU_BASE ((uint32_t)0xE000D000) +#define EXTEN_BASE ((uint32_t)0x40023800) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define TIM5 ((TIM_TypeDef *)TIM5_BASE) +#define TIM6 ((TIM_TypeDef *)TIM6_BASE) +#define TIM7 ((TIM_TypeDef *)TIM7_BASE) +#define TIM12 ((TIM_TypeDef *)TIM12_BASE) +#define TIM13 ((TIM_TypeDef *)TIM13_BASE) +#define TIM14 ((TIM_TypeDef *)TIM14_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define SPI3 ((SPI_TypeDef *)SPI3_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define UART4 ((USART_TypeDef *)UART4_BASE) +#define UART5 ((USART_TypeDef *)UART5_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define DAC ((DAC_TypeDef *)DAC_BASE) +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define TIM8 ((TIM_TypeDef *)TIM8_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define ADC3 ((ADC_TypeDef *)ADC3_BASE) +#define TIM15 ((TIM_TypeDef *)TIM15_BASE) +#define TIM16 ((TIM_TypeDef *)TIM16_BASE) +#define TIM17 ((TIM_TypeDef *)TIM17_BASE) +#define TIM9 ((TIM_TypeDef *)TIM9_BASE) +#define TIM10 ((TIM_TypeDef *)TIM10_BASE) +#define TIM11 ((TIM_TypeDef *)TIM11_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR11 register *******************/ +#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR12 register *******************/ +#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR13 register *******************/ +#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR14 register *******************/ +#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR15 register *******************/ +#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR16 register *******************/ +#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR17 register *******************/ +#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_DATAR18 register ********************/ +#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR19 register *******************/ +#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR20 register *******************/ +#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR21 register *******************/ +#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR22 register *******************/ +#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR23 register *******************/ +#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR24 register *******************/ +#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR25 register *******************/ +#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR26 register *******************/ +#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR27 register *******************/ +#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR28 register *******************/ +#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR29 register *******************/ +#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR30 register *******************/ +#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR31 register *******************/ +#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR32 register *******************/ +#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR33 register *******************/ +#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR34 register *******************/ +#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR35 register *******************/ +#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR36 register *******************/ +#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR37 register *******************/ +#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR38 register *******************/ +#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR39 register *******************/ +#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR40 register *******************/ +#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR41 register *******************/ +#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR42 register *******************/ +#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + +/******************************************************************************/ +/* Digital to Analog Converter */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CTLR register ********************/ +#define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */ +#define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */ +#define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */ + +#define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */ +#define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */ + +#define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */ +#define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */ +#define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */ +#define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */ + +#define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */ +#define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */ +#define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */ + +#define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */ + +#define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTR register ******************/ +#define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */ +#define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */ + +/***************** Bit definition for DAC_R12BDHR1 register ******************/ +#define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR1 register ******************/ +#define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR1 register ******************/ +#define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_R12BDHR2 register ******************/ +#define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR2 register ******************/ +#define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR2 register ******************/ +#define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_RD12BDHR register ******************/ +#define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ +#define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_LD12BDHR register ******************/ +#define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ +#define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_RD8BDHR register ******************/ +#define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */ +#define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + +#define FLASH_ACTLR_HLFCYA ((uint8_t)0x08) /* Flash Half Cycle Access Enable */ +#define FLASH_ACTLR_PRFTBE ((uint8_t)0x10) /* Prefetch Buffer Enable */ +#define FLASH_ACTLR_PRFTBS ((uint8_t)0x20) /* Prefetch Buffer Status */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG ((uint16_t)0x0001) /* Programming */ +#define FLASH_CTLR_PER ((uint16_t)0x0002) /* Page Erase */ +#define FLASH_CTLR_MER ((uint16_t)0x0004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG ((uint16_t)0x0010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint16_t)0x0020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint16_t)0x0040) /* Start */ +#define FLASH_CTLR_LOCK ((uint16_t)0x0080) /* Lock */ +#define FLASH_CTLR_OPTWRE ((uint16_t)0x0200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint16_t)0x0400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint16_t)0x1000) /* End of operation interrupt enable */ +#define FLASH_CTLR_PAGE_PG ((uint16_t)0x00010000) /* Page Programming 128Byte */ +#define FLASH_CTLR_PAGE_ER ((uint16_t)0x00020000) /* Page Erase 128Byte */ +#define FLASH_CTLR_BUF_LOAD ((uint16_t)0x00040000) /* Buffer Load */ +#define FLASH_CTLR_BUF_RST ((uint16_t)0x00080000) /* Buffer Reset */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /* BFB2 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ +#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) +#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080) +#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0) +#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0) +#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0) + +#define PWR_CTLR_PLS_2V2 PWR_CTLR_PLS_MODE0 +#define PWR_CTLR_PLS_2V3 PWR_CTLR_PLS_MODE1 +#define PWR_CTLR_PLS_2V4 PWR_CTLR_PLS_MODE2 +#define PWR_CTLR_PLS_2V5 PWR_CTLR_PLS_MODE3 +#define PWR_CTLR_PLS_2V6 PWR_CTLR_PLS_MODE4 +#define PWR_CTLR_PLS_2V7 PWR_CTLR_PLS_MODE5 +#define PWR_CTLR_PLS_2V8 PWR_CTLR_PLS_MODE6 +#define PWR_CTLR_PLS_2V9 PWR_CTLR_PLS_MODE7 + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ +#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ + +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ + +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ + +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ + +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ + +#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ +#define RCC_FLITFEN ((uint16_t)0x0010) /* FLITF clock enable */ +#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ +#define RCC_USBHD ((uint16_t)0x1000) + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ + +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ + +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ + +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */ +#define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */ +#define RCC_RTCSEL_HSE ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCH register *******************/ +#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ +#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ +#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */ +#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */ +#define EXTEN_USBFS_IO_EN ((uint32_t)0x00000004) /* Bit 2 */ +#define EXTEN_USB_5V_SEL ((uint32_t)0x00000008) /* Bit 3 */ +#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ +#define EXTEN_USBHD_IO_EN EXTEN_USBFS_IO_EN + +#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */ +#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ +#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define EXTEN_IDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */ +#define EXTEN_WRITE_EN ((uint32_t)0x00004000) /* Bit 14 */ +#define EXTEN_SHORT_WAKE ((uint32_t)0x00008000) /* Bit 15 */ + +#define EXTEN_FLASH_CLK_TRIM ((uint32_t)0x00070000) /* FLASH_CLK_TRIM[2:0] bits */ +#define EXTEN_FLASH_CLK_TRIM0 ((uint32_t)0x00010000) /* Bit 0 */ +#define EXTEN_FLASH_CLK_TRIM1 ((uint32_t)0x00020000) /* Bit 1 */ +#define EXTEN_FLASH_CLK_TRIM2 ((uint32_t)0x00040000) /* Bit 2 */ + +#include "ch32v10x_conf.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_adc.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_adc.h index bfdbc8d..15fac0e 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_adc.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_adc.h @@ -1,190 +1,190 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_adc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the - * ADC firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V10x_ADC_H -#define __CH32V10x_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* ADC Init structure definition */ -typedef struct -{ - uint32_t ADC_Mode; /* Configures the ADC to operate in independent or - dual mode. - This parameter can be a value of @ref ADC_mode */ - - FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in - Scan (multichannels) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ -} ADC_InitTypeDef; - -/* ADC_mode */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) -#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) -#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) -#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) -#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) -#define ADC_Mode_RegSimult ((uint32_t)0x00060000) -#define ADC_Mode_FastInterl ((uint32_t)0x00070000) -#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) -#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) - -/* ADC_external_trigger_sources_for_regular_channels_conversion */ -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) - -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) - -/* ADC_data_align */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) - -/* ADC_channels */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) - -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) - -/* ADC_sampling_time */ -#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) -#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) -#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) -#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) -#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) -#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) -#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) -#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) - -/* ADC_external_trigger_sources_for_injected_channels_conversion */ -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) -#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) - -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) - -/* ADC_injected_channel_selection */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) - -/* ADC_analog_watchdog_selection */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -/* ADC_interrupts_definition */ -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) - -/* ADC_flags_definition */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) - -void ADC_DeInit(ADC_TypeDef *ADCx); -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); -void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); -void ADC_ResetCalibration(ADC_TypeDef *ADCx); -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); -void ADC_StartCalibration(ADC_TypeDef *ADCx); -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); -void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); -uint32_t ADC_GetDualModeConversionValue(void); -void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); -void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); -void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); -s32 TempSensor_Volt_To_Temper(s32 Value); -int16_t Get_CalibrationValue(ADC_TypeDef *ADCx); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V10x_ADC_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_adc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the + * ADC firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V10x_ADC_H +#define __CH32V10x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +} ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +/* ADC_sampling_time */ +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +void ADC_DeInit(ADC_TypeDef *ADCx); +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_StartCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); +s32 TempSensor_Volt_To_Temper(s32 Value); +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V10x_ADC_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_bkp.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_bkp.h index e7c30aa..59bd6e0 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_bkp.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_bkp.h @@ -1,93 +1,93 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_bkp.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the - * BKP firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V10x_BKP_H -#define __CH32V10x_BKP_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* Tamper_Pin_active_level */ -#define BKP_TamperPinLevel_High ((uint16_t)0x0000) -#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) - -/* RTC_output_source_to_output_on_the_Tamper_pin */ -#define BKP_RTCOutputSource_None ((uint16_t)0x0000) -#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) -#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) -#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) - -/* Data_Backup_Register */ -#define BKP_DR1 ((uint16_t)0x0004) -#define BKP_DR2 ((uint16_t)0x0008) -#define BKP_DR3 ((uint16_t)0x000C) -#define BKP_DR4 ((uint16_t)0x0010) -#define BKP_DR5 ((uint16_t)0x0014) -#define BKP_DR6 ((uint16_t)0x0018) -#define BKP_DR7 ((uint16_t)0x001C) -#define BKP_DR8 ((uint16_t)0x0020) -#define BKP_DR9 ((uint16_t)0x0024) -#define BKP_DR10 ((uint16_t)0x0028) -#define BKP_DR11 ((uint16_t)0x0040) -#define BKP_DR12 ((uint16_t)0x0044) -#define BKP_DR13 ((uint16_t)0x0048) -#define BKP_DR14 ((uint16_t)0x004C) -#define BKP_DR15 ((uint16_t)0x0050) -#define BKP_DR16 ((uint16_t)0x0054) -#define BKP_DR17 ((uint16_t)0x0058) -#define BKP_DR18 ((uint16_t)0x005C) -#define BKP_DR19 ((uint16_t)0x0060) -#define BKP_DR20 ((uint16_t)0x0064) -#define BKP_DR21 ((uint16_t)0x0068) -#define BKP_DR22 ((uint16_t)0x006C) -#define BKP_DR23 ((uint16_t)0x0070) -#define BKP_DR24 ((uint16_t)0x0074) -#define BKP_DR25 ((uint16_t)0x0078) -#define BKP_DR26 ((uint16_t)0x007C) -#define BKP_DR27 ((uint16_t)0x0080) -#define BKP_DR28 ((uint16_t)0x0084) -#define BKP_DR29 ((uint16_t)0x0088) -#define BKP_DR30 ((uint16_t)0x008C) -#define BKP_DR31 ((uint16_t)0x0090) -#define BKP_DR32 ((uint16_t)0x0094) -#define BKP_DR33 ((uint16_t)0x0098) -#define BKP_DR34 ((uint16_t)0x009C) -#define BKP_DR35 ((uint16_t)0x00A0) -#define BKP_DR36 ((uint16_t)0x00A4) -#define BKP_DR37 ((uint16_t)0x00A8) -#define BKP_DR38 ((uint16_t)0x00AC) -#define BKP_DR39 ((uint16_t)0x00B0) -#define BKP_DR40 ((uint16_t)0x00B4) -#define BKP_DR41 ((uint16_t)0x00B8) -#define BKP_DR42 ((uint16_t)0x00BC) - -void BKP_DeInit(void); -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); -void BKP_TamperPinCmd(FunctionalState NewState); -void BKP_ITConfig(FunctionalState NewState); -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); -FlagStatus BKP_GetFlagStatus(void); -void BKP_ClearFlag(void); -ITStatus BKP_GetITStatus(void); -void BKP_ClearITPendingBit(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_BKP_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_bkp.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the + * BKP firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V10x_BKP_H +#define __CH32V10x_BKP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* Tamper_Pin_active_level */ +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) + +/* RTC_output_source_to_output_on_the_Tamper_pin */ +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) + +/* Data_Backup_Register */ +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_BKP_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_crc.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_crc.h index 8fa3464..560d1e2 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_crc.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_crc.h @@ -1,33 +1,33 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_crc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the - * CRC firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V10x_CRC_H -#define __CH32V10x_CRC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_CRC_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_crc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the + * CRC firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V10x_CRC_H +#define __CH32V10x_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_CRC_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_dbgmcu.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_dbgmcu.h index d7a9119..059692b 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_dbgmcu.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_dbgmcu.h @@ -1,47 +1,47 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_dbgmcu.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the - * DBGMCU firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V10x_DBGMCU_H -#define __CH32V10x_DBGMCU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* CFGR0 Register */ -#define DBGMCU_IWDG_STOP ((uint32_t)0x00000001) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000002) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000004) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000008) -#define DBGMCU_TIM1_STOP ((uint32_t)0x00000010) -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000020) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00000040) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00000080) - -/* CFGR1 Register */ -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) - - -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -uint32_t DBGMCU_GetCHIPID( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_DBGMCU_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_dbgmcu.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the + * DBGMCU firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V10x_DBGMCU_H +#define __CH32V10x_DBGMCU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* CFGR0 Register */ +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000001) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000002) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000004) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000008) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000010) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000020) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00000040) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00000080) + +/* CFGR1 Register */ +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) + + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +uint32_t DBGMCU_GetCHIPID( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_DBGMCU_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_dma.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_dma.h index cf6fbf4..fc3689b 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_dma.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_dma.h @@ -1,218 +1,218 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_dma.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the - * DMA firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_DMA_H -#define __CH32V10x_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* DMA Init structure definition */ -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode. - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -} DMA_InitTypeDef; - -/* DMA_data_transfer_direction */ -#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) - -/* DMA_peripheral_incremented_mode */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) - -/* DMA_memory_incremented_mode */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) - -/* DMA_peripheral_data_size */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) - -/* DMA_memory_data_size */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) - -/* DMA_circular_normal_mode */ -#define DMA_Mode_Circular ((uint32_t)0x00000020) -#define DMA_Mode_Normal ((uint32_t)0x00000000) - -/* DMA_priority_level */ -#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) -#define DMA_Priority_High ((uint32_t)0x00002000) -#define DMA_Priority_Medium ((uint32_t)0x00001000) -#define DMA_Priority_Low ((uint32_t)0x00000000) - -/* DMA_memory_to_memory */ -#define DMA_M2M_Enable ((uint32_t)0x00004000) -#define DMA_M2M_Disable ((uint32_t)0x00000000) - -/* DMA_interrupts_definition */ -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) - -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) - -#define DMA2_IT_GL1 ((uint32_t)0x10000001) -#define DMA2_IT_TC1 ((uint32_t)0x10000002) -#define DMA2_IT_HT1 ((uint32_t)0x10000004) -#define DMA2_IT_TE1 ((uint32_t)0x10000008) -#define DMA2_IT_GL2 ((uint32_t)0x10000010) -#define DMA2_IT_TC2 ((uint32_t)0x10000020) -#define DMA2_IT_HT2 ((uint32_t)0x10000040) -#define DMA2_IT_TE2 ((uint32_t)0x10000080) -#define DMA2_IT_GL3 ((uint32_t)0x10000100) -#define DMA2_IT_TC3 ((uint32_t)0x10000200) -#define DMA2_IT_HT3 ((uint32_t)0x10000400) -#define DMA2_IT_TE3 ((uint32_t)0x10000800) -#define DMA2_IT_GL4 ((uint32_t)0x10001000) -#define DMA2_IT_TC4 ((uint32_t)0x10002000) -#define DMA2_IT_HT4 ((uint32_t)0x10004000) -#define DMA2_IT_TE4 ((uint32_t)0x10008000) -#define DMA2_IT_GL5 ((uint32_t)0x10010000) -#define DMA2_IT_TC5 ((uint32_t)0x10020000) -#define DMA2_IT_HT5 ((uint32_t)0x10040000) -#define DMA2_IT_TE5 ((uint32_t)0x10080000) - -/* DMA_flags_definition */ -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) - -#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) -#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) -#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) -#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) -#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) -#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) -#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) -#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) -#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) -#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) -#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) -#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) -#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) -#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) -#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) -#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) -#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) -#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) -#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) -#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) - -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); -void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); -void DMA_ClearFlag(uint32_t DMAy_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMAy_IT); -void DMA_ClearITPendingBit(uint32_t DMAy_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V10x_DMA_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_dma.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the + * DMA firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_DMA_H +#define __CH32V10x_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) + +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V10x_DMA_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_exti.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_exti.h index 48f325b..587a899 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_exti.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_exti.h @@ -1,88 +1,88 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_exti.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the - * EXTI firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_EXTI_H -#define __CH32V10x_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* EXTI mode enumeration */ -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -} EXTIMode_TypeDef; - -/* EXTI Trigger enumeration */ -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -} EXTITrigger_TypeDef; - -/* EXTI Init Structure definition */ -typedef struct -{ - uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -} EXTI_InitTypeDef; - -/* EXTI_Lines */ -#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) -#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the USBHD Wakeup event */ - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_EXTI_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_exti.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/30 + * Description : This file contains all the functions prototypes for the + * EXTI firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_EXTI_H +#define __CH32V10x_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitTypeDef; + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) +#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the USBFS Wakeup event */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_EXTI_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_flash.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_flash.h index 54e3c7b..a6c44d2 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_flash.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_flash.h @@ -1,157 +1,162 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_flash.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the FLASH - * firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_FLASH_H -#define __CH32V10x_FLASH_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* FLASH Status */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT -} FLASH_Status; - -/* Flash_Latency */ -#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ - -/* Half_Cycle_Enable_Disable */ -#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */ -#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */ - -/* Prefetch_Buffer_Enable_Disable */ -#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */ -#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */ - -/* Values to be used with CH32V10x Low and Medium density devices */ -#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 3 */ -#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 4 to 7 */ -#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 8 to 11 */ -#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 12 to 15 */ -#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 16 to 19 */ -#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 20 to 23 */ -#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 24 to 27 */ -#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 28 to 31 */ - -/* Values to be used with CH32V10x Medium-density devices */ -#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 32 to 35 */ -#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 36 to 39 */ -#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 40 to 43 */ -#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 44 to 47 */ -#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 48 to 51 */ -#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 52 to 55 */ -#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 56 to 59 */ -#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 60 to 63 */ -#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /* CH32 Medium-density devices: Write protection of page 64 to 67 */ -#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /* CH32 Medium-density devices: Write protection of page 68 to 71 */ -#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /* CH32 Medium-density devices: Write protection of page 72 to 75 */ -#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /* CH32 Medium-density devices: Write protection of page 76 to 79 */ -#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /* CH32 Medium-density devices: Write protection of page 80 to 83 */ -#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /* CH32 Medium-density devices: Write protection of page 84 to 87 */ -#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /* CH32 Medium-density devices: Write protection of page 88 to 91 */ -#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /* CH32 Medium-density devices: Write protection of page 92 to 95 */ -#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /* CH32 Medium-density devices: Write protection of page 96 to 99 */ -#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /* CH32 Medium-density devices: Write protection of page 100 to 103 */ -#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /* CH32 Medium-density devices: Write protection of page 104 to 107 */ -#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /* CH32 Medium-density devices: Write protection of page 108 to 111 */ -#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /* CH32 Medium-density devices: Write protection of page 112 to 115 */ -#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /* CH32 Medium-density devices: Write protection of page 115 to 119 */ -#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /* CH32 Medium-density devices: Write protection of page 120 to 123 */ -#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 124 to 127 */ - -#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 62 to 255 */ - -#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ - -/* Option_Bytes_IWatchdog */ -#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ -#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ - -/* Option_Bytes_nRST_STOP */ -#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ - -/* Option_Bytes_nRST_STDBY */ -#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ - -/* FLASH_Interrupts */ -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ - -/* FLASH_Flags */ -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ -#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /* FLASH BANK1 Program error flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ - -/*Functions used for all CH32V10x devices*/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); -uint32_t FLASH_GetUserOptionByte(void); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -FlagStatus FLASH_GetPrefetchBufferStatus(void); -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); -void FLASH_Unlock_Fast(void); -void FLASH_Lock_Fast(void); -void FLASH_BufReset(void); -void FLASH_BufLoad(uint32_t Address, uint32_t Data0, uint32_t Data1, uint32_t Data2, uint32_t Data3); -void FLASH_ErasePage_Fast(uint32_t Page_Address); -void FLASH_ProgramPage_Fast(uint32_t Page_Address); - -/* New function used for all CH32V10x devices */ -void FLASH_UnlockBank1(void); -void FLASH_LockBank1(void); -FLASH_Status FLASH_EraseAllBank1Pages(void); -FLASH_Status FLASH_GetBank1Status(void); -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_FLASH_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_flash.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the FLASH + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_FLASH_H +#define __CH32V10x_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ + +/* Half_Cycle_Enable_Disable */ +#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */ + +/* Prefetch_Buffer_Enable_Disable */ +#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */ + +/* Values to be used with CH32V10x Low and Medium density devices */ +#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 28 to 31 */ + +/* Values to be used with CH32V10x Medium-density devices */ +#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /* CH32 Medium-density devices: Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /* CH32 Medium-density devices: Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /* CH32 Medium-density devices: Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /* CH32 Medium-density devices: Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /* CH32 Medium-density devices: Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /* CH32 Medium-density devices: Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /* CH32 Medium-density devices: Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /* CH32 Medium-density devices: Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /* CH32 Medium-density devices: Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /* CH32 Medium-density devices: Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /* CH32 Medium-density devices: Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /* CH32 Medium-density devices: Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /* CH32 Medium-density devices: Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /* CH32 Medium-density devices: Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /* CH32 Medium-density devices: Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 124 to 127 */ + +#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 62 to 255 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /* FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/*Functions used for all CH32V10x devices*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_BufReset(void); +void FLASH_BufLoad(uint32_t Address, uint32_t Data0, uint32_t Data1, uint32_t Data2, uint32_t Data3); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address); + +/* New function used for all CH32V10x devices */ +void FLASH_UnlockBank1(void); +void FLASH_LockBank1(void); +FLASH_Status FLASH_EraseAllBank1Pages(void); +FLASH_Status FLASH_GetBank1Status(void); +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_FLASH_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_gpio.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_gpio.h index adc89b6..544be33 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_gpio.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_gpio.h @@ -1,160 +1,160 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_gpio.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the - * GPIO firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_GPIO_H -#define __CH32V10x_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* Output Maximum frequency selection */ -typedef enum -{ - GPIO_Speed_10MHz = 1, - GPIO_Speed_2MHz, - GPIO_Speed_50MHz -} GPIOSpeed_TypeDef; - -/* Configuration Mode enumeration */ -typedef enum -{ - GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 -} GPIOMode_TypeDef; - -/* GPIO Init structure definition */ -typedef struct -{ - uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -} GPIO_InitTypeDef; - -/* Bit_SET and Bit_RESET enumeration */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -} BitAction; - -/* GPIO_pins_define */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - -/* GPIO_Remap_define */ -#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ -#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ -#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping */ -#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ -#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ -#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ -#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ -#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ -#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ -#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ -#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \ - to TIM2 Internal Trigger 1 for calibration \ - (only for Connectivity line devices) */ -#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /* TIM1 DMA requests mapping (only for Value line devices) */ -#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /* TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ -#define GPIO_Remap_MISC ((uint32_t)0x80002000) /* Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, \ - only for High density Value line devices) */ - -/* GPIO_Port_Sources */ -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOB ((uint8_t)0x01) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) -#define GPIO_PortSourceGPIOD ((uint8_t)0x03) -#define GPIO_PortSourceGPIOE ((uint8_t)0x04) -#define GPIO_PortSourceGPIOF ((uint8_t)0x05) -#define GPIO_PortSourceGPIOG ((uint8_t)0x06) - -/* GPIO_Pin_sources */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -void GPIO_DeInit(GPIO_TypeDef *GPIOx); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_EventOutputCmd(FunctionalState NewState); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_GPIO_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_gpio.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/30 + * Description : This file contains all the functions prototypes for the + * GPIO firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_GPIO_H +#define __CH32V10x_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; + +/* Configuration Mode enumeration */ +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +} GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \ + to TIM2 Internal Trigger 1 for calibration \ + (only for Connectivity line devices) */ +#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /* TIM1 DMA requests mapping (only for Value line devices) */ +#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /* TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ +#define GPIO_Remap_MISC ((uint32_t)0x80002000) /* Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, \ + only for High density Value line devices) */ + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +void GPIO_DeInit(GPIO_TypeDef *GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_GPIO_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_i2c.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_i2c.h index ad2baba..03ed67b 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_i2c.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_i2c.h @@ -1,429 +1,429 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_i2c.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the - * I2C firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_I2C_H -#define __CH32V10x_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* I2C Init structure definition */ -typedef struct -{ - uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /* Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /* Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /* Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -} I2C_InitTypeDef; - -/* I2C_mode */ -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) - -/* I2C_duty_cycle_in_fast_mode */ -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ - -/* I2C_acknowledgement */ -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) - -/* I2C_transfer_direction */ -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) - -/* I2C_acknowledged_address */ -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) - -/* I2C_registers */ -#define I2C_Register_CTLR1 ((uint8_t)0x00) -#define I2C_Register_CTLR2 ((uint8_t)0x04) -#define I2C_Register_OADDR1 ((uint8_t)0x08) -#define I2C_Register_OADDR2 ((uint8_t)0x0C) -#define I2C_Register_DATAR ((uint8_t)0x10) -#define I2C_Register_STAR1 ((uint8_t)0x14) -#define I2C_Register_STAR2 ((uint8_t)0x18) -#define I2C_Register_CKCFGR ((uint8_t)0x1C) -#define I2C_Register_RTR ((uint8_t)0x20) - -/* I2C_SMBus_alert_pin_level */ -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) - -/* I2C_PEC_position */ -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) - -/* I2C_NACK_position */ -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) - -/* I2C_interrupts_definition */ -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) - -/* I2C_interrupts_definition */ -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -/* SR2 register flags */ -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/* SR1 register flags */ -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -/****************I2C Master Events (Events grouped in order of communication)********************/ - -/******************************************************************************************************************** - * @brief Start communicate - * - * After master use I2C_GenerateSTART() function sending the START condition,the master - * has to wait for event 5(the Start condition has been correctly - * released on the I2C bus ). - * - */ -/* EVT5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/******************************************************************************************************************** - * @brief Address Acknowledge - * - * When start condition correctly released on the bus(check EVT5), the - * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate - * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will be set: - * - * - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (after generating the START - * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. - * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent - * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part - * of the 10-bit address (LSB) . Then master should wait for event 6. - * - * - */ - -/* EVT6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/*EVT9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/******************************************************************************************************************** - * @brief Communication events - * - * If START condition has generated and slave address - * been acknowledged. then the master has to check one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EVT7 then use - * I2C_ReceiveData() function to read the data received from the slave . - * - * 2) Master Transmitter mode: The master use I2C_SendData() function to send data - * then to wait on event EVT8 or EVT8_2. - * These two events are similar: - * - EVT8 means that the data has been written in the data register and is - * being shifted out. - * - EVT8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EVT8 is sufficient for the application. - * Using EVT8_2 will leads to a slower communication speed but will more reliable . - * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission - * - * - * Note: - * In case the user software does not guarantee that this event EVT7 is managed before - * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. - * - * - */ - -/* Master Receive mode */ -/* EVT7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master Transmitter mode*/ -/* EVT8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* EVT8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - -/******************I2C Slave Events (Events grouped in order of communication)******************/ - -/******************************************************************************************************************** - * @brief Start Communicate events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a start condition of master device generate on the bus. - * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. - * - * - * - * a) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * b) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * c) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* EVT1 */ -/* a) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* b) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* c) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/******************************************************************************************************************** - * @brief Communication events - * - * Wait on one of these events when EVT1 has already been checked : - * - * - Slave Receiver mode: - * - EVT2--The device is expecting to receive a data byte . - * - EVT4--The device is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EVT3--When a byte has been transmitted by the slave and the Master is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee - * the EVT3 is managed before the current byte end of transfer The second one can optionally - * be used. - * - EVT3_2--When the master sends a NACK to tell slave device that data transmission - * shall end . The slave device has to stop sending - * data bytes and wait a Stop condition from bus. - * - * Note: - * If the user software does not guarantee that the event 2 is - * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time . - * In this case the communication will be slower. - * - */ - -/* Slave Receiver mode*/ -/* EVT2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* EVT4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave Transmitter mode*/ -/* EVT3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/*EVT3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - - -void I2C_DeInit(I2C_TypeDef *I2Cx); -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); -void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); -void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert); -void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); -void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); - - -/***************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * profit the application requirements and constraints: - * - * - * a) First way: - * Using I2C_CheckEvent() function: - * It compares the status registers (STARR1 and STAR2) content to a given event - * (can be the combination of more flags). - * If the current status registers includes the given flags will return SUCCESS. - * and if the current status registers miss flags will returns ERROR. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (CH32V10xRM). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs besides to the monitored error, - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * in corrupted state. it is suggeted to use error interrupts to monitor the error - * events and handle them in IRQ handler. - * - * - * Note: - * The following functions are recommended for error management: : - * - I2C_ITConfig() main function of configure and enable the error interrupts. - * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions - * to determine which error occurred. - * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() - * \ I2C_GenerateStop() will be use to clear the error flag and source, - * and return to correct communication status. - * - * - * b) Second way: - * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. - * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). - * - When to use: - * - * - This function is suitable for the same applications above but it - * don't have the limitations of I2C_GetFlagStatus() function . - * The returned value could be compared to events already defined in the - * library (CH32V10x_i2c.h) or to custom values defined by user. - * - This function can be used to monitor the status of multiple flags simultaneously. - * - Contrary to the I2C_CheckEvent () function, this function can choose the time to - * accept the event according to the user's needs (when all event flags are set and - * no other flags are set, or only when the required flags are set) - * - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * c) Third way: - * Using the function I2C_GetFlagStatus() get the status of - * one single flag . - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed . - * - * - Limitations: - * - Call this function to access the status register. Some flag bits may be cleared. - * - Function may need to be called twice or more in order to monitor one single event. - */ - - - -/********************************************************* - * - * a) Basic state monitoring(First way) - ******************************************************** - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/********************************************************* - * - * b) Advanced state monitoring(Second way:) - ******************************************************** - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/********************************************************* - * - * c) Flag-based state monitoring(Third way) - ********************************************************* - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - -void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V10x_I2C_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_i2c.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the + * I2C firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_I2C_H +#define __CH32V10x_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef *I2Cx); +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); + + +/***************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * profit the application requirements and constraints: + * + * + * a) First way: + * Using I2C_CheckEvent() function: + * It compares the status registers (STARR1 and STAR2) content to a given event + * (can be the combination of more flags). + * If the current status registers includes the given flags will return SUCCESS. + * and if the current status registers miss flags will returns ERROR. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (CH32V10xRM). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs besides to the monitored error, + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * in corrupted state. it is suggeted to use error interrupts to monitor the error + * events and handle them in IRQ handler. + * + * + * Note: + * The following functions are recommended for error management: : + * - I2C_ITConfig() main function of configure and enable the error interrupts. + * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions + * to determine which error occurred. + * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() + * \ I2C_GenerateStop() will be use to clear the error flag and source, + * and return to correct communication status. + * + * + * b) Second way: + * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. + * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). + * - When to use: + * + * - This function is suitable for the same applications above but it + * don't have the limitations of I2C_GetFlagStatus() function . + * The returned value could be compared to events already defined in the + * library (CH32V10x_i2c.h) or to custom values defined by user. + * - This function can be used to monitor the status of multiple flags simultaneously. + * - Contrary to the I2C_CheckEvent () function, this function can choose the time to + * accept the event according to the user's needs (when all event flags are set and + * no other flags are set, or only when the required flags are set) + * + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * c) Third way: + * Using the function I2C_GetFlagStatus() get the status of + * one single flag . + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed . + * + * - Limitations: + * - Call this function to access the status register. Some flag bits may be cleared. + * - Function may need to be called twice or more in order to monitor one single event. + */ + + + +/********************************************************* + * + * a) Basic state monitoring(First way) + ******************************************************** + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/********************************************************* + * + * b) Advanced state monitoring(Second way:) + ******************************************************** + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/********************************************************* + * + * c) Flag-based state monitoring(Third way) + ********************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V10x_I2C_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_iwdg.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_iwdg.h index 112181a..54a4918 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_iwdg.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_iwdg.h @@ -1,50 +1,50 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_iwdg.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the - * IWDG firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_IWDG_H -#define __CH32V10x_IWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* IWDG_WriteAccess */ -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) - -/* IWDG_prescaler */ -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) - -/* IWDG_Flag */ -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) - -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_Enable(void); -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_IWDG_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_iwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the + * IWDG firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_IWDG_H +#define __CH32V10x_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_IWDG_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_misc.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_misc.h index 859a34b..9ff51c5 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_misc.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_misc.h @@ -1,48 +1,74 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_misc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the - * miscellaneous firmware library functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10X_MISC_H -#define __CH32V10X_MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v10x.h" - -/* NVIC Init Structure definition */ -typedef struct -{ - uint8_t NVIC_IRQChannel; - uint8_t NVIC_IRQChannelPreemptionPriority; - uint8_t NVIC_IRQChannelSubPriority; - FunctionalState NVIC_IRQChannelCmd; -} NVIC_InitTypeDef; - - -/* Preemption_Priority_Group */ -#define NVIC_PriorityGroup_0 ((uint32_t)0x00) -#define NVIC_PriorityGroup_1 ((uint32_t)0x01) -#define NVIC_PriorityGroup_2 ((uint32_t)0x02) -#define NVIC_PriorityGroup_3 ((uint32_t)0x03) -#define NVIC_PriorityGroup_4 ((uint32_t)0x04) - - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_MISC_H */ - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_misc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/05 + * Description : This file contains all the functions prototypes for the + * miscellaneous firmware library functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10X_MISC_H +#define __CH32V10X_MISC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* CSR_INTSYSCR_INEST_definition */ +#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(PFIC->CFGR bit1 = 1) */ +#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(PFIC->CFGR bit1 = 0) */ + +/* Check the configuration of PFIC->CFGR + * interrupt nesting enable(PFIC->CFGR bit1 = 0) + * priority - bit[7] - Preemption Priority + * bit[6:4] - Sub priority + * bit[3:0] - Reserve + * interrupt nesting disable(PFIC->CFGR bit1 = 1) + * priority - bit[7:4] - Sub priority + * bit[3:0] - Reserve + */ + +#ifndef INTSYSCR_INEST +#define INTSYSCR_INEST INTSYSCR_INEST_EN +#endif + +/* NVIC Init Structure definition + * interrupt nesting enable(PFIC->CFGR bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + * interrupt nesting disable(PFIC->CFGR bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 0xF. + * + */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Preemption_Priority_Group */ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(PFIC->CFGR bit1 = 1) */ +#else +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(PFIC->CFGR bit1 = 0) */ +#endif + + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_MISC_H */ + diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_pwr.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_pwr.h index ee775ad..2c9bcd7 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_pwr.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_pwr.h @@ -1,63 +1,72 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_pwr.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the PWR - * firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_PWR_H -#define __CH32V10x_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* PVD_detection_level */ -#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) -#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) -#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) -#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) -#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) -#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) -#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) -#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) - -/* Regulator_state_is_STOP_mode */ -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower ((uint32_t)0x00000001) - -/* STOP_mode_entry */ -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) - -/* PWR_Flag */ -#define PWR_FLAG_WU ((uint32_t)0x00000001) -#define PWR_FLAG_SB ((uint32_t)0x00000002) -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) - -/* PWR_VDD_Supply_Voltage */ -typedef enum {PWR_VDD_5V = 0, PWR_VDD_3V3 = !PWR_VDD_5V} PWR_VDD; - -void PWR_DeInit(void); -void PWR_BackupAccessCmd(FunctionalState NewState); -void PWR_PVDCmd(FunctionalState NewState); -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_WakeUpPinCmd(FunctionalState NewState); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); -PWR_VDD PWR_VDD_SupplyVoltage(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_PWR_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_pwr.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/14 + * Description : This file contains all the functions prototypes for the PWR + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_PWR_H +#define __CH32V10x_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* PVD_detection_level */ +#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080) +#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0) + +#define PWR_PVDLevel_2V7 PWR_PVDLevel_MODE0 +#define PWR_PVDLevel_2V9 PWR_PVDLevel_MODE1 +#define PWR_PVDLevel_3V1 PWR_PVDLevel_MODE2 +#define PWR_PVDLevel_3V3 PWR_PVDLevel_MODE3 +#define PWR_PVDLevel_3V5 PWR_PVDLevel_MODE4 +#define PWR_PVDLevel_3V8 PWR_PVDLevel_MODE5 +#define PWR_PVDLevel_4V1 PWR_PVDLevel_MODE6 +#define PWR_PVDLevel_4V4 PWR_PVDLevel_MODE7 + +/* Regulator_state_is_STOP_mode */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + +/* PWR_VDD_Supply_Voltage */ +typedef enum {PWR_VDD_5V = 0, PWR_VDD_3V3 = !PWR_VDD_5V} PWR_VDD; + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); +PWR_VDD PWR_VDD_SupplyVoltage(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_PWR_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_rcc.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_rcc.h index b8dc487..b725e89 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_rcc.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_rcc.h @@ -1,230 +1,231 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_rcc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the RCC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_RCC_H -#define __CH32V10x_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* RCC_Exported_Types */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ - uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ -} RCC_ClocksTypeDef; - -/* HSE_configuration */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00010000) -#define RCC_HSE_Bypass ((uint32_t)0x00040000) - -/* PLL_entry_clock_source */ -#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) -#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) -#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) - -/* PLL_multiplication_factor */ -#define RCC_PLLMul_2 ((uint32_t)0x00000000) -#define RCC_PLLMul_3 ((uint32_t)0x00040000) -#define RCC_PLLMul_4 ((uint32_t)0x00080000) -#define RCC_PLLMul_5 ((uint32_t)0x000C0000) -#define RCC_PLLMul_6 ((uint32_t)0x00100000) -#define RCC_PLLMul_7 ((uint32_t)0x00140000) -#define RCC_PLLMul_8 ((uint32_t)0x00180000) -#define RCC_PLLMul_9 ((uint32_t)0x001C0000) -#define RCC_PLLMul_10 ((uint32_t)0x00200000) -#define RCC_PLLMul_11 ((uint32_t)0x00240000) -#define RCC_PLLMul_12 ((uint32_t)0x00280000) -#define RCC_PLLMul_13 ((uint32_t)0x002C0000) -#define RCC_PLLMul_14 ((uint32_t)0x00300000) -#define RCC_PLLMul_15 ((uint32_t)0x00340000) -#define RCC_PLLMul_16 ((uint32_t)0x00380000) - -/* System_clock_source */ -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) - -/* AHB_clock_source */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) - -/* APB1_APB2_clock_source */ -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00000400) -#define RCC_HCLK_Div4 ((uint32_t)0x00000500) -#define RCC_HCLK_Div8 ((uint32_t)0x00000600) -#define RCC_HCLK_Div16 ((uint32_t)0x00000700) - -/* RCC_Interrupt_source */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) - -/* USB_Device_clock_source */ -#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) -#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) - -/* ADC_clock_source */ -#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) -#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) -#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) -#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) - -/* LSE_configuration */ -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) - -/* RTC_clock_source */ -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) - -/* AHB_peripheral */ -#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) -#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) -#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) -#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) -#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) -#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) -#define RCC_AHBPeriph_USBHD ((uint32_t)0x00001000) - -/* APB2_peripheral */ -#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) -#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) -#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) -#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) -#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) -#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) -#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) -#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) -#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) - -/* APB1_peripheral */ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) -#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) -#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_USB ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) - -/* Clock_source_to_output_on_MCO_pin */ -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) -#define RCC_MCO_HSE ((uint8_t)0x06) -#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) - -/* RCC_Flag */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -/* SysTick_clock_source */ -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) - -void RCC_DeInit(void); -void RCC_HSEConfig(uint32_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCO); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_RCC_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_rcc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/30 + * Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_RCC_H +#define __CH32V10x_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ +} RCC_ClocksTypeDef; + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + +/* PLL_multiplication_factor */ +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) + +/* APB1_APB2_clock_source */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +/* USB_Device_clock_source */ +#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) +#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) +#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) +#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000) +#define RCC_AHBPeriph_USBHD RCC_AHBPeriph_USBFS + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) +#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) +#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_RCC_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_rtc.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_rtc.h index 5b0364a..60be5a5 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_rtc.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_rtc.h @@ -1,53 +1,53 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_rtc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the RTC - * firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_RTC_H -#define __CH32V10x_RTC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* RTC_interrupts_define */ -#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ -#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ -#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ - -/* RTC_interrupts_flags */ -#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ -#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ -#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ -#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ -#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ - -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); -void RTC_EnterConfigMode(void); -void RTC_ExitConfigMode(void); -uint32_t RTC_GetCounter(void); -void RTC_SetCounter(uint32_t CounterValue); -void RTC_SetPrescaler(uint32_t PrescalerValue); -void RTC_SetAlarm(uint32_t AlarmValue); -uint32_t RTC_GetDivider(void); -void RTC_WaitForLastTask(void); -void RTC_WaitForSynchro(void); -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); -void RTC_ClearFlag(uint16_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint16_t RTC_IT); -void RTC_ClearITPendingBit(uint16_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_RTC_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_rtc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the RTC + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_RTC_H +#define __CH32V10x_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* RTC_interrupts_define */ +#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ + +/* RTC_interrupts_flags */ +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_RTC_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_spi.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_spi.h index 7ae3ca2..73ff3f4 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_spi.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_spi.h @@ -1,220 +1,220 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_spi.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the - * SPI firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_SPI_H -#define __CH32V10x_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* SPI Init structure definition */ -typedef struct -{ - uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /* Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /* Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /* Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ -} SPI_InitTypeDef; - -/* I2S Init structure definition */ -typedef struct -{ - uint16_t I2S_Mode; /* Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -} I2S_InitTypeDef; - -/* SPI_data_direction */ -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) - -/* SPI_mode */ -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) - -/* SPI_data_size */ -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) - -/* SPI_Clock_Polarity */ -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) - -/* SPI_Clock_Phase */ -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) - -/* SPI_Slave_Select_management */ -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) - -/* SPI_BaudRate_Prescaler */ -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) - -/* SPI_MSB_LSB_transmission */ -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) - -/* I2S_Mode */ -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) - -/* I2S_Standard */ -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) - -/* I2S_Data_Format */ -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) - -/* I2S_MCLK_Output */ -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) - -/* I2S_Audio_Frequency */ -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -/* I2S_Clock_Polarity */ -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) - -/* SPI_I2S_DMA_transfer_requests */ -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) - -/* SPI_NSS_internal_software_management */ -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) - -/* SPI_CRC_Transmit_Receive */ -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) - -/* SPI_direction_transmit_receive */ -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) - -/* SPI_I2S_interrupts_definition */ -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) -#define I2S_IT_UDR ((uint8_t)0x53) - -/* SPI_I2S_flags_definition */ -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) - -void SPI_I2S_DeInit(SPI_TypeDef *SPIx); -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); -void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); -void SPI_TransmitCRC(SPI_TypeDef *SPIx); -void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); -void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V10x_SPI_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_spi.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the + * SPI firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_SPI_H +#define __CH32V10x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +} SPI_InitTypeDef; + +/* I2S Init structure definition */ +typedef struct +{ + uint16_t I2S_Mode; /* Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +} I2S_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB_transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* I2S_Mode */ +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) + +/* I2S_Standard */ +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) + +/* I2S_Data_Format */ +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) + +/* I2S_MCLK_Output */ +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) + +/* I2S_Audio_Frequency */ +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +/* I2S_Clock_Polarity */ +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + +void SPI_I2S_DeInit(SPI_TypeDef *SPIx); +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); +void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef *SPIx); +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V10x_SPI_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_tim.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_tim.h index 3798a40..17d254d 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_tim.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_tim.h @@ -1,508 +1,508 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_tim.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the - * TIM firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_TIM_H -#define __CH32V10x_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* TIM Time Base Init structure definition */ -typedef struct -{ - uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /* Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint16_t TIM_Period; /* Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /* Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/* TIM Output Compare Init structure definition */ -typedef struct -{ - uint16_t TIM_OCMode; /* Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_state - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /* Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/* TIM Input Capture Init structure definition */ -typedef struct -{ - uint16_t TIM_Channel; /* Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /* Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /* Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/* BDTR structure definition */ -typedef struct -{ - uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. - This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. - This parameter can be a value of @ref Lock_level */ - - uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/* TIM_Output_Compare_and_PWM_modes */ -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) - -/* TIM_One_Pulse_Mode */ -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) - -/* TIM_Channel */ -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -/* TIM_Clock_Division_CKD */ -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) - -/* TIM_Counter_Mode */ -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) - -/* TIM_Output_Compare_Polarity */ -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) - -/* TIM_Output_Compare_N_Polarity */ -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) - -/* TIM_Output_Compare_state */ -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) - -/* TIM_Output_Compare_N_state */ -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) - -/* TIM_Capture_Compare_state */ -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) - -/* TIM_Capture_Compare_N_state */ -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) - -/* Break_Input_enable_disable */ -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) - -/* Break_Polarity */ -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) - -/* TIM_AOE_Bit_Set_Reset */ -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) - -/* Lock_level */ -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) - -/* OSSI_Off_State_Selection_for_Idle_mode_state */ -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) - -/* OSSR_Off_State_Selection_for_Run_mode_state */ -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Idle_State */ -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Output_Compare_N_Idle_State */ -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Input_Capture_Polarity */ -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) - -/* TIM_Input_Capture_Selection */ -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ - -/* TIM_Input_Capture_Prescaler */ -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ - -/* TIM_interrupt_sources */ -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) - -/* TIM_DMA_Base_address */ -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) - -/* TIM_DMA_Burst_Length */ -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) - -/* TIM_DMA_sources */ -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) - -/* TIM_External_Trigger_Prescaler */ -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) - -/* TIM_Internal_Trigger_Selection */ -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) - -/* TIM_TIx_External_Clock_Source */ -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/* TIM_External_Trigger_Polarity */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) - -/* TIM_Prescaler_Reload_Mode */ -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) - -/* TIM_Forced_Action */ -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) - -/* TIM_Encoder_Mode */ -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) - -/* TIM_Event_Source */ -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) - -/* TIM_Update_Source */ -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ - or the setting of UG bit, or an update generation \ - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ - -/* TIM_Output_Compare_Preload_State */ -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Fast_State */ -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Clear_State */ -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) - -/* TIM_Trigger_Output_Source */ -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) - -/* TIM_Slave_Mode */ -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) - -/* TIM_Master_Slave_Mode */ -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) - -/* TIM_Flags */ -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) - -/* TIM_Legacy */ -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers - -void TIM_DeInit(TIM_TypeDef *TIMx); -void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); -void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); -void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_InternalClockConfig(TIM_TypeDef *TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); -void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); -void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); -void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); -void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); -void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); -void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); -void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); -void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); -void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); -void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); -void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); -void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); -uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); -uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V10x_TIM_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_tim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_TIM_H +#define __CH32V10x_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef *TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V10x_TIM_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_usart.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_usart.h index b76037e..74d75cd 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_usart.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_usart.h @@ -1,187 +1,185 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_usart.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the - * USART firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_USART_H -#define __CH32V10x_USART_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* USART Init Structure definition */ -typedef struct -{ - uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /* Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/* USART Clock Init Structure definition */ -typedef struct -{ - uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* USART_Word_Length */ -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -/* USART_Stop_Bits */ -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) - -/* USART_Parity */ -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) - -/* USART_Mode */ -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) - -/* USART_Hardware_Flow_Control */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) - -/* USART_Clock */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) - -/* USART_Clock_Polarity */ -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) - -/* USART_Clock_Phase */ -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) - -/* USART_Last_Bit */ -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) - -/* USART_Interrupt_definition */ -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) - -#define USART_IT_ORE USART_IT_ORE_ER - -/* USART_DMA_Requests */ -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) - -/* USART_WakeUp_methods */ -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) - -/* USART_LIN_Break_Detection_Length */ -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) - -/* USART_IrDA_Low_Power */ -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) - -/* USART_Flags */ -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) - -void USART_DeInit(USART_TypeDef *USARTx); -void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); -void USART_StructInit(USART_InitTypeDef *USART_InitStruct); -void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); -void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); -void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef *USARTx); -void USART_SendBreak(USART_TypeDef *USARTx); -void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); -void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_USART_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_usart.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/30 + * Description : This file contains all the functions prototypes for the + * USART firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_USART_H +#define __CH32V10x_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +void USART_DeInit(USART_TypeDef *USARTx); +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); +void USART_StructInit(USART_InitTypeDef *USART_InitStruct); +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef *USARTx); +void USART_SendBreak(USART_TypeDef *USARTx); +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_USART_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_usb.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_usb.h index 63dd61b..52c6411 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_usb.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_usb.h @@ -1,718 +1,718 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_usb.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the USB - * firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_USB_H -#define __CH32V10x_USB_H - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef NULL - #define NULL 0 -#endif - -#ifndef VOID - #define VOID void -#endif -#ifndef CONST - #define CONST const -#endif -#ifndef BOOL -typedef unsigned char BOOL; -#endif -#ifndef BOOLEAN -typedef unsigned char BOOLEAN; -#endif -#ifndef CHAR -typedef char CHAR; -#endif -#ifndef INT8 -typedef char INT8; -#endif -#ifndef INT16 -typedef short INT16; -#endif -#ifndef INT32 -typedef long INT32; -#endif -#ifndef UINT8 -typedef unsigned char UINT8; -#endif -#ifndef UINT16 -typedef unsigned short UINT16; -#endif -#ifndef UINT32 -typedef unsigned long UINT32; -#endif -#ifndef UINT8V -typedef unsigned char volatile UINT8V; -#endif -#ifndef UINT16V -typedef unsigned short volatile UINT16V; -#endif -#ifndef UINT32V -typedef unsigned long volatile UINT32V; -#endif - -#ifndef PVOID -typedef void *PVOID; -#endif -#ifndef PCHAR -typedef char *PCHAR; -#endif -#ifndef PCHAR -typedef const char *PCCHAR; -#endif -#ifndef PINT8 -typedef char *PINT8; -#endif -#ifndef PINT16 -typedef short *PINT16; -#endif -#ifndef PINT32 -typedef long *PINT32; -#endif -#ifndef PUINT8 -typedef unsigned char *PUINT8; -#endif -#ifndef PUINT16 -typedef unsigned short *PUINT16; -#endif -#ifndef PUINT32 -typedef unsigned long *PUINT32; -#endif -#ifndef PUINT8V -typedef volatile unsigned char *PUINT8V; -#endif -#ifndef PUINT16V -typedef volatile unsigned short *PUINT16V; -#endif -#ifndef PUINT32V -typedef volatile unsigned long *PUINT32V; -#endif - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* USB */ -#define R32_USB_CONTROL (*((PUINT32V)(0x40023400))) // USB control & interrupt enable & device address -#define R8_USB_CTRL (*((PUINT8V)(0x40023400))) // USB base control -#define RB_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode -#define RB_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps -#define RB_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable -#define RB_UC_SYS_CTRL1 0x20 // USB system control high bit -#define RB_UC_SYS_CTRL0 0x10 // USB system control low bit -#define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control -// bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control -// 0 00: disable USB device and disable internal pullup resistance -// 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance -// 0 1x: enable USB device and enable internal pullup resistance -// 1 00: enable USB host and normal status -// 1 01: enable USB host and force UDP/UDM output SE0 state -// 1 10: enable USB host and force UDP/UDM output J state -// 1 11: enable USB host and force UDP/UDM output resume or K state -#define RB_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid -#define RB_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear -#define RB_UC_CLR_ALL 0x02 // force clear FIFO and count of USB -#define RB_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB - -#define R8_UDEV_CTRL (*((PUINT8V)(0x40023401))) // USB device physical prot control -#define RB_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable -#define RB_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level -#define RB_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level -#define RB_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed -#define RB_UD_GP_BIT 0x02 // general purpose bit -#define RB_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable - -#define R8_UHOST_CTRL R8_UDEV_CTRL // USB host physical prot control -#define RB_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable -#define RB_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level -#define RB_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level -#define RB_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed -#define RB_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset -#define RB_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached - -#define R8_USB_INT_EN (*((PUINT8V)(0x40023402))) // USB interrupt enable -#define RB_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode -#define RB_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode -#define RB_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow -#define RB_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode -#define RB_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event -#define RB_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion -#define RB_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode -#define RB_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode - -#define R8_USB_DEV_AD (*((PUINT8V)(0x40023403))) // USB device address -#define RB_UDA_GP_BIT 0x80 // general purpose bit -#define MASK_USB_ADDR 0x7F // bit mask for USB device address - -#define R32_USB_STATUS (*((PUINT32V)(0x40023404))) // USB miscellaneous status & interrupt flag & interrupt status -#define R8_USB_MIS_ST (*((PUINT8V)(0x40023405))) // USB miscellaneous status -#define RB_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status -#define RB_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host -#define RB_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status -#define RB_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) -#define RB_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status -#define RB_UMS_SUSPEND 0x04 // RO, indicate USB suspend status -#define RB_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host -#define RB_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host - -#define R8_USB_INT_FG (*((PUINT8V)(0x40023406))) // USB interrupt flag -#define RB_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received -#define RB_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK -#define RB_U_SIE_FREE 0x20 // RO, indicate USB SIE free status -#define RB_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear -#define RB_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear -#define RB_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear -#define RB_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear -#define RB_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear -#define RB_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear - -#define R8_USB_INT_ST (*((PUINT8V)(0x40023407))) // USB interrupt status -#define RB_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode -#define RB_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK -#define RB_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode -#define RB_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode -#define MASK_UIS_TOKEN 0x30 // RO, bit mask of current token PID code received for USB device mode -#define UIS_TOKEN_OUT 0x00 -#define UIS_TOKEN_SOF 0x10 -#define UIS_TOKEN_IN 0x20 -#define UIS_TOKEN_SETUP 0x30 -// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode -// 00: OUT token PID received -// 01: SOF token PID received -// 10: IN token PID received -// 11: SETUP token PID received -#define MASK_UIS_ENDP 0x0F // RO, bit mask of current transfer endpoint number for USB device mode -#define MASK_UIS_H_RES 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received - -#define R16_USB_RX_LEN (*((PUINT16V)(0x40023408))) // USB receiving length -#define MASK_UIS_RX_LEN 0x3FF // RO, bit mask of current receive length(10 bits for ch32v10x) -#define R32_USB_BUF_MODE (*((PUINT32V)(0x4002340c))) // USB endpoint buffer mode -#define R8_UEP4_1_MOD (*((PUINT8V)(0x4002340c))) // endpoint 4/1 mode -#define RB_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) -#define RB_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) -#define RB_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 -// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA -// 0 0 x: disable endpoint and disable buffer -// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) -// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes -// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) -// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes -// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes -// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes -#define RB_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) -#define RB_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) -// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA -// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) -// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes -// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes -// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) -// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes - -#define R8_UEP2_3_MOD (*((PUINT8V)(0x4002340d))) // endpoint 2/3 mode -#define RB_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) -#define RB_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) -#define RB_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 -#define RB_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) -#define RB_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) -#define RB_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 - -#define R8_UH_EP_MOD R8_UEP2_3_MOD //host endpoint mode -#define RB_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal -#define RB_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint -// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA -// 0 x: disable endpoint and disable buffer -// 1 0: 64 bytes buffer for transmittal (OUT endpoint) -// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes -#define RB_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving -#define RB_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint -// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA -// 0 x: disable endpoint and disable buffer -// 1 0: 64 bytes buffer for receiving (IN endpoint) -// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes - -#define R8_UEP5_6_MOD (*((PUINT8V)(0x4002340e))) // endpoint 5/6 mode -#define RB_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) -#define RB_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) -#define RB_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 -#define RB_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) -#define RB_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) -#define RB_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 - -#define R8_UEP7_MOD (*((PUINT8V)(0x4002340f))) // endpoint 7 mode -#define RB_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) -#define RB_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) -#define RB_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 - -#define R16_UEP0_DMA (*((PUINT16V)(0x40023410))) // endpoint 0 DMA buffer address -#define R16_UEP1_DMA (*((PUINT16V)(0x40023414))) // endpoint 1 DMA buffer address -#define R16_UEP2_DMA (*((PUINT16V)(0x40023418))) // endpoint 2 DMA buffer address -#define R16_UH_RX_DMA R16_UEP2_DMA // host rx endpoint buffer high address -#define R16_UEP3_DMA (*((PUINT16V)(0x4002341c))) // endpoint 3 DMA buffer address - -#define R16_UEP4_DMA (*((PUINT16V)(0x40023420))) // endpoint 4 DMA buffer address -#define R16_UEP5_DMA (*((PUINT16V)(0x40023424))) // endpoint 5 DMA buffer address -#define R16_UEP6_DMA (*((PUINT16V)(0x40023428))) // endpoint 6 DMA buffer address -#define R16_UEP7_DMA (*((PUINT16V)(0x4002342c))) // endpoint 7 DMA buffer address - -#define R16_UH_TX_DMA R16_UEP3_DMA // host tx endpoint buffer high address -#define R32_USB_EP0_CTRL (*((PUINT32V)(0x40023430))) // endpoint 0 control & transmittal length -#define R8_UEP0_T_LEN (*((PUINT8V)(0x40023430))) // endpoint 0 transmittal length -#define R8_UEP0_CTRL (*((PUINT8V)(0x40023432))) // endpoint 0 control -#define R32_USB_EP1_CTRL (*((PUINT32V)(0x40023434))) // endpoint 1 control & transmittal length -#define R16_UEP1_T_LEN (*((PUINT16V)(0x40023434))) // endpoint 1 transmittal length(16-bits for ch32v10x) -#define R8_UEP1_CTRL (*((PUINT8V)(0x40023436))) // endpoint 1 control -#define RB_UEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 -#define RB_UEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 -#define RB_UEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle -#define RB_UEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT) -#define RB_UEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT) -#define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT) -#define UEP_R_RES_ACK 0x00 -#define UEP_R_RES_TOUT 0x04 -#define UEP_R_RES_NAK 0x08 -#define UEP_R_RES_STALL 0x0C -// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) -// 00: ACK (ready) -// 01: no response, time out to host, for non-zero endpoint isochronous transactions -// 10: NAK (busy) -// 11: STALL (error) -#define RB_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) -#define RB_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) -#define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) -#define UEP_T_RES_ACK 0x00 -#define UEP_T_RES_TOUT 0x01 -#define UEP_T_RES_NAK 0x02 -#define UEP_T_RES_STALL 0x03 -// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) -// 00: DATA0 or DATA1 then expecting ACK (ready) -// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions -// 10: NAK (busy) -// 11: STALL (error) - -#define R8_UH_SETUP R8_UEP1_CTRL // host aux setup -#define RB_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub -#define RB_UH_SOF_EN 0x40 // USB host automatic SOF enable - -#define R32_USB_EP2_CTRL (*((PUINT32V)(0x40023438))) // endpoint 2 control & transmittal length -#define R16_UEP2_T_LEN (*((PUINT16V)(0x40023438))) // endpoint 2 transmittal length(16-bits for ch32v10x) -#define R8_UEP2_CTRL (*((PUINT8V)(0x4002343a))) // endpoint 2 control - -#define R8_UH_EP_PID (*((PUINT8V)(0x40023438))) // host endpoint and PID -#define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer -#define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer - -#define R8_UH_RX_CTRL R8_UEP2_CTRL // host receiver endpoint control -#define RB_UH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 -#define RB_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle -#define RB_UH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions - -#define R32_USB_EP3_CTRL (*((PUINT32V)(0x4002343c))) // endpoint 3 control & transmittal length -#define R16_UEP3_T_LEN (*((PUINT16V)(0x4002343c))) // endpoint 3 transmittal length(16-bits for ch32v10x) -#define R8_UEP3_CTRL (*((PUINT8V)(0x4002343e))) // endpoint 3 control -#define R8_UH_TX_LEN (*((PUINT16V)(0x4002343c))) //R8_UEP3_T_LEN // host transmittal endpoint transmittal length - -#define R8_UH_TX_CTRL R8_UEP3_CTRL // host transmittal endpoint control -#define RB_UH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 -#define RB_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle -#define RB_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions - -#define R32_USB_EP4_CTRL (*((PUINT32V)(0x40023440))) // endpoint 4 control & transmittal length -#define R16_UEP4_T_LEN (*((PUINT16V)(0x40023440))) // endpoint 4 transmittal length(16-bits for ch32v10x) -#define R8_UEP4_CTRL (*((PUINT8V)(0x40023442))) // endpoint 4 control - -#define R32_USB_EP5_CTRL (*((PUINT32V)(0x40023444))) // endpoint 5 control & transmittal length -#define R16_UEP5_T_LEN (*((PUINT16V)(0x40023444))) // endpoint 5 transmittal length(16-bits for ch32v10x) -#define R8_UEP5_CTRL (*((PUINT8V)(0x40023446))) // endpoint 5 control - -#define R32_USB_EP6_CTRL (*((PUINT32V)(0x40023448))) // endpoint 6 control & transmittal length -#define R16_UEP6_T_LEN (*((PUINT16V)(0x40023448))) // endpoint 6 transmittal length(16-bits for ch32v10x) -#define R8_UEP6_CTRL (*((PUINT8V)(0x4002344a))) // endpoint 6 control - -#define R32_USB_EP7_CTRL (*((PUINT32V)(0x4002344c))) // endpoint 7 control & transmittal length -#define R16_UEP7_T_LEN (*((PUINT16V)(0x4002344c))) // endpoint 7 transmittal length(16-bits for ch32v10x) -#define R8_UEP7_CTRL (*((PUINT8V)(0x4002344e))) // endpoint 7 control - -#ifdef __cplusplus -} -#endif - -#endif //__CH32V10x_USB_H - -#ifndef __USB_TYPE__ -#define __USB_TYPE__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* USB constant and structure define */ - -/* USB PID */ -#ifndef USB_PID_SETUP - #define USB_PID_NULL 0x00 /* reserved PID */ - #define USB_PID_SOF 0x05 - #define USB_PID_SETUP 0x0D - #define USB_PID_IN 0x09 - #define USB_PID_OUT 0x01 - #define USB_PID_ACK 0x02 - #define USB_PID_NAK 0x0A - #define USB_PID_STALL 0x0E - #define USB_PID_DATA0 0x03 - #define USB_PID_DATA1 0x0B - #define USB_PID_PRE 0x0C -#endif - -/* USB standard device request code */ -#ifndef USB_GET_DESCRIPTOR - #define USB_GET_STATUS 0x00 - #define USB_CLEAR_FEATURE 0x01 - #define USB_SET_FEATURE 0x03 - #define USB_SET_ADDRESS 0x05 - #define USB_GET_DESCRIPTOR 0x06 - #define USB_SET_DESCRIPTOR 0x07 - #define USB_GET_CONFIGURATION 0x08 - #define USB_SET_CONFIGURATION 0x09 - #define USB_GET_INTERFACE 0x0A - #define USB_SET_INTERFACE 0x0B - #define USB_SYNCH_FRAME 0x0C -#endif - -/* USB hub class request code */ -#ifndef HUB_GET_DESCRIPTOR - #define HUB_GET_STATUS 0x00 - #define HUB_CLEAR_FEATURE 0x01 - #define HUB_GET_STATE 0x02 - #define HUB_SET_FEATURE 0x03 - #define HUB_GET_DESCRIPTOR 0x06 - #define HUB_SET_DESCRIPTOR 0x07 -#endif - -/* USB HID class request code */ -#ifndef HID_GET_REPORT - #define HID_GET_REPORT 0x01 - #define HID_GET_IDLE 0x02 - #define HID_GET_PROTOCOL 0x03 - #define HID_SET_REPORT 0x09 - #define HID_SET_IDLE 0x0A - #define HID_SET_PROTOCOL 0x0B -#endif - -/* USB CDC Class request code */ -#ifndef CDC_GET_LINE_CODING -#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */ -#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ -#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */ -#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */ -#endif - -/* Bit define for USB request type */ -#ifndef USB_REQ_TYP_MASK - #define USB_REQ_TYP_IN 0x80 /* control IN, device to host */ - #define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */ - #define USB_REQ_TYP_READ 0x80 /* control read, device to host */ - #define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */ - #define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */ - #define USB_REQ_TYP_STANDARD 0x00 - #define USB_REQ_TYP_CLASS 0x20 - #define USB_REQ_TYP_VENDOR 0x40 - #define USB_REQ_TYP_RESERVED 0x60 - #define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */ - #define USB_REQ_RECIP_DEVICE 0x00 - #define USB_REQ_RECIP_INTERF 0x01 - #define USB_REQ_RECIP_ENDP 0x02 - #define USB_REQ_RECIP_OTHER 0x03 - #define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 - #define USB_REQ_FEAT_ENDP_HALT 0x00 -#endif - -/* USB request type for hub class request */ -#ifndef HUB_GET_HUB_DESCRIPTOR - #define HUB_CLEAR_HUB_FEATURE 0x20 - #define HUB_CLEAR_PORT_FEATURE 0x23 - #define HUB_GET_BUS_STATE 0xA3 - #define HUB_GET_HUB_DESCRIPTOR 0xA0 - #define HUB_GET_HUB_STATUS 0xA0 - #define HUB_GET_PORT_STATUS 0xA3 - #define HUB_SET_HUB_DESCRIPTOR 0x20 - #define HUB_SET_HUB_FEATURE 0x20 - #define HUB_SET_PORT_FEATURE 0x23 -#endif - -/* Hub class feature selectors */ -#ifndef HUB_PORT_RESET - #define HUB_C_HUB_LOCAL_POWER 0 - #define HUB_C_HUB_OVER_CURRENT 1 - #define HUB_PORT_CONNECTION 0 - #define HUB_PORT_ENABLE 1 - #define HUB_PORT_SUSPEND 2 - #define HUB_PORT_OVER_CURRENT 3 - #define HUB_PORT_RESET 4 - #define HUB_PORT_POWER 8 - #define HUB_PORT_LOW_SPEED 9 - #define HUB_C_PORT_CONNECTION 16 - #define HUB_C_PORT_ENABLE 17 - #define HUB_C_PORT_SUSPEND 18 - #define HUB_C_PORT_OVER_CURRENT 19 - #define HUB_C_PORT_RESET 20 -#endif - -/* USB descriptor type */ -#ifndef USB_DESCR_TYP_DEVICE - #define USB_DESCR_TYP_DEVICE 0x01 - #define USB_DESCR_TYP_CONFIG 0x02 - #define USB_DESCR_TYP_STRING 0x03 - #define USB_DESCR_TYP_INTERF 0x04 - #define USB_DESCR_TYP_ENDP 0x05 - #define USB_DESCR_TYP_QUALIF 0x06 - #define USB_DESCR_TYP_SPEED 0x07 - #define USB_DESCR_TYP_OTG 0x09 - #define USB_DESCR_TYP_HID 0x21 - #define USB_DESCR_TYP_REPORT 0x22 - #define USB_DESCR_TYP_PHYSIC 0x23 - #define USB_DESCR_TYP_CS_INTF 0x24 - #define USB_DESCR_TYP_CS_ENDP 0x25 - #define USB_DESCR_TYP_HUB 0x29 -#endif - -/* USB device class */ -#ifndef USB_DEV_CLASS_HUB - #define USB_DEV_CLASS_RESERVED 0x00 - #define USB_DEV_CLASS_AUDIO 0x01 - #define USB_DEV_CLASS_COMMUNIC 0x02 - #define USB_DEV_CLASS_HID 0x03 - #define USB_DEV_CLASS_MONITOR 0x04 - #define USB_DEV_CLASS_PHYSIC_IF 0x05 - #define USB_DEV_CLASS_IMAGE 0x06 - #define USB_DEV_CLASS_PRINTER 0x07 - #define USB_DEV_CLASS_STORAGE 0x08 - #define USB_DEV_CLASS_HUB 0x09 - #define USB_DEV_CLASS_VEN_SPEC 0xFF -#endif - -/* USB endpoint type and attributes */ -#ifndef USB_ENDP_TYPE_MASK - #define USB_ENDP_DIR_MASK 0x80 - #define USB_ENDP_ADDR_MASK 0x0F - #define USB_ENDP_TYPE_MASK 0x03 - #define USB_ENDP_TYPE_CTRL 0x00 - #define USB_ENDP_TYPE_ISOCH 0x01 - #define USB_ENDP_TYPE_BULK 0x02 - #define USB_ENDP_TYPE_INTER 0x03 -#endif - -#ifndef USB_DEVICE_ADDR - #define USB_DEVICE_ADDR 0x02 -#endif -#ifndef DEFAULT_ENDP0_SIZE - #define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */ -#endif -#ifndef MAX_PACKET_SIZE - #define MAX_PACKET_SIZE 64 /* maximum packet size */ -#endif -#ifndef USB_BO_CBW_SIZE - #define USB_BO_CBW_SIZE 0x1F - #define USB_BO_CSW_SIZE 0x0D -#endif -#ifndef USB_BO_CBW_SIG0 - #define USB_BO_CBW_SIG0 0x55 - #define USB_BO_CBW_SIG1 0x53 - #define USB_BO_CBW_SIG2 0x42 - #define USB_BO_CBW_SIG3 0x43 - #define USB_BO_CSW_SIG0 0x55 - #define USB_BO_CSW_SIG1 0x53 - #define USB_BO_CSW_SIG2 0x42 - #define USB_BO_CSW_SIG3 0x53 -#endif - -#define DEF_STRING_DESC_LANG 0x00 -#define DEF_STRING_DESC_MANU 0x01 -#define DEF_STRING_DESC_PROD 0x02 -#define DEF_STRING_DESC_SERN 0x03 - -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif - -typedef struct __PACKED _USB_SETUP_REQ -{ - UINT8 bRequestType; - UINT8 bRequest; - UINT16 wValue; - UINT16 wIndex; - UINT16 wLength; -} USB_SETUP_REQ, *PUSB_SETUP_REQ; - -typedef struct __PACKED _USB_DEVICE_DESCR -{ - UINT8 bLength; - UINT8 bDescriptorType; - UINT16 bcdUSB; - UINT8 bDeviceClass; - UINT8 bDeviceSubClass; - UINT8 bDeviceProtocol; - UINT8 bMaxPacketSize0; - UINT16 idVendor; - UINT16 idProduct; - UINT16 bcdDevice; - UINT8 iManufacturer; - UINT8 iProduct; - UINT8 iSerialNumber; - UINT8 bNumConfigurations; -} USB_DEV_DESCR, *PUSB_DEV_DESCR; - -typedef struct __PACKED _USB_CONFIG_DESCR -{ - UINT8 bLength; - UINT8 bDescriptorType; - UINT16 wTotalLength; - UINT8 bNumInterfaces; - UINT8 bConfigurationValue; - UINT8 iConfiguration; - UINT8 bmAttributes; - UINT8 MaxPower; -} USB_CFG_DESCR, *PUSB_CFG_DESCR; - -typedef struct __PACKED _USB_INTERF_DESCR -{ - UINT8 bLength; - UINT8 bDescriptorType; - UINT8 bInterfaceNumber; - UINT8 bAlternateSetting; - UINT8 bNumEndpoints; - UINT8 bInterfaceClass; - UINT8 bInterfaceSubClass; - UINT8 bInterfaceProtocol; - UINT8 iInterface; -} USB_ITF_DESCR, *PUSB_ITF_DESCR; - -typedef struct __PACKED _USB_ENDPOINT_DESCR -{ - UINT8 bLength; - UINT8 bDescriptorType; - UINT8 bEndpointAddress; - UINT8 bmAttributes; - UINT16 wMaxPacketSize; - UINT8 bInterval; -} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; - -typedef struct __PACKED _USB_CONFIG_DESCR_LONG -{ - USB_CFG_DESCR cfg_descr; - USB_ITF_DESCR itf_descr; - USB_ENDP_DESCR endp_descr[1]; -} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; - -typedef struct __PACKED _USB_HUB_DESCR -{ - UINT8 bDescLength; - UINT8 bDescriptorType; - UINT8 bNbrPorts; - UINT8 wHubCharacteristicsL; - UINT8 wHubCharacteristicsH; - UINT8 bPwrOn2PwrGood; - UINT8 bHubContrCurrent; - UINT8 DeviceRemovable; - UINT8 PortPwrCtrlMask; -} USB_HUB_DESCR, *PUSB_HUB_DESCR; - -typedef struct __PACKED _USB_HID_DESCR -{ - UINT8 bLength; - UINT8 bDescriptorType; - UINT16 bcdHID; - UINT8 bCountryCode; - UINT8 bNumDescriptors; - UINT8 bDescriptorTypeX; - UINT8 wDescriptorLengthL; - UINT8 wDescriptorLengthH; -} USB_HID_DESCR, *PUSB_HID_DESCR; - -typedef struct __PACKED _UDISK_BOC_CBW -{ /* command of BulkOnly USB-FlashDisk */ - UINT32 mCBW_Sig; - UINT32 mCBW_Tag; - UINT32 mCBW_DataLen; /* uppest byte of data length, always is 0 */ - UINT8 mCBW_Flag; /* transfer direction and etc. */ - UINT8 mCBW_LUN; - UINT8 mCBW_CB_Len; /* length of command block */ - UINT8 mCBW_CB_Buf[16]; /* command block buffer */ -} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; - -typedef struct __PACKED _UDISK_BOC_CSW -{ /* status of BulkOnly USB-FlashDisk */ - UINT32 mCBW_Sig; - UINT32 mCBW_Tag; - UINT32 mCSW_Residue; /* return: remainder bytes */ /* uppest byte of remainder length, always is 0 */ - UINT8 mCSW_Status; /* return: result status */ -} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; - -extern PUINT8 pEP0_RAM_Addr; //ep0(64) -extern PUINT8 pEP1_RAM_Addr; //ep1_out(64)+ep1_in(64) -extern PUINT8 pEP2_RAM_Addr; //ep2_out(64)+ep2_in(64) -extern PUINT8 pEP3_RAM_Addr; //ep3_out(64)+ep3_in(64) -extern PUINT8 pEP4_RAM_Addr; //ep4_out(64)+ep4_in(64) -extern PUINT8 pEP5_RAM_Addr; //ep5_out(64)+ep5_in(64) -extern PUINT8 pEP6_RAM_Addr; //ep6_out(64)+ep6_in(64) -extern PUINT8 pEP7_RAM_Addr; //ep7_out(64)+ep7_in(64) - -#define pSetupReqPak ((PUSB_SETUP_REQ)pEP0_RAM_Addr) -#define pEP0_DataBuf (pEP0_RAM_Addr) -#define pEP1_OUT_DataBuf (pEP1_RAM_Addr) -#define pEP1_IN_DataBuf (pEP1_RAM_Addr + 64) -#define pEP2_OUT_DataBuf (pEP2_RAM_Addr) -#define pEP2_IN_DataBuf (pEP2_RAM_Addr + 64) -#define pEP3_OUT_DataBuf (pEP3_RAM_Addr) -#define pEP3_IN_DataBuf (pEP3_RAM_Addr + 64) -#define pEP4_OUT_DataBuf (pEP4_RAM_Addr) -#define pEP4_IN_DataBuf (pEP4_RAM_Addr + 64) -#define pEP5_OUT_DataBuf (pEP5_RAM_Addr) -#define pEP5_IN_DataBuf (pEP5_RAM_Addr + 64) -#define pEP6_OUT_DataBuf (pEP6_RAM_Addr) -#define pEP6_IN_DataBuf (pEP6_RAM_Addr + 64) -#define pEP7_OUT_DataBuf (pEP7_RAM_Addr) -#define pEP7_IN_DataBuf (pEP7_RAM_Addr + 64) - -void USB_DeviceInit(void); -void USB_DevTransProcess(void); - -void DevEP1_OUT_Deal(UINT16 l); -void DevEP2_OUT_Deal(UINT16 l); -void DevEP3_OUT_Deal(UINT16 l); -void DevEP4_OUT_Deal(UINT16 l); -void DevEP5_OUT_Deal(UINT16 l); -void DevEP6_OUT_Deal(UINT16 l); -void DevEP7_OUT_Deal(UINT16 l); - -void DevEP1_IN_Deal(UINT16 l); -void DevEP2_IN_Deal(UINT16 l); -void DevEP3_IN_Deal(UINT16 l); -void DevEP4_IN_Deal(UINT16 l); -void DevEP5_IN_Deal(UINT16 l); -void DevEP6_IN_Deal(UINT16 l); -void DevEP7_IN_Deal(UINT16 l); - -#define EP1_GetINSta() (R8_UEP1_CTRL & UEP_T_RES_NAK) -#define EP2_GetINSta() (R8_UEP2_CTRL & UEP_T_RES_NAK) -#define EP3_GetINSta() (R8_UEP3_CTRL & UEP_T_RES_NAK) -#define EP4_GetINSta() (R8_UEP4_CTRL & UEP_T_RES_NAK) -#define EP5_GetINSta() (R8_UEP5_CTRL & UEP_T_RES_NAK) -#define EP6_GetINSta() (R8_UEP6_CTRL & UEP_T_RES_NAK) -#define EP7_GetINSta() (R8_UEP7_CTRL & UEP_T_RES_NAK) - -#ifdef __cplusplus -} -#endif - -#endif // __USB_TYPE__ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_usb.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the USB + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_USB_H +#define __CH32V10x_USB_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef NULL + #define NULL 0 +#endif + +#ifndef VOID + #define VOID void +#endif +#ifndef CONST + #define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* USB */ +#define R32_USB_CONTROL (*((PUINT32V)(0x40023400))) // USB control & interrupt enable & device address +#define R8_USB_CTRL (*((PUINT8V)(0x40023400))) // USB base control +#define RB_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define RB_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps +#define RB_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable +#define RB_UC_SYS_CTRL1 0x20 // USB system control high bit +#define RB_UC_SYS_CTRL0 0x10 // USB system control low bit +#define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control +// bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control +// 0 00: disable USB device and disable internal pullup resistance +// 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance +// 0 1x: enable USB device and enable internal pullup resistance +// 1 00: enable USB host and normal status +// 1 01: enable USB host and force UDP/UDM output SE0 state +// 1 10: enable USB host and force UDP/UDM output J state +// 1 11: enable USB host and force UDP/UDM output resume or K state +#define RB_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define RB_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define RB_UC_CLR_ALL 0x02 // force clear FIFO and count of USB +#define RB_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB + +#define R8_UDEV_CTRL (*((PUINT8V)(0x40023401))) // USB device physical prot control +#define RB_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define RB_UD_GP_BIT 0x02 // general purpose bit +#define RB_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +#define R8_UHOST_CTRL R8_UDEV_CTRL // USB host physical prot control +#define RB_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define RB_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define RB_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +#define R8_USB_INT_EN (*((PUINT8V)(0x40023402))) // USB interrupt enable +#define RB_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode +#define RB_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode +#define RB_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow +#define RB_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define RB_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define RB_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion +#define RB_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define RB_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode + +#define R8_USB_DEV_AD (*((PUINT8V)(0x40023403))) // USB device address +#define RB_UDA_GP_BIT 0x80 // general purpose bit +#define MASK_USB_ADDR 0x7F // bit mask for USB device address + +#define R32_USB_STATUS (*((PUINT32V)(0x40023404))) // USB miscellaneous status & interrupt flag & interrupt status +#define R8_USB_MIS_ST (*((PUINT8V)(0x40023405))) // USB miscellaneous status +#define RB_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status +#define RB_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host +#define RB_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) +#define RB_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status +#define RB_UMS_SUSPEND 0x04 // RO, indicate USB suspend status +#define RB_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host +#define RB_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host + +#define R8_USB_INT_FG (*((PUINT8V)(0x40023406))) // USB interrupt flag +#define RB_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define RB_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define RB_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define RB_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define RB_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +#define R8_USB_INT_ST (*((PUINT8V)(0x40023407))) // USB interrupt status +#define RB_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define RB_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode +#define RB_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode +#define MASK_UIS_TOKEN 0x30 // RO, bit mask of current token PID code received for USB device mode +#define UIS_TOKEN_OUT 0x00 +#define UIS_TOKEN_SOF 0x10 +#define UIS_TOKEN_IN 0x20 +#define UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define MASK_UIS_ENDP 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define MASK_UIS_H_RES 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +#define R16_USB_RX_LEN (*((PUINT16V)(0x40023408))) // USB receiving length +#define MASK_UIS_RX_LEN 0x3FF // RO, bit mask of current receive length(10 bits for ch32v10x) +#define R32_USB_BUF_MODE (*((PUINT32V)(0x4002340c))) // USB endpoint buffer mode +#define R8_UEP4_1_MOD (*((PUINT8V)(0x4002340c))) // endpoint 4/1 mode +#define RB_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define RB_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define RB_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes +// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes +// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes +// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes +#define RB_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define RB_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA +// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes +// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes +// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes + +#define R8_UEP2_3_MOD (*((PUINT8V)(0x4002340d))) // endpoint 2/3 mode +#define RB_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define RB_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define RB_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define RB_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define RB_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define RB_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +#define R8_UH_EP_MOD R8_UEP2_3_MOD //host endpoint mode +#define RB_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define RB_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define RB_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define RB_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +#define R8_UEP5_6_MOD (*((PUINT8V)(0x4002340e))) // endpoint 5/6 mode +#define RB_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define RB_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define RB_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define RB_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define RB_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define RB_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +#define R8_UEP7_MOD (*((PUINT8V)(0x4002340f))) // endpoint 7 mode +#define RB_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define RB_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define RB_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +#define R16_UEP0_DMA (*((PUINT16V)(0x40023410))) // endpoint 0 DMA buffer address +#define R16_UEP1_DMA (*((PUINT16V)(0x40023414))) // endpoint 1 DMA buffer address +#define R16_UEP2_DMA (*((PUINT16V)(0x40023418))) // endpoint 2 DMA buffer address +#define R16_UH_RX_DMA R16_UEP2_DMA // host rx endpoint buffer high address +#define R16_UEP3_DMA (*((PUINT16V)(0x4002341c))) // endpoint 3 DMA buffer address + +#define R16_UEP4_DMA (*((PUINT16V)(0x40023420))) // endpoint 4 DMA buffer address +#define R16_UEP5_DMA (*((PUINT16V)(0x40023424))) // endpoint 5 DMA buffer address +#define R16_UEP6_DMA (*((PUINT16V)(0x40023428))) // endpoint 6 DMA buffer address +#define R16_UEP7_DMA (*((PUINT16V)(0x4002342c))) // endpoint 7 DMA buffer address + +#define R16_UH_TX_DMA R16_UEP3_DMA // host tx endpoint buffer high address +#define R32_USB_EP0_CTRL (*((PUINT32V)(0x40023430))) // endpoint 0 control & transmittal length +#define R8_UEP0_T_LEN (*((PUINT8V)(0x40023430))) // endpoint 0 transmittal length +#define R8_UEP0_CTRL (*((PUINT8V)(0x40023432))) // endpoint 0 control +#define R32_USB_EP1_CTRL (*((PUINT32V)(0x40023434))) // endpoint 1 control & transmittal length +#define R16_UEP1_T_LEN (*((PUINT16V)(0x40023434))) // endpoint 1 transmittal length(16-bits for ch32v10x) +#define R8_UEP1_CTRL (*((PUINT8V)(0x40023436))) // endpoint 1 control +#define RB_UEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define RB_UEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define RB_UEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define RB_UEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT) +#define RB_UEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT) +#define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define UEP_R_RES_ACK 0x00 +#define UEP_R_RES_TOUT 0x04 +#define UEP_R_RES_NAK 0x08 +#define UEP_R_RES_STALL 0x0C +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +#define RB_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) +#define RB_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) +#define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define UEP_T_RES_ACK 0x00 +#define UEP_T_RES_TOUT 0x01 +#define UEP_T_RES_NAK 0x02 +#define UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +#define R8_UH_SETUP R8_UEP1_CTRL // host aux setup +#define RB_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub +#define RB_UH_SOF_EN 0x40 // USB host automatic SOF enable + +#define R32_USB_EP2_CTRL (*((PUINT32V)(0x40023438))) // endpoint 2 control & transmittal length +#define R16_UEP2_T_LEN (*((PUINT16V)(0x40023438))) // endpoint 2 transmittal length(16-bits for ch32v10x) +#define R8_UEP2_CTRL (*((PUINT8V)(0x4002343a))) // endpoint 2 control + +#define R8_UH_EP_PID (*((PUINT8V)(0x40023438))) // host endpoint and PID +#define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer +#define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer + +#define R8_UH_RX_CTRL R8_UEP2_CTRL // host receiver endpoint control +#define RB_UH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define RB_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +#define R32_USB_EP3_CTRL (*((PUINT32V)(0x4002343c))) // endpoint 3 control & transmittal length +#define R16_UEP3_T_LEN (*((PUINT16V)(0x4002343c))) // endpoint 3 transmittal length(16-bits for ch32v10x) +#define R8_UEP3_CTRL (*((PUINT8V)(0x4002343e))) // endpoint 3 control +#define R8_UH_TX_LEN (*((PUINT16V)(0x4002343c))) //R8_UEP3_T_LEN // host transmittal endpoint transmittal length + +#define R8_UH_TX_CTRL R8_UEP3_CTRL // host transmittal endpoint control +#define RB_UH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define RB_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + +#define R32_USB_EP4_CTRL (*((PUINT32V)(0x40023440))) // endpoint 4 control & transmittal length +#define R16_UEP4_T_LEN (*((PUINT16V)(0x40023440))) // endpoint 4 transmittal length(16-bits for ch32v10x) +#define R8_UEP4_CTRL (*((PUINT8V)(0x40023442))) // endpoint 4 control + +#define R32_USB_EP5_CTRL (*((PUINT32V)(0x40023444))) // endpoint 5 control & transmittal length +#define R16_UEP5_T_LEN (*((PUINT16V)(0x40023444))) // endpoint 5 transmittal length(16-bits for ch32v10x) +#define R8_UEP5_CTRL (*((PUINT8V)(0x40023446))) // endpoint 5 control + +#define R32_USB_EP6_CTRL (*((PUINT32V)(0x40023448))) // endpoint 6 control & transmittal length +#define R16_UEP6_T_LEN (*((PUINT16V)(0x40023448))) // endpoint 6 transmittal length(16-bits for ch32v10x) +#define R8_UEP6_CTRL (*((PUINT8V)(0x4002344a))) // endpoint 6 control + +#define R32_USB_EP7_CTRL (*((PUINT32V)(0x4002344c))) // endpoint 7 control & transmittal length +#define R16_UEP7_T_LEN (*((PUINT16V)(0x4002344c))) // endpoint 7 transmittal length(16-bits for ch32v10x) +#define R8_UEP7_CTRL (*((PUINT8V)(0x4002344e))) // endpoint 7 control + +#ifdef __cplusplus +} +#endif + +#endif //__CH32V10x_USB_H + +#ifndef __USB_TYPE__ +#define __USB_TYPE__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USB constant and structure define */ + +/* USB PID */ +#ifndef USB_PID_SETUP + #define USB_PID_NULL 0x00 /* reserved PID */ + #define USB_PID_SOF 0x05 + #define USB_PID_SETUP 0x0D + #define USB_PID_IN 0x09 + #define USB_PID_OUT 0x01 + #define USB_PID_ACK 0x02 + #define USB_PID_NAK 0x0A + #define USB_PID_STALL 0x0E + #define USB_PID_DATA0 0x03 + #define USB_PID_DATA1 0x0B + #define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR + #define USB_GET_STATUS 0x00 + #define USB_CLEAR_FEATURE 0x01 + #define USB_SET_FEATURE 0x03 + #define USB_SET_ADDRESS 0x05 + #define USB_GET_DESCRIPTOR 0x06 + #define USB_SET_DESCRIPTOR 0x07 + #define USB_GET_CONFIGURATION 0x08 + #define USB_SET_CONFIGURATION 0x09 + #define USB_GET_INTERFACE 0x0A + #define USB_SET_INTERFACE 0x0B + #define USB_SYNCH_FRAME 0x0C +#endif + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR + #define HUB_GET_STATUS 0x00 + #define HUB_CLEAR_FEATURE 0x01 + #define HUB_GET_STATE 0x02 + #define HUB_SET_FEATURE 0x03 + #define HUB_GET_DESCRIPTOR 0x06 + #define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT + #define HID_GET_REPORT 0x01 + #define HID_GET_IDLE 0x02 + #define HID_GET_PROTOCOL 0x03 + #define HID_SET_REPORT 0x09 + #define HID_SET_IDLE 0x0A + #define HID_SET_PROTOCOL 0x0B +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif + +/* Bit define for USB request type */ +#ifndef USB_REQ_TYP_MASK + #define USB_REQ_TYP_IN 0x80 /* control IN, device to host */ + #define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */ + #define USB_REQ_TYP_READ 0x80 /* control read, device to host */ + #define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */ + #define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */ + #define USB_REQ_TYP_STANDARD 0x00 + #define USB_REQ_TYP_CLASS 0x20 + #define USB_REQ_TYP_VENDOR 0x40 + #define USB_REQ_TYP_RESERVED 0x60 + #define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */ + #define USB_REQ_RECIP_DEVICE 0x00 + #define USB_REQ_RECIP_INTERF 0x01 + #define USB_REQ_RECIP_ENDP 0x02 + #define USB_REQ_RECIP_OTHER 0x03 + #define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 + #define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB request type for hub class request */ +#ifndef HUB_GET_HUB_DESCRIPTOR + #define HUB_CLEAR_HUB_FEATURE 0x20 + #define HUB_CLEAR_PORT_FEATURE 0x23 + #define HUB_GET_BUS_STATE 0xA3 + #define HUB_GET_HUB_DESCRIPTOR 0xA0 + #define HUB_GET_HUB_STATUS 0xA0 + #define HUB_GET_PORT_STATUS 0xA3 + #define HUB_SET_HUB_DESCRIPTOR 0x20 + #define HUB_SET_HUB_FEATURE 0x20 + #define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub class feature selectors */ +#ifndef HUB_PORT_RESET + #define HUB_C_HUB_LOCAL_POWER 0 + #define HUB_C_HUB_OVER_CURRENT 1 + #define HUB_PORT_CONNECTION 0 + #define HUB_PORT_ENABLE 1 + #define HUB_PORT_SUSPEND 2 + #define HUB_PORT_OVER_CURRENT 3 + #define HUB_PORT_RESET 4 + #define HUB_PORT_POWER 8 + #define HUB_PORT_LOW_SPEED 9 + #define HUB_C_PORT_CONNECTION 16 + #define HUB_C_PORT_ENABLE 17 + #define HUB_C_PORT_SUSPEND 18 + #define HUB_C_PORT_OVER_CURRENT 19 + #define HUB_C_PORT_RESET 20 +#endif + +/* USB descriptor type */ +#ifndef USB_DESCR_TYP_DEVICE + #define USB_DESCR_TYP_DEVICE 0x01 + #define USB_DESCR_TYP_CONFIG 0x02 + #define USB_DESCR_TYP_STRING 0x03 + #define USB_DESCR_TYP_INTERF 0x04 + #define USB_DESCR_TYP_ENDP 0x05 + #define USB_DESCR_TYP_QUALIF 0x06 + #define USB_DESCR_TYP_SPEED 0x07 + #define USB_DESCR_TYP_OTG 0x09 + #define USB_DESCR_TYP_HID 0x21 + #define USB_DESCR_TYP_REPORT 0x22 + #define USB_DESCR_TYP_PHYSIC 0x23 + #define USB_DESCR_TYP_CS_INTF 0x24 + #define USB_DESCR_TYP_CS_ENDP 0x25 + #define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB device class */ +#ifndef USB_DEV_CLASS_HUB + #define USB_DEV_CLASS_RESERVED 0x00 + #define USB_DEV_CLASS_AUDIO 0x01 + #define USB_DEV_CLASS_COMMUNIC 0x02 + #define USB_DEV_CLASS_HID 0x03 + #define USB_DEV_CLASS_MONITOR 0x04 + #define USB_DEV_CLASS_PHYSIC_IF 0x05 + #define USB_DEV_CLASS_IMAGE 0x06 + #define USB_DEV_CLASS_PRINTER 0x07 + #define USB_DEV_CLASS_STORAGE 0x08 + #define USB_DEV_CLASS_HUB 0x09 + #define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB endpoint type and attributes */ +#ifndef USB_ENDP_TYPE_MASK + #define USB_ENDP_DIR_MASK 0x80 + #define USB_ENDP_ADDR_MASK 0x0F + #define USB_ENDP_TYPE_MASK 0x03 + #define USB_ENDP_TYPE_CTRL 0x00 + #define USB_ENDP_TYPE_ISOCH 0x01 + #define USB_ENDP_TYPE_BULK 0x02 + #define USB_ENDP_TYPE_INTER 0x03 +#endif + +#ifndef USB_DEVICE_ADDR + #define USB_DEVICE_ADDR 0x02 +#endif +#ifndef DEFAULT_ENDP0_SIZE + #define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */ +#endif +#ifndef MAX_PACKET_SIZE + #define MAX_PACKET_SIZE 64 /* maximum packet size */ +#endif +#ifndef USB_BO_CBW_SIZE + #define USB_BO_CBW_SIZE 0x1F + #define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 + #define USB_BO_CBW_SIG0 0x55 + #define USB_BO_CBW_SIG1 0x53 + #define USB_BO_CBW_SIG2 0x42 + #define USB_BO_CBW_SIG3 0x43 + #define USB_BO_CSW_SIG0 0x55 + #define USB_BO_CSW_SIG1 0x53 + #define USB_BO_CSW_SIG2 0x42 + #define USB_BO_CSW_SIG3 0x53 +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 + +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif + +typedef struct __PACKED _USB_SETUP_REQ +{ + UINT8 bRequestType; + UINT8 bRequest; + UINT16 wValue; + UINT16 wIndex; + UINT16 wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + +typedef struct __PACKED _USB_DEVICE_DESCR +{ + UINT8 bLength; + UINT8 bDescriptorType; + UINT16 bcdUSB; + UINT8 bDeviceClass; + UINT8 bDeviceSubClass; + UINT8 bDeviceProtocol; + UINT8 bMaxPacketSize0; + UINT16 idVendor; + UINT16 idProduct; + UINT16 bcdDevice; + UINT8 iManufacturer; + UINT8 iProduct; + UINT8 iSerialNumber; + UINT8 bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + +typedef struct __PACKED _USB_CONFIG_DESCR +{ + UINT8 bLength; + UINT8 bDescriptorType; + UINT16 wTotalLength; + UINT8 bNumInterfaces; + UINT8 bConfigurationValue; + UINT8 iConfiguration; + UINT8 bmAttributes; + UINT8 MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + +typedef struct __PACKED _USB_INTERF_DESCR +{ + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 bInterfaceNumber; + UINT8 bAlternateSetting; + UINT8 bNumEndpoints; + UINT8 bInterfaceClass; + UINT8 bInterfaceSubClass; + UINT8 bInterfaceProtocol; + UINT8 iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + +typedef struct __PACKED _USB_ENDPOINT_DESCR +{ + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 bEndpointAddress; + UINT8 bmAttributes; + UINT16 wMaxPacketSize; + UINT8 bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + +typedef struct __PACKED _USB_CONFIG_DESCR_LONG +{ + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[1]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + +typedef struct __PACKED _USB_HUB_DESCR +{ + UINT8 bDescLength; + UINT8 bDescriptorType; + UINT8 bNbrPorts; + UINT8 wHubCharacteristicsL; + UINT8 wHubCharacteristicsH; + UINT8 bPwrOn2PwrGood; + UINT8 bHubContrCurrent; + UINT8 DeviceRemovable; + UINT8 PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + +typedef struct __PACKED _USB_HID_DESCR +{ + UINT8 bLength; + UINT8 bDescriptorType; + UINT16 bcdHID; + UINT8 bCountryCode; + UINT8 bNumDescriptors; + UINT8 bDescriptorTypeX; + UINT8 wDescriptorLengthL; + UINT8 wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + +typedef struct __PACKED _UDISK_BOC_CBW +{ /* command of BulkOnly USB-FlashDisk */ + UINT32 mCBW_Sig; + UINT32 mCBW_Tag; + UINT32 mCBW_DataLen; /* uppest byte of data length, always is 0 */ + UINT8 mCBW_Flag; /* transfer direction and etc. */ + UINT8 mCBW_LUN; + UINT8 mCBW_CB_Len; /* length of command block */ + UINT8 mCBW_CB_Buf[16]; /* command block buffer */ +} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; + +typedef struct __PACKED _UDISK_BOC_CSW +{ /* status of BulkOnly USB-FlashDisk */ + UINT32 mCBW_Sig; + UINT32 mCBW_Tag; + UINT32 mCSW_Residue; /* return: remainder bytes */ /* uppest byte of remainder length, always is 0 */ + UINT8 mCSW_Status; /* return: result status */ +} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; + +extern PUINT8 pEP0_RAM_Addr; //ep0(64) +extern PUINT8 pEP1_RAM_Addr; //ep1_out(64)+ep1_in(64) +extern PUINT8 pEP2_RAM_Addr; //ep2_out(64)+ep2_in(64) +extern PUINT8 pEP3_RAM_Addr; //ep3_out(64)+ep3_in(64) +extern PUINT8 pEP4_RAM_Addr; //ep4_out(64)+ep4_in(64) +extern PUINT8 pEP5_RAM_Addr; //ep5_out(64)+ep5_in(64) +extern PUINT8 pEP6_RAM_Addr; //ep6_out(64)+ep6_in(64) +extern PUINT8 pEP7_RAM_Addr; //ep7_out(64)+ep7_in(64) + +#define pSetupReqPak ((PUSB_SETUP_REQ)pEP0_RAM_Addr) +#define pEP0_DataBuf (pEP0_RAM_Addr) +#define pEP1_OUT_DataBuf (pEP1_RAM_Addr) +#define pEP1_IN_DataBuf (pEP1_RAM_Addr + 64) +#define pEP2_OUT_DataBuf (pEP2_RAM_Addr) +#define pEP2_IN_DataBuf (pEP2_RAM_Addr + 64) +#define pEP3_OUT_DataBuf (pEP3_RAM_Addr) +#define pEP3_IN_DataBuf (pEP3_RAM_Addr + 64) +#define pEP4_OUT_DataBuf (pEP4_RAM_Addr) +#define pEP4_IN_DataBuf (pEP4_RAM_Addr + 64) +#define pEP5_OUT_DataBuf (pEP5_RAM_Addr) +#define pEP5_IN_DataBuf (pEP5_RAM_Addr + 64) +#define pEP6_OUT_DataBuf (pEP6_RAM_Addr) +#define pEP6_IN_DataBuf (pEP6_RAM_Addr + 64) +#define pEP7_OUT_DataBuf (pEP7_RAM_Addr) +#define pEP7_IN_DataBuf (pEP7_RAM_Addr + 64) + +void USB_DeviceInit(void); +void USB_DevTransProcess(void); + +void DevEP1_OUT_Deal(UINT16 l); +void DevEP2_OUT_Deal(UINT16 l); +void DevEP3_OUT_Deal(UINT16 l); +void DevEP4_OUT_Deal(UINT16 l); +void DevEP5_OUT_Deal(UINT16 l); +void DevEP6_OUT_Deal(UINT16 l); +void DevEP7_OUT_Deal(UINT16 l); + +void DevEP1_IN_Deal(UINT16 l); +void DevEP2_IN_Deal(UINT16 l); +void DevEP3_IN_Deal(UINT16 l); +void DevEP4_IN_Deal(UINT16 l); +void DevEP5_IN_Deal(UINT16 l); +void DevEP6_IN_Deal(UINT16 l); +void DevEP7_IN_Deal(UINT16 l); + +#define EP1_GetINSta() (R8_UEP1_CTRL & UEP_T_RES_NAK) +#define EP2_GetINSta() (R8_UEP2_CTRL & UEP_T_RES_NAK) +#define EP3_GetINSta() (R8_UEP3_CTRL & UEP_T_RES_NAK) +#define EP4_GetINSta() (R8_UEP4_CTRL & UEP_T_RES_NAK) +#define EP5_GetINSta() (R8_UEP5_CTRL & UEP_T_RES_NAK) +#define EP6_GetINSta() (R8_UEP6_CTRL & UEP_T_RES_NAK) +#define EP7_GetINSta() (R8_UEP7_CTRL & UEP_T_RES_NAK) + +#ifdef __cplusplus +} +#endif + +#endif // __USB_TYPE__ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_usb_host.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_usb_host.h index 29bb7e1..62717d0 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_usb_host.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_usb_host.h @@ -1,101 +1,101 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_usb_host.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the USB - * Host firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_USBHOST_H -#define __CH32V10x_USBHOST_H - -#include "ch32v10x_usb.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define ERR_SUCCESS 0x00 -#define ERR_USB_CONNECT 0x15 -#define ERR_USB_DISCON 0x16 -#define ERR_USB_BUF_OVER 0x17 -#define ERR_USB_DISK_ERR 0x1F -#define ERR_USB_TRANSFER 0x20 -#define ERR_USB_UNSUPPORT 0xFB -#define ERR_USB_UNKNOWN 0xFE -#define ERR_AOA_PROTOCOL 0x41 - -#define ROOT_DEV_DISCONNECT 0 -#define ROOT_DEV_CONNECTED 1 -#define ROOT_DEV_FAILED 2 -#define ROOT_DEV_SUCCESS 3 -#define DEV_TYPE_KEYBOARD (USB_DEV_CLASS_HID | 0x20) -#define DEV_TYPE_MOUSE (USB_DEV_CLASS_HID | 0x30) -#define DEF_AOA_DEVICE 0xF0 -#define DEV_TYPE_UNKNOW 0xFF - -#define HUB_MAX_PORTS 4 -#define WAIT_USB_TOUT_200US 3000 - -typedef struct -{ - UINT8 DeviceStatus; - UINT8 DeviceAddress; - UINT8 DeviceSpeed; - UINT8 DeviceType; - UINT16 DeviceVID; - UINT16 DevicePID; - UINT8 GpVar[4]; - UINT8 GpHUBPortNum; -} _RootHubDev; - -extern _RootHubDev ThisUsbDev; -extern UINT8 UsbDevEndp0Size; -extern UINT8 FoundNewDev; - -extern PUINT8 pHOST_RX_RAM_Addr; -extern PUINT8 pHOST_TX_RAM_Addr; -#define pSetupReq ((PUSB_SETUP_REQ)pHOST_TX_RAM_Addr) - -extern const UINT8 SetupGetDevDescr[]; -extern const UINT8 SetupGetCfgDescr[]; -extern const UINT8 SetupSetUsbAddr[]; -extern const UINT8 SetupSetUsbConfig[]; -extern const UINT8 SetupSetUsbInterface[]; -extern const UINT8 SetupClrEndpStall[]; - -#if 0 -void DisableRootHubPort(void); -UINT8 AnalyzeRootHub(void); -void SetHostUsbAddr(UINT8 addr); -void SetUsbSpeed(UINT8 FullSpeed); -void ResetRootHubPort(void); -UINT8 EnableRootHubPort(void); -void SelectHubPort(UINT8 HubPortIndex); -UINT8 WaitUSB_Interrupt(void); -UINT8 USBHostTransact(UINT8 endp_pid, UINT8 tog, UINT32 timeout); -UINT8 HostCtrlTransfer(PUINT8 DataBuf, PUINT8 RetLen); -void CopySetupReqPkg(const UINT8 *pReqPkt); -UINT8 CtrlGetDeviceDescr(PUINT8 DataBuf); -UINT8 CtrlGetConfigDescr(PUINT8 DataBuf); -UINT8 CtrlSetUsbAddress(UINT8 addr); -UINT8 CtrlSetUsbConfig(UINT8 cfg); -UINT8 CtrlClearEndpStall(UINT8 endp); -UINT8 CtrlSetUsbIntercace(UINT8 cfg); - -void USB_HostInit(void); -UINT8 InitRootDevice(PUINT8 DataBuf); -UINT8 HubGetPortStatus(UINT8 HubPortIndex); -UINT8 HubSetPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt); -UINT8 HubClearPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_USBHOST_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_usb_host.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the USB + * Host firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_USBHOST_H +#define __CH32V10x_USBHOST_H + +#include "ch32v10x_usb.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ERR_SUCCESS 0x00 +#define ERR_USB_CONNECT 0x15 +#define ERR_USB_DISCON 0x16 +#define ERR_USB_BUF_OVER 0x17 +#define ERR_USB_DISK_ERR 0x1F +#define ERR_USB_TRANSFER 0x20 +#define ERR_USB_UNSUPPORT 0xFB +#define ERR_USB_UNKNOWN 0xFE +#define ERR_AOA_PROTOCOL 0x41 + +#define ROOT_DEV_DISCONNECT 0 +#define ROOT_DEV_CONNECTED 1 +#define ROOT_DEV_FAILED 2 +#define ROOT_DEV_SUCCESS 3 +#define DEV_TYPE_KEYBOARD (USB_DEV_CLASS_HID | 0x20) +#define DEV_TYPE_MOUSE (USB_DEV_CLASS_HID | 0x30) +#define DEF_AOA_DEVICE 0xF0 +#define DEV_TYPE_UNKNOW 0xFF + +#define HUB_MAX_PORTS 4 +#define WAIT_USB_TOUT_200US 3000 + +typedef struct +{ + UINT8 DeviceStatus; + UINT8 DeviceAddress; + UINT8 DeviceSpeed; + UINT8 DeviceType; + UINT16 DeviceVID; + UINT16 DevicePID; + UINT8 GpVar[4]; + UINT8 GpHUBPortNum; +} _RootHubDev; + +extern _RootHubDev ThisUsbDev; +extern UINT8 UsbDevEndp0Size; +extern UINT8 FoundNewDev; + +extern PUINT8 pHOST_RX_RAM_Addr; +extern PUINT8 pHOST_TX_RAM_Addr; +#define pSetupReq ((PUSB_SETUP_REQ)pHOST_TX_RAM_Addr) + +extern const UINT8 SetupGetDevDescr[]; +extern const UINT8 SetupGetCfgDescr[]; +extern const UINT8 SetupSetUsbAddr[]; +extern const UINT8 SetupSetUsbConfig[]; +extern const UINT8 SetupSetUsbInterface[]; +extern const UINT8 SetupClrEndpStall[]; + +#if 0 +void DisableRootHubPort(void); +UINT8 AnalyzeRootHub(void); +void SetHostUsbAddr(UINT8 addr); +void SetUsbSpeed(UINT8 FullSpeed); +void ResetRootHubPort(void); +UINT8 EnableRootHubPort(void); +void SelectHubPort(UINT8 HubPortIndex); +UINT8 WaitUSB_Interrupt(void); +UINT8 USBHostTransact(UINT8 endp_pid, UINT8 tog, UINT32 timeout); +UINT8 HostCtrlTransfer(PUINT8 DataBuf, PUINT8 RetLen); +void CopySetupReqPkg(const UINT8 *pReqPkt); +UINT8 CtrlGetDeviceDescr(PUINT8 DataBuf); +UINT8 CtrlGetConfigDescr(PUINT8 DataBuf); +UINT8 CtrlSetUsbAddress(UINT8 addr); +UINT8 CtrlSetUsbConfig(UINT8 cfg); +UINT8 CtrlClearEndpStall(UINT8 endp); +UINT8 CtrlSetUsbIntercace(UINT8 cfg); + +void USB_HostInit(void); +UINT8 InitRootDevice(PUINT8 DataBuf); +UINT8 HubGetPortStatus(UINT8 HubPortIndex); +UINT8 HubSetPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt); +UINT8 HubClearPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_USBHOST_H */ diff --git a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_wwdg.h b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_wwdg.h index 8f00abe..dfe8044 100644 --- a/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_wwdg.h +++ b/system/CH32V10x/SRC/Peripheral/inc/ch32v10x_wwdg.h @@ -1,41 +1,41 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_wwdg.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file contains all the functions prototypes for the WWDG - * firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_WWDG_H -#define __CH32V10x_WWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v10x.h" - -/* WWDG_Prescaler */ -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) - -void WWDG_DeInit(void); -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); -void WWDG_Enable(uint8_t Counter); -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V10x_WWDG_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_wwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the WWDG + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_WWDG_H +#define __CH32V10x_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_WWDG_H */ diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_adc.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_adc.c index 8b91734..be52908 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_adc.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_adc.c @@ -1,1147 +1,1147 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_adc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the ADC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_adc.h" -#include "ch32v10x_rcc.h" - -/* ADC DISCNUM mask */ -#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) -#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) - -/* ADC JAUTO mask */ -#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) -#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) - -/* ADC AWDCH mask */ -#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) - -/* CTLR1 register Mask */ -#define CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) - -/* ADC ADON mask */ -#define CTLR2_ADON_Set ((uint32_t)0x00000001) -#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CTLR2_DMA_Set ((uint32_t)0x00000100) -#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) - -/* ADC RSTCAL mask */ -#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) - -/* ADC CAL mask */ -#define CTLR2_CAL_Set ((uint32_t)0x00000004) - -/* ADC SWSTART mask */ -#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) - -/* ADC EXTTRIG mask */ -#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) - -/* ADC JEXTSEL mask */ -#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTART mask */ -#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) - -/* ADC TSPD mask */ -#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) -#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) - -/* CTLR2 register Mask */ -#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) - -/* ADC SQx mask */ -#define RSQR3_SQ_Set ((uint32_t)0x0000001F) -#define RSQR2_SQ_Set ((uint32_t)0x0000001F) -#define RSQR1_SQ_Set ((uint32_t)0x0000001F) - -/* RSQR1 register Mask */ -#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define ISQR_JSQ_Set ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define ISQR_JL_Set ((uint32_t)0x00300000) -#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) -#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) - -/* ADC IDATARx registers offset */ -#define IDATAR_Offset ((uint8_t)0x28) - -/* ADC1 RDATAR register base address */ -#define RDATAR_ADDRESS ((uint32_t)0x4001244C) - -/********************************************************************* - * @fn ADC_DeInit - * - * @brief Deinitializes the ADCx peripheral registers to their default - * reset values. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return none - */ -void ADC_DeInit(ADC_TypeDef *ADCx) -{ - if(ADCx == ADC1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); - } -} - -/********************************************************************* - * @fn ADC_Init - * - * @brief Initializes the ADCx peripheral according to the specified - * parameters in the ADC_InitStruct. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); - ADCx->CTLR1 = tmpreg1; - - tmpreg1 = ADCx->CTLR2; - tmpreg1 &= CTLR2_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - ADCx->CTLR2 = tmpreg1; - - tmpreg1 = ADCx->RSQR1; - tmpreg1 &= RSQR1_CLEAR_Mask; - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); - tmpreg1 |= (uint32_t)tmpreg2 << 20; - ADCx->RSQR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_StructInit - * - * @brief Fills each ADC_InitStruct member with its default value. - * - * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) -{ - ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStruct->ADC_NbrOfChannel = 1; -} - -/********************************************************************* - * @fn ADC_Cmd - * - * @brief Enables or disables the specified ADC peripheral. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_ADON_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_ADON_Reset; - } -} - -/********************************************************************* - * @fn ADC_DMACmd - * - * @brief Enables or disables the specified ADC DMA request. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_DMA_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_DMA_Reset; - } -} - -/********************************************************************* - * @fn ADC_ITConfig - * - * @brief Enables or disables the specified ADC interrupts. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)ADC_IT; - - if(NewState != DISABLE) - { - ADCx->CTLR1 |= itmask; - } - else - { - ADCx->CTLR1 &= (~(uint32_t)itmask); - } -} - -/********************************************************************* - * @fn ADC_ResetCalibration - * - * @brief Resets the selected ADC calibration registers. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return none - */ -void ADC_ResetCalibration(ADC_TypeDef *ADCx) -{ - ADCx->CTLR2 |= CTLR2_RSTCAL_Set; -} - -/********************************************************************* - * @fn ADC_GetResetCalibrationStatus - * - * @brief Gets the selected ADC reset calibration registers status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_StartCalibration - * - * @brief Starts the selected ADC calibration process. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return None - */ -void ADC_StartCalibration(ADC_TypeDef *ADCx) -{ - ADCx->CTLR2 |= CTLR2_CAL_Set; -} - -/********************************************************************* - * @fn ADC_GetCalibrationStatus - * - * @brief Gets the selected ADC calibration status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_SoftwareStartConvCmd - * - * @brief Enables or disables the selected ADC software start conversion. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartConvStatus - * - * @brief Gets the selected ADC Software start conversion Status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_DiscModeChannelCountConfig - * - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * Number - specifies the discontinuous mode regular channel - * count value(1-8). - * - * @return None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_DISCNUM_Reset; - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - ADCx->CTLR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_DiscModeCmd - * - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_DISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_DISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_RegularChannelConfig - * - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_10 - ADC Channel10 selected. - * ADC_Channel_11 - ADC Channel11 selected. - * ADC_Channel_12 - ADC Channel12 selected. - * ADC_Channel_13 - ADC Channel13 selected. - * ADC_Channel_14 - ADC Channel14 selected. - * ADC_Channel_15 - ADC Channel15 selected. - * ADC_Channel_16 - ADC Channel16 selected. - * ADC_Channel_17 - ADC Channel17 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. - * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. - * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. - * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. - * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. - * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. - * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. - * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. - * - * @return None - */ -void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - if(Rank < 7) - { - tmpreg1 = ADCx->RSQR3; - tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - tmpreg1 |= tmpreg2; - ADCx->RSQR3 = tmpreg1; - } - else if(Rank < 13) - { - tmpreg1 = ADCx->RSQR2; - tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - tmpreg1 |= tmpreg2; - ADCx->RSQR2 = tmpreg1; - } - else - { - tmpreg1 = ADCx->RSQR1; - tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - tmpreg1 |= tmpreg2; - ADCx->RSQR1 = tmpreg1; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigConvCmd - * - * @brief Enables or disables the ADCx conversion through external trigger. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetConversionValue - * - * @brief Returns the last ADCx conversion result data for regular channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return ADCx->RDATAR - The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) -{ - return (uint16_t)ADCx->RDATAR; -} - -/********************************************************************* - * @fn ADC_GetDualModeConversionValue - * - * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. - * - * @return RDATAR_ADDRESS - The Data conversion value. - */ -uint32_t ADC_GetDualModeConversionValue(void) -{ - return (*(__IO uint32_t *)RDATAR_ADDRESS); -} - -/********************************************************************* - * @fn ADC_AutoInjectedConvCmd - * - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JAUTO_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JAUTO_Reset; - } -} - -/********************************************************************* - * @fn ADC_InjectedDiscModeCmd - * - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JDISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvConfig - * - * @brief Configures the ADCx external trigger for injected channels conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start - * injected conversion. - * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. - * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. - * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. - * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. - * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. - * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. - * ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 - External interrupt - * line 15 event selected. - * ADC_ExternalTrigInjecConv_None: Injected conversion started - * by software and not by external trigger. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR2; - tmpreg &= CTLR2_JEXTSEL_Reset; - tmpreg |= ADC_ExternalTrigInjecConv; - ADCx->CTLR2 = tmpreg; -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvCmd - * - * @brief Enables or disables the ADCx injected channels conversion through - * external trigger. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_SoftwareStartInjectedConvCmd - * - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartInjectedConvCmdStatus - * - * @brief Gets the selected ADC Software start injected conversion Status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_InjectedChannelConfig - * - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_10 - ADC Channel10 selected. - * ADC_Channel_11 - ADC Channel11 selected. - * ADC_Channel_12 - ADC Channel12 selected. - * ADC_Channel_13 - ADC Channel13 selected. - * ADC_Channel_14 - ADC Channel14 selected. - * ADC_Channel_15 - ADC Channel15 selected. - * ADC_Channel_16 - ADC Channel16 selected. - * ADC_Channel_17 - ADC Channel17 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 4. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. - * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. - * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. - * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. - * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. - * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. - * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. - * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. - * - * @return None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - tmpreg1 = ADCx->ISQR; - tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; - tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 |= tmpreg2; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_InjectedSequencerLengthConfig - * - * @brief Configures the sequencer length for injected channels. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * Length - The sequencer length. - * This parameter must be a number between 1 to 4. - * - * @return None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->ISQR; - tmpreg1 &= ISQR_JL_Reset; - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_SetInjectedOffset - * - * @brief Set the injected channels conversion value offset. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InjectedChannel: the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * Offset - the offset value for the selected ADC injected channel. - * This parameter must be a 12bit value. - * - * @return None - */ -void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - *(__IO uint32_t *)tmp = (uint32_t)Offset; -} - -/********************************************************************* - * @fn ADC_GetInjectedConversionValue - * - * @brief Returns the ADC injected channel conversion result. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InjectedChannel - the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * - * @return tmp - The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + IDATAR_Offset; - - return (uint16_t)(*(__IO uint32_t *)tmp); -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogCmd - * - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_AnalogWatchdog - the ADC analog watchdog configuration. - * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a - * single regular channel. - * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a - * single injected channel. - * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog - * on a single regular or injected channel. - * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all - * regular channel. - * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all - * injected channel. - * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on - * all regular and injected channels. - * ADC_AnalogWatchdog_None - No channel guarded by the analog - * watchdog. - * - * @return none - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDMode_Reset; - tmpreg |= ADC_AnalogWatchdog; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogThresholdsConfig - * - * @brief Configures the high and low thresholds of the analog watchdog. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * HighThreshold - the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * LowThreshold - the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * - * @return none - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - ADCx->WDHTR = HighThreshold; - ADCx->WDLTR = LowThreshold; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogSingleChannelConfig - * - * @brief Configures the analog watchdog guarded single channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_10 - ADC Channel10 selected. - * ADC_Channel_11 - ADC Channel11 selected. - * ADC_Channel_12 - ADC Channel12 selected. - * ADC_Channel_13 - ADC Channel13 selected. - * ADC_Channel_14 - ADC Channel14 selected. - * ADC_Channel_15 - ADC Channel15 selected. - * ADC_Channel_16 - ADC Channel16 selected. - * ADC_Channel_17 - ADC Channel17 selected. - * - * @return None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDCH_Reset; - tmpreg |= ADC_Channel; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_TempSensorVrefintCmd - * - * @brief Enables or disables the temperature sensor and Vrefint channel. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADC1->CTLR2 |= CTLR2_TSVREFE_Set; - } - else - { - ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetFlagStatus - * - * @brief Checks whether the specified ADC flag is set or not. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to check. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearFlag - * - * @brief Clears the ADCx's pending flags. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to clear. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return none - */ -void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - ADCx->STATR = ~(uint32_t)ADC_FLAG; -} - -/********************************************************************* - * @fn ADC_GetITStatus - * - * @brief Checks whether the specified ADC interrupt has occurred or not. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt source to check. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return ITStatus: SET or RESET. - */ -ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - itmask = ADC_IT >> 8; - enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); - - if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearITPendingBit - * - * @brief Clears the ADCx's interrupt pending bits. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt pending bit to clear. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return none - */ -void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)(ADC_IT >> 8); - ADCx->STATR = ~(uint32_t)itmask; -} - -/********************************************************************* - * @fn TempSensor_Volt_To_Temper - * - * @brief Internal Temperature Sensor Voltage to temperature. - * - * @param Value - Voltage Value(mv). - * - * @return Temper - Temperature Value. - */ -s32 TempSensor_Volt_To_Temper(s32 Value) -{ - s32 Temper, Refer_Volt, Refer_Temper; - s32 k = 43; - - Refer_Volt = (s32)((*(u32 *)0x1FFFF898) & 0x0000FFFF); - Refer_Temper = (s32)(((*(u32 *)0x1FFFF898) >> 16) & 0x0000FFFF); - - Temper = Refer_Temper + ((Value - Refer_Volt) * 10 + (k >> 1)) / k; - - return Temper; -} - -/********************************************************************* - * @fn Get_CalibrationValue - * - * @brief Get ADCx Calibration Value. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return CalibrationValue - */ -int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) -{ - __IO uint8_t i, j; - uint16_t buf[10]; - __IO uint16_t t; - - for(i = 0; i < 10; i++){ - ADC_ResetCalibration(ADCx); - while(ADC_GetResetCalibrationStatus(ADCx)); - ADC_StartCalibration(ADCx); - while(ADC_GetCalibrationStatus(ADCx)); - buf[i] = ADCx->RDATAR; - } - - for(i = 0; i < 10; i++){ - for(j = 0; j < 9; j++){ - if(buf[j] > buf[j + 1]){ - t = buf[j]; - buf[j] = buf[j + 1]; - buf[j+1] = t; - } - } - } - - t = 0; - for(i = 0; i < 6; i++){ - t += buf[i + 2]; - } - - t = (t / 6) + ((t % 6) / 3); - - return (int16_t)(2048 - (int16_t)t); -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_adc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the ADC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_adc.h" +#include "ch32v10x_rcc.h" + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_ResetCalibration + * + * @brief Resets the selected ADC calibration registers. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_ResetCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_RSTCAL_Set; +} + +/********************************************************************* + * @fn ADC_GetResetCalibrationStatus + * + * @brief Gets the selected ADC reset calibration registers status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_StartCalibration + * + * @brief Starts the selected ADC calibration process. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return None + */ +void ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_CAL_Set; +} + +/********************************************************************* + * @fn ADC_GetCalibrationStatus + * + * @brief Gets the selected ADC calibration status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_GetDualModeConversionValue + * + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * + * @return RDATAR_ADDRESS - The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + return (*(__IO uint32_t *)RDATAR_ADDRESS); +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. + * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. + * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. + * ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 - External interrupt + * line 15 event selected. + * ADC_ExternalTrigInjecConv_None: Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 4. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 12bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_TempSensorVrefintCmd + * + * @brief Enables or disables the temperature sensor and Vrefint channel. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADC1->CTLR2 |= CTLR2_TSVREFE_Set; + } + else + { + ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return ITStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn TempSensor_Volt_To_Temper + * + * @brief Internal Temperature Sensor Voltage to temperature. + * + * @param Value - Voltage Value(mv). + * + * @return Temper - Temperature Value. + */ +s32 TempSensor_Volt_To_Temper(s32 Value) +{ + s32 Temper, Refer_Volt, Refer_Temper; + s32 k = 43; + + Refer_Volt = (s32)((*(u32 *)0x1FFFF898) & 0x0000FFFF); + Refer_Temper = (s32)(((*(u32 *)0x1FFFF898) >> 16) & 0x0000FFFF); + + Temper = Refer_Temper + ((Value - Refer_Volt) * 10 + (k >> 1)) / k; + + return Temper; +} + +/********************************************************************* + * @fn Get_CalibrationValue + * + * @brief Get ADCx Calibration Value. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return CalibrationValue + */ +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) +{ + __IO uint8_t i, j; + uint16_t buf[10]; + __IO uint16_t t; + + for(i = 0; i < 10; i++){ + ADC_ResetCalibration(ADCx); + while(ADC_GetResetCalibrationStatus(ADCx)); + ADC_StartCalibration(ADCx); + while(ADC_GetCalibrationStatus(ADCx)); + buf[i] = ADCx->RDATAR; + } + + for(i = 0; i < 10; i++){ + for(j = 0; j < 9; j++){ + if(buf[j] > buf[j + 1]){ + t = buf[j]; + buf[j] = buf[j + 1]; + buf[j+1] = t; + } + } + } + + t = 0; + for(i = 0; i < 6; i++){ + t += buf[i + 2]; + } + + t = (t / 6) + ((t % 6) / 3); + + return (int16_t)(2048 - (int16_t)t); +} diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_bkp.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_bkp.c index b10d455..1a1b823 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_bkp.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_bkp.c @@ -1,250 +1,250 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_bkp.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the BKP firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_bkp.h" -#include "ch32v10x_rcc.h" - -/* BKP registers bit mask */ - -/* OCTLR register bit mask */ -#define OCTLR_CAL_MASK ((uint16_t)0xFF80) -#define OCTLR_MASK ((uint16_t)0xFC7F) - -/********************************************************************* - * @fn BKP_DeInit - * - * @brief Deinitializes the BKP peripheral registers to their default reset values. - * - * @return none - */ -void BKP_DeInit(void) -{ - RCC_BackupResetCmd(ENABLE); - RCC_BackupResetCmd(DISABLE); -} - -/********************************************************************* - * @fn BKP_TamperPinLevelConfig - * - * @brief Configures the Tamper Pin active level. - * - * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. - * BKP_TamperPinLevel_High - Tamper pin active on high level. - * BKP_TamperPinLevel_Low - Tamper pin active on low level. - * - * @return none - */ -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) -{ - if(BKP_TamperPinLevel) - { - BKP->TPCTLR |= (1 << 1); - } - else - { - BKP->TPCTLR &= ~(1 << 1); - } -} - -/********************************************************************* - * @fn BKP_TamperPinCmd - * - * @brief Enables or disables the Tamper Pin activation. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void BKP_TamperPinCmd(FunctionalState NewState) -{ - if(NewState) - { - BKP->TPCTLR |= (1 << 0); - } - else - { - BKP->TPCTLR &= ~(1 << 0); - } -} - -/********************************************************************* - * @fn BKP_ITConfig - * - * @brief Enables or disables the Tamper Pin Interrupt. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void BKP_ITConfig(FunctionalState NewState) -{ - if(NewState) - { - BKP->TPCSR |= (1 << 2); - } - else - { - BKP->TPCSR &= ~(1 << 2); - } -} - -/********************************************************************* - * @fn BKP_RTCOutputConfig - * - * @brief Select the RTC output source to output on the Tamper pin. - * - * @param BKP_RTCOutputSource - specifies the RTC output source. - * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. - * BKP_RTCOutputSource_CalibClock - output the RTC clock with - * frequency divided by 64 on the Tamper pin. - * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal - * on the Tamper pin. - * BKP_RTCOutputSource_Second - output the RTC Second pulse - * signal on the Tamper pin. - * - * @return none - */ -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) -{ - uint16_t tmpreg = 0; - - tmpreg = BKP->OCTLR; - tmpreg &= OCTLR_MASK; - tmpreg |= BKP_RTCOutputSource; - BKP->OCTLR = tmpreg; -} - -/********************************************************************* - * @fn BKP_SetRTCCalibrationValue - * - * @brief Sets RTC Clock Calibration value. - * - * @param CalibrationValue - specifies the RTC Clock Calibration value. - * This parameter must be a number between 0 and 0x1F. - * - * @return none - */ -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) -{ - uint16_t tmpreg = 0; - - tmpreg = BKP->OCTLR; - tmpreg &= OCTLR_CAL_MASK; - tmpreg |= CalibrationValue; - BKP->OCTLR = tmpreg; -} - -/********************************************************************* - * @fn BKP_WriteBackupRegister - * - * @brief Writes user data to the specified Data Backup Register. - * - * @param BKP_DR - specifies the Data Backup Register. - * Data - data to write. - * - * @return none - */ -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - *(__IO uint32_t *)tmp = Data; -} - -/********************************************************************* - * @fn BKP_ReadBackupRegister - * - * @brief Reads data from the specified Data Backup Register. - * - * @param BKP_DR - specifies the Data Backup Register. - * This parameter can be BKP_DRx where x=[1, 42]. - * - * @return none - */ -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - return (*(__IO uint16_t *)tmp); -} - -/********************************************************************* - * @fn BKP_GetFlagStatus - * - * @brief Checks whether the Tamper Pin Event flag is set or not. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus BKP_GetFlagStatus(void) -{ - if(BKP->TPCSR & (1 << 8)) - { - return SET; - } - else - { - return RESET; - } -} - -/********************************************************************* - * @fn BKP_ClearFlag - * - * @brief Clears Tamper Pin Event pending flag. - * - * @return none - */ -void BKP_ClearFlag(void) -{ - BKP->TPCSR |= BKP_CTE; -} - -/********************************************************************* - * @fn BKP_GetITStatus - * - * @brief Checks whether the Tamper Pin Interrupt has occurred or not. - * - * @return ITStatus - SET or RESET. - */ -ITStatus BKP_GetITStatus(void) -{ - if(BKP->TPCSR & (1 << 9)) - { - return SET; - } - else - { - return RESET; - } -} - -/********************************************************************* - * @fn BKP_ClearITPendingBit - * - * @brief Clears Tamper Pin Interrupt pending bit. - * - * @return none - */ -void BKP_ClearITPendingBit(void) -{ - BKP->TPCSR |= BKP_CTI; -} - - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_bkp.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/06 + * Description : This file provides all the BKP firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_bkp.h" +#include "ch32v10x_rcc.h" + +/* BKP registers bit mask */ + +/* OCTLR register bit mask */ +#define OCTLR_CAL_MASK ((uint16_t)0xFF80) +#define OCTLR_MASK ((uint16_t)0xFC7F) + +/********************************************************************* + * @fn BKP_DeInit + * + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * + * @return none + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/********************************************************************* + * @fn BKP_TamperPinLevelConfig + * + * @brief Configures the Tamper Pin active level. + * + * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. + * BKP_TamperPinLevel_High - Tamper pin active on high level. + * BKP_TamperPinLevel_Low - Tamper pin active on low level. + * + * @return none + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + if(BKP_TamperPinLevel) + { + BKP->TPCTLR |= (1 << 1); + } + else + { + BKP->TPCTLR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn BKP_TamperPinCmd + * + * @brief Enables or disables the Tamper Pin activation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCTLR |= (1 << 0); + } + else + { + BKP->TPCTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn BKP_ITConfig + * + * @brief Enables or disables the Tamper Pin Interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_ITConfig(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCSR |= (1 << 2); + } + else + { + BKP->TPCSR &= ~(1 << 2); + } +} + +/********************************************************************* + * @fn BKP_RTCOutputConfig + * + * @brief Select the RTC output source to output on the Tamper pin. + * + * @param BKP_RTCOutputSource - specifies the RTC output source. + * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. + * BKP_RTCOutputSource_CalibClock - output the RTC clock with + * frequency divided by 64 on the Tamper pin. + * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal + * on the Tamper pin. + * BKP_RTCOutputSource_Second - output the RTC Second pulse + * signal on the Tamper pin. + * + * @return none + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_MASK; + tmpreg |= BKP_RTCOutputSource; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_SetRTCCalibrationValue + * + * @brief Sets RTC Clock Calibration value. + * + * @param CalibrationValue - specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x7F. + * + * @return none + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_CAL_MASK; + tmpreg |= CalibrationValue; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_WriteBackupRegister + * + * @brief Writes user data to the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * Data - data to write. + * + * @return none + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn BKP_ReadBackupRegister + * + * @brief Reads data from the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * This parameter can be BKP_DRx where x=[1, 42]. + * + * @return none + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn BKP_GetFlagStatus + * + * @brief Checks whether the Tamper Pin Event flag is set or not. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus BKP_GetFlagStatus(void) +{ + if(BKP->TPCSR & (1 << 8)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearFlag + * + * @brief Clears Tamper Pin Event pending flag. + * + * @return none + */ +void BKP_ClearFlag(void) +{ + BKP->TPCSR |= BKP_CTE; +} + +/********************************************************************* + * @fn BKP_GetITStatus + * + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * + * @return ITStatus - SET or RESET. + */ +ITStatus BKP_GetITStatus(void) +{ + if(BKP->TPCSR & (1 << 9)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearITPendingBit + * + * @brief Clears Tamper Pin Interrupt pending bit. + * + * @return none + */ +void BKP_ClearITPendingBit(void) +{ + BKP->TPCSR |= BKP_CTI; +} + + + + + + diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_crc.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_crc.c index 68c86ed..0822b14 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_crc.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_crc.c @@ -1,105 +1,105 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_crc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the CRC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_crc.h" - -/********************************************************************* - * @fn CRC_ResetDR - * - * @brief Resets the CRC Data register (DR). - * - * @return none - */ -void CRC_ResetDR(void) -{ - CRC->CTLR = CRC_CTLR_RESET; -} - -/********************************************************************* - * @fn CRC_CalcCRC - * - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * - * @param Data - data word(32-bit) to compute its CRC. - * - * @return 32-bit CRC. - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DATAR = Data; - - return (CRC->DATAR); -} - -/********************************************************************* - * @fn CRC_CalcBlockCRC - * - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * - * @param pBuffer - pointer to the buffer containing the data to be computed. - * BufferLength - length of the buffer to be computed. - * - * @return 32-bit CRC. - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DATAR = pBuffer[index]; - } - - return (CRC->DATAR); -} - -/********************************************************************* - * @fn CRC_GetCRC - * - * @brief Returns the current CRC value. - * - * @return 32-bit CRC. - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DATAR); -} - -/********************************************************************* - * @fn CRC_SetIDRegister - * - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * - * @param IDValue - 8-bit value to be stored in the ID register. - * - * @return none - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDATAR = IDValue; -} - -/********************************************************************* - * @fn CRC_GetIDRegister - * - * @brief Returns the 8-bit data stored in the Independent Data(ID) register. - * - * @return 8-bit value of the ID register. - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDATAR); -} - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_crc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the CRC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_crc.h" + +/********************************************************************* + * @fn CRC_ResetDR + * + * @brief Resets the CRC Data register (DR). + * + * @return none + */ +void CRC_ResetDR(void) +{ + CRC->CTLR = CRC_CTLR_RESET; +} + +/********************************************************************* + * @fn CRC_CalcCRC + * + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * + * @param Data - data word(32-bit) to compute its CRC. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DATAR = Data; + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_CalcBlockCRC + * + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * + * @param pBuffer - pointer to the buffer containing the data to be computed. + * BufferLength - length of the buffer to be computed. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DATAR = pBuffer[index]; + } + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_GetCRC + * + * @brief Returns the current CRC value. + * + * @return 32-bit CRC. + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_SetIDRegister + * + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * + * @param IDValue - 8-bit value to be stored in the ID register. + * + * @return none + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDATAR = IDValue; +} + +/********************************************************************* + * @fn CRC_GetIDRegister + * + * @brief Returns the 8-bit data stored in the Independent Data(ID) register. + * + * @return 8-bit value of the ID register. + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDATAR); +} + + + + + diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_dbgmcu.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_dbgmcu.c index c1479aa..09147b4 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_dbgmcu.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_dbgmcu.c @@ -1,101 +1,101 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_dbgmcu.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the DBGMCU firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_dbgmcu.h" - -#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) - -/********************************************************************* - * @fn DBGMCU_GetREVID - * - * @brief Returns the device revision identifier. - * - * @return Revision identifier. - */ -uint32_t DBGMCU_GetREVID(void) -{ - return ((*(uint32_t *)0x1FFFF884) >> 16); -} - -/********************************************************************* - * @fn DBGMCU_GetDEVID - * - * @brief Returns the device identifier. - * - * @return Device identifier. - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return ((*(uint32_t *)0x1FFFF884) & IDCODE_DEVID_MASK); -} - - -/********************************************************************* - * @fn DBGMCU_Config - * - * @brief Configures the specified peripheral and low power mode behavior - * when the MCU under Debug mode. - * - * @param DBGMCU_Periph - specifies the peripheral and low power mode. - * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted - * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted - * DBGMCU_I2C1_SMBUS_TIMEOUT - I2C1 SMBUS timeout mode stopped when Core is halted - * DBGMCU_I2C2_SMBUS_TIMEOUT - I2C2 SMBUS timeout mode stopped when Core is halted - * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted - * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted - * DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted - * DBGMCU_TIM4_STOP - TIM4 counter stopped when Core is halted - * DBGMCU_SLEEP - Keep debugger connection during SLEEP mode - * DBGMCU_STOP - Keep debugger connection during STOP mode - * DBGMCU_STANDBY - Keep debugger connection during STANDBY mode - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - if((DBGMCU_Periph == DBGMCU_SLEEP) || (DBGMCU_Periph == DBGMCU_STOP) || (DBGMCU_Periph == DBGMCU_STANDBY)) - { - if(NewState != DISABLE) - { - DBGMCU->CFGR1 |= DBGMCU_Periph; - } - else - { - DBGMCU->CFGR1 &= ~DBGMCU_Periph; - } - } - else - { - if(NewState != DISABLE) - { - DBGMCU->CFGR0 |= DBGMCU_Periph; - } - else - { - DBGMCU->CFGR0 &= ~DBGMCU_Periph; - } - } -} -/********************************************************************* - * @fn DBGMCU_GetCHIPID - * - * @brief Returns the CHIP identifier. - * - * @return Device identifier. - * ChipID List- - * CH32V103C8T6-0x25004102 - * CH32V103R8T6-0x2500410F - */ -uint32_t DBGMCU_GetCHIPID( void ) -{ - return( *( uint32_t * )0x1FFFF884 ); +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_dbgmcu.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the DBGMCU firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_dbgmcu.h" + +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return ((*(uint32_t *)0x1FFFF884) >> 16); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return ((*(uint32_t *)0x1FFFF884) & IDCODE_DEVID_MASK); +} + + +/********************************************************************* + * @fn DBGMCU_Config + * + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * + * @param DBGMCU_Periph - specifies the peripheral and low power mode. + * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted + * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted + * DBGMCU_I2C1_SMBUS_TIMEOUT - I2C1 SMBUS timeout mode stopped when Core is halted + * DBGMCU_I2C2_SMBUS_TIMEOUT - I2C2 SMBUS timeout mode stopped when Core is halted + * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted + * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted + * DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted + * DBGMCU_TIM4_STOP - TIM4 counter stopped when Core is halted + * DBGMCU_SLEEP - Keep debugger connection during SLEEP mode + * DBGMCU_STOP - Keep debugger connection during STOP mode + * DBGMCU_STANDBY - Keep debugger connection during STANDBY mode + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + if((DBGMCU_Periph == DBGMCU_SLEEP) || (DBGMCU_Periph == DBGMCU_STOP) || (DBGMCU_Periph == DBGMCU_STANDBY)) + { + if(NewState != DISABLE) + { + DBGMCU->CFGR1 |= DBGMCU_Periph; + } + else + { + DBGMCU->CFGR1 &= ~DBGMCU_Periph; + } + } + else + { + if(NewState != DISABLE) + { + DBGMCU->CFGR0 |= DBGMCU_Periph; + } + else + { + DBGMCU->CFGR0 &= ~DBGMCU_Periph; + } + } +} +/********************************************************************* + * @fn DBGMCU_GetCHIPID + * + * @brief Returns the CHIP identifier. + * + * @return Device identifier. + * ChipID List- + * CH32V103C8T6-0x25004102 + * CH32V103R8T6-0x2500410F + */ +uint32_t DBGMCU_GetCHIPID( void ) +{ + return( *( uint32_t * )0x1FFFF884 ); } \ No newline at end of file diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_dma.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_dma.c index 19238b1..0ade3e1 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_dma.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_dma.c @@ -1,552 +1,552 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_dma.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the DMA firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_dma.h" -#include "ch32v10x_rcc.h" - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) -#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) -#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) -#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) -#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) -#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) -#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) - -/* DMA2 Channelx interrupt pending bit masks */ -#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) -#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) -#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) -#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) -#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) - -/* DMA2 FLAG mask */ -#define FLAG_Mask ((uint32_t)0x10000000) - -/* DMA registers Masks */ -#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) - -/********************************************************************* - * @fn DMA_DeInit - * - * @brief Deinitializes the DMAy Channelx registers to their default - * reset values. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * - * @return none - */ -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) -{ - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - DMAy_Channelx->CFGR = 0; - DMAy_Channelx->CNTR = 0; - DMAy_Channelx->PADDR = 0; - DMAy_Channelx->MADDR = 0; - if(DMAy_Channelx == DMA1_Channel1) - { - DMA1->INTFCR |= DMA1_Channel1_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel2) - { - DMA1->INTFCR |= DMA1_Channel2_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel3) - { - DMA1->INTFCR |= DMA1_Channel3_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel4) - { - DMA1->INTFCR |= DMA1_Channel4_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel5) - { - DMA1->INTFCR |= DMA1_Channel5_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel6) - { - DMA1->INTFCR |= DMA1_Channel6_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel7) - { - DMA1->INTFCR |= DMA1_Channel7_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel1) - { - DMA2->INTFCR |= DMA2_Channel1_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel2) - { - DMA2->INTFCR |= DMA2_Channel2_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel3) - { - DMA2->INTFCR |= DMA2_Channel3_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel4) - { - DMA2->INTFCR |= DMA2_Channel4_IT_Mask; - } - else - { - if(DMAy_Channelx == DMA2_Channel5) - { - DMA2->INTFCR |= DMA2_Channel5_IT_Mask; - } - } -} - -/********************************************************************* - * @fn DMA_Init - * - * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - tmpreg = DMAy_Channelx->CFGR; - tmpreg &= CFGR_CLEAR_Mask; - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - DMAy_Channelx->CFGR = tmpreg; - DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; - DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; - DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/********************************************************************* - * @fn DMA_StructInit - * - * @brief Fills each DMA_InitStruct member with its default value. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) -{ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - DMA_InitStruct->DMA_BufferSize = 0; - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/********************************************************************* - * @fn DMA_Cmd - * - * @brief Enables or disables the specified DMAy Channelx. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_CFGR1_EN; - } - else - { - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - } -} - -/********************************************************************* - * @fn DMA_ITConfig - * - * @brief Enables or disables the specified DMAy Channelx interrupts. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * DMA_IT - specifies the DMA interrupts sources to be enabled - * or disabled. - * DMA_IT_TC - Transfer complete interrupt mask - * DMA_IT_HT - Half transfer interrupt mask - * DMA_IT_TE - Transfer error interrupt mask - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_IT; - } - else - { - DMAy_Channelx->CFGR &= ~DMA_IT; - } -} - -/********************************************************************* - * @fn DMA_SetCurrDataCounter - * - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * DataNumber - The number of data units in the current DMAy Channelx - * transfer. - * - * @return none - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) -{ - DMAy_Channelx->CNTR = DataNumber; -} - -/********************************************************************* - * @fn DMA_GetCurrDataCounter - * - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * - * @return DataNumber - The number of remaining data units in the current - * DMAy Channelx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) -{ - return ((uint16_t)(DMAy_Channelx->CNTR)); -} - -/********************************************************************* - * @fn DMA_GetFlagStatus - * - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. - * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. - * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. - * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. - * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. - * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. - * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. - * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. - * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. - * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. - * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. - * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. - * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. - * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. - * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. - * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. - * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. - * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. - * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. - * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. - * - * @return The new state of DMAy_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - if((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - tmpreg = DMA2->INTFR; - } - else - { - tmpreg = DMA1->INTFR; - } - - if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearFlag - * - * @brief Clears the DMAy Channelx's pending flags. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. - * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. - * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. - * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. - * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. - * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. - * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. - * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. - * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. - * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. - * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. - * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. - * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. - * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. - * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. - * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. - * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. - * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. - * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. - * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. - * - * @return none - */ -void DMA_ClearFlag(uint32_t DMAy_FLAG) -{ - if((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - DMA2->INTFCR = DMAy_FLAG; - } - else - { - DMA1->INTFCR = DMAy_FLAG; - } -} - -/********************************************************************* - * @fn DMA_GetITStatus - * - * @brief Checks whether the specified DMAy Channelx interrupt has - * occurred or not. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * DMA2_IT_GL1 - DMA2 Channel1 global flag. - * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. - * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. - * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. - * DMA2_IT_GL2 - DMA2 Channel2 global flag. - * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. - * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. - * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. - * DMA2_IT_GL3 - DMA2 Channel3 global flag. - * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. - * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. - * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. - * DMA2_IT_GL4 - DMA2 Channel4 global flag. - * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. - * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. - * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. - * DMA2_IT_GL5 - DMA2 Channel5 global flag. - * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. - * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. - * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. - * - * @return The new state of DMAy_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMAy_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - if((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - tmpreg = DMA2->INTFR; - } - else - { - tmpreg = DMA1->INTFR; - } - - if((tmpreg & DMAy_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearITPendingBit - * - * @brief Clears the DMAy Channelx's interrupt pending bits. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * DMA2_IT_GL1 - DMA2 Channel1 global flag. - * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. - * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. - * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. - * DMA2_IT_GL2 - DMA2 Channel2 global flag. - * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. - * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. - * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. - * DMA2_IT_GL3 - DMA2 Channel3 global flag. - * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. - * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. - * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. - * DMA2_IT_GL4 - DMA2 Channel4 global flag. - * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. - * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. - * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. - * DMA2_IT_GL5 - DMA2 Channel5 global flag. - * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. - * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. - * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. - * - * @return none - */ -void DMA_ClearITPendingBit(uint32_t DMAy_IT) -{ - if((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - DMA2->INTFCR = DMAy_IT; - } - else - { - DMA1->INTFCR = DMAy_IT; - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_dma.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the DMA firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_dma.h" +#include "ch32v10x_rcc.h" + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel1) + { + DMA2->INTFCR |= DMA2_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel2) + { + DMA2->INTFCR |= DMA2_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel3) + { + DMA2->INTFCR |= DMA2_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel4) + { + DMA2->INTFCR |= DMA2_Channel4_IT_Mask; + } + else + { + if(DMAy_Channelx == DMA2_Channel5) + { + DMA2->INTFCR |= DMA2_Channel5_IT_Mask; + } + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. + * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. + * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. + * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. + * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. + * + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + if((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + tmpreg = DMA2->INTFR; + } + else + { + tmpreg = DMA1->INTFR; + } + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. + * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. + * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. + * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. + * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. + * + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + if((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + DMA2->INTFCR = DMAy_FLAG; + } + else + { + DMA1->INTFCR = DMAy_FLAG; + } +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_IT_GL2 - DMA2 Channel2 global flag. + * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_IT_GL3 - DMA2 Channel3 global flag. + * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_IT_GL4 - DMA2 Channel4 global flag. + * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_IT_GL5 - DMA2 Channel5 global flag. + * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. + * + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + if((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + tmpreg = DMA2->INTFR; + } + else + { + tmpreg = DMA1->INTFR; + } + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_IT_GL2 - DMA2 Channel2 global flag. + * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_IT_GL3 - DMA2 Channel3 global flag. + * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_IT_GL4 - DMA2 Channel4 global flag. + * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_IT_GL5 - DMA2 Channel5 global flag. + * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. + * + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + if((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + DMA2->INTFCR = DMAy_IT; + } + else + { + DMA1->INTFCR = DMAy_IT; + } +} diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_exti.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_exti.c index e9dee42..37ee6ae 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_exti.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_exti.c @@ -1,182 +1,182 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_exti.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the EXTI firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_exti.h" - -/* No interrupt selected */ -#define EXTI_LINENONE ((uint32_t)0x00000) - -/********************************************************************* - * @fn EXTI_DeInit - * - * @brief Deinitializes the EXTI peripheral registers to their default - * reset values. - * - * @return none. - */ -void EXTI_DeInit(void) -{ - EXTI->INTENR = 0x00000000; - EXTI->EVENR = 0x00000000; - EXTI->RTENR = 0x00000000; - EXTI->FTENR = 0x00000000; - EXTI->INTFR = 0x000FFFFF; -} - -/********************************************************************* - * @fn EXTI_Init - * - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) -{ - uint32_t tmp = 0; - - tmp = (uint32_t)EXTI_BASE; - if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; - if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/********************************************************************* - * @fn EXTI_StructInit - * - * @brief Fills each EXTI_InitStruct member with its reset value. - * - * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/********************************************************************* - * @fn EXTI_GenerateSWInterrupt - * - * @brief Generates a Software interrupt. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none. - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - EXTI->SWIEVR |= EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetFlagStatus - * - * @brief Checks whether the specified EXTI line flag is set or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearFlag - * - * @brief Clears the EXTI's line pending flags. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetITStatus - * - * @brief Checks whether the specified EXTI line is asserted or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = EXTI->INTENR & EXTI_Line; - if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearITPendingBit - * - * @brief Clears the EXTI's line pending bits. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_exti.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the EXTI firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_exti.h" + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x000FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_flash.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_flash.c index fb557aa..7aa971d 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_flash.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_flash.c @@ -1,958 +1,1194 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_flash.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the FLASH firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - ***************************************************************************************/ -#include "ch32v10x_flash.h" - -/* Flash Access Control Register bits */ -#define ACR_LATENCY_Mask ((uint32_t)0x00000038) -#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) -#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) - -/* Flash Access Control Register bits */ -#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) - -/* Flash Control Register bits */ -#define CR_PG_Set ((uint32_t)0x00000001) -#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) -#define CR_FAST_LOCK_Set ((uint32_t)0x00008000) -#define CR_PAGE_PG ((uint32_t)0x00010000) -#define CR_PAGE_ER ((uint32_t)0x00020000) -#define CR_BUF_LOAD ((uint32_t)0x00040000) -#define CR_BUF_RST ((uint32_t)0x00080000) - -/* FLASH Status Register bits */ -#define SR_BSY ((uint32_t)0x00000001) -#define SR_PGERR ((uint32_t)0x00000004) -#define SR_WRPRTERR ((uint32_t)0x00000010) -#define SR_EOP ((uint32_t)0x00000020) - -/* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) -#define OB_USER_BFB2 ((uint16_t)0x0008) - -/* FLASH Keys */ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) - -/* FLASH BANK address */ -#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) - -/* Delay definition */ -#define EraseTimeout ((uint32_t)0x000B0000) -#define ProgramTimeout ((uint32_t)0x00002000) - -/* Flash Program Vaild Address */ -#define ValidAddrStart (FLASH_BASE) -#define ValidAddrEnd (FLASH_BASE + 0x10000) - -/******************************************************************************** - * @fn FLASH_SetLatency - * - * @brief Sets the code latency value. - * - * @param FLASH_Latency - specifies the FLASH Latency value. - * FLASH_Latency_0 - FLASH Zero Latency cycle - * FLASH_Latency_1 - FLASH One Latency cycle - * FLASH_Latency_2 - FLASH Two Latency cycles - * - * @return None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - tmpreg = FLASH->ACTLR; - tmpreg &= ACR_LATENCY_Mask; - tmpreg |= FLASH_Latency; - FLASH->ACTLR = tmpreg; -} - -/******************************************************************************** - * @fn FLASH_HalfCycleAccessCmd - * - * @brief Enables or disables the Half cycle flash access. - * - * @param FLASH_HalfCycleAccess - specifies the FLASH Half cycle Access mode. - * FLASH_HalfCycleAccess_Enable - FLASH Half Cycle Enable - * FLASH_HalfCycleAccess_Disable - FLASH Half Cycle Disable - * - * @return None - */ -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) -{ - FLASH->ACTLR &= ACR_HLFCYA_Mask; - FLASH->ACTLR |= FLASH_HalfCycleAccess; -} - -/******************************************************************************** - * @fn FLASH_PrefetchBufferCmd - * - * @brief Enables or disables the Prefetch Buffer. - * - * @param FLASH_PrefetchBuffer - specifies the Prefetch buffer status. - * FLASH_PrefetchBuffer_Enable - FLASH Prefetch Buffer Enable - * FLASH_PrefetchBuffer_Disable - FLASH Prefetch Buffer Disable - * - * @return None - */ -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) -{ - FLASH->ACTLR &= ACR_PRFTBE_Mask; - FLASH->ACTLR |= FLASH_PrefetchBuffer; -} - -/******************************************************************************** - * @fn FLASH_Unlock - * - * @brief Unlocks the FLASH Program Erase Controller. - * - * @return None - */ -void FLASH_Unlock(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -/******************************************************************************** - * @fn FLASH_UnlockBank1 - * - * @brief Unlocks the FLASH Bank1 Program Erase Controller. - * equivalent to FLASH_Unlock function. - * - * @return None - */ -void FLASH_UnlockBank1(void) -{ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -/******************************************************************************** - * @fn FLASH_Lock - * - * @brief Locks the FLASH Program Erase Controller. - * - * @return None - */ -void FLASH_Lock(void) -{ - FLASH->CTLR |= CR_LOCK_Set; -} - -/******************************************************************************** - * @fn FLASH_LockBank1 - * - * @brief Locks the FLASH Bank1 Program Erase Controller. - * - * @return None - */ -void FLASH_LockBank1(void) -{ - FLASH->CTLR |= CR_LOCK_Set; -} - -/******************************************************************************** - * @fn FLASH_ErasePage - * - * @brief Erases a specified FLASH page. - * - * @param Page_Address - The page address to be erased. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_PER_Set; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_PER_Reset; - } - *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Page_Address & 0xFFFFFFFC) ^ 0x00001000); - return status; -} - -/******************************************************************************** - * @fn FLASH_EraseAllPages - * - * @brief Erases all FLASH pages. - * - * @return FLASH Status - The returned value can be:FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_MER_Set; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_MER_Reset; - } - - return status; -} - -/******************************************************************************** - * @fn FLASH_EraseAllBank1Pages - * - * @brief Erases all Bank1 FLASH pages. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllBank1Pages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_MER_Set; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - FLASH->CTLR &= CR_MER_Reset; - } - return status; -} - -/******************************************************************************** - * @fn FLASH_EraseOptionBytes - * - * @brief Erases the FLASH option bytes. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseOptionBytes(void) -{ - uint16_t rdptmp = RDP_Key; - - FLASH_Status status = FLASH_COMPLETE; - if(FLASH_GetReadOutProtectionStatus() != RESET) - { - rdptmp = 0x00; - } - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR &= CR_OPTER_Reset; - FLASH->CTLR |= CR_OPTPG_Set; - OB->RDPR = (uint16_t)rdptmp; - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - } - return status; -} - -/********************************************************************* - * @fn FLASH_ProgramWord - * - * @brief Programs a word at a specified address. - * - * @param Address - specifies the address to be programmed. - * Data - specifies the data to be programmed. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_PG_Set; - - *(__IO uint16_t *)Address = (uint16_t)Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - tmp = Address + 2; - *(__IO uint16_t *)tmp = Data >> 16; - status = FLASH_WaitForLastOperation(ProgramTimeout); - FLASH->CTLR &= CR_PG_Reset; - } - else - { - FLASH->CTLR &= CR_PG_Reset; - } - } - *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Address & 0xFFFFFFFC) ^ 0x00001000); - return status; -} - -/********************************************************************* - * @fn FLASH_ProgramHalfWord - * - * @brief Programs a half word at a specified address. - * - * @param Address - specifies the address to be programmed. - * Data - specifies the data to be programmed. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_PG_Set; - *(__IO uint16_t *)Address = Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - FLASH->CTLR &= CR_PG_Reset; - } - *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Address & 0xFFFFFFFC) ^ 0x00001000); - return status; -} - -/********************************************************************* - * @fn FLASH_ProgramOptionByteData - * - * @brief Programs a half word at a specified Option Byte Data address. - * - * @param Address - specifies the address to be programmed. - * Data - specifies the data to be programmed. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - FLASH->CTLR |= CR_OPTPG_Set; - *(__IO uint16_t *)Address = Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Address & 0xFFFFFFFC) ^ 0x00001000); - return status; -} - -/********************************************************************* - * @fn FLASH_EnableWriteProtection - * - * @brief Write protects the desired sectors - * - * @param FLASH_Sectors - specifies the address of the pages to be write protected. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) -{ - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; - - FLASH_Status status = FLASH_COMPLETE; - - FLASH_Pages = (uint32_t)(~FLASH_Pages); - WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); - WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); - WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); - WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); - - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - FLASH->CTLR |= CR_OPTPG_Set; - if(WRP0_Data != 0xFF) - { - OB->WRPR0 = WRP0_Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) - { - OB->WRPR1 = WRP1_Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) - { - OB->WRPR2 = WRP2_Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if((status == FLASH_COMPLETE) && (WRP3_Data != 0xFF)) - { - OB->WRPR3 = WRP3_Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - return status; -} - -/********************************************************************* - * @fn FLASH_ReadOutProtection - * - * @brief Enables or disables the read out protection. - * - * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->CTLR &= CR_OPTER_Reset; - FLASH->CTLR |= CR_OPTPG_Set; - if(NewState != DISABLE) - { - OB->RDPR = 0x00; - } - else - { - OB->RDPR = RDP_Key; - } - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTER_Reset; - } - } - } - return status; -} - -/********************************************************************* - * @fn FLASH_UserOptionByteConfig - * - * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. - * - * @param OB_IWDG - Selects the IWDG mode - * OB_IWDG_SW - Software IWDG selected - * OB_IWDG_HW - Hardware IWDG selected - * OB_STOP - Reset event when entering STOP mode. - * OB_STOP_NoRST - No reset generated when entering in STOP - * OB_STOP_RST - Reset generated when entering in STOP - * OB_STDBY - Reset event when entering Standby mode. - * OB_STDBY_NoRST - No reset generated when entering in STANDBY - * OB_STDBY_RST - Reset generated when entering in STANDBY - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) -{ - FLASH_Status status = FLASH_COMPLETE; - - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_OPTPG_Set; - - OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); - - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - return status; -} - -/********************************************************************* - * @fn FLASH_GetUserOptionByte - * - * @brief Returns the FLASH User Option Bytes values. - * - * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint32_t FLASH_GetUserOptionByte(void) -{ - return (uint32_t)(FLASH->OBR >> 2); -} - -/********************************************************************* - * @fn FLASH_GetWriteProtectionOptionByte - * - * @brief Returns the FLASH Write Protection Option Bytes Register value. - * - * @return The FLASH Write Protection Option Bytes Register value. - */ -uint32_t FLASH_GetWriteProtectionOptionByte(void) -{ - return (uint32_t)(FLASH->WPR); -} - -/********************************************************************* - * @fn FLASH_GetReadOutProtectionStatus - * - * @brief Checks whether the FLASH Read Out Protection Status is set or not. - * - * @return FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetReadOutProtectionStatus(void) -{ - FlagStatus readoutstatus = RESET; - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - readoutstatus = SET; - } - else - { - readoutstatus = RESET; - } - return readoutstatus; -} - -/********************************************************************* - * @fn FLASH_GetPrefetchBufferStatus - * - * @brief Checks whether the FLASH Prefetch Buffer status is set or not. - * - * @return FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetPrefetchBufferStatus(void) -{ - FlagStatus bitstatus = RESET; - - if((FLASH->ACTLR & ACR_PRFTBS_Mask) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn FLASH_ITConfig - * - * @brief Enables or disables the specified FLASH interrupts. - * - * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. - * FLASH_IT_ERROR - FLASH Error Interrupt - * FLASH_IT_EOP - FLASH end of operation Interrupt - * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). - * - * @return FLASH Prefetch Buffer Status (SET or RESET). - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - FLASH->CTLR |= FLASH_IT; - } - else - { - FLASH->CTLR &= ~(uint32_t)FLASH_IT; - } -} - -/********************************************************************* - * @fn FLASH_GetFlagStatus - * - * @brief Checks whether the specified FLASH flag is set or not. - * - * @param FLASH_FLAG - specifies the FLASH flag to check. - * FLASH_FLAG_BSY - FLASH Busy flag - * FLASH_FLAG_PGERR - FLASH Program error flag - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * FLASH_FLAG_OPTERR - FLASH Option Byte error flag - * - * @return The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - return bitstatus; -} - -/********************************************************************* - * @fn FLASH_ClearFlag - * - * @brief Clears the FLASH's pending flags. - * - * @param FLASH_FLAG - specifies the FLASH flags to clear. - * FLASH_FLAG_PGERR - FLASH Program error flag - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * - * @return none - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - FLASH->STATR = FLASH_FLAG; -} - -/********************************************************************* - * @fn FLASH_GetStatus - * - * @brief Returns the FLASH Status. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_PGERR) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_GetBank1Status - * - * @brief Returns the FLASH Bank1 Status. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetBank1Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_BANK1_PGERR) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_WaitForLastOperation - * - * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_WaitForLastBank1Operation - * - * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_Unlock_Fast - * - * @brief Unlocks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Unlock_Fast(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - - /* Fast program mode unlock */ - FLASH->MODEKEYR = FLASH_KEY1; - FLASH->MODEKEYR = FLASH_KEY2; -} - -/********************************************************************* - * @fn FLASH_Lock_Fast - * - * @brief Locks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Lock_Fast(void) -{ - FLASH->CTLR |= CR_FAST_LOCK_Set; -} - -/********************************************************************* - * @fn FLASH_BufReset - * - * @brief Flash Buffer reset. - * - * @return none - */ -void FLASH_BufReset(void) -{ - FLASH->CTLR |= CR_PAGE_PG; - FLASH->CTLR |= CR_BUF_RST; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; -} - -/********************************************************************* - * @fn FLASH_BufLoad - * - * @brief Flash Buffer load(128 bit). - * - * @param Address - specifies the address to be programmed. - * Data0 - specifies the data0 to be programmed. - * Data1 - specifies the data1 to be programmed. - * Data2 - specifies the data2 to be programmed. - * Data3 - specifies the data3 to be programmed. - * - * @return none - */ -void FLASH_BufLoad(uint32_t Address, uint32_t Data0, uint32_t Data1, uint32_t Data2, uint32_t Data3) -{ - if((Address >= ValidAddrStart) && (Address < ValidAddrEnd)) - { - FLASH->CTLR |= CR_PAGE_PG; - *(__IO uint32_t *)(Address + 0x00) = Data0; - *(__IO uint32_t *)(Address + 0x04) = Data1; - *(__IO uint32_t *)(Address + 0x08) = Data2; - *(__IO uint32_t *)(Address + 0x0C) = Data3; - FLASH->CTLR |= CR_BUF_LOAD; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; - *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Address & 0xFFFFFFFC) ^ 0x00001000); - } -} - -/********************************************************************* - * @fn FLASH_ErasePage_Fast - * - * @brief Erases a specified FLASH page (1page = 128Byte). - * - * @param Page_Address - The page address to be erased. - * - * @return none - */ -void FLASH_ErasePage_Fast(uint32_t Page_Address) -{ - if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) - { - FLASH->CTLR |= CR_PAGE_ER; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_ER; - *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Page_Address & 0xFFFFFFFC) ^ 0x00001000); - } -} - -/********************************************************************* - * @fn FLASH_ProgramPage_Fast - * - * @brief Program a specified FLASH page (1page = 256Byte). - * - * @param Page_Address - The page address to be programed. - * - * @return none - */ -void FLASH_ProgramPage_Fast(uint32_t Page_Address) -{ - if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) - { - FLASH->CTLR |= CR_PAGE_PG; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; - *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Page_Address & 0xFFFFFFFC) ^ 0x00001000); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_flash.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the FLASH firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "ch32v10x_flash.h" + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) +#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) +#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) + +/* Flash Access Control Register bits */ +#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FLOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BUF_LOAD ((uint32_t)0x00040000) +#define CR_BUF_RST ((uint32_t)0x00080000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_PGERR ((uint32_t)0x00000004) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x10000) + +/* FLASH Size */ +#define Size_128B 0x80 +#define Size_1KB 0x400 + +/******************************************************************************** + * @fn FLASH_SetLatency + * + * @brief Sets the code latency value. + * + * @param FLASH_Latency - specifies the FLASH Latency value. + * FLASH_Latency_0 - FLASH Zero Latency cycle + * FLASH_Latency_1 - FLASH One Latency cycle + * FLASH_Latency_2 - FLASH Two Latency cycles + * + * @return None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + tmpreg = FLASH->ACTLR; + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + FLASH->ACTLR = tmpreg; +} + +/******************************************************************************** + * @fn FLASH_HalfCycleAccessCmd + * + * @brief Enables or disables the Half cycle flash access. + * + * @param FLASH_HalfCycleAccess - specifies the FLASH Half cycle Access mode. + * FLASH_HalfCycleAccess_Enable - FLASH Half Cycle Enable + * FLASH_HalfCycleAccess_Disable - FLASH Half Cycle Disable + * + * @return None + */ +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) +{ + FLASH->ACTLR &= ACR_HLFCYA_Mask; + FLASH->ACTLR |= FLASH_HalfCycleAccess; +} + +/******************************************************************************** + * @fn FLASH_PrefetchBufferCmd + * + * @brief Enables or disables the Prefetch Buffer. + * + * @param FLASH_PrefetchBuffer - specifies the Prefetch buffer status. + * FLASH_PrefetchBuffer_Enable - FLASH Prefetch Buffer Enable + * FLASH_PrefetchBuffer_Disable - FLASH Prefetch Buffer Disable + * + * @return None + */ +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) +{ + FLASH->ACTLR &= ACR_PRFTBE_Mask; + FLASH->ACTLR |= FLASH_PrefetchBuffer; +} + +/******************************************************************************** + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/******************************************************************************** + * @fn FLASH_UnlockBank1 + * + * @brief Unlocks the FLASH Bank1 Program Erase Controller. + * equivalent to FLASH_Unlock function. + * + * @return None + */ +void FLASH_UnlockBank1(void) +{ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/******************************************************************************** + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/******************************************************************************** + * @fn FLASH_LockBank1 + * + * @brief Locks the FLASH Bank1 Program Erase Controller. + * + * @return None + */ +void FLASH_LockBank1(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/******************************************************************************** + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page. + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Page_Address & 0xFFFFFFFC) ^ 0x00001000); + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - The returned value can be:FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseAllBank1Pages + * + * @brief Erases all Bank1 FLASH pages. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank1Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + + FLASH_Status status = FLASH_COMPLETE; + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= CR_OPTER_Reset; + FLASH->CTLR |= CR_OPTPG_Set; + OB->RDPR = (uint16_t)rdptmp; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + } + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramWord + * + * @brief Programs a word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + + *(__IO uint16_t *)Address = (uint16_t)Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + tmp = Address + 2; + *(__IO uint16_t *)tmp = Data >> 16; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + else + { + FLASH->CTLR &= CR_PG_Reset; + } + } + *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Address & 0xFFFFFFFC) ^ 0x00001000); + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramHalfWord + * + * @brief Programs a half word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + *(__IO uint16_t *)Address = Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Address & 0xFFFFFFFC) ^ 0x00001000); + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramOptionByteData + * + * @brief Programs a half word at a specified Option Byte Data address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + FLASH->CTLR |= CR_OPTPG_Set; + *(__IO uint16_t *)Address = Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Address & 0xFFFFFFFC) ^ 0x00001000); + return status; +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Sectors - specifies the address of the pages to be write protected. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + FLASH->CTLR |= CR_OPTPG_Set; + if(WRP0_Data != 0xFF) + { + OB->WRPR0 = WRP0_Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRPR1 = WRP1_Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) + { + OB->WRPR2 = WRP2_Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if((status == FLASH_COMPLETE) && (WRP3_Data != 0xFF)) + { + OB->WRPR3 = WRP3_Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + return status; +} + +/********************************************************************* + * @fn FLASH_ReadOutProtection + * + * @brief Enables or disables the read out protection. + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= CR_OPTER_Reset; + FLASH->CTLR |= CR_OPTPG_Set; + if(NewState != DISABLE) + { + OB->RDPR = 0x00; + } + else + { + OB->RDPR = RDP_Key; + } + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTER_Reset; + } + } + } + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. + * + * @param OB_IWDG - Selects the IWDG mode + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STOP - Reset event when entering STOP mode. + * OB_STOP_NoRST - No reset generated when entering in STOP + * OB_STOP_RST - Reset generated when entering in STOP + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY + * OB_STDBY_RST - Reset generated when entering in STANDBY + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_OPTPG_Set; + + OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_GetPrefetchBufferStatus + * + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if((FLASH->ACTLR & ACR_PRFTBS_Mask) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt + * FLASH_IT_EOP - FLASH end of operation Interrupt + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_PGERR - FLASH Program error flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_PGERR - FLASH Program error flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + FLASH->STATR = FLASH_FLAG; +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_FLOCK_Set; +} + +/********************************************************************* + * @fn FLASH_BufReset + * + * @brief Flash Buffer reset. + * + * @return none + */ +void FLASH_BufReset(void) +{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_BufLoad + * + * @brief Flash Buffer load(128 bit). + * + * @param Address - specifies the address to be programmed. + * Data0 - specifies the data0 to be programmed. + * Data1 - specifies the data1 to be programmed. + * Data2 - specifies the data2 to be programmed. + * Data3 - specifies the data3 to be programmed. + * + * @return none + */ +void FLASH_BufLoad(uint32_t Address, uint32_t Data0, uint32_t Data1, uint32_t Data2, uint32_t Data3) +{ + if((Address >= ValidAddrStart) && (Address < ValidAddrEnd)) + { + FLASH->CTLR |= CR_PAGE_PG; + *(__IO uint32_t *)(Address + 0x00) = Data0; + *(__IO uint32_t *)(Address + 0x04) = Data1; + *(__IO uint32_t *)(Address + 0x08) = Data2; + *(__IO uint32_t *)(Address + 0x0C) = Data3; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Address & 0xFFFFFFFC) ^ 0x00001000); + } +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 128Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) + { + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_ER; + *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Page_Address & 0xFFFFFFFC) ^ 0x00001000); + } +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address) +{ + if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) + { + FLASH->CTLR |= CR_PAGE_PG; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((Page_Address & 0xFFFFFFFC) ^ 0x00001000); + } +} + +/********************************************************************* + * @fn ROM_ERASE + * + * @brief Select erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%128 == 0). + * Cnt - Erases count. + * Erase_Size - Erases size select.The returned value can be: + * Size_1KB, Size_128B. + * + * @return none. + */ +static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) +{ + do{ + if(Erase_Size == Size_1KB) + { + FLASH->CTLR |= CR_PER_Set; + } + else if(Erase_Size == Size_128B) + { + FLASH->CTLR |= CR_PAGE_ER; + } + + FLASH->ADDR = StartAddr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + + *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((StartAddr & 0xFFFFFFFC) ^ 0x00001000); + + if(Erase_Size == Size_1KB) + { + FLASH->CTLR &= ~CR_PER_Set; + StartAddr += Size_1KB; + } + else if(Erase_Size == Size_128B) + { + FLASH->CTLR &= ~CR_PAGE_ER; + StartAddr += Size_128B; + } + }while(--Cnt); +} + +/********************************************************************* + * @fn FLASH_ROM_ERASE + * + * @brief Erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%128 == 0). + * Length - Erases Flash start Length(Length%128 == 0). + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_ERASE( uint32_t StartAddr, uint32_t Length ) +{ + uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_128B-1)) || (Length & (Size_128B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + Addr0 = StartAddr; + + if(Length >= Size_1KB) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_128B) + { + Length0 = Length; + } + + /* Erase 1KB */ + if(Length0 >= Size_1KB) //front + { + Length = Length0; + if(Addr0 & (Size_1KB - 1)) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB); + } + + if(Length1 >= Size_1KB) //back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_1KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1))); + Length1 = (StartAddr + Length1) & (Size_1KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB); + } + + /* Erase 128B */ + if(Length0)//front + { + ROM_ERASE(Addr0, (Length0 >> 7), Size_128B); + } + + if(Length1)//back + { + ROM_ERASE(Addr1, (Length1 >> 7), Size_128B); + } + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + +/********************************************************************* + * @fn FLASH_ROM_WRITE + * + * @brief Writes a specified FLASH . + * + * @param StartAddr - Writes Flash start address(StartAddr%128 == 0). + * Length - Writes Flash start Length(Length%128 == 0). + * pbuf - Writes Flash value buffer. + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_WRITE( uint32_t StartAddr, uint32_t *pbuf, uint32_t Length ) +{ + uint32_t i, adr; + uint8_t size; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_128B-1)) || (Length & (Size_128B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + adr = StartAddr; + i = Length >> 7; + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + do{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + size = 8; + while(size) + { + *(__IO uint32_t *)(StartAddr) = *(uint32_t *)pbuf++; + *(__IO uint32_t *)(StartAddr + 0x04) = *(uint32_t *)pbuf++; + *(__IO uint32_t *)(StartAddr + 0x08) = *(uint32_t *)pbuf++; + *(__IO uint32_t *)(StartAddr + 0x0C) = *(uint32_t *)pbuf++; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((StartAddr & 0xFFFFFFFC) ^ 0x00001000); + StartAddr += 16; + size -= 1; + } + + FLASH->ADDR = adr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + *(__IO uint32_t*)0x40022034 = *(__IO uint32_t*)((adr & 0xFFFFFFFC) ^ 0x00001000); + adr += 128; + }while(--i); + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + + diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_gpio.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_gpio.c index f582923..dd3726e 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_gpio.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_gpio.c @@ -1,580 +1,578 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_gpio.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the GPIO firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include "ch32v10x_gpio.h" -#include "ch32v10x_rcc.h" - -/* MASK */ -#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) - -/********************************************************************* - * @fn GPIO_DeInit - * - * @brief Deinitializes the GPIOx peripheral registers to their default - * reset values. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @return none - */ -void GPIO_DeInit(GPIO_TypeDef *GPIOx) -{ - if(GPIOx == GPIOA) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); - } - else if(GPIOx == GPIOB) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); - } - else if(GPIOx == GPIOC) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); - } - else if(GPIOx == GPIOD) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); - } - else if(GPIOx == GPIOE) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); - } - else if(GPIOx == GPIOF) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); - } - else - { - if(GPIOx == GPIOG) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); - } - } -} - -/********************************************************************* - * @fn GPIO_AFIODeInit - * - * @brief Deinitializes the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * - * @return none - */ -void GPIO_AFIODeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); -} - -/********************************************************************* - * @fn GPIO_Init - * - * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. - * - * @return none - */ -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - - if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - { - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } - - if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) - { - tmpreg = GPIOx->CFGLR; - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << pinpos); - } - else - { - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CFGLR = tmpreg; - } - - if(GPIO_InitStruct->GPIO_Pin > 0x00FF) - { - tmpreg = GPIOx->CFGHR; - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x08)); - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - } - } - GPIOx->CFGHR = tmpreg; - } -} - -/********************************************************************* - * @fn GPIO_StructInit - * - * @brief Fills each GPIO_InitStruct member with its default - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) -{ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/********************************************************************* - * @fn GPIO_ReadInputDataBit - * - * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @param GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * - * @return The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadInputData - * - * @brief Reads the specified GPIO input data port. - * - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * - * @return The input port pin value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) -{ - return ((uint16_t)GPIOx->INDR); -} - -/********************************************************************* - * @fn GPIO_ReadOutputDataBit - * - * @brief Reads the specified output data port bit. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadOutputData - * - * @brief Reads the specified GPIO output data port. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @return GPIO output port pin value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) -{ - return ((uint16_t)GPIOx->OUTDR); -} - -/********************************************************************* - * @fn GPIO_SetBits - * - * @brief Sets the selected data port bits. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BSHR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_ResetBits - * - * @brief Clears the selected data port bits. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BCR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_WriteBit - * - * @brief Sets or clears the selected data port bit. - * - * @param GPIO_Pin - specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * BitVal - specifies the value to be written to the selected bit. - * Bit_RESET - to clear the port pin. - * Bit_SET - to set the port pin. - * - * @return none - */ -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - if(BitVal != Bit_RESET) - { - GPIOx->BSHR = GPIO_Pin; - } - else - { - GPIOx->BCR = GPIO_Pin; - } -} - -/********************************************************************* - * @fn GPIO_Write - * - * @brief Writes data to the specified GPIO data port. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * PortVal - specifies the value to be written to the port output data register. - * - * @return none - */ -void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) -{ - GPIOx->OUTDR = PortVal; -} - -/********************************************************************* - * @fn GPIO_PinLockConfig - * - * @brief Locks GPIO Pins configuration registers. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - - tmp |= GPIO_Pin; - GPIOx->LCKR = tmp; - GPIOx->LCKR = GPIO_Pin; - GPIOx->LCKR = tmp; - tmp = GPIOx->LCKR; - tmp = GPIOx->LCKR; -} - -/********************************************************************* - * @fn GPIO_EventOutputConfig - * - * @brief Selects the GPIO pin used as Event output. - * - * @param GPIO_PortSource - selects the GPIO port to be used as source - * for Event output. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). - * GPIO_PinSource - specifies the pin for the Event output. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * - * @return none - */ -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmpreg = 0x00; - - tmpreg = AFIO->ECR; - tmpreg &= ECR_PORTPINCONFIG_MASK; - tmpreg |= (uint32_t)GPIO_PortSource << 0x04; - tmpreg |= GPIO_PinSource; - AFIO->ECR = tmpreg; -} - -/********************************************************************* - * @fn GPIO_EventOutputCmd - * - * @brief Enables or disables the Event Output. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void GPIO_EventOutputCmd(FunctionalState NewState) -{ - if(NewState) - { - AFIO->ECR |= (1 << 7); - } - else - { - AFIO->ECR &= ~(1 << 7); - } -} - -/********************************************************************* - * @fn GPIO_PinRemapConfig - * - * @brief Changes the mapping of the specified pin. - * - * @param GPIO_Remap - selects the pin to remap. - * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping - * GPIO_Remap_I2C1 - I2C1 Alternate Function mapping - * GPIO_Remap_USART1 - USART1 Alternate Function mapping - * GPIO_Remap_USART2 - USART2 Alternate Function mapping - * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping - * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping - * GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping - * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping - * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping - * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping - * GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping - * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping - * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping - * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping - * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping - * GPIO_Remap_PD01 - PD01 Alternate Function mapping - * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping - * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping - * GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping - * GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping - * GPIO_Remap_ETH - Ethernet remapping - * GPIO_Remap_CAN2 - CAN2 remapping - * GPIO_Remap_MII_RMII_SEL - MII or RMII selection - * GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST - * GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled - * GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP) - * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected - * to TIM2 Internal Trigger 1 for calibration - * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) - * GPIO_Remap_TIM8 - TIM8 Alternate Function mapping - * GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping - * GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping - * GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping - * GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping - * GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping - * GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping - * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping - * GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping - * GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping - * GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping - * GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping - * GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping - * GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping - * GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping - * GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping - * GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) -{ - uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - tmpreg = AFIO->PCFR2; - } - else - { - tmpreg = AFIO->PCFR1; - } - - tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - tmp = GPIO_Remap & LSB_MASK; - - if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) - { - tmpreg &= DBGAFR_SWJCFG_MASK; - AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; - } - else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - else - { - tmpreg &= ~(tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10)); - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - - if(NewState != DISABLE) - { - tmpreg |= (tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10)); - } - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - AFIO->PCFR2 = tmpreg; - } - else - { - AFIO->PCFR1 = tmpreg; - } -} - -/********************************************************************* - * @fn GPIO_EXTILineConfig - * - * @brief Selects the GPIO pin used as EXTI Line. - * - * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). - * GPIO_PinSource - specifies the EXTI line to be configured. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * - * @return none - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmp = 0x00; - - tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); - AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; - AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); -} - - -/********************************************************************* - * @fn GPIO_IPD_Unused - * - * @brief Configure unused GPIO as input pull-up. - * - * @param none - * - * @return none - */ -void GPIO_IPD_Unused(void) -{ - GPIO_InitTypeDef GPIO_InitStructure = {0}; - uint32_t chip = 0; - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, ENABLE); - chip = *( uint32_t * )0x1FFFF884 ; - switch(chip) - { - case 0x25004102: //CH32V103C8T6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ - |GPIO_Pin_2|GPIO_Pin_3\ - |GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6|GPIO_Pin_7\ - |GPIO_Pin_8|GPIO_Pin_9\ - |GPIO_Pin_10|GPIO_Pin_11|GPIO_Pin_12; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOD, &GPIO_InitStructure); - break; - } - default: - { - break; - } - } - -} - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_gpio.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the GPIO firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32v10x_gpio.h" +#include "ch32v10x_rcc.h" + +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if(GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } + else if(GPIOx == GPIOF) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); + } + else + { + if(GPIOx == GPIOG) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); + } + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } + + if(GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CFGHR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CFGHR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * + * @return The input port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->INDR); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->OUTDR); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BSHR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * BitVal - specifies the value to be written to the selected bit. + * Bit_RESET - to clear the port pin. + * Bit_SET - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = GPIO_Pin; + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_EventOutputConfig + * + * @brief Selects the GPIO pin used as Event output. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * GPIO_PinSource - specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + + tmpreg = AFIO->ECR; + tmpreg &= ECR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->ECR = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EventOutputCmd + * + * @brief Enables or disables the Event Output. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + if(NewState) + { + AFIO->ECR |= (1 << 7); + } + else + { + AFIO->ECR &= ~(1 << 7); + } +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping + * GPIO_Remap_I2C1 - I2C1 Alternate Function mapping + * GPIO_Remap_USART1 - USART1 Alternate Function mapping + * GPIO_Remap_USART2 - USART2 Alternate Function mapping + * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping + * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping + * GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping + * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping + * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping + * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap_PD01 - PD01 Alternate Function mapping + * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping + * GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping + * GPIO_Remap_ETH - Ethernet remapping + * GPIO_Remap_CAN2 - CAN2 remapping + * GPIO_Remap_MII_RMII_SEL - MII or RMII selection + * GPIO_Remap_SWJ_Disable - Full SWJ Disabled + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected + * to TIM2 Internal Trigger 1 for calibration + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) + * GPIO_Remap_TIM8 - TIM8 Alternate Function mapping + * GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping + * GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping + * GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping + * GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping + * GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping + * GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping + * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping + * GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping + * GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping + * GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping + * GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping + * GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping + * GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping + * GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping + * GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping + * GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->PCFR2; + } + else + { + tmpreg = AFIO->PCFR1; + } + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else + { + tmpreg &= ~(tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + + if(NewState != DISABLE) + { + tmpreg |= (tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10)); + } + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->PCFR2 = tmpreg; + } + else + { + AFIO->PCFR1 = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + + +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-up. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, ENABLE); + chip = *( uint32_t * )0x1FFFF884 & (~0x000000F0); + switch(chip) + { + case 0x25004102: //CH32V103C8T6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11|GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + default: + { + break; + } + } + +} + + + diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_i2c.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_i2c.c index 0a12d2d..53f260d 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_i2c.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_i2c.c @@ -1,1015 +1,1015 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_i2c.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the I2C firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_i2c.h" -#include "ch32v10x_rcc.h" - -/* I2C SPE mask */ -#define CTLR1_PE_Set ((uint16_t)0x0001) -#define CTLR1_PE_Reset ((uint16_t)0xFFFE) - -/* I2C START mask */ -#define CTLR1_START_Set ((uint16_t)0x0100) -#define CTLR1_START_Reset ((uint16_t)0xFEFF) - -/* I2C STOP mask */ -#define CTLR1_STOP_Set ((uint16_t)0x0200) -#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) - -/* I2C ACK mask */ -#define CTLR1_ACK_Set ((uint16_t)0x0400) -#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) - -/* I2C ENGC mask */ -#define CTLR1_ENGC_Set ((uint16_t)0x0040) -#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) - -/* I2C SWRST mask */ -#define CTLR1_SWRST_Set ((uint16_t)0x8000) -#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) - -/* I2C PEC mask */ -#define CTLR1_PEC_Set ((uint16_t)0x1000) -#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) - -/* I2C ENPEC mask */ -#define CTLR1_ENPEC_Set ((uint16_t)0x0020) -#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) - -/* I2C ENARP mask */ -#define CTLR1_ENARP_Set ((uint16_t)0x0010) -#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) - -/* I2C NOSTRETCH mask */ -#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) -#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) - -/* I2C registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) - -/* I2C DMAEN mask */ -#define CTLR2_DMAEN_Set ((uint16_t)0x0800) -#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) - -/* I2C LAST mask */ -#define CTLR2_LAST_Set ((uint16_t)0x1000) -#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) - -/* I2C FREQ mask */ -#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) - -/* I2C ADD0 mask */ -#define OADDR1_ADD0_Set ((uint16_t)0x0001) -#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) - -/* I2C ENDUAL mask */ -#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) -#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) - -/* I2C ADD2 mask */ -#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) - -/* I2C F/S mask */ -#define CKCFGR_FS_Set ((uint16_t)0x8000) - -/* I2C CCR mask */ -#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) - -/* I2C FLAG mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) - -/* I2C Interrupt Enable mask */ -#define ITEN_Mask ((uint32_t)0x07000000) - -/********************************************************************* - * @fn I2C_DeInit - * - * @brief Deinitializes the I2Cx peripheral registers to their default - * reset values. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return none - */ -void I2C_DeInit(I2C_TypeDef *I2Cx) -{ - if(I2Cx == I2C1) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); - } - else - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); - } -} - -/********************************************************************* - * @fn I2C_Init - * - * @brief Initializes the I2Cx peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified I2C peripheral. - * - * @return none - */ -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) -{ - uint16_t tmpreg = 0, freqrange = 0; - uint16_t result = 0x04; - uint32_t pclk1 = 8000000; - - RCC_ClocksTypeDef rcc_clocks; - - tmpreg = I2Cx->CTLR2; - tmpreg &= CTLR2_FREQ_Reset; - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - I2Cx->CTLR2 = tmpreg; - - I2Cx->CTLR1 &= CTLR1_PE_Reset; - tmpreg = 0; - - if(I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - - if(result < 0x04) - { - result = 0x04; - } - - tmpreg |= result; - I2Cx->RTR = freqrange + 1; - } - else - { - if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - result |= I2C_DutyCycle_16_9; - } - - if((result & CKCFGR_CCR_Set) == 0) - { - result |= (uint16_t)0x0001; - } - - tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); - I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - I2Cx->CKCFGR = tmpreg; - I2Cx->CTLR1 |= CTLR1_PE_Set; - - tmpreg = I2Cx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - I2Cx->CTLR1 = tmpreg; - - I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/********************************************************************* - * @fn I2C_StructInit - * - * @brief Fills each I2C_InitStruct member with its default value. - * - * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) -{ - I2C_InitStruct->I2C_ClockSpeed = 5000; - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStruct->I2C_OwnAddress1 = 0; - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/********************************************************************* - * @fn I2C_Cmd - * - * @brief Enables or disables the specified I2C peripheral. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PE_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PE_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMACmd - * - * @brief Enables or disables the specified I2C DMA requests. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_DMAEN_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMALastTransferCmd - * - * @brief Specifies if the next DMA transfer will be the last one. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_LAST_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_LAST_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTART - * - * @brief Generates I2Cx communication START condition. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_START_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_START_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTOP - * - * @brief Generates I2Cx communication STOP condition. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_STOP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_STOP_Reset; - } -} - -/********************************************************************* - * @fn I2C_AcknowledgeConfig - * - * @brief Enables or disables the specified I2C acknowledge feature. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ACK_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ACK_Reset; - } -} - -/********************************************************************* - * @fn I2C_OwnAddress2Config - * - * @brief Configures the specified I2C own address2. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * Address - specifies the 7bit I2C own address2. - * - * @return none - */ -void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - tmpreg = I2Cx->OADDR2; - tmpreg &= OADDR2_ADD2_Reset; - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - I2Cx->OADDR2 = tmpreg; -} - -/********************************************************************* - * @fn I2C_DualAddressCmd - * - * @brief Enables or disables the specified I2C dual addressing mode. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; - } - else - { - I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; - } -} - -/********************************************************************* - * @fn I2C_GeneralCallCmd - * - * @brief Enables or disables the specified I2C general call feature. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENGC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENGC_Reset; - } -} - -/********************************************************************* - * @fn I2C_ITConfig - * - * @brief Enables or disables the specified I2C interrupts. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. - * I2C_IT_BUF - Buffer interrupt mask. - * I2C_IT_EVT - Event interrupt mask. - * I2C_IT_ERR - Error interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= I2C_IT; - } - else - { - I2Cx->CTLR2 &= (uint16_t)~I2C_IT; - } -} - -/********************************************************************* - * @fn I2C_SendData - * - * @brief Sends a data byte through the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * Data - Byte to be transmitted. - * - * @return none - */ -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) -{ - I2Cx->DATAR = Data; -} - -/********************************************************************* - * @fn I2C_ReceiveData - * - * @brief Returns the most recent received data by the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) -{ - return (uint8_t)I2Cx->DATAR; -} - -/********************************************************************* - * @fn I2C_Send7bitAddress - * - * @brief Transmits the address byte to select the slave device. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * Address - specifies the slave address which will be transmitted. - * I2C_Direction - specifies whether the I2C device will be a - * Transmitter or a Receiver. - * I2C_Direction_Transmitter - Transmitter mode. - * I2C_Direction_Receiver - Receiver mode. - * - * @return none - */ -void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - if(I2C_Direction != I2C_Direction_Transmitter) - { - Address |= OADDR1_ADD0_Set; - } - else - { - Address &= OADDR1_ADD0_Reset; - } - - I2Cx->DATAR = Address; -} - -/********************************************************************* - * @fn I2C_ReadRegister - * - * @brief Reads the specified I2C register and returns its value. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_Register - specifies the register to read. - * I2C_Register_CTLR1. - * I2C_Register_CTLR2. - * I2C_Register_OADDR1. - * I2C_Register_OADDR2. - * I2C_Register_DATAR. - * I2C_Register_STAR1. - * I2C_Register_STAR2. - * I2C_Register_CKCFGR. - * I2C_Register_RTR. - * - * @return none - */ -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)I2Cx; - tmp += I2C_Register; - - return (*(__IO uint16_t *)tmp); -} - -/********************************************************************* - * @fn I2C_SoftwareResetCmd - * - * @brief Enables or disables the specified I2C software reset. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_SWRST_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_SWRST_Reset; - } -} - -/********************************************************************* - * @fn I2C_NACKPositionConfig - * - * @brief Selects the specified I2C NACK position in master receiver mode. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_NACKPosition - specifies the NACK position. - * I2C_NACKPosition_Next - indicates that the next byte will be - * the last received byte. - * I2C_NACKPosition_Current - indicates that current byte is the - * last received byte. - * Note- - * This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * @return none - */ -void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) -{ - if(I2C_NACKPosition == I2C_NACKPosition_Next) - { - I2Cx->CTLR1 |= I2C_NACKPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_NACKPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_SMBusAlertConfig - * - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_SMBusAlert - specifies SMBAlert pin level. - * I2C_SMBusAlert_Low - SMBAlert pin driven low. - * I2C_SMBusAlert_High - SMBAlert pin driven high. - * - * @return none - */ -void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert) -{ - if(I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - I2Cx->CTLR1 |= I2C_SMBusAlert_Low; - } - else - { - I2Cx->CTLR1 &= I2C_SMBusAlert_High; - } -} - -/********************************************************************* - * @fn I2C_TransmitPEC - * - * @brief Enables or disables the specified I2C PEC transfer. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_PECPositionConfig - * - * @brief Selects the specified I2C PEC position. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_PECPosition - specifies the PEC position. - * I2C_PECPosition_Next - indicates that the next byte is PEC. - * I2C_PECPosition_Current - indicates that current byte is PEC. - * - * @return none - */ -void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) -{ - if(I2C_PECPosition == I2C_PECPosition_Next) - { - I2Cx->CTLR1 |= I2C_PECPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_PECPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_CalculatePEC - * - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * - * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENPEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_GetPEC - * - * @brief Returns the PEC value for the specified I2C. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) -{ - return ((I2Cx->STAR2) >> 8); -} - -/********************************************************************* - * @fn I2C_ARPCmd - * - * @brief Enables or disables the specified I2C ARP. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return The PEC value. - */ -void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENARP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENARP_Reset; - } -} - -/********************************************************************* - * @fn I2C_StretchClockCmd - * - * @brief Enables or disables the specified I2C Clock stretching. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState == DISABLE) - { - I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; - } -} - -/********************************************************************* - * @fn I2C_FastModeDutyCycleConfig - * - * @brief Selects the specified I2C fast mode duty cycle. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_DutyCycle - specifies the fast mode duty cycle. - * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. - * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. - * - * @return none - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) -{ - if(I2C_DutyCycle != I2C_DutyCycle_16_9) - { - I2Cx->CKCFGR &= I2C_DutyCycle_2; - } - else - { - I2Cx->CKCFGR |= I2C_DutyCycle_16_9; - } -} - -/********************************************************************* - * @fn I2C_CheckEvent - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. - * I2C_EVENT: specifies the event to be checked. - * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. - * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. - * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. - * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. - * I2C_EVENT_MASTER_MODE_SELECT - EVT5. - * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. - * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. - * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. - * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. - * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. - * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. - * - * @return ErrorStatus - READY or NoREADY. - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = NoREADY; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - - lastevent = (flag1 | flag2) & FLAG_Mask; - - if((lastevent & I2C_EVENT) == I2C_EVENT) - { - status = READY; - } - else - { - status = NoREADY; - } - - return status; -} - -/********************************************************************* - * @fn I2C_GetLastEvent - * - * @brief Returns the last I2Cx Event. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return none - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - lastevent = (flag1 | flag2) & FLAG_Mask; - - return lastevent; -} - -/********************************************************************* - * @fn I2C_GetFlagStatus - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to check. - * I2C_FLAG_DUALF - Dual flag (Slave mode). - * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). - * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). - * I2C_FLAG_GENCALL - General call header flag (Slave mode). - * I2C_FLAG_TRA - Transmitter/Receiver flag. - * I2C_FLAG_BUSY - Bus busy flag. - * I2C_FLAG_MSL - Master/Slave flag. - * I2C_FLAG_SMBALERT - SMBus Alert flag. - * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * I2C_FLAG_TXE - Data register empty flag (Transmitter). - * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. - * I2C_FLAG_STOPF - Stop detection flag (Slave mode). - * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). - * I2C_FLAG_BTF - Byte transfer finished flag. - * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDA". - * I2C_FLAG_SB - Start bit flag (Master mode). - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - i2cxbase = (uint32_t)I2Cx; - i2creg = I2C_FLAG >> 28; - I2C_FLAG &= FLAG_Mask; - - if(i2creg != 0) - { - i2cxbase += 0x14; - } - else - { - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearFlag - * - * @brief Clears the I2Cx's pending flags. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to clear. - * I2C_FLAG_SMBALERT - SMBus Alert flag. - * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * Note- - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DATAR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DATAR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SATR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR - * register (I2C_SendData()). - * @return none - */ -void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - - flagpos = I2C_FLAG & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} - -/********************************************************************* - * @fn I2C_GetITStatus - * - * @brief Checks whether the specified I2C interrupt has occurred or not. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * II2C_IT - specifies the interrupt source to check. - * I2C_IT_SMBALERT - SMBus Alert flag. - * I2C_IT_TIMEOUT - Timeout or Tlow error flag. - * I2C_IT_PECERR - PEC error in reception flag. - * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). - * I2C_IT_AF - Acknowledge failure flag. - * I2C_IT_ARLO - Arbitration lost flag (Master mode). - * I2C_IT_BERR - Bus error flag. - * I2C_IT_TXE - Data register empty flag (Transmitter). - * I2C_IT_RXNE - Data register not empty (Receiver) flag. - * I2C_IT_STOPF - Stop detection flag (Slave mode). - * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). - * I2C_IT_BTF - Byte transfer finished flag. - * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched - * flag (Slave mode)"ENDAD". - * I2C_IT_SB - Start bit flag (Master mode). - * - * @return none - */ -ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); - I2C_IT &= FLAG_Mask; - - if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearITPendingBit - * - * @brief Clears the I2Cx interrupt pending bits. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_IT - specifies the interrupt pending bit to clear. - * I2C_IT_SMBALERT - SMBus Alert interrupt. - * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. - * I2C_IT_PECERR - PEC error in reception interrupt. - * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). - * I2C_IT_AF - Acknowledge failure interrupt. - * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). - * I2C_IT_BERR - Bus error interrupt. - * Note- - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DATAR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DATAR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_STAR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DATAR register (I2C_SendData()). - * - * @return none - */ -void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - - flagpos = I2C_IT & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} - - - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_i2c.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the I2C firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_i2c.h" +#include "ch32v10x_rcc.h" + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } + else + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + I2Cx->RTR = freqrange + 1; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * I2C_Register_RTR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * Note- + * This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_SMBusAlertConfig + * + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_SMBusAlert - specifies SMBAlert pin level. + * I2C_SMBusAlert_Low - SMBAlert pin driven low. + * I2C_SMBusAlert_High - SMBAlert pin driven high. + * + * @return none + */ +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert) +{ + if(I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + I2Cx->CTLR1 |= I2C_SMBusAlert_Low; + } + else + { + I2Cx->CTLR1 &= I2C_SMBusAlert_High; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. + * I2C_EVENT_MASTER_MODE_SELECT - EVT5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. + * + * @return ErrorStatus - READY or NoREADY. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = NoREADY; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = READY; + } + else + { + status = NoREADY; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). + * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SATR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR + * register (I2C_SendData()). + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_SMBALERT - SMBus Alert flag. + * I2C_IT_TIMEOUT - Timeout or Tlow error flag. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_SMBALERT - SMBus Alert interrupt. + * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_STAR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DATAR register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + + + + + + + diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_iwdg.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_iwdg.c index da867d2..7e327c2 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_iwdg.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_iwdg.c @@ -1,125 +1,126 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_iwdg.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the IWDG firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_iwdg.h" - -/* CTLR register bit mask */ -#define CTLR_KEY_Reload ((uint16_t)0xAAAA) -#define CTLR_KEY_Enable ((uint16_t)0xCCCC) - -/********************************************************************* - * @fn IWDG_WriteAccessCmd - * - * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. - * - * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR - * and IWDG_RLDR registers. - * - * @return none - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - IWDG->CTLR = IWDG_WriteAccess; -} - -/********************************************************************* - * @fn IWDG_SetPrescaler - * - * @brief Sets IWDG Prescaler value. - * - * @param IWDG_Prescaler - specifies the IWDG Prescaler value. - * IWDG_Prescaler_4 - IWDG prescaler set to 4. - * IWDG_Prescaler_8 - IWDG prescaler set to 8. - * IWDG_Prescaler_16 - IWDG prescaler set to 16. - * IWDG_Prescaler_32 - IWDG prescaler set to 32. - * IWDG_Prescaler_64 - IWDG prescaler set to 64. - * IWDG_Prescaler_128 - IWDG prescaler set to 128. - * IWDG_Prescaler_256 - IWDG prescaler set to 256. - * - * @return none - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - IWDG->PSCR = IWDG_Prescaler; -} - -/********************************************************************* - * @fn IWDG_SetReload - * - * @brief Sets IWDG Reload value. - * - * @param Reload - specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * - * @return none - */ -void IWDG_SetReload(uint16_t Reload) -{ - IWDG->RLDR = Reload; -} - -/********************************************************************* - * @fn IWDG_ReloadCounter - * - * @brief Reloads IWDG counter with value defined in the reload register. - * - * @return none - */ -void IWDG_ReloadCounter(void) -{ - IWDG->CTLR = CTLR_KEY_Reload; -} - -/********************************************************************* - * @fn IWDG_Enable - * - * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). - * - * @return none - */ -void IWDG_Enable(void) -{ - IWDG->CTLR = CTLR_KEY_Enable; -} - -/********************************************************************* - * @fn IWDG_GetFlagStatus - * - * @brief Checks whether the specified IWDG flag is set or not. - * - * @param IWDG_FLAG - specifies the flag to check. - * IWDG_FLAG_PVU - Prescaler Value Update on going. - * IWDG_FLAG_RVU - Reload Value Update on going. - * - * @return none - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_iwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the IWDG firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_iwdg.h" + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; + while((RCC->RSTSCKR & 0x2)==RESET); +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + + diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_misc.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_misc.c index c28ce17..542193d 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_misc.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_misc.c @@ -1,109 +1,87 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_misc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the miscellaneous firmware functions . -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_misc.h" - -__IO uint32_t NVIC_Priority_Group = 0; - -/********************************************************************* - * @fn NVIC_PriorityGroupConfig - * - * @brief Configures the priority grouping - pre-emption priority and subpriority. - * - * @param NVIC_PriorityGroup - specifies the priority grouping bits length. - * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority - * 4 bits for subpriority - * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority - * 3 bits for subpriority - * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority - * 2 bits for subpriority - * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority - * 1 bits for subpriority - * NVIC_PriorityGroup_4 - 4 bits for pre-emption priority - * 0 bits for subpriority - * - * @return none - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - NVIC_Priority_Group = NVIC_PriorityGroup; -} - -/********************************************************************* - * @fn NVIC_Init - * - * @brief Initializes the NVIC peripheral according to the specified parameters in - * the NVIC_InitStruct. - * - * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the - * configuration information for the specified NVIC peripheral. - * - * @return none - */ -void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) -{ - uint8_t tmppre = 0; - - if(NVIC_Priority_Group == NVIC_PriorityGroup_0) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); - } - else - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); - } - else - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3) - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); - } - else - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4)); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_4) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4); - } - - if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } - else - { - NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_misc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/05 + * Description : This file provides all the miscellaneous firmware functions . +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_misc.h" + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 4 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 3 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + NVIC_INTNestCfg(DISABLE); +#else + NVIC_INTNestCfg(ENABLE); +#endif + + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * interrupt nesting enable(PFIC->CFGR bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + * interrupt nesting disable(PFIC->CFGR bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 0xF. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); + } +#else + if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); + } + else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); + } + } +#endif + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_pwr.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_pwr.c index 3ff4637..94f47b4 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_pwr.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_pwr.c @@ -1,243 +1,250 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_pwr.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the PWR firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_pwr.h" -#include "ch32v10x_rcc.h" - -/* PWR registers bit mask */ -/* CTLR register bit mask */ -#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) - -/********************************************************************* - * @fn PWR_DeInit - * - * @brief Deinitializes the PWR peripheral registers to their default - * reset values. - * - * @return none - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/********************************************************************* - * @fn PWR_BackupAccessCmd - * - * @brief Enables or disables access to the RTC and backup registers. - * - * @param NewState - new state of the access to the RTC and backup registers, - * This parameter can be: ENABLE or DISABLE. - * - * @return none - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (1 << 8); - } - else - { - PWR->CTLR &= ~(1 << 8); - } -} - -/********************************************************************* - * @fn PWR_PVDCmd - * - * @brief Enables or disables the Power Voltage Detector(PVD). - * - * @param NewState - new state of the PVD(ENABLE or DISABLE). - * - * @return none - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (1 << 4); - } - else - { - PWR->CTLR &= ~(1 << 4); - } -} - -/********************************************************************* - * @fn PWR_PVDLevelConfig - * - * @brief Configures the voltage threshold detected by the Power Voltage - * Detector(PVD). - * - * @param PWR_PVDLevel - specifies the PVD detection level - * PWR_PVDLevel_2V2 - PVD detection level set to 2.2V - * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V - * PWR_PVDLevel_2V4 - PVD detection level set to 2.4V - * PWR_PVDLevel_2V5 - PVD detection level set to 2.5V - * PWR_PVDLevel_2V6 - PVD detection level set to 2.6V - * PWR_PVDLevel_2V7 - PVD detection level set to 2.7V - * PWR_PVDLevel_2V8 - PVD detection level set to 2.8V - * PWR_PVDLevel_2V9 - PVD detection level set to 2.9V - * - * @return none - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_PLS_MASK; - tmpreg |= PWR_PVDLevel; - PWR->CTLR = tmpreg; -} - -/********************************************************************* - * @fn PWR_WakeUpPinCmd - * - * @brief Enables or disables the WakeUp Pin functionality. - * - * @param NewState - new state of the WakeUp Pin functionality - * (ENABLE or DISABLE). - * - * @return none - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CSR |= (1 << 8); - } - else - { - PWR->CSR &= ~(1 << 8); - } -} - -/********************************************************************* - * @fn PWR_EnterSTOPMode - * - * @brief Enters STOP mode. - * - * @param PWR_Regulator - specifies the regulator state in STOP mode. - * PWR_Regulator_ON - STOP mode with regulator ON - * PWR_Regulator_LowPower - STOP mode with regulator in low power mode - * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. - * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction - * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction - * - * @return none - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_DS_MASK; - tmpreg |= PWR_Regulator; - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - __WFI(); - } - else - { - __WFE(); - } - - NVIC->SCTLR &= ~(1 << 2); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode - * - * @brief Enters STANDBY mode. - * - * @return none - */ -void PWR_EnterSTANDBYMode(void) -{ - PWR->CTLR |= PWR_CTLR_CWUF; - PWR->CTLR |= PWR_CTLR_PDDS; - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_GetFlagStatus - * - * @brief Checks whether the specified PWR flag is set or not. - * - * @param PWR_FLAG - specifies the flag to check. - * PWR_FLAG_WU - Wake Up flag - * PWR_FLAG_SB - StandBy flag - * PWR_FLAG_PVDO - PVD Output - * - * @return The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn PWR_ClearFlag - * - * @brief Clears the PWR's pending flags. - * - * @param PWR_FLAG - specifies the flag to clear. - * PWR_FLAG_WU - Wake Up flag - * PWR_FLAG_SB - StandBy flag - * - * @return none - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - PWR->CTLR |= PWR_FLAG << 2; -} - -/********************************************************************* - * @fn PWR_VDD_SupplyVoltage - * - * @brief Checks VDD Supply Voltage. - * - * @param none - * - * @return PWR_VDD - VDD Supply Voltage. - * PWR_VDD_5V - VDD = 5V - * PWR_VDD_3V3 - VDD = 3.3V - */ -PWR_VDD PWR_VDD_SupplyVoltage(void) -{ - PWR_VDD VDD_Voltage = PWR_VDD_3V3; - - if((*((uint32_t*)0x08000048)) == 0x005FFFFF) - { - VDD_Voltage = PWR_VDD_5V; - } - - return VDD_Voltage; -} - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_pwr.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/14 + * Description : This file provides all the PWR firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_pwr.h" +#include "ch32v10x_rcc.h" + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_BackupAccessCmd + * + * @brief Enables or disables access to the RTC and backup registers. + * + * @param NewState - new state of the access to the RTC and backup registers, + * This parameter can be: ENABLE or DISABLE. + * + * @return none + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 8); + } + else + { + PWR->CTLR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_PVDCmd + * + * @brief Enables or disables the Power Voltage Detector(PVD). + * + * @param NewState - new state of the PVD(ENABLE or DISABLE). + * + * @return none + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 4); + } + else + { + PWR->CTLR &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_MODE0 - PVD detection level set to mode 0. + * PWR_PVDLevel_MODE1 - PVD detection level set to mode 1. + * PWR_PVDLevel_MODE2 - PVD detection level set to mode 2. + * PWR_PVDLevel_MODE3 - PVD detection level set to mode 3. + * PWR_PVDLevel_MODE4 - PVD detection level set to mode 4. + * PWR_PVDLevel_MODE5 - PVD detection level set to mode 5. + * PWR_PVDLevel_MODE6 - PVD detection level set to mode 6. + * PWR_PVDLevel_MODE7 - PVD detection level set to mode 7. + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_WakeUpPinCmd + * + * @brief Enables or disables the WakeUp Pin functionality. + * + * @param NewState - new state of the WakeUp Pin functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CSR |= (1 << 8); + } + else + { + PWR->CSR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_EnterSTOPMode + * + * @brief Enters STOP mode. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_ON - STOP mode with regulator ON + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @return none + */ +void PWR_EnterSTANDBYMode(void) +{ + PWR->CTLR |= PWR_CTLR_CWUF; + PWR->CTLR |= PWR_CTLR_PDDS; + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * PWR_FLAG_PVDO - PVD Output + * + * @return The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn PWR_ClearFlag + * + * @brief Clears the PWR's pending flags. + * + * @param PWR_FLAG - specifies the flag to clear. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * + * @return none + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + PWR->CTLR |= PWR_FLAG << 2; +} + +/********************************************************************* + * @fn PWR_VDD_SupplyVoltage + * + * @brief Checks VDD Supply Voltage. + * + * @param none + * + * @return PWR_VDD - VDD Supply Voltage. + * PWR_VDD_5V - VDD = 5V + * PWR_VDD_3V3 - VDD = 3.3V + */ +PWR_VDD PWR_VDD_SupplyVoltage(void) +{ + + PWR_VDD VDD_Voltage = PWR_VDD_3V3; + Delay_Init(); + RCC_APB1PeriphClockCmd( RCC_APB1Periph_PWR, ENABLE); + PWR_PVDLevelConfig(PWR_PVDLevel_MODE6); + PWR_PVDCmd(ENABLE); + Delay_Us(10); + if( PWR_GetFlagStatus(PWR_FLAG_PVDO) == (uint32_t)RESET) + { + VDD_Voltage = PWR_VDD_5V; + } + PWR_PVDLevelConfig(PWR_PVDLevel_MODE0); + PWR_PVDCmd(DISABLE); + + return VDD_Voltage; +} + diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_rcc.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_rcc.c index c663b00..66b93ea 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_rcc.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_rcc.c @@ -1,950 +1,950 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_rcc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the RCC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_rcc.h" - -/* RCC registers bit address in the alias region */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* BDCTLR Register */ -#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) - -/* RCC registers bit mask */ - -/* CTLR register bit mask */ -#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) -#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CTLR_HSEON_Set ((uint32_t)0x00010000) -#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) -#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) -#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) -#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) -#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) -#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) -#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) -#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) -#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) - -/* RSTSCKR register bit mask */ -#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -/* INTR register byte 2 (Bits[15:8]) base address */ -#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* INTR register byte 3 (Bits[23:16]) base address */ -#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CFGR0 register byte 4 (Bits[31:24]) base address */ -#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) - -/* BDCTLR register base address */ -#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) - -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; - -/********************************************************************* - * @fn RCC_DeInit - * - * @brief Resets the RCC clock configuration to the default reset state. - * Note- - * HSE can not be stopped if it is used directly or through the PLL as system clock. - * @return none - */ -void RCC_DeInit(void) -{ - RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; - RCC->CTLR &= (uint32_t)0xFEF6FFFF; - RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; - RCC->INTR = 0x009F0000; -} - -/********************************************************************* - * @fn RCC_HSEConfig - * - * @brief Configures the External High Speed oscillator (HSE). - * - * @param RCC_HSE - - * RCC_HSE_OFF - HSE oscillator OFF. - * RCC_HSE_ON - HSE oscillator ON. - * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. - * Note- - * HSE can not be stopped if it is used directly or through the PLL as system clock. - * @return none - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - RCC->CTLR &= CTLR_HSEON_Reset; - RCC->CTLR &= CTLR_HSEBYP_Reset; - - switch(RCC_HSE) - { - case RCC_HSE_ON: - RCC->CTLR |= CTLR_HSEON_Set; - break; - - case RCC_HSE_Bypass: - RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn RCC_WaitForHSEStartUp - * - * @brief Waits for HSE start-up. - * - * @return READY - HSE oscillator is stable and ready to use. - * NoREADY - HSE oscillator not yet ready. - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - - ErrorStatus status = NoREADY; - FlagStatus HSEStatus = RESET; - - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = READY; - } - else - { - status = NoREADY; - } - - return (status); -} - -/********************************************************************* - * @fn RCC_AdjustHSICalibrationValue - * - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * - * @param HSICalibrationValue - specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * - * @return none - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CTLR; - tmpreg &= CTLR_HSITRIM_Mask; - tmpreg |= (uint32_t)HSICalibrationValue << 3; - RCC->CTLR = tmpreg; -} - -/********************************************************************* - * @fn RCC_HSICmd - * - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_HSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 0); - } - else - { - RCC->CTLR &= ~(1 << 0); - } -} - -/********************************************************************* - * @fn RCC_PLLConfig - * - * @brief Configures the PLL clock source and multiplication factor. - * - * @param RCC_PLLSource - specifies the PLL entry clock source. - * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 - * selected as PLL clock entry. - * RCC_PLLSource_HSE_Div1 - HSE oscillator clock selected as PLL - * clock entry. - * RCC_PLLSource_HSE_Div2 - HSE oscillator clock divided by 2 - * selected as PLL clock entry. - * RCC_PLLMul - specifies the PLL multiplication factor. - * This parameter can be RCC_PLLMul_x where x:[2,16]. - * - * @return none - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_PLL_Mask; - tmpreg |= RCC_PLLSource | RCC_PLLMul; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PLLCmd - * - * @brief Enables or disables the PLL. - * Note-The PLL can not be disabled if it is used as system clock. - * - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 24); - } - else - { - RCC->CTLR &= ~(1 << 24); - } -} - -/********************************************************************* - * @fn RCC_SYSCLKConfig - * - * @brief Configures the system clock (SYSCLK). - * - * @param RCC_SYSCLKSource - specifies the clock source used as system clock. - * RCC_SYSCLKSource_HSI - HSI selected as system clock. - * RCC_SYSCLKSource_HSE - HSE selected as system clock. - * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. - * - * @return none - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_SW_Mask; - tmpreg |= RCC_SYSCLKSource; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_GetSYSCLKSource - * - * @brief Returns the clock source used as system clock. - * - * @return 0x00 - HSI used as system clock. - * 0x04 - HSE used as system clock. - * 0x08 - PLL used as system clock. - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); -} - -/********************************************************************* - * @fn RCC_HCLKConfig - * - * @brief Configures the AHB clock (HCLK). - * - * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. - * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. - * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. - * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. - * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. - * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. - * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. - * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. - * RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512. - * - * @return none - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_HPRE_Reset_Mask; - tmpreg |= RCC_SYSCLK; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PCLK1Config - * - * @brief Configures the Low Speed APB clock (PCLK1). - * - * @param RCC_HCLK - defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * RCC_HCLK_Div1 - APB1 clock = HCLK. - * RCC_HCLK_Div2 - APB1 clock = HCLK/2. - * RCC_HCLK_Div4 - APB1 clock = HCLK/4. - * RCC_HCLK_Div8 - APB1 clock = HCLK/8. - * RCC_HCLK_Div16 - APB1 clock = HCLK/16. - * - * @return none - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_PPRE1_Reset_Mask; - tmpreg |= RCC_HCLK; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PCLK2Config - * - * @brief Configures the High Speed APB clock (PCLK2). - * - * @param RCC_HCLK - defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * RCC_HCLK_Div1 - APB2 clock = HCLK. - * RCC_HCLK_Div2 - APB2 clock = HCLK/2. - * RCC_HCLK_Div4 - APB2 clock = HCLK/4. - * RCC_HCLK_Div8 - APB2 clock = HCLK/8. - * RCC_HCLK_Div16 - APB2 clock = HCLK/16. - * @return none - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_PPRE2_Reset_Mask; - tmpreg |= RCC_HCLK << 3; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_ITConfig - * - * @brief Enables or disables the specified RCC interrupts. - * - * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/********************************************************************* - * @fn RCC_USBCLKConfig - * - * @brief Configures the USB clock (USBCLK). - * - * @param RCC_USBCLKSource: specifies the USB clock source. This clock is - * derived from the PLL output. - * RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB - * clock source. - * RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source. - * - * @return none - */ -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) -{ - if(RCC_USBCLKSource) - { - RCC->CFGR0 |= (1 << 22); - } - else - { - RCC->CFGR0 &= ~(1 << 22); - } -} - -/********************************************************************* - * @fn RCC_ADCCLKConfig - * - * @brief Configures the ADC clock (ADCCLK). - * - * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from - * the APB2 clock (PCLK2). - * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. - * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. - * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. - * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. - * - * @return none - */ -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_ADCPRE_Reset_Mask; - tmpreg |= RCC_PCLK2; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_LSEConfig - * - * @brief Configures the External Low Speed oscillator (LSE). - * - * @param RCC_LSE - specifies the new state of the LSE. - * RCC_LSE_OFF - LSE oscillator OFF. - * RCC_LSE_ON - LSE oscillator ON. - * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. - * - * @return none - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; - *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; - - switch(RCC_LSE) - { - case RCC_LSE_ON: - *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_ON; - break; - - case RCC_LSE_Bypass: - *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn RCC_LSICmd - * - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * Note- - * LSI can not be disabled if the IWDG is running. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_LSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->RSTSCKR |= (1 << 0); - } - else - { - RCC->RSTSCKR &= ~(1 << 0); - } -} - -/********************************************************************* - * @fn RCC_RTCCLKConfig - * - * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. - * - * @param RCC_RTCCLKSource - specifies the RTC clock source. - * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. - * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. - * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. - * Note- - * Once the RTC clock is selected it can't be changed unless the Backup domain is reset. - * @return none - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - RCC->BDCTLR |= RCC_RTCCLKSource; -} - -/********************************************************************* - * @fn RCC_RTCCLKCmd - * - * @brief This function must be used only after the RTC clock was selected - * using the RCC_RTCCLKConfig function. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->BDCTLR |= (1 << 15); - } - else - { - RCC->BDCTLR &= ~(1 << 15); - } -} - -/********************************************************************* - * @fn RCC_GetClocksFreq - * - * @brief The result of this function could be not correct when using - * fractional value for HSE crystal. - * - * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @return none - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; - - tmp = RCC->CFGR0 & CFGR0_SWS_Mask; - - switch(tmp) - { - case 0x00: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - - case 0x04: - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - - case 0x08: - pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; - pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; - pllmull = (pllmull >> 18) + 2; - - if(pllsource == 0x00) - { - if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) - { - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE)*pllmull; - } - else - { - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; - } - } - else - { - if((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) - { - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; - } - else - { - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; - } - } - break; - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - - tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; - tmp = tmp >> 11; - presc = APBAHBPrescTable[tmp]; - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; - tmp = tmp >> 14; - presc = ADCPrescTable[tmp]; - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; -} - -/********************************************************************* - * @fn RCC_AHBPeriphClockCmd - * - * @brief Enables or disables the AHB peripheral clock. - * - * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. - * RCC_AHBPeriph_DMA1. - * RCC_AHBPeriph_DMA2. - * RCC_AHBPeriph_SRAM. - * Note- - * SRAM clock can be disabled only during sleep mode. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->AHBPCENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBPCENR &= ~RCC_AHBPeriph; - } -} - -/********************************************************************* - * @fn RCC_APB2PeriphClockCmd - * - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * - * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. - * RCC_APB2Periph_AFIO. - * RCC_APB2Periph_GPIOA. - * RCC_APB2Periph_GPIOB. - * RCC_APB2Periph_GPIOC. - * RCC_APB2Periph_GPIOD. - * RCC_APB2Periph_GPIOE - * RCC_APB2Periph_ADC1. - * RCC_APB2Periph_ADC2 - * RCC_APB2Periph_TIM1. - * RCC_APB2Periph_SPI1. - * RCC_APB2Periph_TIM8 - * RCC_APB2Periph_USART1. - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->APB2PCENR |= RCC_APB2Periph; - } - else - { - RCC->APB2PCENR &= ~RCC_APB2Periph; - } -} - -/********************************************************************* - * @fn RCC_APB1PeriphClockCmd - * - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * - * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. - * RCC_APB1Periph_TIM2. - * RCC_APB1Periph_TIM3. - * RCC_APB1Periph_TIM4. - * RCC_APB1Periph_WWDG. - * RCC_APB1Periph_SPI2. - * RCC_APB1Periph_USART2. - * RCC_APB1Periph_I2C1. - * RCC_APB1Periph_I2C2. - * RCC_APB1Periph_USB. - * RCC_APB1Periph_CAN1. - * RCC_APB1Periph_BKP. - * RCC_APB1Periph_PWR. - * RCC_APB1Periph_DAC. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->APB1PCENR |= RCC_APB1Periph; - } - else - { - RCC->APB1PCENR &= ~RCC_APB1Periph; - } -} - -/********************************************************************* - * @fn RCC_APB2PeriphResetCmd - * - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * - * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. - * RCC_APB2Periph_AFIO. - * RCC_APB2Periph_GPIOA. - * RCC_APB2Periph_GPIOB. - * RCC_APB2Periph_GPIOC. - * RCC_APB2Periph_GPIOD. - * RCC_APB2Periph_GPIOE - * RCC_APB2Periph_ADC1. - * RCC_APB2Periph_TIM1. - * RCC_APB2Periph_SPI1. - * RCC_APB2Periph_USART1. - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->APB2PRSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2PRSTR &= ~RCC_APB2Periph; - } -} - -/********************************************************************* - * @fn RCC_APB1PeriphResetCmd - * - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * - * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. - * RCC_APB1Periph_TIM2. - * RCC_APB1Periph_TIM3. - * RCC_APB1Periph_TIM4. - * RCC_APB1Periph_WWDG. - * RCC_APB1Periph_SPI2. - * RCC_APB1Periph_USART2. - * RCC_APB1Periph_USART3. - * RCC_APB1Periph_I2C1. - * RCC_APB1Periph_I2C2. - * RCC_APB1Periph_USB. - * RCC_APB1Periph_CAN1. - * RCC_APB1Periph_BKP. - * RCC_APB1Periph_PWR. - * RCC_APB1Periph_DAC. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->APB1PRSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1PRSTR &= ~RCC_APB1Periph; - } -} - -/********************************************************************* - * @fn RCC_BackupResetCmd - * - * @brief Forces or releases the Backup domain reset. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->BDCTLR |= (1 << 16); - } - else - { - RCC->BDCTLR &= ~(1 << 16); - } -} - -/********************************************************************* - * @fn RCC_ClockSecuritySystemCmd - * - * @brief Enables or disables the Clock Security System. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 19); - } - else - { - RCC->CTLR &= ~(1 << 19); - } -} - -/********************************************************************* - * @fn RCC_MCOConfig - * - * @brief Selects the clock source to output on MCO pin. - * - * @param RCC_MCO - specifies the clock source to output. - * RCC_MCO_NoClock - No clock selected. - * RCC_MCO_SYSCLK - System clock selected. - * RCC_MCO_HSI - HSI oscillator clock selected. - * RCC_MCO_HSE - HSE oscillator clock selected. - * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. - * - * @return none - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO; -} - -/********************************************************************* - * @fn RCC_GetFlagStatus - * - * @brief Checks whether the specified RCC flag is set or not. - * - * @param RCC_FLAG - specifies the flag to check. - * RCC_FLAG_HSIRDY - HSI oscillator clock ready. - * RCC_FLAG_HSERDY - HSE oscillator clock ready. - * RCC_FLAG_PLLRDY - PLL clock ready. - * RCC_FLAG_LSERDY - LSE oscillator clock ready. - * RCC_FLAG_LSIRDY - LSI oscillator clock ready. - * RCC_FLAG_PINRST - Pin reset. - * RCC_FLAG_PORRST - POR/PDR reset. - * RCC_FLAG_SFTRST - Software reset. - * RCC_FLAG_IWDGRST - Independent Watchdog reset. - * RCC_FLAG_WWDGRST - Window Watchdog reset. - * RCC_FLAG_LPWRRST - Low Power reset. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - - FlagStatus bitstatus = RESET; - tmp = RCC_FLAG >> 5; - - if(tmp == 1) - { - statusreg = RCC->CTLR; - } - else if(tmp == 2) - { - statusreg = RCC->BDCTLR; - } - else - { - statusreg = RCC->RSTSCKR; - } - - tmp = RCC_FLAG & FLAG_Mask; - - if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearFlag - * - * @brief Clears the RCC reset flags. - * Note- - * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @return none - */ -void RCC_ClearFlag(void) -{ - RCC->RSTSCKR |= RSTSCKR_RMVF_Set; -} - -/********************************************************************* - * @fn RCC_GetITStatus - * - * @brief Checks whether the specified RCC interrupt has occurred or not. - * - * @param RCC_IT - specifies the RCC interrupt source to check. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * - * @return ITStatus - SET or RESET. - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - if((RCC->INTR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearITPendingBit - * - * @brief Clears the RCC's interrupt pending bits. - * - * @param RCC_IT - specifies the interrupt pending bit to clear. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * - * @return none - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT; -} - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_rcc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_rcc.h" + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->INTR = 0x009F0000; +} + +/********************************************************************* + * @fn RCC_HSEConfig + * + * @brief Configures the External High Speed oscillator (HSE). + * + * @param RCC_HSE - + * RCC_HSE_OFF - HSE oscillator OFF. + * RCC_HSE_ON - HSE oscillator ON. + * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + RCC->CTLR &= CTLR_HSEON_Reset; + RCC->CTLR &= CTLR_HSEBYP_Reset; + + switch(RCC_HSE) + { + case RCC_HSE_ON: + RCC->CTLR |= CTLR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_WaitForHSEStartUp + * + * @brief Waits for HSE start-up. + * + * @return READY - HSE oscillator is stable and ready to use. + * NoREADY - HSE oscillator not yet ready. + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + + ErrorStatus status = NoREADY; + FlagStatus HSEStatus = RESET; + + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = READY; + } + else + { + status = NoREADY; + } + + return (status); +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 0); + } + else + { + RCC->CTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_PLLConfig + * + * @brief Configures the PLL clock source and multiplication factor. + * + * @param RCC_PLLSource - specifies the PLL entry clock source. + * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 + * selected as PLL clock entry. + * RCC_PLLSource_HSE_Div1 - HSE oscillator clock selected as PLL + * clock entry. + * RCC_PLLSource_HSE_Div2 - HSE oscillator clock divided by 2 + * selected as PLL clock entry. + * RCC_PLLMul - specifies the PLL multiplication factor. + * This parameter can be RCC_PLLMul_x where x:[2,16]. + * + * @return none + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PLL_Mask; + tmpreg |= RCC_PLLSource | RCC_PLLMul; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLLCmd + * + * @brief Enables or disables the PLL. + * Note-The PLL can not be disabled if it is used as system clock. + * + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 24); + } + else + { + RCC->CTLR &= ~(1 << 24); + } +} + +/********************************************************************* + * @fn RCC_SYSCLKConfig + * + * @brief Configures the system clock (SYSCLK). + * + * @param RCC_SYSCLKSource - specifies the clock source used as system clock. + * RCC_SYSCLKSource_HSI - HSI selected as system clock. + * RCC_SYSCLKSource_HSE - HSE selected as system clock. + * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. + * + * @return none + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_SW_Mask; + tmpreg |= RCC_SYSCLKSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetSYSCLKSource + * + * @brief Returns the clock source used as system clock. + * + * @return 0x00 - HSI used as system clock. + * 0x04 - HSE used as system clock. + * 0x08 - PLL used as system clock. + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the AHB clock (HCLK). + * + * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. + * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. + * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. + * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. + * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. + * RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK1Config + * + * @brief Configures the Low Speed APB clock (PCLK1). + * + * @param RCC_HCLK - defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB1 clock = HCLK. + * RCC_HCLK_Div2 - APB1 clock = HCLK/2. + * RCC_HCLK_Div4 - APB1 clock = HCLK/4. + * RCC_HCLK_Div8 - APB1 clock = HCLK/8. + * RCC_HCLK_Div16 - APB1 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE1_Reset_Mask; + tmpreg |= RCC_HCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK2Config + * + * @brief Configures the High Speed APB clock (PCLK2). + * + * @param RCC_HCLK - defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB2 clock = HCLK. + * RCC_HCLK_Div2 - APB2 clock = HCLK/2. + * RCC_HCLK_Div4 - APB2 clock = HCLK/4. + * RCC_HCLK_Div8 - APB2 clock = HCLK/8. + * RCC_HCLK_Div16 - APB2 clock = HCLK/16. + * @return none + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE2_Reset_Mask; + tmpreg |= RCC_HCLK << 3; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_ITConfig + * + * @brief Enables or disables the specified RCC interrupts. + * + * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/********************************************************************* + * @fn RCC_USBCLKConfig + * + * @brief Configures the USB clock (USBCLK). + * + * @param RCC_USBCLKSource: specifies the USB clock source. This clock is + * derived from the PLL output. + * RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB + * clock source. + * RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source. + * + * @return none + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + if(RCC_USBCLKSource) + { + RCC->CFGR0 |= (1 << 22); + } + else + { + RCC->CFGR0 &= ~(1 << 22); + } +} + +/********************************************************************* + * @fn RCC_ADCCLKConfig + * + * @brief Configures the ADC clock (ADCCLK). + * + * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. + * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. + * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. + * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. + * + * @return none + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_ADCPRE_Reset_Mask; + tmpreg |= RCC_PCLK2; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_LSEConfig + * + * @brief Configures the External Low Speed oscillator (LSE). + * + * @param RCC_LSE - specifies the new state of the LSE. + * RCC_LSE_OFF - LSE oscillator OFF. + * RCC_LSE_ON - LSE oscillator ON. + * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. + * + * @return none + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; + + switch(RCC_LSE) + { + case RCC_LSE_ON: + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_LSICmd + * + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * Note- + * LSI can not be disabled if the IWDG is running. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_LSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->RSTSCKR |= (1 << 0); + } + else + { + RCC->RSTSCKR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_RTCCLKConfig + * + * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * + * @param RCC_RTCCLKSource - specifies the RTC clock source. + * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. + * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. + * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. + * Note- + * Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * @return none + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + RCC->BDCTLR |= RCC_RTCCLKSource; +} + +/********************************************************************* + * @fn RCC_RTCCLKCmd + * + * @brief This function must be used only after the RTC clock was selected + * using the RCC_RTCCLKConfig function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1 << 15); + } + else + { + RCC->BDCTLR &= ~(1 << 15); + } +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + + tmp = RCC->CFGR0 & CFGR0_SWS_Mask; + + switch(tmp) + { + case 0x00: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + + case 0x04: + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: + pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; + pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; + pllmull = (pllmull >> 18) + 2; + + if(pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) + { + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE)*pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + } + else + { + if((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) + { + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; + } + } + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/********************************************************************* + * @fn RCC_AHBPeriphClockCmd + * + * @brief Enables or disables the AHB peripheral clock. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. + * RCC_AHBPeriph_DMA1. + * RCC_AHBPeriph_DMA2. + * RCC_AHBPeriph_SRAM. + * Note- + * SRAM clock can be disabled only during sleep mode. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->AHBPCENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCENR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphClockCmd + * + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_ADC2 + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_TIM8 + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PCENR |= RCC_APB2Periph; + } + else + { + RCC->APB2PCENR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * RCC_APB1Periph_DAC. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PCENR |= RCC_APB1Periph; + } + else + { + RCC->APB1PCENR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphResetCmd + * + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PRSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2PRSTR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphResetCmd + * + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * RCC_APB1Periph_DAC. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PRSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1PRSTR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_BackupResetCmd + * + * @brief Forces or releases the Backup domain reset. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1 << 16); + } + else + { + RCC->BDCTLR &= ~(1 << 16); + } +} + +/********************************************************************* + * @fn RCC_ClockSecuritySystemCmd + * + * @brief Enables or disables the Clock Security System. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 19); + } + else + { + RCC->CTLR &= ~(1 << 19); + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * RCC_MCO_HSE - HSE oscillator clock selected. + * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_HSERDY - HSE oscillator clock ready. + * RCC_FLAG_PLLRDY - PLL clock ready. + * RCC_FLAG_LSERDY - LSE oscillator clock ready. + * RCC_FLAG_LSIRDY - LSI oscillator clock ready. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if(tmp == 1) + { + statusreg = RCC->CTLR; + } + else if(tmp == 2) + { + statusreg = RCC->BDCTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * Note- + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + +/********************************************************************* + * @fn RCC_GetITStatus + * + * @brief Checks whether the specified RCC interrupt has occurred or not. + * + * @param RCC_IT - specifies the RCC interrupt source to check. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return ITStatus - SET or RESET. + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + if((RCC->INTR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearITPendingBit + * + * @brief Clears the RCC's interrupt pending bits. + * + * @param RCC_IT - specifies the interrupt pending bit to clear. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return none + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT; +} + + + diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_rtc.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_rtc.c index f2a9496..37e3d93 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_rtc.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_rtc.c @@ -1,279 +1,316 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_rtc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the RTC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_rtc.h" - -/* RTC_Private_Defines */ -#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ -#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ - -/********************************************************************* - * @fn RTC_ITConfig - * - * @brief Enables or disables the specified RTC interrupts. - * - * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. - * RTC_IT_OW - Overflow interrupt - * RTC_IT_ALR - Alarm interrupt - * RTC_IT_SEC - Second interrupt - * - * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). - */ -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RTC->CTLRH |= RTC_IT; - } - else - { - RTC->CTLRH &= (uint16_t)~RTC_IT; - } -} - -/********************************************************************* - * @fn RTC_EnterConfigMode - * - * @brief Enters the RTC configuration mode. - * - * @return none - */ -void RTC_EnterConfigMode(void) -{ - RTC->CTLRL |= RTC_CTLRL_CNF; -} - -/********************************************************************* - * @fn RTC_ExitConfigMode - * - * @brief Exits from the RTC configuration mode. - * - * @return none - */ -void RTC_ExitConfigMode(void) -{ - RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); -} - -/********************************************************************* - * @fn RTC_GetCounter - * - * @brief Gets the RTC counter value - * - * @return RTC counter value - */ -uint32_t RTC_GetCounter(void) -{ - uint16_t high1 = 0, high2 = 0, low = 0; - - high1 = RTC->CNTH; - low = RTC->CNTL; - high2 = RTC->CNTH; - - if(high1 != high2) - { - return (((uint32_t)high2 << 16) | RTC->CNTL); - } - else - { - return (((uint32_t)high1 << 16) | low); - } -} - -/********************************************************************* - * @fn RTC_SetCounter - * - * @brief Sets the RTC counter value. - * - * @param CounterValue - RTC counter new value. - * - * @return RTC counter value - */ -void RTC_SetCounter(uint32_t CounterValue) -{ - RTC_EnterConfigMode(); - RTC->CNTH = CounterValue >> 16; - RTC->CNTL = (CounterValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/********************************************************************* - * @fn RTC_SetPrescaler - * - * @brief Sets the RTC prescaler value - * - * @param PrescalerValue - RTC prescaler new value - * - * @return none - */ -void RTC_SetPrescaler(uint32_t PrescalerValue) -{ - RTC_EnterConfigMode(); - RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; - RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/********************************************************************* - * @fn RTC_SetAlarm - * - * @brief Sets the RTC alarm value - * - * @param AlarmValue - RTC alarm new value - * - * @return none - */ -void RTC_SetAlarm(uint32_t AlarmValue) -{ - RTC_EnterConfigMode(); - RTC->ALRMH = AlarmValue >> 16; - RTC->ALRML = (AlarmValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/********************************************************************* - * @fn RTC_GetDivider - * - * @brief Gets the RTC divider value - * - * @return RTC Divider value - */ -uint32_t RTC_GetDivider(void) -{ - uint32_t tmp = 0x00; - tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; - tmp |= RTC->DIVL; - return tmp; -} - -/********************************************************************* - * @fn RTC_WaitForLastTask - * - * @brief Waits until last write operation on RTC registers has finished - * Note- - * This function must be called before any write to RTC registers. - * @return none - */ -void RTC_WaitForLastTask(void) -{ - while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) - { - } -} - -/********************************************************************* - * @fn RTC_WaitForSynchro - * - * @brief Waits until the RTC registers are synchronized with RTC APB clock - * Note- - * This function must be called before any read operation after an APB reset - * or an APB clock stop. - * - * @return none - */ -void RTC_WaitForSynchro(void) -{ - RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; - while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) - { - } -} - -/********************************************************************* - * @fn RTC_GetFlagStatus - * - * @brief Checks whether the specified RTC flag is set or not - * - * @param RTC_FLAG- specifies the flag to check - * RTC_FLAG_RTOFF - RTC Operation OFF flag - * RTC_FLAG_RSF - Registers Synchronized flag - * RTC_FLAG_OW - Overflow flag - * RTC_FLAG_ALR - Alarm flag - * RTC_FLAG_SEC - Second flag - * - * @return The new state of RTC_FLAG (SET or RESET) - */ -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn RTC_ClearFlag - * - * @brief Clears the RTC's pending flags - * - * @param RTC_FLAG - specifies the flag to clear - * RTC_FLAG_RSF - Registers Synchronized flag - * RTC_FLAG_OW - Overflow flag - * RTC_FLAG_ALR - Alarm flag - * RTC_FLAG_SEC - Second flag - * - * @return none - */ -void RTC_ClearFlag(uint16_t RTC_FLAG) -{ - RTC->CTLRL &= (uint16_t)~RTC_FLAG; -} - -/********************************************************************* - * @fn RTC_GetITStatus - * - * @brief Checks whether the specified RTC interrupt has occurred or not - * - * @param RTC_IT - specifies the RTC interrupts sources to check - * RTC_FLAG_OW - Overflow interrupt - * RTC_FLAG_ALR - Alarm interrupt - * RTC_FLAG_SEC - Second interrupt - * - * @return The new state of the RTC_IT (SET or RESET) - */ -ITStatus RTC_GetITStatus(uint16_t RTC_IT) -{ - ITStatus bitstatus = RESET; - - bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); - if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn RTC_ClearITPendingBit - * - * @brief Clears the RTC's interrupt pending bits - * - * @param RTC_IT - specifies the interrupt pending bit to clear - * RTC_FLAG_OW - Overflow interrupt - * RTC_FLAG_ALR - Alarm interrupt - * RTC_FLAG_SEC - Second interrupt - * - * @return none - */ -void RTC_ClearITPendingBit(uint16_t RTC_IT) -{ - RTC->CTLRL &= (uint16_t)~RTC_IT; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_rtc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the RTC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_rtc.h" + +/* RTC_Private_Defines */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ + +/********************************************************************* + * @fn RTC_ITConfig + * + * @brief Enables or disables the specified RTC interrupts. + * + * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. + * RTC_IT_OW - Overflow interrupt + * RTC_IT_ALR - Alarm interrupt + * RTC_IT_SEC - Second interrupt + * + * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RTC->CTLRH |= RTC_IT; + } + else + { + RTC->CTLRH &= (uint16_t)~RTC_IT; + } +} + +/********************************************************************* + * @fn RTC_EnterConfigMode + * + * @brief Enters the RTC configuration mode. + * + * @return none + */ +void RTC_EnterConfigMode(void) +{ + RTC->CTLRL |= RTC_CTLRL_CNF; +} + +/********************************************************************* + * @fn RTC_ExitConfigMode + * + * @brief Exits from the RTC configuration mode. + * + * @return none + */ +void RTC_ExitConfigMode(void) +{ + RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); +} + +/********************************************************************* + * @fn RTC_GetCounter + * + * @brief Gets the RTC counter value + * + * @return RTC counter value + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0; + uint16_t low1 = 0, low2 = 0; + + do{ + high1a = RTC->CNTH; + high1b = RTC->CNTH; + }while( high1a != high1b ); + + do{ + low1 = RTC->CNTL; + low2 = RTC->CNTL; + }while( low1 != low2 ); + + do{ + high2a = RTC->CNTH; + high2b = RTC->CNTH; + }while( high2a != high2b ); + + if(high1b != high2b) + { + do{ + low1 = RTC->CNTL; + low2 = RTC->CNTL; + }while( low1 != low2 ); + } + + return (((uint32_t)high2b << 16) | low2); +} + +/********************************************************************* + * @fn RTC_SetCounter + * + * @brief Sets the RTC counter value. + * + * @param CounterValue - RTC counter new value. + * + * @return RTC counter value + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + RTC->CNTH = CounterValue >> 16; + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetPrescaler + * + * @brief Sets the RTC prescaler value + * + * @param PrescalerValue - RTC prescaler new value + * + * @return none + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + RTC_EnterConfigMode(); + RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetAlarm + * + * @brief Sets the RTC alarm value + * + * @param AlarmValue - RTC alarm new value + * + * @return none + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + RTC->ALRMH = AlarmValue >> 16; + RTC->ALRML = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_GetDivider + * + * @brief Gets the RTC divider value + * + * @return RTC Divider value + */ +uint32_t RTC_GetDivider(void) +{ + uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0; + uint16_t low1 = 0, low2 = 0; + + do{ + high1a = RTC->DIVH; + high1b = RTC->DIVH; + }while( high1a != high1b ); + + do{ + low1 = RTC->DIVL; + low2 = RTC->DIVL; + }while( low1 != low2 ); + + do{ + high2a = RTC->DIVH; + high2b = RTC->DIVH; + }while( high2a != high2b ); + + if(high1b != high2b) + { + do{ + low1 = RTC->DIVL; + low2 = RTC->DIVL; + }while( low1 != low2 ); + } + + return ((((uint32_t)high2b & (uint32_t)0x000F) << 16) | low2); +} + + +/********************************************************************* + * @fn RTC_WaitForLastTask + * + * @brief Waits until last write operation on RTC registers has finished + * Note- + * This function must be called before any write to RTC registers. + * @return none + */ +void RTC_WaitForLastTask(void) +{ + while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_WaitForSynchro + * + * @brief Waits until the RTC registers are synchronized with RTC APB clock + * Note- + * This function must be called before any read operation after an APB reset + * or an APB clock stop. + * + * @return none + */ +void RTC_WaitForSynchro(void) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; + while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_GetFlagStatus + * + * @brief Checks whether the specified RTC flag is set or not + * + * @param RTC_FLAG- specifies the flag to check + * RTC_FLAG_RTOFF - RTC Operation OFF flag + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return The new state of RTC_FLAG (SET or RESET) + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearFlag + * + * @brief Clears the RTC's pending flags + * + * @param RTC_FLAG - specifies the flag to clear + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return none + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG; +} + +/********************************************************************* + * @fn RTC_GetITStatus + * + * @brief Checks whether the specified RTC interrupt has occurred or not + * + * @param RTC_IT - specifies the RTC interrupts sources to check + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return The new state of the RTC_IT (SET or RESET) + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + + bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); + if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearITPendingBit + * + * @brief Clears the RTC's interrupt pending bits + * + * @param RTC_IT - specifies the interrupt pending bit to clear + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return none + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + RTC->CTLRL &= (uint16_t)~RTC_IT; +} diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_spi.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_spi.c index 64ea960..cc8238f 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_spi.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_spi.c @@ -1,671 +1,671 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_spi.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the SPI firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_spi.h" -#include "ch32v10x_rcc.h" - -/* SPI SPE mask */ -#define CTLR1_SPE_Set ((uint16_t)0x0040) -#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) - -/* I2S I2SE mask */ -#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) -#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) - -/* SPI CRCNext mask */ -#define CTLR1_CRCNext_Set ((uint16_t)0x1000) - -/* SPI CRCEN mask */ -#define CTLR1_CRCEN_Set ((uint16_t)0x2000) -#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) - -/* SPI SSOE mask */ -#define CTLR2_SSOE_Set ((uint16_t)0x0004) -#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) - -/* SPI registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) - -/* SPI or I2S mode selection masks */ -#define SPI_Mode_Select ((uint16_t)0xF7FF) -#define I2S_Mode_Select ((uint16_t)0x0800) - -/* I2S clock source selection masks */ -#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) -#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) -#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) -#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) - -/********************************************************************* - * @fn SPI_I2S_DeInit - * - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values (Affects also the I2Ss). - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * - * @return none - */ -void SPI_I2S_DeInit(SPI_TypeDef *SPIx) -{ - if(SPIx == SPI1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if(SPIx == SPI2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else - { - if(SPIx == SPI3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - } -} - -/********************************************************************* - * @fn SPI_Init - * - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * - * @return none - */ -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - tmpreg = SPIx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - - SPIx->CTLR1 = tmpreg; - SPIx->I2SCFGR &= SPI_Mode_Select; - SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/********************************************************************* - * @fn I2S_Init - * - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * (configured in I2S mode). - * I2S_InitStruct - pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * @return none - */ -void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0; - RCC_ClocksTypeDef RCC_Clocks; - uint32_t sourceclock = 0; - - SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; - SPIx->I2SPR = 0x0002; - tmpreg = SPIx->I2SCFGR; - - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - else - { - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - packetlength = 1; - } - else - { - packetlength = 2; - } - - if(((uint32_t)SPIx) == SPI2_BASE) - { - tmp = I2S2_CLOCK_SRC; - } - else - { - tmp = I2S3_CLOCK_SRC; - } - - RCC_GetClocksFreq(&RCC_Clocks); - - sourceclock = RCC_Clocks.SYSCLK_Frequency; - - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - tmp = tmp / 10; - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - i2sodd = (uint16_t)(i2sodd << 8); - } - - if((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - i2sdiv = 2; - i2sodd = 0; - } - - SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - SPIx->I2SCFGR = tmpreg; -} - -/********************************************************************* - * @fn SPI_StructInit - * - * @brief Fills each SPI_InitStruct member with its default value. - * - * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) -{ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/********************************************************************* - * @fn I2S_StructInit - * - * @brief Fills each I2S_InitStruct member with its default value. - * - * @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct) -{ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/********************************************************************* - * @fn SPI_Cmd - * - * @brief Enables or disables the specified SPI peripheral. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_SPE_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_SPE_Reset; - } -} - -/********************************************************************* - * @fn I2S_Cmd - * - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; - } - else - { - SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; - } -} - -/********************************************************************* - * @fn SPI_I2S_ITConfig - * - * @brief Enables or disables the specified SPI/I2S interrupts. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_IT - specifies the SPI/I2S interrupt source to be - * enabled or disabled. - * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. - * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. - * SPI_I2S_IT_ERR - Error interrupt mask. - * NewState: ENABLE or DISABLE. - * @return none - */ -void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0; - - itpos = SPI_I2S_IT >> 4; - itmask = (uint16_t)1 << (uint16_t)itpos; - - if(NewState != DISABLE) - { - SPIx->CTLR2 |= itmask; - } - else - { - SPIx->CTLR2 &= (uint16_t)~itmask; - } -} - -/********************************************************************* - * @fn SPI_I2S_DMACmd - * - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to - * be enabled or disabled. - * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. - * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= SPI_I2S_DMAReq; - } - else - { - SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/********************************************************************* - * @fn SPI_I2S_SendData - * - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * Data - Data to be transmitted. - * - * @return none - */ -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) -{ - SPIx->DATAR = Data; -} - -/********************************************************************* - * @fn SPI_I2S_ReceiveData - * - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * Data - Data to be transmitted. - * - * @return SPIx->DATAR - The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) -{ - return SPIx->DATAR; -} - -/********************************************************************* - * @fn SPI_NSSInternalSoftwareConfig - * - * @brief Configures internally by software the NSS pin for the selected SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_NSSInternalSoft - - * SPI_NSSInternalSoft_Set - Set NSS pin internally. - * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. - * - * @return none - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) -{ - if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; - } - else - { - SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/********************************************************************* - * @fn SPI_SSOutputCmd - * - * @brief Enables or disables the SS output for the selected SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * NewState - new state of the SPIx SS output. - * - * @return none - */ -void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= CTLR2_SSOE_Set; - } - else - { - SPIx->CTLR2 &= CTLR2_SSOE_Reset; - } -} - -/********************************************************************* - * @fn SPI_DataSizeConfig - * - * @brief Configures the data size for the selected SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_DataSize - specifies the SPI data size. - * SPI_DataSize_16b - Set data frame format to 16bit. - * SPI_DataSize_8b - Set data frame format to 8bit. - * - * @return none - */ -void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) -{ - SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; - SPIx->CTLR1 |= SPI_DataSize; -} - -/********************************************************************* - * @fn SPI_TransmitCRC - * - * @brief Transmit the SPIx CRC value. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * - * @return none - */ -void SPI_TransmitCRC(SPI_TypeDef *SPIx) -{ - SPIx->CTLR1 |= CTLR1_CRCNext_Set; -} - -/********************************************************************* - * @fn SPI_CalculateCRC - * - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * NewState - new state of the SPIx CRC value calculation. - * - * @return none - */ -void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_CRCEN_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_CRCEN_Reset; - } -} - -/********************************************************************* - * @fn SPI_GetCRC - * - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_CRC - specifies the CRC register to be read. - * SPI_CRC_Tx - Selects Tx CRC register. - * SPI_CRC_Rx - Selects Rx CRC register. - * - * @return crcreg: The selected CRC register value. - */ -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - - if(SPI_CRC != SPI_CRC_Rx) - { - crcreg = SPIx->TCRCR; - } - else - { - crcreg = SPIx->RCRCR; - } - - return crcreg; -} - -/********************************************************************* - * @fn SPI_GetCRCPolynomial - * - * @brief Returns the CRC Polynomial register value for the specified SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * - * @return SPIx->CRCR - The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) -{ - return SPIx->CRCR; -} - -/********************************************************************* - * @fn SPI_BiDirectionalLineConfig - * - * @brief Selects the data transfer direction in bi-directional mode - * for the specified SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_Direction - specifies the data transfer direction in - * bi-directional mode. - * SPI_Direction_Tx - Selects Tx transmission direction. - * SPI_Direction_Rx - Selects Rx receive direction. - * - * @return none - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) -{ - if(SPI_Direction == SPI_Direction_Tx) - { - SPIx->CTLR1 |= SPI_Direction_Tx; - } - else - { - SPIx->CTLR1 &= SPI_Direction_Rx; - } -} - -/********************************************************************* - * @fn SPI_I2S_GetFlagStatus - * - * @brief Checks whether the specified SPI/I2S flag is set or not. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. - * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. - * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. - * SPI_I2S_FLAG_BSY - Busy flag. - * SPI_I2S_FLAG_OVR - Overrun flag. - * SPI_FLAG_MODF - Mode Fault flag. - * SPI_FLAG_CRCERR - CRC Error flag. - * I2S_FLAG_UDR - Underrun Error flag. - * I2S_FLAG_CHSIDE - Channel Side flag. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearFlag - * - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_FLAG - specifies the SPI flag to clear. - * SPI_FLAG_CRCERR - CRC Error flag. - * Note- - * - OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). - * - UDR (UnderRun error) flag is cleared by a read operation to - * SPI_STATR register (SPI_I2S_GetFlagStatus()). - * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). - * @return FlagStatus: SET or RESET. - */ -void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; -} - -/********************************************************************* - * @fn SPI_I2S_GetITStatus - * - * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_IT - specifies the SPI/I2S interrupt source to check.. - * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. - * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. - * SPI_I2S_IT_OVR - Overrun interrupt. - * SPI_IT_MODF - Mode Fault interrupt. - * SPI_IT_CRCERR - CRC Error interrupt. - * I2S_IT_UDR - Underrun Error interrupt. - * - * @return FlagStatus: SET or RESET. - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - itmask = SPI_I2S_IT >> 4; - itmask = 0x01 << itmask; - enablestatus = (SPIx->CTLR2 & itmask); - - if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearITPendingBit - * - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. - * SPI_IT_CRCERR - CRC Error interrupt. - * Note- - * - OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). - * - UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_STATR register (SPI_I2S_GetITStatus()). - * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable - * the SPI). - * @return none - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - SPIx->STATR = (uint16_t)~itpos; -} - - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_spi.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the SPI firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_spi.h" +#include "ch32v10x_rcc.h" + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if(SPIx == SPI2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if(SPIx == SPI3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->I2SCFGR &= SPI_Mode_Select; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn I2S_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * (configured in I2S mode). + * I2S_InitStruct - pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @return none + */ +void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + tmpreg = SPIx->I2SCFGR; + + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + else + { + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + packetlength = 1; + } + else + { + packetlength = 2; + } + + if(((uint32_t)SPIx) == SPI2_BASE) + { + tmp = I2S2_CLOCK_SRC; + } + else + { + tmp = I2S3_CLOCK_SRC; + } + + RCC_GetClocksFreq(&RCC_Clocks); + + sourceclock = RCC_Clocks.SYSCLK_Frequency; + + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + tmp = tmp / 10; + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + i2sodd = (uint16_t)(i2sodd << 8); + } + + if((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + i2sdiv = 2; + i2sodd = 0; + } + + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + SPIx->I2SCFGR = tmpreg; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn I2S_StructInit + * + * @brief Fills each I2S_InitStruct member with its default value. + * + * @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct) +{ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn I2S_Cmd + * + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI/I2S interrupts. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState: ENABLE or DISABLE. + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg: The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI/I2S flag is set or not. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * I2S_FLAG_UDR - Underrun Error flag. + * I2S_FLAG_CHSIDE - Channel Side flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * Note- + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). + * @return FlagStatus: SET or RESET. + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * I2S_IT_UDR - Underrun Error interrupt. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * Note- + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable + * the SPI). + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} + + + + + + diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_tim.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_tim.c index 7ae1459..7a772b6 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_tim.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_tim.c @@ -1,2355 +1,2355 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_tim.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the TIM firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_tim.h" -#include "ch32v10x_rcc.h" - -/* TIM registers bit mask */ -#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) -#define CHCTLR_Offset ((uint16_t)0x0018) -#define CCER_CCE_Set ((uint16_t)0x0001) -#define CCER_CCNE_Set ((uint16_t)0x0004) - -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/********************************************************************* - * @fn TIM_DeInit - * - * @brief Deinitializes the TIMx peripheral registers to their default - * reset values. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * - * @return none - */ -void TIM_DeInit(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if(TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if(TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if(TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } -} - -/********************************************************************* - * @fn TIM_TimeBaseInit - * - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef - * structure. - * - * @return none - */ -void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - tmpcr1 = TIMx->CTLR1; - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) - { - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - - TIMx->CTLR1 = tmpcr1; - TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if(TIMx == TIM1) - { - TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; -} - -/********************************************************************* - * @fn TIM_OC1Init - * - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if(TIMx == TIM1) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); - - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2Init - * - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if(TIMx == TIM1) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3Init - * - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if(TIMx == TIM1) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4Init - * - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if(TIMx == TIM1) - { - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ICInit - * - * @brief IInitializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_PWMIConfig - * - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external - * PWM signal. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - - if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_BDTRConfig - * - * @brief Configures the: Break feature, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable). - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/********************************************************************* - * @fn TIM_TimeBaseStructInit - * - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * - * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. - * - * @return none - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/********************************************************************* - * @fn TIM_OCStructInit - * - * @brief Fills each TIM_OCInitStruct member with its default value. - * - * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/********************************************************************* - * @fn TIM_ICStructInit - * - * @brief Fills each TIM_ICInitStruct member with its default value. - * - * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/********************************************************************* - * @fn TIM_BDTRStructInit - * - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * - * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/********************************************************************* - * @fn TIM_Cmd - * - * @brief Enables or disables the specified TIM peripheral. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_CEN; - } - else - { - TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); - } -} - -/********************************************************************* - * @fn TIM_CtrlPWMOutputs - * - * @brief Enables or disables the TIM peripheral Main Outputs. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->BDTR |= TIM_MOE; - } - else - { - TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); - } -} - -/********************************************************************* - * @fn TIM_ITConfig - * - * @brief Enables or disables the specified TIM interrupts. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->DMAINTENR |= TIM_IT; - } - else - { - TIMx->DMAINTENR &= (uint16_t)~TIM_IT; - } -} - -/********************************************************************* - * @fn TIM_GenerateEvent - * - * @brief Configures the TIMx event to be generate by software. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) -{ - TIMx->SWEVGR = TIM_EventSource; -} - -/********************************************************************* - * @fn TIM_DMAConfig - * - * @brief Configures the TIMx's DMA interface. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_DMABase: DMA Base address. - * TIM_DMABase_CR. - * TIM_DMABase_CR2. - * TIM_DMABase_SMCR. - * TIM_DMABase_DIER. - * TIM1_DMABase_SR. - * TIM_DMABase_EGR. - * TIM_DMABase_CCMR1. - * TIM_DMABase_CCMR2. - * TIM_DMABase_CCER. - * TIM_DMABase_CNT. - * TIM_DMABase_PSC. - * TIM_DMABase_CCR1. - * TIM_DMABase_CCR2. - * TIM_DMABase_CCR3. - * TIM_DMABase_CCR4. - * TIM_DMABase_BDTR. - * TIM_DMABase_DCR. - * TIM_DMABurstLength - DMA Burst length. - * TIM_DMABurstLength_1Transfer. - * TIM_DMABurstLength_18Transfers. - * - * @return none - */ -void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; -} - -/********************************************************************* - * @fn TIM_DMACmd - * - * @brief Enables or disables the TIMx's DMA Requests. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_DMASource - specifies the DMA Request sources. - * TIM_DMA_Update - TIM update Interrupt source. - * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. - * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. - * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. - * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. - * TIM_DMA_COM - TIM Commutation DMA source. - * TIM_DMA_Trigger - TIM Trigger DMA source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->DMAINTENR |= TIM_DMASource; - } - else - { - TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; - } -} - -/********************************************************************* - * @fn TIM_InternalClockConfig - * - * @brief Configures the TIMx internal Clock. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * - * @return none - */ -void TIM_InternalClockConfig(TIM_TypeDef *TIMx) -{ - TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); -} - -/********************************************************************* - * @fn TIM_ITRxExternalClockConfig - * - * @brief Configures the TIMx Internal Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_InputTriggerSource: Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * - * @return none - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_TIxExternalClockConfig - * - * @brief Configures the TIMx Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_TIxExternalCLKSource - Trigger source. - * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. - * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. - * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. - * TIM_ICPolarity - specifies the TIx Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_DMA_COM - TIM Commutation DMA source. - * TIM_DMA_Trigger - TIM Trigger DMA source. - * ICFilter - specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_ETRClockMode1Config - * - * @brief Configures the External clock Mode1. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_SlaveMode_External1; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_TS_ETRF; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_ETRClockMode2Config - * - * @brief Configures the External clock Mode2. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - TIMx->SMCFGR |= TIM_ECE; -} - -/********************************************************************* - * @fn TIM_ETRConfig - * - * @brief Configures the TIMx External Trigger (ETR). - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= SMCFGR_ETR_Mask; - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_PrescalerConfig - * - * @brief Configures the TIMx Prescaler. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * Prescaler - specifies the Prescaler Register value. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. - * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. - * - * @return none - */ -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - TIMx->PSC = Prescaler; - TIMx->SWEVGR = TIM_PSCReloadMode; -} - -/********************************************************************* - * @fn TIM_CounterModeConfig - * - * @brief Specifies the TIMx Counter Mode to be used. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_CounterMode - specifies the Counter Mode to be used. - * TIM_CounterMode_Up - TIM Up Counting Mode. - * TIM_CounterMode_Down - TIM Down Counting Mode. - * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. - * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. - * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. - * - * @return none - */ -void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - tmpcr1 = TIMx->CTLR1; - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= TIM_CounterMode; - TIMx->CTLR1 = tmpcr1; -} - -/********************************************************************* - * @fn TIM_SelectInputTrigger - * - * @brief Selects the Input Trigger source. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_InputTriggerSource - The Input Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * TIM_TS_TI1F_ED - TI1 Edge Detector. - * TIM_TS_TI1FP1 - Filtered Timer Input 1. - * TIM_TS_TI2FP2 - Filtered Timer Input 2. - * TIM_TS_ETRF - External Trigger input. - * - * @return none - */ -void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_InputTriggerSource; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_EncoderInterfaceConfig - * - * @brief Configures the TIMx Encoder Interface. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_EncoderMode - specifies the TIMx Encoder Mode. - * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending - * on TI2FP2 level. - * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending - * on TI1FP1 level. - * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and - * TI2FP2 edges depending. - * TIM_IC1Polarity - specifies the IC1 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TTIM_ICPolarity_Rising - IC Rising edge. - * TIM_IC2Polarity - specifies the IC2 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TIM_ICPolarity_Rising - IC Rising edge. - * - * @return none - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_EncoderMode; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); - tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; - tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - TIMx->SMCFGR = tmpsmcr; - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ForcedOC1Config - * - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC1REF. - * TIM_ForcedAction_InActive - Force inactive level on OC1REF. - * - * @return none - */ -void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); - tmpccmr1 |= TIM_ForcedAction; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC2Config - * - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC2REF. - * TIM_ForcedAction_InActive - Force inactive level on OC2REF. - * - * @return none - */ -void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC3Config - * - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC3REF. - * TIM_ForcedAction_InActive - Force inactive level on OC3REF. - * - * @return none - */ -void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); - tmpccmr2 |= TIM_ForcedAction; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ForcedOC4Config - * - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC4REF. - * TIM_ForcedAction_InActive - Force inactive level on OC4REF. - * - * @return none - */ -void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ARRPreloadConfig - * - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_ARPE; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); - } -} - -/********************************************************************* - * @fn TIM_SelectCOM - * - * @brief Selects the TIM peripheral Commutation event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCUS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); - } -} - -/********************************************************************* - * @fn TIM_SelectCCDMA - * - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCDS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); - } -} - -/********************************************************************* - * @fn TIM_CCPreloadControl - * - * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. - * reset values (Affects also the I2Ss). - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCPC; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); - } -} - -/********************************************************************* - * @fn TIM_OC1PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); - tmpccmr1 |= TIM_OCPreload; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC2PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC3PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); - tmpccmr2 |= TIM_OCPreload; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC4PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC1FastConfig - * - * @brief Configures the TIMx Output Compare 1 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); - tmpccmr1 |= TIM_OCFast; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC2FastConfig - * - * @brief Configures the TIMx Output Compare 2 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC3FastConfig - * - * @brief Configures the TIMx Output Compare 3 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); - tmpccmr2 |= TIM_OCFast; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC4FastConfig - * - * @brief Configures the TIMx Output Compare 4 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC1Ref - * - * @brief Clears or safeguards the OCREF1 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); - tmpccmr1 |= TIM_OCClear; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC2Ref - * - * @brief Clears or safeguards the OCREF2 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC3Ref - * - * @brief Clears or safeguards the OCREF3 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); - tmpccmr2 |= TIM_OCClear; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC4Ref - * - * @brief Clears or safeguards the OCREF4 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC1PolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC1 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); - tmpccer |= TIM_OCPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC1NPolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); - tmpccer |= TIM_OCNPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2PolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC2 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2NPolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3PolarityConfig - * - * @brief Configures the TIMx Channel 3 polarity. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3NPolarityConfig - * - * @brief Configures the TIMx Channel 3N polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC2N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4PolarityConfig - * - * @brief Configures the TIMx Channel 4 polarity. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_CCxCmd - * - * @brief Enables or disables the TIM Capture Compare Channel x. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_CCx - specifies the TIM Channel CCxE bit new state. - * TIM_CCx_Enable. - * TIM_CCx_Disable. - * - * @return none - */ -void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - tmp = CCER_CCE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_CCxNCmd - * - * @brief Enables or disables the TIM Capture Compare Channel xN. - * - * @param TIMx - where x can be 1 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. - * TIM_CCxN_Enable. - * TIM_CCxN_Disable. - * - * @return none - */ -void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - tmp = CCER_CCNE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_SelectOCxM - * - * @brief Selects the TIM Output Compare Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_OCMode - specifies the TIM Output Compare Mode. - * TIM_OCMode_Timing. - * TIM_OCMode_Active. - * TIM_OCMode_Toggle. - * TIM_OCMode_PWM1. - * TIM_OCMode_PWM2. - * TIM_ForcedAction_Active. - * TIM_ForcedAction_InActive. - * - * @return none - */ -void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - tmp = (uint32_t)TIMx; - tmp += CHCTLR_Offset; - tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp1; - - if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel >> 1); - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); - *(__IO uint32_t *)tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); - *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/********************************************************************* - * @fn TIM_UpdateDisableConfig - * - * @brief Enables or Disables the TIMx Update event. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_UDIS; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); - } -} - -/********************************************************************* - * @fn TIM_UpdateRequestConfig - * - * @brief Configures the TIMx Update Request Interrupt source. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_UpdateSource - specifies the Update source. - * TIM_UpdateSource_Regular. - * TIM_UpdateSource_Global. - * - * @return none - */ -void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) -{ - if(TIM_UpdateSource != TIM_UpdateSource_Global) - { - TIMx->CTLR1 |= TIM_URS; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); - } -} - -/********************************************************************* - * @fn TIM_SelectHallSensor - * - * @brief Enables or disables the TIMx's Hall sensor interface. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_TI1S; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); - } -} - -/********************************************************************* - * @fn TIM_SelectOnePulseMode - * - * @brief Selects the TIMx's One Pulse Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OPMode - specifies the OPM Mode to be used. - * TIM_OPMode_Single. - * TIM_OPMode_Repetitive. - * - * @return none - */ -void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); - TIMx->CTLR1 |= TIM_OPMode; -} - -/********************************************************************* - * @fn TIM_SelectOutputTrigger - * - * @brief Selects the TIMx Trigger Output Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_TRGOSource - specifies the Trigger Output source. - * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is - * used as the trigger output (TRGO). - * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the - * trigger output (TRGO). - * TIM_TRGOSource_Update - The update event is selected as the - * trigger output (TRGO). - * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse - * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). - * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). - * - * @return none - */ -void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) -{ - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); - TIMx->CTLR2 |= TIM_TRGOSource; -} - -/********************************************************************* - * @fn TIM_SelectSlaveMode - * - * @brief Selects the TIMx Slave Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_SlaveMode - specifies the Timer Slave Mode. - * TIM_SlaveMode_Reset - Rising edge of the selected trigger - * signal (TRGI) re-initializes. - * TIM_SlaveMode_Gated - The counter clock is enabled when the - * trigger signal (TRGI) is high. - * TIM_SlaveMode_Trigger - The counter starts at a rising edge - * of the trigger TRGI. - * TIM_SlaveMode_External1 - Rising edges of the selected trigger - * (TRGI) clock the counter. - * - * @return none - */ -void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) -{ - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); - TIMx->SMCFGR |= TIM_SlaveMode; -} - -/********************************************************************* - * @fn TIM_SelectMasterSlaveMode - * - * @brief Sets or Resets the TIMx Master/Slave Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. - * TIM_MasterSlaveMode_Enable - synchronization between the current - * timer and its slaves (through TRGO). - * TIM_MasterSlaveMode_Disable - No action. - * - * @return none - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) -{ - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); - TIMx->SMCFGR |= TIM_MasterSlaveMode; -} - -/********************************************************************* - * @fn TIM_SetCounter - * - * @brief Sets the TIMx Counter Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Counter - specifies the Counter register new value. - * - * @return none - */ -void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) -{ - TIMx->CNT = Counter; -} - -/********************************************************************* - * @fn TIM_SetAutoreload - * - * @brief Sets the TIMx Autoreload Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Autoreload - specifies the Autoreload register new value. - * - * @return none - */ -void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) -{ - TIMx->ATRLR = Autoreload; -} - -/********************************************************************* - * @fn TIM_SetCompare1 - * - * @brief Sets the TIMx Capture Compare1 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) -{ - TIMx->CH1CVR = Compare1; -} - -/********************************************************************* - * @fn TIM_SetCompare2 - * - * @brief Sets the TIMx Capture Compare2 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) -{ - TIMx->CH2CVR = Compare2; -} - -/********************************************************************* - * @fn TIM_SetCompare3 - * - * @brief Sets the TIMx Capture Compare3 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) -{ - TIMx->CH3CVR = Compare3; -} - -/********************************************************************* - * @fn TIM_SetCompare4 - * - * @brief Sets the TIMx Capture Compare4 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) -{ - TIMx->CH4CVR = Compare4; -} - -/********************************************************************* - * @fn TIM_SetIC1Prescaler - * - * @brief Sets the TIMx Input Capture 1 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); - TIMx->CHCTLR1 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC2Prescaler - * - * @brief Sets the TIMx Input Capture 2 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); - TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetIC3Prescaler - * - * @brief Sets the TIMx Input Capture 3 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); - TIMx->CHCTLR2 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC4Prescaler - * - * @brief Sets the TIMx Input Capture 4 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); - TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetClockDivision - * - * @brief Sets the TIMx Clock Division value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_CKD - specifies the clock division value. - * TIM_CKD_DIV1 - TDTS = Tck_tim. - * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. - * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. - * - * @return none - */ -void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); - TIMx->CTLR1 |= TIM_CKD; -} - -/********************************************************************* - * @fn TIM_GetCapture1 - * - * @brief Gets the TIMx Input Capture 1 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH1CVR - Capture Compare 1 Register value. - */ -uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) -{ - return TIMx->CH1CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture2 - * - * @brief Gets the TIMx Input Capture 2 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH2CVR - Capture Compare 2 Register value. - */ -uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) -{ - return TIMx->CH2CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture2 - * - * @brief Gets the TIMx Input Capture 2 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH2CVR - Capture Compare 2 Register value. - */ -uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) -{ - return TIMx->CH3CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture4 - * - * @brief Gets the TIMx Input Capture 4 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH4CVR - Capture Compare 4 Register value. - */ -uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) -{ - return TIMx->CH4CVR; -} - -/********************************************************************* - * @fn TIM_GetCounter - * - * @brief Gets the TIMx Counter value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CNT - Counter Register value. - */ -uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) -{ - return TIMx->CNT; -} - -/********************************************************************* - * @fn TIM_GetPrescaler - * - * @brief Gets the TIMx Prescaler value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->PSC - Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) -{ - return TIMx->PSC; -} - -/********************************************************************* - * @fn TIM_GetFlagStatus - * - * @brief Checks whether the specified TIM flag is set or not. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return SET or RESET. - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - - if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearFlag - * - * @brief Clears the TIMx's pending flags. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return none - */ -void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - TIMx->INTFR = (uint16_t)~TIM_FLAG; -} - -/********************************************************************* - * @fn TIM_GetITStatus - * - * @brief Checks whether the TIM interrupt has occurred or not. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - - itstatus = TIMx->INTFR & TIM_IT; - - itenable = TIMx->DMAINTENR & TIM_IT; - if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearITPendingBit - * - * @brief Clears the TIMx's interrupt pending bits. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - TIMx->INTFR = (uint16_t)~TIM_IT; -} - -/********************************************************************* - * @fn TI1_Config - * - * @brief Configure the TI1 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); - - TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI2_Config - * - * @brief Configure the TI2 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 2 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 2 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 2 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); - - TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI3_Config - * - * @brief Configure the TI3 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 3 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 3 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 3 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); - - TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI4_Config - * - * @brief Configure the TI4 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 4 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 4 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 4 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); - - TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC4NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_tim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/06 + * Description : This file provides all the TIM firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_tim.h" +#include "ch32v10x_rcc.h" + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if(TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if(TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + + TIMx->CTLR1 = tmpcr1; + TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if(TIMx == TIM1) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if(TIMx == TIM1) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +/********************************************************************* + * @fn TIM_GenerateEvent + * + * @brief Configures the TIMx event to be generate by software. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMABase: DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values (Affects also the I2Ss). + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 4 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) +{ + TIMx->CNT = Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) +{ + TIMx->ATRLR = Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) +{ + TIMx->CH1CVR = Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) +{ + TIMx->CH2CVR = Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) +{ + TIMx->CH3CVR = Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) +{ + TIMx->CH4CVR = Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return SET or RESET. + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 2 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 2 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 2 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 3 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 3 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 3 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 4 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 4 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 4 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_usart.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_usart.c index 39e183d..b9a4f89 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_usart.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_usart.c @@ -1,818 +1,747 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_usart.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the USART firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_usart.h" -#include "ch32v10x_rcc.h" - -/* USART_Private_Defines */ -#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ -#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ - -#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ - -#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ -#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ -#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ -#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ - -#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ -#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ - -#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ -#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ -#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ - -#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ -#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ - -#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ -#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ - -#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ -#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ - -#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ -#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ - -#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ -#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ -#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ -#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ -#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ - -/* USART OverSampling-8 Mask */ -#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ -#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ - -/* USART One Bit Sampling Mask */ -#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ -#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ - -/********************************************************************* - * @fn USART_DeInit - * - * @brief Deinitializes the USARTx peripheral registers to their default - * reset values. - * - * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. - * - * @return none - */ -void USART_DeInit(USART_TypeDef *USARTx) -{ - if(USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if(USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if(USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if(USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else - { - if(USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - } -} - -/********************************************************************* - * @fn USART_Init - * - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct. - * - * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. - * USART_InitStruct - pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified - * USART peripheral. - * - * @return none - */ -void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - uint32_t usartxbase = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - - if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - } - - usartxbase = (uint32_t)USARTx; - tmpreg = USARTx->CTLR2; - tmpreg &= CTLR2_STOP_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - USARTx->CTLR2 = (uint16_t)tmpreg; - tmpreg = USARTx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - USARTx->CTLR1 = (uint16_t)tmpreg; - - tmpreg = USARTx->CTLR3; - tmpreg &= CTLR3_CLEAR_Mask; - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - USARTx->CTLR3 = (uint16_t)tmpreg; - - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if(usartxbase == USART1_BASE) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) - { - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else - { - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - USARTx->BRR = (uint16_t)tmpreg; -} - -/********************************************************************* - * @fn USART_StructInit - * - * @brief Fills each USART_InitStruct member with its default value. - * - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void USART_StructInit(USART_InitTypeDef *USART_InitStruct) -{ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/********************************************************************* - * @fn USART_ClockInit - * - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * - * @return none - */ -void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - - tmpreg = USARTx->CTLR2; - tmpreg &= CTLR2_CLOCK_CLEAR_Mask; - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - USARTx->CTLR2 = (uint16_t)tmpreg; -} - -/********************************************************************* - * @fn USART_ClockStructInit - * - * @brief Fills each USART_ClockStructInit member with its default value. - * - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * - * @return none - */ -void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/********************************************************************* - * @fn USART_Cmd - * - * @brief Enables or disables the specified USART peripheral. - * reset values (Affects also the I2Ss). - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_UE_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_UE_Reset; - } -} - -/********************************************************************* - * @fn USART_ITConfig - * - * @brief Enables or disables the specified USART interrupts. - * reset values (Affects also the I2Ss). - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_IT - specifies the USART interrupt sources to be enabled or disabled. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Transmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_PE - Parity Error interrupt. - * USART_IT_ERR - Error interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - - usartxbase = (uint32_t)USARTx; - usartreg = (((uint8_t)USART_IT) >> 0x05); - itpos = USART_IT & IT_Mask; - itmask = (((uint32_t)0x01) << itpos); - - if(usartreg == 0x01) - { - usartxbase += 0x0C; - } - else if(usartreg == 0x02) - { - usartxbase += 0x10; - } - else - { - usartxbase += 0x14; - } - - if(NewState != DISABLE) - { - *(__IO uint32_t *)usartxbase |= itmask; - } - else - { - *(__IO uint32_t *)usartxbase &= ~itmask; - } -} - -/********************************************************************* - * @fn USART_DMACmd - * - * @brief Enables or disables the USART DMA interface. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_DMAReq - specifies the DMA request. - * USART_DMAReq_Tx - USART DMA transmit request. - * USART_DMAReq_Rx - USART DMA receive request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= USART_DMAReq; - } - else - { - USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; - } -} - -/********************************************************************* - * @fn USART_SetAddress - * - * @brief Sets the address of the USART node. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_Address - Indicates the address of the USART node. - * - * @return none - */ -void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) -{ - USARTx->CTLR2 &= CTLR2_Address_Mask; - USARTx->CTLR2 |= USART_Address; -} - -/********************************************************************* - * @fn USART_WakeUpConfig - * - * @brief Selects the USART WakeUp method. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_WakeUp - specifies the USART wakeup method. - * USART_WakeUp_IdleLine - WakeUp by an idle line detection. - * USART_WakeUp_AddressMark - WakeUp by an address mark. - * - * @return none - */ -void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) -{ - USARTx->CTLR1 &= CTLR1_WAKE_Mask; - USARTx->CTLR1 |= USART_WakeUp; -} - -/********************************************************************* - * @fn USART_ReceiverWakeUpCmd - * - * @brief Determines if the USART is in mute mode or not. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_RWU_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_RWU_Reset; - } -} - -/********************************************************************* - * @fn USART_LINBreakDetectLengthConfig - * - * @brief Sets the USART LIN Break detection length. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_LINBreakDetectLength - specifies the LIN break detection length. - * USART_LINBreakDetectLength_10b - 10-bit break detection. - * USART_LINBreakDetectLength_11b - 11-bit break detection. - * - * @return none - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) -{ - USARTx->CTLR2 &= CTLR2_LBDL_Mask; - USARTx->CTLR2 |= USART_LINBreakDetectLength; -} - -/********************************************************************* - * @fn USART_LINCmd - * - * @brief Enables or disables the USART LIN mode. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR2 |= CTLR2_LINEN_Set; - } - else - { - USARTx->CTLR2 &= CTLR2_LINEN_Reset; - } -} - -/********************************************************************* - * @fn USART_SendData - * - * @brief Transmits single data through the USARTx peripheral. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * Data - the data to transmit. - * - * @return none - */ -void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) -{ - USARTx->DATAR = (Data & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_ReceiveData - * - * @brief Returns the most recent received data by the USARTx peripheral. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * - * @return The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef *USARTx) -{ - return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_SendBreak - * - * @brief Transmits break characters. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * - * @return none - */ -void USART_SendBreak(USART_TypeDef *USARTx) -{ - USARTx->CTLR1 |= CTLR1_SBK_Set; -} - -/********************************************************************* - * @fn USART_SetGuardTime - * - * @brief Sets the specified USART guard time. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_GuardTime - specifies the guard time. - * - * @return none - */ -void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) -{ - USARTx->GPR &= GPR_LSB_Mask; - USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/********************************************************************* - * @fn USART_SetPrescaler - * - * @brief Sets the system clock prescaler. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_Prescaler - specifies the prescaler clock. - * - * @return none - */ -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) -{ - USARTx->GPR &= GPR_MSB_Mask; - USARTx->GPR |= USART_Prescaler; -} - -/********************************************************************* - * @fn USART_SmartCardCmd - * - * @brief Enables or disables the USART Smart Card mode. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_SCEN_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_SCEN_Reset; - } -} - -/********************************************************************* - * @fn USART_SmartCardNACKCmd - * - * @brief Enables or disables NACK transmission. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_NACK_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_NACK_Reset; - } -} - -/********************************************************************* - * @fn USART_HalfDuplexCmd - * - * @brief Enables or disables the USART Half Duplex communication. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_HDSEL_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_HDSEL_Reset; - } -} - -/********************************************************************* - * @fn USART_OverSampling8Cmd - * - * @brief Enables or disables the USART's 8x oversampling mode. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * Note- - * This function has to be called before calling USART_Init() - * function in order to have correct baudrate Divider value. - * @return none - */ -void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_OVER8_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_OVER8_Reset; - } -} - -/********************************************************************* - * @fn USART_OneBitMethodCmd - * - * @brief Enables or disables the USART's one bit sampling method. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_ONEBITE_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_ONEBITE_Reset; - } -} - -/********************************************************************* - * @fn USART_IrDAConfig - * - * @brief Configures the USART's IrDA interface. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_IrDAMode - specifies the IrDA mode. - * USART_IrDAMode_LowPower. - * USART_IrDAMode_Normal. - * - * @return none - */ -void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) -{ - USARTx->CTLR3 &= CTLR3_IRLP_Mask; - USARTx->CTLR3 |= USART_IrDAMode; -} - -/********************************************************************* - * @fn USART_IrDACmd - * - * @brief Enables or disables the USART's IrDA interface. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_IREN_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_IREN_Reset; - } -} - -/********************************************************************* - * @fn USART_GetFlagStatus - * - * @brief Checks whether the specified USART flag is set or not. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_FLAG - specifies the flag to check. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TXE - Transmit data register empty flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * USART_FLAG_IDLE - Idle Line detection flag. - * USART_FLAG_ORE - OverRun Error flag. - * USART_FLAG_NE - Noise Error flag. - * USART_FLAG_FE - Framing Error flag. - * USART_FLAG_PE - Parity Error flag. - * - * @return bitstatus: SET or RESET - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearFlag - * - * @brief Clears the USARTx's pending flags. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_FLAG - specifies the flag to clear. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * Note- - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DATAR register (USART_ReceiveData()). - * - RXNE flag can be also cleared by a read to the USART_DATAR register - * (USART_ReceiveData()). - * - TC flag can be also cleared by software sequence: a read operation to - * USART_STATR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DATAR register (USART_SendData()). - * - TXE flag is cleared only by a write to the USART_DATAR register - * (USART_SendData()). - * @return none - */ -void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - - USARTx->STATR = (uint16_t)~USART_FLAG; -} - -/********************************************************************* - * @fn USART_GetITStatus - * - * @brief Checks whether the specified USART interrupt has occurred or not. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_IT - specifies the USART interrupt source to check. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Tansmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. - * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. - * USART_IT_NE - Noise Error interrupt. - * USART_IT_FE - Framing Error interrupt. - * USART_IT_PE - Parity Error interrupt. - * - * @return bitstatus: SET or RESET. - */ -ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - - usartreg = (((uint8_t)USART_IT) >> 0x05); - itmask = USART_IT & IT_Mask; - itmask = (uint32_t)0x01 << itmask; - - if(usartreg == 0x01) - { - itmask &= USARTx->CTLR1; - } - else if(usartreg == 0x02) - { - itmask &= USARTx->CTLR2; - } - else - { - itmask &= USARTx->CTLR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->STATR; - - if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearITPendingBit - * - * @brief Clears the USARTx's interrupt pending bits. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_IT - specifies the interrupt pending bit to clear. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * Note- - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_STATR register - * (USART_GetITStatus()) followed by a read operation to USART_DATAR register - * (USART_ReceiveData()). - * - RXNE pending bit can be also cleared by a read to the USART_DATAR register - * (USART_ReceiveData()). - * - TC pending bit can be also cleared by software sequence: a read - * operation to USART_STATR register (USART_GetITStatus()) followed by a write - * operation to USART_DATAR register (USART_SendData()). - * - TXE pending bit is cleared only by a write to the USART_DATAR register - * (USART_SendData()). - * @return none - */ -void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->STATR = (uint16_t)~itmask; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_usart.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/06 + * Description : This file provides all the USART firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_usart.h" +#include "ch32v10x_rcc.h" + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if(USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if(USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if(USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else + { + if(USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + tmpreg = (integerdivider / 100) << 4; + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return bitstatus: SET or RESET + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DATAR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_STATR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DATAR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return bitstatus: SET or RESET. + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_STATR register + * (USART_GetITStatus()) followed by a read operation to USART_DATAR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_STATR register (USART_GetITStatus()) followed by a write + * operation to USART_DATAR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_usb.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_usb.c index 2fc775e..4558075 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_usb.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_usb.c @@ -1,172 +1,172 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_usb.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the USB firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_usb.h" -#include "ch32v10x_rcc.h" -#include "debug.h" -/******************************** USB DEVICE **********************************/ - -/* Endpoint address */ -PUINT8 pEP0_RAM_Addr; -PUINT8 pEP1_RAM_Addr; -PUINT8 pEP2_RAM_Addr; -PUINT8 pEP3_RAM_Addr; -PUINT8 pEP4_RAM_Addr; -PUINT8 pEP5_RAM_Addr; -PUINT8 pEP6_RAM_Addr; -PUINT8 pEP7_RAM_Addr; - -/********************************************************************* - * @fn USB_DeviceInit - * - * @brief Initializes USB device. - * - * @return none - */ -void USB_DeviceInit(void) -{ - R8_USB_CTRL = 0x00; - - R8_UEP4_1_MOD = RB_UEP4_RX_EN | RB_UEP4_TX_EN | RB_UEP1_RX_EN | RB_UEP1_TX_EN; - R8_UEP2_3_MOD = RB_UEP2_RX_EN | RB_UEP2_TX_EN | RB_UEP3_RX_EN | RB_UEP3_TX_EN; - R8_UEP5_6_MOD = RB_UEP5_RX_EN | RB_UEP5_TX_EN | RB_UEP6_RX_EN | RB_UEP6_TX_EN; - R8_UEP7_MOD = RB_UEP7_RX_EN | RB_UEP7_TX_EN; - - R16_UEP0_DMA = (UINT16)(UINT32)pEP0_RAM_Addr; - R16_UEP1_DMA = (UINT16)(UINT32)pEP1_RAM_Addr; - R16_UEP2_DMA = (UINT16)(UINT32)pEP2_RAM_Addr; - R16_UEP3_DMA = (UINT16)(UINT32)pEP3_RAM_Addr; - R16_UEP4_DMA = (UINT16)(UINT32)pEP4_RAM_Addr; - R16_UEP5_DMA = (UINT16)(UINT32)pEP5_RAM_Addr; - R16_UEP6_DMA = (UINT16)(UINT32)pEP6_RAM_Addr; - R16_UEP7_DMA = (UINT16)(UINT32)pEP7_RAM_Addr; - - R8_UEP0_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; - R8_UEP1_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; - R8_UEP2_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; - R8_UEP3_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; - R8_UEP4_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; - R8_UEP5_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; - R8_UEP6_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; - R8_UEP7_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; - - R8_USB_INT_FG = 0xFF; - R8_USB_INT_EN = RB_UIE_SUSPEND | RB_UIE_BUS_RST | RB_UIE_TRANSFER; - - R8_USB_DEV_AD = 0x00; - R8_USB_CTRL = RB_UC_DEV_PU_EN | RB_UC_INT_BUSY | RB_UC_DMA_EN; - R8_UDEV_CTRL = RB_UD_PD_DIS | RB_UD_PORT_EN; -} - -/********************************************************************* - * @fn DevEP1_IN_Deal - * - * @brief Device endpoint1 IN - * - * @param l: IN length(<64B) - * - * @return none - */ -void DevEP1_IN_Deal(UINT16 l) -{ - R16_UEP1_T_LEN = l; - R8_UEP1_CTRL = (R8_UEP1_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; -} - -/********************************************************************* - * @fn DevEP2_IN_Deal - * - * @brief Device endpoint2 IN - * - * @param l: IN length(<64B) - * - * @return none - */ -void DevEP2_IN_Deal(UINT16 l) -{ - R16_UEP2_T_LEN = l; - R8_UEP2_CTRL = (R8_UEP2_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; -} - -/********************************************************************* - * @fn DevEP3_IN_Deal - * - * @brief Device endpoint3 IN - * - * @param l: IN length(<64B) - * - * @return none - */ -void DevEP3_IN_Deal(UINT16 l) -{ - R16_UEP3_T_LEN = l; - R8_UEP3_CTRL = (R8_UEP3_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; -} - -/********************************************************************* - * @fn DevEP4_IN_Deal - * - * @brief Device endpoint4 IN - * - * @param l: IN length(<64B) - * - * @return none - */ -void DevEP4_IN_Deal(UINT16 l) -{ - R16_UEP4_T_LEN = l; - R8_UEP4_CTRL = (R8_UEP4_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; -} - -/********************************************************************* - * @fn DevEP5_IN_Deal - * - * @brief Device endpoint5 IN - * - * @param l: IN length(<64B) - * - * @return none - */ -void DevEP5_IN_Deal(UINT16 l) -{ - R16_UEP5_T_LEN = l; - R8_UEP5_CTRL = (R8_UEP5_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; -} - -/********************************************************************* - * @fn DevEP6_IN_Deal - * - * @brief Device endpoint6 IN - * - * @param l: IN length(<64B) - * - * @return none - */ -void DevEP6_IN_Deal(UINT16 l) -{ - R16_UEP6_T_LEN = l; - R8_UEP6_CTRL = (R8_UEP6_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; -} - -/********************************************************************* - * @fn DevEP7_IN_Deal - * - * @brief Device endpoint7 IN - * - * @param l: IN length(<64B) - * - * @return none - */ -void DevEP7_IN_Deal(UINT16 l) -{ - R16_UEP7_T_LEN = l; - R8_UEP7_CTRL = (R8_UEP7_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_usb.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the USB firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_usb.h" +#include "ch32v10x_rcc.h" +#include "debug.h" +/******************************** USB DEVICE **********************************/ + +/* Endpoint address */ +PUINT8 pEP0_RAM_Addr; +PUINT8 pEP1_RAM_Addr; +PUINT8 pEP2_RAM_Addr; +PUINT8 pEP3_RAM_Addr; +PUINT8 pEP4_RAM_Addr; +PUINT8 pEP5_RAM_Addr; +PUINT8 pEP6_RAM_Addr; +PUINT8 pEP7_RAM_Addr; + +/********************************************************************* + * @fn USB_DeviceInit + * + * @brief Initializes USB device. + * + * @return none + */ +void USB_DeviceInit(void) +{ + R8_USB_CTRL = 0x00; + + R8_UEP4_1_MOD = RB_UEP4_RX_EN | RB_UEP4_TX_EN | RB_UEP1_RX_EN | RB_UEP1_TX_EN; + R8_UEP2_3_MOD = RB_UEP2_RX_EN | RB_UEP2_TX_EN | RB_UEP3_RX_EN | RB_UEP3_TX_EN; + R8_UEP5_6_MOD = RB_UEP5_RX_EN | RB_UEP5_TX_EN | RB_UEP6_RX_EN | RB_UEP6_TX_EN; + R8_UEP7_MOD = RB_UEP7_RX_EN | RB_UEP7_TX_EN; + + R16_UEP0_DMA = (UINT16)(UINT32)pEP0_RAM_Addr; + R16_UEP1_DMA = (UINT16)(UINT32)pEP1_RAM_Addr; + R16_UEP2_DMA = (UINT16)(UINT32)pEP2_RAM_Addr; + R16_UEP3_DMA = (UINT16)(UINT32)pEP3_RAM_Addr; + R16_UEP4_DMA = (UINT16)(UINT32)pEP4_RAM_Addr; + R16_UEP5_DMA = (UINT16)(UINT32)pEP5_RAM_Addr; + R16_UEP6_DMA = (UINT16)(UINT32)pEP6_RAM_Addr; + R16_UEP7_DMA = (UINT16)(UINT32)pEP7_RAM_Addr; + + R8_UEP0_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; + R8_UEP1_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; + R8_UEP2_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; + R8_UEP3_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; + R8_UEP4_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; + R8_UEP5_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; + R8_UEP6_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; + R8_UEP7_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; + + R8_USB_INT_FG = 0xFF; + R8_USB_INT_EN = RB_UIE_SUSPEND | RB_UIE_BUS_RST | RB_UIE_TRANSFER; + + R8_USB_DEV_AD = 0x00; + R8_USB_CTRL = RB_UC_DEV_PU_EN | RB_UC_INT_BUSY | RB_UC_DMA_EN; + R8_UDEV_CTRL = RB_UD_PD_DIS | RB_UD_PORT_EN; +} + +/********************************************************************* + * @fn DevEP1_IN_Deal + * + * @brief Device endpoint1 IN + * + * @param l: IN length(<64B) + * + * @return none + */ +void DevEP1_IN_Deal(UINT16 l) +{ + R16_UEP1_T_LEN = l; + R8_UEP1_CTRL = (R8_UEP1_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; +} + +/********************************************************************* + * @fn DevEP2_IN_Deal + * + * @brief Device endpoint2 IN + * + * @param l: IN length(<64B) + * + * @return none + */ +void DevEP2_IN_Deal(UINT16 l) +{ + R16_UEP2_T_LEN = l; + R8_UEP2_CTRL = (R8_UEP2_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; +} + +/********************************************************************* + * @fn DevEP3_IN_Deal + * + * @brief Device endpoint3 IN + * + * @param l: IN length(<64B) + * + * @return none + */ +void DevEP3_IN_Deal(UINT16 l) +{ + R16_UEP3_T_LEN = l; + R8_UEP3_CTRL = (R8_UEP3_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; +} + +/********************************************************************* + * @fn DevEP4_IN_Deal + * + * @brief Device endpoint4 IN + * + * @param l: IN length(<64B) + * + * @return none + */ +void DevEP4_IN_Deal(UINT16 l) +{ + R16_UEP4_T_LEN = l; + R8_UEP4_CTRL = (R8_UEP4_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; +} + +/********************************************************************* + * @fn DevEP5_IN_Deal + * + * @brief Device endpoint5 IN + * + * @param l: IN length(<64B) + * + * @return none + */ +void DevEP5_IN_Deal(UINT16 l) +{ + R16_UEP5_T_LEN = l; + R8_UEP5_CTRL = (R8_UEP5_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; +} + +/********************************************************************* + * @fn DevEP6_IN_Deal + * + * @brief Device endpoint6 IN + * + * @param l: IN length(<64B) + * + * @return none + */ +void DevEP6_IN_Deal(UINT16 l) +{ + R16_UEP6_T_LEN = l; + R8_UEP6_CTRL = (R8_UEP6_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; +} + +/********************************************************************* + * @fn DevEP7_IN_Deal + * + * @brief Device endpoint7 IN + * + * @param l: IN length(<64B) + * + * @return none + */ +void DevEP7_IN_Deal(UINT16 l) +{ + R16_UEP7_T_LEN = l; + R8_UEP7_CTRL = (R8_UEP7_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; +} diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_usb_host.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_usb_host.c index 9731214..d2aee40 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_usb_host.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_usb_host.c @@ -1,807 +1,807 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_usb_host.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the USB firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_usb_host.h" -#include "debug.h" - -/******************************** HOST DEVICE **********************************/ -UINT8 UsbDevEndp0Size; -UINT8 FoundNewDev; -_RootHubDev ThisUsbDev; - -PUINT8 pHOST_RX_RAM_Addr; -PUINT8 pHOST_TX_RAM_Addr; -extern UINT8 Com_Buffer[128]; - -__attribute__((aligned(4))) const UINT8 SetupGetDevDescr[] = {USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_DEVICE, 0x00, 0x00, sizeof(USB_DEV_DESCR), 0x00}; - -__attribute__((aligned(4))) const UINT8 SetupGetCfgDescr[] = {USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_CONFIG, 0x00, 0x00, 0x04, 0x00}; - -__attribute__((aligned(4))) const UINT8 SetupSetUsbAddr[] = {USB_REQ_TYP_OUT, USB_SET_ADDRESS, USB_DEVICE_ADDR, 0x00, 0x00, 0x00, 0x00, 0x00}; - -__attribute__((aligned(4))) const UINT8 SetupSetUsbConfig[] = {USB_REQ_TYP_OUT, USB_SET_CONFIGURATION, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - -__attribute__((aligned(4))) const UINT8 SetupSetUsbInterface[] = {USB_REQ_RECIP_INTERF, USB_SET_INTERFACE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - -__attribute__((aligned(4))) const UINT8 SetupClrEndpStall[] = {USB_REQ_TYP_OUT | USB_REQ_RECIP_ENDP, USB_CLEAR_FEATURE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - -/********************************************************************* - * @fn DisableRootHubPort( ) - * - * @brief Disable root hub - * - * @return none - */ -void DisableRootHubPort(void) -{ -#ifdef FOR_ROOT_UDISK_ONLY - CH103DiskStatus = DISK_DISCONNECT; - -#endif - -#ifndef DISK_BASE_BUF_LEN - ThisUsbDev.DeviceStatus = ROOT_DEV_DISCONNECT; - ThisUsbDev.DeviceAddress = 0x00; - -#endif -} - -/********************************************************************* - * @fn AnalyzeRootHub - * - * @brief Analyze root hub state. - * - * @return Error - */ -UINT8 AnalyzeRootHub(void) -{ - UINT8 s; - - s = ERR_SUCCESS; - - if(R8_USB_MIS_ST & RB_UMS_DEV_ATTACH) - { -#ifdef DISK_BASE_BUF_LEN - if(CH103DiskStatus == DISK_DISCONNECT - -#else - if(ThisUsbDev.DeviceStatus == ROOT_DEV_DISCONNECT - -#endif - || (R8_UHOST_CTRL & RB_UH_PORT_EN) == 0x00) - { - DisableRootHubPort(); - -#ifdef DISK_BASE_BUF_LEN - CH103DiskStatus = DISK_CONNECT; - -#else - ThisUsbDev.DeviceSpeed = R8_USB_MIS_ST & RB_UMS_DM_LEVEL ? 0 : 1; - ThisUsbDev.DeviceStatus = ROOT_DEV_CONNECTED; - -#endif - s = ERR_USB_CONNECT; - } - } - -#ifdef DISK_BASE_BUF_LEN - else if(CH103DiskStatus >= DISK_CONNECT) - { -#else - else if(ThisUsbDev.DeviceStatus >= ROOT_DEV_CONNECTED) - { - -#endif - DisableRootHubPort(); - if(s == ERR_SUCCESS) - s = ERR_USB_DISCON; - } - - return (s); -} - -/********************************************************************* - * @fn SetHostUsbAddr - * - * @brief Set USB host address - * - * @param addr - host address - * - * @return none - */ -void SetHostUsbAddr(UINT8 addr) -{ - R8_USB_DEV_AD = (R8_USB_DEV_AD & RB_UDA_GP_BIT) | (addr & MASK_USB_ADDR); -} - -#ifndef FOR_ROOT_UDISK_ONLY -/********************************************************************* - * @fn SetUsbSpeed - * - * @brief Set USB speed. - * - * @param FullSpeed - USB speed. - * - * @return none - */ -void SetUsbSpeed(UINT8 FullSpeed) -{ - if(FullSpeed) - { - R8_USB_CTRL &= ~RB_UC_LOW_SPEED; - R8_UH_SETUP &= ~RB_UH_PRE_PID_EN; - } - else - { - R8_USB_CTRL |= RB_UC_LOW_SPEED; - } -} -#endif - -/********************************************************************* - * @fn ResetRootHubPort( ) - * - * @brief Reset root hub - * - * @return none - */ -void ResetRootHubPort(void) -{ - UsbDevEndp0Size = DEFAULT_ENDP0_SIZE; - SetHostUsbAddr(0x00); - R8_UHOST_CTRL &= ~RB_UH_PORT_EN; - SetUsbSpeed(1); - R8_UHOST_CTRL = (R8_UHOST_CTRL & ~RB_UH_LOW_SPEED) | RB_UH_BUS_RESET; - Delay_Ms(15); - R8_UHOST_CTRL = R8_UHOST_CTRL & ~RB_UH_BUS_RESET; - Delay_Us(250); - R8_USB_INT_FG = RB_UIF_DETECT; -} - -/********************************************************************* - * @fn EnableRootHubPort( ) - * - * @brief Enable root hub. - * - * @return ERROR - */ -UINT8 EnableRootHubPort(void) -{ -#ifdef DISK_BASE_BUF_LEN - if(CH103DiskStatus < DISK_CONNECT) - CH103DiskStatus = DISK_CONNECT; - -#else - if(ThisUsbDev.DeviceStatus < ROOT_DEV_CONNECTED) - ThisUsbDev.DeviceStatus = ROOT_DEV_CONNECTED; - -#endif - if(R8_USB_MIS_ST & RB_UMS_DEV_ATTACH) - { -#ifndef DISK_BASE_BUF_LEN - if((R8_UHOST_CTRL & RB_UH_PORT_EN) == 0x00) - { - ThisUsbDev.DeviceSpeed = (R8_USB_MIS_ST & RB_UMS_DM_LEVEL) ? 0 : 1; - if(ThisUsbDev.DeviceSpeed == 0) - R8_UHOST_CTRL |= RB_UH_LOW_SPEED; - } - -#endif - R8_UHOST_CTRL |= RB_UH_PORT_EN; - return (ERR_SUCCESS); - } - - return (ERR_USB_DISCON); -} - -/********************************************************************* - * @fn WaitUSB_Interrupt - * - * @brief Wait USB Interrput. - * - * @return ERROR - */ -UINT8 WaitUSB_Interrupt(void) -{ - UINT16 i; - - for(i = WAIT_USB_TOUT_200US; i != 0 && (R8_USB_INT_FG & RB_UIF_TRANSFER) == 0; i--) - { - ; - } - return ((R8_USB_INT_FG & RB_UIF_TRANSFER) ? ERR_SUCCESS : ERR_USB_UNKNOWN); -} - -/********************************************************************* - * @fn USBHostTransact - * - * @brief USB host transport transaction - * @param endp_pid: endpoint and PID - * tog: Synchronization flag - * timeout: timeout times - * - * @return EEROR: - * ERR_USB_UNKNOWN - * ERR_USB_DISCON - * ERR_USB_CONNECT - * ERR_SUCCESS - */ -UINT8 USBHostTransact(UINT8 endp_pid, UINT8 tog, UINT32 timeout) -{ - UINT8 TransRetry; - UINT8 s, r; - UINT16 i; - - R8_UH_RX_CTRL = R8_UH_TX_CTRL = tog; - TransRetry = 0; - - do - { - R8_UH_EP_PID = endp_pid; - R8_USB_INT_FG = RB_UIF_TRANSFER; - for(i = WAIT_USB_TOUT_200US; i != 0 && (R8_USB_INT_FG & RB_UIF_TRANSFER) == 0; i--) - ; - R8_UH_EP_PID = 0x00; - if((R8_USB_INT_FG & RB_UIF_TRANSFER) == 0) - { - return (ERR_USB_UNKNOWN); - } - - if(R8_USB_INT_FG & RB_UIF_DETECT) - { - R8_USB_INT_FG = RB_UIF_DETECT; - s = AnalyzeRootHub(); - - if(s == ERR_USB_CONNECT) - FoundNewDev = 1; - -#ifdef DISK_BASE_BUF_LEN - - if(CH103DiskStatus == DISK_DISCONNECT) - return (ERR_USB_DISCON); - if(CH103DiskStatus == DISK_CONNECT) - return (ERR_USB_CONNECT); - -#else - if(ThisUsbDev.DeviceStatus == ROOT_DEV_DISCONNECT) - return (ERR_USB_DISCON); - if(ThisUsbDev.DeviceStatus == ROOT_DEV_CONNECTED) - return (ERR_USB_CONNECT); - -#endif - Delay_Us(200); - } - - if(R8_USB_INT_FG & RB_UIF_TRANSFER) - { - if(R8_USB_INT_ST & RB_UIS_TOG_OK) - return (ERR_SUCCESS); - r = R8_USB_INT_ST & MASK_UIS_H_RES; - if(r == USB_PID_STALL) - return (r | ERR_USB_TRANSFER); - - if(r == USB_PID_NAK) - { - if(timeout == 0) - return (r | ERR_USB_TRANSFER); - if(timeout < 0xFFFF) - timeout--; - --TransRetry; - } - else - switch(endp_pid >> 4) - { - case USB_PID_SETUP: - - case USB_PID_OUT: - if(r) - return (r | ERR_USB_TRANSFER); - break; - - case USB_PID_IN: - if(r == USB_PID_DATA0 && r == USB_PID_DATA1) - { - } - else if(r) - return (r | ERR_USB_TRANSFER); - break; - - default: - return (ERR_USB_UNKNOWN); - } - } - else - { - R8_USB_INT_FG = 0xFF; - } - Delay_Us(15); - } while(++TransRetry < 3); - - return (ERR_USB_TRANSFER); -} - -/********************************************************************* - * @fn HostCtrlTransfer - * - * @brief Host control transport. - * - * @param DataBuf : Receive or send data buffer. - * RetLen : Data length. - * - * @return ERR_USB_BUF_OVER IN - * ERR_SUCCESS - */ -UINT8 HostCtrlTransfer(PUINT8 DataBuf, PUINT8 RetLen) -{ - UINT16 RemLen = 0; - UINT8 s, RxLen, RxCnt, TxCnt; - PUINT8 pBuf; - PUINT8 pLen; - - pBuf = DataBuf; - pLen = RetLen; - Delay_Us(200); - if(pLen) - *pLen = 0; - - R8_UH_TX_LEN = sizeof(USB_SETUP_REQ); - s = USBHostTransact(USB_PID_SETUP << 4 | 0x00, 0x00, 200000 / 20); - if(s != ERR_SUCCESS) - return (s); - R8_UH_RX_CTRL = R8_UH_TX_CTRL = RB_UH_R_TOG | RB_UH_R_AUTO_TOG | RB_UH_T_TOG | RB_UH_T_AUTO_TOG; - R8_UH_TX_LEN = 0x01; - RemLen = pSetupReq->wLength; - - if(RemLen && pBuf) - { - if(pSetupReq->bRequestType & USB_REQ_TYP_IN) - { - while(RemLen) - { - Delay_Us(200); - s = USBHostTransact(USB_PID_IN << 4 | 0x00, R8_UH_RX_CTRL, 200000 / 20); - if(s != ERR_SUCCESS) - return (s); - RxLen = R16_USB_RX_LEN < RemLen ? R16_USB_RX_LEN : RemLen; - RemLen -= RxLen; - if(pLen) - *pLen += RxLen; - - for(RxCnt = 0; RxCnt != RxLen; RxCnt++) { - *pBuf = pHOST_RX_RAM_Addr[RxCnt]; - pBuf++; - } - - if(R16_USB_RX_LEN == 0 || (R16_USB_RX_LEN & (UsbDevEndp0Size - 1))) - break; - } - R8_UH_TX_LEN = 0x00; - } - else - { - while(RemLen) - { - Delay_Us(200); - R8_UH_TX_LEN = RemLen >= UsbDevEndp0Size ? UsbDevEndp0Size : RemLen; - - for(TxCnt = 0; TxCnt != R8_UH_TX_LEN; TxCnt++){ - pHOST_TX_RAM_Addr[TxCnt] = *pBuf; - pBuf++; - } - - s = USBHostTransact(USB_PID_OUT << 4 | 0x00, R8_UH_TX_CTRL, 200000 / 20); - if(s != ERR_SUCCESS) - return (s); - RemLen -= R8_UH_TX_LEN; - if(pLen) - *pLen += R8_UH_TX_LEN; - } - } - } - - Delay_Us(200); - s = USBHostTransact((R8_UH_TX_LEN ? USB_PID_IN << 4 | 0x00 : USB_PID_OUT << 4 | 0x00), RB_UH_R_TOG | RB_UH_T_TOG, 200000 / 20); - if(s != ERR_SUCCESS) - return (s); - if(R8_UH_TX_LEN == 0) - return (ERR_SUCCESS); - if(R16_USB_RX_LEN == 0) - return (ERR_SUCCESS); - - return (ERR_USB_BUF_OVER); -} - -/********************************************************************* - * @fn CopySetupReqPkg - * - * @brief Copy setup request package. - * - * @param pReqPkt: setup request package address. - * - * @return none - */ -void CopySetupReqPkg(const UINT8 *pReqPkt) -{ - UINT8 i; - - for(i = 0; i != sizeof(USB_SETUP_REQ); i++) { - ((PUINT8)pSetupReq)[i] = *pReqPkt; - pReqPkt++; - } -} - -/********************************************************************* - * @fn CtrlGetDeviceDescr - * - * @brief Get device descrptor. - * - * @param DataBuf: Data buffer. - * - * @return ERR_USB_BUF_OVER - * ERR_SUCCESS - */ -UINT8 CtrlGetDeviceDescr(PUINT8 DataBuf) -{ - UINT8 s; - UINT8 len; - - UsbDevEndp0Size = DEFAULT_ENDP0_SIZE; - CopySetupReqPkg(SetupGetDevDescr); - s = HostCtrlTransfer(DataBuf, &len); - - if(s != ERR_SUCCESS) - return (s); - UsbDevEndp0Size = ((PUSB_DEV_DESCR)DataBuf)->bMaxPacketSize0; - if(len < ((PUSB_SETUP_REQ)SetupGetDevDescr)->wLength) - return (ERR_USB_BUF_OVER); - - return (ERR_SUCCESS); -} - -/********************************************************************* - * @fn CtrlGetConfigDescr - * - * @brief Get configration descrptor. - * - * @param DataBuf: Data buffer. - * - * @return ERR_USB_BUF_OVER - * ERR_SUCCESS - */ -UINT8 CtrlGetConfigDescr(PUINT8 DataBuf) -{ - UINT8 s; - UINT8 len; - - CopySetupReqPkg(SetupGetCfgDescr); - s = HostCtrlTransfer(DataBuf, &len); - if(s != ERR_SUCCESS) - return (s); - if(len < ((PUSB_SETUP_REQ)SetupGetCfgDescr)->wLength) - return (ERR_USB_BUF_OVER); - - len = ((PUSB_CFG_DESCR)DataBuf)->wTotalLength; - CopySetupReqPkg(SetupGetCfgDescr); - pSetupReq->wLength = len; - s = HostCtrlTransfer(DataBuf, &len); - if(s != ERR_SUCCESS) - return (s); - - return (ERR_SUCCESS); -} - -/********************************************************************* - * @fn CtrlSetUsbAddress - * - * @brief Set USB device address. - * - * @param addr: Device address. - * - * @return ERR_SUCCESS - */ -UINT8 CtrlSetUsbAddress(UINT8 addr) -{ - UINT8 s; - - CopySetupReqPkg(SetupSetUsbAddr); - pSetupReq->wValue = addr; - s = HostCtrlTransfer(NULL, NULL); - if(s != ERR_SUCCESS) - return (s); - SetHostUsbAddr(addr); - Delay_Ms(10); - - return (ERR_SUCCESS); -} - -/********************************************************************* - * @fn CtrlSetUsbConfig - * - * @brief Set usb configration. - * - * @param cfg: Configration Value. - * - * @return ERR_SUCCESS - */ -UINT8 CtrlSetUsbConfig(UINT8 cfg) -{ - CopySetupReqPkg(SetupSetUsbConfig); - pSetupReq->wValue = cfg; - return (HostCtrlTransfer(NULL, NULL)); -} - -/********************************************************************* - * @fn CtrlClearEndpStall - * - * @brief Clear endpoint STALL. - * - * @param endp: Endpoint address. - * - * @return ERR_SUCCESS - */ -UINT8 CtrlClearEndpStall(UINT8 endp) -{ - CopySetupReqPkg(SetupClrEndpStall); - pSetupReq->wIndex = endp; - return (HostCtrlTransfer(NULL, NULL)); -} - -/********************************************************************* - * @fn CtrlSetUsbIntercace - * - * @brief Set USB Interface configration. - * - * @param cfg: Configration value. - * - * @return ERR_SUCCESS - */ -UINT8 CtrlSetUsbIntercace(UINT8 cfg) -{ - CopySetupReqPkg(SetupSetUsbInterface); - pSetupReq->wValue = cfg; - return (HostCtrlTransfer(NULL, NULL)); -} - -/********************************************************************* - * @fn USB_HostInit - * - * @brief Initializes USB host mode. - * - * @return ERR_SUCCESS - */ -void USB_HostInit(void) -{ - R8_USB_CTRL = RB_UC_HOST_MODE; - R8_UHOST_CTRL = 0; - R8_USB_DEV_AD = 0x00; - R8_UH_EP_MOD = RB_UH_EP_TX_EN | RB_UH_EP_RX_EN; - R16_UH_RX_DMA = (UINT16)(UINT32)pHOST_RX_RAM_Addr; - R16_UH_TX_DMA = (UINT16)(UINT32)pHOST_TX_RAM_Addr; - - R8_UH_RX_CTRL = 0x00; - R8_UH_TX_CTRL = 0x00; - R8_USB_CTRL = RB_UC_HOST_MODE | RB_UC_INT_BUSY | RB_UC_DMA_EN; - R8_UH_SETUP = RB_UH_SOF_EN; - R8_USB_INT_FG = 0xFF; - DisableRootHubPort(); - R8_USB_INT_EN = RB_UIE_TRANSFER | RB_UIE_DETECT; - - FoundNewDev = 0; -} - -/********************************************************************* - * @fn InitRootDevice - * - * @brief Initializes USB root hub. - * - * @param DataBuf: Data buffer. - * - * @return ERROR - */ -UINT8 InitRootDevice(PUINT8 DataBuf) -{ - UINT8 i, s; - UINT8 cfg, dv_cls, if_cls; - - ResetRootHubPort(); - - for(i = 0, s = 0; i < 100; i++) - { - Delay_Ms(1); - if(EnableRootHubPort() == ERR_SUCCESS) - { - i = 0; - s++; - if(s > 100) - break; - } - } - - if(i) - { - DisableRootHubPort(); - return (ERR_USB_DISCON); - } - - SetUsbSpeed(ThisUsbDev.DeviceSpeed); - - s = CtrlGetDeviceDescr(DataBuf); - - if(s == ERR_SUCCESS) - { - ThisUsbDev.DeviceVID = ((PUSB_DEV_DESCR)DataBuf)->idVendor; - ThisUsbDev.DevicePID = ((PUSB_DEV_DESCR)DataBuf)->idProduct; - dv_cls = ((PUSB_DEV_DESCR)DataBuf)->bDeviceClass; - - s = CtrlSetUsbAddress(((PUSB_SETUP_REQ)SetupSetUsbAddr)->wValue); - - if(s == ERR_SUCCESS) - { - ThisUsbDev.DeviceAddress = ((PUSB_SETUP_REQ)SetupSetUsbAddr)->wValue; - - s = CtrlGetConfigDescr(DataBuf); - - if(s == ERR_SUCCESS) - { - cfg = ((PUSB_CFG_DESCR)DataBuf)->bConfigurationValue; - if_cls = ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceClass; - - if((dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_STORAGE)) - { -#ifdef FOR_ROOT_UDISK_ONLY - CH103DiskStatus = DISK_USB_ADDR; - return (ERR_SUCCESS); - } - else - return (ERR_USB_UNSUPPORT); - -#else - s = CtrlSetUsbConfig(cfg); - - if(s == ERR_SUCCESS) - { - ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS; - ThisUsbDev.DeviceType = USB_DEV_CLASS_STORAGE; - SetUsbSpeed(1); - return (ERR_SUCCESS); - } - } - else if((dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_PRINTER) && ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceSubClass == 0x01) - { - s = CtrlSetUsbConfig(cfg); - if(s == ERR_SUCCESS) - { - ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS; - ThisUsbDev.DeviceType = USB_DEV_CLASS_PRINTER; - SetUsbSpeed(1); - return (ERR_SUCCESS); - } - } - else if((dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_HID) && ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceSubClass <= 0x01) - { - if_cls = ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceProtocol; - s = CtrlSetUsbConfig(cfg); - if(s == ERR_SUCCESS) - { - ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS; - if(if_cls == 1) - { - ThisUsbDev.DeviceType = DEV_TYPE_KEYBOARD; - SetUsbSpeed(1); - return (ERR_SUCCESS); - } - else if(if_cls == 2) - { - ThisUsbDev.DeviceType = DEV_TYPE_MOUSE; - SetUsbSpeed(1); - return (ERR_SUCCESS); - } - s = ERR_USB_UNSUPPORT; - } - } - else - { - s = CtrlSetUsbConfig(cfg); - if(s == ERR_SUCCESS) - { - ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS; - ThisUsbDev.DeviceType = DEV_TYPE_UNKNOW; - SetUsbSpeed(1); - return (ERR_SUCCESS); - } - } -#endif - } - } - } - -#ifdef FOR_ROOT_UDISK_ONLY - CH103DiskStatus = DISK_CONNECT; - -#else - ThisUsbDev.DeviceStatus = ROOT_DEV_FAILED; - -#endif - - SetUsbSpeed(1); - - return (s); -} - -/********************************************************************* - * @fn HubGetPortStatus - * - * - * @param UINT8 HubPortIndex - * - * @return ERR_SUCCESS - * ERR_USB_BUF_OVER - */ -UINT8 HubGetPortStatus(UINT8 HubPortIndex) -{ - UINT8 s; - UINT8 len; - - pSetupReq->bRequestType = HUB_GET_PORT_STATUS; - pSetupReq->bRequest = HUB_GET_STATUS; - pSetupReq->wValue = 0x0000; - pSetupReq->wIndex = 0x0000 | HubPortIndex; - pSetupReq->wLength = 0x0004; - s = HostCtrlTransfer(Com_Buffer, &len); - if(s != ERR_SUCCESS) - { - return (s); - } - if(len < 4) - { - return (ERR_USB_BUF_OVER); - } - - return (ERR_SUCCESS); -} - -/********************************************************************* - * @fn HubSetPortFeature - * - * - * @param UINT8 HubPortIndex - * UINT8 FeatureSelt - * - * @return ERR_SUCCESS - */ -UINT8 HubSetPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt) -{ - pSetupReq->bRequestType = HUB_SET_PORT_FEATURE; - pSetupReq->bRequest = HUB_SET_FEATURE; - pSetupReq->wValue = 0x0000 | FeatureSelt; - pSetupReq->wIndex = 0x0000 | HubPortIndex; - pSetupReq->wLength = 0x0000; - return (HostCtrlTransfer(NULL, NULL)); -} - -/********************************************************************* - * @fn HubClearPortFeature - * - * - * @param UINT8 HubPortIndex - * UINT8 FeatureSelt - * - * @return ERR_SUCCESS - */ -UINT8 HubClearPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt) -{ - pSetupReq->bRequestType = HUB_CLEAR_PORT_FEATURE; - pSetupReq->bRequest = HUB_CLEAR_FEATURE; - pSetupReq->wValue = 0x0000 | FeatureSelt; - pSetupReq->wIndex = 0x0000 | HubPortIndex; - pSetupReq->wLength = 0x0000; - return (HostCtrlTransfer(NULL, NULL)); -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_usb_host.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the USB firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_usb_host.h" +#include "debug.h" + +/******************************** HOST DEVICE **********************************/ +UINT8 UsbDevEndp0Size; +UINT8 FoundNewDev; +_RootHubDev ThisUsbDev; + +PUINT8 pHOST_RX_RAM_Addr; +PUINT8 pHOST_TX_RAM_Addr; +extern UINT8 Com_Buffer[128]; + +__attribute__((aligned(4))) const UINT8 SetupGetDevDescr[] = {USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_DEVICE, 0x00, 0x00, sizeof(USB_DEV_DESCR), 0x00}; + +__attribute__((aligned(4))) const UINT8 SetupGetCfgDescr[] = {USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_CONFIG, 0x00, 0x00, 0x04, 0x00}; + +__attribute__((aligned(4))) const UINT8 SetupSetUsbAddr[] = {USB_REQ_TYP_OUT, USB_SET_ADDRESS, USB_DEVICE_ADDR, 0x00, 0x00, 0x00, 0x00, 0x00}; + +__attribute__((aligned(4))) const UINT8 SetupSetUsbConfig[] = {USB_REQ_TYP_OUT, USB_SET_CONFIGURATION, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + +__attribute__((aligned(4))) const UINT8 SetupSetUsbInterface[] = {USB_REQ_RECIP_INTERF, USB_SET_INTERFACE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + +__attribute__((aligned(4))) const UINT8 SetupClrEndpStall[] = {USB_REQ_TYP_OUT | USB_REQ_RECIP_ENDP, USB_CLEAR_FEATURE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + +/********************************************************************* + * @fn DisableRootHubPort( ) + * + * @brief Disable root hub + * + * @return none + */ +void DisableRootHubPort(void) +{ +#ifdef FOR_ROOT_UDISK_ONLY + CH103DiskStatus = DISK_DISCONNECT; + +#endif + +#ifndef DISK_BASE_BUF_LEN + ThisUsbDev.DeviceStatus = ROOT_DEV_DISCONNECT; + ThisUsbDev.DeviceAddress = 0x00; + +#endif +} + +/********************************************************************* + * @fn AnalyzeRootHub + * + * @brief Analyze root hub state. + * + * @return Error + */ +UINT8 AnalyzeRootHub(void) +{ + UINT8 s; + + s = ERR_SUCCESS; + + if(R8_USB_MIS_ST & RB_UMS_DEV_ATTACH) + { +#ifdef DISK_BASE_BUF_LEN + if(CH103DiskStatus == DISK_DISCONNECT + +#else + if(ThisUsbDev.DeviceStatus == ROOT_DEV_DISCONNECT + +#endif + || (R8_UHOST_CTRL & RB_UH_PORT_EN) == 0x00) + { + DisableRootHubPort(); + +#ifdef DISK_BASE_BUF_LEN + CH103DiskStatus = DISK_CONNECT; + +#else + ThisUsbDev.DeviceSpeed = R8_USB_MIS_ST & RB_UMS_DM_LEVEL ? 0 : 1; + ThisUsbDev.DeviceStatus = ROOT_DEV_CONNECTED; + +#endif + s = ERR_USB_CONNECT; + } + } + +#ifdef DISK_BASE_BUF_LEN + else if(CH103DiskStatus >= DISK_CONNECT) + { +#else + else if(ThisUsbDev.DeviceStatus >= ROOT_DEV_CONNECTED) + { + +#endif + DisableRootHubPort(); + if(s == ERR_SUCCESS) + s = ERR_USB_DISCON; + } + + return (s); +} + +/********************************************************************* + * @fn SetHostUsbAddr + * + * @brief Set USB host address + * + * @param addr - host address + * + * @return none + */ +void SetHostUsbAddr(UINT8 addr) +{ + R8_USB_DEV_AD = (R8_USB_DEV_AD & RB_UDA_GP_BIT) | (addr & MASK_USB_ADDR); +} + +#ifndef FOR_ROOT_UDISK_ONLY +/********************************************************************* + * @fn SetUsbSpeed + * + * @brief Set USB speed. + * + * @param FullSpeed - USB speed. + * + * @return none + */ +void SetUsbSpeed(UINT8 FullSpeed) +{ + if(FullSpeed) + { + R8_USB_CTRL &= ~RB_UC_LOW_SPEED; + R8_UH_SETUP &= ~RB_UH_PRE_PID_EN; + } + else + { + R8_USB_CTRL |= RB_UC_LOW_SPEED; + } +} +#endif + +/********************************************************************* + * @fn ResetRootHubPort( ) + * + * @brief Reset root hub + * + * @return none + */ +void ResetRootHubPort(void) +{ + UsbDevEndp0Size = DEFAULT_ENDP0_SIZE; + SetHostUsbAddr(0x00); + R8_UHOST_CTRL &= ~RB_UH_PORT_EN; + SetUsbSpeed(1); + R8_UHOST_CTRL = (R8_UHOST_CTRL & ~RB_UH_LOW_SPEED) | RB_UH_BUS_RESET; + Delay_Ms(15); + R8_UHOST_CTRL = R8_UHOST_CTRL & ~RB_UH_BUS_RESET; + Delay_Us(250); + R8_USB_INT_FG = RB_UIF_DETECT; +} + +/********************************************************************* + * @fn EnableRootHubPort( ) + * + * @brief Enable root hub. + * + * @return ERROR + */ +UINT8 EnableRootHubPort(void) +{ +#ifdef DISK_BASE_BUF_LEN + if(CH103DiskStatus < DISK_CONNECT) + CH103DiskStatus = DISK_CONNECT; + +#else + if(ThisUsbDev.DeviceStatus < ROOT_DEV_CONNECTED) + ThisUsbDev.DeviceStatus = ROOT_DEV_CONNECTED; + +#endif + if(R8_USB_MIS_ST & RB_UMS_DEV_ATTACH) + { +#ifndef DISK_BASE_BUF_LEN + if((R8_UHOST_CTRL & RB_UH_PORT_EN) == 0x00) + { + ThisUsbDev.DeviceSpeed = (R8_USB_MIS_ST & RB_UMS_DM_LEVEL) ? 0 : 1; + if(ThisUsbDev.DeviceSpeed == 0) + R8_UHOST_CTRL |= RB_UH_LOW_SPEED; + } + +#endif + R8_UHOST_CTRL |= RB_UH_PORT_EN; + return (ERR_SUCCESS); + } + + return (ERR_USB_DISCON); +} + +/********************************************************************* + * @fn WaitUSB_Interrupt + * + * @brief Wait USB Interrput. + * + * @return ERROR + */ +UINT8 WaitUSB_Interrupt(void) +{ + UINT16 i; + + for(i = WAIT_USB_TOUT_200US; i != 0 && (R8_USB_INT_FG & RB_UIF_TRANSFER) == 0; i--) + { + ; + } + return ((R8_USB_INT_FG & RB_UIF_TRANSFER) ? ERR_SUCCESS : ERR_USB_UNKNOWN); +} + +/********************************************************************* + * @fn USBHostTransact + * + * @brief USB host transport transaction + * @param endp_pid: endpoint and PID + * tog: Synchronization flag + * timeout: timeout times + * + * @return EEROR: + * ERR_USB_UNKNOWN + * ERR_USB_DISCON + * ERR_USB_CONNECT + * ERR_SUCCESS + */ +UINT8 USBHostTransact(UINT8 endp_pid, UINT8 tog, UINT32 timeout) +{ + UINT8 TransRetry; + UINT8 s, r; + UINT16 i; + + R8_UH_RX_CTRL = R8_UH_TX_CTRL = tog; + TransRetry = 0; + + do + { + R8_UH_EP_PID = endp_pid; + R8_USB_INT_FG = RB_UIF_TRANSFER; + for(i = WAIT_USB_TOUT_200US; i != 0 && (R8_USB_INT_FG & RB_UIF_TRANSFER) == 0; i--) + ; + R8_UH_EP_PID = 0x00; + if((R8_USB_INT_FG & RB_UIF_TRANSFER) == 0) + { + return (ERR_USB_UNKNOWN); + } + + if(R8_USB_INT_FG & RB_UIF_DETECT) + { + R8_USB_INT_FG = RB_UIF_DETECT; + s = AnalyzeRootHub(); + + if(s == ERR_USB_CONNECT) + FoundNewDev = 1; + +#ifdef DISK_BASE_BUF_LEN + + if(CH103DiskStatus == DISK_DISCONNECT) + return (ERR_USB_DISCON); + if(CH103DiskStatus == DISK_CONNECT) + return (ERR_USB_CONNECT); + +#else + if(ThisUsbDev.DeviceStatus == ROOT_DEV_DISCONNECT) + return (ERR_USB_DISCON); + if(ThisUsbDev.DeviceStatus == ROOT_DEV_CONNECTED) + return (ERR_USB_CONNECT); + +#endif + Delay_Us(200); + } + + if(R8_USB_INT_FG & RB_UIF_TRANSFER) + { + if(R8_USB_INT_ST & RB_UIS_TOG_OK) + return (ERR_SUCCESS); + r = R8_USB_INT_ST & MASK_UIS_H_RES; + if(r == USB_PID_STALL) + return (r | ERR_USB_TRANSFER); + + if(r == USB_PID_NAK) + { + if(timeout == 0) + return (r | ERR_USB_TRANSFER); + if(timeout < 0xFFFF) + timeout--; + --TransRetry; + } + else + switch(endp_pid >> 4) + { + case USB_PID_SETUP: + + case USB_PID_OUT: + if(r) + return (r | ERR_USB_TRANSFER); + break; + + case USB_PID_IN: + if(r == USB_PID_DATA0 && r == USB_PID_DATA1) + { + } + else if(r) + return (r | ERR_USB_TRANSFER); + break; + + default: + return (ERR_USB_UNKNOWN); + } + } + else + { + R8_USB_INT_FG = 0xFF; + } + Delay_Us(15); + } while(++TransRetry < 3); + + return (ERR_USB_TRANSFER); +} + +/********************************************************************* + * @fn HostCtrlTransfer + * + * @brief Host control transport. + * + * @param DataBuf : Receive or send data buffer. + * RetLen : Data length. + * + * @return ERR_USB_BUF_OVER IN + * ERR_SUCCESS + */ +UINT8 HostCtrlTransfer(PUINT8 DataBuf, PUINT8 RetLen) +{ + UINT16 RemLen = 0; + UINT8 s, RxLen, RxCnt, TxCnt; + PUINT8 pBuf; + PUINT8 pLen; + + pBuf = DataBuf; + pLen = RetLen; + Delay_Us(200); + if(pLen) + *pLen = 0; + + R8_UH_TX_LEN = sizeof(USB_SETUP_REQ); + s = USBHostTransact(USB_PID_SETUP << 4 | 0x00, 0x00, 200000 / 20); + if(s != ERR_SUCCESS) + return (s); + R8_UH_RX_CTRL = R8_UH_TX_CTRL = RB_UH_R_TOG | RB_UH_R_AUTO_TOG | RB_UH_T_TOG | RB_UH_T_AUTO_TOG; + R8_UH_TX_LEN = 0x01; + RemLen = pSetupReq->wLength; + + if(RemLen && pBuf) + { + if(pSetupReq->bRequestType & USB_REQ_TYP_IN) + { + while(RemLen) + { + Delay_Us(200); + s = USBHostTransact(USB_PID_IN << 4 | 0x00, R8_UH_RX_CTRL, 200000 / 20); + if(s != ERR_SUCCESS) + return (s); + RxLen = R16_USB_RX_LEN < RemLen ? R16_USB_RX_LEN : RemLen; + RemLen -= RxLen; + if(pLen) + *pLen += RxLen; + + for(RxCnt = 0; RxCnt != RxLen; RxCnt++) { + *pBuf = pHOST_RX_RAM_Addr[RxCnt]; + pBuf++; + } + + if(R16_USB_RX_LEN == 0 || (R16_USB_RX_LEN & (UsbDevEndp0Size - 1))) + break; + } + R8_UH_TX_LEN = 0x00; + } + else + { + while(RemLen) + { + Delay_Us(200); + R8_UH_TX_LEN = RemLen >= UsbDevEndp0Size ? UsbDevEndp0Size : RemLen; + + for(TxCnt = 0; TxCnt != R8_UH_TX_LEN; TxCnt++){ + pHOST_TX_RAM_Addr[TxCnt] = *pBuf; + pBuf++; + } + + s = USBHostTransact(USB_PID_OUT << 4 | 0x00, R8_UH_TX_CTRL, 200000 / 20); + if(s != ERR_SUCCESS) + return (s); + RemLen -= R8_UH_TX_LEN; + if(pLen) + *pLen += R8_UH_TX_LEN; + } + } + } + + Delay_Us(200); + s = USBHostTransact((R8_UH_TX_LEN ? USB_PID_IN << 4 | 0x00 : USB_PID_OUT << 4 | 0x00), RB_UH_R_TOG | RB_UH_T_TOG, 200000 / 20); + if(s != ERR_SUCCESS) + return (s); + if(R8_UH_TX_LEN == 0) + return (ERR_SUCCESS); + if(R16_USB_RX_LEN == 0) + return (ERR_SUCCESS); + + return (ERR_USB_BUF_OVER); +} + +/********************************************************************* + * @fn CopySetupReqPkg + * + * @brief Copy setup request package. + * + * @param pReqPkt: setup request package address. + * + * @return none + */ +void CopySetupReqPkg(const UINT8 *pReqPkt) +{ + UINT8 i; + + for(i = 0; i != sizeof(USB_SETUP_REQ); i++) { + ((PUINT8)pSetupReq)[i] = *pReqPkt; + pReqPkt++; + } +} + +/********************************************************************* + * @fn CtrlGetDeviceDescr + * + * @brief Get device descrptor. + * + * @param DataBuf: Data buffer. + * + * @return ERR_USB_BUF_OVER + * ERR_SUCCESS + */ +UINT8 CtrlGetDeviceDescr(PUINT8 DataBuf) +{ + UINT8 s; + UINT8 len; + + UsbDevEndp0Size = DEFAULT_ENDP0_SIZE; + CopySetupReqPkg(SetupGetDevDescr); + s = HostCtrlTransfer(DataBuf, &len); + + if(s != ERR_SUCCESS) + return (s); + UsbDevEndp0Size = ((PUSB_DEV_DESCR)DataBuf)->bMaxPacketSize0; + if(len < ((PUSB_SETUP_REQ)SetupGetDevDescr)->wLength) + return (ERR_USB_BUF_OVER); + + return (ERR_SUCCESS); +} + +/********************************************************************* + * @fn CtrlGetConfigDescr + * + * @brief Get configration descrptor. + * + * @param DataBuf: Data buffer. + * + * @return ERR_USB_BUF_OVER + * ERR_SUCCESS + */ +UINT8 CtrlGetConfigDescr(PUINT8 DataBuf) +{ + UINT8 s; + UINT8 len; + + CopySetupReqPkg(SetupGetCfgDescr); + s = HostCtrlTransfer(DataBuf, &len); + if(s != ERR_SUCCESS) + return (s); + if(len < ((PUSB_SETUP_REQ)SetupGetCfgDescr)->wLength) + return (ERR_USB_BUF_OVER); + + len = ((PUSB_CFG_DESCR)DataBuf)->wTotalLength; + CopySetupReqPkg(SetupGetCfgDescr); + pSetupReq->wLength = len; + s = HostCtrlTransfer(DataBuf, &len); + if(s != ERR_SUCCESS) + return (s); + + return (ERR_SUCCESS); +} + +/********************************************************************* + * @fn CtrlSetUsbAddress + * + * @brief Set USB device address. + * + * @param addr: Device address. + * + * @return ERR_SUCCESS + */ +UINT8 CtrlSetUsbAddress(UINT8 addr) +{ + UINT8 s; + + CopySetupReqPkg(SetupSetUsbAddr); + pSetupReq->wValue = addr; + s = HostCtrlTransfer(NULL, NULL); + if(s != ERR_SUCCESS) + return (s); + SetHostUsbAddr(addr); + Delay_Ms(10); + + return (ERR_SUCCESS); +} + +/********************************************************************* + * @fn CtrlSetUsbConfig + * + * @brief Set usb configration. + * + * @param cfg: Configration Value. + * + * @return ERR_SUCCESS + */ +UINT8 CtrlSetUsbConfig(UINT8 cfg) +{ + CopySetupReqPkg(SetupSetUsbConfig); + pSetupReq->wValue = cfg; + return (HostCtrlTransfer(NULL, NULL)); +} + +/********************************************************************* + * @fn CtrlClearEndpStall + * + * @brief Clear endpoint STALL. + * + * @param endp: Endpoint address. + * + * @return ERR_SUCCESS + */ +UINT8 CtrlClearEndpStall(UINT8 endp) +{ + CopySetupReqPkg(SetupClrEndpStall); + pSetupReq->wIndex = endp; + return (HostCtrlTransfer(NULL, NULL)); +} + +/********************************************************************* + * @fn CtrlSetUsbIntercace + * + * @brief Set USB Interface configration. + * + * @param cfg: Configration value. + * + * @return ERR_SUCCESS + */ +UINT8 CtrlSetUsbIntercace(UINT8 cfg) +{ + CopySetupReqPkg(SetupSetUsbInterface); + pSetupReq->wValue = cfg; + return (HostCtrlTransfer(NULL, NULL)); +} + +/********************************************************************* + * @fn USB_HostInit + * + * @brief Initializes USB host mode. + * + * @return ERR_SUCCESS + */ +void USB_HostInit(void) +{ + R8_USB_CTRL = RB_UC_HOST_MODE; + R8_UHOST_CTRL = 0; + R8_USB_DEV_AD = 0x00; + R8_UH_EP_MOD = RB_UH_EP_TX_EN | RB_UH_EP_RX_EN; + R16_UH_RX_DMA = (UINT16)(UINT32)pHOST_RX_RAM_Addr; + R16_UH_TX_DMA = (UINT16)(UINT32)pHOST_TX_RAM_Addr; + + R8_UH_RX_CTRL = 0x00; + R8_UH_TX_CTRL = 0x00; + R8_USB_CTRL = RB_UC_HOST_MODE | RB_UC_INT_BUSY | RB_UC_DMA_EN; + R8_UH_SETUP = RB_UH_SOF_EN; + R8_USB_INT_FG = 0xFF; + DisableRootHubPort(); + R8_USB_INT_EN = RB_UIE_TRANSFER | RB_UIE_DETECT; + + FoundNewDev = 0; +} + +/********************************************************************* + * @fn InitRootDevice + * + * @brief Initializes USB root hub. + * + * @param DataBuf: Data buffer. + * + * @return ERROR + */ +UINT8 InitRootDevice(PUINT8 DataBuf) +{ + UINT8 i, s; + UINT8 cfg, dv_cls, if_cls; + + ResetRootHubPort(); + + for(i = 0, s = 0; i < 100; i++) + { + Delay_Ms(1); + if(EnableRootHubPort() == ERR_SUCCESS) + { + i = 0; + s++; + if(s > 100) + break; + } + } + + if(i) + { + DisableRootHubPort(); + return (ERR_USB_DISCON); + } + + SetUsbSpeed(ThisUsbDev.DeviceSpeed); + + s = CtrlGetDeviceDescr(DataBuf); + + if(s == ERR_SUCCESS) + { + ThisUsbDev.DeviceVID = ((PUSB_DEV_DESCR)DataBuf)->idVendor; + ThisUsbDev.DevicePID = ((PUSB_DEV_DESCR)DataBuf)->idProduct; + dv_cls = ((PUSB_DEV_DESCR)DataBuf)->bDeviceClass; + + s = CtrlSetUsbAddress(((PUSB_SETUP_REQ)SetupSetUsbAddr)->wValue); + + if(s == ERR_SUCCESS) + { + ThisUsbDev.DeviceAddress = ((PUSB_SETUP_REQ)SetupSetUsbAddr)->wValue; + + s = CtrlGetConfigDescr(DataBuf); + + if(s == ERR_SUCCESS) + { + cfg = ((PUSB_CFG_DESCR)DataBuf)->bConfigurationValue; + if_cls = ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceClass; + + if((dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_STORAGE)) + { +#ifdef FOR_ROOT_UDISK_ONLY + CH103DiskStatus = DISK_USB_ADDR; + return (ERR_SUCCESS); + } + else + return (ERR_USB_UNSUPPORT); + +#else + s = CtrlSetUsbConfig(cfg); + + if(s == ERR_SUCCESS) + { + ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS; + ThisUsbDev.DeviceType = USB_DEV_CLASS_STORAGE; + SetUsbSpeed(1); + return (ERR_SUCCESS); + } + } + else if((dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_PRINTER) && ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceSubClass == 0x01) + { + s = CtrlSetUsbConfig(cfg); + if(s == ERR_SUCCESS) + { + ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS; + ThisUsbDev.DeviceType = USB_DEV_CLASS_PRINTER; + SetUsbSpeed(1); + return (ERR_SUCCESS); + } + } + else if((dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_HID) && ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceSubClass <= 0x01) + { + if_cls = ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceProtocol; + s = CtrlSetUsbConfig(cfg); + if(s == ERR_SUCCESS) + { + ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS; + if(if_cls == 1) + { + ThisUsbDev.DeviceType = DEV_TYPE_KEYBOARD; + SetUsbSpeed(1); + return (ERR_SUCCESS); + } + else if(if_cls == 2) + { + ThisUsbDev.DeviceType = DEV_TYPE_MOUSE; + SetUsbSpeed(1); + return (ERR_SUCCESS); + } + s = ERR_USB_UNSUPPORT; + } + } + else + { + s = CtrlSetUsbConfig(cfg); + if(s == ERR_SUCCESS) + { + ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS; + ThisUsbDev.DeviceType = DEV_TYPE_UNKNOW; + SetUsbSpeed(1); + return (ERR_SUCCESS); + } + } +#endif + } + } + } + +#ifdef FOR_ROOT_UDISK_ONLY + CH103DiskStatus = DISK_CONNECT; + +#else + ThisUsbDev.DeviceStatus = ROOT_DEV_FAILED; + +#endif + + SetUsbSpeed(1); + + return (s); +} + +/********************************************************************* + * @fn HubGetPortStatus + * + * + * @param UINT8 HubPortIndex + * + * @return ERR_SUCCESS + * ERR_USB_BUF_OVER + */ +UINT8 HubGetPortStatus(UINT8 HubPortIndex) +{ + UINT8 s; + UINT8 len; + + pSetupReq->bRequestType = HUB_GET_PORT_STATUS; + pSetupReq->bRequest = HUB_GET_STATUS; + pSetupReq->wValue = 0x0000; + pSetupReq->wIndex = 0x0000 | HubPortIndex; + pSetupReq->wLength = 0x0004; + s = HostCtrlTransfer(Com_Buffer, &len); + if(s != ERR_SUCCESS) + { + return (s); + } + if(len < 4) + { + return (ERR_USB_BUF_OVER); + } + + return (ERR_SUCCESS); +} + +/********************************************************************* + * @fn HubSetPortFeature + * + * + * @param UINT8 HubPortIndex + * UINT8 FeatureSelt + * + * @return ERR_SUCCESS + */ +UINT8 HubSetPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt) +{ + pSetupReq->bRequestType = HUB_SET_PORT_FEATURE; + pSetupReq->bRequest = HUB_SET_FEATURE; + pSetupReq->wValue = 0x0000 | FeatureSelt; + pSetupReq->wIndex = 0x0000 | HubPortIndex; + pSetupReq->wLength = 0x0000; + return (HostCtrlTransfer(NULL, NULL)); +} + +/********************************************************************* + * @fn HubClearPortFeature + * + * + * @param UINT8 HubPortIndex + * UINT8 FeatureSelt + * + * @return ERR_SUCCESS + */ +UINT8 HubClearPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt) +{ + pSetupReq->bRequestType = HUB_CLEAR_PORT_FEATURE; + pSetupReq->bRequest = HUB_CLEAR_FEATURE; + pSetupReq->wValue = 0x0000 | FeatureSelt; + pSetupReq->wIndex = 0x0000 | HubPortIndex; + pSetupReq->wLength = 0x0000; + return (HostCtrlTransfer(NULL, NULL)); +} diff --git a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_wwdg.c b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_wwdg.c index ab0738e..2c1f2bb 100644 --- a/system/CH32V10x/SRC/Peripheral/src/ch32v10x_wwdg.c +++ b/system/CH32V10x/SRC/Peripheral/src/ch32v10x_wwdg.c @@ -1,141 +1,141 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_wwdg.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : This file provides all the WWDG firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_wwdg.h" -#include "ch32v10x_rcc.h" - -/* CTLR register bit mask */ -#define CTLR_WDGA_Set ((uint32_t)0x00000080) - -/* CFGR register bit mask */ -#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) -#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) -#define BIT_Mask ((uint8_t)0x7F) - -/********************************************************************* - * @fn WWDG_DeInit - * - * @brief Deinitializes the WWDG peripheral registers to their default reset values - * - * @return none - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/********************************************************************* - * @fn WWDG_SetPrescaler - * - * @brief Sets the WWDG Prescaler - * - * @param WWDG_Prescaler - specifies the WWDG Prescaler - * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 - * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 - * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 - * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 - * - * @return none - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; - tmpreg |= WWDG_Prescaler; - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_SetWindowValue - * - * @brief Sets the WWDG window value - * - * @param WindowValue - specifies the window value to be compared to the - * downcounter,which must be lower than 0x80 - * - * @return none - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - tmpreg = WWDG->CFGR & CFGR_W_Mask; - - tmpreg |= WindowValue & (uint32_t)BIT_Mask; - - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_EnableIT - * - * @brief Enables the WWDG Early Wakeup interrupt(EWI) - * - * @return none - */ -void WWDG_EnableIT(void) -{ - WWDG->CFGR |= (1 << 9); -} - -/********************************************************************* - * @fn WWDG_SetCounter - * - * @brief Sets the WWDG counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * - * @return none - */ -void WWDG_SetCounter(uint8_t Counter) -{ - WWDG->CTLR = Counter & BIT_Mask; -} - -/********************************************************************* - * @fn WWDG_Enable - * - * @brief Enables WWDG and load the counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * @return none - */ -void WWDG_Enable(uint8_t Counter) -{ - WWDG->CTLR = CTLR_WDGA_Set | Counter; -} - -/********************************************************************* - * @fn WWDG_GetFlagStatus - * - * @brief Checks whether the Early Wakeup interrupt flag is set or not - * - * @return The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - return (FlagStatus)(WWDG->STATR); -} - -/********************************************************************* - * @fn WWDG_ClearFlag - * - * @brief Clears Early Wakeup interrupt flag - * - * @return none - */ -void WWDG_ClearFlag(void) -{ - WWDG->STATR = (uint32_t)RESET; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_wwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the WWDG firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_wwdg.h" +#include "ch32v10x_rcc.h" + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/system/CH32V10x/SRC/Startup/startup_ch32v10x_3v3.S b/system/CH32V10x/SRC/Startup/startup_ch32v10x_3v3.S index 175b5a3..1c5bf54 100644 --- a/system/CH32V10x/SRC/Startup/startup_ch32v10x_3v3.S +++ b/system/CH32V10x/SRC/Startup/startup_ch32v10x_3v3.S @@ -1,8 +1,8 @@ ;/********************************** (C) COPYRIGHT ******************************* ;* File Name : startup_ch32v10x.s ;* Author : WCH -;* Version : V1.0.0 -;* Date : 2020/04/30 +;* Version : V1.0.1 +;* Date : 2024/01/11 ;* Description : CH32V10x vector table for eclipse toolchain. ;* Applied to VDD = 3.3V ;********************************************************************************* @@ -29,6 +29,7 @@ _start: .word 0x00000013 .word 0x00000013 .word 0x00100073 + .section .vector,"ax",@progbits .align 1 _vector_base: @@ -93,10 +94,9 @@ _vector_base: j EXTI15_10_IRQHandler /* EXTI Line 15..10 */ j RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ j USBWakeUp_IRQHandler /* USB Wakeup from suspend */ - j USBHD_IRQHandler /* USBHD */ + j USBFS_IRQHandler /* USBFS */ .option rvc; - .section .text.vector_handler, "ax", @progbits .weak NMI_Handler .weak HardFault_Handler @@ -141,52 +141,54 @@ _vector_base: .weak EXTI15_10_IRQHandler .weak RTCAlarm_IRQHandler .weak USBWakeUp_IRQHandler - .weak USBHD_IRQHandler + .weak USBFS_IRQHandler -NMI_Handler: 1: j 1b -HardFault_Handler: 1: j 1b -SysTick_Handler: 1: j 1b -SW_Handler: 1: j 1b -WWDG_IRQHandler: 1: j 1b -PVD_IRQHandler: 1: j 1b -TAMPER_IRQHandler: 1: j 1b -RTC_IRQHandler: 1: j 1b -FLASH_IRQHandler: 1: j 1b -RCC_IRQHandler: 1: j 1b -EXTI0_IRQHandler: 1: j 1b -EXTI1_IRQHandler: 1: j 1b -EXTI2_IRQHandler: 1: j 1b -EXTI3_IRQHandler: 1: j 1b -EXTI4_IRQHandler: 1: j 1b -DMA1_Channel1_IRQHandler: 1: j 1b -DMA1_Channel2_IRQHandler: 1: j 1b -DMA1_Channel3_IRQHandler: 1: j 1b -DMA1_Channel4_IRQHandler: 1: j 1b -DMA1_Channel5_IRQHandler: 1: j 1b -DMA1_Channel6_IRQHandler: 1: j 1b -DMA1_Channel7_IRQHandler: 1: j 1b -ADC1_2_IRQHandler: 1: j 1b -EXTI9_5_IRQHandler: 1: j 1b -TIM1_BRK_IRQHandler: 1: j 1b -TIM1_UP_IRQHandler: 1: j 1b -TIM1_TRG_COM_IRQHandler: 1: j 1b -TIM1_CC_IRQHandler: 1: j 1b -TIM2_IRQHandler: 1: j 1b -TIM3_IRQHandler: 1: j 1b -TIM4_IRQHandler: 1: j 1b -I2C1_EV_IRQHandler: 1: j 1b -I2C1_ER_IRQHandler: 1: j 1b -I2C2_EV_IRQHandler: 1: j 1b -I2C2_ER_IRQHandler: 1: j 1b -SPI1_IRQHandler: 1: j 1b -SPI2_IRQHandler: 1: j 1b -USART1_IRQHandler: 1: j 1b -USART2_IRQHandler: 1: j 1b -USART3_IRQHandler: 1: j 1b -EXTI15_10_IRQHandler: 1: j 1b -RTCAlarm_IRQHandler: 1: j 1b -USBWakeUp_IRQHandler: 1: j 1b -USBHD_IRQHandler: 1: j 1b +NMI_Handler: +HardFault_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +TAMPER_IRQHandler: +RTC_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI0_IRQHandler: +EXTI1_IRQHandler: +EXTI2_IRQHandler: +EXTI3_IRQHandler: +EXTI4_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_2_IRQHandler: +EXTI9_5_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +TIM3_IRQHandler: +TIM4_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +I2C2_EV_IRQHandler: +I2C2_ER_IRQHandler: +SPI1_IRQHandler: +SPI2_IRQHandler: +USART1_IRQHandler: +USART2_IRQHandler: +USART3_IRQHandler: +EXTI15_10_IRQHandler: +RTCAlarm_IRQHandler: +USBWakeUp_IRQHandler: +USBFS_IRQHandler: +1: + j 1b .section .text.handle_reset,"ax",@progbits .weak handle_reset @@ -199,7 +201,7 @@ handle_reset: 1: la sp, _eusrstack 2: - /* Load data section from flash to RAM */ +/* Load data section from flash to RAM */ la a0, _data_lma la a1, _data_vma la a2, _edata @@ -211,7 +213,7 @@ handle_reset: addi a1, a1, 4 bltu a1, a2, 1b 2: - /* clear bss section */ +/* Clear bss section */ la a0, _sbss la a1, _ebss bgeu a0, a1, 2f @@ -220,18 +222,15 @@ handle_reset: addi a0, a0, 4 bltu a0, a1, 1b 2: - /* enable all interrupt */ - li t0, 0x88 - csrs mstatus, t0 +/* Enable global interrupt and configure privileged mode */ + li t0, 0x88 + csrw mstatus, t0 +/* Configure entry address mode */ la t0, _vector_base - ori t0, t0, 1 + ori t0, t0, 1 csrw mtvec, t0 - la a0, __libc_fini_array - call atexit - call __libc_init_array - - jal SystemInit + jal SystemInit la t0, main csrw mepc, t0 mret diff --git a/system/CH32V10x/SRC/Startup/startup_ch32v10x_5v.S b/system/CH32V10x/SRC/Startup/startup_ch32v10x_5v.S index 7bcb7e7..04b848d 100644 --- a/system/CH32V10x/SRC/Startup/startup_ch32v10x_5v.S +++ b/system/CH32V10x/SRC/Startup/startup_ch32v10x_5v.S @@ -1,8 +1,8 @@ ;/********************************** (C) COPYRIGHT ******************************* ;* File Name : startup_ch32v10x.s ;* Author : WCH -;* Version : V1.0.0 -;* Date : 2020/04/30 +;* Version : V1.0.1 +;* Date : 2024/01/11 ;* Description : CH32V10x vector table for eclipse toolchain. ;* Applied to VDD = 5V ;********************************************************************************* @@ -29,6 +29,7 @@ _start: .word 0x00000013 .word 0x00000013 .word 0x00100073 + .section .vector,"ax",@progbits .align 1 _vector_base: @@ -93,10 +94,9 @@ _vector_base: j EXTI15_10_IRQHandler /* EXTI Line 15..10 */ j RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ j USBWakeUp_IRQHandler /* USB Wakeup from suspend */ - j USBHD_IRQHandler /* USBHD */ + j USBFS_IRQHandler /* USBFS */ .option rvc; - .section .text.vector_handler, "ax", @progbits .weak NMI_Handler .weak HardFault_Handler @@ -141,52 +141,54 @@ _vector_base: .weak EXTI15_10_IRQHandler .weak RTCAlarm_IRQHandler .weak USBWakeUp_IRQHandler - .weak USBHD_IRQHandler + .weak USBFS_IRQHandler -NMI_Handler: 1: j 1b -HardFault_Handler: 1: j 1b -SysTick_Handler: 1: j 1b -SW_Handler: 1: j 1b -WWDG_IRQHandler: 1: j 1b -PVD_IRQHandler: 1: j 1b -TAMPER_IRQHandler: 1: j 1b -RTC_IRQHandler: 1: j 1b -FLASH_IRQHandler: 1: j 1b -RCC_IRQHandler: 1: j 1b -EXTI0_IRQHandler: 1: j 1b -EXTI1_IRQHandler: 1: j 1b -EXTI2_IRQHandler: 1: j 1b -EXTI3_IRQHandler: 1: j 1b -EXTI4_IRQHandler: 1: j 1b -DMA1_Channel1_IRQHandler: 1: j 1b -DMA1_Channel2_IRQHandler: 1: j 1b -DMA1_Channel3_IRQHandler: 1: j 1b -DMA1_Channel4_IRQHandler: 1: j 1b -DMA1_Channel5_IRQHandler: 1: j 1b -DMA1_Channel6_IRQHandler: 1: j 1b -DMA1_Channel7_IRQHandler: 1: j 1b -ADC1_2_IRQHandler: 1: j 1b -EXTI9_5_IRQHandler: 1: j 1b -TIM1_BRK_IRQHandler: 1: j 1b -TIM1_UP_IRQHandler: 1: j 1b -TIM1_TRG_COM_IRQHandler: 1: j 1b -TIM1_CC_IRQHandler: 1: j 1b -TIM2_IRQHandler: 1: j 1b -TIM3_IRQHandler: 1: j 1b -TIM4_IRQHandler: 1: j 1b -I2C1_EV_IRQHandler: 1: j 1b -I2C1_ER_IRQHandler: 1: j 1b -I2C2_EV_IRQHandler: 1: j 1b -I2C2_ER_IRQHandler: 1: j 1b -SPI1_IRQHandler: 1: j 1b -SPI2_IRQHandler: 1: j 1b -USART1_IRQHandler: 1: j 1b -USART2_IRQHandler: 1: j 1b -USART3_IRQHandler: 1: j 1b -EXTI15_10_IRQHandler: 1: j 1b -RTCAlarm_IRQHandler: 1: j 1b -USBWakeUp_IRQHandler: 1: j 1b -USBHD_IRQHandler: 1: j 1b +NMI_Handler: +HardFault_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +TAMPER_IRQHandler: +RTC_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI0_IRQHandler: +EXTI1_IRQHandler: +EXTI2_IRQHandler: +EXTI3_IRQHandler: +EXTI4_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_2_IRQHandler: +EXTI9_5_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +TIM3_IRQHandler: +TIM4_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +I2C2_EV_IRQHandler: +I2C2_ER_IRQHandler: +SPI1_IRQHandler: +SPI2_IRQHandler: +USART1_IRQHandler: +USART2_IRQHandler: +USART3_IRQHandler: +EXTI15_10_IRQHandler: +RTCAlarm_IRQHandler: +USBWakeUp_IRQHandler: +USBFS_IRQHandler: +1: + j 1b .section .text.handle_reset,"ax",@progbits .weak handle_reset @@ -199,7 +201,7 @@ handle_reset: 1: la sp, _eusrstack 2: - /* Load data section from flash to RAM */ +/* Load data section from flash to RAM */ la a0, _data_lma la a1, _data_vma la a2, _edata @@ -211,7 +213,7 @@ handle_reset: addi a1, a1, 4 bltu a1, a2, 1b 2: - /* clear bss section */ +/* Clear bss section */ la a0, _sbss la a1, _ebss bgeu a0, a1, 2f @@ -220,18 +222,15 @@ handle_reset: addi a0, a0, 4 bltu a0, a1, 1b 2: - /* enable all interrupt */ - li t0, 0x88 - csrs mstatus, t0 +/* Enable global interrupt and configure privileged mode */ + li t0, 0x88 + csrw mstatus, t0 +/* Configure entry address mode */ la t0, _vector_base - ori t0, t0, 1 + ori t0, t0, 1 csrw mtvec, t0 - - la a0, __libc_fini_array - call atexit - call __libc_init_array - jal SystemInit + jal SystemInit la t0, main csrw mepc, t0 mret diff --git a/system/CH32V10x/USER/ch32v10x_conf.h b/system/CH32V10x/USER/ch32v10x_conf.h index 0ce9c92..5bb9fd6 100644 --- a/system/CH32V10x/USER/ch32v10x_conf.h +++ b/system/CH32V10x/USER/ch32v10x_conf.h @@ -1,43 +1,37 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_conf.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : Library configuration file. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V10x_CONF_H -#define __CH32V10x_CONF_H - -#include "ch32v10x_it.h" -#include "ch32v10x_adc.h" -#include "ch32v10x_bkp.h" -#include "ch32v10x_crc.h" -#include "ch32v10x_dbgmcu.h" -#include "ch32v10x_dma.h" -#include "ch32v10x_exti.h" -#include "ch32v10x_flash.h" -#include "ch32v10x_gpio.h" -#include "ch32v10x_i2c.h" -#include "ch32v10x_iwdg.h" -#include "ch32v10x_pwr.h" -#include "ch32v10x_rcc.h" -#include "ch32v10x_rtc.h" -#include "ch32v10x_spi.h" -#include "ch32v10x_tim.h" -#include "ch32v10x_usart.h" -#include "ch32v10x_wwdg.h" -#include "ch32v10x_usb.h" -#include "ch32v10x_usb_host.h" -#include "ch32v10x_misc.h" - - -#endif /* __CH32V10x_CONF_H */ - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : Library configuration file. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_CONF_H +#define __CH32V10x_CONF_H + +#include "ch32v10x_adc.h" +#include "ch32v10x_bkp.h" +#include "ch32v10x_crc.h" +#include "ch32v10x_dbgmcu.h" +#include "ch32v10x_dma.h" +#include "ch32v10x_exti.h" +#include "ch32v10x_flash.h" +#include "ch32v10x_gpio.h" +#include "ch32v10x_i2c.h" +#include "ch32v10x_iwdg.h" +#include "ch32v10x_pwr.h" +#include "ch32v10x_rcc.h" +#include "ch32v10x_rtc.h" +#include "ch32v10x_spi.h" +#include "ch32v10x_tim.h" +#include "ch32v10x_usart.h" +#include "ch32v10x_wwdg.h" +#include "ch32v10x_usb.h" +#include "ch32v10x_usb_host.h" +#include "ch32v10x_it.h" +#include "ch32v10x_misc.h" + +#endif /* __CH32V10x_CONF_H */ diff --git a/system/CH32V10x/USER/ch32v10x_it.c b/system/CH32V10x/USER/ch32v10x_it.c index 5cef22b..699c420 100644 --- a/system/CH32V10x/USER/ch32v10x_it.c +++ b/system/CH32V10x/USER/ch32v10x_it.c @@ -1,42 +1,43 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v10x_it.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : Main Interrupt Service Routines. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x_it.h" - -void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); - -/********************************************************************* - * @fn NMI_Handler - * - * @brief This function handles NMI exception. - * - * @return none - */ -void NMI_Handler(void) -{ -} - -/********************************************************************* - * @fn HardFault_Handler - * - * @brief This function handles Hard Fault exception. - * - * @return none - */ -void HardFault_Handler(void) -{ - while (1) - { - } -} - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_it.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/05 + * Description : Main Interrupt Service Routines. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_it.h" + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ + while(1) + { + } +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + while(1) + { + } +} diff --git a/system/CH32V10x/USER/ch32v10x_it.h b/system/CH32V10x/USER/ch32v10x_it.h index 9843fe2..d0cd306 100644 --- a/system/CH32V10x/USER/ch32v10x_it.h +++ b/system/CH32V10x/USER/ch32v10x_it.h @@ -14,7 +14,4 @@ #include "debug.h" - #endif /* __CH32V10x_IT_H */ - - diff --git a/system/CH32V10x/USER/system_ch32v10x.c b/system/CH32V10x/USER/system_ch32v10x.c index 4629c5c..fa595b2 100644 --- a/system/CH32V10x/USER/system_ch32v10x.c +++ b/system/CH32V10x/USER/system_ch32v10x.c @@ -1,593 +1,600 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : system_ch32v10x.c - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : CH32V10x Device Peripheral Access Layer System Source File. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v10x.h" - -/* - * Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after - * reset the HSI is used as SYSCLK source). - * If none of the define below is enabled, the HSI is used as System clock source. - */ -//#define SYSCLK_FREQ_HSE HSE_VALUE -//#define SYSCLK_FREQ_48MHz_HSE 48000000 -//#define SYSCLK_FREQ_56MHz_HSE 56000000 -// #define SYSCLK_FREQ_72MHz_HSE 72000000 -//#define SYSCLK_FREQ_HSI HSI_VALUE -//#define SYSCLK_FREQ_48MHz_HSI 48000000 -//#define SYSCLK_FREQ_56MHz_HSI 56000000 -//#define SYSCLK_FREQ_72MHz_HSI 72000000 - -/* Clock Definitions */ -#ifdef SYSCLK_FREQ_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ -#else -uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ - -#endif - -__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/* ch32v10x_system_private_function_proto_types */ -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE -static void SetSysClockToHSE( void ); -#elif defined SYSCLK_FREQ_48MHz_HSE -static void SetSysClockTo48_HSE( void ); -#elif defined SYSCLK_FREQ_56MHz_HSE -static void SetSysClockTo56_HSE( void ); -#elif defined SYSCLK_FREQ_72MHz_HSE -static void SetSysClockTo72_HSE( void ); -#elif defined SYSCLK_FREQ_48MHz_HSI -static void SetSysClockTo48_HSI( void ); -#elif defined SYSCLK_FREQ_56MHz_HSI -static void SetSysClockTo56_HSI( void ); -#elif defined SYSCLK_FREQ_72MHz_HSI -static void SetSysClockTo72_HSI( void ); - -#endif - -/********************************************************************* - * @fn SystemInit - * - * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, - * the PLL and update the SystemCoreClock variable. - * - * @return none - */ -void SystemInit(void) -{ - RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; - RCC->CTLR &= (uint32_t)0xFEF6FFFF; - RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; - RCC->INTR = 0x009F0000; - SetSysClock(); -} - -/********************************************************************* - * @fn SystemCoreClockUpdate - * - * @brief Update SystemCoreClock variable according to Clock Register Values. - * - * @return none - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0; - - tmp = RCC->CFGR0 & RCC_SWS; - - switch(tmp) - { - case 0x00: - SystemCoreClock = HSI_VALUE; - break; - case 0x04: - SystemCoreClock = HSE_VALUE; - break; - case 0x08: - pllmull = RCC->CFGR0 & RCC_PLLMULL; - pllsource = RCC->CFGR0 & RCC_PLLSRC; - pllmull = (pllmull >> 18) + 2; - if(pllsource == 0x00) - { - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - { - if((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) - { - SystemCoreClock = (HSE_VALUE >> 1) * pllmull; - } - else - { - SystemCoreClock = HSE_VALUE * pllmull; - } - } - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - - tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; - SystemCoreClock >>= tmp; -} - -/********************************************************************* - * @fn SetSysClock - * - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClock(void) -{ - //GPIO_IPD_Unused(); -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_48MHz_HSE - SetSysClockTo48_HSE(); -#elif defined SYSCLK_FREQ_56MHz_HSE - SetSysClockTo56_HSE(); -#elif defined SYSCLK_FREQ_72MHz_HSE - SetSysClockTo72_HSE(); -#elif defined SYSCLK_FREQ_48MHz_HSI - SetSysClockTo48_HSI(); -#elif defined SYSCLK_FREQ_56MHz_HSI - SetSysClockTo56_HSI(); -#elif defined SYSCLK_FREQ_72MHz_HSI - SetSysClockTo72_HSI(); - -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - * source (default after reset) - */ -} - -#ifdef SYSCLK_FREQ_HSE - -/********************************************************************* - * @fn SetSysClockToHSE - * - * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if(HSEStatus == (uint32_t)0x01) - { - FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; - - /* Wait till HSE is used as system clock source */ - while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) - { - } - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - - -#elif defined SYSCLK_FREQ_48MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo48_HSE - * - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo48_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if(HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL6); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_56MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo56_HSE - * - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo56_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if(HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; - - /* Flash 2 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL7); - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_72MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo72_HSE - * - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo72_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if(HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; - - /* Flash 2 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | - RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL9); - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_48MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo48_HSI - * - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo48_HSI(void) -{ - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; - - /* Enable Prefetch Buffer */ - FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - -#elif defined SYSCLK_FREQ_56MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo56_HSI - * - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo56_HSI(void) -{ - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; - - /* Enable Prefetch Buffer */ - FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - -#elif defined SYSCLK_FREQ_72MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo72_HSI - * - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo72_HSI(void) -{ - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; - - /* Enable Prefetch Buffer */ - FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v10x.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/23 + * Description : CH32V10x Device Peripheral Access Layer System Source File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x.h" + +/* + * Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after + * reset the HSI is used as SYSCLK source). + * If none of the define below is enabled, the HSI is used as System clock source. + */ +//#define SYSCLK_FREQ_HSE HSE_VALUE +//#define SYSCLK_FREQ_48MHz_HSE 48000000 +//#define SYSCLK_FREQ_56MHz_HSE 56000000 +// #define SYSCLK_FREQ_72MHz_HSE 72000000 +//#define SYSCLK_FREQ_HSI HSI_VALUE +//#define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_56MHz_HSI 56000000 +//#define SYSCLK_FREQ_72MHz_HSI 72000000 + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ +#else +uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ + +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/* ch32v10x_system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE +static void SetSysClockToHSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSE +static void SetSysClockTo48_HSE( void ); +#elif defined SYSCLK_FREQ_56MHz_HSE +static void SetSysClockTo56_HSE( void ); +#elif defined SYSCLK_FREQ_72MHz_HSE +static void SetSysClockTo72_HSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSI +static void SetSysClockTo48_HSI( void ); +#elif defined SYSCLK_FREQ_56MHz_HSI +static void SetSysClockTo56_HSI( void ); +#elif defined SYSCLK_FREQ_72MHz_HSI +static void SetSysClockTo72_HSI( void ); + +#endif + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->INTR = 0x009F0000; + SetSysClock(); +} + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch(tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = (pllmull >> 18) + 2; + if(pllsource == 0x00) + { + if( EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE ) + { + SystemCoreClock = ( HSI_VALUE ) * pllmull; + } + else + { + SystemCoreClock = ( HSI_VALUE >> 1 ) * pllmull; + } + } + else + { + if((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + } + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ + //GPIO_IPD_Unused(); +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo48_HSE(); +#elif defined SYSCLK_FREQ_56MHz_HSE + SetSysClockTo56_HSE(); +#elif defined SYSCLK_FREQ_72MHz_HSE + SetSysClockTo72_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); +#elif defined SYSCLK_FREQ_56MHz_HSI + SetSysClockTo56_HSI(); +#elif defined SYSCLK_FREQ_72MHz_HSI + SetSysClockTo72_HSI(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if(HSEStatus == (uint32_t)0x01) + { + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo48_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if(HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo56_HSE + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if(HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL7); + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo72_HSE + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if(HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL9); + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* Enable Prefetch Buffer */ + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo56_HSI + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* Enable Prefetch Buffer */ + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo72_HSI + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* Enable Prefetch Buffer */ + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#endif diff --git a/system/CH32V10x/USER/system_ch32v10x.h b/system/CH32V10x/USER/system_ch32v10x.h index a7e0f59..03652f0 100644 --- a/system/CH32V10x/USER/system_ch32v10x.h +++ b/system/CH32V10x/USER/system_ch32v10x.h @@ -1,32 +1,29 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : system_ch32v10x.h - * Author : WCH - * Version : V1.0.0 - * Date : 2020/04/30 - * Description : CH32V10x Device Peripheral Access Layer System Header File. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __SYSTEM_CH32V10x_H -#define __SYSTEM_CH32V10x_H - -#ifdef __cplusplus - extern "C" { -#endif - -extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ - -/* System_Exported_Functions */ -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V10x_SYSTEM_H */ - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v10x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : CH32V10x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_CH32V10x_H +#define __SYSTEM_CH32V10x_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V10x_SYSTEM_H */ diff --git a/system/CH32V20x/SRC/Core/core_riscv.c b/system/CH32V20x/SRC/Core/core_riscv.c index 4bb9cf3..9d70fa0 100644 --- a/system/CH32V20x/SRC/Core/core_riscv.c +++ b/system/CH32V20x/SRC/Core/core_riscv.c @@ -1,333 +1,306 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : core_riscv.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : RISC-V Core Peripheral Access Layer Source File - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - - -/********************************************************************* - * @fn __get_MSTATUS - * - * @brief Return the Machine Status Register - * - * @return mstatus value - */ -uint32_t __get_MSTATUS(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MSTATUS - * - * @brief Set the Machine Status Register - * - * @param value - set mstatus value - * - * @return none - */ -void __set_MSTATUS(uint32_t value) -{ - __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MISA - * - * @brief Return the Machine ISA Register - * - * @return misa value - */ -uint32_t __get_MISA(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MISA - * - * @brief Set the Machine ISA Register - * - * @param value - set misa value - * - * @return none - */ -void __set_MISA(uint32_t value) -{ - __ASM volatile ("csrw misa, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MIE - * - * @brief Return the Machine Interrupt Enable Register - * - * @return mie value - */ -uint32_t __get_MIE(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mie" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MISA - * - * @brief Set the Machine ISA Register - * - * @param value - set mie value - * - * @return none - */ -void __set_MIE(uint32_t value) -{ - __ASM volatile ("csrw mie, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MTVEC - * - * @brief Return the Machine Trap-Vector Base-Address Register - * - * @return mtvec value - */ -uint32_t __get_MTVEC(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MTVEC - * - * @brief Set the Machine Trap-Vector Base-Address Register - * - * @param value - set mtvec value - * - * @return none - */ -void __set_MTVEC(uint32_t value) -{ - __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MSCRATCH - * - * @brief Return the Machine Seratch Register - * - * @return mscratch value - */ -uint32_t __get_MSCRATCH(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MSCRATCH - * - * @brief Set the Machine Seratch Register - * - * @param value - set mscratch value - * - * @return none - */ -void __set_MSCRATCH(uint32_t value) -{ - __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MEPC - * - * @brief Return the Machine Exception Program Register - * - * @return mepc value - */ -uint32_t __get_MEPC(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Exception Program Register - * - * @return mepc value - */ -void __set_MEPC(uint32_t value) -{ - __ASM volatile ("csrw mepc, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MCAUSE - * - * @brief Return the Machine Cause Register - * - * @return mcause value - */ -uint32_t __get_MCAUSE(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Cause Register - * - * @return mcause value - */ -void __set_MCAUSE(uint32_t value) -{ - __ASM volatile ("csrw mcause, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MTVAL - * - * @brief Return the Machine Trap Value Register - * - * @return mtval value - */ -uint32_t __get_MTVAL(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MTVAL - * - * @brief Set the Machine Trap Value Register - * - * @return mtval value - */ -void __set_MTVAL(uint32_t value) -{ - __ASM volatile ("csrw mtval, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MVENDORID - * - * @brief Return Vendor ID Register - * - * @return mvendorid value - */ -uint32_t __get_MVENDORID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_MARCHID - * - * @brief Return Machine Architecture ID Register - * - * @return marchid value - */ -uint32_t __get_MARCHID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_MIMPID - * - * @brief Return Machine Implementation ID Register - * - * @return mimpid value - */ -uint32_t __get_MIMPID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_MHARTID - * - * @brief Return Hart ID Register - * - * @return mhartid value - */ -uint32_t __get_MHARTID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_SP - * - * @brief Return SP Register - * - * @return SP value - */ -uint32_t __get_SP(void) -{ - uint32_t result; - - __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); - return (result); -} - +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.c + * Author : WCH + * Version : V1.0.1 + * Date : 2023/11/11 + * Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32V20x +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /* asm keyword for ARM Compiler */ + #define __INLINE __inline /* inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /* asm keyword for IAR Compiler */ + #define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /* asm keyword for GNU Compiler */ + #define __INLINE inline /* inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /* asm keyword for TASKING Compiler */ + #define __INLINE inline /* inline keyword for TASKING Compiler */ + +#endif + + + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile ("csrw misa, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile ("csrw mepc, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile ("csrw mcause, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile ("csrw mtval, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); + return (result); +} + diff --git a/system/CH32V20x/SRC/Core/core_riscv.h b/system/CH32V20x/SRC/Core/core_riscv.h index b07815c..188a535 100644 --- a/system/CH32V20x/SRC/Core/core_riscv.h +++ b/system/CH32V20x/SRC/Core/core_riscv.h @@ -1,377 +1,589 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : core_riscv.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : RISC-V Core Peripheral Access Layer Header File for CH32V20x - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CORE_RISCV_H__ -#define __CORE_RISCV_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* IO definitions */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/* Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef __I uint64_t vuc64; /* Read Only */ -typedef __I uint32_t vuc32; /* Read Only */ -typedef __I uint16_t vuc16; /* Read Only */ -typedef __I uint8_t vuc8; /* Read Only */ - -typedef const uint64_t uc64; /* Read Only */ -typedef const uint32_t uc32; /* Read Only */ -typedef const uint16_t uc16; /* Read Only */ -typedef const uint8_t uc8; /* Read Only */ - -typedef __I int64_t vsc64; /* Read Only */ -typedef __I int32_t vsc32; /* Read Only */ -typedef __I int16_t vsc16; /* Read Only */ -typedef __I int8_t vsc8; /* Read Only */ - -typedef const int64_t sc64; /* Read Only */ -typedef const int32_t sc32; /* Read Only */ -typedef const int16_t sc16; /* Read Only */ -typedef const int8_t sc8; /* Read Only */ - -typedef __IO uint64_t vu64; -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef uint64_t u64; -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef __IO int64_t vs64; -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef int64_t s64; -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -#define RV_STATIC_INLINE static inline - -/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ -typedef struct{ - __I uint32_t ISR[8]; - __I uint32_t IPR[8]; - __IO uint32_t ITHRESDR; - __IO uint32_t RESERVED; - __IO uint32_t CFGR; - __I uint32_t GISR; - __IO uint8_t VTFIDR[4]; - uint8_t RESERVED0[12]; - __IO uint32_t VTFADDR[4]; - uint8_t RESERVED1[0x90]; - __O uint32_t IENR[8]; - uint8_t RESERVED2[0x60]; - __O uint32_t IRER[8]; - uint8_t RESERVED3[0x60]; - __O uint32_t IPSR[8]; - uint8_t RESERVED4[0x60]; - __O uint32_t IPRR[8]; - uint8_t RESERVED5[0x60]; - __IO uint32_t IACTR[8]; - uint8_t RESERVED6[0xE0]; - __IO uint8_t IPRIOR[256]; - uint8_t RESERVED7[0x810]; - __IO uint32_t SCTLR; -}PFIC_Type; - -/* memory mapped structure for SysTick */ -typedef struct -{ - __IO u32 CTLR; - __IO u32 SR; - __IO u64 CNT; - __IO u64 CMP; -}SysTick_Type; - - -#define PFIC ((PFIC_Type *) 0xE000E000 ) -#define NVIC PFIC -#define NVIC_KEY1 ((uint32_t)0xFA050000) -#define NVIC_KEY2 ((uint32_t)0xBCAF0000) -#define NVIC_KEY3 ((uint32_t)0xBEEF0000) - -#define SysTick ((SysTick_Type *) 0xE000F000) - - -/********************************************************************* - * @fn __enable_irq - * - * @brief Enable Global Interrupt - * - * @return none - */ -RV_STATIC_INLINE void __enable_irq() -{ - __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) ); -} - -/********************************************************************* - * @fn __disable_irq - * - * @brief Disable Global Interrupt - * - * @return none - */ -RV_STATIC_INLINE void __disable_irq() -{ - __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) ); -} - -/********************************************************************* - * @fn __NOP - * - * @brief nop - * - * @return none - */ -RV_STATIC_INLINE void __NOP() -{ - __asm volatile ("nop"); -} - -/********************************************************************* - * @fn NVIC_EnableIRQ - * - * @brief Disable Interrupt - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_DisableIRQ - * - * @brief Disable Interrupt - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_GetStatusIRQ - * - * @brief Get Interrupt Enable State - * - * @param IRQn - Interrupt Numbers - * - * @return 1 - 1: Interrupt Pending Enable - * 0 - Interrupt Pending Disable - */ -RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_GetPendingIRQ - * - * @brief Get Interrupt Pending State - * - * @param IRQn - Interrupt Numbers - * - * @return 1 - 1: Interrupt Pending Enable - * 0 - Interrupt Pending Disable - */ -RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_SetPendingIRQ - * - * @brief Set Interrupt Pending - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_ClearPendingIRQ - * - * @brief Clear Interrupt Pending - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_GetActive - * - * @brief Get Interrupt Active State - * - * @param IRQn - Interrupt Numbers - * - * @return 1 - Interrupt Active - * 0 - Interrupt No Active - */ -RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_SetPriority - * - * @brief Set Interrupt Priority - * - * @param IRQn - Interrupt Numbers - * priority: bit7 - pre-emption priority - * bit6-bit4 - subpriority - * - * @return none - */ -RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) -{ - NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; -} - -/********************************************************************* - * @fn __WFI - * - * @brief Wait for Interrupt - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) -{ - NVIC->SCTLR &= ~(1<<3); // wfi - asm volatile ("wfi"); -} - -/********************************************************************* - * @fn __WFE - * - * @brief Wait for Events - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) -{ - uint32_t t; - - t = NVIC->SCTLR; - NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev) - NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); - asm volatile ("wfi"); - asm volatile ("wfi"); -} - -/********************************************************************* - * @fn SetVTFIRQ - * - * @brief Set VTF Interrupt - * - * @param addr - VTF interrupt service function base address. - * IRQn - Interrupt Numbers - * num - VTF Interrupt Numbers - * NewState - DISABLE or ENABLE - * - * @return none - */ -RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ - if(num > 3) return ; - - if (NewState != DISABLE) - { - NVIC->VTFIDR[num] = IRQn; - NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); - } - else{ - NVIC->VTFIDR[num] = IRQn; - NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); - } -} - -/********************************************************************* - * @fn NVIC_SystemReset - * - * @brief Initiate a system reset request - * - * @return none - */ -RV_STATIC_INLINE void NVIC_SystemReset(void) -{ - NVIC->CFGR = NVIC_KEY3|(1<<7); -} - - - -/* Core_Exported_Functions */ -extern uint32_t __get_MSTATUS(void); -extern void __set_MSTATUS(uint32_t value); -extern uint32_t __get_MISA(void); -extern void __set_MISA(uint32_t value); -extern uint32_t __get_MIE(void); -extern void __set_MIE(uint32_t value); -extern uint32_t __get_MTVEC(void); -extern void __set_MTVEC(uint32_t value); -extern uint32_t __get_MSCRATCH(void); -extern void __set_MSCRATCH(uint32_t value); -extern uint32_t __get_MEPC(void); -extern void __set_MEPC(uint32_t value); -extern uint32_t __get_MCAUSE(void); -extern void __set_MCAUSE(uint32_t value); -extern uint32_t __get_MTVAL(void); -extern void __set_MTVAL(uint32_t value); -extern uint32_t __get_MVENDORID(void); -extern uint32_t __get_MARCHID(void); -extern uint32_t __get_MIMPID(void); -extern uint32_t __get_MHARTID(void); -extern uint32_t __get_SP(void); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.h + * Author : WCH + * Version : V1.0.1 + * Date : 2023/11/11 + * Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32V20x +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint64_t vuc64; /* Read Only */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint64_t uc64; /* Read Only */ +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int64_t vsc64; /* Read Only */ +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int64_t sc64; /* Read Only */ +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint64_t vu64; +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int64_t vs64; +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int64_t s64; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + __IO uint64_t CMP; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000 ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + +#define SysTick ((SysTick_Type *) 0xE000F000) + + +/********************************************************************* + * @fn __enable_irq + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrs 0x800, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __disable_irq + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrc 0x800, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + NVIC->SCTLR |= (1<<5); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + uint32_t tmp= NVIC->SCTLR; + tmp &= ~(1<<5); + tmp |= (1<<3); + NVIC->SCTLR = tmp; + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); + if(*(vu32*)(0x40023800) & (1<<6)) + { + NVIC->SCTLR |= (1<<5); + } +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param addr - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState) +{ + if(num > 3) return ; + + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + +/********************************************************************* + * @fn __AMOADD_W + * + * @brief Atomic Add with 32bit value + * Atomically ADD 32bit value with value in memory using amoadd.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ADDed + * + * @return return memory value + add value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoadd.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOAND_W + * + * @brief Atomic And with 32bit value + * Atomically AND 32bit value with value in memory using amoand.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ANDed + * + * @return return memory value & and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoand.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAX_W + * + * @brief Atomic signed MAX with 32bit value + * Atomically signed max compare 32bit value with value in memory using amomax.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomax.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAXU_W + * + * @brief Atomic unsigned MAX with 32bit value + * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amomaxu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMIN_W + * + * @brief Atomic signed MIN with 32bit value + * Atomically signed min compare 32bit value with value in memory using amomin.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomin.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMINU_W + * + * @brief Atomic unsigned MIN with 32bit value + * Atomically unsigned min compare 32bit value with value in memory using amominu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amominu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOOR_W + * + * @brief Atomic OR with 32bit value + * Atomically OR 32bit value with value in memory using amoor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ORed + * + * @return return memory value | and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOSWAP_W + * + * @brief Atomically swap new 32bit value into memory using amoswap.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * newval - New value to be stored into the address + * + * @return return the original value in memory + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) +{ + uint32_t result; + + __asm volatile ("amoswap.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); + return result; +} + +/********************************************************************* + * @fn __AMOXOR_W + * + * @brief Atomic XOR with 32bit value + * Atomically XOR 32bit value with value in memory using amoxor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be XORed + * + * @return return memory value ^ and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoxor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/* Core_Exported_Functions */ +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MTVAL(void); +extern void __set_MTVAL(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/system/CH32V20x/SRC/Debug/debug.c b/system/CH32V20x/SRC/Debug/debug.c index 199f1f8..fdce421 100644 --- a/system/CH32V20x/SRC/Debug/debug.c +++ b/system/CH32V20x/SRC/Debug/debug.c @@ -1,197 +1,253 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : debug.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for UART - * Printf , Delay functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include "debug.h" - -static uint8_t p_us = 0; -static uint16_t p_ms = 0; -/********************************************************************* - * @fn Delay_Init - * - * @brief Initializes Delay Funcation. - * - * @return none - */ -void Delay_Init(void) -{ - p_us = SystemCoreClock / 8000000; - p_ms = (uint16_t)p_us * 1000; -} - -/********************************************************************* - * @fn Delay_Us - * - * @brief Microsecond Delay Time. - * - * @param n - Microsecond number. - * - * @return None - */ -void Delay_Us(uint32_t n) -{ - uint32_t i; - - SysTick->SR &= ~(1 << 0); - i = (uint32_t)n * p_us; - - SysTick->CMP = i; - SysTick->CTLR |= (1 << 4); - SysTick->CTLR |= (1 << 5) | (1 << 0); - - while((SysTick->SR & (1 << 0)) != (1 << 0)); - SysTick->CTLR &= ~(1 << 0); -} - -/********************************************************************* - * @fn Delay_Ms - * - * @brief Millisecond Delay Time. - * - * @param n - Millisecond number. - * - * @return None - */ -void Delay_Ms(uint32_t n) -{ - uint32_t i; - - SysTick->SR &= ~(1 << 0); - i = (uint32_t)n * p_ms; - - SysTick->CMP = i; - SysTick->CTLR |= (1 << 4); - SysTick->CTLR |= (1 << 5) | (1 << 0); - - while((SysTick->SR & (1 << 0)) != (1 << 0)); - SysTick->CTLR &= ~(1 << 0); -} - -/********************************************************************* - * @fn USART_Printf_Init - * - * @brief Initializes the USARTx peripheral. - * - * @param baudrate - USART communication baud rate. - * - * @return None - */ -void USART_Printf_Init(uint32_t baudrate) -{ - GPIO_InitTypeDef GPIO_InitStructure; - USART_InitTypeDef USART_InitStructure; - -#if(DEBUG == DEBUG_UART1) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - -#elif(DEBUG == DEBUG_UART2) - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - -#elif(DEBUG == DEBUG_UART3) - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOB, &GPIO_InitStructure); - -#endif - - USART_InitStructure.USART_BaudRate = baudrate; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_No; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Tx; - -#if(DEBUG == DEBUG_UART1) - USART_Init(USART1, &USART_InitStructure); - USART_Cmd(USART1, ENABLE); - -#elif(DEBUG == DEBUG_UART2) - USART_Init(USART2, &USART_InitStructure); - USART_Cmd(USART2, ENABLE); - -#elif(DEBUG == DEBUG_UART3) - USART_Init(USART3, &USART_InitStructure); - USART_Cmd(USART3, ENABLE); - -#endif -} - -/********************************************************************* - * @fn _write - * - * @brief Support Printf Function - * - * @param *buf - UART send Data. - * size - Data length - * - * @return size: Data length - */ - - -#if 0 -//this is not necessary for arduino -__attribute__((used)) -int _write(int fd, char *buf, int size) -{ - int i; - - for(i = 0; i < size; i++){ -#if(DEBUG == DEBUG_UART1) - while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); - USART_SendData(USART1, *buf++); -#elif(DEBUG == DEBUG_UART2) - while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); - USART_SendData(USART2, *buf++); -#elif(DEBUG == DEBUG_UART3) - while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); - USART_SendData(USART3, *buf++); -#endif - } - - return size; -} -#endif - -/********************************************************************* - * @fn _sbrk - * - * @brief Change the spatial position of data segment. - * - * @return size: Data length - */ -void *_sbrk(ptrdiff_t incr) -{ - extern char _end[]; - extern char _heap_end[]; - static char *curbrk = _end; - - if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) - return NULL - 1; - - curbrk += incr; - return curbrk - incr; -} - -void _fini() {} +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "debug.h" + +static uint8_t p_us = 0; +static uint16_t p_ms = 0; + +#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE0000380) +#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE0000384) + +/********************************************************************* + * @fn Delay_Init + * + * @brief Initializes Delay Funcation. + * + * @return none + */ +void Delay_Init(void) +{ + p_us = SystemCoreClock / 8000000; + p_ms = (uint16_t)p_us * 1000; +} + +/********************************************************************* + * @fn Delay_Us + * + * @brief Microsecond Delay Time. + * + * @param n - Microsecond number. + * + * @return None + */ +void Delay_Us(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_us; + + SysTick->CMP = i; + SysTick->CTLR |= (1 << 4); + SysTick->CTLR |= (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn Delay_Ms + * + * @brief Millisecond Delay Time. + * + * @param n - Millisecond number. + * + * @return None + */ +void Delay_Ms(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_ms; + + SysTick->CMP = i; + SysTick->CTLR |= (1 << 4); + SysTick->CTLR |= (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn USART_Printf_Init + * + * @brief Initializes the USARTx peripheral. + * + * @param baudrate - USART communication baud rate. + * + * @return None + */ +void USART_Printf_Init(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + +#if(DEBUG == DEBUG_UART1) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART2) + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART3) + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + +#endif + + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx; + +#if(DEBUG == DEBUG_UART1) + USART_Init(USART1, &USART_InitStructure); + USART_Cmd(USART1, ENABLE); + +#elif(DEBUG == DEBUG_UART2) + USART_Init(USART2, &USART_InitStructure); + USART_Cmd(USART2, ENABLE); + +#elif(DEBUG == DEBUG_UART3) + USART_Init(USART3, &USART_InitStructure); + USART_Cmd(USART3, ENABLE); + +#endif +} + +/********************************************************************* + * @fn SDI_Printf_Enable + * + * @brief Initializes the SDI printf Function. + * + * @param None + * + * @return None + */ +void SDI_Printf_Enable(void) +{ + *(DEBUG_DATA0_ADDRESS) = 0; + Delay_Init(); + Delay_Ms(1); +} + +/********************************************************************* + * @fn _write + * + * @brief Support Printf Function + * + * @param *buf - UART send Data. + * size - Data length + * + * @return size: Data length + */ +#if 0 +__attribute__((used)) +int _write(int fd, char *buf, int size) +{ + int i = 0; + +#if (SDI_PRINT == SDI_PR_OPEN) + int writeSize = size; + + do + { + + /** + * data0 data1 8 byte + * data0 The storage length of the lowest byte, with a maximum of 7 bytes. + */ + + while( (*(DEBUG_DATA0_ADDRESS) != 0u)) + { + + } + + if(writeSize>7) + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + i += 7; + writeSize -= 7; + } + else + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + writeSize = 0; + } + + } while (writeSize); + + +#else + for(i = 0; i < size; i++){ +#if(DEBUG == DEBUG_UART1) + while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); + USART_SendData(USART1, *buf++); +#elif(DEBUG == DEBUG_UART2) + while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); + USART_SendData(USART2, *buf++); +#elif(DEBUG == DEBUG_UART3) + while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); + USART_SendData(USART3, *buf++); +#endif + } +#endif + return size; +} +#endif + +/********************************************************************* + * @fn _sbrk + * + * @brief Change the spatial position of data segment. + * + * @return size: Data length + */ +__attribute__((used)) +void *_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} + +void _fini() {} void _init() {} \ No newline at end of file diff --git a/system/CH32V20x/SRC/Debug/debug.h b/system/CH32V20x/SRC/Debug/debug.h index 69f2ed2..ebead36 100644 --- a/system/CH32V20x/SRC/Debug/debug.h +++ b/system/CH32V20x/SRC/Debug/debug.h @@ -1,48 +1,58 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : debug.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for UART - * Printf , Delay functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __DEBUG_H -#define __DEBUG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" -#include "stdio.h" - - - -/* UART Printf Definition */ -#define DEBUG_UART1 1 -#define DEBUG_UART2 2 -#define DEBUG_UART3 3 - -/* DEBUG UATR Definition */ -#define DEBUG DEBUG_UART1 -// #define DEBUG DEBUG_UART2 -//#define DEBUG DEBUG_UART3 - -void Delay_Init(void); -void Delay_Us(uint32_t n); -void Delay_Ms(uint32_t n); -void USART_Printf_Init(uint32_t baudrate); - -#if(DEBUG) - #define PRINT(format, ...) printf(format, ##__VA_ARGS__) -#else - #define PRINT(X...) -#endif - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/10/24 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __DEBUG_H +#define __DEBUG_H + +#include "stdio.h" +#include "ch32v20x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* UART Printf Definition */ +#define DEBUG_UART1 1 +#define DEBUG_UART2 2 +#define DEBUG_UART3 3 + +/* DEBUG UATR Definition */ +#ifndef DEBUG +#define DEBUG DEBUG_UART1 +#endif + +/* SDI Printf Definition */ +#define SDI_PR_CLOSE 0 +#define SDI_PR_OPEN 1 + +#ifndef SDI_PRINT +#define SDI_PRINT SDI_PR_CLOSE +#endif + + +void Delay_Init(void); +void Delay_Us(uint32_t n); +void Delay_Ms(uint32_t n); +void USART_Printf_Init(uint32_t baudrate); +void SDI_Printf_Enable(void); + +#if(DEBUG) + #define PRINT(format, ...) printf(format, ##__VA_ARGS__) +#else + #define PRINT(X...) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Ld/Link.ld b/system/CH32V20x/SRC/Ld/Link.ld index be5e9c3..d827a11 100644 --- a/system/CH32V20x/SRC/Ld/Link.ld +++ b/system/CH32V20x/SRC/Ld/Link.ld @@ -1 +1,183 @@ -__flash_size = DEFINED(__FLASH_SIZE) ? __FLASH_SIZE : 64K; __ram_size = DEFINED(__RAM_SIZE) ? __RAM_SIZE : 20K; __stack_size = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2048; ENTRY( _start ) PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /**/ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __flash_size RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __ram_size /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K */ } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +__flash_size = DEFINED(__FLASH_SIZE) ? __FLASH_SIZE : 64K; +__ram_size = DEFINED(__RAM_SIZE) ? __RAM_SIZE : 20K; +__stack_size = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2048; + + +ENTRY( _start ) +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __flash_size + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __ram_size + + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K +*/ + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x.h index ef111a1..29d3524 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x.h @@ -1,4817 +1,4889 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : CH32V20x Device Peripheral Access Layer Header File. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_H -#define __CH32V20x_H - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(CH32V20x_D8W) && !defined(CH32V20x_D8) && !defined(CH32V20x_D6) -#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8 */ -//#define CH32V20x_D8 /* CH32V203RBT6 */ -//#define CH32V20x_D8W /* CH32V208 */ - -#endif - -#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ - -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) - #define HSE_VALUE ((uint32_t)32000000) /* Value of the External oscillator in Hz */ -#else - #define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ -#endif - -/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x1000) /* Time out for HSE start up */ - -#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ - -/* Interrupt Number Definition, according to the selected device */ -typedef enum IRQn -{ - /****** RISC-V Processor Exceptions Numbers *******************************************************/ - NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ - EXC_IRQn = 3, /* 3 Exception Interrupt */ - Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ - Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ - Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ - SysTicK_IRQn = 12, /* 12 System timer Interrupt */ - Software_IRQn = 14, /* 14 software Interrupt */ - - /****** RISC-V specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 16, /* Window WatchDog Interrupt */ - PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 18, /* Tamper Interrupt */ - RTC_IRQn = 19, /* RTC global Interrupt */ - FLASH_IRQn = 20, /* FLASH global Interrupt */ - RCC_IRQn = 21, /* RCC global Interrupt */ - EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ - EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ - EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ - EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ - EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ - ADC_IRQn = 34, /* ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ - TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 44, /* TIM2 global Interrupt */ - TIM3_IRQn = 45, /* TIM3 global Interrupt */ - TIM4_IRQn = 46, /* TIM4 global Interrupt */ - I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ - I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ - I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ - I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ - SPI1_IRQn = 51, /* SPI1 global Interrupt */ - SPI2_IRQn = 52, /* SPI2 global Interrupt */ - USART1_IRQn = 53, /* USART1 global Interrupt */ - USART2_IRQn = 54, /* USART2 global Interrupt */ - USART3_IRQn = 55, /* USART3 global Interrupt */ - EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */ - USBHD_IRQn = 59, /* USBHD global Interrupt */ - USBHDWakeUp_IRQn = 60, /* USB Host/Device WakeUp Interrupt */ - -#ifdef CH32V20x_D6 - UART4_IRQn = 61, /* UART4 global Interrupt */ - DMA1_Channel8_IRQn = 62, /* DMA1 Channel 8 global Interrupt */ - -#elif defined(CH32V20x_D8) - ETH_IRQn = 61, /* ETH global Interrupt */ - ETHWakeUp_IRQn = 62, /* ETH WakeUp Interrupt */ - TIM5_IRQn = 65, /* TIM5 global Interrupt */ - UART4_IRQn = 66, /* UART4 global Interrupt */ - DMA1_Channel8_IRQn = 67, /* DMA1 Channel 8 global Interrupt */ - OSC32KCal_IRQn = 68, /* OSC32K global Interrupt */ - OSCWakeUp_IRQn = 69, /* OSC32K WakeUp Interrupt */ - -#elif defined(CH32V20x_D8W) - ETH_IRQn = 61, /* ETH global Interrupt */ - ETHWakeUp_IRQn = 62, /* ETH WakeUp Interrupt */ - BB_IRQn = 63, /* BLE BB global Interrupt */ - LLE_IRQn = 64, /* BLE LLE global Interrupt */ - TIM5_IRQn = 65, /* TIM5 global Interrupt */ - UART4_IRQn = 66, /* UART4 global Interrupt */ - DMA1_Channel8_IRQn = 67, /* DMA1 Channel 8 global Interrupt */ - OSC32KCal_IRQn = 68, /* OSC32K global Interrupt */ - OSCWakeUp_IRQn = 69, /* OSC32K WakeUp Interrupt */ -#endif - -} IRQn_Type; - -#define HardFault_IRQn EXC_IRQn -#define ADC1_2_IRQn ADC_IRQn - -#include -#include "core_riscv.h" -#include "system_ch32v20x.h" - -/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSI_Value HSI_VALUE -#define HSE_Value HSE_VALUE -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT - -/* Analog to Digital Converter */ -typedef struct -{ - __IO uint32_t STATR; - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t SAMPTR1; - __IO uint32_t SAMPTR2; - __IO uint32_t IOFR1; - __IO uint32_t IOFR2; - __IO uint32_t IOFR3; - __IO uint32_t IOFR4; - __IO uint32_t WDHTR; - __IO uint32_t WDLTR; - __IO uint32_t RSQR1; - __IO uint32_t RSQR2; - __IO uint32_t RSQR3; - __IO uint32_t ISQR; - __IO uint32_t IDATAR1; - __IO uint32_t IDATAR2; - __IO uint32_t IDATAR3; - __IO uint32_t IDATAR4; - __IO uint32_t RDATAR; -} ADC_TypeDef; - -/* Backup Registers */ -typedef struct -{ - uint32_t RESERVED0; - __IO uint16_t DATAR1; - uint16_t RESERVED1; - __IO uint16_t DATAR2; - uint16_t RESERVED2; - __IO uint16_t DATAR3; - uint16_t RESERVED3; - __IO uint16_t DATAR4; - uint16_t RESERVED4; - __IO uint16_t DATAR5; - uint16_t RESERVED5; - __IO uint16_t DATAR6; - uint16_t RESERVED6; - __IO uint16_t DATAR7; - uint16_t RESERVED7; - __IO uint16_t DATAR8; - uint16_t RESERVED8; - __IO uint16_t DATAR9; - uint16_t RESERVED9; - __IO uint16_t DATAR10; - uint16_t RESERVED10; - __IO uint16_t OCTLR; - uint16_t RESERVED11; - __IO uint16_t TPCTLR; - uint16_t RESERVED12; - __IO uint16_t TPCSR; - uint16_t RESERVED13[5]; - __IO uint16_t DATAR11; - uint16_t RESERVED14; - __IO uint16_t DATAR12; - uint16_t RESERVED15; - __IO uint16_t DATAR13; - uint16_t RESERVED16; - __IO uint16_t DATAR14; - uint16_t RESERVED17; - __IO uint16_t DATAR15; - uint16_t RESERVED18; - __IO uint16_t DATAR16; - uint16_t RESERVED19; - __IO uint16_t DATAR17; - uint16_t RESERVED20; - __IO uint16_t DATAR18; - uint16_t RESERVED21; - __IO uint16_t DATAR19; - uint16_t RESERVED22; - __IO uint16_t DATAR20; - uint16_t RESERVED23; - __IO uint16_t DATAR21; - uint16_t RESERVED24; - __IO uint16_t DATAR22; - uint16_t RESERVED25; - __IO uint16_t DATAR23; - uint16_t RESERVED26; - __IO uint16_t DATAR24; - uint16_t RESERVED27; - __IO uint16_t DATAR25; - uint16_t RESERVED28; - __IO uint16_t DATAR26; - uint16_t RESERVED29; - __IO uint16_t DATAR27; - uint16_t RESERVED30; - __IO uint16_t DATAR28; - uint16_t RESERVED31; - __IO uint16_t DATAR29; - uint16_t RESERVED32; - __IO uint16_t DATAR30; - uint16_t RESERVED33; - __IO uint16_t DATAR31; - uint16_t RESERVED34; - __IO uint16_t DATAR32; - uint16_t RESERVED35; - __IO uint16_t DATAR33; - uint16_t RESERVED36; - __IO uint16_t DATAR34; - uint16_t RESERVED37; - __IO uint16_t DATAR35; - uint16_t RESERVED38; - __IO uint16_t DATAR36; - uint16_t RESERVED39; - __IO uint16_t DATAR37; - uint16_t RESERVED40; - __IO uint16_t DATAR38; - uint16_t RESERVED41; - __IO uint16_t DATAR39; - uint16_t RESERVED42; - __IO uint16_t DATAR40; - uint16_t RESERVED43; - __IO uint16_t DATAR41; - uint16_t RESERVED44; - __IO uint16_t DATAR42; - uint16_t RESERVED45; -} BKP_TypeDef; - -/* Controller Area Network TxMailBox */ -typedef struct -{ - __IO uint32_t TXMIR; - __IO uint32_t TXMDTR; - __IO uint32_t TXMDLR; - __IO uint32_t TXMDHR; -} CAN_TxMailBox_TypeDef; - -/* Controller Area Network FIFOMailBox */ -typedef struct -{ - __IO uint32_t RXMIR; - __IO uint32_t RXMDTR; - __IO uint32_t RXMDLR; - __IO uint32_t RXMDHR; -} CAN_FIFOMailBox_TypeDef; - -/* Controller Area Network FilterRegister */ -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/* Controller Area Network */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t STATR; - __IO uint32_t TSTATR; - __IO uint32_t RFIFO0; - __IO uint32_t RFIFO1; - __IO uint32_t INTENR; - __IO uint32_t ERRSR; - __IO uint32_t BTIMR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FCTLR; - __IO uint32_t FMCFGR; - uint32_t RESERVED2; - __IO uint32_t FSCFGR; - uint32_t RESERVED3; - __IO uint32_t FAFIFOR; - uint32_t RESERVED4; - __IO uint32_t FWR; - uint32_t RESERVED5[8]; - CAN_FilterRegister_TypeDef sFilterRegister[28]; -} CAN_TypeDef; - -/* CRC Calculation Unit */ -typedef struct -{ - __IO uint32_t DATAR; - __IO uint8_t IDATAR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CTLR; -} CRC_TypeDef; - -/* DMA Channel Controller */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t CNTR; - __IO uint32_t PADDR; - __IO uint32_t MADDR; -} DMA_Channel_TypeDef; - -/* DMA Controller */ -typedef struct -{ - __IO uint32_t INTFR; - __IO uint32_t INTFCR; -} DMA_TypeDef; - -/* External Interrupt/Event Controller */ -typedef struct -{ - __IO uint32_t INTENR; - __IO uint32_t EVENR; - __IO uint32_t RTENR; - __IO uint32_t FTENR; - __IO uint32_t SWIEVR; - __IO uint32_t INTFR; -} EXTI_TypeDef; - -/* FLASH Registers */ -typedef struct -{ - __IO uint32_t ACTLR; - __IO uint32_t KEYR; - __IO uint32_t OBKEYR; - __IO uint32_t STATR; - __IO uint32_t CTLR; - __IO uint32_t ADDR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WPR; - __IO uint32_t MODEKEYR; -} FLASH_TypeDef; - -/* Option Bytes Registers */ -typedef struct -{ - __IO uint16_t RDPR; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRPR0; - __IO uint16_t WRPR1; - __IO uint16_t WRPR2; - __IO uint16_t WRPR3; -} OB_TypeDef; - -/* General Purpose I/O */ -typedef struct -{ - __IO uint32_t CFGLR; - __IO uint32_t CFGHR; - __IO uint32_t INDR; - __IO uint32_t OUTDR; - __IO uint32_t BSHR; - __IO uint32_t BCR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/* Alternate Function I/O */ -typedef struct -{ - __IO uint32_t ECR; - __IO uint32_t PCFR1; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t PCFR2; -} AFIO_TypeDef; - -/* Inter Integrated Circuit Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t OADDR1; - uint16_t RESERVED2; - __IO uint16_t OADDR2; - uint16_t RESERVED3; - __IO uint16_t DATAR; - uint16_t RESERVED4; - __IO uint16_t STAR1; - uint16_t RESERVED5; - __IO uint16_t STAR2; - uint16_t RESERVED6; - __IO uint16_t CKCFGR; - uint16_t RESERVED7; - __IO uint16_t RTR; - uint16_t RESERVED8; -} I2C_TypeDef; - -/* Independent WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t PSCR; - __IO uint32_t RLDR; - __IO uint32_t STATR; -} IWDG_TypeDef; - -/* Power Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/* Reset and Clock Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR0; - __IO uint32_t INTR; - __IO uint32_t APB2PRSTR; - __IO uint32_t APB1PRSTR; - __IO uint32_t AHBPCENR; - __IO uint32_t APB2PCENR; - __IO uint32_t APB1PCENR; - __IO uint32_t BDCTLR; - __IO uint32_t RSTSCKR; - - __IO uint32_t AHBRSTR; - __IO uint32_t CFGR2; -} RCC_TypeDef; - -/* Real-Time Clock */ -typedef struct -{ - __IO uint16_t CTLRH; - uint16_t RESERVED0; - __IO uint16_t CTLRL; - uint16_t RESERVED1; - __IO uint16_t PSCRH; - uint16_t RESERVED2; - __IO uint16_t PSCRL; - uint16_t RESERVED3; - __IO uint16_t DIVH; - uint16_t RESERVED4; - __IO uint16_t DIVL; - uint16_t RESERVED5; - __IO uint16_t CNTH; - uint16_t RESERVED6; - __IO uint16_t CNTL; - uint16_t RESERVED7; - __IO uint16_t ALRMH; - uint16_t RESERVED8; - __IO uint16_t ALRML; - uint16_t RESERVED9; -} RTC_TypeDef; - -/* Serial Peripheral Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t STATR; - uint16_t RESERVED2; - __IO uint16_t DATAR; - uint16_t RESERVED3; - __IO uint16_t CRCR; - uint16_t RESERVED4; - __IO uint16_t RCRCR; - uint16_t RESERVED5; - __IO uint16_t TCRCR; - uint16_t RESERVED6; - __IO uint16_t I2SCFGR; - uint16_t RESERVED7; - __IO uint16_t I2SPR; - uint16_t RESERVED8; - __IO uint16_t HSCR; - uint16_t RESERVED9; -} SPI_TypeDef; - -/* TIM */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t SMCFGR; - uint16_t RESERVED2; - __IO uint16_t DMAINTENR; - uint16_t RESERVED3; - __IO uint16_t INTFR; - uint16_t RESERVED4; - __IO uint16_t SWEVGR; - uint16_t RESERVED5; - __IO uint16_t CHCTLR1; - uint16_t RESERVED6; - __IO uint16_t CHCTLR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ATRLR; - uint16_t RESERVED11; - __IO uint16_t RPTCR; - uint16_t RESERVED12; - __IO uint16_t CH1CVR; - uint16_t RESERVED13; - __IO uint16_t CH2CVR; - uint16_t RESERVED14; - __IO uint16_t CH3CVR; - uint16_t RESERVED15; - __IO uint16_t CH4CVR; - uint16_t RESERVED16; - __IO uint16_t BDTR; - uint16_t RESERVED17; - __IO uint16_t DMACFGR; - uint16_t RESERVED18; - __IO uint16_t DMAADR; - uint16_t RESERVED19; -} TIM_TypeDef; - -/* Universal Synchronous Asynchronous Receiver Transmitter */ -typedef struct -{ - __IO uint16_t STATR; - uint16_t RESERVED0; - __IO uint16_t DATAR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CTLR1; - uint16_t RESERVED3; - __IO uint16_t CTLR2; - uint16_t RESERVED4; - __IO uint16_t CTLR3; - uint16_t RESERVED5; - __IO uint16_t GPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/* Window WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR; - __IO uint32_t STATR; -} WWDG_TypeDef; - -/* Enhanced Registers */ -typedef struct -{ - __IO uint32_t EXTEN_CTR; -} EXTEN_TypeDef; - -/* OPA Registers */ -typedef struct -{ - __IO uint32_t CR; -} OPA_TypeDef; - -/* USBFS Registers */ -typedef struct -{ - __IO uint8_t BASE_CTRL; - __IO uint8_t UDEV_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_ADDR; - __IO uint8_t Reserve0; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint32_t RX_LEN; - __IO uint8_t UEP4_1_MOD; - __IO uint8_t UEP2_3_MOD; - __IO uint8_t UEP5_6_MOD; - __IO uint8_t UEP7_MOD; - __IO uint32_t UEP0_DMA; - __IO uint32_t UEP1_DMA; - __IO uint32_t UEP2_DMA; - __IO uint32_t UEP3_DMA; - __IO uint32_t UEP4_DMA; - __IO uint32_t UEP5_DMA; - __IO uint32_t UEP6_DMA; - __IO uint32_t UEP7_DMA; - __IO uint16_t UEP0_TX_LEN; - __IO uint8_t UEP0_TX_CTRL; - __IO uint8_t UEP0_RX_CTRL; - __IO uint16_t UEP1_TX_LEN; - __IO uint8_t UEP1_TX_CTRL; - __IO uint8_t UEP1_RX_CTRL; - __IO uint16_t UEP2_TX_LEN; - __IO uint8_t UEP2_TX_CTRL; - __IO uint8_t UEP2_RX_CTRL; - __IO uint16_t UEP3_TX_LEN; - __IO uint8_t UEP3_TX_CTRL; - __IO uint8_t UEP3_RX_CTRL; - __IO uint16_t UEP4_TX_LEN; - __IO uint8_t UEP4_TX_CTRL; - __IO uint8_t UEP4_RX_CTRL; - __IO uint16_t UEP5_TX_LEN; - __IO uint8_t UEP5_TX_CTRL; - __IO uint8_t UEP5_RX_CTRL; - __IO uint16_t UEP6_TX_LEN; - __IO uint8_t UEP6_TX_CTRL; - __IO uint8_t UEP6_RX_CTRL; - __IO uint16_t UEP7_TX_LEN; - __IO uint8_t UEP7_TX_CTRL; - __IO uint8_t UEP7_RX_CTRL; - __IO uint32_t Reserve1; - __IO uint32_t OTG_CR; - __IO uint32_t OTG_SR; -} USBOTG_FS_TypeDef; - -typedef struct -{ - __IO uint8_t BASE_CTRL; - __IO uint8_t HOST_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_ADDR; - __IO uint8_t Reserve0; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint16_t RX_LEN; - __IO uint16_t Reserve1; - __IO uint8_t Reserve2; - __IO uint8_t HOST_EP_MOD; - __IO uint16_t Reserve3; - __IO uint32_t Reserve4; - __IO uint32_t Reserve5; - __IO uint32_t HOST_RX_DMA; - __IO uint32_t HOST_TX_DMA; - __IO uint32_t Reserve6; - __IO uint32_t Reserve7; - __IO uint32_t Reserve8; - __IO uint32_t Reserve9; - __IO uint32_t Reserve10; - __IO uint16_t Reserve11; - __IO uint16_t HOST_SETUP; - __IO uint8_t HOST_EP_PID; - __IO uint8_t Reserve12; - __IO uint8_t Reserve13; - __IO uint8_t HOST_RX_CTRL; - __IO uint16_t HOST_TX_LEN; - __IO uint8_t HOST_TX_CTRL; - __IO uint8_t Reserve14; - __IO uint32_t Reserve15; - __IO uint32_t Reserve16; - __IO uint32_t Reserve17; - __IO uint32_t Reserve18; - __IO uint32_t Reserve19; - __IO uint32_t OTG_CR; - __IO uint32_t OTG_SR; -} USBOTG_FS_HOST_TypeDef; - -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -/* ETH10M Registers */ -typedef struct -{ - __IO uint8_t reserved1; - __IO uint8_t reserved2; - __IO uint8_t reserved3; - __IO uint8_t EIE; - - __IO uint8_t EIR; - __IO uint8_t ESTAT; - __IO uint8_t ECON2; - __IO uint8_t ECON1; - - __IO uint16_t ETXST; - __IO uint16_t ETXLN; - - __IO uint16_t ERXST; - __IO uint16_t ERXLN; - - __IO uint32_t HTL; - __IO uint32_t HTH; - - __IO uint8_t ERXFON; - __IO uint8_t MACON1; - __IO uint8_t MACON2; - __IO uint8_t MABBIPG; - - __IO uint16_t EPAUS; - __IO uint16_t MAMXFL; - - __IO uint16_t MIRD; - __IO uint16_t reserved4; - - __IO uint8_t MIERGADR; - __IO uint8_t MISTAT; - __IO uint16_t MIWR; - - __IO uint32_t MAADRL; - - __IO uint16_t MAADRH; - __IO uint16_t reserved5; -} ETH10M_TypeDef; -#endif - -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -/* OSC Registers */ -typedef struct -{ - __IO uint32_t HSE_CAL_CTRL; - __IO uint32_t Reserve0; - __IO uint16_t Reserve1; - __IO uint16_t LSI32K_TUNE; - __IO uint32_t Reserve2; - __IO uint32_t Reserve3; - __IO uint32_t Reserve4; - __IO uint32_t Reserve5; - __IO uint8_t Reserve6; - __IO uint8_t LSI32K_CAL_CFG; - __IO uint16_t Reserve7; - __IO uint16_t LSI32K_CAL_STATR; - __IO uint8_t LSI32K_CAL_OV_CNT; - __IO uint8_t LSI32K_CAL_CTRL; -} OSC_TypeDef; - -#endif - -/* Peripheral memory map */ -#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ - -#define APB1PERIPH_BASE (PERIPH_BASE) -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -//#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -//#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA1_Channel8_BASE (AHBPERIPH_BASE + 0x0094) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) -#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) -#define OPA_BASE (AHBPERIPH_BASE + 0x3804) -#define ETH10M_BASE (AHBPERIPH_BASE + 0x8000) - -#define USBFS_BASE ((uint32_t)0x50000000) - -#define OB_BASE ((uint32_t)0x1FFFF800) - -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -#define OSC_BASE (AHBPERIPH_BASE + 0x202C) -#endif - -/* Peripheral declaration */ -#define TIM2 ((TIM_TypeDef *)TIM2_BASE) -#define TIM3 ((TIM_TypeDef *)TIM3_BASE) -#define TIM4 ((TIM_TypeDef *)TIM4_BASE) -#define TIM5 ((TIM_TypeDef *)TIM5_BASE) -#define RTC ((RTC_TypeDef *)RTC_BASE) -#define WWDG ((WWDG_TypeDef *)WWDG_BASE) -#define IWDG ((IWDG_TypeDef *)IWDG_BASE) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) -#define USART2 ((USART_TypeDef *)USART2_BASE) -#define USART3 ((USART_TypeDef *)USART3_BASE) -#define UART4 ((USART_TypeDef *)UART4_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define I2C2 ((I2C_TypeDef *)I2C2_BASE) -#define CAN1 ((CAN_TypeDef *)CAN1_BASE) -#define BKP ((BKP_TypeDef *)BKP_BASE) -#define PWR ((PWR_TypeDef *)PWR_BASE) - -#define AFIO ((AFIO_TypeDef *)AFIO_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#define ADC2 ((ADC_TypeDef *)ADC2_BASE) -#define TKey1 ((ADC_TypeDef *)ADC1_BASE) -#define TKey2 ((ADC_TypeDef *)ADC2_BASE) -#define TIM1 ((TIM_TypeDef *)TIM1_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) - -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE) -#define RCC ((RCC_TypeDef *)RCC_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#define CRC ((CRC_TypeDef *)CRC_BASE) -#define USBOTG_FS ((USBOTG_FS_TypeDef *)USBFS_BASE) -#define USBOTG_H_FS ((USBOTG_FS_HOST_TypeDef *)USBFS_BASE) -#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) -#define OPA ((OPA_TypeDef *)OPA_BASE) -#define ETH10M ((ETH10M_TypeDef *)ETH10M_BASE) - -#define OB ((OB_TypeDef *)OB_BASE) - -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -#define OSC ((OSC_TypeDef *)OSC_BASE) -#endif - - -/******************************************************************************/ -/* Peripheral Registers Bits Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* Analog to Digital Converter */ -/******************************************************************************/ - -/******************** Bit definition for ADC_STATR register ********************/ -#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ -#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ -#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ -#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ -#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ - -/******************* Bit definition for ADC_CTLR1 register ********************/ -#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ -#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ -#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ -#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ -#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ -#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ -#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ -#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ - -#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ -#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ - -#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ -#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ -#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ - -#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ -#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ - -/******************* Bit definition for ADC_CTLR2 register ********************/ -#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ -#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ -#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ -#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ -#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ -#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ - -#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ - -#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ -#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ -#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ - -#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ -#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ -#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ -#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ - -/****************** Bit definition for ADC_SAMPTR1 register *******************/ -#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ - -/****************** Bit definition for ADC_SAMPTR2 register *******************/ -#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ - -#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ -#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ -#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ - -/****************** Bit definition for ADC_IOFR1 register *******************/ -#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_IOFR2 register *******************/ -#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_IOFR3 register *******************/ -#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_IOFR4 register *******************/ -#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_WDHTR register ********************/ -#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ - -/******************* Bit definition for ADC_WDLTR register ********************/ -#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ - -/******************* Bit definition for ADC_RSQR1 register *******************/ -#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ -#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ - -/******************* Bit definition for ADC_RSQR2 register *******************/ -#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_RSQR3 register *******************/ -#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_ISQR register *******************/ -#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ -#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ - -/******************* Bit definition for ADC_IDATAR1 register *******************/ -#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR2 register *******************/ -#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR3 register *******************/ -#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR4 register *******************/ -#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************** Bit definition for ADC_RDATAR register ********************/ -#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ -#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ - -/******************************************************************************/ -/* Backup registers */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DATAR1 register ********************/ -#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR2 register ********************/ -#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR3 register ********************/ -#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR4 register ********************/ -#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR5 register ********************/ -#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR6 register ********************/ -#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR7 register ********************/ -#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR8 register ********************/ -#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR9 register ********************/ -#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR10 register *******************/ -#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR11 register *******************/ -#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR12 register *******************/ -#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR13 register *******************/ -#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR14 register *******************/ -#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR15 register *******************/ -#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR16 register *******************/ -#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR17 register *******************/ -#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ - -/****************** Bit definition for BKP_DATAR18 register ********************/ -#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR19 register *******************/ -#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR20 register *******************/ -#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR21 register *******************/ -#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR22 register *******************/ -#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR23 register *******************/ -#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR24 register *******************/ -#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR25 register *******************/ -#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR26 register *******************/ -#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR27 register *******************/ -#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR28 register *******************/ -#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR29 register *******************/ -#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR30 register *******************/ -#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR31 register *******************/ -#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR32 register *******************/ -#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR33 register *******************/ -#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR34 register *******************/ -#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR35 register *******************/ -#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR36 register *******************/ -#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR37 register *******************/ -#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR38 register *******************/ -#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR39 register *******************/ -#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR40 register *******************/ -#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR41 register *******************/ -#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR42 register *******************/ -#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ - -/****************** Bit definition for BKP_OCTLR register *******************/ -#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ -#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ -#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ -#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_TPCTLR register ********************/ -#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ -#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ - -/******************* Bit definition for BKP_TPCSR register ********************/ -#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ -#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ -#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ -#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ -#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ - -/******************************************************************************/ -/* Controller Area Network */ -/******************************************************************************/ - -/******************* Bit definition for CAN_CTLR register ********************/ -#define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */ -#define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */ -#define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */ -#define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */ -#define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */ -#define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */ -#define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */ -#define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */ -#define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */ - -/******************* Bit definition for CAN_STATR register ********************/ -#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ -#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ -#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ -#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ -#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ -#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ -#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ -#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ -#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ - -/******************* Bit definition for CAN_TSTATR register ********************/ -#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ -#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ -#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ -#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ -#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ -#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ -#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ -#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ -#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ -#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ -#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ -#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ -#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ -#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ -#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ -#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ - -#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ -#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ -#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ -#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ - -#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ -#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ - -/******************* Bit definition for CAN_RFIFO0 register *******************/ -#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ -#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ -#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ -#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ - -/******************* Bit definition for CAN_RFIFO1 register *******************/ -#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ -#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ -#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ -#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ - -/******************** Bit definition for CAN_INTENR register *******************/ -#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ -#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ -#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ -#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ -#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ -#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ -#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ -#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ -#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ -#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ -#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ -#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ -#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ -#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ - -/******************** Bit definition for CAN_ERRSR register *******************/ -#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ -#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ -#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ - -#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ -#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ - -#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ -#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ - -/******************* Bit definition for CAN_BTIMR register ********************/ -#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) /* Baud Rate Prescaler */ -#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) /* Time Segment 1 */ -#define CAN_BTIMR_TS2 ((uint32_t)0x00700000) /* Time Segment 2 */ -#define CAN_BTIMR_SJW ((uint32_t)0x03000000) /* Resynchronization Jump Width */ -#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */ -#define CAN_BTIMR_SILM ((uint32_t)0x80000000) /* Silent Mode */ - -/****************** Bit definition for CAN_TXMI0R register ********************/ -#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ -#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/****************** Bit definition for CAN_TXMDT0R register *******************/ -#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ -#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/****************** Bit definition for CAN_TXMDL0R register *******************/ -#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/****************** Bit definition for CAN_TXMDH0R register *******************/ -#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_TXMI1R register *******************/ -#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ -#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TXMDT1R register ******************/ -#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ -#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_TXMDL1R register ******************/ -#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_TXMDH1R register ******************/ -#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_TXMI2R register *******************/ -#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ -#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TXMDT2R register ******************/ -#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ -#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_TXMDL2R register ******************/ -#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_TXMDH2R register ******************/ -#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_RXMI0R register *******************/ -#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ -#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RXMDT0R register ******************/ -#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ -#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_RXMDL0R register ******************/ -#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_RXMDH0R register ******************/ -#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_RXMI1R register *******************/ -#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ -#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RXMDT1R register ******************/ -#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ -#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_RXMDL1R register ******************/ -#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_RXMDH1R register ******************/ -#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_FCTLR register ********************/ -#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ - -/******************* Bit definition for CAN_FMCFGR register *******************/ -#define CAN_FMCFGR_FBM ((uint16_t)0x3FFF) /* Filter Mode */ -#define CAN_FMCFGR_FBM0 ((uint16_t)0x0001) /* Filter Init Mode bit 0 */ -#define CAN_FMCFGR_FBM1 ((uint16_t)0x0002) /* Filter Init Mode bit 1 */ -#define CAN_FMCFGR_FBM2 ((uint16_t)0x0004) /* Filter Init Mode bit 2 */ -#define CAN_FMCFGR_FBM3 ((uint16_t)0x0008) /* Filter Init Mode bit 3 */ -#define CAN_FMCFGR_FBM4 ((uint16_t)0x0010) /* Filter Init Mode bit 4 */ -#define CAN_FMCFGR_FBM5 ((uint16_t)0x0020) /* Filter Init Mode bit 5 */ -#define CAN_FMCFGR_FBM6 ((uint16_t)0x0040) /* Filter Init Mode bit 6 */ -#define CAN_FMCFGR_FBM7 ((uint16_t)0x0080) /* Filter Init Mode bit 7 */ -#define CAN_FMCFGR_FBM8 ((uint16_t)0x0100) /* Filter Init Mode bit 8 */ -#define CAN_FMCFGR_FBM9 ((uint16_t)0x0200) /* Filter Init Mode bit 9 */ -#define CAN_FMCFGR_FBM10 ((uint16_t)0x0400) /* Filter Init Mode bit 10 */ -#define CAN_FMCFGR_FBM11 ((uint16_t)0x0800) /* Filter Init Mode bit 11 */ -#define CAN_FMCFGR_FBM12 ((uint16_t)0x1000) /* Filter Init Mode bit 12 */ -#define CAN_FMCFGR_FBM13 ((uint16_t)0x2000) /* Filter Init Mode bit 13 */ - -/******************* Bit definition for CAN_FSCFGR register *******************/ -#define CAN_FSCFGR_FSC ((uint16_t)0x3FFF) /* Filter Scale Configuration */ -#define CAN_FSCFGR_FSC0 ((uint16_t)0x0001) /* Filter Scale Configuration bit 0 */ -#define CAN_FSCFGR_FSC1 ((uint16_t)0x0002) /* Filter Scale Configuration bit 1 */ -#define CAN_FSCFGR_FSC2 ((uint16_t)0x0004) /* Filter Scale Configuration bit 2 */ -#define CAN_FSCFGR_FSC3 ((uint16_t)0x0008) /* Filter Scale Configuration bit 3 */ -#define CAN_FSCFGR_FSC4 ((uint16_t)0x0010) /* Filter Scale Configuration bit 4 */ -#define CAN_FSCFGR_FSC5 ((uint16_t)0x0020) /* Filter Scale Configuration bit 5 */ -#define CAN_FSCFGR_FSC6 ((uint16_t)0x0040) /* Filter Scale Configuration bit 6 */ -#define CAN_FSCFGR_FSC7 ((uint16_t)0x0080) /* Filter Scale Configuration bit 7 */ -#define CAN_FSCFGR_FSC8 ((uint16_t)0x0100) /* Filter Scale Configuration bit 8 */ -#define CAN_FSCFGR_FSC9 ((uint16_t)0x0200) /* Filter Scale Configuration bit 9 */ -#define CAN_FSCFGR_FSC10 ((uint16_t)0x0400) /* Filter Scale Configuration bit 10 */ -#define CAN_FSCFGR_FSC11 ((uint16_t)0x0800) /* Filter Scale Configuration bit 11 */ -#define CAN_FSCFGR_FSC12 ((uint16_t)0x1000) /* Filter Scale Configuration bit 12 */ -#define CAN_FSCFGR_FSC13 ((uint16_t)0x2000) /* Filter Scale Configuration bit 13 */ - -/****************** Bit definition for CAN_FAFIFOR register *******************/ -#define CAN_FAFIFOR_FFA ((uint16_t)0x3FFF) /* Filter FIFO Assignment */ -#define CAN_FAFIFOR_FFA0 ((uint16_t)0x0001) /* Filter FIFO Assignment for Filter 0 */ -#define CAN_FAFIFOR_FFA1 ((uint16_t)0x0002) /* Filter FIFO Assignment for Filter 1 */ -#define CAN_FAFIFOR_FFA2 ((uint16_t)0x0004) /* Filter FIFO Assignment for Filter 2 */ -#define CAN_FAFIFOR_FFA3 ((uint16_t)0x0008) /* Filter FIFO Assignment for Filter 3 */ -#define CAN_FAFIFOR_FFA4 ((uint16_t)0x0010) /* Filter FIFO Assignment for Filter 4 */ -#define CAN_FAFIFOR_FFA5 ((uint16_t)0x0020) /* Filter FIFO Assignment for Filter 5 */ -#define CAN_FAFIFOR_FFA6 ((uint16_t)0x0040) /* Filter FIFO Assignment for Filter 6 */ -#define CAN_FAFIFOR_FFA7 ((uint16_t)0x0080) /* Filter FIFO Assignment for Filter 7 */ -#define CAN_FAFIFOR_FFA8 ((uint16_t)0x0100) /* Filter FIFO Assignment for Filter 8 */ -#define CAN_FAFIFOR_FFA9 ((uint16_t)0x0200) /* Filter FIFO Assignment for Filter 9 */ -#define CAN_FAFIFOR_FFA10 ((uint16_t)0x0400) /* Filter FIFO Assignment for Filter 10 */ -#define CAN_FAFIFOR_FFA11 ((uint16_t)0x0800) /* Filter FIFO Assignment for Filter 11 */ -#define CAN_FAFIFOR_FFA12 ((uint16_t)0x1000) /* Filter FIFO Assignment for Filter 12 */ -#define CAN_FAFIFOR_FFA13 ((uint16_t)0x2000) /* Filter FIFO Assignment for Filter 13 */ - -/******************* Bit definition for CAN_FWR register *******************/ -#define CAN_FWR_FACT ((uint16_t)0x3FFF) /* Filter Active */ -#define CAN_FWR_FACT0 ((uint16_t)0x0001) /* Filter 0 Active */ -#define CAN_FWR_FACT1 ((uint16_t)0x0002) /* Filter 1 Active */ -#define CAN_FWR_FACT2 ((uint16_t)0x0004) /* Filter 2 Active */ -#define CAN_FWR_FACT3 ((uint16_t)0x0008) /* Filter 3 Active */ -#define CAN_FWR_FACT4 ((uint16_t)0x0010) /* Filter 4 Active */ -#define CAN_FWR_FACT5 ((uint16_t)0x0020) /* Filter 5 Active */ -#define CAN_FWR_FACT6 ((uint16_t)0x0040) /* Filter 6 Active */ -#define CAN_FWR_FACT7 ((uint16_t)0x0080) /* Filter 7 Active */ -#define CAN_FWR_FACT8 ((uint16_t)0x0100) /* Filter 8 Active */ -#define CAN_FWR_FACT9 ((uint16_t)0x0200) /* Filter 9 Active */ -#define CAN_FWR_FACT10 ((uint16_t)0x0400) /* Filter 10 Active */ -#define CAN_FWR_FACT11 ((uint16_t)0x0800) /* Filter 11 Active */ -#define CAN_FWR_FACT12 ((uint16_t)0x1000) /* Filter 12 Active */ -#define CAN_FWR_FACT13 ((uint16_t)0x2000) /* Filter 13 Active */ - -/******************* Bit definition for CAN_F0R1 register *******************/ -#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F1R1 register *******************/ -#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F2R1 register *******************/ -#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F3R1 register *******************/ -#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F4R1 register *******************/ -#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F5R1 register *******************/ -#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F6R1 register *******************/ -#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F7R1 register *******************/ -#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F8R1 register *******************/ -#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F9R1 register *******************/ -#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F10R1 register ******************/ -#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F11R1 register ******************/ -#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F12R1 register ******************/ -#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F13R1 register ******************/ -#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F0R2 register *******************/ -#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F1R2 register *******************/ -#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F2R2 register *******************/ -#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F3R2 register *******************/ -#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F4R2 register *******************/ -#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F5R2 register *******************/ -#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F6R2 register *******************/ -#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F7R2 register *******************/ -#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F8R2 register *******************/ -#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F9R2 register *******************/ -#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F10R2 register ******************/ -#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F11R2 register ******************/ -#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F12R2 register ******************/ -#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F13R2 register ******************/ -#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************************************************************************/ -/* CRC Calculation Unit */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DATAR register *********************/ -#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ - -/******************* Bit definition for CRC_IDATAR register ********************/ -#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ - -/******************** Bit definition for CRC_CTLR register ********************/ -#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ - -/******************************************************************************/ -/* DMA Controller */ -/******************************************************************************/ - -/******************* Bit definition for DMA_INTFR register ********************/ -#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ -#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ -#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ -#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ -#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ -#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ -#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ -#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ -#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ -#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ -#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ -#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ -#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ -#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ -#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ -#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ -#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ -#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ -#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ -#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ -#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ -#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ -#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ -#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ -#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ -#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ -#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ -#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ - -#define DMA_GIF8 ((uint32_t)0x00000001) /* Channel 8 Global interrupt flag */ -#define DMA_TCIF8 ((uint32_t)0x00000002) /* Channel 8 Transfer Complete flag */ -#define DMA_HTIF8 ((uint32_t)0x00000004) /* Channel 8 Half Transfer flag */ -#define DMA_TEIF8 ((uint32_t)0x00000008) /* Channel 8 Transfer Error flag */ -#define DMA_GIF9 ((uint32_t)0x00000010) /* Channel 9 Global interrupt flag */ -#define DMA_TCIF9 ((uint32_t)0x00000020) /* Channel 9 Transfer Complete flag */ -#define DMA_HTIF9 ((uint32_t)0x00000040) /* Channel 9 Half Transfer flag */ -#define DMA_TEIF9 ((uint32_t)0x00000080) /* Channel 9 Transfer Error flag */ -#define DMA_GIF10 ((uint32_t)0x00000100) /* Channel 10 Global interrupt flag */ -#define DMA_TCIF10 ((uint32_t)0x00000200) /* Channel 10 Transfer Complete flag */ -#define DMA_HTIF10 ((uint32_t)0x00000400) /* Channel 10 Half Transfer flag */ -#define DMA_TEIF10 ((uint32_t)0x00000800) /* Channel 10 Transfer Error flag */ -#define DMA_GIF11 ((uint32_t)0x00001000) /* Channel 11 Global interrupt flag */ -#define DMA_TCIF11 ((uint32_t)0x00002000) /* Channel 11 Transfer Complete flag */ -#define DMA_HTIF11 ((uint32_t)0x00004000) /* Channel 11 Half Transfer flag */ -#define DMA_TEIF11 ((uint32_t)0x00008000) /* Channel 11 Transfer Error flag */ - -/******************* Bit definition for DMA_INTFCR register *******************/ -#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ -#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ -#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ -#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ -#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ -#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ -#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ -#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ -#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ -#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ -#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ -#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ -#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ -#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ -#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ -#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ -#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ -#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ -#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ -#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ -#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ -#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ -#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ -#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ -#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ -#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ -#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ -#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CFGR1 register *******************/ -#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ -#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ -#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR2 register *******************/ -#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR3 register *******************/ -#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG4 register *******************/ -#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/****************** Bit definition for DMA_CFG5 register *******************/ -#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/******************* Bit definition for DMA_CFG6 register *******************/ -#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG7 register *******************/ -#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/****************** Bit definition for DMA_CNTR1 register ******************/ -#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR2 register ******************/ -#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR3 register ******************/ -#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR4 register ******************/ -#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR5 register ******************/ -#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR6 register ******************/ -#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR7 register ******************/ -#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_PADDR1 register *******************/ -#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR2 register *******************/ -#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR3 register *******************/ -#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR4 register *******************/ -#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR5 register *******************/ -#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR6 register *******************/ -#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR7 register *******************/ -#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_MADDR1 register *******************/ -#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR2 register *******************/ -#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR3 register *******************/ -#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR4 register *******************/ -#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR5 register *******************/ -#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR6 register *******************/ -#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR7 register *******************/ -#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/******************************************************************************/ -/* External Interrupt/Event Controller */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_INTENR register *******************/ -#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ -#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ -#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ -#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ -#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ -#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ -#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ -#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ -#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ -#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ -#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ -#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ -#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ -#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ -#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ -#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ -#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ -#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ -#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ -#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ - -/******************* Bit definition for EXTI_EVENR register *******************/ -#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ -#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ -#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ -#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ -#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ -#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ -#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ -#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ -#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ -#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ -#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ -#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ -#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ -#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ -#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ -#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ -#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ -#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ -#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ -#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ - -/****************** Bit definition for EXTI_RTENR register *******************/ -#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ -#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ -#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ -#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ -#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ -#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ -#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ -#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ -#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ -#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ -#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ -#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ -#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ -#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ -#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ -#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ -#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ -#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ -#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ -#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_FTENR register *******************/ -#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ -#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ -#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ -#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ -#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ -#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ -#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ -#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ -#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ -#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ -#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ -#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ -#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ -#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ -#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ -#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ -#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ -#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ -#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ -#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_SWIEVR register ******************/ -#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ -#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ -#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ -#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ -#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ -#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ -#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ -#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ -#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ -#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ -#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ -#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ -#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ -#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ -#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ -#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ -#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ -#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ -#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ -#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ - -/******************* Bit definition for EXTI_INTFR register ********************/ -#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ -#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ -#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ -#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ -#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ -#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ -#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ -#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ -#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ -#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ -#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ -#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ -#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ -#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ -#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ -#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ -#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ -#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ -#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ -#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ - -/******************************************************************************/ -/* FLASH and Option Bytes Registers */ -/******************************************************************************/ - -/******************* Bit definition for FLASH_ACTLR register ******************/ - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ - -/***************** Bit definition for FLASH_OBKEYR register ****************/ -#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ - -/****************** Bit definition for FLASH_STATR register *******************/ -#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ -#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ -#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ -#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ - -/******************* Bit definition for FLASH_CTLR register *******************/ -#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */ -#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */ -#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ -#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ -#define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ -#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ -#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ -#define FLASH_CTLR_OPTWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ -#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ -#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ -#define FLASH_CTLR_FAST_LOCK ((uint32_t)0x00008000) /* Fast Lock */ -#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */ -#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */ -#define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */ -#define FLASH_CTLR_PAGE_BER64 ((uint32_t)0x00080000) /* Block Erase 64K */ -#define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */ - -/******************* Bit definition for FLASH_ADDR register *******************/ -#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ - -#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ -#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ -#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /* BFB2 */ - -/****************** Bit definition for FLASH_WPR register ******************/ -#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ - -/****************** Bit definition for FLASH_RDPR register *******************/ -#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ -#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_WRPR0 register ******************/ -#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR1 register ******************/ -#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR2 register ******************/ -#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR3 register ******************/ -#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ - -/******************************************************************************/ -/* General Purpose and Alternate Function I/O */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CFGLR register *******************/ -#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_CFGHR register *******************/ -#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_INDR register *******************/ -#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ -#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ -#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ -#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ -#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ -#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ -#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ -#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ -#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ -#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ -#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ -#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ -#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ -#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ -#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ -#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ - -/******************* Bit definition for GPIO_OUTDR register *******************/ -#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ -#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ -#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ -#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ -#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ -#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ -#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ -#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ -#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ -#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ -#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ -#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ -#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ -#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ -#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ -#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSHR register *******************/ -#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ -#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ -#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ -#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ -#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ -#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ -#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ -#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ -#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ -#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ -#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ -#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ -#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ -#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ -#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ -#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ - -#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ -#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ -#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ -#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ -#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ -#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ -#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ -#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ -#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ -#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ -#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ -#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ -#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ -#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ -#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ -#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BCR register *******************/ -#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ -#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ -#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ -#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ -#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ -#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ -#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ -#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ -#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ -#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ -#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ -#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ -#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ -#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ -#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ -#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ -#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ -#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ -#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ -#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ -#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ -#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ -#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ -#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ -#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ -#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ -#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ -#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ -#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ -#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ -#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ -#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ - -/****************** Bit definition for AFIO_ECR register *******************/ -#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ -#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ -#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ -#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ -#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ - -#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ -#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ -#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ -#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ -#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ -#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ -#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ -#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ -#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ -#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ -#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ -#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ -#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ -#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ -#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ -#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ - -#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ -#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ -#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ -#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ - -#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ -#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ -#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ -#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ -#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ - -#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ - -/****************** Bit definition for AFIO_PCFR1register *******************/ -#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ -#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ -#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ -#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ - -#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ - -#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ -#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ - -#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ - -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ - -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ - -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ - -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ - -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ - -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ - -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ - -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ - -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ - -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ - -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ - -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ - -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ - -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ - -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ - -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ - -/******************************************************************************/ -/* Independent WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_CTLR register ********************/ -#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PSCR register ********************/ -#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ -#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ -#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ -#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ - -/******************* Bit definition for IWDG_RLDR register *******************/ -#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ - -/******************* Bit definition for IWDG_STATR register ********************/ -#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ -#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ - -/******************************************************************************/ -/* Inter-integrated Circuit Interface */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CTLR1 register ********************/ -#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ -#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ -#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ -#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ -#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ -#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ -#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ -#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ -#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ -#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ -#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ -#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ -#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ -#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ - -/******************* Bit definition for I2C_CTLR2 register ********************/ -#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ - -#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ -#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ -#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ -#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ -#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ - -/******************* Bit definition for I2C_OADDR1 register *******************/ -#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ -#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ - -#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ -#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ -#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ -#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ -#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ - -#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OADDR2 register *******************/ -#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ -#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ - -/******************** Bit definition for I2C_DATAR register ********************/ -#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ - -/******************* Bit definition for I2C_STAR1 register ********************/ -#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ -#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ -#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ -#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ -#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ -#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ -#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ -#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ -#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ -#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ -#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ -#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ -#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ -#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ - -/******************* Bit definition for I2C_STAR2 register ********************/ -#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ -#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ -#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ -#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ -#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ -#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ -#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ -#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ - -/******************* Bit definition for I2C_CKCFGR register ********************/ -#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ -#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ - -/****************** Bit definition for I2C_RTR register *******************/ -#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ - -/******************************************************************************/ -/* Power Control */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CTLR register ********************/ -#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ -#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ -#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ -#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ -#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ - -#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ -#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ - -#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */ -#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */ -#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */ -#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */ -#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */ -#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */ -#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */ -#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */ - -#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ - -/******************************************************************************/ -/* Reset and Clock Control */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CTLR register ********************/ -#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ -#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ -#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ -#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ -#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ -#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ -#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ -#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ -#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ -#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ - -/******************* Bit definition for RCC_CFGR0 register *******************/ -#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ -#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ -#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ -#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ - -#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ -#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ -#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ - -#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ -#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ -#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ - -#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ -#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ -#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ -#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ -#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ -#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ -#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ -#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ -#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ - -#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ -#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ - -#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* PPRE1 not divided */ -#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* PPRE1 divided by 2 */ -#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* PPRE1 divided by 4 */ -#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* PPRE1 divided by 8 */ -#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* PPRE1 divided by 16 */ - -#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ -#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ -#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ - -#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* PPRE2 not divided */ -#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* PPRE2 divided by 2 */ -#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* PPRE2 divided by 4 */ -#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* PPRE2 divided by 8 */ -#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* PPRE2 divided by 16 */ - -#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* ADCPRE divided by 2 */ -#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* ADCPRE divided by 4 */ -#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* ADCPRE divided by 6 */ -#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* ADCPRE divided by 8 */ - -#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ - -#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ - -#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ -#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ - -#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ -#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ - -#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ -#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ - -/* for other CH32V20x */ -#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ -#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ -#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ -#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ -#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ -#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ -#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ -#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ -#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ -#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ -#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ -#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ -#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ -#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ -#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ -#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ - -#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ - -#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ -#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ -#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ -#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ - -/******************* Bit definition for RCC_INTR register ********************/ -#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ -#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ -#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ -#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ -#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ -#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ -#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ -#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ -#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ -#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ -#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ -#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ -#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ -#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ -#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ -#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ -#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ - -/***************** Bit definition for RCC_APB2PRSTR register *****************/ -#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ -#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ -#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ -#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ -#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ -#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ - -#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ - -#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ -#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ -#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ - -#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ - -/***************** Bit definition for RCC_APB1PRSTR register *****************/ -#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ -#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ -#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ -#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ -#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ - -#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ - -#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ -#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ - -#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ -#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ -#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ -#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ - -#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ - -/****************** Bit definition for RCC_AHBPCENR register ******************/ -#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ -#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ -#define RCC_FLITFEN ((uint16_t)0x0010) /* FLITF clock enable */ -#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ -#define RCC_USBHD ((uint16_t)0x1000) - -/****************** Bit definition for RCC_APB2PCENR register *****************/ -#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ -#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ -#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ -#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ -#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ -#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ - -#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ - -#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ -#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ -#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ - -/***************** Bit definition for RCC_APB1PCENR register ******************/ -#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ -#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ -#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ -#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ -#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ - -#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ -#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ - -#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ - -/******************* Bit definition for RCC_BDCTLR register *******************/ -#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ -#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ -#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ - -#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ -#define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */ -#define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */ -#define RCC_RTCSEL_HSE ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ -#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ - -/******************* Bit definition for RCC_RSTSCKR register ********************/ -#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ -#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ -#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ -#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ -#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ -#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ -#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ -#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ -#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ - -/******************************************************************************/ -/* Real-Time Clock */ -/******************************************************************************/ - -/******************* Bit definition for RTC_CTLRH register ********************/ -#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ -#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ -#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ - -/******************* Bit definition for RTC_CTLRL register ********************/ -#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ -#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ -#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ -#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ -#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ -#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ - -/******************* Bit definition for RTC_PSCH register *******************/ -#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ - -/******************* Bit definition for RTC_PRLL register *******************/ -#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ - -/******************* Bit definition for RTC_DIVH register *******************/ -#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ - -/******************* Bit definition for RTC_DIVL register *******************/ -#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ - -/******************* Bit definition for RTC_CNTH register *******************/ -#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ - -/******************* Bit definition for RTC_CNTL register *******************/ -#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ - -/******************* Bit definition for RTC_ALRMH register *******************/ -#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ - -/******************* Bit definition for RTC_ALRML register *******************/ -#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ - -/******************************************************************************/ -/* Serial Peripheral Interface */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CTLR1 register ********************/ -#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ -#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ -#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ - -#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ -#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ -#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ -#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ - -#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ -#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ -#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ -#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ -#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ -#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ -#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ -#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ -#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ -#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CTLR2 register ********************/ -#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ -#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ -#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ -#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ -#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ -#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_STATR register ********************/ -#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ -#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ -#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ -#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ -#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ -#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ -#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ -#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ - -/******************** Bit definition for SPI_DATAR register ********************/ -#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ - -/******************* Bit definition for SPI_CRCR register ******************/ -#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ - -/****************** Bit definition for SPI_RCRCR register ******************/ -#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ - -/****************** Bit definition for SPI_TCRCR register ******************/ -#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ - -/****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ - -#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ -#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ - -/****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ -#define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ - -/******************************************************************************/ -/* TIM */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CTLR1 register ********************/ -#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ -#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ -#define TIM_URS ((uint16_t)0x0004) /* Update request source */ -#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ -#define TIM_DIR ((uint16_t)0x0010) /* Direction */ - -#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ - -#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ - -#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ -#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ - -/******************* Bit definition for TIM_CTLR2 register ********************/ -#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ -#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ -#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ - -#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ -#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ -#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ -#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ -#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ -#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ -#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ -#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ -#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIM_SMCFGR register *******************/ -#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ - -#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ -#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ - -#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ -#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ - -#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ -#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ - -/******************* Bit definition for TIM_DMAINTENR register *******************/ -#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ -#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ -#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ -#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ -#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ -#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ -#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ -#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ -#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ -#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ -#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ -#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ -#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ -#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ -#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ - -/******************** Bit definition for TIM_INTFR register ********************/ -#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ -#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ -#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ -#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ -#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ -#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ -#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ -#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ -#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ -#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ -#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ -#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIM_SWEVGR register ********************/ -#define TIM_UG ((uint8_t)0x01) /* Update Generation */ -#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ -#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ -#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ -#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ -#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ -#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ -#define TIM_BG ((uint8_t)0x80) /* Break Generation */ - -/****************** Bit definition for TIM_CHCTLR1 register *******************/ -#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ -#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ - -#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ - -#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ -#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ - -#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ - -#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/****************** Bit definition for TIM_CHCTLR2 register *******************/ -#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ -#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ - -#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ - -#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ -#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ - -#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ - -#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ -#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ -#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ -#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ -#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ -#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ -#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ -#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ -#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ -#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ -#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ -#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ -#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ -#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ -#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ - -/******************* Bit definition for TIM_ATRLR register ********************/ -#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ - -/******************* Bit definition for TIM_RPTCR register ********************/ -#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ - -/******************* Bit definition for TIM_CH1CVR register *******************/ -#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ - -/******************* Bit definition for TIM_CH2CVR register *******************/ -#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ - -/******************* Bit definition for TIM_CH3CVR register *******************/ -#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ - -/******************* Bit definition for TIM_CH4CVR register *******************/ -#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ -#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ -#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ -#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ - -#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ -#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ -#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ -#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ -#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ -#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ -#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ - -/******************* Bit definition for TIM_DMACFGR register ********************/ -#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ -#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ - -#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ -#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ - -/******************* Bit definition for TIM_DMAADR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ - -/******************************************************************************/ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/******************************************************************************/ - -/******************* Bit definition for USART_STATR register *******************/ -#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ -#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ -#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ -#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ -#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ -#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ -#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ -#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ -#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ -#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ - -/******************* Bit definition for USART_DATAR register *******************/ -#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ - -/****************** Bit definition for USART_CTLR1 register *******************/ -#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ -#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ -#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ -#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ -#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ -#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ -#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ -#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ -#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ -#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ -#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ -#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ -#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ -#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ -#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ - -/****************** Bit definition for USART_CTLR2 register *******************/ -#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ -#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ -#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ -#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ -#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ -#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ -#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ - -#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ -#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ -#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ - -/****************** Bit definition for USART_CTLR3 register *******************/ -#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ -#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ -#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ -#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ -#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ -#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ -#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ -#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ -#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ -#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ -#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ -#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ - -/****************** Bit definition for USART_GPR register ******************/ -#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ -#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ -#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ -#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ -#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ -#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ -#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ -#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ -#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ - -#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ - -/******************************************************************************/ -/* Window WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CTLR register ********************/ -#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ -#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ -#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ -#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ -#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ -#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ -#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ - -#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ - -/******************* Bit definition for WWDG_CFGR register *******************/ -#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ -#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ -#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ -#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ -#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ -#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ -#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ -#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ - -#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ -#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ - -#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_STATR register ********************/ -#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ - -/******************************************************************************/ -/* ENHANCED FUNNCTION */ -/******************************************************************************/ - -/**************************** Enhanced register *****************************/ -#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */ -#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */ -#define EXTEN_ETH_10M_EN ((uint32_t)0x00000004) /* Bit 2 */ -#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ -#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ -#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ - -#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */ -#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ -#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define EXTEN_LDO_TRIM ((uint32_t)0x00000C00) /* LDO_TRIM[1:0] bits */ -#define EXTEN_LDO_TRIM0 ((uint32_t)0x00000400) /* Bit 0 */ -#define EXTEN_LDO_TRIM1 ((uint32_t)0x00000800) /* Bit 1 */ - -/******************************************************************************/ -/* DVP */ -/******************************************************************************/ - -/******************* Bit definition for DVP_CR0 register ********************/ -#define RB_DVP_ENABLE 0x01 // RW, DVP enable -#define RB_DVP_V_POLAR 0x02 // RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert -#define RB_DVP_H_POLAR 0x04 // RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert -#define RB_DVP_P_POLAR 0x08 // RW, DVP PCLK polarity control: 1 = invert, 0 = not invert -#define RB_DVP_MSK_DAT_MOD 0x30 -#define RB_DVP_D8_MOD 0x00 // RW, DVP 8bits data mode -#define RB_DVP_D10_MOD 0x10 // RW, DVP 10bits data mode -#define RB_DVP_D12_MOD 0x20 // RW, DVP 12bits data mode -#define RB_DVP_JPEG 0x40 // RW, DVP JPEG mode - -/******************* Bit definition for DVP_CR1 register ********************/ -#define RB_DVP_DMA_EN 0x01 // RW, DVP dma enable -#define RB_DVP_ALL_CLR 0x02 // RW, DVP all clear, high action -#define RB_DVP_RCV_CLR 0x04 // RW, DVP receive logic clear, high action -#define RB_DVP_BUF_TOG 0x08 // RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0 -#define RB_DVP_CM 0x10 // RW, DVP capture mode -#define RB_DVP_CROP 0x20 // RW, DVP Crop feature enable -#define RB_DVP_FCRC 0xC0 // RW, DVP frame capture rate control: -#define DVP_RATE_100P 0x00 //00 = every frame captured (100%) -#define DVP_RATE_50P 0x40 //01 = every alternate frame captured (50%) -#define DVP_RATE_25P 0x80 //10 = one frame in four frame captured (25%) - -/******************* Bit definition for DVP_IER register ********************/ -#define RB_DVP_IE_STR_FRM 0x01 // RW, DVP frame start interrupt enable -#define RB_DVP_IE_ROW_DONE 0x02 // RW, DVP row received done interrupt enable -#define RB_DVP_IE_FRM_DONE 0x04 // RW, DVP frame received done interrupt enable -#define RB_DVP_IE_FIFO_OV 0x08 // RW, DVP receive fifo overflow interrupt enable -#define RB_DVP_IE_STP_FRM 0x10 // RW, DVP frame stop interrupt enable - -/******************* Bit definition for DVP_IFR register ********************/ -#define RB_DVP_IF_STR_FRM 0x01 // RW1, interrupt flag for DVP frame start -#define RB_DVP_IF_ROW_DONE 0x02 // RW1, interrupt flag for DVP row receive done -#define RB_DVP_IF_FRM_DONE 0x04 // RW1, interrupt flag for DVP frame receive done -#define RB_DVP_IF_FIFO_OV 0x08 // RW1, interrupt flag for DVP receive fifo overflow -#define RB_DVP_IF_STP_FRM 0x10 // RW1, interrupt flag for DVP frame stop - -/******************* Bit definition for DVP_STATUS register ********************/ -#define RB_DVP_FIFO_RDY 0x01 // RO, DVP receive fifo ready -#define RB_DVP_FIFO_FULL 0x02 // RO, DVP receive fifo full -#define RB_DVP_FIFO_OV 0x04 // RO, DVP receive fifo overflow -#define RB_DVP_MSK_FIFO_CNT 0x70 // RO, DVP receive fifo count - - -/******************************************************************************/ -/* ETH10M */ -/******************************************************************************/ -/* ETH register */ -#define R8_ETH_EIE (*((volatile uint8_t *)(0x40028000+3))) /* Interrupt Enable Register */ -#define RB_ETH_EIE_INTIE 0x80 /* RW interrupt enable*/ -#define RB_ETH_EIE_RXIE 0x40 /* RW Receive complete interrupt enable */ -#define RB_ETH_EIE_LINKIE 0x10 /* RW Link Change Interrupt Enable */ -#define RB_ETH_EIE_TXIE 0x08 /* RW send complete interrupt enable */ -#define RB_ETH_EIE_R_EN50 0x04 /* RW TX 50�� resistor adjustment. 1: On-chip 50�� connected 0: On-chip 50�� disconnected */ -#define RB_ETH_EIE_TXERIE 0x02 /* RW Transmit Error Interrupt Enable */ -#define RB_ETH_EIE_RXERIE 0x01 /* RW1 receive error flag */ -#define R8_ETH_EIR (*((volatile uint8_t *)(0x40028000+4))) /* Interrupt Flag Register */ -#define RB_ETH_EIR_RXIF 0x40 /* RW1 Receive complete flag */ -#define RB_ETH_EIR_LINKIF 0x10 /* RW1 Link Change Flag */ -#define RB_ETH_EIR_TXIF 0x08 /* RW1 Link Change Flag */ -#define RB_ETH_EIR_TXERIF 0x02 /* RW1 send error flag */ -#define RB_ETH_EIR_RXERIF 0x01 /* RW1 receive error flag */ -#define R8_ETH_ESTAT (*((volatile uint8_t *)(0x40028000+5))) /* status register */ -#define RB_ETH_ESTAT_INT 0x80 /* RW1 interrupt */ -#define RB_ETH_ESTAT_BUFER 0x40 /* RW1 Buffer error */ -#define RB_ETH_ESTAT_RXCRCER 0x20 /* RO receive crc error */ -#define RB_ETH_ESTAT_RXNIBBLE 0x10 /* RO receives nibble error */ -#define RB_ETH_ESTAT_RXMORE 0x08 /* RO receives more than maximum packets */ -#define RB_ETH_ESTAT_RXBUSY 0x04 /* RO receive busy */ -#define RB_ETH_ESTAT_TXABRT 0x02 /* RO send interrupted by mcu */ -#define R8_ETH_ECON2 (*((volatile uint8_t *)(0x40028000+6))) /* ETH PHY Analog Block Control Register */ -#define RB_ETH_ECON2_RX 0x0E /* 011b must be written */ -#define RB_ETH_ECON2_TX 0x01 -#define RB_ETH_ECON2_MUST 0x06 /* 011b must be written */ -#define R8_ETH_ECON1 (*((volatile uint8_t *)(0x40028000+7))) /* Transceiver Control Register */ -#define RB_ETH_ECON1_TXRST 0x80 /* RW Send module reset */ -#define RB_ETH_ECON1_RXRST 0x40 /* RW Receiver module reset */ -#define RB_ETH_ECON1_TXRTS 0x08 /* RW The transmission starts, and it is automatically cleared after the transmission is completed. */ -#define RB_ETH_ECON1_RXEN 0x04 /* RW Receive is enabled, when cleared, the error flag RXERIF will change to 1 if it is receiving */ - -#define R32_ETH_TX (*((volatile uint32_t *)(0x40028000+8))) /* send control */ -#define R16_ETH_ETXST (*((volatile uint16_t *)(0x40028000+8))) /* RW Send DMA buffer start address */ -#define R16_ETH_ETXLN (*((volatile uint16_t *)(0x40028000+0xA))) /* RW send length */ -#define R32_ETH_RX (*((volatile uint32_t *)(0x40028000+0xC))) /* receive control */ -#define R16_ETH_ERXST (*((volatile uint16_t *)(0x40028000+0xC))) /* RW Receive DMA buffer start address */ -#define R16_ETH_ERXLN (*((volatile uint16_t *)(0x40028000+0xE))) /* RO receive length */ - -#define R32_ETH_HTL (*((volatile uint32_t *)(0x40028000+0x10))) -#define R8_ETH_EHT0 (*((volatile uint8_t *)(0x40028000+0x10))) /* RW Hash Table Byte0 */ -#define R8_ETH_EHT1 (*((volatile uint8_t *)(0x40028000+0x11))) /* RW Hash Table Byte1 */ -#define R8_ETH_EHT2 (*((volatile uint8_t *)(0x40028000+0x12))) /* RW Hash Table Byte2 */ -#define R8_ETH_EHT3 (*((volatile uint8_t *)(0x40028000+0x13))) /* RW Hash Table Byte3 */ -#define R32_ETH_HTH (*((volatile uint32_t *)(0x40028000+0x14))) -#define R8_ETH_EHT4 (*((volatile uint8_t *)(0x40028000+0x14))) /* RW Hash Table Byte4 */ -#define R8_ETH_EHT5 (*((volatile uint8_t *)(0x40028000+0x15))) /* RW Hash Table Byte5 */ -#define R8_ETH_EHT6 (*((volatile uint8_t *)(0x40028000+0x16))) /* RW Hash Table Byte6 */ -#define R8_ETH_EHT7 (*((volatile uint8_t *)(0x40028000+0x17))) /* RW Hash Table Byte7 */ - -#define R32_ETH_MACON (*((volatile uint32_t *)(0x40028000+0x18))) -#define R8_ETH_ERXFCON (*((volatile uint8_t *)(0x40028000+0x18))) /* Received Packet Filtering Control Register */ -/* RW 0=Do not enable this filter condition, 1=When ANDOR=1, -target address mismatch will be filtered, when ANDOR=0, target address match will be accepted */ -#define RB_ETH_ERXFCON_UCEN 0x80 -#define RB_ETH_ERXFCON_CRCEN 0x20 -#define RB_ETH_ERXFCON_EN 0x10 -#define RB_ETH_ERXFCON_MPEN 0x08 -#define RB_ETH_ERXFCON_HTEN 0x04 -#define RB_ETH_ERXFCON_MCEN 0x02 -#define RB_ETH_ERXFCON_BCEN 0x01 -#define R8_ETH_MACON1 (*((volatile uint8_t *)(0x40028000+0x19))) /* Mac flow control registers */ -/* RW When FULDPX=0 is invalid, when FULDPX=1, 11=send 0 timer pause frame, -then stop sending, 10=send pause frame periodically, 01=send pause frame once, then stop sending, 00=stop sending pause frame */ -#define RB_ETH_MACON1_FCEN 0x30 -#define RB_ETH_MACON1_TXPAUS 0x08 /* RW Send pause frame enable*/ -#define RB_ETH_MACON1_RXPAUS 0x04 /* RW Receive pause frame enable */ -#define RB_ETH_MACON1_PASSALL 0x02 /* RW 1=Unfiltered control frames will be written to the buffer, 0=Control frames will be filtered */ -#define RB_ETH_MACON1_MARXEN 0x01 /* RW MAC layer receive enable */ -#define R8_ETH_MACON2 (*((volatile uint8_t *)(0x40028000+0x1A))) /* Mac Layer Packet Control Register */ -#define RB_ETH_MACON2_PADCFG 0xE0 /* RW Short Packet Padding Settings */ -#define RB_ETH_MACON2_TXCRCEN 0x10 /* RW Send to add crc, if you need to add crc in PADCFG, this position is 1 */ -#define RB_ETH_MACON2_PHDREN 0x08 /* RW Special 4 bytes do not participate in crc check */ -#define RB_ETH_MACON2_HFRMEN 0x04 /* RW Allow jumbo frames */ -#define RB_ETH_MACON2_FULDPX 0x01 /* RW full duplex */ -#define R8_ETH_MABBIPG (*((volatile uint8_t *)(0x40028000+0x1B))) /* Minimum Interpacket Interval Register */ -#define RB_ETH_MABBIPG_MABBIPG 0x7F /* RW Minimum number of bytes between packets */ - -#define R32_ETH_TIM (*((volatile uint32_t *)(0x40028000+0x1C))) -#define R16_ETH_EPAUS (*((volatile uint16_t *)(0x40028000+0x1C))) /* RW Flow Control Pause Frame Time Register */ -#define R16_ETH_MAMXFL (*((volatile uint16_t *)(0x40028000+0x1E))) /* RW Maximum Received Packet Length Register */ -#define R16_ETH_MIRD (*((volatile uint16_t *)(0x40028000+0x20))) /* RW MII read data register */ - -#define R32_ETH_MIWR (*((volatile uint32_t *)(0x40028000+0x24))) -#define R8_ETH_MIREGADR (*((volatile uint8_t *)(0x40028000+0x24))) /* MII address register*/ -#define RB_ETH_MIREGADR_MASK 0x1F /* RW PHY register address mask */ -#define R8_ETH_MISTAT (*((volatile uint8_t *)(0x40028000+0x25))) /* RW PHY register address mask */ -//#define RB_ETH_MIREGADR_MIIWR 0x20 /* WO MII write command */ -#define R16_ETH_MIWR (*((volatile uint16_t *)(0x40028000+0x26))) /* WO MII Write Data Register */ -#define R32_ETH_MAADRL (*((volatile uint32_t *)(0x40028000+0x28))) /* RW MAC 1-4 */ -#define R8_ETH_MAADRL1 (*((volatile uint8_t *)(0x40028000+0x28))) /* RW MAC 1 */ -#define R8_ETH_MAADRL2 (*((volatile uint8_t *)(0x40028000+0x29))) /* RW MAC 2 */ -#define R8_ETH_MAADRL3 (*((volatile uint8_t *)(0x40028000+0x2A))) /* RW MAC 3 */ -#define R8_ETH_MAADRL4 (*((volatile uint8_t *)(0x40028000+0x2B))) /* RW MAC 4 */ -#define R16_ETH_MAADRH (*((volatile uint16_t *)(0x40028000+0x2C))) /* RW MAC 5-6 */ -#define R8_ETH_MAADRL5 (*((volatile uint8_t *)(0x40028000+0x2C))) /* RW MAC 4 */ -#define R8_ETH_MAADRL6 (*((volatile uint8_t *)(0x40028000+0x2D))) /* RW MAC 4 */ - -//PHY address -#define PHY_BMCR 0x00 /* Control Register */ -#define PHY_BMSR 0x01 /* Status Register */ -#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisement Register */ -#define PHY_ANLPAR 0x05 /* Auto-Negotiation Link Partner Base Page Ability Register*/ -#define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ -#define PHY_MDIX 0x1e /* Custom MDIX Mode Register */ -//Custom MDIX Mode Register @PHY_MDIX -#define PN_NORMAL 0x04 /* Analog p, n polarity selection */ -#define MDIX_MODE_MASK 0x03 /* mdix settings */ -#define MDIX_MODE_AUTO 0x00 /* */ -#define MDIX_MODE_MDIX 0x01 -#define MDIX_MODE_MDI 0x02 -//ECON2 test mode, to be determined -#define RX_VCM_MODE_0 -#define RX_VCM_MODE_1 -#define RX_VCM_MODE_2 -#define RX_VCM_MODE_3 -//RX reference voltage value setting @RX_REF -#define RX_REF_25mV (0<<2) /* 25mV */ -#define RX_REF_49mV (1<<2) /* 49mV */ -#define RX_REF_74mV (2<<2) /* 74mV */ -#define RX_REF_98mV (3<<2) /* 98mV */ -#define RX_REF_123mV (4<<2) /* 123mV */ -#define RX_REF_148mV (5<<2) /* 148mV */ -#define RX_REF_173mV (6<<2) /* 173mV */ -#define RX_REF_198mV (7<<2) /* 198mV */ -//TX DRIVER Bias Current @TX_AMP -#define TX_AMP_0 (0<<0) /* 43mA / 14.5mA (1.4V/0.7V) */ -#define TX_AMP_1 (1<<0) /* 53.1mA / 18mA (1.8V/0.9V) */ -#define TX_AMP_2 (2<<0) /* 75.6mA / 25.6mA (2.6V/1.3V) */ -#define TX_AMP_3 (3<<0) /* 122mA / 41.45mA (4.1V/2.3V) */ -//FCEN pause frame control @FCEN -#define FCEN_0_TIMER (3<<4) /* Send a 0 timer pause frame, then stop sending */ -#define FCEN_CYCLE (2<<4) /* Periodically send pause frames */ -#define FCEN_ONCE (1<<4) /* Send pause frame once, then stop sending */ -#define FCEN_STOP (0<<4) /* Stop sending pause frames */ -//PADCFG short packet control @PADCFG -#define PADCFG_AUTO_0 (7<<5) /* All short packets are filled with 00h to 64 bytes, then 4 bytes crc */ -#define PADCFG_NO_ACT_0 (6<<5) /* No padding for short packets */ -/* The detected VLAN network packet whose field is 8100h is automatically filled -with 00h to 64 bytes, otherwise the short packet is filled with 60 bytes of 0, and then 4 bytes of crc after filling */ -#define PADCFG_DETE_AUTO (5<<5) -#define PADCFG_NO_ACT_1 (4<<5) /* No padding for short packets */ -#define PADCFG_AUTO_1 (3<<5) /* All short packets are filled with 00h to 64 bytes, then 4 bytes crc */ -#define PADCFG_NO_ACT_2 (2<<5) /* No padding for short packets */ -#define PADCFG_AUTO_3 (1<<5) /* All short packets are filled with 00h to 60 bytes, and then 4 bytes crc */ -#define PADCFG_NO_ACT_3 (0<<5) /* No padding for short packets */ - -/* Bit or field definition for PHY basic status register */ -#define PHY_Linked_Status ((uint16_t)0x0004) /* Valid link established */ - -#define PHY_Reset ((uint16_t)0x8000) /* PHY Reset */ - -#define PHY_AutoNego_Complete ((uint16_t)0x0020) /* Auto-Negotioation process completed */ - -//MII control -#define RB_ETH_MIREGADR_MIIWR 0x20 /* WO MII write command */ -#define RB_ETH_MIREGADR_MIRDL 0x1f /* RW PHY register address */ - - -#include "ch32v20x_conf.h" - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/07/04 + * Description : CH32V20x Device Peripheral Access Layer Header File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V20x_H +#define __CH32V20x_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(CH32V20x_D8W) && !defined(CH32V20x_D8) && !defined(CH32V20x_D6) +#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8*/ +//#define CH32V20x_D8 /* CH32V203RBT6 */ +//#define CH32V20x_D8W /* CH32V208 */ + +#endif + +#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#ifndef HSE_VALUE + #if defined(CH32V20x_D8) || defined(CH32V20x_D8W) + #define HSE_VALUE ((uint32_t)32000000) /* Value of the External oscillator in Hz */ + #else + #define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ + #endif +#endif + +/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x1000) /* Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ + +/* CH32V20x Standard Peripheral Library version number */ +#define __CH32V20x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */ +#define __CH32V20x_STDPERIPH_VERSION_SUB (0x02) /* [7:0] sub version */ +#define __CH32V20x_STDPERIPH_VERSION ( (__CH32V20x_STDPERIPH_VERSION_MAIN << 8)\ + |(__CH32V20x_STDPERIPH_VERSION_SUB << 0)) + + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */ + USBFS_IRQn = 59, /* USBFS global Interrupt */ + USBFSWakeUp_IRQn = 60, /* USB Host/Device WakeUp Interrupt */ + +#ifdef CH32V20x_D6 + UART4_IRQn = 61, /* UART4 global Interrupt */ + DMA1_Channel8_IRQn = 62, /* DMA1 Channel 8 global Interrupt */ + +#elif defined(CH32V20x_D8) + ETH_IRQn = 61, /* ETH global Interrupt */ + ETHWakeUp_IRQn = 62, /* ETH WakeUp Interrupt */ + TIM5_IRQn = 65, /* TIM5 global Interrupt */ + UART4_IRQn = 66, /* UART4 global Interrupt */ + DMA1_Channel8_IRQn = 67, /* DMA1 Channel 8 global Interrupt */ + OSC32KCal_IRQn = 68, /* OSC32K global Interrupt */ + OSCWakeUp_IRQn = 69, /* OSC32K WakeUp Interrupt */ + +#elif defined(CH32V20x_D8W) + ETH_IRQn = 61, /* ETH global Interrupt */ + ETHWakeUp_IRQn = 62, /* ETH WakeUp Interrupt */ + BB_IRQn = 63, /* BLE BB global Interrupt */ + LLE_IRQn = 64, /* BLE LLE global Interrupt */ + TIM5_IRQn = 65, /* TIM5 global Interrupt */ + UART4_IRQn = 66, /* UART4 global Interrupt */ + DMA1_Channel8_IRQn = 67, /* DMA1 Channel 8 global Interrupt */ + OSC32KCal_IRQn = 68, /* OSC32K global Interrupt */ + OSCWakeUp_IRQn = 69, /* OSC32K WakeUp Interrupt */ +#endif + +} IRQn_Type; + +#define HardFault_IRQn EXC_IRQn +#define ADC1_2_IRQn ADC_IRQn +#define SysTicK_IRQn SysTick_IRQn +#define USBHD_IRQn USBFS_IRQn +#define USBHDWakeUp_IRQn USBFSWakeUp_IRQn + +#define USBHD_IRQHandler USBFS_IRQHandler +#define USBHDWakeUp_IRQHandler USBFSWakeUp_IRQHandler + +#define USBOTG_FS USBFSD +#define USBOTG_H_FS USBFSH + + +#include +#include "core_riscv.h" +#include "system_ch32v20x.h" + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13[5]; + __IO uint16_t DATAR11; + uint16_t RESERVED14; + __IO uint16_t DATAR12; + uint16_t RESERVED15; + __IO uint16_t DATAR13; + uint16_t RESERVED16; + __IO uint16_t DATAR14; + uint16_t RESERVED17; + __IO uint16_t DATAR15; + uint16_t RESERVED18; + __IO uint16_t DATAR16; + uint16_t RESERVED19; + __IO uint16_t DATAR17; + uint16_t RESERVED20; + __IO uint16_t DATAR18; + uint16_t RESERVED21; + __IO uint16_t DATAR19; + uint16_t RESERVED22; + __IO uint16_t DATAR20; + uint16_t RESERVED23; + __IO uint16_t DATAR21; + uint16_t RESERVED24; + __IO uint16_t DATAR22; + uint16_t RESERVED25; + __IO uint16_t DATAR23; + uint16_t RESERVED26; + __IO uint16_t DATAR24; + uint16_t RESERVED27; + __IO uint16_t DATAR25; + uint16_t RESERVED28; + __IO uint16_t DATAR26; + uint16_t RESERVED29; + __IO uint16_t DATAR27; + uint16_t RESERVED30; + __IO uint16_t DATAR28; + uint16_t RESERVED31; + __IO uint16_t DATAR29; + uint16_t RESERVED32; + __IO uint16_t DATAR30; + uint16_t RESERVED33; + __IO uint16_t DATAR31; + uint16_t RESERVED34; + __IO uint16_t DATAR32; + uint16_t RESERVED35; + __IO uint16_t DATAR33; + uint16_t RESERVED36; + __IO uint16_t DATAR34; + uint16_t RESERVED37; + __IO uint16_t DATAR35; + uint16_t RESERVED38; + __IO uint16_t DATAR36; + uint16_t RESERVED39; + __IO uint16_t DATAR37; + uint16_t RESERVED40; + __IO uint16_t DATAR38; + uint16_t RESERVED41; + __IO uint16_t DATAR39; + uint16_t RESERVED42; + __IO uint16_t DATAR40; + uint16_t RESERVED43; + __IO uint16_t DATAR41; + uint16_t RESERVED44; + __IO uint16_t DATAR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/* Controller Area Network TxMailBox */ +typedef struct +{ + __IO uint32_t TXMIR; + __IO uint32_t TXMDTR; + __IO uint32_t TXMDLR; + __IO uint32_t TXMDHR; +} CAN_TxMailBox_TypeDef; + +/* Controller Area Network FIFOMailBox */ +typedef struct +{ + __IO uint32_t RXMIR; + __IO uint32_t RXMDTR; + __IO uint32_t RXMDLR; + __IO uint32_t RXMDHR; +} CAN_FIFOMailBox_TypeDef; + +/* Controller Area Network FilterRegister */ +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/* Controller Area Network */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t STATR; + __IO uint32_t TSTATR; + __IO uint32_t RFIFO0; + __IO uint32_t RFIFO1; + __IO uint32_t INTENR; + __IO uint32_t ERRSR; + __IO uint32_t BTIMR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FCTLR; + __IO uint32_t FMCFGR; + uint32_t RESERVED2; + __IO uint32_t FSCFGR; + uint32_t RESERVED3; + __IO uint32_t FAFIFOR; + uint32_t RESERVED4; + __IO uint32_t FWR; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[28]; +} CAN_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + +/* DMA Channel Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; + + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + union + { + __IO uint32_t CNT_R32; + struct + { + __IO uint16_t CNT; + uint16_t RESERVED9; + }; + }; + __IO uint16_t PSC; + uint16_t RESERVED10; + union + { + __IO uint32_t ATRLR_R32; + struct + { + __IO uint16_t ATRLR; + uint16_t RESERVED11; + }; + }; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + union + { + __IO uint32_t CH1CVR_R32; + struct + { + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + }; + }; + union + { + __IO uint32_t CH2CVR_R32; + struct + { + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + }; + }; + union + { + __IO uint32_t CH3CVR_R32; + struct + { + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + }; + }; + union + { + __IO uint32_t CH4CVR_R32; + struct + { + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + }; + }; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DMACFGR; + uint16_t RESERVED18; + __IO uint16_t DMAADR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* OPA Registers */ +typedef struct +{ + __IO uint32_t CR; +} OPA_TypeDef; + +/* USBFS Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint32_t RX_LEN; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint32_t Reserve1; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBFSD_TypeDef; + +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t Reserve2; + __IO uint8_t HOST_EP_MOD; + __IO uint16_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t Reserve6; + __IO uint32_t Reserve7; + __IO uint32_t Reserve8; + __IO uint32_t Reserve9; + __IO uint32_t Reserve10; + __IO uint16_t Reserve11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + __IO uint8_t Reserve12; + __IO uint8_t Reserve13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t Reserve14; + __IO uint32_t Reserve15; + __IO uint32_t Reserve16; + __IO uint32_t Reserve17; + __IO uint32_t Reserve18; + __IO uint32_t Reserve19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBFSH_TypeDef; + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +/* ETH10M Registers */ +typedef struct +{ + __IO uint8_t reserved1; + __IO uint8_t reserved2; + __IO uint8_t reserved3; + __IO uint8_t EIE; + + __IO uint8_t EIR; + __IO uint8_t ESTAT; + __IO uint8_t ECON2; + __IO uint8_t ECON1; + + __IO uint16_t ETXST; + __IO uint16_t ETXLN; + + __IO uint16_t ERXST; + __IO uint16_t ERXLN; + + __IO uint32_t HTL; + __IO uint32_t HTH; + + __IO uint8_t ERXFON; + __IO uint8_t MACON1; + __IO uint8_t MACON2; + __IO uint8_t MABBIPG; + + __IO uint16_t EPAUS; + __IO uint16_t MAMXFL; + + __IO uint16_t MIRD; + __IO uint16_t reserved4; + + __IO uint8_t MIERGADR; + __IO uint8_t MISTAT; + __IO uint16_t MIWR; + + __IO uint32_t MAADRL; + + __IO uint16_t MAADRH; + __IO uint16_t reserved5; +} ETH10M_TypeDef; +#endif + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +/* OSC Registers */ +typedef struct +{ + __IO uint32_t HSE_CAL_CTRL; + __IO uint32_t Reserve0; + __IO uint16_t Reserve1; + __IO uint16_t LSI32K_TUNE; + __IO uint32_t Reserve2; + __IO uint32_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint8_t Reserve6; + __IO uint8_t LSI32K_CAL_CFG; + __IO uint16_t Reserve7; + __IO uint16_t LSI32K_CAL_STATR; + __IO uint8_t LSI32K_CAL_OV_CNT; + __IO uint8_t LSI32K_CAL_CTRL; +} OSC_TypeDef; + +#endif + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA1_Channel8_BASE (AHBPERIPH_BASE + 0x0094) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) +#define OPA_BASE (AHBPERIPH_BASE + 0x3804) +#define ETH10M_BASE (AHBPERIPH_BASE + 0x8000) + +#define USBFS_BASE ((uint32_t)0x50000000) + +#define OB_BASE ((uint32_t)0x1FFFF800) + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +#define OSC_BASE (AHBPERIPH_BASE + 0x202C) +#endif + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define TIM5 ((TIM_TypeDef *)TIM5_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define UART4 ((USART_TypeDef *)UART4_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) + +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define TKey1 ((ADC_TypeDef *)ADC1_BASE) +#define TKey2 ((ADC_TypeDef *)ADC2_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) + +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE) +#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) +#define OPA ((OPA_TypeDef *)OPA_BASE) +#define ETH10M ((ETH10M_TypeDef *)ETH10M_BASE) + +#define OB ((OB_TypeDef *)OB_BASE) + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +#define OSC ((OSC_TypeDef *)OSC_BASE) +#endif + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR11 register *******************/ +#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR12 register *******************/ +#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR13 register *******************/ +#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR14 register *******************/ +#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR15 register *******************/ +#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR16 register *******************/ +#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR17 register *******************/ +#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_DATAR18 register ********************/ +#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR19 register *******************/ +#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR20 register *******************/ +#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR21 register *******************/ +#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR22 register *******************/ +#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR23 register *******************/ +#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR24 register *******************/ +#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR25 register *******************/ +#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR26 register *******************/ +#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR27 register *******************/ +#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR28 register *******************/ +#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR29 register *******************/ +#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR30 register *******************/ +#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR31 register *******************/ +#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR32 register *******************/ +#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR33 register *******************/ +#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR34 register *******************/ +#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR35 register *******************/ +#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR36 register *******************/ +#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR37 register *******************/ +#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR38 register *******************/ +#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR39 register *******************/ +#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR40 register *******************/ +#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR41 register *******************/ +#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR42 register *******************/ +#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* Controller Area Network */ +/******************************************************************************/ + +/******************* Bit definition for CAN_CTLR register ********************/ +#define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */ +#define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */ +#define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */ +#define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */ +#define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */ +#define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */ +#define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */ +#define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */ +#define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */ + +/******************* Bit definition for CAN_STATR register ********************/ +#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ +#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ +#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ +#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ +#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ +#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ +#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ +#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTATR register ********************/ +#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ + +#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFIFO0 register *******************/ +#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ +#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ +#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ +#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFIFO1 register *******************/ +#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ +#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ +#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ +#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTENR register *******************/ +#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ +#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ERRSR register *******************/ +#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ +#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ +#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ + +#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ + +#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ + +/******************* Bit definition for CAN_BTIMR register ********************/ +#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) /* Baud Rate Prescaler */ +#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) /* Time Segment 1 */ +#define CAN_BTIMR_TS2 ((uint32_t)0x00700000) /* Time Segment 2 */ +#define CAN_BTIMR_SJW ((uint32_t)0x03000000) /* Resynchronization Jump Width */ +#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */ +#define CAN_BTIMR_SILM ((uint32_t)0x80000000) /* Silent Mode */ + +/****************** Bit definition for CAN_TXMI0R register ********************/ +#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TXMDT0R register *******************/ +#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/****************** Bit definition for CAN_TXMDL0R register *******************/ +#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/****************** Bit definition for CAN_TXMDH0R register *******************/ +#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI1R register *******************/ +#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT1R register ******************/ +#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL1R register ******************/ +#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH1R register ******************/ +#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI2R register *******************/ +#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT2R register ******************/ +#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL2R register ******************/ +#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH2R register ******************/ +#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI0R register *******************/ +#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT0R register ******************/ +#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL0R register ******************/ +#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH0R register ******************/ +#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI1R register *******************/ +#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT1R register ******************/ +#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL1R register ******************/ +#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH1R register ******************/ +#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_FCTLR register ********************/ +#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ + +/******************* Bit definition for CAN_FMCFGR register *******************/ +#define CAN_FMCFGR_FBM ((uint16_t)0x3FFF) /* Filter Mode */ +#define CAN_FMCFGR_FBM0 ((uint16_t)0x0001) /* Filter Init Mode bit 0 */ +#define CAN_FMCFGR_FBM1 ((uint16_t)0x0002) /* Filter Init Mode bit 1 */ +#define CAN_FMCFGR_FBM2 ((uint16_t)0x0004) /* Filter Init Mode bit 2 */ +#define CAN_FMCFGR_FBM3 ((uint16_t)0x0008) /* Filter Init Mode bit 3 */ +#define CAN_FMCFGR_FBM4 ((uint16_t)0x0010) /* Filter Init Mode bit 4 */ +#define CAN_FMCFGR_FBM5 ((uint16_t)0x0020) /* Filter Init Mode bit 5 */ +#define CAN_FMCFGR_FBM6 ((uint16_t)0x0040) /* Filter Init Mode bit 6 */ +#define CAN_FMCFGR_FBM7 ((uint16_t)0x0080) /* Filter Init Mode bit 7 */ +#define CAN_FMCFGR_FBM8 ((uint16_t)0x0100) /* Filter Init Mode bit 8 */ +#define CAN_FMCFGR_FBM9 ((uint16_t)0x0200) /* Filter Init Mode bit 9 */ +#define CAN_FMCFGR_FBM10 ((uint16_t)0x0400) /* Filter Init Mode bit 10 */ +#define CAN_FMCFGR_FBM11 ((uint16_t)0x0800) /* Filter Init Mode bit 11 */ +#define CAN_FMCFGR_FBM12 ((uint16_t)0x1000) /* Filter Init Mode bit 12 */ +#define CAN_FMCFGR_FBM13 ((uint16_t)0x2000) /* Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FSCFGR register *******************/ +#define CAN_FSCFGR_FSC ((uint16_t)0x3FFF) /* Filter Scale Configuration */ +#define CAN_FSCFGR_FSC0 ((uint16_t)0x0001) /* Filter Scale Configuration bit 0 */ +#define CAN_FSCFGR_FSC1 ((uint16_t)0x0002) /* Filter Scale Configuration bit 1 */ +#define CAN_FSCFGR_FSC2 ((uint16_t)0x0004) /* Filter Scale Configuration bit 2 */ +#define CAN_FSCFGR_FSC3 ((uint16_t)0x0008) /* Filter Scale Configuration bit 3 */ +#define CAN_FSCFGR_FSC4 ((uint16_t)0x0010) /* Filter Scale Configuration bit 4 */ +#define CAN_FSCFGR_FSC5 ((uint16_t)0x0020) /* Filter Scale Configuration bit 5 */ +#define CAN_FSCFGR_FSC6 ((uint16_t)0x0040) /* Filter Scale Configuration bit 6 */ +#define CAN_FSCFGR_FSC7 ((uint16_t)0x0080) /* Filter Scale Configuration bit 7 */ +#define CAN_FSCFGR_FSC8 ((uint16_t)0x0100) /* Filter Scale Configuration bit 8 */ +#define CAN_FSCFGR_FSC9 ((uint16_t)0x0200) /* Filter Scale Configuration bit 9 */ +#define CAN_FSCFGR_FSC10 ((uint16_t)0x0400) /* Filter Scale Configuration bit 10 */ +#define CAN_FSCFGR_FSC11 ((uint16_t)0x0800) /* Filter Scale Configuration bit 11 */ +#define CAN_FSCFGR_FSC12 ((uint16_t)0x1000) /* Filter Scale Configuration bit 12 */ +#define CAN_FSCFGR_FSC13 ((uint16_t)0x2000) /* Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FAFIFOR register *******************/ +#define CAN_FAFIFOR_FFA ((uint16_t)0x3FFF) /* Filter FIFO Assignment */ +#define CAN_FAFIFOR_FFA0 ((uint16_t)0x0001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FAFIFOR_FFA1 ((uint16_t)0x0002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FAFIFOR_FFA2 ((uint16_t)0x0004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FAFIFOR_FFA3 ((uint16_t)0x0008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FAFIFOR_FFA4 ((uint16_t)0x0010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FAFIFOR_FFA5 ((uint16_t)0x0020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FAFIFOR_FFA6 ((uint16_t)0x0040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FAFIFOR_FFA7 ((uint16_t)0x0080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FAFIFOR_FFA8 ((uint16_t)0x0100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FAFIFOR_FFA9 ((uint16_t)0x0200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FAFIFOR_FFA10 ((uint16_t)0x0400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FAFIFOR_FFA11 ((uint16_t)0x0800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FAFIFOR_FFA12 ((uint16_t)0x1000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FAFIFOR_FFA13 ((uint16_t)0x2000) /* Filter FIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FWR register *******************/ +#define CAN_FWR_FACT ((uint16_t)0x3FFF) /* Filter Active */ +#define CAN_FWR_FACT0 ((uint16_t)0x0001) /* Filter 0 Active */ +#define CAN_FWR_FACT1 ((uint16_t)0x0002) /* Filter 1 Active */ +#define CAN_FWR_FACT2 ((uint16_t)0x0004) /* Filter 2 Active */ +#define CAN_FWR_FACT3 ((uint16_t)0x0008) /* Filter 3 Active */ +#define CAN_FWR_FACT4 ((uint16_t)0x0010) /* Filter 4 Active */ +#define CAN_FWR_FACT5 ((uint16_t)0x0020) /* Filter 5 Active */ +#define CAN_FWR_FACT6 ((uint16_t)0x0040) /* Filter 6 Active */ +#define CAN_FWR_FACT7 ((uint16_t)0x0080) /* Filter 7 Active */ +#define CAN_FWR_FACT8 ((uint16_t)0x0100) /* Filter 8 Active */ +#define CAN_FWR_FACT9 ((uint16_t)0x0200) /* Filter 9 Active */ +#define CAN_FWR_FACT10 ((uint16_t)0x0400) /* Filter 10 Active */ +#define CAN_FWR_FACT11 ((uint16_t)0x0800) /* Filter 11 Active */ +#define CAN_FWR_FACT12 ((uint16_t)0x1000) /* Filter 12 Active */ +#define CAN_FWR_FACT13 ((uint16_t)0x2000) /* Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + +#define DMA_GIF8 ((uint32_t)0x00000001) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x00000002) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x00000004) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x00000008) /* Channel 8 Transfer Error flag */ +#define DMA_GIF9 ((uint32_t)0x00000010) /* Channel 9 Global interrupt flag */ +#define DMA_TCIF9 ((uint32_t)0x00000020) /* Channel 9 Transfer Complete flag */ +#define DMA_HTIF9 ((uint32_t)0x00000040) /* Channel 9 Half Transfer flag */ +#define DMA_TEIF9 ((uint32_t)0x00000080) /* Channel 9 Transfer Error flag */ +#define DMA_GIF10 ((uint32_t)0x00000100) /* Channel 10 Global interrupt flag */ +#define DMA_TCIF10 ((uint32_t)0x00000200) /* Channel 10 Transfer Complete flag */ +#define DMA_HTIF10 ((uint32_t)0x00000400) /* Channel 10 Half Transfer flag */ +#define DMA_TEIF10 ((uint32_t)0x00000800) /* Channel 10 Transfer Error flag */ +#define DMA_GIF11 ((uint32_t)0x00001000) /* Channel 11 Global interrupt flag */ +#define DMA_TCIF11 ((uint32_t)0x00002000) /* Channel 11 Transfer Complete flag */ +#define DMA_HTIF11 ((uint32_t)0x00004000) /* Channel 11 Half Transfer flag */ +#define DMA_TEIF11 ((uint32_t)0x00008000) /* Channel 11 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */ +#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */ +#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ +#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ +#define FLASH_CTLR_OPTWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FAST_LOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */ +#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */ +#define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */ +#define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /* BFB2 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ +#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) +#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080) +#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0) +#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0) +#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0) + +#define PWR_CTLR_PLS_2V2 PWR_CTLR_PLS_MODE0 +#define PWR_CTLR_PLS_2V3 PWR_CTLR_PLS_MODE1 +#define PWR_CTLR_PLS_2V4 PWR_CTLR_PLS_MODE2 +#define PWR_CTLR_PLS_2V5 PWR_CTLR_PLS_MODE3 +#define PWR_CTLR_PLS_2V6 PWR_CTLR_PLS_MODE4 +#define PWR_CTLR_PLS_2V7 PWR_CTLR_PLS_MODE5 +#define PWR_CTLR_PLS_2V8 PWR_CTLR_PLS_MODE6 +#define PWR_CTLR_PLS_2V9 PWR_CTLR_PLS_MODE7 + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* PPRE1 not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* PPRE1 divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* PPRE1 divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* PPRE1 divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* PPRE1 divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* PPRE2 not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* PPRE2 divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* PPRE2 divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* PPRE2 divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* PPRE2 divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* ADCPRE divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* ADCPRE divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* ADCPRE divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* ADCPRE divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +/* for other CH32V20x */ +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ +#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ + +#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ + +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ + +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ + +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ + +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ + +#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ +#define RCC_FLITFEN ((uint16_t)0x0010) /* FLITF clock enable */ +#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ +#define RCC_USBFS ((uint16_t)0x1000) +#define RCC_USBHD RCC_USBFS + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ + +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ + +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ + +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */ +#define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */ +#define RCC_RTCSEL_HSE ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCH register *******************/ +#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ +#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ +#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */ +#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */ +#define EXTEN_ETH_10M_EN ((uint32_t)0x00000004) /* Bit 2 */ +#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + +#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */ +#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ +#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define EXTEN_LDO_TRIM ((uint32_t)0x00000C00) /* LDO_TRIM[1:0] bits */ +#define EXTEN_LDO_TRIM0 ((uint32_t)0x00000400) /* Bit 0 */ +#define EXTEN_LDO_TRIM1 ((uint32_t)0x00000800) /* Bit 1 */ + +/******************************************************************************/ +/* DVP */ +/******************************************************************************/ + +/******************* Bit definition for DVP_CR0 register ********************/ +#define RB_DVP_ENABLE 0x01 // RW, DVP enable +#define RB_DVP_V_POLAR 0x02 // RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_H_POLAR 0x04 // RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_P_POLAR 0x08 // RW, DVP PCLK polarity control: 1 = invert, 0 = not invert +#define RB_DVP_MSK_DAT_MOD 0x30 +#define RB_DVP_D8_MOD 0x00 // RW, DVP 8bits data mode +#define RB_DVP_D10_MOD 0x10 // RW, DVP 10bits data mode +#define RB_DVP_D12_MOD 0x20 // RW, DVP 12bits data mode +#define RB_DVP_JPEG 0x40 // RW, DVP JPEG mode + +/******************* Bit definition for DVP_CR1 register ********************/ +#define RB_DVP_DMA_EN 0x01 // RW, DVP dma enable +#define RB_DVP_ALL_CLR 0x02 // RW, DVP all clear, high action +#define RB_DVP_RCV_CLR 0x04 // RW, DVP receive logic clear, high action +#define RB_DVP_BUF_TOG 0x08 // RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0 +#define RB_DVP_CM 0x10 // RW, DVP capture mode +#define RB_DVP_CROP 0x20 // RW, DVP Crop feature enable +#define RB_DVP_FCRC 0xC0 // RW, DVP frame capture rate control: +#define DVP_RATE_100P 0x00 //00 = every frame captured (100%) +#define DVP_RATE_50P 0x40 //01 = every alternate frame captured (50%) +#define DVP_RATE_25P 0x80 //10 = one frame in four frame captured (25%) + +/******************* Bit definition for DVP_IER register ********************/ +#define RB_DVP_IE_STR_FRM 0x01 // RW, DVP frame start interrupt enable +#define RB_DVP_IE_ROW_DONE 0x02 // RW, DVP row received done interrupt enable +#define RB_DVP_IE_FRM_DONE 0x04 // RW, DVP frame received done interrupt enable +#define RB_DVP_IE_FIFO_OV 0x08 // RW, DVP receive fifo overflow interrupt enable +#define RB_DVP_IE_STP_FRM 0x10 // RW, DVP frame stop interrupt enable + +/******************* Bit definition for DVP_IFR register ********************/ +#define RB_DVP_IF_STR_FRM 0x01 // RW1, interrupt flag for DVP frame start +#define RB_DVP_IF_ROW_DONE 0x02 // RW1, interrupt flag for DVP row receive done +#define RB_DVP_IF_FRM_DONE 0x04 // RW1, interrupt flag for DVP frame receive done +#define RB_DVP_IF_FIFO_OV 0x08 // RW1, interrupt flag for DVP receive fifo overflow +#define RB_DVP_IF_STP_FRM 0x10 // RW1, interrupt flag for DVP frame stop + +/******************* Bit definition for DVP_STATUS register ********************/ +#define RB_DVP_FIFO_RDY 0x01 // RO, DVP receive fifo ready +#define RB_DVP_FIFO_FULL 0x02 // RO, DVP receive fifo full +#define RB_DVP_FIFO_OV 0x04 // RO, DVP receive fifo overflow +#define RB_DVP_MSK_FIFO_CNT 0x70 // RO, DVP receive fifo count + + +/******************************************************************************/ +/* ETH10M */ +/******************************************************************************/ +/* ETH register */ +#define R8_ETH_EIE (*((volatile uint8_t *)(0x40028000+3))) /* Interrupt Enable Register */ +#define RB_ETH_EIE_INTIE 0x80 /* RW interrupt enable*/ +#define RB_ETH_EIE_RXIE 0x40 /* RW Receive complete interrupt enable */ +#define RB_ETH_EIE_LINKIE 0x10 /* RW Link Change Interrupt Enable */ +#define RB_ETH_EIE_TXIE 0x08 /* RW send complete interrupt enable */ +#define RB_ETH_EIE_R_EN50 0x04 /* RW TX 50�� resistor adjustment. 1: On-chip 50�� connected 0: On-chip 50�� disconnected */ +#define RB_ETH_EIE_TXERIE 0x02 /* RW Transmit Error Interrupt Enable */ +#define RB_ETH_EIE_RXERIE 0x01 /* RW1 receive error flag */ +#define R8_ETH_EIR (*((volatile uint8_t *)(0x40028000+4))) /* Interrupt Flag Register */ +#define RB_ETH_EIR_RXIF 0x40 /* RW1 Receive complete flag */ +#define RB_ETH_EIR_LINKIF 0x10 /* RW1 Link Change Flag */ +#define RB_ETH_EIR_TXIF 0x08 /* RW1 Link Change Flag */ +#define RB_ETH_EIR_TXERIF 0x02 /* RW1 send error flag */ +#define RB_ETH_EIR_RXERIF 0x01 /* RW1 receive error flag */ +#define R8_ETH_ESTAT (*((volatile uint8_t *)(0x40028000+5))) /* status register */ +#define RB_ETH_ESTAT_INT 0x80 /* RW1 interrupt */ +#define RB_ETH_ESTAT_BUFER 0x40 /* RW1 Buffer error */ +#define RB_ETH_ESTAT_RXCRCER 0x20 /* RO receive crc error */ +#define RB_ETH_ESTAT_RXNIBBLE 0x10 /* RO receives nibble error */ +#define RB_ETH_ESTAT_RXMORE 0x08 /* RO receives more than maximum packets */ +#define RB_ETH_ESTAT_RXBUSY 0x04 /* RO receive busy */ +#define RB_ETH_ESTAT_TXABRT 0x02 /* RO send interrupted by mcu */ +#define R8_ETH_ECON2 (*((volatile uint8_t *)(0x40028000+6))) /* ETH PHY Analog Block Control Register */ +#define RB_ETH_ECON2_RX 0x0E /* 011b must be written */ +#define RB_ETH_ECON2_TX 0x01 +#define RB_ETH_ECON2_MUST 0x06 /* 011b must be written */ +#define R8_ETH_ECON1 (*((volatile uint8_t *)(0x40028000+7))) /* Transceiver Control Register */ +#define RB_ETH_ECON1_TXRST 0x80 /* RW Send module reset */ +#define RB_ETH_ECON1_RXRST 0x40 /* RW Receiver module reset */ +#define RB_ETH_ECON1_TXRTS 0x08 /* RW The transmission starts, and it is automatically cleared after the transmission is completed. */ +#define RB_ETH_ECON1_RXEN 0x04 /* RW Receive is enabled, when cleared, the error flag RXERIF will change to 1 if it is receiving */ + +#define R32_ETH_TX (*((volatile uint32_t *)(0x40028000+8))) /* send control */ +#define R16_ETH_ETXST (*((volatile uint16_t *)(0x40028000+8))) /* RW Send DMA buffer start address */ +#define R16_ETH_ETXLN (*((volatile uint16_t *)(0x40028000+0xA))) /* RW send length */ +#define R32_ETH_RX (*((volatile uint32_t *)(0x40028000+0xC))) /* receive control */ +#define R16_ETH_ERXST (*((volatile uint16_t *)(0x40028000+0xC))) /* RW Receive DMA buffer start address */ +#define R16_ETH_ERXLN (*((volatile uint16_t *)(0x40028000+0xE))) /* RO receive length */ + +#define R32_ETH_HTL (*((volatile uint32_t *)(0x40028000+0x10))) +#define R8_ETH_EHT0 (*((volatile uint8_t *)(0x40028000+0x10))) /* RW Hash Table Byte0 */ +#define R8_ETH_EHT1 (*((volatile uint8_t *)(0x40028000+0x11))) /* RW Hash Table Byte1 */ +#define R8_ETH_EHT2 (*((volatile uint8_t *)(0x40028000+0x12))) /* RW Hash Table Byte2 */ +#define R8_ETH_EHT3 (*((volatile uint8_t *)(0x40028000+0x13))) /* RW Hash Table Byte3 */ +#define R32_ETH_HTH (*((volatile uint32_t *)(0x40028000+0x14))) +#define R8_ETH_EHT4 (*((volatile uint8_t *)(0x40028000+0x14))) /* RW Hash Table Byte4 */ +#define R8_ETH_EHT5 (*((volatile uint8_t *)(0x40028000+0x15))) /* RW Hash Table Byte5 */ +#define R8_ETH_EHT6 (*((volatile uint8_t *)(0x40028000+0x16))) /* RW Hash Table Byte6 */ +#define R8_ETH_EHT7 (*((volatile uint8_t *)(0x40028000+0x17))) /* RW Hash Table Byte7 */ + +#define R32_ETH_MACON (*((volatile uint32_t *)(0x40028000+0x18))) +#define R8_ETH_ERXFCON (*((volatile uint8_t *)(0x40028000+0x18))) /* Received Packet Filtering Control Register */ +/* RW 0=Do not enable this filter condition, 1=When ANDOR=1, +target address mismatch will be filtered, when ANDOR=0, target address match will be accepted */ +#define RB_ETH_ERXFCON_UCEN 0x80 +#define RB_ETH_ERXFCON_CRCEN 0x20 +#define RB_ETH_ERXFCON_EN 0x10 +#define RB_ETH_ERXFCON_MPEN 0x08 +#define RB_ETH_ERXFCON_HTEN 0x04 +#define RB_ETH_ERXFCON_MCEN 0x02 +#define RB_ETH_ERXFCON_BCEN 0x01 +#define R8_ETH_MACON1 (*((volatile uint8_t *)(0x40028000+0x19))) /* Mac flow control registers */ +/* RW When FULDPX=0 is invalid, when FULDPX=1, 11=send 0 timer pause frame, +then stop sending, 10=send pause frame periodically, 01=send pause frame once, then stop sending, 00=stop sending pause frame */ +#define RB_ETH_MACON1_FCEN 0x30 +#define RB_ETH_MACON1_TXPAUS 0x08 /* RW Send pause frame enable*/ +#define RB_ETH_MACON1_RXPAUS 0x04 /* RW Receive pause frame enable */ +#define RB_ETH_MACON1_PASSALL 0x02 /* RW 1=Unfiltered control frames will be written to the buffer, 0=Control frames will be filtered */ +#define RB_ETH_MACON1_MARXEN 0x01 /* RW MAC layer receive enable */ +#define R8_ETH_MACON2 (*((volatile uint8_t *)(0x40028000+0x1A))) /* Mac Layer Packet Control Register */ +#define RB_ETH_MACON2_PADCFG 0xE0 /* RW Short Packet Padding Settings */ +#define RB_ETH_MACON2_TXCRCEN 0x10 /* RW Send to add crc, if you need to add crc in PADCFG, this position is 1 */ +#define RB_ETH_MACON2_PHDREN 0x08 /* RW Special 4 bytes do not participate in crc check */ +#define RB_ETH_MACON2_HFRMEN 0x04 /* RW Allow jumbo frames */ +#define RB_ETH_MACON2_FULDPX 0x01 /* RW full duplex */ +#define R8_ETH_MABBIPG (*((volatile uint8_t *)(0x40028000+0x1B))) /* Minimum Interpacket Interval Register */ +#define RB_ETH_MABBIPG_MABBIPG 0x7F /* RW Minimum number of bytes between packets */ + +#define R32_ETH_TIM (*((volatile uint32_t *)(0x40028000+0x1C))) +#define R16_ETH_EPAUS (*((volatile uint16_t *)(0x40028000+0x1C))) /* RW Flow Control Pause Frame Time Register */ +#define R16_ETH_MAMXFL (*((volatile uint16_t *)(0x40028000+0x1E))) /* RW Maximum Received Packet Length Register */ +#define R16_ETH_MIRD (*((volatile uint16_t *)(0x40028000+0x20))) /* RW MII read data register */ + +#define R32_ETH_MIWR (*((volatile uint32_t *)(0x40028000+0x24))) +#define R8_ETH_MIREGADR (*((volatile uint8_t *)(0x40028000+0x24))) /* MII address register*/ +#define RB_ETH_MIREGADR_MASK 0x1F /* RW PHY register address mask */ +#define R8_ETH_MISTAT (*((volatile uint8_t *)(0x40028000+0x25))) /* RW PHY register address mask */ +//#define RB_ETH_MIREGADR_MIIWR 0x20 /* WO MII write command */ +#define R16_ETH_MIWR (*((volatile uint16_t *)(0x40028000+0x26))) /* WO MII Write Data Register */ +#define R32_ETH_MAADRL (*((volatile uint32_t *)(0x40028000+0x28))) /* RW MAC 1-4 */ +#define R8_ETH_MAADRL1 (*((volatile uint8_t *)(0x40028000+0x28))) /* RW MAC 1 */ +#define R8_ETH_MAADRL2 (*((volatile uint8_t *)(0x40028000+0x29))) /* RW MAC 2 */ +#define R8_ETH_MAADRL3 (*((volatile uint8_t *)(0x40028000+0x2A))) /* RW MAC 3 */ +#define R8_ETH_MAADRL4 (*((volatile uint8_t *)(0x40028000+0x2B))) /* RW MAC 4 */ +#define R16_ETH_MAADRH (*((volatile uint16_t *)(0x40028000+0x2C))) /* RW MAC 5-6 */ +#define R8_ETH_MAADRL5 (*((volatile uint8_t *)(0x40028000+0x2C))) /* RW MAC 4 */ +#define R8_ETH_MAADRL6 (*((volatile uint8_t *)(0x40028000+0x2D))) /* RW MAC 4 */ + +//PHY address +#define PHY_BMCR 0x00 /* Control Register */ +#define PHY_BMSR 0x01 /* Status Register */ +#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisement Register */ +#define PHY_ANLPAR 0x05 /* Auto-Negotiation Link Partner Base Page Ability Register*/ +#define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ +#define PHY_MDIX 0x1e /* Custom MDIX Mode Register */ +//Custom MDIX Mode Register @PHY_MDIX +#define PN_NORMAL 0x04 /* Analog p, n polarity selection */ +#define MDIX_MODE_MASK 0x03 /* mdix settings */ +#define MDIX_MODE_AUTO 0x00 /* */ +#define MDIX_MODE_MDIX 0x01 +#define MDIX_MODE_MDI 0x02 +//ECON2 test mode, to be determined +#define RX_VCM_MODE_0 +#define RX_VCM_MODE_1 +#define RX_VCM_MODE_2 +#define RX_VCM_MODE_3 +//RX reference voltage value setting @RX_REF +#define RX_REF_25mV (0<<2) /* 25mV */ +#define RX_REF_49mV (1<<2) /* 49mV */ +#define RX_REF_74mV (2<<2) /* 74mV */ +#define RX_REF_98mV (3<<2) /* 98mV */ +#define RX_REF_123mV (4<<2) /* 123mV */ +#define RX_REF_148mV (5<<2) /* 148mV */ +#define RX_REF_173mV (6<<2) /* 173mV */ +#define RX_REF_198mV (7<<2) /* 198mV */ +//TX DRIVER Bias Current @TX_AMP +#define TX_AMP_0 (0<<0) /* 43mA / 14.5mA (1.4V/0.7V) */ +#define TX_AMP_1 (1<<0) /* 53.1mA / 18mA (1.8V/0.9V) */ +#define TX_AMP_2 (2<<0) /* 75.6mA / 25.6mA (2.6V/1.3V) */ +#define TX_AMP_3 (3<<0) /* 122mA / 41.45mA (4.1V/2.3V) */ +//FCEN pause frame control @FCEN +#define FCEN_0_TIMER (3<<4) /* Send a 0 timer pause frame, then stop sending */ +#define FCEN_CYCLE (2<<4) /* Periodically send pause frames */ +#define FCEN_ONCE (1<<4) /* Send pause frame once, then stop sending */ +#define FCEN_STOP (0<<4) /* Stop sending pause frames */ +//PADCFG short packet control @PADCFG +#define PADCFG_AUTO_0 (7<<5) /* All short packets are filled with 00h to 64 bytes, then 4 bytes crc */ +#define PADCFG_NO_ACT_0 (6<<5) /* No padding for short packets */ +/* The detected VLAN network packet whose field is 8100h is automatically filled +with 00h to 64 bytes, otherwise the short packet is filled with 60 bytes of 0, and then 4 bytes of crc after filling */ +#define PADCFG_DETE_AUTO (5<<5) +#define PADCFG_NO_ACT_1 (4<<5) /* No padding for short packets */ +#define PADCFG_AUTO_1 (3<<5) /* All short packets are filled with 00h to 64 bytes, then 4 bytes crc */ +#define PADCFG_NO_ACT_2 (2<<5) /* No padding for short packets */ +#define PADCFG_AUTO_3 (1<<5) /* All short packets are filled with 00h to 60 bytes, and then 4 bytes crc */ +#define PADCFG_NO_ACT_3 (0<<5) /* No padding for short packets */ + +/* Bit or field definition for PHY basic status register */ +#define PHY_Linked_Status ((uint16_t)0x0004) /* Valid link established */ + +#define PHY_Reset ((uint16_t)0x8000) /* PHY Reset */ + +#define PHY_AutoNego_Complete ((uint16_t)0x0020) /* Auto-Negotioation process completed */ + +//MII control +#define RB_ETH_MIREGADR_MIIWR 0x20 /* WO MII write command */ +#define RB_ETH_MIREGADR_MIRDL 0x1f /* RW PHY register address */ + + +#include "ch32v20x_conf.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_adc.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_adc.h index 589a8f7..a94bf5d 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_adc.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_adc.h @@ -1,218 +1,220 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_adc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * ADC firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_ADC_H -#define __CH32V20x_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* ADC Init structure definition */ -typedef struct -{ - uint32_t ADC_Mode; /* Configures the ADC to operate in independent or - dual mode. - This parameter can be a value of @ref ADC_mode */ - - FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in - Scan (multichannels) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ - - uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. - This parameter can be a value of @ref ADC_OutputBuffer */ - - uint32_t ADC_Pga; /* Specifies the PGA gain multiple. - This parameter can be a value of @ref ADC_Pga */ -} ADC_InitTypeDef; - -/* ADC_mode */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) -#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) -#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) -#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) -#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) -#define ADC_Mode_RegSimult ((uint32_t)0x00060000) -#define ADC_Mode_FastInterl ((uint32_t)0x00070000) -#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) -#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) - -/* ADC_external_trigger_sources_for_regular_channels_conversion */ -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) - -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) - -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) - -/* ADC_data_align */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) - -/* ADC_channels */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) - -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) - -/*ADC_output_buffer*/ -#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) -#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) - -/*ADC_pga*/ -#define ADC_Pga_1 ((uint32_t)0x00000000) -#define ADC_Pga_4 ((uint32_t)0x08000000) -#define ADC_Pga_16 ((uint32_t)0x10000000) -#define ADC_Pga_64 ((uint32_t)0x18000000) - -/* ADC_sampling_time */ -#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) -#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) -#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) -#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) -#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) -#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) -#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) -#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) - -/* ADC_external_trigger_sources_for_injected_channels_conversion */ -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) -#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) - -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) - -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) - -/* ADC_injected_channel_selection */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) - -/* ADC_analog_watchdog_selection */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -/* ADC_interrupts_definition */ -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) - -/* ADC_flags_definition */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) - -void ADC_DeInit(ADC_TypeDef *ADCx); -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); -void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); -void ADC_ResetCalibration(ADC_TypeDef *ADCx); -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); -void ADC_StartCalibration(ADC_TypeDef *ADCx); -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); -void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); -uint32_t ADC_GetDualModeConversionValue(void); -void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); -void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); -void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); -s32 TempSensor_Volt_To_Temper(s32 Value); -void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -int16_t Get_CalibrationValue(ADC_TypeDef *ADCx); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_adc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the + * ADC firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_ADC_H +#define __CH32V20x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ + + uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. + This parameter can be a value of @ref ADC_OutputBuffer */ + + uint32_t ADC_Pga; /* Specifies the PGA gain multiple. + This parameter can be a value of @ref ADC_Pga */ +} ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +/*ADC_output_buffer*/ +#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) +#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) + +/*ADC_pga*/ +#define ADC_Pga_1 ((uint32_t)0x00000000) +#define ADC_Pga_4 ((uint32_t)0x08000000) +#define ADC_Pga_16 ((uint32_t)0x10000000) +#define ADC_Pga_64 ((uint32_t)0x18000000) + +/* ADC_sampling_time */ +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +void ADC_DeInit(ADC_TypeDef *ADCx); +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_StartCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); +s32 TempSensor_Volt_To_Temper(s32 Value); +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_bkp.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_bkp.h index 37b2b65..f2a8c21 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_bkp.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_bkp.h @@ -1,91 +1,93 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_bkp.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * BKP firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_BKP_H -#define __CH32V20x_BKP_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* Tamper_Pin_active_level */ -#define BKP_TamperPinLevel_High ((uint16_t)0x0000) -#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) - -/* RTC_output_source_to_output_on_the_Tamper_pin */ -#define BKP_RTCOutputSource_None ((uint16_t)0x0000) -#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) -#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) -#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) - -/* Data_Backup_Register */ -#define BKP_DR1 ((uint16_t)0x0004) -#define BKP_DR2 ((uint16_t)0x0008) -#define BKP_DR3 ((uint16_t)0x000C) -#define BKP_DR4 ((uint16_t)0x0010) -#define BKP_DR5 ((uint16_t)0x0014) -#define BKP_DR6 ((uint16_t)0x0018) -#define BKP_DR7 ((uint16_t)0x001C) -#define BKP_DR8 ((uint16_t)0x0020) -#define BKP_DR9 ((uint16_t)0x0024) -#define BKP_DR10 ((uint16_t)0x0028) -#define BKP_DR11 ((uint16_t)0x0040) -#define BKP_DR12 ((uint16_t)0x0044) -#define BKP_DR13 ((uint16_t)0x0048) -#define BKP_DR14 ((uint16_t)0x004C) -#define BKP_DR15 ((uint16_t)0x0050) -#define BKP_DR16 ((uint16_t)0x0054) -#define BKP_DR17 ((uint16_t)0x0058) -#define BKP_DR18 ((uint16_t)0x005C) -#define BKP_DR19 ((uint16_t)0x0060) -#define BKP_DR20 ((uint16_t)0x0064) -#define BKP_DR21 ((uint16_t)0x0068) -#define BKP_DR22 ((uint16_t)0x006C) -#define BKP_DR23 ((uint16_t)0x0070) -#define BKP_DR24 ((uint16_t)0x0074) -#define BKP_DR25 ((uint16_t)0x0078) -#define BKP_DR26 ((uint16_t)0x007C) -#define BKP_DR27 ((uint16_t)0x0080) -#define BKP_DR28 ((uint16_t)0x0084) -#define BKP_DR29 ((uint16_t)0x0088) -#define BKP_DR30 ((uint16_t)0x008C) -#define BKP_DR31 ((uint16_t)0x0090) -#define BKP_DR32 ((uint16_t)0x0094) -#define BKP_DR33 ((uint16_t)0x0098) -#define BKP_DR34 ((uint16_t)0x009C) -#define BKP_DR35 ((uint16_t)0x00A0) -#define BKP_DR36 ((uint16_t)0x00A4) -#define BKP_DR37 ((uint16_t)0x00A8) -#define BKP_DR38 ((uint16_t)0x00AC) -#define BKP_DR39 ((uint16_t)0x00B0) -#define BKP_DR40 ((uint16_t)0x00B4) -#define BKP_DR41 ((uint16_t)0x00B8) -#define BKP_DR42 ((uint16_t)0x00BC) - -void BKP_DeInit(void); -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); -void BKP_TamperPinCmd(FunctionalState NewState); -void BKP_ITConfig(FunctionalState NewState); -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); -FlagStatus BKP_GetFlagStatus(void); -void BKP_ClearFlag(void); -ITStatus BKP_GetITStatus(void); -void BKP_ClearITPendingBit(void); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_bkp.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the + * BKP firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_BKP_H +#define __CH32V20x_BKP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* Tamper_Pin_active_level */ +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) + +/* RTC_output_source_to_output_on_the_Tamper_pin */ +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) + +/* Data_Backup_Register */ +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_can.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_can.h index fbf1138..799ad54 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_can.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_can.h @@ -1,358 +1,369 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_can.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * CAN firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_CAN_H -#define __CH32V20x_CAN_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* CAN init structure definition */ -typedef struct -{ - uint16_t CAN_Prescaler; /* Specifies the length of a time quantum. - It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /* Specifies the CAN operating mode. - This parameter can be a value of - @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /* Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of - @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit - Segment 2. - This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /* Enable or disable the time triggered - communication mode. This parameter can be set - either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off - management. This parameter can be set either - to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or - DISABLE. */ - - FunctionalState CAN_NART; /* Enable or disable the no-automatic - retransmission mode. This parameter can be - set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE - or DISABLE. */ - - FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE - or DISABLE. */ -} CAN_InitTypeDef; - -/* CAN filter init structure definition */ -typedef struct -{ - uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /* Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /* Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/* CAN Tx message structure definition */ -typedef struct -{ - uint32_t StdId; /* Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /* Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /* Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /* Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /* Specifies the length of the frame that will be - transmitted. This parameter can be a value between - 0 to 8 */ - - uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ -} CanTxMsg; - -/* CAN Rx message structure definition */ -typedef struct -{ - uint32_t StdId; /* Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /* Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /* Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /* Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /* Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t FMI; /* Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanRxMsg; - -/* CAN_sleep_constants */ -#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */ -#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */ - -/* CAN_Mode */ -#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */ - -/* CAN_Operating_Mode */ -#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */ -#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */ -#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */ - -/* CAN_Mode_Status */ -#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */ -#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */ - -/* CAN_synchronisation_jump_width */ -#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ - -/* CAN_time_quantum_in_bit_segment_1 */ -#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ - -/* CAN_time_quantum_in_bit_segment_2 */ -#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ - -/* CAN_filter_mode */ -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */ - -/* CAN_filter_scale */ -#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */ - -/* CAN_filter_FIFO */ -#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */ -#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */ - -/* CAN_identifier_type */ -#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */ -#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */ - -/* CAN_remote_transmission_request */ -#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */ -#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */ - -/* CAN_transmit_constants */ -#define CAN_TxStatus_Failed ((uint8_t)0x00) /* CAN transmission failed */ -#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */ -#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */ -#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ - -/* CAN_receive_FIFO_number_constants */ -#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */ - -/* CAN_sleep_constants */ -#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */ -#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */ - -/* CAN_wake_up_constants */ -#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */ -#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */ - -/* CAN_Error_Code_constants */ -#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */ -#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */ -#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */ -#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */ -#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */ -#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */ -#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */ -#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */ - -/* CAN_flags */ -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */ - -/* Receive Flags */ -#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */ -#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */ -#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */ - -/* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */ -#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */ - -/* CAN_interrupts */ -#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/ - -/* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/ -#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/ - -/* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/ -#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/ -#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/ -#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/ -#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/ - -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME - -/* CAN_Legacy */ -#define CANINITFAILED CAN_InitStatus_Failed -#define CANINITOK CAN_InitStatus_Success -#define CAN_FilterFIFO0 CAN_Filter_FIFO0 -#define CAN_FilterFIFO1 CAN_Filter_FIFO1 -#define CAN_ID_STD CAN_Id_Standard -#define CAN_ID_EXT CAN_Id_Extended -#define CAN_RTR_DATA CAN_RTR_Data -#define CAN_RTR_REMOTE CAN_RTR_Remote -#define CANTXFAILE CAN_TxStatus_Failed -#define CANTXOK CAN_TxStatus_Ok -#define CANTXPENDING CAN_TxStatus_Pending -#define CAN_NO_MB CAN_TxStatus_NoMailBox -#define CANSLEEPFAILED CAN_Sleep_Failed -#define CANSLEEPOK CAN_Sleep_Ok -#define CANWAKEUPFAILED CAN_WakeUp_Failed -#define CANWAKEUPOK CAN_WakeUp_Ok - -void CAN_DeInit(CAN_TypeDef *CANx); -uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState); -void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState); -uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox); -void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage); -void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber); -uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode); -uint8_t CAN_Sleep(CAN_TypeDef *CANx); -uint8_t CAN_WakeUp(CAN_TypeDef *CANx); -uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx); -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx); -void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_can.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the + * CAN firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_CAN_H +#define __CH32V20x_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* CAN init structure definition */ +typedef struct +{ + uint16_t CAN_Prescaler; /* Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /* Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /* Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /* Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CAN_NART; /* Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitTypeDef; + +/* CAN filter init structure definition */ +typedef struct +{ + uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /* Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /* Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/* CAN Tx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/* CAN Rx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /* Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/* CAN_sleep_constants */ +#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */ + +/* CAN_Mode */ +#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */ + +/* CAN_Operating_Mode */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */ + +/* CAN_Mode_Status */ +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */ + +/* CAN_synchronisation_jump_width */ +#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ + +/* CAN_time_quantum_in_bit_segment_1 */ +#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_time_quantum_in_bit_segment_2 */ +#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ + +/* CAN_filter_mode */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */ + +/* CAN_filter_scale */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */ + +/* CAN_filter_FIFO */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */ + +/* CAN_identifier_type */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */ + +/* CAN_remote_transmission_request */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */ + +/* CAN_transmit_constants */ +#define CAN_TxStatus_Failed ((uint8_t)0x00) /* CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ + +/* CAN_receive_FIFO_number_constants */ +#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */ + +/* CAN_sleep_constants */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */ + +/* CAN_wake_up_constants */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */ + +/* CAN_Error_Code_constants */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */ + +/* CAN_flags */ +/* Transmit Flags */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + * and CAN_ClearFlag() functions. + * If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. +*/ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */ +/* Note: + *When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + *In this case the SLAK bit can be polled. +*/ + + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */ + +/* CAN_interrupts */ +#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + +/* CAN_Legacy */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok + +void CAN_DeInit(CAN_TypeDef *CANx); +uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState); +uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox); +void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage); +void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber); +uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef *CANx); +uint8_t CAN_WakeUp(CAN_TypeDef *CANx); +uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx); +void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_crc.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_crc.h index dcd9bb3..7e76b23 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_crc.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_crc.h @@ -1,31 +1,33 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_crc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * CRC firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_CRC_H -#define __CH32V20x_CRC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_crc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the + * CRC firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_CRC_H +#define __CH32V20x_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_dbgmcu.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_dbgmcu.h index 6272c78..609f1a2 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_dbgmcu.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_dbgmcu.h @@ -1,50 +1,52 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_dbgmcu.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * DBGMCU firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_DBGMCU_H -#define __CH32V20x_DBGMCU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) -#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) -#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) -#define DBGMCU_TIM5_STOP ((uint32_t)0x00010000) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00020000) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00040000) -#define DBGMCU_TIM8_STOP ((uint32_t)0x00080000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) -#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) -#define DBGMCU_TIM9_STOP ((uint32_t)0x00400000) -#define DBGMCU_TIM10_STOP ((uint32_t)0x00800000) - -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -uint32_t __get_DEBUG_CR(void); -void __set_DEBUG_CR(uint32_t value); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_dbgmcu.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the + * DBGMCU firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_DBGMCU_H +#define __CH32V20x_DBGMCU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00010000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00080000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) +#define DBGMCU_TIM9_STOP ((uint32_t)0x00400000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x00800000) + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +uint32_t __get_DEBUG_CR(void); +void __set_DEBUG_CR(uint32_t value); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +uint32_t DBGMCU_GetCHIPID( void ); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_dma.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_dma.h index 29f40f2..a33e793 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_dma.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_dma.h @@ -1,182 +1,184 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_dma.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * DMA firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_DMA_H -#define __CH32V20x_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* DMA Init structure definition */ -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode. - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -} DMA_InitTypeDef; - -/* DMA_data_transfer_direction */ -#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) - -/* DMA_peripheral_incremented_mode */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) - -/* DMA_memory_incremented_mode */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) - -/* DMA_peripheral_data_size */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) - -/* DMA_memory_data_size */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) - -/* DMA_circular_normal_mode */ -#define DMA_Mode_Circular ((uint32_t)0x00000020) -#define DMA_Mode_Normal ((uint32_t)0x00000000) - -/* DMA_priority_level */ -#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) -#define DMA_Priority_High ((uint32_t)0x00002000) -#define DMA_Priority_Medium ((uint32_t)0x00001000) -#define DMA_Priority_Low ((uint32_t)0x00000000) - -/* DMA_memory_to_memory */ -#define DMA_M2M_Enable ((uint32_t)0x00004000) -#define DMA_M2M_Disable ((uint32_t)0x00000000) - -/* DMA_interrupts_definition */ -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) - -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) -#define DMA1_IT_GL8 ((uint32_t)0x10000000) -#define DMA1_IT_TC8 ((uint32_t)0x20000000) -#define DMA1_IT_HT8 ((uint32_t)0x40000000) -#define DMA1_IT_TE8 ((uint32_t)0x80000000) - -/* DMA_flags_definition */ -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) -#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) -#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) -#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) -#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) - -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); -void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); -void DMA_ClearFlag(uint32_t DMAy_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMAy_IT); -void DMA_ClearITPendingBit(uint32_t DMAy_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_dma.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the + * DMA firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_DMA_H +#define __CH32V20x_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) +#define DMA1_IT_GL8 ((uint32_t)0x10000000) +#define DMA1_IT_TC8 ((uint32_t)0x20000000) +#define DMA1_IT_HT8 ((uint32_t)0x40000000) +#define DMA1_IT_TE8 ((uint32_t)0x80000000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) + +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_exti.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_exti.h index bc0f159..8d3610f 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_exti.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_exti.h @@ -1,93 +1,95 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_exti.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * EXTI firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_EXTI_H -#define __CH32V20x_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* EXTI mode enumeration */ -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -} EXTIMode_TypeDef; - -/* EXTI Trigger enumeration */ -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -} EXTITrigger_TypeDef; - -/* EXTI Init Structure definition */ -typedef struct -{ - uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -} EXTI_InitTypeDef; - -/* EXTI_Lines */ -#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD Device \ - Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */ -#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */ - -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) - #define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the OSCCAL Wakeup event */ - -#endif - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_exti.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the + * EXTI firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_EXTI_H +#define __CH32V20x_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitTypeDef; + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD Device \ + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */ + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) + #define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the OSCCAL Wakeup event */ + +#endif + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_flash.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_flash.h index 7a4ed15..bb0e485 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_flash.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_flash.h @@ -1,142 +1,148 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_flash.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the FLASH - * firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_FLASH_H -#define __CH32V20x_FLASH_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* FLASH Status */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT -} FLASH_Status; - -/* Write Protect */ -#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */ - -#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ - -/* Option_Bytes_IWatchdog */ -#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ -#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ - -/* Option_Bytes_nRST_STOP */ -#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ - -/* Option_Bytes_nRST_STDBY */ -#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ - -/* FLASH_Interrupts */ -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ - -/* FLASH_Flags */ -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ - -/* FLASH_Access_CLK */ -#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Enhance Clock = SYSTEM */ -#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* Enhance_CLK = SYSTEM/2 */ - -/*Functions used for all devices*/ -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors); -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); -uint32_t FLASH_GetUserOptionByte(void); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); -void FLASH_Unlock_Fast(void); -void FLASH_Lock_Fast(void); -void FLASH_ErasePage_Fast(uint32_t Page_Address); -void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); -void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address); -void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf); -void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK); -void FLASH_Enhance_Mode(FunctionalState NewState); - -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -void FLASH_GetMACAddress(uint8_t *Buffer); -#endif - -/* New function used for all devices */ -void FLASH_UnlockBank1(void); -void FLASH_LockBank1(void); -FLASH_Status FLASH_EraseAllBank1Pages(void); -FLASH_Status FLASH_GetBank1Status(void); -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_flash.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the FLASH + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_FLASH_H +#define __CH32V20x_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; + +/* Write Protect */ +#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 1 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 2 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 3 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 4 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 5 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 6 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 7 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 8 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 9 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 10 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 11 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 12 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 13 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 14 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 15 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 16 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 17 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 18 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 19 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 20 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 21 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 22 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 23 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 24 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 25 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 26 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 27 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 28 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 29 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 30 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 31 to 127 */ + +#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/* FLASH_Access_CLK */ +#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Enhance Clock = SYSTEM */ +#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* Enhance_CLK = SYSTEM/2 */ + +/*Functions used for all devices*/ +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf); +void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK); +void FLASH_Enhance_Mode(FunctionalState NewState); + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +void FLASH_GetMACAddress(uint8_t *Buffer); +#endif + +/* New function used for all devices */ +void FLASH_UnlockBank1(void); +void FLASH_LockBank1(void); +FLASH_Status FLASH_EraseAllBank1Pages(void); +FLASH_Status FLASH_GetBank1Status(void); +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_gpio.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_gpio.h index 2767cae..edc566e 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_gpio.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_gpio.h @@ -1,189 +1,191 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_gpio.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * GPIO firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_GPIO_H -#define __CH32V20x_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* Output Maximum frequency selection */ -typedef enum -{ - GPIO_Speed_10MHz = 1, - GPIO_Speed_2MHz, - GPIO_Speed_50MHz -} GPIOSpeed_TypeDef; - -/* Configuration Mode enumeration */ -typedef enum -{ - GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 -} GPIOMode_TypeDef; - -/* GPIO Init structure definition */ -typedef struct -{ - uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -} GPIO_InitTypeDef; - -/* Bit_SET and Bit_RESET enumeration */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -} BitAction; - -/* GPIO_pins_define */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - -/* GPIO_Remap_define */ -/* PCFR1 */ -#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ -#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ -#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */ -#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ -#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ -#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ -#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ -#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ -#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ -#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ -#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */ -#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */ -#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */ -#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ -#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */ -#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ -#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ -#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \ - to TIM2 Internal Trigger 1 for calibration \ - (only for Connectivity line devices) */ -#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ - -/* PCFR2 */ -#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */ -#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */ -#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */ -#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */ -#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */ -#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */ -#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */ -#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */ -#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */ - -/* GPIO_Port_Sources */ -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOB ((uint8_t)0x01) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) -#define GPIO_PortSourceGPIOD ((uint8_t)0x03) -#define GPIO_PortSourceGPIOE ((uint8_t)0x04) -#define GPIO_PortSourceGPIOF ((uint8_t)0x05) -#define GPIO_PortSourceGPIOG ((uint8_t)0x06) - -/* GPIO_Pin_sources */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -/* Ethernet_Media_Interface */ -#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) -#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) - -void GPIO_DeInit(GPIO_TypeDef *GPIOx); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_EventOutputCmd(FunctionalState NewState); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_gpio.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/07/23 + * Description : This file contains all the functions prototypes for the + * GPIO firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_GPIO_H +#define __CH32V20x_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; + +/* Configuration Mode enumeration */ +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +} GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +/* PCFR1 */ +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD0PD1 ((uint32_t)0x00008000) /* PD0 and PD1 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */ +#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */ +#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \ + to TIM2 Internal Trigger 1 for calibration \ + (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ +#define GPIO_Remap_PD01 GPIO_Remap_PD0PD1 + +/* PCFR2 */ +#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */ +#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */ +#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */ +#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */ +#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */ + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +/* Ethernet_Media_Interface */ +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) + +void GPIO_DeInit(GPIO_TypeDef *GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); +void GPIO_IPD_Unused(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_i2c.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_i2c.h index 2da137d..e1f8300 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_i2c.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_i2c.h @@ -1,199 +1,429 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_i2c.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * I2C firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_I2C_H -#define __CH32V20x_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* I2C Init structure definition */ -typedef struct -{ - uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /* Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /* Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /* Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -} I2C_InitTypeDef; - -/* I2C_mode */ -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) - -/* I2C_duty_cycle_in_fast_mode */ -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ - -/* I2C_acknowledgement */ -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) - -/* I2C_transfer_direction */ -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) - -/* I2C_acknowledged_address */ -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) - -/* I2C_registers */ -#define I2C_Register_CTLR1 ((uint8_t)0x00) -#define I2C_Register_CTLR2 ((uint8_t)0x04) -#define I2C_Register_OADDR1 ((uint8_t)0x08) -#define I2C_Register_OADDR2 ((uint8_t)0x0C) -#define I2C_Register_DATAR ((uint8_t)0x10) -#define I2C_Register_STAR1 ((uint8_t)0x14) -#define I2C_Register_STAR2 ((uint8_t)0x18) -#define I2C_Register_CKCFGR ((uint8_t)0x1C) -#define I2C_Register_RTR ((uint8_t)0x20) - -/* I2C_SMBus_alert_pin_level */ -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) - -/* I2C_PEC_position */ -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) - -/* I2C_NACK_position */ -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) - -/* I2C_interrupts_definition */ -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) - -/* I2C_interrupts_definition */ -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -/* SR2 register flags */ -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/* SR1 register flags */ -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -/****************I2C Master Events (Events grouped in order of communication)********************/ - -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - -/******************I2C Slave Events (Events grouped in order of communication)******************/ - -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -void I2C_DeInit(I2C_TypeDef *I2Cx); -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); -void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); -void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert); -void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); -void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); - -/**************************************************************************************** - * I2C State Monitoring Functions - ****************************************************************************************/ - -ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT); -uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx); -FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); - -void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_i2c.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the + * I2C firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_I2C_H +#define __CH32V20x_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef *I2Cx); +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); + + +/***************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * profit the application requirements and constraints: + * + * + * a) First way: + * Using I2C_CheckEvent() function: + * It compares the status registers (STARR1 and STAR2) content to a given event + * (can be the combination of more flags). + * If the current status registers includes the given flags will return SUCCESS. + * and if the current status registers miss flags will returns ERROR. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (CH32FV2x-V3xRM). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs besides to the monitored error, + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * in corrupted state. it is suggeted to use error interrupts to monitor the error + * events and handle them in IRQ handler. + * + * + * Note: + * The following functions are recommended for error management: : + * - I2C_ITConfig() main function of configure and enable the error interrupts. + * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions + * to determine which error occurred. + * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() + * \ I2C_GenerateStop() will be use to clear the error flag and source, + * and return to correct communication status. + * + * + * b) Second way: + * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. + * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). + * - When to use: + * + * - This function is suitable for the same applications above but it + * don't have the limitations of I2C_GetFlagStatus() function . + * The returned value could be compared to events already defined in the + * library (CH32V20x_i2c.h) or to custom values defined by user. + * - This function can be used to monitor the status of multiple flags simultaneously. + * - Contrary to the I2C_CheckEvent () function, this function can choose the time to + * accept the event according to the user's needs (when all event flags are set and + * no other flags are set, or only when the required flags are set) + * + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * c) Third way: + * Using the function I2C_GetFlagStatus() get the status of + * one single flag . + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed . + * + * - Limitations: + * - Call this function to access the status register. Some flag bits may be cleared. + * - Function may need to be called twice or more in order to monitor one single event. + */ + + + +/********************************************************* + * + * a) Basic state monitoring(First way) + ******************************************************** + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/********************************************************* + * + * b) Advanced state monitoring(Second way:) + ******************************************************** + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/********************************************************* + * + * c) Flag-based state monitoring(Third way) + ********************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_iwdg.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_iwdg.h index 0574536..4da2f03 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_iwdg.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_iwdg.h @@ -1,48 +1,50 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_iwdg.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * IWDG firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_IWDG_H -#define __CH32V20x_IWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* IWDG_WriteAccess */ -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) - -/* IWDG_prescaler */ -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) - -/* IWDG_Flag */ -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) - -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_Enable(void); -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_iwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the + * IWDG firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_IWDG_H +#define __CH32V20x_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_misc.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_misc.h index 39b0bb6..87178f8 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_misc.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_misc.h @@ -1,43 +1,72 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_misc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * miscellaneous firmware library functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_MISC_H -#define __CH32V20x_MISC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* NVIC Init Structure definition */ -typedef struct -{ - uint8_t NVIC_IRQChannel; - uint8_t NVIC_IRQChannelPreemptionPriority; - uint8_t NVIC_IRQChannelSubPriority; - FunctionalState NVIC_IRQChannelCmd; -} NVIC_InitTypeDef; - -/* Preemption_Priority_Group */ -#define NVIC_PriorityGroup_0 ((uint32_t)0x00) -#define NVIC_PriorityGroup_1 ((uint32_t)0x01) -#define NVIC_PriorityGroup_2 ((uint32_t)0x02) -#define NVIC_PriorityGroup_3 ((uint32_t)0x03) -#define NVIC_PriorityGroup_4 ((uint32_t)0x04) - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_misc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the + * miscellaneous firmware library functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_MISC_H +#define __CH32V20x_MISC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* CSR_INTSYSCR_INEST_definition */ +#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ + +/* Check the configuration of CSR(0x804) in the startup file(.S) + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + */ + +#ifndef INTSYSCR_INEST +#define INTSYSCR_INEST INTSYSCR_INEST_EN +#endif + +/* NVIC Init Structure definition + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Preemption_Priority_Group */ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#else +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ +#endif + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_opa.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_opa.h index 336870e..86aa80e 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_opa.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_opa.h @@ -1,72 +1,74 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_opa.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * OPA firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_OPA_H -#define __CH32V20x_OPA_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -#define OPA_PSEL_OFFSET 3 -#define OPA_NSEL_OFFSET 2 -#define OPA_MODE_OFFSET 1 - -/* OPA member enumeration */ -typedef enum -{ - OPA1 = 0, - OPA2, - OPA3, - OPA4 -} OPA_Num_TypeDef; - -/* OPA PSEL enumeration */ -typedef enum -{ - CHP0 = 0, - CHP1 -} OPA_PSEL_TypeDef; - -/* OPA NSEL enumeration */ -typedef enum -{ - CHN0 = 0, - CHN1 -} OPA_NSEL_TypeDef; - -/* OPA out channel enumeration */ -typedef enum -{ - OUT_IO_OUT0 = 0, - OUT_IO_OUT1 -} OPA_Mode_TypeDef; - -/* OPA Init Structure definition */ -typedef struct -{ - OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ - OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ - OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ - OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ -} OPA_InitTypeDef; - -void OPA_DeInit(void); -void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); -void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); -void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_opa.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the + * OPA firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_OPA_H +#define __CH32V20x_OPA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +#define OPA_PSEL_OFFSET 3 +#define OPA_NSEL_OFFSET 2 +#define OPA_MODE_OFFSET 1 + +/* OPA member enumeration */ +typedef enum +{ + OPA1 = 0, + OPA2, + OPA3, + OPA4 +} OPA_Num_TypeDef; + +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0 = 0, + CHP1 +} OPA_PSEL_TypeDef; + +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0 = 0, + CHN1 +} OPA_NSEL_TypeDef; + +/* OPA out channel enumeration */ +typedef enum +{ + OUT_IO_OUT0 = 0, + OUT_IO_OUT1 +} OPA_Mode_TypeDef; + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ +} OPA_InitTypeDef; + +void OPA_DeInit(void); +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_pwr.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_pwr.h index ae8c466..efa8e24 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_pwr.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_pwr.h @@ -1,62 +1,74 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_pwr.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the PWR - * firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_PWR_H -#define __CH32V20x_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* PVD_detection_level */ -#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) -#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) -#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) -#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) -#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) -#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) -#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) -#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) - -/* Regulator_state_is_STOP_mode */ -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower ((uint32_t)0x00000001) - -/* STOP_mode_entry */ -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) - -/* PWR_Flag */ -#define PWR_FLAG_WU ((uint32_t)0x00000001) -#define PWR_FLAG_SB ((uint32_t)0x00000002) -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) - -void PWR_DeInit(void); -void PWR_BackupAccessCmd(FunctionalState NewState); -void PWR_PVDCmd(FunctionalState NewState); -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_WakeUpPinCmd(FunctionalState NewState); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); -void PWR_EnterSTANDBYMode_RAM(void); -void PWR_EnterSTANDBYMode_RAM_LV(void); -void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); -void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); -void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_pwr.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the PWR + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_PWR_H +#define __CH32V20x_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* PVD_detection_level */ + +#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080) +#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0) + +#define PWR_PVDLevel_2V2 PWR_PVDLevel_MODE0 +#define PWR_PVDLevel_2V3 PWR_PVDLevel_MODE1 +#define PWR_PVDLevel_2V4 PWR_PVDLevel_MODE2 +#define PWR_PVDLevel_2V5 PWR_PVDLevel_MODE3 +#define PWR_PVDLevel_2V6 PWR_PVDLevel_MODE4 +#define PWR_PVDLevel_2V7 PWR_PVDLevel_MODE5 +#define PWR_PVDLevel_2V8 PWR_PVDLevel_MODE6 +#define PWR_PVDLevel_2V9 PWR_PVDLevel_MODE7 + +/* Regulator_state_is_STOP_mode */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); +void PWR_EnterSTANDBYMode_RAM(void); +void PWR_EnterSTANDBYMode_RAM_LV(void); +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); +void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_rcc.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_rcc.h index e09d694..ea90b4a 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_rcc.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_rcc.h @@ -1,255 +1,264 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_rcc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the RCC firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_RCC_H -#define __CH32V20x_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* RCC_Exported_Types */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ - uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ -} RCC_ClocksTypeDef; - -/* HSE_configuration */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00010000) -#define RCC_HSE_Bypass ((uint32_t)0x00040000) - -/* PLL_entry_clock_source */ -#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) -#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) -#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) - -/* PLL_multiplication_factor for other CH32V20x */ -#define RCC_PLLMul_2 ((uint32_t)0x00000000) -#define RCC_PLLMul_3 ((uint32_t)0x00040000) -#define RCC_PLLMul_4 ((uint32_t)0x00080000) -#define RCC_PLLMul_5 ((uint32_t)0x000C0000) -#define RCC_PLLMul_6 ((uint32_t)0x00100000) -#define RCC_PLLMul_7 ((uint32_t)0x00140000) -#define RCC_PLLMul_8 ((uint32_t)0x00180000) -#define RCC_PLLMul_9 ((uint32_t)0x001C0000) -#define RCC_PLLMul_10 ((uint32_t)0x00200000) -#define RCC_PLLMul_11 ((uint32_t)0x00240000) -#define RCC_PLLMul_12 ((uint32_t)0x00280000) -#define RCC_PLLMul_13 ((uint32_t)0x002C0000) -#define RCC_PLLMul_14 ((uint32_t)0x00300000) -#define RCC_PLLMul_15 ((uint32_t)0x00340000) -#define RCC_PLLMul_16 ((uint32_t)0x00380000) -#define RCC_PLLMul_18 ((uint32_t)0x003C0000) - -/* System_clock_source */ -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) - -/* AHB_clock_source */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) - -/* APB1_APB2_clock_source */ -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00000400) -#define RCC_HCLK_Div4 ((uint32_t)0x00000500) -#define RCC_HCLK_Div8 ((uint32_t)0x00000600) -#define RCC_HCLK_Div16 ((uint32_t)0x00000700) - -/* RCC_Interrupt_source */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) - -/* USB_Device_clock_source */ -#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x00) -#define RCC_USBCLKSource_PLLCLK_Div2 ((uint8_t)0x01) -#define RCC_USBCLKSource_PLLCLK_Div3 ((uint8_t)0x02) - -#ifdef CH32V20x_D8W - #define RCC_USBCLKSource_PLLCLK_Div5 ((uint8_t)0x03) - -#endif - -/* ADC_clock_source */ -#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) -#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) -#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) -#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) - -/* LSE_configuration */ -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) - -/* RTC_clock_source */ -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) - -/* AHB_peripheral */ -#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) -#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) -#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) -#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) -#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200) -#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) -#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800) -#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) - -#ifdef CH32V20x_D8W -#define RCC_AHBPeriph_BLE_CRC ((uint32_t)0x00030040) -#endif - -/* APB2_peripheral */ -#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) -#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) -#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) - -/* APB1_peripheral */ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040) -#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080) -#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_USB ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) - -/* Clock_source_to_output_on_MCO_pin */ -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) -#define RCC_MCO_HSE ((uint8_t)0x06) -#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) - -/* RCC_Flag */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -/* SysTick_clock_source */ -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) - -/* USBFS_clock_source */ -#define RCC_USBPLL_Div1 ((uint32_t)0x00) -#define RCC_USBPLL_Div2 ((uint32_t)0x01) -#define RCC_USBPLL_Div3 ((uint32_t)0x02) -#define RCC_USBPLL_Div4 ((uint32_t)0x03) -#define RCC_USBPLL_Div5 ((uint32_t)0x04) -#define RCC_USBPLL_Div6 ((uint32_t)0x05) -#define RCC_USBPLL_Div7 ((uint32_t)0x06) -#define RCC_USBPLL_Div8 ((uint32_t)0x07) - -/* ETH_clock_source */ -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) - #define RCC_ETHCLK_Div1 ((uint32_t)0x00) - #define RCC_ETHCLK_Div2 ((uint32_t)0x01) - -#endif - -void RCC_DeInit(void); -void RCC_HSEConfig(uint32_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCO); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); -void RCC_ADCCLKADJcmd(FunctionalState NewState); - -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -void RCC_ETHDIVConfig(uint32_t RCC_ETHPRE_Div); - -#endif - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_rcc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/02/21 + * Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_RCC_H +#define __CH32V20x_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ +} RCC_ClocksTypeDef; + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + +/* PLL_multiplication_factor for other CH32V20x */ +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) +#define RCC_PLLMul_18 ((uint32_t)0x003C0000) + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) + +/* APB1_APB2_clock_source */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +/* USB_Device_clock_source */ +#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x00) +#define RCC_USBCLKSource_PLLCLK_Div2 ((uint8_t)0x01) +#define RCC_USBCLKSource_PLLCLK_Div3 ((uint8_t)0x02) + +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + #define RCC_USBCLKSource_PLLCLK_Div5 ((uint8_t)0x03) + +#endif + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +#define RCC_RTCCLKSource_HSE_Div512 ((uint32_t)0x00000300) +#else +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) +#endif + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) +#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200) +#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) +#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800) +#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000) +#define RCC_AHBPeriph_OTG_FS RCC_AHBPeriph_USBFS + +#ifdef CH32V20x_D8W +#define RCC_AHBPeriph_BLE_CRC ((uint32_t)0x00030040) +#endif + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040) +#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080) +#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +/* USBFS_clock_source */ +#define RCC_USBPLL_Div1 ((uint32_t)0x00) +#define RCC_USBPLL_Div2 ((uint32_t)0x01) +#define RCC_USBPLL_Div3 ((uint32_t)0x02) +#define RCC_USBPLL_Div4 ((uint32_t)0x03) +#define RCC_USBPLL_Div5 ((uint32_t)0x04) +#define RCC_USBPLL_Div6 ((uint32_t)0x05) +#define RCC_USBPLL_Div7 ((uint32_t)0x06) +#define RCC_USBPLL_Div8 ((uint32_t)0x07) + +/* ETH_clock_source */ +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) + #define RCC_ETHCLK_Div1 ((uint32_t)0x00) + #define RCC_ETHCLK_Div2 ((uint32_t)0x01) + +#endif + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); +void RCC_ADCCLKADJcmd(FunctionalState NewState); +FlagStatus RCC_USB5PRE_JUDGE(); + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +void RCC_ETHDIVConfig(uint32_t RCC_ETHPRE_Div); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_rtc.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_rtc.h index 0b32654..4026051 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_rtc.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_rtc.h @@ -1,96 +1,98 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_rtc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the RTC - * firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_RTC_H -#define __CH32V20x_RTC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -typedef enum -{ - Level_32 = 2, - Level_64, - Level_128, - -} Cali_LevelTypeDef; - -/* RTC_interrupts_define */ -#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ -#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ -#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ - -/* RTC_interrupts_flags */ -#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ -#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ -#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ -#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ -#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ - -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -#define RB_OSC32K_HTUNE (0x1FE0) -#define RB_OSC32K_LTUNE (0x1F) - -#define RB_OSC_CAL_HALT (0x80) -#define RB_OSC_CAL_EN (0x02) -#define RB_OSC_CAL_INT_EN (0x01) - -#define RB_OSC_CAL_OV_CNT (0xFF) - -#define RB_OSC_CAL_IF_END (1 << 15) -#define RB_OSC_CAL_CNT_OV (1 << 14) -#define RB_OSC_CAL_CNT (0x3FFF) - -#define RB_CAL_LP_EN (1 << 6) -#define RB_CAL_WKUP_EN (1 << 5) -#define RB_OSC_HALT_MD (1 << 4) -#define RB_OSC_CNT_VLU (0x0F) - - -#ifdef CLK_OSC32K -#if ( CLK_OSC32K == 1 ) -#define CAB_LSIFQ 32000 -#else -#define CAB_LSIFQ 32768 -#endif -#else -#define CAB_LSIFQ 32000 -#endif -#endif - - -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); -void RTC_EnterConfigMode(void); -void RTC_ExitConfigMode(void); -uint32_t RTC_GetCounter(void); -void RTC_SetCounter(uint32_t CounterValue); -void RTC_SetPrescaler(uint32_t PrescalerValue); -void RTC_SetAlarm(uint32_t AlarmValue); -uint32_t RTC_GetDivider(void); -void RTC_WaitForLastTask(void); -void RTC_WaitForSynchro(void); -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); -void RTC_ClearFlag(uint16_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint16_t RTC_IT); -void RTC_ClearITPendingBit(uint16_t RTC_IT); - -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -void Calibration_LSI(Cali_LevelTypeDef cali_Lv); - -#endif - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_rtc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the RTC + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_RTC_H +#define __CH32V20x_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +typedef enum +{ + Level_32 = 2, + Level_64, + Level_128, + +} Cali_LevelTypeDef; + +/* RTC_interrupts_define */ +#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ + +/* RTC_interrupts_flags */ +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +#define RB_OSC32K_HTUNE (0x1FE0) +#define RB_OSC32K_LTUNE (0x1F) + +#define RB_OSC_CAL_HALT (0x80) +#define RB_OSC_CAL_EN (0x02) +#define RB_OSC_CAL_INT_EN (0x01) + +#define RB_OSC_CAL_OV_CNT (0xFF) + +#define RB_OSC_CAL_IF_END (1 << 15) +#define RB_OSC_CAL_CNT_OV (1 << 14) +#define RB_OSC_CAL_CNT (0x3FFF) + +#define RB_CAL_LP_EN (1 << 6) +#define RB_CAL_WKUP_EN (1 << 5) +#define RB_OSC_HALT_MD (1 << 4) +#define RB_OSC_CNT_VLU (0x0F) + + +#ifdef CLK_OSC32K +#if ( CLK_OSC32K == 1 ) +#define CAB_LSIFQ 32000 +#else +#define CAB_LSIFQ 32768 +#endif +#else +#define CAB_LSIFQ 32000 +#endif +#endif + + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +void Calibration_LSI(Cali_LevelTypeDef cali_Lv); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_spi.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_spi.h index dfa5f9e..5912726 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_spi.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_spi.h @@ -1,218 +1,220 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_spi.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * SPI firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_SPI_H -#define __CH32V20x_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* SPI Init structure definition */ -typedef struct -{ - uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /* Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /* Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /* Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ -} SPI_InitTypeDef; - -/* I2S Init structure definition */ -typedef struct -{ - uint16_t I2S_Mode; /* Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -} I2S_InitTypeDef; - -/* SPI_data_direction */ -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) - -/* SPI_mode */ -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) - -/* SPI_data_size */ -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) - -/* SPI_Clock_Polarity */ -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) - -/* SPI_Clock_Phase */ -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) - -/* SPI_Slave_Select_management */ -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) - -/* SPI_BaudRate_Prescaler */ -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) - -/* SPI_MSB_LSB_transmission */ -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) - -/* I2S_Mode */ -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) - -/* I2S_Standard */ -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) - -/* I2S_Data_Format */ -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) - -/* I2S_MCLK_Output */ -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) - -/* I2S_Audio_Frequency */ -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -/* I2S_Clock_Polarity */ -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) - -/* SPI_I2S_DMA_transfer_requests */ -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) - -/* SPI_NSS_internal_software_management */ -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) - -/* SPI_CRC_Transmit_Receive */ -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) - -/* SPI_direction_transmit_receive */ -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) - -/* SPI_I2S_interrupts_definition */ -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) -#define I2S_IT_UDR ((uint8_t)0x53) - -/* SPI_I2S_flags_definition */ -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) - -void SPI_I2S_DeInit(SPI_TypeDef *SPIx); -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); -void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); -void SPI_TransmitCRC(SPI_TypeDef *SPIx); -void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); -void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_spi.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the + * SPI firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_SPI_H +#define __CH32V20x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +} SPI_InitTypeDef; + +/* I2S Init structure definition */ +typedef struct +{ + uint16_t I2S_Mode; /* Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +} I2S_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB_transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* I2S_Mode */ +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) + +/* I2S_Standard */ +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) + +/* I2S_Data_Format */ +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) + +/* I2S_MCLK_Output */ +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) + +/* I2S_Audio_Frequency */ +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +/* I2S_Clock_Polarity */ +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + +void SPI_I2S_DeInit(SPI_TypeDef *SPIx); +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); +void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef *SPIx); +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_tim.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_tim.h index 64821f7..120be5e 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_tim.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_tim.h @@ -1,506 +1,508 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_tim.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * TIM firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_TIM_H -#define __CH32V20x_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* TIM Time Base Init structure definition */ -typedef struct -{ - uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /* Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint16_t TIM_Period; /* Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /* Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/* TIM Output Compare Init structure definition */ -typedef struct -{ - uint16_t TIM_OCMode; /* Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_state - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /* Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/* TIM Input Capture Init structure definition */ -typedef struct -{ - uint16_t TIM_Channel; /* Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /* Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /* Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/* BDTR structure definition */ -typedef struct -{ - uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. - This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. - This parameter can be a value of @ref Lock_level */ - - uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/* TIM_Output_Compare_and_PWM_modes */ -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) - -/* TIM_One_Pulse_Mode */ -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) - -/* TIM_Channel */ -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -/* TIM_Clock_Division_CKD */ -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) - -/* TIM_Counter_Mode */ -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) - -/* TIM_Output_Compare_Polarity */ -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) - -/* TIM_Output_Compare_N_Polarity */ -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) - -/* TIM_Output_Compare_state */ -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) - -/* TIM_Output_Compare_N_state */ -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) - -/* TIM_Capture_Compare_state */ -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) - -/* TIM_Capture_Compare_N_state */ -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) - -/* Break_Input_enable_disable */ -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) - -/* Break_Polarity */ -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) - -/* TIM_AOE_Bit_Set_Reset */ -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) - -/* Lock_level */ -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) - -/* OSSI_Off_State_Selection_for_Idle_mode_state */ -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) - -/* OSSR_Off_State_Selection_for_Run_mode_state */ -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Idle_State */ -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Output_Compare_N_Idle_State */ -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Input_Capture_Polarity */ -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) - -/* TIM_Input_Capture_Selection */ -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ - -/* TIM_Input_Capture_Prescaler */ -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ - -/* TIM_interrupt_sources */ -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) - -/* TIM_DMA_Base_address */ -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) - -/* TIM_DMA_Burst_Length */ -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) - -/* TIM_DMA_sources */ -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) - -/* TIM_External_Trigger_Prescaler */ -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) - -/* TIM_Internal_Trigger_Selection */ -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) - -/* TIM_TIx_External_Clock_Source */ -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/* TIM_External_Trigger_Polarity */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) - -/* TIM_Prescaler_Reload_Mode */ -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) - -/* TIM_Forced_Action */ -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) - -/* TIM_Encoder_Mode */ -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) - -/* TIM_Event_Source */ -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) - -/* TIM_Update_Source */ -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ - or the setting of UG bit, or an update generation \ - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ - -/* TIM_Output_Compare_Preload_State */ -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Fast_State */ -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Clear_State */ -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) - -/* TIM_Trigger_Output_Source */ -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) - -/* TIM_Slave_Mode */ -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) - -/* TIM_Master_Slave_Mode */ -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) - -/* TIM_Flags */ -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) - -/* TIM_Legacy */ -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers - -void TIM_DeInit(TIM_TypeDef *TIMx); -void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); -void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); -void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_InternalClockConfig(TIM_TypeDef *TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); -void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); -void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); -void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); -void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); -void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); -void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); -void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); -void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); -void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); -void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); -void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); -void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); -uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); -uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_tim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_TIM_H +#define __CH32V20x_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef *TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_usart.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_usart.h index 1211381..2bf2a8b 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_usart.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_usart.h @@ -1,185 +1,185 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_usart.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the - * USART firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_USART_H -#define __CH32V20x_USART_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* USART Init Structure definition */ -typedef struct -{ - uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /* Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/* USART Clock Init Structure definition */ -typedef struct -{ - uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* USART_Word_Length */ -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -/* USART_Stop_Bits */ -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) - -/* USART_Parity */ -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) - -/* USART_Mode */ -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) - -/* USART_Hardware_Flow_Control */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) - -/* USART_Clock */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) - -/* USART_Clock_Polarity */ -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) - -/* USART_Clock_Phase */ -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) - -/* USART_Last_Bit */ -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) - -/* USART_Interrupt_definition */ -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) - -#define USART_IT_ORE USART_IT_ORE_ER - -/* USART_DMA_Requests */ -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) - -/* USART_WakeUp_methods */ -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) - -/* USART_LIN_Break_Detection_Length */ -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) - -/* USART_IrDA_Low_Power */ -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) - -/* USART_Flags */ -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) - -void USART_DeInit(USART_TypeDef *USARTx); -void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); -void USART_StructInit(USART_InitTypeDef *USART_InitStruct); -void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); -void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); -void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef *USARTx); -void USART_SendBreak(USART_TypeDef *USARTx); -void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); -void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_usart.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/06 + * Description : This file contains all the functions prototypes for the + * USART firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_USART_H +#define __CH32V20x_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +void USART_DeInit(USART_TypeDef *USARTx); +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); +void USART_StructInit(USART_InitTypeDef *USART_InitStruct); +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef *USARTx); +void USART_SendBreak(USART_TypeDef *USARTx); +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_usb.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_usb.h new file mode 100644 index 0000000..9ebfd17 --- /dev/null +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_usb.h @@ -0,0 +1,528 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_usb.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/30 + * Description : This file contains all the functions prototypes for the USB + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20X_USB_H +#define __CH32V20X_USB_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*******************************************************************************/ +/* Header File */ +#include "stdint.h" + +/*******************************************************************************/ +/* USB Communication Related Macro Definition */ +#ifndef DEFAULT_ENDP0_SIZE +#define DEFAULT_ENDP0_SIZE 8 // default maximum packet size for endpoint 0 +#endif +#ifndef MAX_PACKET_SIZE +#define MAX_PACKET_SIZE 64 // maximum packet size +#endif + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_NYET 0x06 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* Bit Define for USB Request Type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 +#define USB_REQ_TYP_OUT 0x00 +#define USB_REQ_TYP_READ 0x80 +#define USB_REQ_TYP_WRITE 0x00 +#define USB_REQ_TYP_MASK 0x60 +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB Descriptor Type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB Device Class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_IMAGE 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB Hub Class Request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub Class Feature Selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB HID Class Request Code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif + +/* USB UDisk */ +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + + +/*******************************************************************************/ +/* USBFS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBFS_UC_HOST_MODE 0x80 +#define USBFS_UC_LOW_SPEED 0x40 +#define USBFS_UC_DEV_PU_EN 0x20 +#define USBFS_UC_SYS_CTRL_MASK 0x30 +#define USBFS_UC_SYS_CTRL0 0x00 +#define USBFS_UC_SYS_CTRL1 0x10 +#define USBFS_UC_SYS_CTRL2 0x20 +#define USBFS_UC_SYS_CTRL3 0x30 +#define USBFS_UC_INT_BUSY 0x08 +#define USBFS_UC_RESET_SIE 0x04 +#define USBFS_UC_CLR_ALL 0x02 +#define USBFS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBFS_UIE_DEV_NAK 0x40 +#define USBFS_UIE_FIFO_OV 0x10 +#define USBFS_UIE_HST_SOF 0x08 +#define USBFS_UIE_SUSPEND 0x04 +#define USBFS_UIE_TRANSFER 0x02 +#define USBFS_UIE_DETECT 0x01 +#define USBFS_UIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +/* R8_USB_MIS_ST */ +#define USBFS_UMS_SOF_PRES 0x80 +#define USBFS_UMS_SOF_ACT 0x40 +#define USBFS_UMS_SIE_FREE 0x20 +#define USBFS_UMS_R_FIFO_RDY 0x10 +#define USBFS_UMS_BUS_RESET 0x08 +#define USBFS_UMS_SUSPEND 0x04 +#define USBFS_UMS_DM_LEVEL 0x02 +#define USBFS_UMS_DEV_ATTACH 0x01 + +/* R8_USB_INT_FG */ +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* R8_USB_INT_ST */ +#define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +/* R32_USB_OTG_CR */ +#define USBFS_CR_SESS_VTH 0x20 +#define USBFS_CR_VBUS_VTH 0x10 +#define USBFS_CR_OTG_EN 0x08 +#define USBFS_CR_IDPU 0x04 +#define USBFS_CR_CHARGE_VBUS 0x02 +#define USBFS_CR_DISCHAR_VBUS 0x01 + +/* R32_USB_OTG_SR */ +#define USBFS_SR_ID_DIG 0x08 +#define USBFS_SR_SESS_END 0x04 +#define USBFS_SR_SESS_VLD 0x02 +#define USBFS_SR_VBUS_VLD 0x01 + +/* R8_UDEV_CTRL */ +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* R8_UEP4_1_MOD */ +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +#define USBFS_UEP4_BUF_MOD 0x01 + +/* R8_UEP2_3_MOD */ +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* R8_UEP5_6_MOD */ +#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +/* R8_UEP7_MOD */ +#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +/* R8_UEPn_TX_CTRL */ +#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK 0x00 +#define USBFS_UEP_T_RES_NONE 0x01 +#define USBFS_UEP_T_RES_NAK 0x02 +#define USBFS_UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +// host aux setup + +/* R8_UEPn_RX_CTRL, n=0-7 */ +#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK 0x00 +#define USBFS_UEP_R_RES_NONE 0x01 +#define USBFS_UEP_R_RES_NAK 0x02 +#define USBFS_UEP_R_RES_STALL 0x03 +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +/* R8_UHOST_CTRL */ +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +/* R32_UH_EP_MOD */ +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +/* R16_UH_SETUP */ +#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable + +/* R8_UH_EP_PID */ +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + +/* R8_UH_RX_CTRL */ +#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +/* R8_UH_TX_CTRL */ +#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + + +/*******************************************************************************/ +/* Struct Definition */ + +/* USB Setup Request */ +typedef struct __attribute__((packed)) _USB_SETUP_REQ +{ + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + +/* USB Device Descriptor */ +typedef struct __attribute__((packed)) _USB_DEVICE_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + +/* USB Configuration Descriptor */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + +/* USB Interface Descriptor */ +typedef struct __attribute__((packed)) _USB_INTERF_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + +/* USB Endpoint Descriptor */ +typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSizeL; + uint8_t wMaxPacketSizeH; + uint8_t bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + +/* USB Configuration Descriptor Set */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG +{ + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[ 1 ]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + +/* USB HUB Descriptor */ +typedef struct __attribute__((packed)) _USB_HUB_DESCR +{ + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint8_t wHubCharacteristicsL; + uint8_t wHubCharacteristicsH; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + +/* USB HID Descriptor */ +typedef struct __attribute__((packed)) _USB_HID_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bDescriptorTypeX; + uint8_t wDescriptorLengthL; + uint8_t wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CBW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCBW_DataLen; + uint8_t mCBW_Flag; + uint8_t mCBW_LUN; + uint8_t mCBW_CB_Len; + uint8_t mCBW_CB_Buf[ 16 ]; +} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CSW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCSW_Residue; + uint8_t mCSW_Status; +} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; + + +#ifdef __cplusplus +} +#endif + +#endif /*_CH32V20X_USB_H */ diff --git a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_wwdg.h b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_wwdg.h index 5cbcbce..5e6d547 100644 --- a/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_wwdg.h +++ b/system/CH32V20x/SRC/Peripheral/inc/ch32v20x_wwdg.h @@ -1,39 +1,41 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_wwdg.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file contains all the functions prototypes for the WWDG - * firmware library. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_WWDG_H -#define __CH32V20x_WWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v20x.h" - -/* WWDG_Prescaler */ -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) - -void WWDG_DeInit(void); -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); -void WWDG_Enable(uint8_t Counter); -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_wwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains all the functions prototypes for the WWDG + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_WWDG_H +#define __CH32V20x_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v20x.h" + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_adc.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_adc.c index 3d79458..1c99a85 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_adc.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_adc.c @@ -1,1208 +1,1210 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_adc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the ADC firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include "ch32v20x_adc.h" -#include "ch32v20x_rcc.h" - -/* ADC DISCNUM mask */ -#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) -#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) - -/* ADC JAUTO mask */ -#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) -#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) - -/* ADC AWDCH mask */ -#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) - -/* CTLR1 register Mask */ -#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) - -/* ADC ADON mask */ -#define CTLR2_ADON_Set ((uint32_t)0x00000001) -#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CTLR2_DMA_Set ((uint32_t)0x00000100) -#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) - -/* ADC RSTCAL mask */ -#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) - -/* ADC CAL mask */ -#define CTLR2_CAL_Set ((uint32_t)0x00000004) - -/* ADC SWSTART mask */ -#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) - -/* ADC EXTTRIG mask */ -#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) - -/* ADC JEXTSEL mask */ -#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTART mask */ -#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) - -/* ADC TSPD mask */ -#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) -#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) - -/* CTLR2 register Mask */ -#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) - -/* ADC SQx mask */ -#define RSQR3_SQ_Set ((uint32_t)0x0000001F) -#define RSQR2_SQ_Set ((uint32_t)0x0000001F) -#define RSQR1_SQ_Set ((uint32_t)0x0000001F) - -/* RSQR1 register Mask */ -#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define ISQR_JSQ_Set ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define ISQR_JL_Set ((uint32_t)0x00300000) -#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) -#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) - -/* ADC IDATARx registers offset */ -#define IDATAR_Offset ((uint8_t)0x28) - -/* ADC1 RDATAR register base address */ -#define RDATAR_ADDRESS ((uint32_t)0x4001244C) - -/********************************************************************* - * @fn ADC_DeInit - * - * @brief Deinitializes the ADCx peripheral registers to their default - * reset values. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return none - */ -void ADC_DeInit(ADC_TypeDef *ADCx) -{ - if(ADCx == ADC1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); - } - else if(ADCx == ADC2) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); - } -} - -/********************************************************************* - * @fn ADC_Init - * - * @brief Initializes the ADCx peripheral according to the specified - * parameters in the ADC_InitStruct. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | - (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); - ADCx->CTLR1 = tmpreg1; - - tmpreg1 = ADCx->CTLR2; - tmpreg1 &= CTLR2_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - ADCx->CTLR2 = tmpreg1; - - tmpreg1 = ADCx->RSQR1; - tmpreg1 &= RSQR1_CLEAR_Mask; - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); - tmpreg1 |= (uint32_t)tmpreg2 << 20; - ADCx->RSQR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_StructInit - * - * @brief Fills each ADC_InitStruct member with its default value. - * - * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) -{ - ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStruct->ADC_NbrOfChannel = 1; -} - -/********************************************************************* - * @fn ADC_Cmd - * - * @brief Enables or disables the specified ADC peripheral. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_ADON_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_ADON_Reset; - } -} - -/********************************************************************* - * @fn ADC_DMACmd - * - * @brief Enables or disables the specified ADC DMA request. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_DMA_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_DMA_Reset; - } -} - -/********************************************************************* - * @fn ADC_ITConfig - * - * @brief Enables or disables the specified ADC interrupts. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)ADC_IT; - - if(NewState != DISABLE) - { - ADCx->CTLR1 |= itmask; - } - else - { - ADCx->CTLR1 &= (~(uint32_t)itmask); - } -} - -/********************************************************************* - * @fn ADC_ResetCalibration - * - * @brief Resets the selected ADC calibration registers. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return none - */ -void ADC_ResetCalibration(ADC_TypeDef *ADCx) -{ - ADCx->CTLR2 |= CTLR2_RSTCAL_Set; -} - -/********************************************************************* - * @fn ADC_GetResetCalibrationStatus - * - * @brief Gets the selected ADC reset calibration registers status. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_StartCalibration - * - * @brief Starts the selected ADC calibration process. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return None - */ -void ADC_StartCalibration(ADC_TypeDef *ADCx) -{ - ADCx->CTLR2 |= CTLR2_CAL_Set; -} - -/********************************************************************* - * @fn ADC_GetCalibrationStatus - * - * @brief Gets the selected ADC calibration status. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_SoftwareStartConvCmd - * - * @brief Enables or disables the selected ADC software start conversion. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartConvStatus - * - * @brief Gets the selected ADC Software start conversion Status. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return FlagStatus - SET or RESET. - */ - -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_DiscModeChannelCountConfig - * - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * Number - specifies the discontinuous mode regular channel - * count value(1-8). - * - * @return None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_DISCNUM_Reset; - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - ADCx->CTLR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_DiscModeCmd - * - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_DISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_DISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_RegularChannelConfig - * - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_10 - ADC Channel10 selected. - * ADC_Channel_11 - ADC Channel11 selected. - * ADC_Channel_12 - ADC Channel12 selected. - * ADC_Channel_13 - ADC Channel13 selected. - * ADC_Channel_14 - ADC Channel14 selected. - * ADC_Channel_15 - ADC Channel15 selected. - * ADC_Channel_16 - ADC Channel16 selected. - * ADC_Channel_17 - ADC Channel17 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. - * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. - * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. - * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. - * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. - * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. - * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. - * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. - * - * @return None - */ -void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - if(Rank < 7) - { - tmpreg1 = ADCx->RSQR3; - tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - tmpreg1 |= tmpreg2; - ADCx->RSQR3 = tmpreg1; - } - else if(Rank < 13) - { - tmpreg1 = ADCx->RSQR2; - tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - tmpreg1 |= tmpreg2; - ADCx->RSQR2 = tmpreg1; - } - else - { - tmpreg1 = ADCx->RSQR1; - tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - tmpreg1 |= tmpreg2; - ADCx->RSQR1 = tmpreg1; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigConvCmd - * - * @brief Enables or disables the ADCx conversion through external trigger. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetConversionValue - * - * @brief Returns the last ADCx conversion result data for regular channel. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return ADCx->RDATAR - The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) -{ - return (uint16_t)ADCx->RDATAR; -} - -/********************************************************************* - * @fn ADC_GetDualModeConversionValue - * - * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. - * - * @return RDATAR_ADDRESS - The Data conversion value. - */ -uint32_t ADC_GetDualModeConversionValue(void) -{ - return (*(__IO uint32_t *)RDATAR_ADDRESS); -} - -/********************************************************************* - * @fn ADC_AutoInjectedConvCmd - * - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JAUTO_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JAUTO_Reset; - } -} - -/********************************************************************* - * @fn ADC_InjectedDiscModeCmd - * - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JDISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvConfig - * - * @brief Configures the ADCx external trigger for injected channels conversion. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start - * injected conversion. - * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. - * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. - * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. - * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. - * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. - * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. - * ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 - External interrupt - * line 15 event selected. - * ADC_ExternalTrigInjecConv_None: Injected conversion started - * by software and not by external trigger. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR2; - tmpreg &= CTLR2_JEXTSEL_Reset; - tmpreg |= ADC_ExternalTrigInjecConv; - ADCx->CTLR2 = tmpreg; -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvCmd - * - * @brief Enables or disables the ADCx injected channels conversion through - * external trigger. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_SoftwareStartInjectedConvCmd - * - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartInjectedConvCmdStatus - * - * @brief Gets the selected ADC Software start injected conversion Status. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_InjectedChannelConfig - * - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_10 - ADC Channel10 selected. - * ADC_Channel_11 - ADC Channel11 selected. - * ADC_Channel_12 - ADC Channel12 selected. - * ADC_Channel_13 - ADC Channel13 selected. - * ADC_Channel_14 - ADC Channel14 selected. - * ADC_Channel_15 - ADC Channel15 selected. - * ADC_Channel_16 - ADC Channel16 selected. - * ADC_Channel_17 - ADC Channel17 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 4. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. - * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. - * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. - * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. - * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. - * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. - * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. - * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. - * - * @return None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - tmpreg1 = ADCx->ISQR; - tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; - tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 |= tmpreg2; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_InjectedSequencerLengthConfig - * - * @brief Configures the sequencer length for injected channels. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * Length - The sequencer length. - * This parameter must be a number between 1 to 4. - * - * @return None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->ISQR; - tmpreg1 &= ISQR_JL_Reset; - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_SetInjectedOffset - * - * @brief Set the injected channels conversion value offset. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_InjectedChannel: the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * Offset - the offset value for the selected ADC injected channel. - * This parameter must be a 12bit value. - * - * @return None - */ -void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - *(__IO uint32_t *)tmp = (uint32_t)Offset; -} - -/********************************************************************* - * @fn ADC_GetInjectedConversionValue - * - * @brief Returns the ADC injected channel conversion result. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_InjectedChannel - the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * - * @return tmp - The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + IDATAR_Offset; - - return (uint16_t)(*(__IO uint32_t *)tmp); -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogCmd - * - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_AnalogWatchdog - the ADC analog watchdog configuration. - * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a - * single regular channel. - * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a - * single injected channel. - * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog - * on a single regular or injected channel. - * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all - * regular channel. - * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all - * injected channel. - * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on - * all regular and injected channels. - * ADC_AnalogWatchdog_None - No channel guarded by the analog - * watchdog. - * - * @return none - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDMode_Reset; - tmpreg |= ADC_AnalogWatchdog; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogThresholdsConfig - * - * @brief Configures the high and low thresholds of the analog watchdog. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * HighThreshold - the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * LowThreshold - the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * - * @return none - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - ADCx->WDHTR = HighThreshold; - ADCx->WDLTR = LowThreshold; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogSingleChannelConfig - * - * @brief Configures the analog watchdog guarded single channel. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_10 - ADC Channel10 selected. - * ADC_Channel_11 - ADC Channel11 selected. - * ADC_Channel_12 - ADC Channel12 selected. - * ADC_Channel_13 - ADC Channel13 selected. - * ADC_Channel_14 - ADC Channel14 selected. - * ADC_Channel_15 - ADC Channel15 selected. - * ADC_Channel_16 - ADC Channel16 selected. - * ADC_Channel_17 - ADC Channel17 selected. - * - * @return None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDCH_Reset; - tmpreg |= ADC_Channel; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_TempSensorVrefintCmd - * - * @brief Enables or disables the temperature sensor and Vrefint channel. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADC1->CTLR2 |= CTLR2_TSVREFE_Set; - } - else - { - ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetFlagStatus - * - * @brief Checks whether the specified ADC flag is set or not. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to check. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearFlag - * - * @brief Clears the ADCx's pending flags. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to clear. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return none - */ -void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - ADCx->STATR = ~(uint32_t)ADC_FLAG; -} - -/********************************************************************* - * @fn ADC_GetITStatus - * - * @brief Checks whether the specified ADC interrupt has occurred or not. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt source to check. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return FlagStatus: SET or RESET. - */ -ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - itmask = ADC_IT >> 8; - enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); - - if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearITPendingBit - * - * @brief Clears the ADCx's interrupt pending bits. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt pending bit to clear. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return none - */ -void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)(ADC_IT >> 8); - ADCx->STATR = ~(uint32_t)itmask; -} - -/********************************************************************* - * @fn TempSensor_Volt_To_Temper - * - * @brief Internal Temperature Sensor Voltage to temperature. - * - * @param Value - Voltage Value(mv). - * - * @return Temper - Temperature Value. - */ -s32 TempSensor_Volt_To_Temper(s32 Value) -{ - s32 Temper, Refer_Volt, Refer_Temper; - s32 k = 43; - - Refer_Volt = (s32)((*(u32 *)0x1FFFF720) & 0x0000FFFF); - Refer_Temper = (s32)(((*(u32 *)0x1FFFF720) >> 16) & 0x0000FFFF); - - Temper = Refer_Temper - ((Value - Refer_Volt) * 10 + (k >> 1)) / k; - - return Temper; -} - -/********************************************************************* - * @fn ADC_BufferCmd - * - * @brief Enables or disables the ADCx buffer. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= (1 << 26); - } - else - { - ADCx->CTLR1 &= ~(1 << 26); - } -} - -/********************************************************************* - * @fn Get_CalibrationValue - * - * @brief Get ADCx Calibration Value. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return CalibrationValue - */ -int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) -{ - __IO uint8_t i, j; - uint16_t buf[10]; - __IO uint16_t t; -#if defined (CH32V20x_D6) - __IO uint16_t p; -#endif - - for(i = 0; i < 10; i++){ - ADC_ResetCalibration(ADCx); - while(ADC_GetResetCalibrationStatus(ADCx)); - ADC_StartCalibration(ADCx); - while(ADC_GetCalibrationStatus(ADCx)); - buf[i] = ADCx->RDATAR; - } - - for(i = 0; i < 10; i++){ - for(j = 0; j < 9; j++){ - if(buf[j] > buf[j + 1]) - { - t = buf[j]; - buf[j] = buf[j + 1]; - buf[j + 1] = t; - } - } - } - -#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) - t = 0; - for( i = 0; i < 6; i++ ) { - t += buf[i + 2]; - } - - t = ( t / 6 ) + ( ( t % 6 ) / 3 ); - - return ( int16_t )( 2048 - ( int16_t )t ); -#else - t = 0; - p = 0; - /* 1024 */ - for(i = 0; i < 6; i++ ){ - if(buf[i+2] > 1536) break; - t += buf[i+2]; - } - - if(i > 0){ - t = ( t / i ) + ( (( t % i )*2) / i ); - } - else t = 1024; - - /* 2048 */ - j = 6-i; - if(j > 0){ - for(; i < 6; i++ ){ - p += buf[i+2]; - } - - p = ( p / j ) + ( (( p % j )*2) / j ); - } - else p = 2048; - - return ( int16_t )(((( int16_t )( 1024 - ( int16_t )t ) + ( int16_t )( 2048 - ( int16_t )p ))/2) + ((( int16_t )( 1024 - ( int16_t )t ) + ( int16_t )( 2048 - ( int16_t )p ))%2)); - - -#endif -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_adc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file provides all the ADC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_adc.h" +#include "ch32v20x_rcc.h" + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } + else if(ADCx == ADC2) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | + (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_ResetCalibration + * + * @brief Resets the selected ADC calibration registers. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return none + */ +void ADC_ResetCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_RSTCAL_Set; +} + +/********************************************************************* + * @fn ADC_GetResetCalibrationStatus + * + * @brief Gets the selected ADC reset calibration registers status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_StartCalibration + * + * @brief Starts the selected ADC calibration process. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return None + */ +void ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_CAL_Set; +} + +/********************************************************************* + * @fn ADC_GetCalibrationStatus + * + * @brief Gets the selected ADC calibration status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ + +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_GetDualModeConversionValue + * + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * + * @return RDATAR_ADDRESS - The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + return (*(__IO uint32_t *)RDATAR_ADDRESS); +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. + * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. + * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. + * ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 - External interrupt + * line 15 event selected. + * ADC_ExternalTrigInjecConv_None: Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 4. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 12bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_TempSensorVrefintCmd + * + * @brief Enables or disables the temperature sensor and Vrefint channel. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADC1->CTLR2 |= CTLR2_TSVREFE_Set; + } + else + { + ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn TempSensor_Volt_To_Temper + * + * @brief Internal Temperature Sensor Voltage to temperature. + * + * @param Value - Voltage Value(mv). + * + * @return Temper - Temperature Value. + */ +s32 TempSensor_Volt_To_Temper(s32 Value) +{ + s32 Temper, Refer_Volt, Refer_Temper; + s32 k = 43; + + Refer_Volt = (s32)((*(u32 *)0x1FFFF720) & 0x0000FFFF); + Refer_Temper = (s32)(((*(u32 *)0x1FFFF720) >> 16) & 0x0000FFFF); + + Temper = Refer_Temper - ((Value - Refer_Volt) * 10 + (k >> 1)) / k; + + return Temper; +} + +/********************************************************************* + * @fn ADC_BufferCmd + * + * @brief Enables or disables the ADCx buffer. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= (1 << 26); + } + else + { + ADCx->CTLR1 &= ~(1 << 26); + } +} + +/********************************************************************* + * @fn Get_CalibrationValue + * + * @brief Get ADCx Calibration Value. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return CalibrationValue + */ +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) +{ + __IO uint8_t i, j; + uint16_t buf[10]; + __IO uint16_t t; +#if defined (CH32V20x_D6) + __IO uint16_t p; +#endif + + for(i = 0; i < 10; i++){ + ADC_ResetCalibration(ADCx); + while(ADC_GetResetCalibrationStatus(ADCx)); + ADC_StartCalibration(ADCx); + while(ADC_GetCalibrationStatus(ADCx)); + buf[i] = ADCx->RDATAR; + } + + for(i = 0; i < 10; i++){ + for(j = 0; j < 9; j++){ + if(buf[j] > buf[j + 1]) + { + t = buf[j]; + buf[j] = buf[j + 1]; + buf[j + 1] = t; + } + } + } + +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + t = 0; + for( i = 0; i < 6; i++ ) { + t += buf[i + 2]; + } + + t = ( t / 6 ) + ( ( t % 6 ) / 3 ); + + return ( int16_t )( 2048 - ( int16_t )t ); +#else + t = 0; + p = 0; + /* 1024 */ + for(i = 0; i < 6; i++ ){ + if(buf[i+2] > 1536) break; + t += buf[i+2]; + } + + if(i > 0){ + t = ( t / i ) + ( (( t % i )*2) / i ); + } + else t = 1024; + + /* 2048 */ + j = 6-i; + if(j > 0){ + for(; i < 6; i++ ){ + p += buf[i+2]; + } + + p = ( p / j ) + ( (( p % j )*2) / j ); + } + else p = 2048; + + return ( int16_t )(((( int16_t )( 1024 - ( int16_t )t ) + ( int16_t )( 2048 - ( int16_t )p ))/2) + ((( int16_t )( 1024 - ( int16_t )t ) + ( int16_t )( 2048 - ( int16_t )p ))%2)); + + +#endif +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_bkp.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_bkp.c index c21e23e..825777e 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_bkp.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_bkp.c @@ -1,242 +1,244 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_bkp.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the BKP firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include "ch32v20x_bkp.h" -#include "ch32v20x_rcc.h" - -/* BKP registers bit mask */ - -/* OCTLR register bit mask */ -#define OCTLR_CAL_MASK ((uint16_t)0xFF80) -#define OCTLR_MASK ((uint16_t)0xFC7F) - -/********************************************************************* - * @fn BKP_DeInit - * - * @brief Deinitializes the BKP peripheral registers to their default reset values. - * - * @return none - */ -void BKP_DeInit(void) -{ - RCC_BackupResetCmd(ENABLE); - RCC_BackupResetCmd(DISABLE); -} - -/********************************************************************* - * @fn BKP_TamperPinLevelConfig - * - * @brief Configures the Tamper Pin active level. - * - * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. - * BKP_TamperPinLevel_High - Tamper pin active on high level. - * BKP_TamperPinLevel_Low - Tamper pin active on low level. - * - * @return none - */ -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) -{ - if(BKP_TamperPinLevel) - { - BKP->TPCTLR |= (1 << 1); - } - else - { - BKP->TPCTLR &= ~(1 << 1); - } -} - -/********************************************************************* - * @fn BKP_TamperPinCmd - * - * @brief Enables or disables the Tamper Pin activation. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void BKP_TamperPinCmd(FunctionalState NewState) -{ - if(NewState) - { - BKP->TPCTLR |= (1 << 0); - } - else - { - BKP->TPCTLR &= ~(1 << 0); - } -} - -/********************************************************************* - * @fn BKP_ITConfig - * - * @brief Enables or disables the Tamper Pin Interrupt. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void BKP_ITConfig(FunctionalState NewState) -{ - if(NewState) - { - BKP->TPCSR |= (1 << 2); - } - else - { - BKP->TPCSR &= ~(1 << 2); - } -} - -/********************************************************************* - * @fn BKP_RTCOutputConfig - * - * @brief Select the RTC output source to output on the Tamper pin. - * - * @param BKP_RTCOutputSource - specifies the RTC output source. - * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. - * BKP_RTCOutputSource_CalibClock - output the RTC clock with - * frequency divided by 64 on the Tamper pin. - * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal - * on the Tamper pin. - * BKP_RTCOutputSource_Second - output the RTC Second pulse - * signal on the Tamper pin. - * - * @return none - */ -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) -{ - uint16_t tmpreg = 0; - - tmpreg = BKP->OCTLR; - tmpreg &= OCTLR_MASK; - tmpreg |= BKP_RTCOutputSource; - BKP->OCTLR = tmpreg; -} - -/********************************************************************* - * @fn BKP_SetRTCCalibrationValue - * - * @brief Sets RTC Clock Calibration value. - * - * @param CalibrationValue - specifies the RTC Clock Calibration value. - * This parameter must be a number between 0 and 0x1F. - * - * @return none - */ -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) -{ - uint16_t tmpreg = 0; - - tmpreg = BKP->OCTLR; - tmpreg &= OCTLR_CAL_MASK; - tmpreg |= CalibrationValue; - BKP->OCTLR = tmpreg; -} - -/********************************************************************* - * @fn BKP_WriteBackupRegister - * - * @brief Writes user data to the specified Data Backup Register. - * - * @param BKP_DR - specifies the Data Backup Register. - * Data - data to write. - * - * @return none - */ -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - *(__IO uint32_t *)tmp = Data; -} - -/********************************************************************* - * @fn BKP_ReadBackupRegister - * - * @brief Reads data from the specified Data Backup Register. - * - * @param BKP_DR - specifies the Data Backup Register. - * This parameter can be BKP_DRx where x=[1, 42]. - * - * @return none - */ -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - return (*(__IO uint16_t *)tmp); -} - -/********************************************************************* - * @fn BKP_GetFlagStatus - * - * @brief Checks whether the Tamper Pin Event flag is set or not. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus BKP_GetFlagStatus(void) -{ - if(BKP->TPCSR & (1 << 8)) - { - return SET; - } - else - { - return RESET; - } -} - -/********************************************************************* - * @fn BKP_ClearFlag - * - * @brief Clears Tamper Pin Event pending flag. - * - * @return none - */ -void BKP_ClearFlag(void) -{ - BKP->TPCSR |= BKP_CTE; -} - -/********************************************************************* - * @fn BKP_GetITStatus - * - * @brief Checks whether the Tamper Pin Interrupt has occurred or not. - * - * @return ITStatus - SET or RESET. - */ -ITStatus BKP_GetITStatus(void) -{ - if(BKP->TPCSR & (1 << 9)) - { - return SET; - } - else - { - return RESET; - } -} - -/********************************************************************* - * @fn BKP_ClearITPendingBit - * - * @brief Clears Tamper Pin Interrupt pending bit. - * - * @return none - */ -void BKP_ClearITPendingBit(void) -{ - BKP->TPCSR |= BKP_CTI; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_bkp.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/01/06 + * Description : This file provides all the BKP firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_bkp.h" +#include "ch32v20x_rcc.h" + +/* BKP registers bit mask */ + +/* OCTLR register bit mask */ +#define OCTLR_CAL_MASK ((uint16_t)0xFF80) +#define OCTLR_MASK ((uint16_t)0xFC7F) + +/********************************************************************* + * @fn BKP_DeInit + * + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * + * @return none + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/********************************************************************* + * @fn BKP_TamperPinLevelConfig + * + * @brief Configures the Tamper Pin active level. + * + * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. + * BKP_TamperPinLevel_High - Tamper pin active on high level. + * BKP_TamperPinLevel_Low - Tamper pin active on low level. + * + * @return none + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + if(BKP_TamperPinLevel) + { + BKP->TPCTLR |= (1 << 1); + } + else + { + BKP->TPCTLR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn BKP_TamperPinCmd + * + * @brief Enables or disables the Tamper Pin activation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCTLR |= (1 << 0); + } + else + { + BKP->TPCTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn BKP_ITConfig + * + * @brief Enables or disables the Tamper Pin Interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_ITConfig(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCSR |= (1 << 2); + } + else + { + BKP->TPCSR &= ~(1 << 2); + } +} + +/********************************************************************* + * @fn BKP_RTCOutputConfig + * + * @brief Select the RTC output source to output on the Tamper pin. + * + * @param BKP_RTCOutputSource - specifies the RTC output source. + * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. + * BKP_RTCOutputSource_CalibClock - output the RTC clock with + * frequency divided by 64 on the Tamper pin. + * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal + * on the Tamper pin. + * BKP_RTCOutputSource_Second - output the RTC Second pulse + * signal on the Tamper pin. + * + * @return none + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_MASK; + tmpreg |= BKP_RTCOutputSource; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_SetRTCCalibrationValue + * + * @brief Sets RTC Clock Calibration value. + * + * @param CalibrationValue - specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x7F. + * + * @return none + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_CAL_MASK; + tmpreg |= CalibrationValue; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_WriteBackupRegister + * + * @brief Writes user data to the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * Data - data to write. + * + * @return none + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn BKP_ReadBackupRegister + * + * @brief Reads data from the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * This parameter can be BKP_DRx where x=[1, 42]. + * + * @return none + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn BKP_GetFlagStatus + * + * @brief Checks whether the Tamper Pin Event flag is set or not. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus BKP_GetFlagStatus(void) +{ + if(BKP->TPCSR & (1 << 8)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearFlag + * + * @brief Clears Tamper Pin Event pending flag. + * + * @return none + */ +void BKP_ClearFlag(void) +{ + BKP->TPCSR |= BKP_CTE; +} + +/********************************************************************* + * @fn BKP_GetITStatus + * + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * + * @return ITStatus - SET or RESET. + */ +ITStatus BKP_GetITStatus(void) +{ + if(BKP->TPCSR & (1 << 9)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearITPendingBit + * + * @brief Clears Tamper Pin Interrupt pending bit. + * + * @return none + */ +void BKP_ClearITPendingBit(void) +{ + BKP->TPCSR |= BKP_CTI; +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_can.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_can.c index b255de1..90abdcd 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_can.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_can.c @@ -1,1228 +1,1261 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_can.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the CAN firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include "ch32v20x_can.h" -#include "ch32v20x_rcc.h" - -/* CAN CTLR Register bits */ -#define CTLR_DBF ((uint32_t)0x00010000) - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) - -/* CAN FCTLR Register bits */ -#define FCTLR_FINIT ((uint32_t)0x00000001) - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) - - -/* Flags in TSTATR register */ -#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) -/* Flags in RFIFO1 register */ -#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) -/* Flags in RFIFO0 register */ -#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) -/* Flags in STATR register */ -#define CAN_FLAGS_STATR ((uint32_t)0x01000000) -/* Flags in ERRSR register */ -#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - - -#define CAN_MODE_MASK ((uint32_t) 0x00000003) - -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - - -/********************************************************************* - * @fn CAN_DeInit - * - * @brief Deinitializes the CAN peripheral registers to their default reset - * values. - * - * @param CANx - where x can be 1 or 2 to select the CAN peripheral. - * - * @return none - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - if (CANx == CAN1) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); - } - else - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); - } -} - -/********************************************************************* - * @fn CAN_Init - * - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_InitStruct - pointer to a CAN_InitTypeDef structure that - * contains the configuration information for the CAN peripheral. - * - * @return InitStatus - CAN InitStatus state. -* CAN_InitStatus_Failed. -* CAN_InitStatus_Success. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - uint32_t wait_ack = 0x00000000; - - CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); - CANx->CTLR |= CAN_CTLR_INRQ ; - - while (((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - if ((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_TTCM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; - } - - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_ABOM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; - } - - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_AWUM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; - } - - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->CTLR |= CAN_CTLR_NART; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; - } - - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_RFLM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFLM; - } - - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->CTLR |= CAN_CTLR_TXFP; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; - } - - CANx->BTIMR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ - ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ - ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; - wait_ack = 0; - - while (((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - if ((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success ; - } - } - - return InitStatus; -} - -/********************************************************************* - * @fn CAN_FilterInit - * - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_FilterInitStruct. - * - * @param CAN_FilterInitStruct - pointer to a CAN_FilterInitTypeDef - * structure that contains the configuration information. - * - * @return none - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - CAN1->FCTLR |= FCTLR_FINIT; - CAN1->FWR &= ~(uint32_t)filter_number_bit_pos; - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - CAN1->FSCFGR &= ~(uint32_t)filter_number_bit_pos; - - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - CAN1->FSCFGR |= filter_number_bit_pos; - - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - -#if defined (CH32V20x_D6) - if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0) - { - uint32_t i; - - for(i = 0; i < 64; i++){ - *(__IO uint16_t *)(0x40006000 + 512 + 4 * i) = *(__IO uint16_t *)(0x40006000 + 768 + 4 * i); - } - } - -#endif - - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos; - } - else - { - CAN1->FMCFGR |= (uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - CAN1->FAFIFOR &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - CAN1->FAFIFOR |= (uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FWR |= filter_number_bit_pos; - } - - CAN1->FCTLR &= ~FCTLR_FINIT; -} - -/********************************************************************* - * @fn CAN_StructInit - * - * @brief Fills each CAN_InitStruct member with its default value. - * - * @param CAN_InitStruct - pointer to a CAN_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - CAN_InitStruct->CAN_TTCM = DISABLE; - CAN_InitStruct->CAN_ABOM = DISABLE; - CAN_InitStruct->CAN_AWUM = DISABLE; - CAN_InitStruct->CAN_NART = DISABLE; - CAN_InitStruct->CAN_RFLM = DISABLE; - CAN_InitStruct->CAN_TXFP = DISABLE; - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - CAN_InitStruct->CAN_Prescaler = 1; -} - -/********************************************************************* - * @fn CAN_SlaveStartBank - * - * @brief This function applies only to CH32 Connectivity line devices. - * - * @param CAN_BankNumber - Select the start slave bank filter from 1..27. - * - * @return none - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - CAN1->FCTLR |= FCTLR_FINIT; - CAN1->FCTLR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FCTLR |= (uint32_t)(CAN_BankNumber)<<8; - CAN1->FCTLR &= ~FCTLR_FINIT; -} - -/********************************************************************* - * @fn CAN_DBGFreeze - * - * @brief Enables or disables the DBG Freeze for CAN. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - CANx->CTLR |= CTLR_DBF; - } - else - { - CANx->CTLR &= ~CTLR_DBF; - } -} - -/********************************************************************* - * @fn CAN_TTComModeCmd - * - * @brief Enables or disabes the CAN Time TriggerOperation communication mode. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - CANx->CTLR |= CAN_CTLR_TTCM; - - CANx->sTxMailBox[0].TXMDTR |= ((uint32_t)CAN_TXMDT0R_TGT); - CANx->sTxMailBox[1].TXMDTR |= ((uint32_t)CAN_TXMDT1R_TGT); - CANx->sTxMailBox[2].TXMDTR |= ((uint32_t)CAN_TXMDT2R_TGT); - } - else - { - CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTCM); - - CANx->sTxMailBox[0].TXMDTR &= ((uint32_t)~CAN_TXMDT0R_TGT); - CANx->sTxMailBox[1].TXMDTR &= ((uint32_t)~CAN_TXMDT1R_TGT); - CANx->sTxMailBox[2].TXMDTR &= ((uint32_t)~CAN_TXMDT2R_TGT); - } -} - -/********************************************************************* - * @fn CAN_Transmit - * - * @brief Initiates the transmission of a message. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * TxMessage - pointer to a structure which contains CAN Id, CAN - * DLC and CAN data. - * - * @return transmit_mailbox - The number of the mailbox that is used for - * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - - if ((CANx->TSTATR&CAN_TSTATR_TME0) == CAN_TSTATR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSTATR&CAN_TSTATR_TME1) == CAN_TSTATR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSTATR&CAN_TSTATR_TME2) == CAN_TSTATR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if (transmit_mailbox != CAN_TxStatus_NoMailBox) - { - CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_Id_Standard) - { - CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | \ - TxMessage->RTR); - } - else - { - CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->IDE | \ - TxMessage->RTR); - } - - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; - - CANx->sTxMailBox[transmit_mailbox].TXMDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TXMDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; - } - - return transmit_mailbox; -} - -/********************************************************************* - * @fn CAN_TransmitStatus - * - * @brief Checks the transmission of a message. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * TransmitMailbox - the number of the mailbox that is used for - * transmission. - * - * @return state - - * CAN_TxStatus_Ok. - * CAN_TxStatus_Failed. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - switch (TransmitMailbox) - { - case (CAN_TXMAILBOX_0): - state = CANx->TSTATR & (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0); - break; - - case (CAN_TXMAILBOX_1): - state = CANx->TSTATR & (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1); - break; - - case (CAN_TXMAILBOX_2): - state = CANx->TSTATR & (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2); - break; - - default: - state = CAN_TxStatus_Failed; - break; - } - - switch (state) - { - case (0x0): - state = CAN_TxStatus_Pending; - break; - - case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TME0): - state = CAN_TxStatus_Failed; - break; - - case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TME1): - state = CAN_TxStatus_Failed; - break; - - case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TME2): - state = CAN_TxStatus_Failed; - break; - - case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0): - state = CAN_TxStatus_Ok; - break; - - case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1): - state = CAN_TxStatus_Ok; - break; - - case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2): - state = CAN_TxStatus_Ok; - break; - - default: - state = CAN_TxStatus_Failed; - break; - } - - return (uint8_t) state; -} - -/********************************************************************* - * @fn CAN_CancelTransmit - * - * @brief Cancels a transmit request. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * Mailbox - Mailbox number. - * CAN_TXMAILBOX_0. - * CAN_TXMAILBOX_1. - * CAN_TXMAILBOX_2. - * - * @return none - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - switch (Mailbox) - { - case (CAN_TXMAILBOX_0): - CANx->TSTATR |= CAN_TSTATR_ABRQ0; - break; - - case (CAN_TXMAILBOX_1): - CANx->TSTATR |= CAN_TSTATR_ABRQ1; - break; - - case (CAN_TXMAILBOX_2): - CANx->TSTATR |= CAN_TSTATR_ABRQ2; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn CAN_Receive - * - * @brief Receives a message. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * FIFONumber - Receive FIFO number. - * CAN_FIFO0. - * CAN_FIFO1. - * RxMessage - pointer to a structure receive message which contains - * CAN Id, CAN DLC, CAN datas and FMI number. - * - * @return none - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; - - if (RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 24); - - if (FIFONumber == CAN_FIFO0) - { - CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; - } - else - { - CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; - } -} - -/********************************************************************* - * @fn CAN_FIFORelease - * - * @brief Releases the specified FIFO. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * FIFONumber - Receive FIFO number. - * CAN_FIFO0. - * CAN_FIFO1. - * - * @return none - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - if (FIFONumber == CAN_FIFO0) - { - CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; - } - else - { - CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; - } -} - -/********************************************************************* - * @fn CAN_MessagePending - * - * @brief Returns the number of pending messages. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * FIFONumber - Receive FIFO number. - * CAN_FIFO0. - * CAN_FIFO1. - * - * @return message_pending: which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RFIFO0&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RFIFO1&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - - return message_pending; -} - -/********************************************************************* - * @fn CAN_OperatingModeRequest - * - * @brief Select the CAN Operation mode. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_OperatingMode - CAN Operating Mode. - * CAN_OperatingMode_Initialization. - * CAN_OperatingMode_Normal. - * CAN_OperatingMode_Sleep. - * - * @return status - - * CAN_ModeStatus_Failed - CAN failed entering the specific mode. - * CAN_ModeStatus_Success - CAN Succeed entering the specific mode. - */ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) -{ - uint8_t status = CAN_ModeStatus_Failed; - uint32_t timeout = INAK_TIMEOUT; - - if (CAN_OperatingMode == CAN_OperatingMode_Initialization) - { - CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SLEEP)) | CAN_CTLR_INRQ); - - while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) && (timeout != 0)) - { - timeout--; - } - if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Normal) - { - CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SLEEP|CAN_CTLR_INRQ)); - - while (((CANx->STATR & CAN_MODE_MASK) != 0) && (timeout!=0)) - { - timeout--; - } - if ((CANx->STATR & CAN_MODE_MASK) != 0) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) - { - CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); - - while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) && (timeout!=0)) - { - timeout--; - } - if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else - { - status = CAN_ModeStatus_Failed; - } - - return (uint8_t) status; -} - -/********************************************************************* - * @fn CAN_Sleep - * - * @brief Enters the low power mode. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return sleepstatus - - * CAN_Sleep_Ok. - * CAN_Sleep_Failed. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CAN_Sleep_Failed; - - CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); - - if ((CANx->STATR & (CAN_STATR_SLAK|CAN_STATR_INAK)) == CAN_STATR_SLAK) - { - sleepstatus = CAN_Sleep_Ok; - } - - return (uint8_t)sleepstatus; -} - -/********************************************************************* - * @fn CAN_WakeUp - * - * @brief Wakes the CAN up. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return wakeupstatus - - * CAN_WakeUp_Ok. - * CAN_WakeUp_Failed. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CAN_WakeUp_Failed; - - CANx->CTLR &= ~(uint32_t)CAN_CTLR_SLEEP; - - while(((CANx->STATR & CAN_STATR_SLAK) == CAN_STATR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->STATR & CAN_STATR_SLAK) != CAN_STATR_SLAK) - { - wakeupstatus = CAN_WakeUp_Ok; - } - - return (uint8_t)wakeupstatus; -} - -/********************************************************************* - * @fn CAN_GetLastErrorCode - * - * @brief Returns the CANx's last error code (LEC). - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return errorcode - specifies the Error code. - * CAN_ErrorCode_NoErr - No Error. - * CAN_ErrorCode_StuffErr - Stuff Error. - * CAN_ErrorCode_FormErr - Form Error. - * CAN_ErrorCode_ACKErr - Acknowledgment Error. - * CAN_ErrorCode_BitRecessiveErr - Bit Recessive Error. - * CAN_ErrorCode_BitDominantErr - Bit Dominant Error. - * CAN_ErrorCode_CRCErr - CRC Error. - * CAN_ErrorCode_SoftwareSetErr - Software Set Error. - */ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) -{ - uint8_t errorcode=0; - - errorcode = (((uint8_t)CANx->ERRSR) & (uint8_t)CAN_ERRSR_LEC); - - return errorcode; -} - -/********************************************************************* - * @fn CAN_GetReceiveErrorCounter - * - * @brief Returns the CANx Receive Error Counter (REC). - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return counter - CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_REC)>> 24); - - return counter; -} - -/********************************************************************* - * @fn CAN_GetLSBTransmitErrorCounter - * - * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return counter - LSB of the 9-bit CAN Transmit Error Counter. - */ -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_TEC)>> 16); - - return counter; -} - -/********************************************************************* - * @fn CAN_ITConfig - * - * @brief Enables or disables the specified CANx interrupts. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_IT - specifies the CAN interrupt sources to be enabled or disabled. - * CAN_IT_TME. - * CAN_IT_FMP0. - * CAN_IT_FF0. - * CAN_IT_FOV0. - * CAN_IT_FMP1. - * CAN_IT_FF1. - * CAN_IT_FOV1. - * CAN_IT_EWG. - * CAN_IT_EPV. - * CAN_IT_LEC. - * CAN_IT_ERR. - * CAN_IT_WKU. - * CAN_IT_SLK. - * NewState - ENABLE or DISABLE. - * - * @return counter - LSB of the 9-bit CAN Transmit Error Counter. - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - CANx->INTENR |= CAN_IT; - } - else - { - CANx->INTENR &= ~CAN_IT; - } -} - -/********************************************************************* - * @fn CAN_GetFlagStatus - * - * @brief Checks whether the specified CAN flag is set or not. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_FLAG - specifies the flag to check. - * CAN_FLAG_EWG. - * CAN_FLAG_EPV. - * CAN_FLAG_BOF. - * CAN_FLAG_RQCP0. - * CAN_FLAG_RQCP1. - * CAN_FLAG_RQCP2. - * CAN_FLAG_FMP1. - * CAN_FLAG_FF1. - * CAN_FLAG_FOV1. - * CAN_FLAG_FMP0. - * CAN_FLAG_FF0. - * CAN_FLAG_FOV0. - * CAN_FLAG_WKU. - * CAN_FLAG_SLAK. - * CAN_FLAG_LEC. - * NewState - ENABLE or DISABLE. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((CAN_FLAG & CAN_FLAGS_ERRSR) != (uint32_t)RESET) - { - if ((CANx->ERRSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_STATR) != (uint32_t)RESET) - { - if ((CANx->STATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) - { - if ((CANx->TSTATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) - { - if ((CANx->RFIFO0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if ((uint32_t)(CANx->RFIFO1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - - return bitstatus; -} - -/********************************************************************* - * @fn CAN_ClearFlag - * - * @brief Clears the CAN's pending flags. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_FLAG - specifies the flag to clear. - * CAN_FLAG_RQCP0. - * CAN_FLAG_RQCP1. - * CAN_FLAG_RQCP2. - * CAN_FLAG_FF1. - * CAN_FLAG_FOV1. - * CAN_FLAG_FF0. - * CAN_FLAG_FOV0. - * CAN_FLAG_WKU. - * CAN_FLAG_SLAK. - * CAN_FLAG_LEC. - * - * @return none - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - uint32_t flagtmp=0; - - if (CAN_FLAG == CAN_FLAG_LEC) - { - CANx->ERRSR = (uint32_t)RESET; - } - else - { - flagtmp = CAN_FLAG & 0x000FFFFF; - - if ((CAN_FLAG & CAN_FLAGS_RFIFO0)!=(uint32_t)RESET) - { - CANx->RFIFO0 = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_RFIFO1)!=(uint32_t)RESET) - { - CANx->RFIFO1 = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_TSTATR)!=(uint32_t)RESET) - { - CANx->TSTATR = (uint32_t)(flagtmp); - } - else - { - CANx->STATR = (uint32_t)(flagtmp); - } - } -} - -/********************************************************************* - * @fn CAN_GetITStatus - * - * @brief Checks whether the specified CANx interrupt has occurred or not. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_IT - specifies the CAN interrupt source to check. - * CAN_IT_TME. - * CAN_IT_FMP0. - * CAN_IT_FF0. - * CAN_IT_FOV0. - * CAN_IT_FMP1. - * CAN_IT_FF1. - * CAN_IT_FOV1. - * CAN_IT_WKU. - * CAN_IT_SLK. - * CAN_IT_EWG. - * CAN_IT_EPV. - * CAN_IT_BOF. - * CAN_IT_LEC. - * CAN_IT_ERR. - * - * @return ITStatus - SET or RESET. - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus itstatus = RESET; - - if((CANx->INTENR & CAN_IT) != RESET) - { - switch (CAN_IT) - { - case CAN_IT_TME: - itstatus = CheckITStatus(CANx->TSTATR, CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2); - break; - - case CAN_IT_FMP0: - itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FMP0); - break; - - case CAN_IT_FF0: - itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FULL0); - break; - - case CAN_IT_FOV0: - itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FOVR0); - break; - - case CAN_IT_FMP1: - itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FMP1); - break; - - case CAN_IT_FF1: - itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FULL1); - break; - - case CAN_IT_FOV1: - itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FOVR1); - break; - - case CAN_IT_WKU: - itstatus = CheckITStatus(CANx->STATR, CAN_STATR_WKUI); - break; - - case CAN_IT_SLK: - itstatus = CheckITStatus(CANx->STATR, CAN_STATR_SLAKI); - break; - - case CAN_IT_EWG: - itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EWGF); - break; - - case CAN_IT_EPV: - itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EPVF); - break; - - case CAN_IT_BOF: - itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_BOFF); - break; - - case CAN_IT_LEC: - itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_LEC); - break; - - case CAN_IT_ERR: - itstatus = CheckITStatus(CANx->STATR, CAN_STATR_ERRI); - break; - - default : - itstatus = RESET; - break; - } - } - else - { - itstatus = RESET; - } - - return itstatus; -} - -/********************************************************************* - * @fn CAN_ClearITPendingBit - * - * @brief Clears the CANx's interrupt pending bits. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_IT - specifies the interrupt pending bit to clear. - * CAN_IT_TME. - * CAN_IT_FF0. - * CAN_IT_FOV0. - * CAN_IT_FF1. - * CAN_IT_FOV1. - * CAN_IT_WKU. - * CAN_IT_SLK. - * CAN_IT_EWG. - * CAN_IT_EPV. - * CAN_IT_BOF. - * CAN_IT_LEC. - * CAN_IT_ERR. - * - * @return none - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - switch (CAN_IT) - { - case CAN_IT_TME: - CANx->TSTATR = CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2; - break; - - case CAN_IT_FF0: - CANx->RFIFO0 = CAN_RFIFO0_FULL0; - break; - - case CAN_IT_FOV0: - CANx->RFIFO0 = CAN_RFIFO0_FOVR0; - break; - - case CAN_IT_FF1: - CANx->RFIFO1 = CAN_RFIFO1_FULL1; - break; - - case CAN_IT_FOV1: - CANx->RFIFO1 = CAN_RFIFO1_FOVR1; - break; - - case CAN_IT_WKU: - CANx->STATR = CAN_STATR_WKUI; - break; - - case CAN_IT_SLK: - CANx->STATR = CAN_STATR_SLAKI; - break; - - case CAN_IT_EWG: - CANx->STATR = CAN_STATR_ERRI; - break; - - case CAN_IT_EPV: - CANx->STATR = CAN_STATR_ERRI; - break; - - case CAN_IT_BOF: - CANx->STATR = CAN_STATR_ERRI; - break; - - case CAN_IT_LEC: - CANx->ERRSR = RESET; - CANx->STATR = CAN_STATR_ERRI; - break; - - case CAN_IT_ERR: - CANx->ERRSR = RESET; - CANx->STATR = CAN_STATR_ERRI; - break; - - default : - break; - } -} - -/********************************************************************* - * @fn CheckITStatus - * - * @brief Checks whether the CAN interrupt has occurred or not. - * - * @param CAN_Reg - specifies the CAN interrupt register to check - * It_Bit - specifies the interrupt source bit to check. - * - * @return ITStatus - SET or RESET. - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - pendingbitstatus = SET; - } - else - { - pendingbitstatus = RESET; - } - - return pendingbitstatus; -} - - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_can.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file provides all the CAN firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_can.h" +#include "ch32v20x_rcc.h" + +/* CAN CTLR Register bits */ +#define CTLR_DBF ((uint32_t)0x00010000) + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) + +/* CAN FCTLR Register bits */ +#define FCTLR_FINIT ((uint32_t)0x00000001) + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + + +/* Flags in TSTATR register */ +#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) +/* Flags in RFIFO1 register */ +#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) +/* Flags in RFIFO0 register */ +#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) +/* Flags in STATR register */ +#define CAN_FLAGS_STATR ((uint32_t)0x01000000) +/* Flags in ERRSR register */ +#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + + +/********************************************************************* + * @fn CAN_DeInit + * + * @brief Deinitializes the CAN peripheral registers to their default reset + * values. + * + * @param CANx - where x can be 1 or 2 to select the CAN peripheral. + * + * @return none + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + if (CANx == CAN1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/********************************************************************* + * @fn CAN_Init + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_InitStruct - pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * + * @return InitStatus - CAN InitStatus state. +* CAN_InitStatus_Failed. +* CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + + CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); + CANx->CTLR |= CAN_CTLR_INRQ ; + + while (((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; + } + + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_ABOM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; + } + + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_AWUM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; + } + + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->CTLR |= CAN_CTLR_NART; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; + } + + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_RFLM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFLM; + } + + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TXFP; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; + } + + CANx->BTIMR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; + wait_ack = 0; + + while (((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if ((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + return InitStatus; +} + +/********************************************************************* + * @fn CAN_FilterInit + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * + * @param CAN_FilterInitStruct - pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration information. + * + * @return none + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FWR &= ~(uint32_t)filter_number_bit_pos; + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + CAN1->FSCFGR &= ~(uint32_t)filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + CAN1->FSCFGR |= filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + +#if defined (CH32V20x_D6) + if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0) + { + uint32_t i; + + for(i = 0; i < 64; i++) + { + *(__IO uint16_t *)(0x40006000 + 512 + 4 * i) = *(__IO uint16_t *)(0x40006000 + 768 + 4 * i); + } + } + +#endif + + +#if defined (CH32V20x_D8) + RCC->AHBPCENR |= (1<<17); + *(vu32*)0x400250A0 = 0x55aaaa55; + + if(*(vu32*)0x400250A0 != 0x55aaaa55) + { + uint32_t i; + + for(i = 0; i < 64; i++) + { + *(__IO uint16_t *)(0x40006000 + 512 + 4 * i) = *(__IO uint16_t *)(0x40006000 + 768 + 4 * i); + } + } + + RCC->AHBPCENR &= ~(1<<17); + +#endif + + + + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos; + } + else + { + CAN1->FMCFGR |= (uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + CAN1->FAFIFOR &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + CAN1->FAFIFOR |= (uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FWR |= filter_number_bit_pos; + } + + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_StructInit + * + * @brief Fills each CAN_InitStruct member with its default value. + * + * @param CAN_InitStruct - pointer to a CAN_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + CAN_InitStruct->CAN_TTCM = DISABLE; + CAN_InitStruct->CAN_ABOM = DISABLE; + CAN_InitStruct->CAN_AWUM = DISABLE; + CAN_InitStruct->CAN_NART = DISABLE; + CAN_InitStruct->CAN_RFLM = DISABLE; + CAN_InitStruct->CAN_TXFP = DISABLE; + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + CAN_InitStruct->CAN_Prescaler = 1; +} + +/********************************************************************* + * @fn CAN_SlaveStartBank + * + * @brief This function applies only to CH32 Connectivity line devices. + * + * @param CAN_BankNumber - Select the start slave bank filter from 1..27. + * + * @return none + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FCTLR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FCTLR |= (uint32_t)(CAN_BankNumber)<<8; + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_DBGFreeze + * + * @brief Enables or disables the DBG Freeze for CAN. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CANx->CTLR |= CTLR_DBF; + } + else + { + CANx->CTLR &= ~CTLR_DBF; + } +} + +/********************************************************************* + * @fn CAN_TTComModeCmd + * + * @brief Enables or disabes the CAN Time TriggerOperation communication mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * Note- + * DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * + * @return none + */ +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + + CANx->sTxMailBox[0].TXMDTR |= ((uint32_t)CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR |= ((uint32_t)CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR |= ((uint32_t)CAN_TXMDT2R_TGT); + } + else + { + CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTCM); + + CANx->sTxMailBox[0].TXMDTR &= ((uint32_t)~CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR &= ((uint32_t)~CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR &= ((uint32_t)~CAN_TXMDT2R_TGT); + } +} + +/********************************************************************* + * @fn CAN_Transmit + * + * @brief Initiates the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TxMessage - pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * + * @return transmit_mailbox - The number of the mailbox that is used for + * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + + if ((CANx->TSTATR&CAN_TSTATR_TME0) == CAN_TSTATR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME1) == CAN_TSTATR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSTATR&CAN_TSTATR_TME2) == CAN_TSTATR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; + + CANx->sTxMailBox[transmit_mailbox].TXMDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TXMDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; + } + + return transmit_mailbox; +} + +/********************************************************************* + * @fn CAN_TransmitStatus + * + * @brief Checks the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TransmitMailbox - the number of the mailbox that is used for + * transmission. + * + * @return state - + * CAN_TxStatus_Ok. + * CAN_TxStatus_Failed. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSTATR & (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0); + break; + + case (CAN_TXMAILBOX_1): + state = CANx->TSTATR & (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1); + break; + + case (CAN_TXMAILBOX_2): + state = CANx->TSTATR & (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2); + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + switch (state) + { + case (0x0): + state = CAN_TxStatus_Pending; + break; + + case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Failed; + break; + + case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Failed; + break; + + case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Failed; + break; + + case (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Ok; + break; + + case (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Ok; + break; + + case (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Ok; + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + return (uint8_t) state; +} + +/********************************************************************* + * @fn CAN_CancelTransmit + * + * @brief Cancels a transmit request. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Mailbox - Mailbox number. + * CAN_TXMAILBOX_0. + * CAN_TXMAILBOX_1. + * CAN_TXMAILBOX_2. + * + * @return none + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): + CANx->TSTATR |= CAN_TSTATR_ABRQ0; + break; + + case (CAN_TXMAILBOX_1): + CANx->TSTATR |= CAN_TSTATR_ABRQ1; + break; + + case (CAN_TXMAILBOX_2): + CANx->TSTATR |= CAN_TSTATR_ABRQ2; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn CAN_Receive + * + * @brief Receives a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * RxMessage - pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * + * @return none + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 24); + + if (FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_FIFORelease + * + * @brief Releases the specified FIFO. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return none + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + if (FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_MessagePending + * + * @brief Returns the number of pending messages. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return message_pending: which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RFIFO0&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RFIFO1&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + + return message_pending; +} + +/********************************************************************* + * @fn CAN_OperatingModeRequest + * + * @brief Select the CAN Operation mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_OperatingMode - CAN Operating Mode. + * CAN_OperatingMode_Initialization. + * CAN_OperatingMode_Normal. + * CAN_OperatingMode_Sleep. + * + * @return status - + * CAN_ModeStatus_Failed - CAN failed entering the specific mode. + * CAN_ModeStatus_Success - CAN Succeed entering the specific mode. + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + uint32_t timeout = INAK_TIMEOUT; + + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SLEEP)) | CAN_CTLR_INRQ); + + while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Normal) + { + CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SLEEP|CAN_CTLR_INRQ)); + + while (((CANx->STATR & CAN_MODE_MASK) != 0) && (timeout!=0)) + { + timeout--; + } + if ((CANx->STATR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + while (((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) && (timeout!=0)) + { + timeout--; + } + if ((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t) status; +} + +/********************************************************************* + * @fn CAN_Sleep + * + * @brief Enters the low power mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return sleepstatus - + * CAN_Sleep_Ok. + * CAN_Sleep_Failed. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + if ((CANx->STATR & (CAN_STATR_SLAK|CAN_STATR_INAK)) == CAN_STATR_SLAK) + { + sleepstatus = CAN_Sleep_Ok; + } + + return (uint8_t)sleepstatus; +} + +/********************************************************************* + * @fn CAN_WakeUp + * + * @brief Wakes the CAN up. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return wakeupstatus - + * CAN_WakeUp_Ok. + * CAN_WakeUp_Failed. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + CANx->CTLR &= ~(uint32_t)CAN_CTLR_SLEEP; + + while(((CANx->STATR & CAN_STATR_SLAK) == CAN_STATR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->STATR & CAN_STATR_SLAK) != CAN_STATR_SLAK) + { + wakeupstatus = CAN_WakeUp_Ok; + } + + return (uint8_t)wakeupstatus; +} + +/********************************************************************* + * @fn CAN_GetLastErrorCode + * + * @brief Returns the CANx's last error code (LEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return errorcode - specifies the Error code. + * CAN_ErrorCode_NoErr - No Error. + * CAN_ErrorCode_StuffErr - Stuff Error. + * CAN_ErrorCode_FormErr - Form Error. + * CAN_ErrorCode_ACKErr - Acknowledgment Error. + * CAN_ErrorCode_BitRecessiveErr - Bit Recessive Error. + * CAN_ErrorCode_BitDominantErr - Bit Dominant Error. + * CAN_ErrorCode_CRCErr - CRC Error. + * CAN_ErrorCode_SoftwareSetErr - Software Set Error. + */ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) +{ + uint8_t errorcode=0; + + errorcode = (((uint8_t)CANx->ERRSR) & (uint8_t)CAN_ERRSR_LEC); + + return errorcode; +} + +/********************************************************************* + * @fn CAN_GetReceiveErrorCounter + * + * @brief Returns the CANx Receive Error Counter (REC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Note- + * In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @return counter - CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_REC)>> 24); + + return counter; +} + +/********************************************************************* + * @fn CAN_GetLSBTransmitErrorCounter + * + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_TEC)>> 16); + + return counter; +} + +/********************************************************************* + * @fn CAN_ITConfig + * + * @brief Enables or disables the specified CANx interrupts. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt sources to be enabled or disabled. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_LEC. + * CAN_IT_ERR. + * CAN_IT_WKU. + * CAN_IT_SLK. + * NewState - ENABLE or DISABLE. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + CANx->INTENR |= CAN_IT; + } + else + { + CANx->INTENR &= ~CAN_IT; + } +} + +/********************************************************************* + * @fn CAN_GetFlagStatus + * + * @brief Checks whether the specified CAN flag is set or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to check. + * CAN_FLAG_EWG. + * CAN_FLAG_EPV. + * CAN_FLAG_BOF. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FMP1. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FMP0. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * NewState - ENABLE or DISABLE. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((CAN_FLAG & CAN_FLAGS_ERRSR) != (uint32_t)RESET) + { + if ((CANx->ERRSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_STATR) != (uint32_t)RESET) + { + if ((CANx->STATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) + { + if ((CANx->TSTATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) + { + if ((CANx->RFIFO0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((uint32_t)(CANx->RFIFO1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/********************************************************************* + * @fn CAN_ClearFlag + * + * @brief Clears the CAN's pending flags. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to clear. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * + * @return none + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp=0; + + if (CAN_FLAG == CAN_FLAG_LEC) + { + CANx->ERRSR = (uint32_t)RESET; + } + else + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RFIFO0)!=(uint32_t)RESET) + { + CANx->RFIFO0 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RFIFO1)!=(uint32_t)RESET) + { + CANx->RFIFO1 = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSTATR)!=(uint32_t)RESET) + { + CANx->TSTATR = (uint32_t)(flagtmp); + } + else + { + CANx->STATR = (uint32_t)(flagtmp); + } + } +} + +/********************************************************************* + * @fn CAN_GetITStatus + * + * @brief Checks whether the specified CANx interrupt has occurred or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt source to check. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return ITStatus - SET or RESET. + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + + if((CANx->INTENR & CAN_IT) != RESET) + { + switch (CAN_IT) + { + case CAN_IT_TME: + itstatus = CheckITStatus(CANx->TSTATR, CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2); + break; + + case CAN_IT_FMP0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FMP0); + break; + + case CAN_IT_FF0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FULL0); + break; + + case CAN_IT_FOV0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FOVR0); + break; + + case CAN_IT_FMP1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FMP1); + break; + + case CAN_IT_FF1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FULL1); + break; + + case CAN_IT_FOV1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FOVR1); + break; + + case CAN_IT_WKU: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_WKUI); + break; + + case CAN_IT_SLK: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_SLAKI); + break; + + case CAN_IT_EWG: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EWGF); + break; + + case CAN_IT_EPV: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EPVF); + break; + + case CAN_IT_BOF: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_BOFF); + break; + + case CAN_IT_LEC: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_LEC); + break; + + case CAN_IT_ERR: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_ERRI); + break; + + default : + itstatus = RESET; + break; + } + } + else + { + itstatus = RESET; + } + + return itstatus; +} + +/********************************************************************* + * @fn CAN_ClearITPendingBit + * + * @brief Clears the CANx's interrupt pending bits. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the interrupt pending bit to clear. + * CAN_IT_TME. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return none + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + switch (CAN_IT) + { + case CAN_IT_TME: + CANx->TSTATR = CAN_TSTATR_RQCP0|CAN_TSTATR_RQCP1|CAN_TSTATR_RQCP2; + break; + + case CAN_IT_FF0: + CANx->RFIFO0 = CAN_RFIFO0_FULL0; + break; + + case CAN_IT_FOV0: + CANx->RFIFO0 = CAN_RFIFO0_FOVR0; + break; + + case CAN_IT_FF1: + CANx->RFIFO1 = CAN_RFIFO1_FULL1; + break; + + case CAN_IT_FOV1: + CANx->RFIFO1 = CAN_RFIFO1_FOVR1; + break; + + case CAN_IT_WKU: + CANx->STATR = CAN_STATR_WKUI; + break; + + case CAN_IT_SLK: + CANx->STATR = CAN_STATR_SLAKI; + break; + + case CAN_IT_EWG: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_EPV: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_BOF: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_LEC: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_ERR: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + default : + break; + } +} + +/********************************************************************* + * @fn CheckITStatus + * + * @brief Checks whether the CAN interrupt has occurred or not. + * + * @param CAN_Reg - specifies the CAN interrupt register to check + * It_Bit - specifies the interrupt source bit to check. + * + * @return ITStatus - SET or RESET. + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + pendingbitstatus = SET; + } + else + { + pendingbitstatus = RESET; + } + + return pendingbitstatus; +} + + + + + + diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_crc.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_crc.c index 0839ad0..930f451 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_crc.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_crc.c @@ -1,97 +1,99 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_crc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the CRC firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include "ch32v20x_crc.h" - -/********************************************************************* - * @fn CRC_ResetDR - * - * @brief Resets the CRC Data register (DR). - * - * @return none - */ -void CRC_ResetDR(void) -{ - CRC->CTLR = CRC_CTLR_RESET; -} - -/********************************************************************* - * @fn CRC_CalcCRC - * - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * - * @param Data - data word(32-bit) to compute its CRC. - * - * @return 32-bit CRC. - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DATAR = Data; - - return (CRC->DATAR); -} - -/********************************************************************* - * @fn CRC_CalcBlockCRC - * - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * - * @param pBuffer - pointer to the buffer containing the data to be computed. - * BufferLength - length of the buffer to be computed. - * - * @return 32-bit CRC. - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++){ - CRC->DATAR = pBuffer[index]; - } - - return (CRC->DATAR); -} - -/********************************************************************* - * @fn CRC_GetCRC - * - * @brief Returns the current CRC value. - * - * @return 32-bit CRC. - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DATAR); -} - -/********************************************************************* - * @fn CRC_SetIDRegister - * - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * - * @param IDValue - 8-bit value to be stored in the ID register. - * - * @return none - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDATAR = IDValue; -} - -/********************************************************************* - * @fn CRC_GetIDRegister - * - * @brief Returns the 8-bit data stored in the Independent Data(ID) register. - * - * @return 8-bit value of the ID register. - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDATAR); -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_crc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file provides all the CRC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_crc.h" + +/********************************************************************* + * @fn CRC_ResetDR + * + * @brief Resets the CRC Data register (DR). + * + * @return none + */ +void CRC_ResetDR(void) +{ + CRC->CTLR = CRC_CTLR_RESET; +} + +/********************************************************************* + * @fn CRC_CalcCRC + * + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * + * @param Data - data word(32-bit) to compute its CRC. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DATAR = Data; + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_CalcBlockCRC + * + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * + * @param pBuffer - pointer to the buffer containing the data to be computed. + * BufferLength - length of the buffer to be computed. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++){ + CRC->DATAR = pBuffer[index]; + } + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_GetCRC + * + * @brief Returns the current CRC value. + * + * @return 32-bit CRC. + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_SetIDRegister + * + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * + * @param IDValue - 8-bit value to be stored in the ID register. + * + * @return none + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDATAR = IDValue; +} + +/********************************************************************* + * @fn CRC_GetIDRegister + * + * @brief Returns the 8-bit data stored in the Independent Data(ID) register. + * + * @return 8-bit value of the ID register. + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDATAR); +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_dbgmcu.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_dbgmcu.c index 2bdef2d..b5c50ef 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_dbgmcu.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_dbgmcu.c @@ -1,98 +1,126 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_dbgmcu.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the DBGMCU firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - ****************************************************************************************/ -#include "ch32v20x_dbgmcu.h" - -#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) - -/********************************************************************* - * @fn DBGMCU_GetREVID - * - * @brief Returns the device revision identifier. - * - * @return Revision identifier. - */ -uint32_t DBGMCU_GetREVID(void) -{ - return ((*(uint32_t *)0x1FFFF704) >> 16); -} - -/********************************************************************* - * @fn DBGMCU_GetDEVID - * - * @brief Returns the device identifier. - * - * @return Device identifier. - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); -} - -/********************************************************************* - * @fn __get_DEBUG_CR - * - * @brief Return the DEBUGE Control Register - * - * @return DEBUGE Control value - */ -uint32_t __get_DEBUG_CR(void) -{ - uint32_t result; - - __asm volatile("csrr %0,""0x7C0" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_DEBUG_CR - * - * @brief Set the DEBUGE Control Register - * - * @param value - set DEBUGE Control value - * - * @return none - */ -void __set_DEBUG_CR(uint32_t value) -{ - __asm volatile("csrw 0x7C0, %0" : : "r"(value)); -} - - -/********************************************************************* - * @fn DBGMCU_Config - * - * @brief Configures the specified peripheral and low power mode behavior - * when the MCU under Debug mode. - * - * @param DBGMCU_Periph - specifies the peripheral and low power mode. - * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted - * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted - * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted - * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - uint32_t val; - - if(NewState != DISABLE) - { - __set_DEBUG_CR(DBGMCU_Periph); - } - else - { - val = __get_DEBUG_CR(); - val &= ~(uint32_t)DBGMCU_Periph; - __set_DEBUG_CR(val); - } - -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_dbgmcu.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file provides all the DBGMCU firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32v20x_dbgmcu.h" + +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) >> 16); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); +} + +/********************************************************************* + * @fn __get_DEBUG_CR + * + * @brief Return the DEBUGE Control Register + * + * @return DEBUGE Control value + */ +uint32_t __get_DEBUG_CR(void) +{ + uint32_t result; + + __asm volatile("csrr %0,""0x7C0" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_DEBUG_CR + * + * @brief Set the DEBUGE Control Register + * + * @param value - set DEBUGE Control value + * + * @return none + */ +void __set_DEBUG_CR(uint32_t value) +{ + __asm volatile("csrw 0x7C0, %0" : : "r"(value)); +} + + +/********************************************************************* + * @fn DBGMCU_Config + * + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * + * @param DBGMCU_Periph - specifies the peripheral and low power mode. + * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted + * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted + * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted + * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + uint32_t val; + + if(NewState != DISABLE) + { + __set_DEBUG_CR(DBGMCU_Periph); + } + else + { + val = __get_DEBUG_CR(); + val &= ~(uint32_t)DBGMCU_Periph; + __set_DEBUG_CR(val); + } + +} +/********************************************************************* + * @fn DBGMCU_GetCHIPID + * + * @brief Returns the CHIP identifier. + * + * @return Device identifier. + * ChipID List- + * CH32V203C8U6-0x203005x0 + * CH32V203C8T6-0x203105x0 + * CH32V203K8T6-0x203205x0 + * CH32V203C6T6-0x203305x0 + * CH32V203G6U6-0x203605x0 + * CH32V203G8R6-0x203B05x0 + * CH32V203F8U6-0x203E05x0 + * CH32V203F6P6-0x203705x0-0x203905x0 + * CH32V203F8P6-0x203A05x0 + * CH32V203RBT6-0x203405xC + * CH32V208WBU6-0x208005xC + * CH32V208RBT6-0x208105xC + * CH32V208CBU6-0x208205xC + * CH32V208GBU6-0x208305xC + */ +uint32_t DBGMCU_GetCHIPID( void ) +{ + return( *( uint32_t * )0x1FFFF704 ); +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_dma.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_dma.c index 44a4662..9a1272d 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_dma.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_dma.c @@ -1,430 +1,432 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_dma.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the DMA firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include "ch32v20x_dma.h" -#include "ch32v20x_rcc.h" - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) -#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) -#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) -#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) -#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) -#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) -#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) -#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) - -/* DMA2 FLAG mask */ -#define FLAG_Mask ((uint32_t)0x10000000) - -/* DMA registers Masks */ -#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) - -/********************************************************************* - * @fn DMA_DeInit - * - * @brief Deinitializes the DMAy Channelx registers to their default - * reset values. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * - * @return none - */ -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) -{ - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - DMAy_Channelx->CFGR = 0; - DMAy_Channelx->CNTR = 0; - DMAy_Channelx->PADDR = 0; - DMAy_Channelx->MADDR = 0; - if(DMAy_Channelx == DMA1_Channel1) - { - DMA1->INTFCR |= DMA1_Channel1_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel2) - { - DMA1->INTFCR |= DMA1_Channel2_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel3) - { - DMA1->INTFCR |= DMA1_Channel3_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel4) - { - DMA1->INTFCR |= DMA1_Channel4_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel5) - { - DMA1->INTFCR |= DMA1_Channel5_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel6) - { - DMA1->INTFCR |= DMA1_Channel6_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel7) - { - DMA1->INTFCR |= DMA1_Channel7_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel8) - { - DMA1->INTFCR |= DMA1_Channel8_IT_Mask; - } -} - -/********************************************************************* - * @fn DMA_Init - * - * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - tmpreg = DMAy_Channelx->CFGR; - tmpreg &= CFGR_CLEAR_Mask; - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - DMAy_Channelx->CFGR = tmpreg; - DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; - DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; - DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/********************************************************************* - * @fn DMA_StructInit - * - * @brief Fills each DMA_InitStruct member with its default value. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) -{ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - DMA_InitStruct->DMA_BufferSize = 0; - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/********************************************************************* - * @fn DMA_Cmd - * - * @brief Enables or disables the specified DMAy Channelx. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_CFGR1_EN; - } - else - { - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - } -} - -/********************************************************************* - * @fn DMA_ITConfig - * - * @brief Enables or disables the specified DMAy Channelx interrupts. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * DMA_IT - specifies the DMA interrupts sources to be enabled - * or disabled. - * DMA_IT_TC - Transfer complete interrupt mask - * DMA_IT_HT - Half transfer interrupt mask - * DMA_IT_TE - Transfer error interrupt mask - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_IT; - } - else - { - DMAy_Channelx->CFGR &= ~DMA_IT; - } -} - -/********************************************************************* - * @fn DMA_SetCurrDataCounter - * - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * DataNumber - The number of data units in the current DMAy Channelx - * transfer. - * - * @return none - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) -{ - DMAy_Channelx->CNTR = DataNumber; -} - -/********************************************************************* - * @fn DMA_GetCurrDataCounter - * - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * - * @return DataNumber - The number of remaining data units in the current - * DMAy Channelx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) -{ - return ((uint16_t)(DMAy_Channelx->CNTR)); -} - -/********************************************************************* - * @fn DMA_GetFlagStatus - * - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. - * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. - * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. - * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. - - * @return The new state of DMAy_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - tmpreg = DMA1->INTFR; - - if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearFlag - * - * @brief Clears the DMAy Channelx's pending flags. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. - * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. - * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. - * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. - * @return none - */ -void DMA_ClearFlag(uint32_t DMAy_FLAG) -{ - DMA1->INTFCR = DMAy_FLAG; -} - -/********************************************************************* - * @fn DMA_GetITStatus - * - * @brief Checks whether the specified DMAy Channelx interrupt has - * occurred or not. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * DMA2_IT_GL1 - DMA2 Channel1 global flag. - * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. - * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. - * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. - * @return The new state of DMAy_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMAy_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - tmpreg = DMA1->INTFR; - - if((tmpreg & DMAy_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearITPendingBit - * - * @brief Clears the DMAy Channelx's interrupt pending bits. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * DMA2_IT_GL1 - DMA2 Channel1 global flag. - * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. - * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. - * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. - * @return none - */ -void DMA_ClearITPendingBit(uint32_t DMAy_IT) -{ - DMA1->INTFCR = DMAy_IT; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_dma.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file provides all the DMA firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_dma.h" +#include "ch32v20x_rcc.h" + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel8) + { + DMA1->INTFCR |= DMA1_Channel8_IT_Mask; + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + DMA1->INTFCR = DMAy_FLAG; +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + DMA1->INTFCR = DMAy_IT; +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_exti.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_exti.c index 9d56c58..929e773 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_exti.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_exti.c @@ -1,180 +1,182 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_exti.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the EXTI firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - ***************************************************************************************/ -#include "ch32v20x_exti.h" - -/* No interrupt selected */ -#define EXTI_LINENONE ((uint32_t)0x00000) - -/********************************************************************* - * @fn EXTI_DeInit - * - * @brief Deinitializes the EXTI peripheral registers to their default - * reset values. - * - * @return none. - */ -void EXTI_DeInit(void) -{ - EXTI->INTENR = 0x00000000; - EXTI->EVENR = 0x00000000; - EXTI->RTENR = 0x00000000; - EXTI->FTENR = 0x00000000; - EXTI->INTFR = 0x000FFFFF; -} - -/********************************************************************* - * @fn EXTI_Init - * - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) -{ - uint32_t tmp = 0; - - tmp = (uint32_t)EXTI_BASE; - if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; - if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/********************************************************************* - * @fn EXTI_StructInit - * - * @brief Fills each EXTI_InitStruct member with its reset value. - * - * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/********************************************************************* - * @fn EXTI_GenerateSWInterrupt - * - * @brief Generates a Software interrupt. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none. - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - EXTI->SWIEVR |= EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetFlagStatus - * - * @brief Checks whether the specified EXTI line flag is set or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearFlag - * - * @brief Clears the EXTI's line pending flags. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetITStatus - * - * @brief Checks whether the specified EXTI line is asserted or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = EXTI->INTENR & EXTI_Line; - if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearITPendingBit - * - * @brief Clears the EXTI's line pending bits. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_exti.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file provides all the EXTI firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_exti.h" + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x000FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_flash.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_flash.c index e6b430f..659eafd 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_flash.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_flash.c @@ -1,965 +1,1232 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_flash.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the FLASH firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - ***************************************************************************************/ -#include "ch32v20x_flash.h" - -/* Flash Control Register bits */ -#define CR_PG_Set ((uint32_t)0x00000001) -#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) -#define CR_FAST_LOCK_Set ((uint32_t)0x00008000) -#define CR_PAGE_PG ((uint32_t)0x00010000) -#define CR_PAGE_ER ((uint32_t)0x00020000) -#define CR_BER32 ((uint32_t)0x00040000) -#define CR_BER64 ((uint32_t)0x00080000) -#define CR_PG_STRT ((uint32_t)0x00200000) - -/* FLASH Status Register bits */ -#define SR_BSY ((uint32_t)0x00000001) -#define SR_WR_BSY ((uint32_t)0x00000002) -#define SR_WRPRTERR ((uint32_t)0x00000010) -#define SR_EOP ((uint32_t)0x00000020) - -/* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) -#define OB_USER_BFB2 ((uint16_t)0x0008) - -/* FLASH Keys */ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) - -/* FLASH BANK address */ -#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) - -/* EEPROM address */ -#define EEPROM_ADDRESS ((uint32_t)0x8070000) - -/* Delay definition */ -#define EraseTimeout ((uint32_t)0x000B0000) -#define ProgramTimeout ((uint32_t)0x00005000) - -/********************************************************************* - * @fn FLASH_Unlock - * - * @brief Unlocks the FLASH Program Erase Controller. - * - * @return none - */ -void FLASH_Unlock(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -/********************************************************************* - * @fn FLASH_UnlockBank1 - * - * @brief Unlocks the FLASH Bank1 Program Erase Controller. - * equivalent to FLASH_Unlock function. - * - * @return none - */ -void FLASH_UnlockBank1(void) -{ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -/********************************************************************* - * @fn FLASH_Lock - * - * @brief Locks the FLASH Program Erase Controller. - * - * @return none - */ -void FLASH_Lock(void) -{ - FLASH->CTLR |= CR_LOCK_Set; -} - -/********************************************************************* - * @fn FLASH_LockBank1 - * - * @brief Locks the FLASH Bank1 Program Erase Controller. - * - * @return none - */ -void FLASH_LockBank1(void) -{ - FLASH->CTLR |= CR_LOCK_Set; -} - -/********************************************************************* - * @fn FLASH_ErasePage - * - * @brief Erases a specified FLASH page(page size 4KB). - * - * @param Page_Address - The page address to be erased. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_PER_Set; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_PER_Reset; - } - - return status; -} - -/********************************************************************* - * @fn FLASH_EraseAllPages - * - * @brief Erases all FLASH pages. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_MER_Set; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_MER_Reset; - } - - return status; -} - -/********************************************************************* - * @fn FLASH_EraseAllBank1Pages - * - * @brief Erases all Bank1 FLASH pages. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllBank1Pages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_MER_Set; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - FLASH->CTLR &= CR_MER_Reset; - } - return status; -} - -/********************************************************************* - * @fn FLASH_EraseOptionBytes - * - * @brief Erases the FLASH option bytes. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseOptionBytes(void) -{ - uint16_t rdptmp = RDP_Key; - uint32_t Address = 0x1FFFF800; - __IO uint8_t i; - - FLASH_Status status = FLASH_COMPLETE; - if(FLASH_GetReadOutProtectionStatus() != RESET) - { - rdptmp = 0x00; - } - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR &= CR_OPTER_Reset; - FLASH->CTLR |= CR_OPTPG_Set; - OB->RDPR = (uint16_t)rdptmp; - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - - /* Write 0xFF */ - FLASH->CTLR |= CR_OPTPG_Set; - - for(i = 0; i < 8; i++){ - *(uint16_t *)(Address + 2 * i) = 0x00FF; - while(FLASH->STATR & SR_BSY); - } - - FLASH->CTLR &= ~CR_OPTPG_Set; - } - return status; -} - -/********************************************************************* - * @fn FLASH_ProgramWord - * - * @brief Programs a word at a specified address. - * - * @param Address - specifies the address to be programmed. - * Data - specifies the data to be programmed. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_PG_Set; - - *(__IO uint16_t *)Address = (uint16_t)Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - tmp = Address + 2; - *(__IO uint16_t *)tmp = Data >> 16; - status = FLASH_WaitForLastOperation(ProgramTimeout); - FLASH->CTLR &= CR_PG_Reset; - } - else - { - FLASH->CTLR &= CR_PG_Reset; - } - } - - return status; -} - -/********************************************************************* - * @fn FLASH_ProgramHalfWord - * - * @brief Programs a half word at a specified address. - * - * @param Address - specifies the address to be programmed. - * Data - specifies the data to be programmed. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_PG_Set; - *(__IO uint16_t *)Address = Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - FLASH->CTLR &= CR_PG_Reset; - } - - return status; -} - -/********************************************************************* - * @fn FLASH_ProgramOptionByteData - * - * @brief Programs a half word at a specified Option Byte Data address. - * - * @param Address - specifies the address to be programmed. - * Data - specifies the data to be programmed. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t Addr = 0x1FFFF800; - __IO uint8_t i; - uint16_t pbuf[8]; - - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - - /* Read optionbytes */ - for(i = 0; i < 8; i++){ - pbuf[i] = *(uint16_t *)(Addr + 2 * i); - } - - /* Erase optionbytes */ - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY); - FLASH->CTLR &= ~CR_OPTER_Set; - - /* Write optionbytes */ - pbuf[((Address - 0x1FFFF800) / 2)] = ((((uint16_t) ~(Data)) << 8) | ((uint16_t)Data)); - - FLASH->CTLR |= CR_OPTPG_Set; - - for(i = 0; i < 8; i++){ - *(uint16_t *)(Addr + 2 * i) = pbuf[i]; - while(FLASH->STATR & SR_BSY) ; - } - - FLASH->CTLR &= ~CR_OPTPG_Set; - } - - return status; -} - -/********************************************************************* - * @fn FLASH_EnableWriteProtection - * - * @brief Write protects the desired sectors - * - * @param FLASH_Sectors - specifies the address of the pages to be write protected. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors) -{ - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; - FLASH_Status status = FLASH_COMPLETE; - uint32_t Addr = 0x1FFFF800; - __IO uint8_t i; - uint16_t pbuf[8]; - - FLASH_Sectors = (uint32_t)(~FLASH_Sectors); - WRP0_Data = (uint16_t)(FLASH_Sectors & WRP0_Mask); - WRP1_Data = (uint16_t)((FLASH_Sectors & WRP1_Mask) >> 8); - WRP2_Data = (uint16_t)((FLASH_Sectors & WRP2_Mask) >> 16); - WRP3_Data = (uint16_t)((FLASH_Sectors & WRP3_Mask) >> 24); - - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - - /* Read optionbytes */ - for(i = 0; i < 8; i++){ - pbuf[i] = *(uint16_t *)(Addr + 2 * i); - } - - /* Erase optionbytes */ - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY); - FLASH->CTLR &= ~CR_OPTER_Set; - - /* Write optionbytes */ - pbuf[4] = WRP0_Data; - pbuf[5] = WRP1_Data; - pbuf[6] = WRP2_Data; - pbuf[7] = WRP3_Data; - - FLASH->CTLR |= CR_OPTPG_Set; - for(i = 0; i < 8; i++){ - *(uint16_t *)(Addr + 2 * i) = pbuf[i]; - while(FLASH->STATR & SR_BSY); - } - FLASH->CTLR &= ~CR_OPTPG_Set; - } - return status; -} - -/********************************************************************* - * @fn FLASH_ReadOutProtection - * - * @brief Enables or disables the read out protection. - * - * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t Addr = 0x1FFFF800; - __IO uint8_t i; - uint16_t pbuf[8]; - - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - - /* Read optionbytes */ - for(i = 0; i < 8; i++){ - pbuf[i] = *(uint16_t *)(Addr + 2 * i); - } - - /* Erase optionbytes */ - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY); - FLASH->CTLR &= ~CR_OPTER_Set; - - /* Write optionbytes */ - if(NewState == DISABLE) - pbuf[0] = 0x5AA5; - else - pbuf[0] = 0x00FF; - - FLASH->CTLR |= CR_OPTPG_Set; - for(i = 0; i < 8; i++){ - *(uint16_t *)(Addr + 2 * i) = pbuf[i]; - while(FLASH->STATR & SR_BSY); - } - FLASH->CTLR &= ~CR_OPTPG_Set; - } - return status; -} - -/********************************************************************* - * @fn FLASH_UserOptionByteConfig - * - * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. - * - * @param OB_IWDG - Selects the IWDG mode - * OB_IWDG_SW - Software IWDG selected - * OB_IWDG_HW - Hardware IWDG selected - * OB_STOP - Reset event when entering STOP mode. - * OB_STOP_NoRST - No reset generated when entering in STOP - * OB_STOP_RST - Reset generated when entering in STOP - * OB_STDBY - Reset event when entering Standby mode. - * OB_STDBY_NoRST - No reset generated when entering in STANDBY - * OB_STDBY_RST - Reset generated when entering in STANDBY - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t Addr = 0x1FFFF800; - __IO uint8_t i; - uint16_t pbuf[8]; - - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Read optionbytes */ - for(i = 0; i < 8; i++){ - pbuf[i] = *(uint16_t *)(Addr + 2 * i); - } - - /* Erase optionbytes */ - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY); - FLASH->CTLR &= ~CR_OPTER_Set; - - /* Write optionbytes */ - pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); - - FLASH->CTLR |= CR_OPTPG_Set; - for(i = 0; i < 8; i++){ - *(uint16_t *)(Addr + 2 * i) = pbuf[i]; - while(FLASH->STATR & SR_BSY); - } - FLASH->CTLR &= ~CR_OPTPG_Set; - } - return status; -} - -/********************************************************************* - * @fn FLASH_GetUserOptionByte - * - * @brief Returns the FLASH User Option Bytes values. - * - * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint32_t FLASH_GetUserOptionByte(void) -{ - return (uint32_t)(FLASH->OBR >> 2); -} - -/********************************************************************* - * @fn FLASH_GetWriteProtectionOptionByte - * - * @brief Returns the FLASH Write Protection Option Bytes Register value. - * - * @return The FLASH Write Protection Option Bytes Register value. - */ -uint32_t FLASH_GetWriteProtectionOptionByte(void) -{ - return (uint32_t)(FLASH->WPR); -} - -/********************************************************************* - * @fn FLASH_GetReadOutProtectionStatus - * - * @brief Checks whether the FLASH Read Out Protection Status is set or not. - * - * @return FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetReadOutProtectionStatus(void) -{ - FlagStatus readoutstatus = RESET; - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - readoutstatus = SET; - } - else - { - readoutstatus = RESET; - } - return readoutstatus; -} - -/********************************************************************* - * @fn FLASH_ITConfig - * - * @brief Enables or disables the specified FLASH interrupts. - * - * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. - * FLASH_IT_ERROR - FLASH Error Interrupt - * FLASH_IT_EOP - FLASH end of operation Interrupt - * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). - * - * @return FLASH Prefetch Buffer Status (SET or RESET). - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - FLASH->CTLR |= FLASH_IT; - } - else - { - FLASH->CTLR &= ~(uint32_t)FLASH_IT; - } -} - -/********************************************************************* - * @fn FLASH_GetFlagStatus - * - * @brief Checks whether the specified FLASH flag is set or not. - * - * @param FLASH_FLAG - specifies the FLASH flag to check. - * FLASH_FLAG_BSY - FLASH Busy flag - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * FLASH_FLAG_OPTERR - FLASH Option Byte error flag - * - * @return The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - return bitstatus; -} - -/********************************************************************* - * @fn FLASH_ClearFlag - * - * @brief Clears the FLASH's pending flags. - * - * @param FLASH_FLAG - specifies the FLASH flags to clear. - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * - * @return none - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - FLASH->STATR = FLASH_FLAG; -} - -/********************************************************************* - * @fn FLASH_GetStatus - * - * @brief Returns the FLASH Status. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_GetBank1Status - * - * @brief Returns the FLASH Bank1 Status. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetBank1Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_WaitForLastOperation - * - * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_WaitForLastBank1Operation - * - * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_Unlock_Fast - * - * @brief Unlocks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Unlock_Fast(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - - /* Fast program mode unlock */ - FLASH->MODEKEYR = FLASH_KEY1; - FLASH->MODEKEYR = FLASH_KEY2; -} - -/********************************************************************* - * @fn FLASH_Lock_Fast - * - * @brief Locks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Lock_Fast(void) -{ - FLASH->CTLR |= CR_LOCK_Set; -} - -/********************************************************************* - * @fn FLASH_ErasePage_Fast - * - * @brief Erases a specified FLASH page (1page = 256Byte). - * - * @param Page_Address - The page address to be erased. - * - * @return none - */ -void FLASH_ErasePage_Fast(uint32_t Page_Address) -{ - Page_Address &= 0xFFFFFF00; - - FLASH->CTLR |= CR_PAGE_ER; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY); - FLASH->CTLR &= ~CR_PAGE_ER; -} - -/********************************************************************* - * @fn FLASH_EraseBlock_32K_Fast - * - * @brief Erases a specified FLASH Block (1Block = 32KByte). - * - * @param Block_Address - The block address to be erased. - * - * @return none - */ -void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) -{ - Block_Address &= 0xFFFF8000; - - FLASH->CTLR |= CR_BER32; - FLASH->ADDR = Block_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY); - FLASH->CTLR &= ~CR_BER32; -} - -/********************************************************************* - * @fn FLASH_EraseBlock_64K_Fast - * - * @brief Erases a specified FLASH Block (1Block = 64KByte). - * - * @param Block_Address - The block address to be erased. - * - * @return none - */ -void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address) -{ - Block_Address &= 0xFFFF0000; - - FLASH->CTLR |= CR_BER64; - FLASH->ADDR = Block_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY); - FLASH->CTLR &= ~CR_BER64; -} - -/********************************************************************* - * @fn FLASH_ProgramPage_Fast - * - * @brief Program a specified FLASH page (1page = 256Byte). - * - * @param Page_Address - The page address to be programed. - * - * @return none - */ -void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf) -{ - uint8_t size = 64; - - Page_Address &= 0xFFFFFF00; - - FLASH->CTLR |= CR_PAGE_PG; - while(FLASH->STATR & SR_BSY); - while(FLASH->STATR & SR_WR_BSY); - - while(size) - { - *(uint32_t *)Page_Address = *(uint32_t *)pbuf; - Page_Address += 4; - pbuf += 1; - size -= 1; - while(FLASH->STATR & SR_WR_BSY); - } - - FLASH->CTLR |= CR_PG_STRT; - while(FLASH->STATR & SR_BSY); - FLASH->CTLR &= ~CR_PAGE_PG; -} - -/********************************************************************* - * @fn FLASH_Access_Clock_Cfg - * - * @brief Config FLASH Access Clock(Need to unlock ) - * - * @param FLASH_Access_CLK - - * FLASH_Access_SYSTEM_HALF - System clock/2 - * FLASH_Access_SYSTEM - System clock - * - * @return none - */ -void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK) -{ - FLASH->CTLR &= ~(1 << 25); - FLASH->CTLR |= FLASH_Access_CLK; -} - -/********************************************************************* - * @fn FLASH_Enhance_Mode - * - * @brief Read FLASH Enhance Mode - * - * @param - * Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). - * - * @return none - */ -void FLASH_Enhance_Mode(FunctionalState NewState) -{ - if(NewState) - { - FLASH->CTLR |= (1 << 24); - } - else - { - FLASH->CTLR &= ~(1 << 24); - FLASH->CTLR |= (1 << 22); - } -} - -/******************************************************************************** - * @fn FLASH_GetMACAddress - * - * @brief Get MAC address - * - * @param *Buffer: Mac address - * - * @return None - */ -void FLASH_GetMACAddress(uint8_t *Buffer) -{ - uint32_t value; - - value = *(uint32_t *)(0x1FFFF7E8); - Buffer[0] = value & 0xFF; - Buffer[1] = (value >> 8) & 0xFF; - Buffer[2] = (value >> 16) & 0xFF; - Buffer[3] = (value >> 24) & 0xFF; - value = *(uint32_t *)(0x1FFFF7EC); - Buffer[4] = value & 0xFF; - Buffer[5] = (value >> 8) & 0xFF; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_flash.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file provides all the FLASH firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_flash.h" + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FLOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BER32 ((uint32_t)0x00040000) +#define CR_PG_STRT ((uint32_t)0x00200000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WR_BSY ((uint32_t)0x00000002) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* EEPROM address */ +#define EEPROM_ADDRESS ((uint32_t)0x8070000) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00005000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +#define ValidAddrEnd (FLASH_BASE + 0x78000) +#else +#define ValidAddrEnd (FLASH_BASE + 0x38000) +#endif + +/* FLASH Size */ +#define Size_256B 0x100 +#define Size_4KB 0x1000 +#define Size_32KB 0x8000 + +/********************************************************************* + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program Erase Controller. + * + * @return none + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_UnlockBank1 + * + * @brief Unlocks the FLASH Bank1 Program Erase Controller. + * equivalent to FLASH_Unlock function. + * + * @return none + */ +void FLASH_UnlockBank1(void) +{ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return none + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/********************************************************************* + * @fn FLASH_LockBank1 + * + * @brief Locks the FLASH Bank1 Program Erase Controller. + * + * @return none + */ +void FLASH_LockBank1(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/********************************************************************* + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page(page size 4KB). + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EraseAllBank1Pages + * + * @brief Erases all Bank1 FLASH pages. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank1Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + return status; +} + +/********************************************************************* + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + uint32_t Address = 0x1FFFF800; + __IO uint8_t i; + + FLASH_Status status = FLASH_COMPLETE; + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= CR_OPTER_Reset; + FLASH->CTLR |= CR_OPTPG_Set; + OB->RDPR = (uint16_t)rdptmp; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + + /* Write 0xFF */ + FLASH->CTLR |= CR_OPTPG_Set; + + for(i = 0; i < 8; i++){ + *(uint16_t *)(Address + 2 * i) = 0x00FF; + while(FLASH->STATR & SR_BSY); + } + + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramWord + * + * @brief Programs a word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + + *(__IO uint16_t *)Address = (uint16_t)Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + tmp = Address + 2; + *(__IO uint16_t *)tmp = Data >> 16; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + else + { + FLASH->CTLR &= CR_PG_Reset; + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramHalfWord + * + * @brief Programs a half word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + *(__IO uint16_t *)Address = Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramOptionByteData + * + * @brief Programs a half word at a specified Option Byte Data address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++){ + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY); + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[((Address - 0x1FFFF800) / 2)] = ((((uint16_t) ~(Data)) << 8) | ((uint16_t)Data)); + + FLASH->CTLR |= CR_OPTPG_Set; + + for(i = 0; i < 8; i++){ + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) ; + } + + FLASH->CTLR &= ~CR_OPTPG_Set; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Sectors - specifies the address of the pages to be write protected. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + FLASH_Sectors = (uint32_t)(~FLASH_Sectors); + WRP0_Data = (uint16_t)(FLASH_Sectors & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Sectors & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Sectors & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Sectors & WRP3_Mask) >> 24); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++){ + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY); + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[4] = WRP0_Data; + pbuf[5] = WRP1_Data; + pbuf[6] = WRP2_Data; + pbuf[7] = WRP3_Data; + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++){ + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY); + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_ReadOutProtection + * + * @brief Enables or disables the read out protection. + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++){ + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY); + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + if(NewState == DISABLE) + pbuf[0] = 0x5AA5; + else + pbuf[0] = 0x00FF; + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++){ + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY); + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. + * + * @param OB_IWDG - Selects the IWDG mode + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STOP - Reset event when entering STOP mode. + * OB_STOP_NoRST - No reset generated when entering in STOP + * OB_STOP_RST - Reset generated when entering in STOP + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY + * OB_STDBY_RST - Reset generated when entering in STANDBY + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + uint16_t temp; + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Read optionbytes */ + for(i = 0; i < 8; i++){ + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + temp=pbuf[1]&(~0x7); + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY); + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)temp))); + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++){ + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY); + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt + * FLASH_IT_EOP - FLASH end of operation Interrupt + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + FLASH->STATR = FLASH_FLAG; +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_FLOCK_Set; +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + Page_Address &= 0xFFFFFF00; + + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY); + FLASH->CTLR &= ~CR_PAGE_ER; +} + +/********************************************************************* + * @fn FLASH_EraseBlock_32K_Fast + * + * @brief Erases a specified FLASH Block (1Block = 32KByte). + * + * @param Block_Address - The block address to be erased. + * + * @return none + */ +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) +{ + Block_Address &= 0xFFFF8000; + + FLASH->CTLR |= CR_BER32; + FLASH->ADDR = Block_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY); + FLASH->CTLR &= ~CR_BER32; +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf) +{ + uint8_t size = 64; + + Page_Address &= 0xFFFFFF00; + + FLASH->CTLR |= CR_PAGE_PG; + while(FLASH->STATR & SR_BSY); + while(FLASH->STATR & SR_WR_BSY); + + while(size) + { + *(uint32_t *)Page_Address = *(uint32_t *)pbuf; + Page_Address += 4; + pbuf += 1; + size -= 1; + while(FLASH->STATR & SR_WR_BSY); + } + + FLASH->CTLR |= CR_PG_STRT; + while(FLASH->STATR & SR_BSY); + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_Access_Clock_Cfg + * + * @brief Config FLASH Access Clock(Need to unlock ) + * + * @param FLASH_Access_CLK - + * FLASH_Access_SYSTEM_HALF - System clock/2 + * FLASH_Access_SYSTEM - System clock + * + * @return none + */ +void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK) +{ + FLASH->CTLR &= ~(1 << 25); + FLASH->CTLR |= FLASH_Access_CLK; +} + +/********************************************************************* + * @fn FLASH_Enhance_Mode + * + * @brief Read FLASH Enhance Mode + * + * @param + * Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return none + */ +void FLASH_Enhance_Mode(FunctionalState NewState) +{ + if(NewState) + { + FLASH->CTLR |= (1 << 24); + } + else + { + FLASH->CTLR &= ~(1 << 24); + FLASH->CTLR |= (1 << 22); + } +} + +/******************************************************************************** + * @fn FLASH_GetMACAddress + * + * @brief Get MAC address + * + * @param *Buffer: Mac address + * + * @return None + */ +void FLASH_GetMACAddress(uint8_t *Buffer) +{ + uint32_t value; + + value = *(uint32_t *)(0x1FFFF7E8); + Buffer[0] = value & 0xFF; + Buffer[1] = (value >> 8) & 0xFF; + Buffer[2] = (value >> 16) & 0xFF; + Buffer[3] = (value >> 24) & 0xFF; + value = *(uint32_t *)(0x1FFFF7EC); + Buffer[4] = value & 0xFF; + Buffer[5] = (value >> 8) & 0xFF; +} + +/********************************************************************* + * @fn ROM_ERASE + * + * @brief Select erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Cnt - Erases count. + * Erase_Size - Erases size select.The returned value can be: + * Size_32KB, Size_4KB, Size_256B. + * + * @return none. + */ +static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) +{ + do{ + if(Erase_Size == Size_32KB) + { + FLASH->CTLR |= CR_BER32; + } + else if(Erase_Size == Size_4KB) + { + FLASH->CTLR |= CR_PER_Set; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR |= CR_PAGE_ER; + } + + FLASH->ADDR = StartAddr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + + if(Erase_Size == Size_32KB) + { + FLASH->CTLR &= ~CR_BER32; + StartAddr += Size_32KB; + } + else if(Erase_Size == Size_4KB) + { + FLASH->CTLR &= ~CR_PER_Set; + StartAddr += Size_4KB; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR &= ~CR_PAGE_ER; + StartAddr += Size_256B; + } + }while(--Cnt); +} + +/********************************************************************* + * @fn FLASH_ROM_ERASE + * + * @brief Erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Length - Erases Flash start Length(Length%256 == 0). + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length) +{ + uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + Addr0 = StartAddr; + + if(Length >= Size_32KB) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_4KB) + { + Length0 = Size_4KB - (Addr0 & (Size_4KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_256B) + { + Length0 = Length; + } + + /* Erase 32KB */ + if(Length0 >= Size_32KB)//front + { + Length = Length0; + if(Addr0 & (Size_32KB - 1)) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB); + } + + if(Length1 >= Size_32KB)//back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_32KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1))); + Length1 = (StartAddr + Length1) & (Size_32KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB); + } + + /* Erase 4KB */ + if(Length0 >= Size_4KB) //front + { + Length = Length0; + if(Addr0 & (Size_4KB - 1)) + { + Length0 = Size_4KB - (Addr0 & (Size_4KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 12), Size_4KB); + } + + if(Length1 >= Size_4KB) //back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_4KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_4KB - 1))); + Length1 = (StartAddr + Length1) & (Size_4KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 12), Size_4KB); + } + + /* Erase 256B */ + if(Length0)//front + { + ROM_ERASE(Addr0, (Length0 >> 8), Size_256B); + } + + if(Length1)//back + { + ROM_ERASE(Addr1, (Length1 >> 8), Size_256B); + } + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + +/********************************************************************* + * @fn FLASH_ROM_WRITE + * + * @brief Writes a specified FLASH . + * + * @param StartAddr - Writes Flash start address(StartAddr%256 == 0). + * Length - Writes Flash start Length(Length%256 == 0). + * pbuf - Writes Flash value buffer. + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length) +{ + uint32_t i; + uint8_t size; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + i = Length >> 8; + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + do{ + FLASH->CTLR |= CR_PAGE_PG; + while(FLASH->STATR & SR_BSY) + ; + while(FLASH->STATR & SR_WR_BSY) + ; + size = 64; + while(size) + { + *(uint32_t *)StartAddr = *(uint32_t *)pbuf; + StartAddr += 4; + pbuf += 1; + size -= 1; + while(FLASH->STATR & SR_WR_BSY) + ; + } + + FLASH->CTLR |= CR_PG_STRT; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + }while(--i); + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_gpio.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_gpio.c index c7f3805..4a089d2 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_gpio.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_gpio.c @@ -1,671 +1,999 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_gpio.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the GPIO firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include "ch32v20x_gpio.h" -#include "ch32v20x_rcc.h" - -/* MASK */ -#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) - -#if defined (CH32V20x_D6) -uint8_t MCU_Version = 0; -#endif - -/********************************************************************* - * @fn GPIO_DeInit - * - * @brief Deinitializes the GPIOx peripheral registers to their default - * reset values. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @return none - */ -void GPIO_DeInit(GPIO_TypeDef *GPIOx) -{ - if(GPIOx == GPIOA) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); - } - else if(GPIOx == GPIOB) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); - } - else if(GPIOx == GPIOC) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); - } - else if(GPIOx == GPIOD) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); - } - else if(GPIOx == GPIOE) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); - } -} - -/********************************************************************* - * @fn GPIO_AFIODeInit - * - * @brief Deinitializes the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * - * @return none - */ -void GPIO_AFIODeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); -} - -/********************************************************************* - * @fn GPIO_Init - * - * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. - * - * @return none - */ -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - - if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - { - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } -#if defined (CH32V20x_D6) - if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0) - { - MCU_Version = 1; - } - - if((GPIOx == GPIOC) && MCU_Version){ - GPIO_InitStruct->GPIO_Pin = GPIO_InitStruct->GPIO_Pin >> 13; - } - -#endif - if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) - { - tmpreg = GPIOx->CFGLR; - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << pinpos); - } - else - { - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CFGLR = tmpreg; - } - - if(GPIO_InitStruct->GPIO_Pin > 0x00FF) - { - tmpreg = GPIOx->CFGHR; - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x08)); - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - } - } - GPIOx->CFGHR = tmpreg; - } -} - -/********************************************************************* - * @fn GPIO_StructInit - * - * @brief Fills each GPIO_InitStruct member with its default - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) -{ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/********************************************************************* - * @fn GPIO_ReadInputDataBit - * - * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @param GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * - * @return The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - -#if defined (CH32V20x_D6) - if((GPIOx == GPIOC) && MCU_Version){ - GPIO_Pin = GPIO_Pin >> 13; - } - -#endif - - if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadInputData - * - * @brief Reads the specified GPIO input data port. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @return The output port pin value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) -{ - uint16_t val; - -#if defined (CH32V20x_D6) - if((GPIOx == GPIOC) && MCU_Version){ - val = ( uint16_t )(GPIOx->INDR << 13); - } - else{ - val = ( uint16_t )GPIOx->INDR; - } - -#else - val = ( uint16_t )GPIOx->INDR; -#endif - -return ( val ); -} - -/********************************************************************* - * @fn GPIO_ReadOutputDataBit - * - * @brief Reads the specified output data port bit. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - -#if defined (CH32V20x_D6) - if((GPIOx == GPIOC) && MCU_Version){ - GPIO_Pin = GPIO_Pin >> 13; - } - -#endif - - if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadOutputData - * - * @brief Reads the specified GPIO output data port. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @return GPIO output port pin value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) -{ - uint16_t val; - -#if defined (CH32V20x_D6) - if((GPIOx == GPIOC) && MCU_Version){ - val = ( uint16_t )(GPIOx->OUTDR << 13); - } - else{ - val = ( uint16_t )GPIOx->OUTDR; - } - -#else - val = ( uint16_t )GPIOx->OUTDR; -#endif - - return ( val ); -} - -/********************************************************************* - * @fn GPIO_SetBits - * - * @brief Sets the selected data port bits. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ -#if defined (CH32V20x_D6) - if((GPIOx == GPIOC) && MCU_Version){ - GPIO_Pin = GPIO_Pin >> 13; - } - -#endif - - GPIOx->BSHR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_ResetBits - * - * @brief Clears the selected data port bits. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ -#if defined (CH32V20x_D6) - if((GPIOx == GPIOC) && MCU_Version){ - GPIO_Pin = GPIO_Pin >> 13; - } - -#endif - - GPIOx->BCR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_WriteBit - * - * @brief Sets or clears the selected data port bit. - * - * @param GPIO_Pin - specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * BitVal - specifies the value to be written to the selected bit. - * Bit_SetL - to clear the port pin. - * Bit_SetH - to set the port pin. - * - * @return none - */ -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ -#if defined (CH32V20x_D6) - if((GPIOx == GPIOC) && MCU_Version){ - GPIO_Pin = GPIO_Pin >> 13; - } - -#endif - - if(BitVal != Bit_RESET) - { - GPIOx->BSHR = GPIO_Pin; - } - else - { - GPIOx->BCR = GPIO_Pin; - } -} - -/********************************************************************* - * @fn GPIO_Write - * - * @brief Writes data to the specified GPIO data port. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * PortVal - specifies the value to be written to the port output data register. - * - * @return none - */ -void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) -{ -#if defined (CH32V20x_D6) - if((GPIOx == GPIOC) && MCU_Version){ - PortVal = PortVal >> 13; - } - -#endif - - GPIOx->OUTDR = PortVal; -} - -/********************************************************************* - * @fn GPIO_PinLockConfig - * - * @brief Locks GPIO Pins configuration registers. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - -#if defined (CH32V20x_D6) - if((GPIOx == GPIOC) && MCU_Version){ - GPIO_Pin = GPIO_Pin >> 13; - } - -#endif - - tmp |= GPIO_Pin; - GPIOx->LCKR = tmp; - GPIOx->LCKR = GPIO_Pin; - GPIOx->LCKR = tmp; - tmp = GPIOx->LCKR; - tmp = GPIOx->LCKR; -} - -/********************************************************************* - * @fn GPIO_EventOutputConfig - * - * @brief Selects the GPIO pin used as Event output. - * - * @param GPIO_PortSource - selects the GPIO port to be used as source - * for Event output. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). - * GPIO_PinSource - specifies the pin for the Event output. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * - * @return none - */ -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmpreg = 0x00; - - tmpreg = AFIO->ECR; - tmpreg &= ECR_PORTPINCONFIG_MASK; - tmpreg |= (uint32_t)GPIO_PortSource << 0x04; - tmpreg |= GPIO_PinSource; - AFIO->ECR = tmpreg; -} - -/********************************************************************* - * @fn GPIO_EventOutputCmd - * - * @brief Enables or disables the Event Output. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void GPIO_EventOutputCmd(FunctionalState NewState) -{ - if(NewState) - { - AFIO->ECR |= (1 << 7); - } - else - { - AFIO->ECR &= ~(1 << 7); - } -} - -/********************************************************************* - * @fn GPIO_PinRemapConfig - * - * @brief Changes the mapping of the specified pin. - * - * @param GPIO_Remap - selects the pin to remap. - * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping - * GPIO_Remap_I2C1 - I2C1 Alternate Function mapping - * GPIO_Remap_USART1 - USART1 Alternate Function mapping - * GPIO_Remap_USART2 - USART2 Alternate Function mapping - * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping - * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping - * GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping - * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping - * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping - * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping - * GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping - * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping - * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping - * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping - * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping - * GPIO_Remap_PD01 - PD01 Alternate Function mapping - * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping - * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping - * GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping - * GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping - * GPIO_Remap_ETH - Ethernet remapping - * GPIO_Remap_CAN2 - CAN2 remapping - * GPIO_Remap_MII_RMII_SEL - MII or RMII selection - * GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST - * GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled - * GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP) - * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected - * to TIM2 Internal Trigger 1 for calibration - * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) - * GPIO_Remap_TIM8 - TIM8 Alternate Function mapping - * GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping - * GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping - * GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping - * GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping - * GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping - * GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping - * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping - * GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping - * GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping - * GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping - * GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping - * GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping - * GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping - * GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping - * GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping - * GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) -{ - uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - tmpreg = AFIO->PCFR2; - } - else - { - tmpreg = AFIO->PCFR1; - -#if defined (CH32V20x_D6) || defined (CH32V20x_D8) - if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0){ - tmpreg = ((tmpreg>>1)&0xFFFFE000)|(tmpreg&0x00001FFF); - } - -#endif - } - - tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - tmp = GPIO_Remap & LSB_MASK; - - /* Clear bit */ - if((GPIO_Remap & 0x80000000) == 0x80000000) - { /* PCFR2 */ - if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */ - { - tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10); - tmpreg &= ~tmp1; - } - else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - } - else /* [31:0] 1bit */ - { - tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); - } - } - else - { /* PCFR1 */ - if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */ - { - tmpreg &= DBGAFR_SWJCFG_MASK; - AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; - } - else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - else /* [31:0] 1bit */ - { - tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - } - - /* Set bit */ - if(NewState != DISABLE) - { - tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); - } - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - AFIO->PCFR2 = tmpreg; - } - else - { - AFIO->PCFR1 = tmpreg; - } -} - -/********************************************************************* - * @fn GPIO_EXTILineConfig - * - * @brief Selects the GPIO pin used as EXTI Line. - * - * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). - * GPIO_PinSource - specifies the EXTI line to be configured. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * - * @return none - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmp = 0x00; - -#if defined (CH32V20x_D6) - if((GPIO_PortSource == GPIO_PortSourceGPIOC) && MCU_Version){ - GPIO_PinSource -= 13; - } - -#endif - - tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); - AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; - AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); -} - -/********************************************************************* - * @fn GPIO_ETH_MediaInterfaceConfig - * - * @brief Selects the Ethernet media interface. - * - * @param GPIO_ETH_MediaInterface - specifies the Media Interface mode. - * GPIO_ETH_MediaInterface_MII - MII mode - * GPIO_ETH_MediaInterface_RMII - RMII mode - * - * @return none - */ -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) -{ - if(GPIO_ETH_MediaInterface) - { - AFIO->PCFR1 |= (1 << 23); - } - else - { - AFIO->PCFR1 &= ~(1 << 23); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_gpio.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/06 + * Description : This file provides all the GPIO firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32v20x_gpio.h" +#include "ch32v20x_rcc.h" + +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +#if defined (CH32V20x_D6) +uint8_t MCU_Version = 0; +#endif + +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if(GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } +#if defined (CH32V20x_D6) + if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0) + { + MCU_Version = 1; + } + + if((GPIOx == GPIOC) && MCU_Version){ + GPIO_InitStruct->GPIO_Pin = GPIO_InitStruct->GPIO_Pin >> 13; + } + +#endif + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } + + if(GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CFGHR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CFGHR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + +#if defined (CH32V20x_D6) + if((GPIOx == GPIOC) && MCU_Version){ + GPIO_Pin = GPIO_Pin >> 13; + } + +#endif + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return The output port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + uint16_t val; + +#if defined (CH32V20x_D6) + if((GPIOx == GPIOC) && MCU_Version){ + val = ( uint16_t )(GPIOx->INDR << 13); + } + else{ + val = ( uint16_t )GPIOx->INDR; + } + +#else + val = ( uint16_t )GPIOx->INDR; +#endif + +return ( val ); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + +#if defined (CH32V20x_D6) + if((GPIOx == GPIOC) && MCU_Version){ + GPIO_Pin = GPIO_Pin >> 13; + } + +#endif + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + uint16_t val; + +#if defined (CH32V20x_D6) + if((GPIOx == GPIOC) && MCU_Version){ + val = ( uint16_t )(GPIOx->OUTDR << 13); + } + else{ + val = ( uint16_t )GPIOx->OUTDR; + } + +#else + val = ( uint16_t )GPIOx->OUTDR; +#endif + + return ( val ); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ +#if defined (CH32V20x_D6) + if((GPIOx == GPIOC) && MCU_Version){ + GPIO_Pin = GPIO_Pin >> 13; + } + +#endif + + GPIOx->BSHR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ +#if defined (CH32V20x_D6) + if((GPIOx == GPIOC) && MCU_Version){ + GPIO_Pin = GPIO_Pin >> 13; + } + +#endif + + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * BitVal - specifies the value to be written to the selected bit. + * Bit_RESET - to clear the port pin. + * Bit_SET - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ +#if defined (CH32V20x_D6) + if((GPIOx == GPIOC) && MCU_Version){ + GPIO_Pin = GPIO_Pin >> 13; + } + +#endif + + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = GPIO_Pin; + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ +#if defined (CH32V20x_D6) + if((GPIOx == GPIOC) && MCU_Version){ + PortVal = PortVal >> 13; + } + +#endif + + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + +#if defined (CH32V20x_D6) + if((GPIOx == GPIOC) && MCU_Version){ + GPIO_Pin = GPIO_Pin >> 13; + } + +#endif + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_EventOutputConfig + * + * @brief Selects the GPIO pin used as Event output. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * GPIO_PinSource - specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + + tmpreg = AFIO->ECR; + tmpreg &= ECR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->ECR = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EventOutputCmd + * + * @brief Enables or disables the Event Output. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + if(NewState) + { + AFIO->ECR |= (1 << 7); + } + else + { + AFIO->ECR &= ~(1 << 7); + } +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping + * GPIO_Remap_I2C1 - I2C1 Alternate Function mapping + * GPIO_Remap_USART1 - USART1 Alternate Function mapping + * GPIO_Remap_USART2 - USART2 Alternate Function mapping + * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping + * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping + * GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping + * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping + * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping + * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap_PD0PD1 - PD0 and PD1 Alternate Function mapping + * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping + * GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping + * GPIO_Remap_ETH - Ethernet remapping + * GPIO_Remap_CAN2 - CAN2 remapping + * GPIO_Remap_MII_RMII_SEL - MII or RMII selection + * GPIO_Remap_SWJ_Disable - Full SWJ Disabled + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected + * to TIM2 Internal Trigger 1 for calibration + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) + * GPIO_Remap_TIM8 - TIM8 Alternate Function mapping + * GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping + * GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping + * GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping + * GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping + * GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping + * GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping + * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping + * GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping + * GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping + * GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping + * GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping + * GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping + * GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping + * GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping + * GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping + * GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->PCFR2; + } + else + { + tmpreg = AFIO->PCFR1; + + if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0){ + tmpreg = ((tmpreg>>1)&0xFFFFE000)|(tmpreg&0x00001FFF); + } + + } + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + /* Clear bit */ + if((GPIO_Remap & 0x80000000) == 0x80000000) + { /* PCFR2 */ + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */ + { + tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10); + tmpreg &= ~tmp1; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + } + else /* [31:0] 1bit */ + { + tmpreg &= ~(tmp << (((GPIO_Remap & 0x7FFFFFFF ) >> 0x15) * 0x10)); + } + } + else + { /* PCFR1 */ + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */ + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else /* [31:0] 1bit */ + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg |= (tmp << (((GPIO_Remap & 0x7FFFFFFF )>> 0x15) * 0x10)); + } + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->PCFR2 = tmpreg; + } + else + { + AFIO->PCFR1 = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/********************************************************************* + * @fn GPIO_ETH_MediaInterfaceConfig + * + * @brief Selects the Ethernet media interface. + * + * @param GPIO_ETH_MediaInterface - specifies the Media Interface mode. + * GPIO_ETH_MediaInterface_MII - MII mode + * GPIO_ETH_MediaInterface_RMII - RMII mode + * + * @return none + */ +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) +{ + if(GPIO_ETH_MediaInterface) + { + AFIO->PCFR1 |= (1 << 23); + } + else + { + AFIO->PCFR1 &= ~(1 << 23); + } +} + +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-up. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB \ + | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD|RCC_APB2Periph_AFIO,ENABLE); + chip = *( uint32_t * )0x1FFFF704 & (~0x000000F0); + switch(chip) + { +#ifdef CH32V20x_D6 + case 0x20370500: //CH32V203F6P6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x203A0500: //CH32V203F8P6 + { + GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x203E0500: //CH32V203F8U6 + { + GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_12|GPIO_Pin_13; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x20360500: //CH32V203G6U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x203B0500: //CH32V203G8R6 + { + GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x20320500: //CH32V203K8T6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x20330500: //CH32V203C6T6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x20310500: //CH32V203C8T6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x20300500: //CH32V203C8U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } +#elif defined(CH32V20x_D8) + case 0x2034050C: //CH32V203RBT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } +#elif defined(CH32V20x_D8W) + case 0x2083050C: //CH32V208GBU6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x2082050C: //CH32V208CBU6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x2081050C: //CH32V208RBT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } +#endif + default: + { + break; + } + } +} \ No newline at end of file diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_i2c.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_i2c.c index 3040b1f..e4af3fb 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_i2c.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_i2c.c @@ -1,972 +1,1012 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_i2c.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the I2C firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include "ch32v20x_i2c.h" -#include "ch32v20x_rcc.h" - -/* I2C SPE mask */ -#define CTLR1_PE_Set ((uint16_t)0x0001) -#define CTLR1_PE_Reset ((uint16_t)0xFFFE) - -/* I2C START mask */ -#define CTLR1_START_Set ((uint16_t)0x0100) -#define CTLR1_START_Reset ((uint16_t)0xFEFF) - -/* I2C STOP mask */ -#define CTLR1_STOP_Set ((uint16_t)0x0200) -#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) - -/* I2C ACK mask */ -#define CTLR1_ACK_Set ((uint16_t)0x0400) -#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) - -/* I2C ENGC mask */ -#define CTLR1_ENGC_Set ((uint16_t)0x0040) -#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) - -/* I2C SWRST mask */ -#define CTLR1_SWRST_Set ((uint16_t)0x8000) -#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) - -/* I2C PEC mask */ -#define CTLR1_PEC_Set ((uint16_t)0x1000) -#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) - -/* I2C ENPEC mask */ -#define CTLR1_ENPEC_Set ((uint16_t)0x0020) -#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) - -/* I2C ENARP mask */ -#define CTLR1_ENARP_Set ((uint16_t)0x0010) -#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) - -/* I2C NOSTRETCH mask */ -#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) -#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) - -/* I2C registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) - -/* I2C DMAEN mask */ -#define CTLR2_DMAEN_Set ((uint16_t)0x0800) -#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) - -/* I2C LAST mask */ -#define CTLR2_LAST_Set ((uint16_t)0x1000) -#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) - -/* I2C FREQ mask */ -#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) - -/* I2C ADD0 mask */ -#define OADDR1_ADD0_Set ((uint16_t)0x0001) -#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) - -/* I2C ENDUAL mask */ -#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) -#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) - -/* I2C ADD2 mask */ -#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) - -/* I2C F/S mask */ -#define CKCFGR_FS_Set ((uint16_t)0x8000) - -/* I2C CCR mask */ -#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) - -/* I2C FLAG mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) - -/* I2C Interrupt Enable mask */ -#define ITEN_Mask ((uint32_t)0x07000000) - -/********************************************************************* - * @fn I2C_DeInit - * - * @brief Deinitializes the I2Cx peripheral registers to their default - * reset values. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return none - */ -void I2C_DeInit(I2C_TypeDef *I2Cx) -{ - if(I2Cx == I2C1) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); - } - else - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); - } -} - -/********************************************************************* - * @fn I2C_Init - * - * @brief Initializes the I2Cx peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified I2C peripheral. - * - * @return none - */ -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) -{ - uint16_t tmpreg = 0, freqrange = 0; - uint16_t result = 0x04; - uint32_t pclk1 = 8000000; - - RCC_ClocksTypeDef rcc_clocks; - - tmpreg = I2Cx->CTLR2; - tmpreg &= CTLR2_FREQ_Reset; - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - I2Cx->CTLR2 = tmpreg; - - I2Cx->CTLR1 &= CTLR1_PE_Reset; - tmpreg = 0; - - if(I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - - if(result < 0x04) - { - result = 0x04; - } - - tmpreg |= result; - I2Cx->RTR = freqrange + 1; - } - else - { - if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - result |= I2C_DutyCycle_16_9; - } - - if((result & CKCFGR_CCR_Set) == 0) - { - result |= (uint16_t)0x0001; - } - - tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); - I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - I2Cx->CKCFGR = tmpreg; - I2Cx->CTLR1 |= CTLR1_PE_Set; - - tmpreg = I2Cx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - I2Cx->CTLR1 = tmpreg; - - I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/********************************************************************* - * @fn I2C_StructInit - * - * @brief Fills each I2C_InitStruct member with its default value. - * - * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) -{ - I2C_InitStruct->I2C_ClockSpeed = 5000; - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStruct->I2C_OwnAddress1 = 0; - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/********************************************************************* - * @fn I2C_Cmd - * - * @brief Enables or disables the specified I2C peripheral. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PE_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PE_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMACmd - * - * @brief Enables or disables the specified I2C DMA requests. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_DMAEN_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMALastTransferCmd - * - * @brief Specifies if the next DMA transfer will be the last one. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_LAST_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_LAST_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTART - * - * @brief Generates I2Cx communication START condition. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_START_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_START_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTOP - * - * @brief Generates I2Cx communication STOP condition. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_STOP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_STOP_Reset; - } -} - -/********************************************************************* - * @fn I2C_AcknowledgeConfig - * - * @brief Enables or disables the specified I2C acknowledge feature. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ACK_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ACK_Reset; - } -} - -/********************************************************************* - * @fn I2C_OwnAddress2Config - * - * @brief Configures the specified I2C own address2. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * Address - specifies the 7bit I2C own address2. - * - * @return none - */ -void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - tmpreg = I2Cx->OADDR2; - tmpreg &= OADDR2_ADD2_Reset; - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - I2Cx->OADDR2 = tmpreg; -} - -/********************************************************************* - * @fn I2C_DualAddressCmd - * - * @brief Enables or disables the specified I2C dual addressing mode. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; - } - else - { - I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; - } -} - -/********************************************************************* - * @fn I2C_GeneralCallCmd - * - * @brief Enables or disables the specified I2C general call feature. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENGC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENGC_Reset; - } -} - -/********************************************************************* - * @fn I2C_ITConfig - * - * @brief Enables or disables the specified I2C interrupts. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. - * I2C_IT_BUF - Buffer interrupt mask. - * I2C_IT_EVT - Event interrupt mask. - * I2C_IT_ERR - Error interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= I2C_IT; - } - else - { - I2Cx->CTLR2 &= (uint16_t)~I2C_IT; - } -} - -/********************************************************************* - * @fn I2C_SendData - * - * @brief Sends a data byte through the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * Data - Byte to be transmitted. - * - * @return none - */ -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) -{ - I2Cx->DATAR = Data; -} - -/********************************************************************* - * @fn I2C_ReceiveData - * - * @brief Returns the most recent received data by the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) -{ - return (uint8_t)I2Cx->DATAR; -} - -/********************************************************************* - * @fn I2C_Send7bitAddress - * - * @brief Transmits the address byte to select the slave device. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * Address - specifies the slave address which will be transmitted. - * I2C_Direction - specifies whether the I2C device will be a - * Transmitter or a Receiver. - * I2C_Direction_Transmitter - Transmitter mode. - * I2C_Direction_Receiver - Receiver mode. - * - * @return none - */ -void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - if(I2C_Direction != I2C_Direction_Transmitter) - { - Address |= OADDR1_ADD0_Set; - } - else - { - Address &= OADDR1_ADD0_Reset; - } - - I2Cx->DATAR = Address; -} - -/********************************************************************* - * @fn I2C_ReadRegister - * - * @brief Reads the specified I2C register and returns its value. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_Register - specifies the register to read. - * I2C_Register_CTLR1. - * I2C_Register_CTLR2. - * I2C_Register_OADDR1. - * I2C_Register_OADDR2. - * I2C_Register_DATAR. - * I2C_Register_STAR1. - * I2C_Register_STAR2. - * I2C_Register_CKCFGR. - * I2C_Register_RTR. - * - * @return none - */ -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)I2Cx; - tmp += I2C_Register; - - return (*(__IO uint16_t *)tmp); -} - -/********************************************************************* - * @fn I2C_SoftwareResetCmd - * - * @brief Enables or disables the specified I2C software reset. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_SWRST_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_SWRST_Reset; - } -} - -/********************************************************************* - * @fn I2C_NACKPositionConfig - * - * @brief Selects the specified I2C NACK position in master receiver mode. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_NACKPosition - specifies the NACK position. - * I2C_NACKPosition_Next - indicates that the next byte will be - * the last received byte. - * I2C_NACKPosition_Current - indicates that current byte is the - * last received byte. - * - * @return none - */ -void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) -{ - if(I2C_NACKPosition == I2C_NACKPosition_Next) - { - I2Cx->CTLR1 |= I2C_NACKPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_NACKPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_SMBusAlertConfig - * - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_SMBusAlert - specifies SMBAlert pin level. - * I2C_SMBusAlert_Low - SMBAlert pin driven low. - * I2C_SMBusAlert_High - SMBAlert pin driven high. - * - * @return none - */ -void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert) -{ - if(I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - I2Cx->CTLR1 |= I2C_SMBusAlert_Low; - } - else - { - I2Cx->CTLR1 &= I2C_SMBusAlert_High; - } -} - -/********************************************************************* - * @fn I2C_TransmitPEC - * - * @brief Enables or disables the specified I2C PEC transfer. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_PECPositionConfig - * - * @brief Selects the specified I2C PEC position. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_PECPosition - specifies the PEC position. - * I2C_PECPosition_Next - indicates that the next byte is PEC. - * I2C_PECPosition_Current - indicates that current byte is PEC. - * - * @return none - */ -void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) -{ - if(I2C_PECPosition == I2C_PECPosition_Next) - { - I2Cx->CTLR1 |= I2C_PECPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_PECPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_CalculatePEC - * - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * - * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENPEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_GetPEC - * - * @brief Returns the PEC value for the specified I2C. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) -{ - return ((I2Cx->STAR2) >> 8); -} - -/********************************************************************* - * @fn I2C_ARPCmd - * - * @brief Enables or disables the specified I2C ARP. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return The PEC value. - */ -void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENARP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENARP_Reset; - } -} - -/********************************************************************* - * @fn I2C_StretchClockCmd - * - * @brief Enables or disables the specified I2C Clock stretching. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState == DISABLE) - { - I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; - } -} - -/********************************************************************* - * @fn I2C_FastModeDutyCycleConfig - * - * @brief Selects the specified I2C fast mode duty cycle. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_DutyCycle - specifies the fast mode duty cycle. - * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. - * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. - * - * @return none - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) -{ - if(I2C_DutyCycle != I2C_DutyCycle_16_9) - { - I2Cx->CKCFGR &= I2C_DutyCycle_2; - } - else - { - I2Cx->CKCFGR |= I2C_DutyCycle_16_9; - } -} - -/********************************************************************* - * @fn I2C_CheckEvent - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. - * I2C_EVENT: specifies the event to be checked. - * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EV1. - * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EV1. - * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EV1. - * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EV1. - * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EV1. - * I2C_EVENT_SLAVE_BYTE_RECEIVED - EV2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EV2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EV2. - * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EV3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EV3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EV3. - * I2C_EVENT_SLAVE_ACK_FAILURE - EV3_2. - * I2C_EVENT_SLAVE_STOP_DETECTED - EV4. - * I2C_EVENT_MASTER_MODE_SELECT - EV5. - * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EV6. - * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EV6. - * I2C_EVENT_MASTER_BYTE_RECEIVED - EV7. - * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EV8. - * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EV8_2. - * I2C_EVENT_MASTER_MODE_ADDRESS10 - EV9. - * - * @return none - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = NoREADY; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - - lastevent = (flag1 | flag2) & FLAG_Mask; - - if((lastevent & I2C_EVENT) == I2C_EVENT) - { - status = READY; - } - else - { - status = NoREADY; - } - - return status; -} - -/********************************************************************* - * @fn I2C_GetLastEvent - * - * @brief Returns the last I2Cx Event. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return none - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - lastevent = (flag1 | flag2) & FLAG_Mask; - - return lastevent; -} - -/********************************************************************* - * @fn I2C_GetFlagStatus - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to check. - * I2C_FLAG_DUALF - Dual flag (Slave mode). - * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). - * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). - * I2C_FLAG_GENCALL - General call header flag (Slave mode). - * I2C_FLAG_TRA - Transmitter/Receiver flag. - * I2C_FLAG_BUSY - Bus busy flag. - * I2C_FLAG_MSL - Master/Slave flag. - * I2C_FLAG_SMBALERT - SMBus Alert flag. - * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * I2C_FLAG_TXE - Data register empty flag (Transmitter). - * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. - * I2C_FLAG_STOPF - Stop detection flag (Slave mode). - * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). - * I2C_FLAG_BTF - Byte transfer finished flag. - * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDA". - * I2C_FLAG_SB - Start bit flag (Master mode). - * - * @return none - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - i2cxbase = (uint32_t)I2Cx; - i2creg = I2C_FLAG >> 28; - I2C_FLAG &= FLAG_Mask; - - if(i2creg != 0) - { - i2cxbase += 0x14; - } - else - { - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearFlag - * - * @brief Clears the I2Cx's pending flags. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to clear. - * I2C_FLAG_SMBALERT - SMBus Alert flag. - * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * - * @return none - */ -void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - - flagpos = I2C_FLAG & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} - -/********************************************************************* - * @fn I2C_GetITStatus - * - * @brief Checks whether the specified I2C interrupt has occurred or not. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * II2C_IT - specifies the interrupt source to check. - * I2C_IT_SMBALERT - SMBus Alert flag. - * I2C_IT_TIMEOUT - Timeout or Tlow error flag. - * I2C_IT_PECERR - PEC error in reception flag. - * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). - * I2C_IT_AF - Acknowledge failure flag. - * I2C_IT_ARLO - Arbitration lost flag (Master mode). - * I2C_IT_BERR - Bus error flag. - * I2C_IT_TXE - Data register empty flag (Transmitter). - * I2C_IT_RXNE - Data register not empty (Receiver) flag. - * I2C_IT_STOPF - Stop detection flag (Slave mode). - * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). - * I2C_IT_BTF - Byte transfer finished flag. - * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched - * flag (Slave mode)"ENDAD". - * I2C_IT_SB - Start bit flag (Master mode). - * - * @return none - */ -ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); - I2C_IT &= FLAG_Mask; - - if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearITPendingBit - * - * @brief Clears the I2Cx interrupt pending bits. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_IT - specifies the interrupt pending bit to clear. - * I2C_IT_SMBALERT - SMBus Alert interrupt. - * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. - * I2C_IT_PECERR - PEC error in reception interrupt. - * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). - * I2C_IT_AF - Acknowledge failure interrupt. - * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). - * I2C_IT_BERR - Bus error interrupt. - * - * @return none - */ -void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - - flagpos = I2C_IT & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_i2c.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/29 + * Description : This file provides all the I2C firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_i2c.h" +#include "ch32v20x_rcc.h" + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } + else + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + if(freqrange >= 60) + { + freqrange = 60; + } + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + I2Cx->RTR = freqrange + 1; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * I2C_Register_RTR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * Note- + * This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_SMBusAlertConfig + * + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_SMBusAlert - specifies SMBAlert pin level. + * I2C_SMBusAlert_Low - SMBAlert pin driven low. + * I2C_SMBusAlert_High - SMBAlert pin driven high. + * + * @return none + */ +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert) +{ + if(I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + I2Cx->CTLR1 |= I2C_SMBusAlert_Low; + } + else + { + I2Cx->CTLR1 &= I2C_SMBusAlert_High; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. + * I2C_EVENT_MASTER_MODE_SELECT - EVT5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. + * + * @return ErrorStatus - READY or NoREADY. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = NoREADY; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = READY; + } + else + { + status = NoREADY; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). + * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SATR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR + * register (I2C_SendData()). + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_SMBALERT - SMBus Alert flag. + * I2C_IT_TIMEOUT - Timeout or Tlow error flag. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_SMBALERT - SMBus Alert interrupt. + * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_STAR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DATAR register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_iwdg.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_iwdg.c index cae190c..38ba991 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_iwdg.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_iwdg.c @@ -1,120 +1,123 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_iwdg.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the IWDG firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include "ch32v20x_iwdg.h" - -/* CTLR register bit mask */ -#define CTLR_KEY_Reload ((uint16_t)0xAAAA) -#define CTLR_KEY_Enable ((uint16_t)0xCCCC) - -/********************************************************************* - * @fn IWDG_WriteAccessCmd - * - * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. - * - * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR - * and IWDG_RLDR registers. - * - * @return none - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - IWDG->CTLR = IWDG_WriteAccess; -} - -/********************************************************************* - * @fn IWDG_SetPrescaler - * - * @brief Sets IWDG Prescaler value. - * - * @param IWDG_Prescaler - specifies the IWDG Prescaler value. - * IWDG_Prescaler_4 - IWDG prescaler set to 4. - * IWDG_Prescaler_8 - IWDG prescaler set to 8. - * IWDG_Prescaler_16 - IWDG prescaler set to 16. - * IWDG_Prescaler_32 - IWDG prescaler set to 32. - * IWDG_Prescaler_64 - IWDG prescaler set to 64. - * IWDG_Prescaler_128 - IWDG prescaler set to 128. - * IWDG_Prescaler_256 - IWDG prescaler set to 256. - * - * @return none - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - IWDG->PSCR = IWDG_Prescaler; -} - -/********************************************************************* - * @fn IWDG_SetReload - * - * @brief Sets IWDG Reload value. - * - * @param Reload - specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * - * @return none - */ -void IWDG_SetReload(uint16_t Reload) -{ - IWDG->RLDR = Reload; -} - -/********************************************************************* - * @fn IWDG_ReloadCounter - * - * @brief Reloads IWDG counter with value defined in the reload register. - * - * @return none - */ -void IWDG_ReloadCounter(void) -{ - IWDG->CTLR = CTLR_KEY_Reload; -} - -/********************************************************************* - * @fn IWDG_Enable - * - * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). - * - * @return none - */ -void IWDG_Enable(void) -{ - IWDG->CTLR = CTLR_KEY_Enable; -} - -/********************************************************************* - * @fn IWDG_GetFlagStatus - * - * @brief Checks whether the specified IWDG flag is set or not. - * - * @param IWDG_FLAG - specifies the flag to check. - * IWDG_FLAG_PVU - Prescaler Value Update on going. - * IWDG_FLAG_RVU - Reload Value Update on going. - * - * @return none - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_iwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/29 + * Description : This file provides all the IWDG firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_iwdg.h" + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; + while((RCC->RSTSCKR & 0x2)==RESET); +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_misc.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_misc.c index 3001aff..06d1ccd 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_misc.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_misc.c @@ -1,107 +1,81 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_misc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the miscellaneous firmware functions . - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *********************************************************************************/ -#include "ch32v20x_misc.h" - -__IO uint32_t NVIC_Priority_Group = 0; - -/********************************************************************* - * @fn NVIC_PriorityGroupConfig - * - * @brief Configures the priority grouping - pre-emption priority and subpriority. - * - * @param NVIC_PriorityGroup - specifies the priority grouping bits length. - * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority - * 4 bits for subpriority - * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority - * 3 bits for subpriority - * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority - * 2 bits for subpriority - * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority - * 1 bits for subpriority - * NVIC_PriorityGroup_4 - 4 bits for pre-emption priority - * 0 bits for subpriority - * - * @return none - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - NVIC_Priority_Group = NVIC_PriorityGroup; -} - -/********************************************************************* - * @fn NVIC_Init - * - * @brief Initializes the NVIC peripheral according to the specified parameters in - * the NVIC_InitStruct. - * - * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the - * configuration information for the specified NVIC peripheral. - * - * @return none - */ -void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) -{ - uint8_t tmppre = 0; - - if(NVIC_Priority_Group == NVIC_PriorityGroup_0) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); - } - else - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); - } - else - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3) - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); - } - else - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4)); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_4) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4); - } - - if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } - else - { - NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_misc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file provides all the miscellaneous firmware functions . +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_misc.h" + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 3 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 2 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); + } +#else + if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + } +#endif + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_opa.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_opa.c index 36aa3f2..6c4ae1e 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_opa.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_opa.c @@ -1,84 +1,86 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_opa.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the OPA firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - ***************************************************************************************/ -#include "ch32v20x_opa.h" - -#define OPA_MASK ((uint32_t)0x000F) -#define OPA_Total_NUM 4 - -/********************************************************************* - * @fn OPA_DeInit - * - * @brief Deinitializes the OPA peripheral registers to their default - * reset values. - * - * @return none - */ -void OPA_DeInit(void) -{ - OPA->CR = 0; -} - -/********************************************************************* - * @fn OPA_Init - * - * @brief Initializes the OPA peripheral according to the specified - * parameters in the OPA_InitStruct. - * - * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure - * - * @return none - */ -void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) -{ - uint32_t tmp = 0; - tmp = OPA->CR; - tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); - tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); - OPA->CR = tmp; -} - -/********************************************************************* - * @fn OPA_StructInit - * - * @brief Fills each OPA_StructInit member with its reset value. - * - * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure - * - * @return none - */ -void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) -{ - OPA_InitStruct->Mode = OUT_IO_OUT1; - OPA_InitStruct->PSEL = CHP0; - OPA_InitStruct->NSEL = CHN0; - OPA_InitStruct->OPA_NUM = OPA1; -} - -/********************************************************************* - * @fn OPA_Cmd - * - * @brief Enables or disables the specified OPA peripheral. - * - * @param OPA_NUM - Select OPA - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM)); - } - else - { - OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM)); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_opa.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file provides all the OPA firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32v20x_opa.h" + +#define OPA_MASK ((uint32_t)0x000F) +#define OPA_Total_NUM 4 + +/********************************************************************* + * @fn OPA_DeInit + * + * @brief Deinitializes the OPA peripheral registers to their default + * reset values. + * + * @return none + */ +void OPA_DeInit(void) +{ + OPA->CR = 0; +} + +/********************************************************************* + * @fn OPA_Init + * + * @brief Initializes the OPA peripheral according to the specified + * parameters in the OPA_InitStruct. + * + * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) +{ + uint32_t tmp = 0; + tmp = OPA->CR; + tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); + tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); + OPA->CR = tmp; +} + +/********************************************************************* + * @fn OPA_StructInit + * + * @brief Fills each OPA_StructInit member with its reset value. + * + * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) +{ + OPA_InitStruct->Mode = OUT_IO_OUT1; + OPA_InitStruct->PSEL = CHP0; + OPA_InitStruct->NSEL = CHN0; + OPA_InitStruct->OPA_NUM = OPA1; +} + +/********************************************************************* + * @fn OPA_Cmd + * + * @brief Enables or disables the specified OPA peripheral. + * + * @param OPA_NUM - Select OPA + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM)); + } + else + { + OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM)); + } +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_pwr.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_pwr.c index e17fdbe..40117d9 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_pwr.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_pwr.c @@ -1,400 +1,398 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_pwr.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the PWR firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - ********************************************************************************/ -#include "ch32v20x_pwr.h" -#include "ch32v20x_rcc.h" - -/* PWR registers bit mask */ -/* CTLR register bit mask */ -#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) - -/********************************************************************* - * @fn PWR_DeInit - * - * @brief Deinitializes the PWR peripheral registers to their default - * reset values. - * - * @return none - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/********************************************************************* - * @fn PWR_BackupAccessCmd - * - * @brief Enables or disables access to the RTC and backup registers. - * - * @param NewState - new state of the access to the RTC and backup registers, - * This parameter can be: ENABLE or DISABLE. - * - * @return none - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (1 << 8); - } - else - { - PWR->CTLR &= ~(1 << 8); - } -} - -/********************************************************************* - * @fn PWR_PVDCmd - * - * @brief Enables or disables the Power Voltage Detector(PVD). - * - * @param NewState - new state of the PVD(ENABLE or DISABLE). - * - * @return none - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (1 << 4); - } - else - { - PWR->CTLR &= ~(1 << 4); - } -} - -/********************************************************************* - * @fn PWR_PVDLevelConfig - * - * @brief Configures the voltage threshold detected by the Power Voltage - * Detector(PVD). - * - * @param PWR_PVDLevel - specifies the PVD detection level - * PWR_PVDLevel_2V2 - PVD detection level set to 2.2V - * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V - * PWR_PVDLevel_2V4 - PVD detection level set to 2.4V - * PWR_PVDLevel_2V5 - PVD detection level set to 2.5V - * PWR_PVDLevel_2V6 - PVD detection level set to 2.6V - * PWR_PVDLevel_2V7 - PVD detection level set to 2.7V - * PWR_PVDLevel_2V8 - PVD detection level set to 2.8V - * PWR_PVDLevel_2V9 - PVD detection level set to 2.9V - * - * @return none - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_PLS_MASK; - tmpreg |= PWR_PVDLevel; - PWR->CTLR = tmpreg; -} - -/********************************************************************* - * @fn PWR_WakeUpPinCmd - * - * @brief Enables or disables the WakeUp Pin functionality. - * - * @param NewState - new state of the WakeUp Pin functionality - * (ENABLE or DISABLE). - * - * @return none - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CSR |= (1 << 8); - } - else - { - PWR->CSR &= ~(1 << 8); - } -} - -/********************************************************************* - * @fn PWR_EnterSTOPMode - * - * @brief Enters STOP mode. - * - * @param PWR_Regulator - specifies the regulator state in STOP mode. - * PWR_Regulator_ON - STOP mode with regulator ON - * PWR_Regulator_LowPower - STOP mode with regulator in low power mode - * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. - * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction - * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction - * - * @return none - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_DS_MASK; - tmpreg |= PWR_Regulator; - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - __WFI(); - } - else - { - __WFE(); - } - - NVIC->SCTLR &= ~(1 << 2); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode - * - * @brief Enters STANDBY mode. - * - * @return none - */ -void PWR_EnterSTANDBYMode(void) -{ - PWR->CTLR |= PWR_CTLR_CWUF; - PWR->CTLR |= PWR_CTLR_PDDS; - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_GetFlagStatus - * - * @brief Checks whether the specified PWR flag is set or not. - * - * @param PWR_FLAG - specifies the flag to check. - * PWR_FLAG_WU - Wake Up flag - * PWR_FLAG_SB - StandBy flag - * PWR_FLAG_PVDO - PVD Output - * - * @return none - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn PWR_ClearFlag - * - * @brief Clears the PWR's pending flags. - * - * @param PWR_FLAG - specifies the flag to clear. - * PWR_FLAG_WU - Wake Up flag - * PWR_FLAG_SB - StandBy flag - * - * @return none - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - PWR->CTLR |= PWR_FLAG << 2; -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode_RAM - * - * @brief Enters STANDBY mode with RAM data retention function on. - * - * @return none - */ -void PWR_EnterSTANDBYMode_RAM(void) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - - tmpreg |= PWR_CTLR_CWUF; - tmpreg |= PWR_CTLR_PDDS; - -#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) - //2K+30K in standby w power. - tmpreg |= (0x1 << 16) | (0x1 << 17); -#else - //RAM in standby power. - tmpreg |= ( ( uint32_t )1 << 16 ); - -#endif - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode_RAM_LV - * - * @brief Enters STANDBY mode with RAM data retention function and LV mode on. - * - * @return none - */ -void PWR_EnterSTANDBYMode_RAM_LV(void) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - - tmpreg |= PWR_CTLR_CWUF; - tmpreg |= PWR_CTLR_PDDS; - -#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) - //2K+30K in standby power. - tmpreg |= (0x1 << 16) | (0x1 << 17); - //2K+30K in standby LV . - tmpreg |= (0x1 << 20); -#else - //RAM in standby power. - tmpreg |= ( ( uint32_t )1 << 16 ); - //RAM in standby LV . - tmpreg |= ( ( uint32_t )1 << 20 ); - -#endif - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN - * - * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable). - * - * @return none - */ -void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - - tmpreg |= PWR_CTLR_CWUF; - tmpreg |= PWR_CTLR_PDDS; - -#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) - //2K+30K in standby power (VBAT Enable). - tmpreg |= (0x1 << 18) | (0x1 << 19); -#else - //RAM in standby w power. - tmpreg |= ( ( uint32_t )1 << 18 ); - -#endif - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN - * - * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable). - * - * @return none - */ -void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - - tmpreg |= PWR_CTLR_CWUF; - tmpreg |= PWR_CTLR_PDDS; - -#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) - //2K+30K in standby power (VBAT Enable). - tmpreg |= (0x1 << 18) | (0x1 << 19); - //2K+30K in standby LV . - tmpreg |= (0x1 << 20); -#else - //RAM in standby w power. - tmpreg |= ( ( uint32_t )1 << 18 ); - //RAM in standby LV . - tmpreg |= ( ( uint32_t )1 << 20 ); - -#endif - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - - -/********************************************************************* - * @fn PWR_EnterSTOPMode_RAM_LV - * - * @brief Enters STOP mode with RAM data retention function and LV mode on. - * - * @param PWR_Regulator - specifies the regulator state in STOP mode. - * PWR_Regulator_ON - STOP mode with regulator ON - * PWR_Regulator_LowPower - STOP mode with regulator in low power mode - * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. - * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction - * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction - * - * @return none - */ -void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_DS_MASK; - tmpreg |= PWR_Regulator; - -#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) - //2K+30K in standby power. - tmpreg |= (0x1 << 16) | (0x1 << 17); - //2K+30K in standby LV . - tmpreg |= (0x1 << 20); -#else - //RAM in standby power. - tmpreg |= ( ( uint32_t )1 << 16 ); - //RAM in standby LV . - tmpreg |= ( ( uint32_t )1 << 20 ); - -#endif - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - __WFI(); - } - else - { - __WFE(); - } - - NVIC->SCTLR &= ~(1 << 2); -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_pwr.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file provides all the PWR firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32v20x_pwr.h" +#include "ch32v20x_rcc.h" + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_BackupAccessCmd + * + * @brief Enables or disables access to the RTC and backup registers. + * + * @param NewState - new state of the access to the RTC and backup registers, + * This parameter can be: ENABLE or DISABLE. + * + * @return none + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 8); + } + else + { + PWR->CTLR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_PVDCmd + * + * @brief Enables or disables the Power Voltage Detector(PVD). + * + * @param NewState - new state of the PVD(ENABLE or DISABLE). + * + * @return none + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 4); + } + else + { + PWR->CTLR &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_MODE0 - PVD detection level set to mode 0. + * PWR_PVDLevel_MODE1 - PVD detection level set to mode 1. + * PWR_PVDLevel_MODE2 - PVD detection level set to mode 2. + * PWR_PVDLevel_MODE3 - PVD detection level set to mode 3. + * PWR_PVDLevel_MODE4 - PVD detection level set to mode 4. + * PWR_PVDLevel_MODE5 - PVD detection level set to mode 5. + * PWR_PVDLevel_MODE6 - PVD detection level set to mode 6. + * PWR_PVDLevel_MODE7 - PVD detection level set to mode 7. + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_WakeUpPinCmd + * + * @brief Enables or disables the WakeUp Pin functionality. + * + * @param NewState - new state of the WakeUp Pin functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CSR |= (1 << 8); + } + else + { + PWR->CSR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_EnterSTOPMode + * + * @brief Enters STOP mode. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_ON - STOP mode with regulator ON + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @return none + */ +void PWR_EnterSTANDBYMode(void) +{ + PWR->CTLR |= PWR_CTLR_CWUF; + PWR->CTLR |= PWR_CTLR_PDDS; + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * PWR_FLAG_PVDO - PVD Output + * + * @return The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn PWR_ClearFlag + * + * @brief Clears the PWR's pending flags. + * + * @param PWR_FLAG - specifies the flag to clear. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * + * @return none + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + PWR->CTLR |= PWR_FLAG << 2; +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM + * + * @brief Enters STANDBY mode with RAM data retention function on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + //2K+30K in standby w power. + tmpreg |= (0x1 << 16) | (0x1 << 17); +#else + //RAM in standby power. + tmpreg |= ( ( uint32_t )1 << 16 ); + +#endif + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + //2K+30K in standby power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + //2K+30K in standby LV . + tmpreg |= (0x1 << 20); +#else + //RAM in standby power. + tmpreg |= ( ( uint32_t )1 << 16 ); + //RAM in standby LV . + tmpreg |= ( ( uint32_t )1 << 20 ); + +#endif + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + //2K+30K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); +#else + //RAM in standby w power. + tmpreg |= ( ( uint32_t )1 << 18 ); + +#endif + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + //2K+30K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + //2K+30K in standby LV . + tmpreg |= (0x1 << 20); +#else + //RAM in standby w power. + tmpreg |= ( ( uint32_t )1 << 18 ); + //RAM in standby LV . + tmpreg |= ( ( uint32_t )1 << 20 ); + +#endif + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + + +/********************************************************************* + * @fn PWR_EnterSTOPMode_RAM_LV + * + * @brief Enters STOP mode with RAM data retention function and LV mode on. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_ON - STOP mode with regulator ON + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + + tmpreg |= (0x1 << 20); +#else + + tmpreg |= ( ( uint32_t )1 << 20 ); + +#endif + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_rcc.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_rcc.c index 261c908..bf8ac00 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_rcc.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_rcc.c @@ -1,1018 +1,1061 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_rcc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the RCC firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include "ch32v20x_rcc.h" - -/* RCC registers bit address in the alias region */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* BDCTLR Register */ -#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) - -/* RCC registers bit mask */ - -/* CTLR register bit mask */ -#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) -#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CTLR_HSEON_Set ((uint32_t)0x00010000) -#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) - -#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) -#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) -#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) -#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) -#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) -#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) -#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) -#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) - -/* RSTSCKR register bit mask */ -#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) - -/* CFGR2 register bit mask */ -#define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) -#define CFGR2_PREDIV1 ((uint32_t)0x0000000F) -#define CFGR2_PREDIV2 ((uint32_t)0x000000F0) -#define CFGR2_PLL2MUL ((uint32_t)0x00000F00) -#define CFGR2_PLL3MUL ((uint32_t)0x0000F000) - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -/* INTR register byte 2 (Bits[15:8]) base address */ -#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* INTR register byte 3 (Bits[23:16]) base address */ -#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CFGR0 register byte 4 (Bits[31:24]) base address */ -#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) - -/* BDCTLR register base address */ -#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) - - -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; - -/********************************************************************* - * @fn RCC_DeInit - * - * @brief Resets the RCC clock configuration to the default reset state. - * - * @return none - */ -void RCC_DeInit(void) -{ - RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; - RCC->CTLR &= (uint32_t)0xFEF6FFFF; - RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; - RCC->INTR = 0x009F0000; -} - -/********************************************************************* - * @fn RCC_HSEConfig - * - * @brief Configures the External High Speed oscillator (HSE). - * - * @param RCC_HSE - - * RCC_HSE_OFF - HSE oscillator OFF. - * RCC_HSE_ON - HSE oscillator ON. - * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. - * - * @return none - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - RCC->CTLR &= CTLR_HSEON_Reset; - RCC->CTLR &= CTLR_HSEBYP_Reset; - - switch(RCC_HSE) - { - case RCC_HSE_ON: - RCC->CTLR |= CTLR_HSEON_Set; - break; - - case RCC_HSE_Bypass: - RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn RCC_WaitForHSEStartUp - * - * @brief Waits for HSE start-up. - * - * @return SUCCESS - HSE oscillator is stable and ready to use. - * ERROR - HSE oscillator not yet ready. - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - - ErrorStatus status = NoREADY; - FlagStatus HSEStatus = RESET; - - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = READY; - } - else - { - status = NoREADY; - } - - return (status); -} - -/********************************************************************* - * @fn RCC_AdjustHSICalibrationValue - * - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * - * @param HSICalibrationValue - specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * - * @return none - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CTLR; - tmpreg &= CTLR_HSITRIM_Mask; - tmpreg |= (uint32_t)HSICalibrationValue << 3; - RCC->CTLR = tmpreg; -} - -/********************************************************************* - * @fn RCC_HSICmd - * - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_HSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<0); - } - else{ - RCC->CTLR &= ~(1<<0); - } -} - -/********************************************************************* - * @fn RCC_PLLConfig - * - * @brief Configures the PLL clock source and multiplication factor. - * - * @param RCC_PLLSource - specifies the PLL entry clock source. - * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 - * selected as PLL clock entry. - * RCC_PLLSource_PREDIV1 - PREDIV1 clock selected as PLL clock - * entry. - * RCC_PLLMul - specifies the PLL multiplication factor. - * This parameter can be RCC_PLLMul_x where x:[2,16]. - * RCC_PLLMul_2 - * RCC_PLLMul_3 - * RCC_PLLMul_4 - * RCC_PLLMul_5 - * RCC_PLLMul_6 - * RCC_PLLMul_7 - * RCC_PLLMul_8 - * RCC_PLLMul_9 - * RCC_PLLMul_10 - * RCC_PLLMul_11 - * RCC_PLLMul_12 - * RCC_PLLMul_13 - * RCC_PLLMul_14 - * RCC_PLLMul_15 - * RCC_PLLMul_16 - * RCC_PLLMul_18 - * - * @return none - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - - tmpreg &= CFGR0_PLL_Mask; - tmpreg |= RCC_PLLSource | RCC_PLLMul; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PLLCmd - * - * @brief Enables or disables the PLL. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<24); - } - else{ - RCC->CTLR &= ~(1<<24); - } -} - -/********************************************************************* - * @fn RCC_SYSCLKConfig - * - * @brief Configures the system clock (SYSCLK). - * - * @param RCC_SYSCLKSource - specifies the clock source used as system clock. - * RCC_SYSCLKSource_HSI - HSI selected as system clock. - * RCC_SYSCLKSource_HSE - HSE selected as system clock. - * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. - * - * @return none - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_SW_Mask; - tmpreg |= RCC_SYSCLKSource; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_GetSYSCLKSource - * - * @brief Returns the clock source used as system clock. - * - * @return 0x00 - HSI used as system clock. - * 0x04 - HSE used as system clock. - * 0x08 - PLL used as system clock. - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); -} - -/********************************************************************* - * @fn RCC_HCLKConfig - * - * @brief Configures the AHB clock (HCLK). - * - * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. - * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. - * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. - * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. - * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. - * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. - * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. - * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. - * RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512. - * - * @return none - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_HPRE_Reset_Mask; - tmpreg |= RCC_SYSCLK; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PCLK1Config - * - * @brief Configures the Low Speed APB clock (PCLK1). - * - * @param RCC_HCLK - defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * RCC_HCLK_Div1 - APB1 clock = HCLK. - * RCC_HCLK_Div2 - APB1 clock = HCLK/2. - * RCC_HCLK_Div4 - APB1 clock = HCLK/4. - * RCC_HCLK_Div8 - APB1 clock = HCLK/8. - * RCC_HCLK_Div16 - APB1 clock = HCLK/16. - * - * @return none - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_PPRE1_Reset_Mask; - tmpreg |= RCC_HCLK; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PCLK2Config - * - * @brief Configures the High Speed APB clock (PCLK2). - * - * @param RCC_HCLK - defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * RCC_PCLK2_Div2 - APB2 clock = HCLK. - * RCC_PCLK2_Div4 - APB2 clock = HCLK/2. - * RCC_PCLK2_Div6 - APB2 clock = HCLK/4. - * RCC_PCLK2_Div8 - APB2 clock = HCLK/8. - * - * @return none - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_PPRE2_Reset_Mask; - tmpreg |= RCC_HCLK << 3; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_ITConfig - * - * @brief Enables or disables the specified RCC interrupts. - * - * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - *(__IO uint8_t *) INTR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - *(__IO uint8_t *) INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/********************************************************************* - * @fn RCC_USBCLKConfig - * - * @brief Configures the USB clock (USBCLK). - * - * @param RCC_USBCLKSource: specifies the USB clock source. This clock is - * derived from the PLL output. - * RCC_USBCLKSource_PLLCLK_Div1 - PLL clock selected as USB clock source(48Mhz). - * RCC_USBCLKSource_PLLCLK_Div2 - PLL clock selected as USB clock source(96MHz). - * RCC_USBCLKSource_PLLCLK_Div3 - PLL clock selected as USB clock source(144MHz). - * RCC_USBCLKSource_PLLCLK_Div5 - PLL clock selected as USB clock source(240MHz). - * - * @return none - */ -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) -{ - RCC->CFGR0 &= ~((uint32_t)3<<22); - RCC->CFGR0 |= RCC_USBCLKSource<<22; -} - -/********************************************************************* - * @fn RCC_ADCCLKConfig - * - * @brief Configures the ADC clock (ADCCLK). - * - * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from - * the APB2 clock (PCLK2). - * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. - * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. - * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. - * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. - * - * @return none - */ -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_ADCPRE_Reset_Mask; - tmpreg |= RCC_PCLK2; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_LSEConfig - * - * @brief Configures the External Low Speed oscillator (LSE). - * - * @param RCC_LSE - specifies the new state of the LSE. - * RCC_LSE_OFF - LSE oscillator OFF. - * RCC_LSE_ON - LSE oscillator ON. - * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. - * - * @return none - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; - *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; - - switch(RCC_LSE) - { - case RCC_LSE_ON: - *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_ON; - break; - - case RCC_LSE_Bypass: - *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn RCC_LSICmd - * - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_LSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->RSTSCKR |= (1<<0); - } - else{ - RCC->RSTSCKR &= ~(1<<0); - } -} - -/********************************************************************* - * @fn RCC_RTCCLKConfig - * - * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. - * - * @param RCC_RTCCLKSource - specifies the RTC clock source. - * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. - * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. - * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. - * - * @return none - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - RCC->BDCTLR |= RCC_RTCCLKSource; -} - -/********************************************************************* - * @fn RCC_RTCCLKCmd - * - * @brief This function must be used only after the RTC clock was selected - * using the RCC_RTCCLKConfig function. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->BDCTLR |= (1<<15); - } - else{ - RCC->BDCTLR &= ~(1<<15); - } -} - -/********************************************************************* - * @fn RCC_GetClocksFreq - * - * @brief The result of this function could be not correct when using - * fractional value for HSE crystal. - * - * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @return none - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; - - tmp = RCC->CFGR0 & CFGR0_SWS_Mask; - - switch (tmp) - { - case 0x00: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - - case 0x04: - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - - case 0x08: - pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; - pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; - - pllmull = ( pllmull >> 18) + 2; - - if(pllmull == 17) pllmull = 18; - - - if (pllsource == 0x00) - { - if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE) * pllmull; - } - else{ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >>1) * pllmull; - } - } - else - { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) - { - RCC_Clocks->SYSCLK_Frequency = ((HSE_VALUE>>1)) * pllmull; - } - else -#endif - if ((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) - { -#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) - RCC_Clocks->SYSCLK_Frequency = ((HSE_VALUE>>2) >> 1) * pllmull; -#else - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; -#endif - } - else - { -#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE>>2) * pllmull; -#else - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; -#endif - - } - } - - break; - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - - tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; - tmp = tmp >> 11; - presc = APBAHBPrescTable[tmp]; - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; - tmp = tmp >> 14; - presc = ADCPrescTable[tmp]; - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; -} - -/********************************************************************* - * @fn RCC_AHBPeriphClockCmd - * - * @brief Enables or disables the AHB peripheral clock. - * - * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. - * RCC_AHBPeriph_DMA1. - * RCC_AHBPeriph_DMA2. - * RCC_AHBPeriph_SRAM. - * RCC_AHBPeriph_CRC. - * RCC_AHBPeriph_OTG_FS - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->AHBPCENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBPCENR &= ~RCC_AHBPeriph; - } -} - -/********************************************************************* - * @fn RCC_APB2PeriphClockCmd - * - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * - * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. - * RCC_APB2Periph_AFIO. - * RCC_APB2Periph_GPIOA. - * RCC_APB2Periph_GPIOB. - * RCC_APB2Periph_GPIOC. - * RCC_APB2Periph_GPIOD. - * RCC_APB2Periph_GPIOE - * RCC_APB2Periph_ADC1. - * RCC_APB2Periph_ADC2 - * RCC_APB2Periph_TIM1. - * RCC_APB2Periph_SPI1. - * RCC_APB2Periph_TIM8 - * RCC_APB2Periph_USART1. - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->APB2PCENR |= RCC_APB2Periph; - } - else - { - RCC->APB2PCENR &= ~RCC_APB2Periph; - } -} - -/********************************************************************* - * @fn RCC_APB1PeriphClockCmd - * - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * - * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. - * RCC_APB1Periph_TIM2. - * RCC_APB1Periph_TIM3. - * RCC_APB1Periph_TIM4. - * RCC_APB1Periph_TIM5 - * RCC_APB1Periph_WWDG. - * RCC_APB1Periph_SPI2. - * RCC_APB1Periph_USART2. - * RCC_APB1Periph_USART3. - * RCC_APB1Periph_UART4 - * RCC_APB1Periph_I2C1. - * RCC_APB1Periph_I2C2. - * RCC_APB1Periph_USB. - * RCC_APB1Periph_CAN1. - * RCC_APB1Periph_BKP. - * RCC_APB1Periph_PWR. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->APB1PCENR |= RCC_APB1Periph; - } - else - { - RCC->APB1PCENR &= ~RCC_APB1Periph; - } -} - -/********************************************************************* - * @fn RCC_APB2PeriphResetCmd - * - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * - * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. - * RCC_APB2Periph_AFIO. - * RCC_APB2Periph_GPIOA. - * RCC_APB2Periph_GPIOB. - * RCC_APB2Periph_GPIOC. - * RCC_APB2Periph_GPIOD. - * RCC_APB2Periph_GPIOE - * RCC_APB2Periph_ADC1. - * RCC_APB2Periph_ADC2 - * RCC_APB2Periph_TIM1. - * RCC_APB2Periph_SPI1. - * RCC_APB2Periph_TIM8 - * RCC_APB2Periph_USART1. - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->APB2PRSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2PRSTR &= ~RCC_APB2Periph; - } -} - -/********************************************************************* - * @fn RCC_APB1PeriphResetCmd - * - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * - * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. - * RCC_APB1Periph_TIM2. - * RCC_APB1Periph_TIM3. - * RCC_APB1Periph_TIM4. - * RCC_APB1Periph_TIM5 - * RCC_APB1Periph_WWDG. - * RCC_APB1Periph_SPI2. - * RCC_APB1Periph_USART2. - * RCC_APB1Periph_USART3. - * RCC_APB1Periph_UART4 - * RCC_APB1Periph_I2C1. - * RCC_APB1Periph_I2C2. - * RCC_APB1Periph_USB. - * RCC_APB1Periph_CAN1. - * RCC_APB1Periph_BKP. - * RCC_APB1Periph_PWR. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->APB1PRSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1PRSTR &= ~RCC_APB1Periph; - } -} - -/********************************************************************* - * @fn RCC_BackupResetCmd - * - * @brief Forces or releases the Backup domain reset. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->BDCTLR |= (1<<16); - } - else{ - RCC->BDCTLR &= ~(1<<16); - } -} - -/******************************************************************************* -* Function Name : RCC_ClockSecuritySystemCmd -* Description : Enables or disables the Clock Security System. -* Input : NewState: ENABLE or DISABLE. -* Return : None -*******************************************************************************/ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<19); - } - else{ - RCC->CTLR &= ~(1<<19); - } -} - -/********************************************************************* - * @fn RCC_MCOConfig - * - * @brief Selects the clock source to output on MCO pin. - * - * @param RCC_MCO - specifies the clock source to output. - * RCC_MCO_NoClock - No clock selected. - * RCC_MCO_SYSCLK - System clock selected. - * RCC_MCO_HSI - HSI oscillator clock selected. - * RCC_MCO_HSE - HSE oscillator clock selected. - * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. - * - * @return none - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO; -} - -/********************************************************************* - * @fn RCC_GetFlagStatus - * - * @brief Checks whether the specified RCC flag is set or not. - * - * @param RCC_FLAG - specifies the flag to check. - * RCC_FLAG_HSIRDY - HSI oscillator clock ready. - * RCC_FLAG_HSERDY - HSE oscillator clock ready. - * RCC_FLAG_PLLRDY - PLL clock ready. - * RCC_FLAG_PLL2RDY - PLL2 clock ready. - * RCC_FLAG_PLL3RDY - PLL3 clock ready. - * RCC_FLAG_LSERDY - LSE oscillator clock ready. - * RCC_FLAG_LSIRDY - LSI oscillator clock ready. - * RCC_FLAG_PINRST - Pin reset. - * RCC_FLAG_PORRST - POR/PDR reset. - * RCC_FLAG_SFTRST - Software reset. - * RCC_FLAG_IWDGRST - Independent Watchdog reset. - * RCC_FLAG_WWDGRST - Window Watchdog reset. - * RCC_FLAG_LPWRRST - Low Power reset. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - - FlagStatus bitstatus = RESET; - tmp = RCC_FLAG >> 5; - - if (tmp == 1) - { - statusreg = RCC->CTLR; - } - else if (tmp == 2) - { - statusreg = RCC->BDCTLR; - } - else - { - statusreg = RCC->RSTSCKR; - } - - tmp = RCC_FLAG & FLAG_Mask; - - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearFlag - * - * @brief Clears the RCC reset flags. - * - * @return none - */ -void RCC_ClearFlag(void) -{ - RCC->RSTSCKR |= RSTSCKR_RMVF_Set; -} - -/********************************************************************* - * @fn RCC_GetITStatus - * - * @brief Checks whether the specified RCC interrupt has occurred or not. - * - * @param RCC_IT - specifies the RCC interrupt source to check. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_PLL2RDY - PLL2 ready interrupt. - * RCC_IT_PLL3RDY - PLL3 ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * - * @return ITStatus - SET or RESET. - */ - -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - if ((RCC->INTR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearITPendingBit - * - * @brief Clears the RCC's interrupt pending bits. - * - * @param RCC_IT - specifies the interrupt pending bit to clear. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_PLL2RDY - PLL2 ready interrupt. - * RCC_IT_PLL3RDY - PLL3 ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * - * @return none - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - *(__IO uint8_t *) INTR_BYTE3_ADDRESS = RCC_IT; -} - -/********************************************************************* - * @fn RCC_ADCCLKADJcmd - * - * @brief Enable ADC clock duty cycle adjustment. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ADCCLKADJcmd(FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->CFGR0 |= (1<<31); - } - else - { - RCC->CFGR0 &= ~(1<<31); - } -} - -/********************************************************************* - * @fn RCC_ETHDIVConfig - * - * @brief Configures the ETH clock. - * - * @param RCC_ETHPRE_Div - defines the USBHS clock divider. - * RCC_ETHCLK_Div1 - ETH clock = AHB/1. - * RCC_ETHCLK_Div2 - ETH clock = AHB/2. - * - * @return none - */ -void RCC_ETHDIVConfig(uint32_t RCC_ETHPRE_Div) -{ - RCC->CFGR0 &= ~((uint32_t)1<<28); - RCC->CFGR0 |= RCC_ETHPRE_Div<<28; -} - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_rcc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/30 + * Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_rcc.h" + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) + +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* CFGR2 register bit mask */ +#define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) +#define CFGR2_PREDIV1 ((uint32_t)0x0000000F) +#define CFGR2_PREDIV2 ((uint32_t)0x000000F0) +#define CFGR2_PLL2MUL ((uint32_t)0x00000F00) +#define CFGR2_PLL3MUL ((uint32_t)0x0000F000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; + RCC->INTR = 0x009F0000; +} + +/********************************************************************* + * @fn RCC_HSEConfig + * + * @brief Configures the External High Speed oscillator (HSE). + * + * @param RCC_HSE - + * RCC_HSE_OFF - HSE oscillator OFF. + * RCC_HSE_ON - HSE oscillator ON. + * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + RCC->CTLR &= CTLR_HSEON_Reset; + RCC->CTLR &= CTLR_HSEBYP_Reset; + + switch(RCC_HSE) + { + case RCC_HSE_ON: + RCC->CTLR |= CTLR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_WaitForHSEStartUp + * + * @brief Waits for HSE start-up. + * + * @return READY - HSE oscillator is stable and ready to use. + * NoREADY - HSE oscillator not yet ready. + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + + ErrorStatus status = NoREADY; + FlagStatus HSEStatus = RESET; + + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = READY; + } + else + { + status = NoREADY; + } + + return (status); +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<0); + } + else{ + RCC->CTLR &= ~(1<<0); + } +} + +/********************************************************************* + * @fn RCC_PLLConfig + * + * @brief Configures the PLL clock source and multiplication factor. + * + * @param RCC_PLLSource - specifies the PLL entry clock source. + * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 + * selected as PLL clock entry. + * RCC_PLLSource_PREDIV1 - PREDIV1 clock selected as PLL clock + * entry. + * RCC_PLLMul - specifies the PLL multiplication factor. + * This parameter can be RCC_PLLMul_x where x:[2,16]. + * RCC_PLLMul_2 + * RCC_PLLMul_3 + * RCC_PLLMul_4 + * RCC_PLLMul_5 + * RCC_PLLMul_6 + * RCC_PLLMul_7 + * RCC_PLLMul_8 + * RCC_PLLMul_9 + * RCC_PLLMul_10 + * RCC_PLLMul_11 + * RCC_PLLMul_12 + * RCC_PLLMul_13 + * RCC_PLLMul_14 + * RCC_PLLMul_15 + * RCC_PLLMul_16 + * RCC_PLLMul_18 + * + * @return none + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + + tmpreg &= CFGR0_PLL_Mask; + tmpreg |= RCC_PLLSource | RCC_PLLMul; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLLCmd + * + * @brief Enables or disables the PLL. + * Note-The PLL can not be disabled if it is used as system clock. + * + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<24); + } + else{ + RCC->CTLR &= ~(1<<24); + } +} + +/********************************************************************* + * @fn RCC_SYSCLKConfig + * + * @brief Configures the system clock (SYSCLK). + * + * @param RCC_SYSCLKSource - specifies the clock source used as system clock. + * RCC_SYSCLKSource_HSI - HSI selected as system clock. + * RCC_SYSCLKSource_HSE - HSE selected as system clock. + * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. + * + * @return none + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_SW_Mask; + tmpreg |= RCC_SYSCLKSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetSYSCLKSource + * + * @brief Returns the clock source used as system clock. + * + * @return 0x00 - HSI used as system clock. + * 0x04 - HSE used as system clock. + * 0x08 - PLL used as system clock. + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the AHB clock (HCLK). + * + * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. + * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. + * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. + * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. + * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. + * RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK1Config + * + * @brief Configures the Low Speed APB clock (PCLK1). + * + * @param RCC_HCLK - defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB1 clock = HCLK. + * RCC_HCLK_Div2 - APB1 clock = HCLK/2. + * RCC_HCLK_Div4 - APB1 clock = HCLK/4. + * RCC_HCLK_Div8 - APB1 clock = HCLK/8. + * RCC_HCLK_Div16 - APB1 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE1_Reset_Mask; + tmpreg |= RCC_HCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK2Config + * + * @brief Configures the High Speed APB clock (PCLK2). + * + * @param RCC_HCLK - defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB2 clock = HCLK. + * RCC_HCLK_Div2 - APB2 clock = HCLK/2. + * RCC_HCLK_Div4 - APB2 clock = HCLK/4. + * RCC_HCLK_Div8 - APB2 clock = HCLK/8. + * RCC_HCLK_Div16 - APB2 clock = HCLK/16. + * @return none + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE2_Reset_Mask; + tmpreg |= RCC_HCLK << 3; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_ITConfig + * + * @brief Enables or disables the specified RCC interrupts. + * + * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + *(__IO uint8_t *) INTR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + *(__IO uint8_t *) INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/********************************************************************* + * @fn RCC_USBCLKConfig + * + * @brief Configures the USB clock (USBCLK). + * + * @param RCC_USBCLKSource: specifies the USB clock source. This clock is + * derived from the PLL output. + * RCC_USBCLKSource_PLLCLK_Div1 - PLL clock selected as USB clock source(48Mhz). + * RCC_USBCLKSource_PLLCLK_Div2 - PLL clock selected as USB clock source(96MHz). + * RCC_USBCLKSource_PLLCLK_Div3 - PLL clock selected as USB clock source(144MHz). + * RCC_USBCLKSource_PLLCLK_Div5 - PLL clock selected as USB clock source(240MHz). + * + * @return none + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + RCC->CFGR0 &= ~((uint32_t)3<<22); + RCC->CFGR0 |= RCC_USBCLKSource<<22; +} + +/********************************************************************* + * @fn RCC_ADCCLKConfig + * + * @brief Configures the ADC clock (ADCCLK). + * + * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. + * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. + * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. + * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. + * + * @return none + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_ADCPRE_Reset_Mask; + tmpreg |= RCC_PCLK2; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_LSEConfig + * + * @brief Configures the External Low Speed oscillator (LSE). + * + * @param RCC_LSE - specifies the new state of the LSE. + * RCC_LSE_OFF - LSE oscillator OFF. + * RCC_LSE_ON - LSE oscillator ON. + * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. + * + * @return none + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; + + switch(RCC_LSE) + { + case RCC_LSE_ON: + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_LSICmd + * + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * Note- + * LSI can not be disabled if the IWDG is running. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_LSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->RSTSCKR |= (1<<0); + } + else{ + RCC->RSTSCKR &= ~(1<<0); + } +} + +/********************************************************************* + * @fn RCC_RTCCLKConfig + * + * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * + * @param RCC_RTCCLKSource - specifies the RTC clock source. + * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. + * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. + * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock(CH32V20x_D6) + * RCC_RTCCLKSource_HSE_Div512 - HSE clock divided by 512 selected as RTC clock(CH32V20x_D8,CH32V20x_D8W) + * Note- + * Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * @return none + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + RCC->BDCTLR |= RCC_RTCCLKSource; +} + +/********************************************************************* + * @fn RCC_RTCCLKCmd + * + * @brief This function must be used only after the RTC clock was selected + * using the RCC_RTCCLKConfig function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1<<15); + } + else{ + RCC->BDCTLR &= ~(1<<15); + } +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + + tmp = RCC->CFGR0 & CFGR0_SWS_Mask; + + switch (tmp) + { + case 0x00: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + + case 0x04: + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: + pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; + pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; + + pllmull = ( pllmull >> 18) + 2; + + if(pllmull == 17) pllmull = 18; + + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE) * pllmull; + } + else{ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >>1) * pllmull; + } + } + else + { +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) + { + RCC_Clocks->SYSCLK_Frequency = ((HSE_VALUE>>1)) * pllmull; + } + else +#endif + if ((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) + { +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + RCC_Clocks->SYSCLK_Frequency = ((HSE_VALUE>>2) >> 1) * pllmull; +#else + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; +#endif + } + else + { +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE>>2) * pllmull; +#else + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; +#endif + + } + } + + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/********************************************************************* + * @fn RCC_AHBPeriphClockCmd + * + * @brief Enables or disables the AHB peripheral clock. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. + * RCC_AHBPeriph_DMA1. + * RCC_AHBPeriph_DMA2. + * RCC_AHBPeriph_SRAM. + * RCC_AHBPeriph_CRC. + * RCC_AHBPeriph_USBFS + * Note- + * SRAM clock can be disabled only during sleep mode. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->AHBPCENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCENR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphClockCmd + * + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_ADC2 + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_TIM8 + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->APB2PCENR |= RCC_APB2Periph; + } + else + { + RCC->APB2PCENR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_TIM5 + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_UART4 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->APB1PCENR |= RCC_APB1Periph; + } + else + { + RCC->APB1PCENR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphResetCmd + * + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_ADC2 + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_TIM8 + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->APB2PRSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2PRSTR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphResetCmd + * + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_TIM5 + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_UART4 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->APB1PRSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1PRSTR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_BackupResetCmd + * + * @brief Forces or releases the Backup domain reset. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1<<16); + } + else{ + RCC->BDCTLR &= ~(1<<16); + } +} + +/******************************************************************************* +* Function Name : RCC_ClockSecuritySystemCmd +* Description : Enables or disables the Clock Security System. +* Input : NewState: ENABLE or DISABLE. +* Return : None +*******************************************************************************/ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<19); + } + else{ + RCC->CTLR &= ~(1<<19); + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * RCC_MCO_HSE - HSE oscillator clock selected. + * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_HSERDY - HSE oscillator clock ready. + * RCC_FLAG_PLLRDY - PLL clock ready. + * RCC_FLAG_PLL2RDY - PLL2 clock ready. + * RCC_FLAG_PLL3RDY - PLL3 clock ready. + * RCC_FLAG_LSERDY - LSE oscillator clock ready. + * RCC_FLAG_LSIRDY - LSI oscillator clock ready. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if (tmp == 1) + { + statusreg = RCC->CTLR; + } + else if (tmp == 2) + { + statusreg = RCC->BDCTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * Note- + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + +/********************************************************************* + * @fn RCC_GetITStatus + * + * @brief Checks whether the specified RCC interrupt has occurred or not. + * + * @param RCC_IT - specifies the RCC interrupt source to check. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_PLL2RDY - PLL2 ready interrupt. + * RCC_IT_PLL3RDY - PLL3 ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return ITStatus - SET or RESET. + */ + +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + if ((RCC->INTR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearITPendingBit + * + * @brief Clears the RCC's interrupt pending bits. + * + * @param RCC_IT - specifies the interrupt pending bit to clear. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_PLL2RDY - PLL2 ready interrupt. + * RCC_IT_PLL3RDY - PLL3 ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return none + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + *(__IO uint8_t *) INTR_BYTE3_ADDRESS = RCC_IT; +} + +/********************************************************************* + * @fn RCC_ADCCLKADJcmd + * + * @brief Enable ADC clock duty cycle adjustment. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ADCCLKADJcmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->CFGR0 |= (1<<31); + } + else + { + RCC->CFGR0 &= ~(1<<31); + } +} + +/********************************************************************* + * @fn RCC_ETHDIVConfig + * + * @brief Configures the ETH clock. + * + * @param RCC_ETHPRE_Div - defines the USBHS clock divider. + * RCC_ETHCLK_Div1 - ETH clock = AHB/1. + * RCC_ETHCLK_Div2 - ETH clock = AHB/2. + * + * @return none + */ +void RCC_ETHDIVConfig(uint32_t RCC_ETHPRE_Div) +{ + RCC->CFGR0 &= ~((uint32_t)1<<28); + RCC->CFGR0 |= RCC_ETHPRE_Div<<28; +} + +/********************************************************************* + * @fn RCC_USB5PRE_JUDGE() + * + * @brief Judge MCU supports PLLCLK/5 for USB. + * + * @param FlagStatus - SET or RESET. + * SET - support + * RESET - not support + * @return none + */ +FlagStatus RCC_USB5PRE_JUDGE() +{ + +#if defined (CH32V20x_D8W) + return SET; +#elif defined (CH32V20x_D8) + RCC->AHBPCENR |= (1<<17); + *(vu32*)0x400250A0 = 0x55aaaa55; + if(*(vu32*)0x400250A0 == 0x55aaaa55) + { + return SET; + } + else + { + return RESET; + } +#endif + return RESET; +} + + diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_rtc.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_rtc.c index 816d487..a9c70af 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_rtc.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_rtc.c @@ -1,373 +1,478 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_rtc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the RTC firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - ********************************************************************************/ -#include "ch32v20x_rtc.h" - -/* RTC_Private_Defines */ -#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ -#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ - -/********************************************************************* - * @fn RTC_ITConfig - * - * @brief Enables or disables the specified RTC interrupts. - * - * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. - * RTC_IT_OW - Overflow interrupt - * RTC_IT_ALR - Alarm interrupt - * RTC_IT_SEC - Second interrupt - * - * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). - */ -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RTC->CTLRH |= RTC_IT; - } - else - { - RTC->CTLRH &= (uint16_t)~RTC_IT; - } -} - -/********************************************************************* - * @fn RTC_EnterConfigMode - * - * @brief Enters the RTC configuration mode. - * - * @return none - */ -void RTC_EnterConfigMode(void) -{ - RTC->CTLRL |= RTC_CTLRL_CNF; -} - -/********************************************************************* - * @fn RTC_ExitConfigMode - * - * @brief Exits from the RTC configuration mode. - * - * @return none - */ -void RTC_ExitConfigMode(void) -{ - RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); -} - -/********************************************************************* - * @fn RTC_GetCounter - * - * @brief Gets the RTC counter value - * - * @return RTC counter value - */ -uint32_t RTC_GetCounter(void) -{ - uint16_t high1 = 0, high2 = 0, low = 0; - - high1 = RTC->CNTH; - low = RTC->CNTL; - high2 = RTC->CNTH; - - if(high1 != high2) - { - return (((uint32_t)high2 << 16) | RTC->CNTL); - } - else - { - return (((uint32_t)high1 << 16) | low); - } -} - -/********************************************************************* - * @fn RTC_SetCounter - * - * @brief Sets the RTC counter value. - * - * @param CounterValue - RTC counter new value. - * - * @return RTC counter value - */ -void RTC_SetCounter(uint32_t CounterValue) -{ - RTC_EnterConfigMode(); - RTC->CNTH = CounterValue >> 16; - RTC->CNTL = (CounterValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/********************************************************************* - * @fn RTC_SetPrescaler - * - * @brief Sets the RTC prescaler value - * - * @param PrescalerValue - RTC prescaler new value - * - * @return none - */ -void RTC_SetPrescaler(uint32_t PrescalerValue) -{ - RTC_EnterConfigMode(); - RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; - RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/********************************************************************* - * @fn RTC_SetAlarm - * - * @brief Sets the RTC alarm value - * - * @param AlarmValue - RTC alarm new value - * - * @return none - */ -void RTC_SetAlarm(uint32_t AlarmValue) -{ - RTC_EnterConfigMode(); - RTC->ALRMH = AlarmValue >> 16; - RTC->ALRML = (AlarmValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/********************************************************************* - * @fn RTC_GetDivider - * - * @brief Gets the RTC divider value - * - * @return RTC Divider value - */ -uint32_t RTC_GetDivider(void) -{ - uint32_t tmp = 0x00; - tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; - tmp |= RTC->DIVL; - return tmp; -} - -/********************************************************************* - * @fn RTC_WaitForLastTask - * - * @brief Waits until last write operation on RTC registers has finished - * - * @return none - */ -void RTC_WaitForLastTask(void) -{ - while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) - { - } -} - -/********************************************************************* - * @fn RTC_WaitForSynchro - * - * @brief Waits until the RTC registers are synchronized with RTC APB clock - * - * @return none - */ -void RTC_WaitForSynchro(void) -{ - RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; - while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) - { - } -} - -/********************************************************************* - * @fn RTC_GetFlagStatus - * - * @brief Checks whether the specified RTC flag is set or not - * - * @param RTC_FLAG- specifies the flag to check - * RTC_FLAG_RTOFF - RTC Operation OFF flag - * RTC_FLAG_RSF - Registers Synchronized flag - * RTC_FLAG_OW - Overflow flag - * RTC_FLAG_ALR - Alarm flag - * RTC_FLAG_SEC - Second flag - * - * @return none - */ -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn RTC_ClearFlag - * - * @brief Clears the RTC's pending flags - * - * @param RTC_FLAG - specifies the flag to clear - * RTC_FLAG_RSF - Registers Synchronized flag - * RTC_FLAG_OW - Overflow flag - * RTC_FLAG_ALR - Alarm flag - * RTC_FLAG_SEC - Second flag - * - * @return none - */ -void RTC_ClearFlag(uint16_t RTC_FLAG) -{ - RTC->CTLRL &= (uint16_t)~RTC_FLAG; -} - -/********************************************************************* - * @fn RTC_GetITStatus - * - * @brief Checks whether the specified RTC interrupt has occurred or not - * - * @param RTC_IT - specifies the RTC interrupts sources to check - * RTC_FLAG_OW - Overflow interrupt - * RTC_FLAG_ALR - Alarm interrupt - * RTC_FLAG_SEC - Second interrupt - * - * @return The new state of the RTC_IT (SET or RESET) - */ -ITStatus RTC_GetITStatus(uint16_t RTC_IT) -{ - ITStatus bitstatus = RESET; - - bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); - if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn RTC_ClearITPendingBit - * - * @brief Clears the RTC's interrupt pending bits - * - * @param RTC_IT - specifies the interrupt pending bit to clear - * RTC_FLAG_OW - Overflow interrupt - * RTC_FLAG_ALR - Alarm interrupt - * RTC_FLAG_SEC - Second interrupt - * - * @return none - */ -void RTC_ClearITPendingBit(uint16_t RTC_IT) -{ - RTC->CTLRL &= (uint16_t)~RTC_IT; -} - -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) -/******************************************************************************* - * @fn Calibration_LSI - * - * @brief LSI calibration - * - * @param cali_Lv : calibration level - * Level_32 - 1.2ms 1100ppm - * Level_64 - 2.2ms 1000ppm - * Level_128 - 4.2ms 800ppm - * - * @return None - */ -void Calibration_LSI(Cali_LevelTypeDef cali_Lv) -{ - uint32_t i; - int32_t cnt_offset; - int32_t Freq = 0; - uint8_t retry = 0; - uint32_t cnt_32k = 0; - Freq = SystemCoreClock; - // Coarse tuning - OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU; - OSC->LSI32K_CAL_CFG |= 0; - while(1) - { - OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN; - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END; - while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END)); - i = OSC->LSI32K_CAL_STATR; - OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN; - OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN; - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END; - cnt_32k = RTC_GetCounter(); - while(RTC_GetCounter() == cnt_32k); - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; - while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END); - while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END)); - i = OSC->LSI32K_CAL_STATR; - cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 2000 * (Freq / 1000) / CAB_LSIFQ; - if(((cnt_offset > -(20 * (Freq / 1000) / 36000)) && (cnt_offset < (20 * (Freq / 1000) / 36000))) || retry > 2) - break; - retry++; - cnt_offset = (cnt_offset > 0) ? (((cnt_offset * 2) / (40 * (Freq / 1000) / 36000)) + 1) / 2 : (((cnt_offset * 2) / (40 * (Freq / 1000) / 36000)) - 1) / 2; - OSC->LSI32K_TUNE += cnt_offset; - } - OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU; - OSC->LSI32K_CAL_CFG |= 2; - OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN; - OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN; - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END; - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; - - // Fine tuning - // After configuring the fine-tuning parameters, discard the two captured values (software behavior) and judge once, only one time is left here - while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END)); - i = OSC->LSI32K_CAL_STATR; - OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN; - OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN; - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END; - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; - cnt_32k = RTC_GetCounter(); - while(RTC_GetCounter() == cnt_32k); - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; - while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END); - while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END)); - i = OSC->LSI32K_CAL_STATR; - cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 8000 * (1 << 2) * (Freq / 1000000) / 256 * 1000 / (CAB_LSIFQ / 256); - cnt_offset = (cnt_offset > 0) ? ((((cnt_offset * 2 * 100) / (748 * ((1 << 2) / 4) * (Freq / 1000) / 36000)) + 1) / 2) << 5 : ((((cnt_offset * 2 * 100) / (748 * ((1 << 2) / 4) * (Freq / 1000) / 36000)) - 1) / 2) << 5; - OSC->LSI32K_TUNE += cnt_offset; - OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU; - OSC->LSI32K_CAL_CFG |= cali_Lv; - OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN; - OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN; - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END; - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; - // Fine tuning - // After configuring the fine-tuning parameters, discard the two captured values (software behavior) and judge once, only one time is left here - while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END)); - i = OSC->LSI32K_CAL_STATR; - OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN; - OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN; - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END; - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; - cnt_32k = RTC_GetCounter(); - while(RTC_GetCounter() == cnt_32k); - OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; - while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END); - while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END)); - OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN; - i = OSC->LSI32K_CAL_STATR; - cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 8000 * (1 << cali_Lv) * (Freq / 1000000) / 256 * 1000 / (CAB_LSIFQ / 256); - cnt_offset = (cnt_offset > 0) ? ((((cnt_offset * 2 * 100) / (748 * ((1 << cali_Lv) / 4) * (Freq / 1000) / 36000)) + 1) / 2) << 5 : ((((cnt_offset * 2 * 100) / (748 * ((1 << cali_Lv) / 4) * (Freq / 1000) / 36000)) - 1) / 2) << 5; - OSC->LSI32K_TUNE += cnt_offset; -} - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_rtc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/06 + * Description : This file provides all the RTC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_rtc.h" + +/* RTC_Private_Defines */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ + +/********************************************************************* + * @fn RTC_ITConfig + * + * @brief Enables or disables the specified RTC interrupts. + * + * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. + * RTC_IT_OW - Overflow interrupt + * RTC_IT_ALR - Alarm interrupt + * RTC_IT_SEC - Second interrupt + * + * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RTC->CTLRH |= RTC_IT; + } + else + { + RTC->CTLRH &= (uint16_t)~RTC_IT; + } +} + +/********************************************************************* + * @fn RTC_EnterConfigMode + * + * @brief Enters the RTC configuration mode. + * + * @return none + */ +void RTC_EnterConfigMode(void) +{ + RTC->CTLRL |= RTC_CTLRL_CNF; +} + +/********************************************************************* + * @fn RTC_ExitConfigMode + * + * @brief Exits from the RTC configuration mode. + * + * @return none + */ +void RTC_ExitConfigMode(void) +{ + RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); +} + +/********************************************************************* + * @fn RTC_GetCounter + * + * @brief Gets the RTC counter value + * + * @return RTC counter value + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0; + uint16_t low1 = 0, low2 = 0; + + do{ + high1a = RTC->CNTH; + high1b = RTC->CNTH; + }while( high1a != high1b ); + + do{ + low1 = RTC->CNTL; + low2 = RTC->CNTL; + }while( low1 != low2 ); + + do{ + high2a = RTC->CNTH; + high2b = RTC->CNTH; + }while( high2a != high2b ); + + if(high1b != high2b) + { + do{ + low1 = RTC->CNTL; + low2 = RTC->CNTL; + }while( low1 != low2 ); + } + + return (((uint32_t)high2b << 16) | low2); +} + + +/********************************************************************* + * @fn RTC_SetCounter + * + * @brief Sets the RTC counter value. + * + * @param CounterValue - RTC counter new value. + * + * @return RTC counter value + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + RTC->CNTH = CounterValue >> 16; + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetPrescaler + * + * @brief Sets the RTC prescaler value + * + * @param PrescalerValue - RTC prescaler new value + * + * @return none + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + RTC_EnterConfigMode(); + RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetAlarm + * + * @brief Sets the RTC alarm value + * + * @param AlarmValue - RTC alarm new value + * + * @return none + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + RTC->ALRMH = AlarmValue >> 16; + RTC->ALRML = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_GetDivider + * + * @brief Gets the RTC divider value + * + * @return RTC Divider value + */ +uint32_t RTC_GetDivider(void) +{ + uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0; + uint16_t low1 = 0, low2 = 0; + + do{ + high1a = RTC->DIVH; + high1b = RTC->DIVH; + }while( high1a != high1b ); + + do{ + low1 = RTC->DIVL; + low2 = RTC->DIVL; + }while( low1 != low2 ); + + do{ + high2a = RTC->DIVH; + high2b = RTC->DIVH; + }while( high2a != high2b ); + + if(high1b != high2b) + { + do{ + low1 = RTC->DIVL; + low2 = RTC->DIVL; + }while( low1 != low2 ); + } + + return ((((uint32_t)high2b & (uint32_t)0x000F) << 16) | low2); +} + +/********************************************************************* + * @fn RTC_WaitForLastTask + * + * @brief Waits until last write operation on RTC registers has finished + * Note- + * This function must be called before any write to RTC registers. + * @return none + */ +void RTC_WaitForLastTask(void) +{ + while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_WaitForSynchro + * + * @brief Waits until the RTC registers are synchronized with RTC APB clock + * Note- + * This function must be called before any read operation after an APB reset + * or an APB clock stop. + * + * @return none + */ +void RTC_WaitForSynchro(void) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; + while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_GetFlagStatus + * + * @brief Checks whether the specified RTC flag is set or not + * + * @param RTC_FLAG- specifies the flag to check + * RTC_FLAG_RTOFF - RTC Operation OFF flag + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return The new state of RTC_FLAG (SET or RESET) + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearFlag + * + * @brief Clears the RTC's pending flags + * + * @param RTC_FLAG - specifies the flag to clear + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return none + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG; +} + +/********************************************************************* + * @fn RTC_GetITStatus + * + * @brief Checks whether the specified RTC interrupt has occurred or not + * + * @param RTC_IT - specifies the RTC interrupts sources to check + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return The new state of the RTC_IT (SET or RESET) + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + + bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); + if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearITPendingBit + * + * @brief Clears the RTC's interrupt pending bits + * + * @param RTC_IT - specifies the interrupt pending bit to clear + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return none + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + RTC->CTLRL &= (uint16_t)~RTC_IT; +} + +#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) +/******************************************************************************* + * @fn Calibration_LSI + * + * @brief LSI calibration + * + * @param cali_Lv : calibration level + * Level_32 - 1.2ms 1100ppm + * Level_64 - 2.2ms 1000ppm + * Level_128 - 4.2ms 800ppm + * + * @return None + */ +void Calibration_LSI(Cali_LevelTypeDef cali_Lv) +{ + uint32_t i; + int32_t cnt_offset; + int32_t Freq = 0; + uint8_t retry = 0; + uint8_t retry_all = 0; + uint32_t cnt_32k = 0; + Freq = SystemCoreClock; + // Coarse tuning + OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU; + OSC->LSI32K_CAL_CFG |= 0; + while(1) + { + retry_all++; + while(1) + { + OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN; + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END; + while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END)); + i = OSC->LSI32K_CAL_STATR; + OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN; + OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN; + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END; + cnt_32k = RTC_GetCounter(); + while(RTC_GetCounter() == cnt_32k); + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; + while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END); + while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END)); + i = OSC->LSI32K_CAL_STATR; + cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 2000 * (Freq / 1000) / CAB_LSIFQ; + if(((cnt_offset > -(20 * (Freq / 1000) / 36000)) && (cnt_offset < (20 * (Freq / 1000) / 36000))) || retry > 2) + break; + retry++; + cnt_offset = (cnt_offset > 0) ? (((cnt_offset * 2) / (40 * (Freq / 1000) / 36000)) + 1) / 2 : (((cnt_offset * 2) / (40 * (Freq / 1000) / 36000)) - 1) / 2; + OSC->LSI32K_TUNE += cnt_offset; + } + OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU; + OSC->LSI32K_CAL_CFG |= 2; + OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN; + OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN; + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END; + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; + + // Fine tuning + // After configuring the fine-tuning parameters, discard the two captured values (software behavior) and judge once, only one time is left here + while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END)); + i = OSC->LSI32K_CAL_STATR; + OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN; + OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN; + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END; + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; + cnt_32k = RTC_GetCounter(); + while(RTC_GetCounter() == cnt_32k); + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; + while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END); + while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END)); + i = OSC->LSI32K_CAL_STATR; + cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 8000 * (1 << 2) * (Freq / 1000000) / 256 * 1000 / (CAB_LSIFQ / 256); + cnt_offset = (cnt_offset > 0) ? ((((cnt_offset * 2 * 100) / (748 * ((1 << 2) / 4) * (Freq / 1000) / 36000)) + 1) / 2) : ((((cnt_offset * 2 * 100) / (748 * ((1 << 2) / 4) * (Freq / 1000) / 36000)) - 1) / 2); + if((cnt_offset > 0)&&(((OSC->LSI32K_TUNE>>5)+cnt_offset)>0x7FF)) + { + if(retry_all>2) + { + OSC->LSI32K_TUNE |= (0xFF<<5); + } + else + { + OSC->LSI32K_TUNE = (OSC->LSI32K_TUNE&0x1F)|(0x3FF<<5); + continue; + } + } + else if((cnt_offset < 0)&&((OSC->LSI32K_TUNE>>5)<(-cnt_offset))) + { + if(retry_all>2) + { + OSC->LSI32K_TUNE &= 0x1F; + } + else + { + OSC->LSI32K_TUNE = (OSC->LSI32K_TUNE&0x1F)|(0x7F<<5); + continue; + } + } + else + { + OSC->LSI32K_TUNE += (cnt_offset<<5); + } + OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU; + OSC->LSI32K_CAL_CFG |= cali_Lv; + OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN; + OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN; + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END; + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; + // Fine tuning + // After configuring the fine-tuning parameters, discard the two captured values (software behavior) and judge once, only one time is left here + while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END)); + i = OSC->LSI32K_CAL_STATR; + OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN; + OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN; + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END; + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; + cnt_32k = RTC_GetCounter(); + while(RTC_GetCounter() == cnt_32k); + OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV; + while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END); + while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END)); + OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN; + i = OSC->LSI32K_CAL_STATR; + cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 8000 * (1 << cali_Lv) * (Freq / 1000000) / 256 * 1000 / (CAB_LSIFQ / 256); + cnt_offset = (cnt_offset > 0) ? ((((cnt_offset * 2 * 100) / (748 * ((1 << cali_Lv) / 4) * (Freq / 1000) / 36000)) + 1) / 2) : ((((cnt_offset * 2 * 100) / (748 * ((1 << cali_Lv) / 4) * (Freq / 1000) / 36000)) - 1) / 2); + if((cnt_offset > 0)&&(((OSC->LSI32K_TUNE>>5)+cnt_offset)>0x7FF)) + { + if(retry_all>2) + { + OSC->LSI32K_TUNE |= (0xFF<<5); + return; + } + else + { + OSC->LSI32K_TUNE = (OSC->LSI32K_TUNE&0x1F)|(0x3FF<<5); + continue; + } + } + else if((cnt_offset < 0)&&((OSC->LSI32K_TUNE>>5)<(-cnt_offset))) + { + if(retry_all>2) + { + OSC->LSI32K_TUNE &= 0x1F; + return; + } + else + { + OSC->LSI32K_TUNE = (OSC->LSI32K_TUNE&0x1F)|(0x3F<<5); + continue; + } + } + else + { + OSC->LSI32K_TUNE += (cnt_offset<<5); + return; + } + } +} + +#endif diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_spi.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_spi.c index 1f3f3f0..bc5488a 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_spi.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_spi.c @@ -1,638 +1,660 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_spi.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the SPI firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *********************************************************************************/ -#include "ch32v20x_spi.h" -#include "ch32v20x_rcc.h" - -/* SPI SPE mask */ -#define CTLR1_SPE_Set ((uint16_t)0x0040) -#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) - -/* I2S I2SE mask */ -#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) -#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) - -/* SPI CRCNext mask */ -#define CTLR1_CRCNext_Set ((uint16_t)0x1000) - -/* SPI CRCEN mask */ -#define CTLR1_CRCEN_Set ((uint16_t)0x2000) -#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) - -/* SPI SSOE mask */ -#define CTLR2_SSOE_Set ((uint16_t)0x0004) -#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) - -/* SPI registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) - -/* SPI or I2S mode selection masks */ -#define SPI_Mode_Select ((uint16_t)0xF7FF) -#define I2S_Mode_Select ((uint16_t)0x0800) - -/* I2S clock source selection masks */ -#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) -#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) -#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) -#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) - -/********************************************************************* - * @fn SPI_I2S_DeInit - * - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values (Affects also the I2Ss). - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * - * @return none - */ -void SPI_I2S_DeInit(SPI_TypeDef *SPIx) -{ - if(SPIx == SPI1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if(SPIx == SPI2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } -} - -/********************************************************************* - * @fn SPI_Init - * - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * - * @return none - */ -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - tmpreg = SPIx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - - SPIx->CTLR1 = tmpreg; - SPIx->I2SCFGR &= SPI_Mode_Select; - SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/********************************************************************* - * @fn I2S_Init - * - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * (configured in I2S mode). - * I2S_InitStruct - pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * @return none - */ -void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0; - RCC_ClocksTypeDef RCC_Clocks; - uint32_t sourceclock = 0; - - SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; - SPIx->I2SPR = 0x0002; - tmpreg = SPIx->I2SCFGR; - - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - else - { - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - packetlength = 1; - } - else - { - packetlength = 2; - } - - if(((uint32_t)SPIx) == SPI2_BASE) - { - tmp = I2S2_CLOCK_SRC; - } - else - { - tmp = I2S3_CLOCK_SRC; - } - - RCC_GetClocksFreq(&RCC_Clocks); - - sourceclock = RCC_Clocks.SYSCLK_Frequency; - - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - tmp = tmp / 10; - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - i2sodd = (uint16_t)(i2sodd << 8); - } - - if((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - i2sdiv = 2; - i2sodd = 0; - } - - SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - SPIx->I2SCFGR = tmpreg; -} - -/********************************************************************* - * @fn SPI_StructInit - * - * @brief Fills each SPI_InitStruct member with its default value. - * - * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) -{ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/********************************************************************* - * @fn I2S_StructInit - * - * @brief Fills each I2S_InitStruct member with its default value. - * - * @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct) -{ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/********************************************************************* - * @fn SPI_Cmd - * - * @brief Enables or disables the specified SPI peripheral. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_SPE_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_SPE_Reset; - } -} - -/********************************************************************* - * @fn I2S_Cmd - * - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; - } - else - { - SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; - } -} - -/********************************************************************* - * @fn SPI_I2S_ITConfig - * - * @brief Enables or disables the specified SPI/I2S interrupts. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_IT - specifies the SPI/I2S interrupt source to be - * enabled or disabled. - * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. - * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. - * SPI_I2S_IT_ERR - Error interrupt mask. - * NewState: ENABLE or DISABLE. - * @return none - */ -void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0; - - itpos = SPI_I2S_IT >> 4; - itmask = (uint16_t)1 << (uint16_t)itpos; - - if(NewState != DISABLE) - { - SPIx->CTLR2 |= itmask; - } - else - { - SPIx->CTLR2 &= (uint16_t)~itmask; - } -} - -/********************************************************************* - * @fn SPI_I2S_DMACmd - * - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to - * be enabled or disabled. - * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. - * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= SPI_I2S_DMAReq; - } - else - { - SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/********************************************************************* - * @fn SPI_I2S_SendData - * - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * Data - Data to be transmitted. - * - * @return none - */ -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) -{ - SPIx->DATAR = Data; -} - -/********************************************************************* - * @fn SPI_I2S_ReceiveData - * - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * Data - Data to be transmitted. - * - * @return SPIx->DATAR - The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) -{ - return SPIx->DATAR; -} - -/********************************************************************* - * @fn SPI_NSSInternalSoftwareConfig - * - * @brief Configures internally by software the NSS pin for the selected SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_NSSInternalSoft - - * SPI_NSSInternalSoft_Set - Set NSS pin internally. - * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. - * - * @return none - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) -{ - if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; - } - else - { - SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/********************************************************************* - * @fn SPI_SSOutputCmd - * - * @brief Enables or disables the SS output for the selected SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * NewState - new state of the SPIx SS output. - * - * @return none - */ -void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= CTLR2_SSOE_Set; - } - else - { - SPIx->CTLR2 &= CTLR2_SSOE_Reset; - } -} - -/********************************************************************* - * @fn SPI_DataSizeConfig - * - * @brief Configures the data size for the selected SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_DataSize - specifies the SPI data size. - * SPI_DataSize_16b - Set data frame format to 16bit. - * SPI_DataSize_8b - Set data frame format to 8bit. - * - * @return none - */ -void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) -{ - SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; - SPIx->CTLR1 |= SPI_DataSize; -} - -/********************************************************************* - * @fn SPI_TransmitCRC - * - * @brief Transmit the SPIx CRC value. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * - * @return none - */ -void SPI_TransmitCRC(SPI_TypeDef *SPIx) -{ - SPIx->CTLR1 |= CTLR1_CRCNext_Set; -} - -/********************************************************************* - * @fn SPI_CalculateCRC - * - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * NewState - new state of the SPIx CRC value calculation. - * - * @return none - */ -void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_CRCEN_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_CRCEN_Reset; - } -} - -/********************************************************************* - * @fn SPI_GetCRC - * - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_CRC - specifies the CRC register to be read. - * SPI_CRC_Tx - Selects Tx CRC register. - * SPI_CRC_Rx - Selects Rx CRC register. - * - * @return crcreg: The selected CRC register value. - */ -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - - if(SPI_CRC != SPI_CRC_Rx) - { - crcreg = SPIx->TCRCR; - } - else - { - crcreg = SPIx->RCRCR; - } - - return crcreg; -} - -/********************************************************************* - * @fn SPI_GetCRCPolynomial - * - * @brief Returns the CRC Polynomial register value for the specified SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * - * @return SPIx->CRCR - The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) -{ - return SPIx->CRCR; -} - -/********************************************************************* - * @fn SPI_BiDirectionalLineConfig - * - * @brief Selects the data transfer direction in bi-directional mode - * for the specified SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_Direction - specifies the data transfer direction in - * bi-directional mode. - * SPI_Direction_Tx - Selects Tx transmission direction. - * SPI_Direction_Rx - Selects Rx receive direction. - * - * @return none - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) -{ - if(SPI_Direction == SPI_Direction_Tx) - { - SPIx->CTLR1 |= SPI_Direction_Tx; - } - else - { - SPIx->CTLR1 &= SPI_Direction_Rx; - } -} - -/********************************************************************* - * @fn SPI_I2S_GetFlagStatus - * - * @brief Checks whether the specified SPI/I2S flag is set or not. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. - * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. - * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. - * SPI_I2S_FLAG_BSY - Busy flag. - * SPI_I2S_FLAG_OVR - Overrun flag. - * SPI_FLAG_MODF - Mode Fault flag. - * SPI_FLAG_CRCERR - CRC Error flag. - * I2S_FLAG_UDR - Underrun Error flag. - * I2S_FLAG_CHSIDE - Channel Side flag. - * - * @return none - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearFlag - * - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_FLAG - specifies the SPI flag to clear. - * SPI_FLAG_CRCERR - CRC Error flag. - * - * @return none - */ -void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; -} - -/********************************************************************* - * @fn SPI_I2S_GetITStatus - * - * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_IT - specifies the SPI/I2S interrupt source to check.. - * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. - * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. - * SPI_I2S_IT_OVR - Overrun interrupt. - * SPI_IT_MODF - Mode Fault interrupt. - * SPI_IT_CRCERR - CRC Error interrupt. - * I2S_IT_UDR - Underrun Error interrupt. - * - * @return FlagStatus: SET or RESET. - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - itmask = SPI_I2S_IT >> 4; - itmask = 0x01 << itmask; - enablestatus = (SPIx->CTLR2 & itmask); - - if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearITPendingBit - * - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. - * SPI_IT_CRCERR - CRC Error interrupt. - * - * @return none - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - SPIx->STATR = (uint16_t)~itpos; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_spi.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file provides all the SPI firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_spi.h" +#include "ch32v20x_rcc.h" + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if(SPIx == SPI2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->I2SCFGR &= SPI_Mode_Select; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn I2S_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * (configured in I2S mode). + * I2S_InitStruct - pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * + * @return none + */ +void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + tmpreg = SPIx->I2SCFGR; + + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + else + { + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + packetlength = 1; + } + else + { + packetlength = 2; + } + + if(((uint32_t)SPIx) == SPI2_BASE) + { + tmp = I2S2_CLOCK_SRC; + } + else + { + tmp = I2S3_CLOCK_SRC; + } + + RCC_GetClocksFreq(&RCC_Clocks); + + sourceclock = RCC_Clocks.SYSCLK_Frequency; + + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + tmp = tmp / 10; + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + i2sodd = (uint16_t)(i2sodd << 8); + } + + if((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + i2sdiv = 2; + i2sodd = 0; + } + + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + SPIx->I2SCFGR = tmpreg; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn I2S_StructInit + * + * @brief Fills each I2S_InitStruct member with its default value. + * + * @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct) +{ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn I2S_Cmd + * + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI/I2S interrupts. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState: ENABLE or DISABLE. + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg: The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI/I2S flag is set or not. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * I2S_FLAG_UDR - Underrun Error flag. + * I2S_FLAG_CHSIDE - Channel Side flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * Note- + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). + * @return FlagStatus: SET or RESET. + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * I2S_IT_UDR - Underrun Error interrupt. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * Note- + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable + * the SPI). + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_tim.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_tim.c index 523bac5..72c5282 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_tim.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_tim.c @@ -1,2351 +1,2353 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_tim.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the TIM firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include "ch32v20x_tim.h" -#include "ch32v20x_rcc.h" - -/* TIM registers bit mask */ -#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) -#define CHCTLR_Offset ((uint16_t)0x0018) -#define CCER_CCE_Set ((uint16_t)0x0001) -#define CCER_CCNE_Set ((uint16_t)0x0004) - -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/********************************************************************* - * @fn TIM_DeInit - * - * @brief Deinitializes the TIMx peripheral registers to their default - * reset values. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * - * @return none - */ -void TIM_DeInit(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if(TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if(TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if(TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if(TIMx == TIM5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); - } -} - -/********************************************************************* - * @fn TIM_TimeBaseInit - * - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef - * structure. - * - * @return none - */ -void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - tmpcr1 = TIMx->CTLR1; - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) - { - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - - TIMx->CTLR1 = tmpcr1; - TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if((TIMx == TIM1)) - { - TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; -} - -/********************************************************************* - * @fn TIM_OC1Init - * - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1)) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); - - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2Init - * - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1)) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3Init - * - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1)) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4Init - * - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1)) - { - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ICInit - * - * @brief IInitializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_PWMIConfig - * - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external - * PWM signal. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - - if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_BDTRConfig - * - * @brief Configures the: Break feature, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable). - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/********************************************************************* - * @fn TIM_TimeBaseStructInit - * - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * - * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. - * - * @return none - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/********************************************************************* - * @fn TIM_OCStructInit - * - * @brief Fills each TIM_OCInitStruct member with its default value. - * - * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/********************************************************************* - * @fn TIM_ICStructInit - * - * @brief Fills each TIM_ICInitStruct member with its default value. - * - * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/********************************************************************* - * @fn TIM_BDTRStructInit - * - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * - * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/********************************************************************* - * @fn TIM_Cmd - * - * @brief Enables or disables the specified TIM peripheral. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_CEN; - } - else - { - TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); - } -} - -/********************************************************************* - * @fn TIM_CtrlPWMOutputs - * - * @brief Enables or disables the TIM peripheral Main Outputs. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->BDTR |= TIM_MOE; - } - else - { - TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); - } -} - -/********************************************************************* - * @fn TIM_ITConfig - * - * @brief Enables or disables the specified TIM interrupts. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->DMAINTENR |= TIM_IT; - } - else - { - TIMx->DMAINTENR &= (uint16_t)~TIM_IT; - } -} - -/******************************************************************************* - * @fn TIM_GenerateEvent - * - * @brief Configures the TIMx event to be generate by software. - * - * @param TIMx: where x can be 1 to 4 to select the TIM peripheral. - * TIM_EventSource: specifies the event source. - * TIM_EventSource_Update: Timer update Event source. - * TIM_EventSource_CC1: Timer Capture Compare 1 Event source. - * TIM_EventSource_CC2: Timer Capture Compare 2 Event source. - * TIM_EventSource_CC3: Timer Capture Compare 3 Event source. - * TIM_EventSource_CC4: Timer Capture Compare 4 Event source. - * TIM_EventSource_COM: Timer COM event source. - * TIM_EventSource_Trigger: Timer Trigger Event source. - * TIM_EventSource_Break: Timer Break event source. - * - * @return None - */ -void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) -{ - TIMx->SWEVGR = TIM_EventSource; -} - -/********************************************************************* - * @fn TIM_DMAConfig - * - * @brief Configures the TIMx's DMA interface. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_DMABase: DMA Base address. - * TIM_DMABase_CR. - * TIM_DMABase_CR2. - * TIM_DMABase_SMCR. - * TIM_DMABase_DIER. - * TIM1_DMABase_SR. - * TIM_DMABase_EGR. - * TIM_DMABase_CCMR1. - * TIM_DMABase_CCMR2. - * TIM_DMABase_CCER. - * TIM_DMABase_CNT. - * TIM_DMABase_PSC. - * TIM_DMABase_CCR1. - * TIM_DMABase_CCR2. - * TIM_DMABase_CCR3. - * TIM_DMABase_CCR4. - * TIM_DMABase_BDTR. - * TIM_DMABase_DCR. - * TIM_DMABurstLength - DMA Burst length. - * TIM_DMABurstLength_1Transfer. - * TIM_DMABurstLength_18Transfers. - * - * @return none - */ -void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; -} - -/********************************************************************* - * @fn TIM_DMACmd - * - * @brief Enables or disables the TIMx's DMA Requests. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_DMASource - specifies the DMA Request sources. - * TIM_DMA_Update - TIM update Interrupt source. - * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. - * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. - * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. - * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. - * TIM_DMA_COM - TIM Commutation DMA source. - * TIM_DMA_Trigger - TIM Trigger DMA source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->DMAINTENR |= TIM_DMASource; - } - else - { - TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; - } -} - -/********************************************************************* - * @fn TIM_InternalClockConfig - * - * @brief Configures the TIMx internal Clock. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * - * @return none - */ -void TIM_InternalClockConfig(TIM_TypeDef *TIMx) -{ - TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); -} - -/********************************************************************* - * @fn TIM_ITRxExternalClockConfig - * - * @brief Configures the TIMx Internal Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_InputTriggerSource: Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * - * @return none - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_TIxExternalClockConfig - * - * @brief Configures the TIMx Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_TIxExternalCLKSource - Trigger source. - * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. - * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. - * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. - * TIM_ICPolarity - specifies the TIx Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_DMA_COM - TIM Commutation DMA source. - * TIM_DMA_Trigger - TIM Trigger DMA source. - * ICFilter - specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_ETRClockMode1Config - * - * @brief Configures the External clock Mode1. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_SlaveMode_External1; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_TS_ETRF; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_ETRClockMode2Config - * - * @brief Configures the External clock Mode2. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - TIMx->SMCFGR |= TIM_ECE; -} - -/********************************************************************* - * @fn TIM_ETRConfig - * - * @brief Configures the TIMx External Trigger (ETR). - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= SMCFGR_ETR_Mask; - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_PrescalerConfig - * - * @brief Configures the TIMx Prescaler. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * Prescaler - specifies the Prescaler Register value. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. - * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. - * - * @return none - */ -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - TIMx->PSC = Prescaler; - TIMx->SWEVGR = TIM_PSCReloadMode; -} - -/********************************************************************* - * @fn TIM_CounterModeConfig - * - * @brief Specifies the TIMx Counter Mode to be used. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_CounterMode - specifies the Counter Mode to be used. - * TIM_CounterMode_Up - TIM Up Counting Mode. - * TIM_CounterMode_Down - TIM Down Counting Mode. - * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. - * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. - * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. - * - * @return none - */ -void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - tmpcr1 = TIMx->CTLR1; - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= TIM_CounterMode; - TIMx->CTLR1 = tmpcr1; -} - -/********************************************************************* - * @fn TIM_SelectInputTrigger - * - * @brief Selects the Input Trigger source. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_InputTriggerSource - The Input Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * TIM_TS_TI1F_ED - TI1 Edge Detector. - * TIM_TS_TI1FP1 - Filtered Timer Input 1. - * TIM_TS_TI2FP2 - Filtered Timer Input 2. - * TIM_TS_ETRF - External Trigger input. - * - * @return none - */ -void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_InputTriggerSource; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_EncoderInterfaceConfig - * - * @brief Configures the TIMx Encoder Interface. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_EncoderMode - specifies the TIMx Encoder Mode. - * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending - * on TI2FP2 level. - * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending - * on TI1FP1 level. - * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and - * TI2FP2 edges depending. - * TIM_IC1Polarity - specifies the IC1 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TTIM_ICPolarity_Rising - IC Rising edge. - * TIM_IC2Polarity - specifies the IC2 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TIM_ICPolarity_Rising - IC Rising edge. - * - * @return none - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_EncoderMode; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); - tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; - tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - TIMx->SMCFGR = tmpsmcr; - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ForcedOC1Config - * - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC1REF. - * TIM_ForcedAction_InActive - Force inactive level on OC1REF. - * - * @return none - */ -void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); - tmpccmr1 |= TIM_ForcedAction; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC2Config - * - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC2REF. - * TIM_ForcedAction_InActive - Force inactive level on OC2REF. - * - * @return none - */ -void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC3Config - * - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC3REF. - * TIM_ForcedAction_InActive - Force inactive level on OC3REF. - * - * @return none - */ -void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); - tmpccmr2 |= TIM_ForcedAction; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ForcedOC4Config - * - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC4REF. - * TIM_ForcedAction_InActive - Force inactive level on OC4REF. - * - * @return none - */ -void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ARRPreloadConfig - * - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_ARPE; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); - } -} - -/********************************************************************* - * @fn TIM_SelectCOM - * - * @brief Selects the TIM peripheral Commutation event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCUS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); - } -} - -/********************************************************************* - * @fn TIM_SelectCCDMA - * - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCDS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); - } -} - -/********************************************************************* - * @fn TIM_CCPreloadControl - * - * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. - * reset values (Affects also the I2Ss). - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCPC; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); - } -} - -/********************************************************************* - * @fn TIM_OC1PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); - tmpccmr1 |= TIM_OCPreload; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC2PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC3PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); - tmpccmr2 |= TIM_OCPreload; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC4PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC1FastConfig - * - * @brief Configures the TIMx Output Compare 1 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); - tmpccmr1 |= TIM_OCFast; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC2FastConfig - * - * @brief Configures the TIMx Output Compare 2 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC3FastConfig - * - * @brief Configures the TIMx Output Compare 3 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); - tmpccmr2 |= TIM_OCFast; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC4FastConfig - * - * @brief Configures the TIMx Output Compare 4 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC1Ref - * - * @brief Clears or safeguards the OCREF1 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); - tmpccmr1 |= TIM_OCClear; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC2Ref - * - * @brief Clears or safeguards the OCREF2 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC3Ref - * - * @brief Clears or safeguards the OCREF3 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); - tmpccmr2 |= TIM_OCClear; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC4Ref - * - * @brief Clears or safeguards the OCREF4 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC1PolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC1 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); - tmpccer |= TIM_OCPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC1NPolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); - tmpccer |= TIM_OCNPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2PolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC2 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2NPolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3PolarityConfig - * - * @brief Configures the TIMx Channel 3 polarity. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3NPolarityConfig - * - * @brief Configures the TIMx Channel 3N polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC2N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4PolarityConfig - * - * @brief Configures the TIMx Channel 4 polarity. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_CCxCmd - * - * @brief Enables or disables the TIM Capture Compare Channel x. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_CCx - specifies the TIM Channel CCxE bit new state. - * TIM_CCx_Enable. - * TIM_CCx_Disable. - * - * @return none - */ -void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - tmp = CCER_CCE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_CCxNCmd - * - * @brief Enables or disables the TIM Capture Compare Channel xN. - * - * @param TIMx - where x can be 1 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. - * TIM_CCxN_Enable. - * TIM_CCxN_Disable. - * - * @return none - */ -void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - tmp = CCER_CCNE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_SelectOCxM - * - * @brief Selects the TIM Output Compare Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_OCMode - specifies the TIM Output Compare Mode. - * TIM_OCMode_Timing. - * TIM_OCMode_Active. - * TIM_OCMode_Toggle. - * TIM_OCMode_PWM1. - * TIM_OCMode_PWM2. - * TIM_ForcedAction_Active. - * TIM_ForcedAction_InActive. - * - * @return none - */ -void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - tmp = (uint32_t)TIMx; - tmp += CHCTLR_Offset; - tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp1; - - if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel >> 1); - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); - *(__IO uint32_t *)tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); - *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/********************************************************************* - * @fn TIM_UpdateDisableConfig - * - * @brief Enables or Disables the TIMx Update event. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_UDIS; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); - } -} - -/********************************************************************* - * @fn TIM_UpdateRequestConfig - * - * @brief Configures the TIMx Update Request Interrupt source. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_UpdateSource - specifies the Update source. - * TIM_UpdateSource_Regular. - * TIM_UpdateSource_Global. - * - * @return none - */ -void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) -{ - if(TIM_UpdateSource != TIM_UpdateSource_Global) - { - TIMx->CTLR1 |= TIM_URS; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); - } -} - -/********************************************************************* - * @fn TIM_SelectHallSensor - * - * @brief Enables or disables the TIMx's Hall sensor interface. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_TI1S; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); - } -} - -/********************************************************************* - * @fn TIM_SelectOnePulseMode - * - * @brief Selects the TIMx's One Pulse Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OPMode - specifies the OPM Mode to be used. - * TIM_OPMode_Single. - * TIM_OPMode_Repetitive. - * - * @return none - */ -void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); - TIMx->CTLR1 |= TIM_OPMode; -} - -/********************************************************************* - * @fn TIM_SelectOutputTrigger - * - * @brief Selects the TIMx Trigger Output Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_TRGOSource - specifies the Trigger Output source. - * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is - * used as the trigger output (TRGO). - * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the - * trigger output (TRGO). - * TIM_TRGOSource_Update - The update event is selected as the - * trigger output (TRGO). - * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse - * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). - * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). - * - * @return none - */ -void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) -{ - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); - TIMx->CTLR2 |= TIM_TRGOSource; -} - -/********************************************************************* - * @fn TIM_SelectSlaveMode - * - * @brief Selects the TIMx Slave Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_SlaveMode - specifies the Timer Slave Mode. - * TIM_SlaveMode_Reset - Rising edge of the selected trigger - * signal (TRGI) re-initializes. - * TIM_SlaveMode_Gated - The counter clock is enabled when the - * trigger signal (TRGI) is high. - * TIM_SlaveMode_Trigger - The counter starts at a rising edge - * of the trigger TRGI. - * TIM_SlaveMode_External1 - Rising edges of the selected trigger - * (TRGI) clock the counter. - * - * @return none - */ -void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) -{ - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); - TIMx->SMCFGR |= TIM_SlaveMode; -} - -/********************************************************************* - * @fn TIM_SelectMasterSlaveMode - * - * @brief Sets or Resets the TIMx Master/Slave Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. - * TIM_MasterSlaveMode_Enable - synchronization between the current - * timer and its slaves (through TRGO). - * TIM_MasterSlaveMode_Disable - No action. - * - * @return none - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) -{ - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); - TIMx->SMCFGR |= TIM_MasterSlaveMode; -} - -/********************************************************************* - * @fn TIM_SetCounter - * - * @brief Sets the TIMx Counter Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Counter - specifies the Counter register new value. - * - * @return none - */ -void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) -{ - TIMx->CNT = Counter; -} - -/********************************************************************* - * @fn TIM_SetAutoreload - * - * @brief Sets the TIMx Autoreload Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Autoreload - specifies the Autoreload register new value. - * - * @return none - */ -void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) -{ - TIMx->ATRLR = Autoreload; -} - -/********************************************************************* - * @fn TIM_SetCompare1 - * - * @brief Sets the TIMx Capture Compare1 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) -{ - TIMx->CH1CVR = Compare1; -} - -/********************************************************************* - * @fn TIM_SetCompare2 - * - * @brief Sets the TIMx Capture Compare2 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) -{ - TIMx->CH2CVR = Compare2; -} - -/********************************************************************* - * @fn TIM_SetCompare3 - * - * @brief Sets the TIMx Capture Compare3 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) -{ - TIMx->CH3CVR = Compare3; -} - -/********************************************************************* - * @fn TIM_SetCompare4 - * - * @brief Sets the TIMx Capture Compare4 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) -{ - TIMx->CH4CVR = Compare4; -} - -/********************************************************************* - * @fn TIM_SetIC1Prescaler - * - * @brief Sets the TIMx Input Capture 1 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); - TIMx->CHCTLR1 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC2Prescaler - * - * @brief Sets the TIMx Input Capture 2 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); - TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetIC3Prescaler - * - * @brief Sets the TIMx Input Capture 3 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); - TIMx->CHCTLR2 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC4Prescaler - * - * @brief Sets the TIMx Input Capture 4 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); - TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetClockDivision - * - * @brief Sets the TIMx Clock Division value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_CKD - specifies the clock division value. - * TIM_CKD_DIV1 - TDTS = Tck_tim. - * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. - * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. - * - * @return none - */ -void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); - TIMx->CTLR1 |= TIM_CKD; -} - -/********************************************************************* - * @fn TIM_GetCapture1 - * - * @brief Gets the TIMx Input Capture 1 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH1CVR - Capture Compare 1 Register value. - */ -uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) -{ - return TIMx->CH1CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture2 - * - * @brief Gets the TIMx Input Capture 2 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH2CVR - Capture Compare 2 Register value. - */ -uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) -{ - return TIMx->CH2CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture3 - * - * @brief Gets the TIMx Input Capture 3 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH3CVR - Capture Compare 3 Register value. - */ -uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) -{ - return TIMx->CH3CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture4 - * - * @brief Gets the TIMx Input Capture 4 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH4CVR - Capture Compare 4 Register value. - */ -uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) -{ - return TIMx->CH4CVR; -} - -/********************************************************************* - * @fn TIM_GetCounter - * - * @brief Gets the TIMx Counter value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CNT - Counter Register value. - */ -uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) -{ - return TIMx->CNT; -} - -/********************************************************************* - * @fn TIM_GetPrescaler - * - * @brief Gets the TIMx Prescaler value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->PSC - Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) -{ - return TIMx->PSC; -} - -/********************************************************************* - * @fn TIM_GetFlagStatus - * - * @brief Checks whether the specified TIM flag is set or not. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return none - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - - if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearFlag - * - * @brief Clears the TIMx's pending flags. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return none - */ -void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - TIMx->INTFR = (uint16_t)~TIM_FLAG; -} - -/********************************************************************* - * @fn TIM_GetITStatus - * - * @brief Checks whether the TIM interrupt has occurred or not. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - - itstatus = TIMx->INTFR & TIM_IT; - - itenable = TIMx->DMAINTENR & TIM_IT; - if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearITPendingBit - * - * @brief Clears the TIMx's interrupt pending bits. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - TIMx->INTFR = (uint16_t)~TIM_IT; -} - -/********************************************************************* - * @fn TI1_Config - * - * @brief Configure the TI1 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI2_Config - * - * @brief Configure the TI2 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI3_Config - * - * @brief Configure the TI3 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI4_Config - * - * @brief Configure the TI4 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC4NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_tim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file provides all the TIM firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_tim.h" +#include "ch32v20x_rcc.h" + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if(TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if(TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if(TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + + TIMx->CTLR1 = tmpcr1; + TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if((TIMx == TIM1)) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1)) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1/8/9/10 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +/******************************************************************************* + * @fn TIM_GenerateEvent + * + * @brief Configures the TIMx event to be generate by software. + * + * @param TIMx: where x can be 1 to 4 to select the TIM peripheral. + * TIM_EventSource: specifies the event source. + * TIM_EventSource_Update: Timer update Event source. + * TIM_EventSource_CC1: Timer Capture Compare 1 Event source. + * TIM_EventSource_CC2: Timer Capture Compare 2 Event source. + * TIM_EventSource_CC3: Timer Capture Compare 3 Event source. + * TIM_EventSource_CC4: Timer Capture Compare 4 Event source. + * TIM_EventSource_COM: Timer COM event source. + * TIM_EventSource_Trigger: Timer Trigger Event source. + * TIM_EventSource_Break: Timer Break event source. + * + * @return None + */ +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMABase: DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values (Affects also the I2Ss). + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 4 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) +{ + TIMx->CNT = Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) +{ + TIMx->ATRLR = Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) +{ + TIMx->CH1CVR = Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) +{ + TIMx->CH2CVR = Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) +{ + TIMx->CH3CVR = Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) +{ + TIMx->CH4CVR = Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture3 + * + * @brief Gets the TIMx Input Capture 3 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH3CVR - Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P )); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_usart.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_usart.c index 4985fef..e635ade 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_usart.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_usart.c @@ -1,806 +1,740 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_usart.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the USART firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include "ch32v20x_usart.h" -#include "ch32v20x_rcc.h" - -/* USART_Private_Defines */ -#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ -#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ - -#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ - -#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ -#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ -#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ -#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ - -#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ -#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ - -#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ -#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ -#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ - -#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ -#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ - -#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ -#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ - -#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ -#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ - -#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ -#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ - -#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ -#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ -#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ -#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ -#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ - -/* USART OverSampling-8 Mask */ -#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ -#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ - -/* USART One Bit Sampling Mask */ -#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ -#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ - -/********************************************************************* - * @fn USART_DeInit - * - * @brief Deinitializes the USARTx peripheral registers to their default - * reset values. - * - * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. - * - * @return none - */ -void USART_DeInit(USART_TypeDef *USARTx) -{ - if(USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if(USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if(USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if(USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } -} - -/********************************************************************* - * @fn USART_Init - * - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct. - * - * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. - * USART_InitStruct - pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified - * USART peripheral. - * - * @return none - */ -void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - uint32_t usartxbase = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - - if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - } - - usartxbase = (uint32_t)USARTx; - tmpreg = USARTx->CTLR2; - tmpreg &= CTLR2_STOP_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - USARTx->CTLR2 = (uint16_t)tmpreg; - tmpreg = USARTx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - USARTx->CTLR1 = (uint16_t)tmpreg; - - tmpreg = USARTx->CTLR3; - tmpreg &= CTLR3_CLEAR_Mask; - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - USARTx->CTLR3 = (uint16_t)tmpreg; - - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if(usartxbase == USART1_BASE) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) - { - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else - { - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - USARTx->BRR = (uint16_t)tmpreg; -} - -/********************************************************************* - * @fn USART_StructInit - * - * @brief Fills each USART_InitStruct member with its default value. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * - * @return none - */ -void USART_StructInit(USART_InitTypeDef *USART_InitStruct) -{ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/********************************************************************* - * @fn USART_ClockInit - * - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * - * @return none - */ -void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - - tmpreg = USARTx->CTLR2; - tmpreg &= CTLR2_CLOCK_CLEAR_Mask; - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - USARTx->CTLR2 = (uint16_t)tmpreg; -} - -/********************************************************************* - * @fn USART_ClockStructInit - * - * @brief Fills each USART_ClockStructInit member with its default value. - * - * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * - * @return none - */ -void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/********************************************************************* - * @fn USART_Cmd - * - * @brief Enables or disables the specified USART peripheral. - * reset values (Affects also the I2Ss). - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_UE_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_UE_Reset; - } -} - -/********************************************************************* - * @fn USART_ITConfig - * - * @brief Enables or disables the specified USART interrupts. - * reset values (Affects also the I2Ss). - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_IT - specifies the USART interrupt sources to be enabled or disabled. - * USART_IT_CTS - CTS change interrupt. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Transmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_PE - Parity Error interrupt. - * USART_IT_ERR - Error interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - - if(USART_IT == USART_IT_CTS) - { - } - - usartxbase = (uint32_t)USARTx; - usartreg = (((uint8_t)USART_IT) >> 0x05); - itpos = USART_IT & IT_Mask; - itmask = (((uint32_t)0x01) << itpos); - - if(usartreg == 0x01) - { - usartxbase += 0x0C; - } - else if(usartreg == 0x02) - { - usartxbase += 0x10; - } - else - { - usartxbase += 0x14; - } - - if(NewState != DISABLE) - { - *(__IO uint32_t *)usartxbase |= itmask; - } - else - { - *(__IO uint32_t *)usartxbase &= ~itmask; - } -} - -/********************************************************************* - * @fn USART_DMACmd - * - * @brief Enables or disables the USART DMA interface. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_DMAReq - specifies the DMA request. - * USART_DMAReq_Tx - USART DMA transmit request. - * USART_DMAReq_Rx - USART DMA receive request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= USART_DMAReq; - } - else - { - USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; - } -} - -/********************************************************************* - * @fn USART_SetAddress - * - * @brief Sets the address of the USART node. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_Address - Indicates the address of the USART node. - * - * @return none - */ -void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) -{ - USARTx->CTLR2 &= CTLR2_Address_Mask; - USARTx->CTLR2 |= USART_Address; -} - -/********************************************************************* - * @fn USART_WakeUpConfig - * - * @brief Selects the USART WakeUp method. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_WakeUp - specifies the USART wakeup method. - * USART_WakeUp_IdleLine - WakeUp by an idle line detection. - * USART_WakeUp_AddressMark - WakeUp by an address mark. - * - * @return none - */ -void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) -{ - USARTx->CTLR1 &= CTLR1_WAKE_Mask; - USARTx->CTLR1 |= USART_WakeUp; -} - -/********************************************************************* - * @fn USART_ReceiverWakeUpCmd - * - * @brief Determines if the USART is in mute mode or not. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_RWU_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_RWU_Reset; - } -} - -/********************************************************************* - * @fn USART_LINBreakDetectLengthConfig - * - * @brief Sets the USART LIN Break detection length. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_LINBreakDetectLength - specifies the LIN break detection length. - * USART_LINBreakDetectLength_10b - 10-bit break detection. - * USART_LINBreakDetectLength_11b - 11-bit break detection. - * - * @return none - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) -{ - USARTx->CTLR2 &= CTLR2_LBDL_Mask; - USARTx->CTLR2 |= USART_LINBreakDetectLength; -} - -/********************************************************************* - * @fn USART_LINCmd - * - * @brief Enables or disables the USART LIN mode. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR2 |= CTLR2_LINEN_Set; - } - else - { - USARTx->CTLR2 &= CTLR2_LINEN_Reset; - } -} - -/********************************************************************* - * @fn USART_SendData - * - * @brief Transmits single data through the USARTx peripheral. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * Data - the data to transmit. - * - * @return none - */ -void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) -{ - USARTx->DATAR = (Data & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_ReceiveData - * - * @brief Returns the most recent received data by the USARTx peripheral. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * - * @return The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef *USARTx) -{ - return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_SendBreak - * - * @brief Transmits break characters. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * - * @return none - */ -void USART_SendBreak(USART_TypeDef *USARTx) -{ - USARTx->CTLR1 |= CTLR1_SBK_Set; -} - -/********************************************************************* - * @fn USART_SetGuardTime - * - * @brief Sets the specified USART guard time. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_GuardTime - specifies the guard time. - * - * @return none - */ -void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) -{ - USARTx->GPR &= GPR_LSB_Mask; - USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/********************************************************************* - * @fn USART_SetPrescaler - * - * @brief Sets the system clock prescaler. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_Prescaler - specifies the prescaler clock. - * - * @return none - */ -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) -{ - USARTx->GPR &= GPR_MSB_Mask; - USARTx->GPR |= USART_Prescaler; -} - -/********************************************************************* - * @fn USART_SmartCardCmd - * - * @brief Enables or disables the USART Smart Card mode. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_SCEN_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_SCEN_Reset; - } -} - -/********************************************************************* - * @fn USART_SmartCardNACKCmd - * - * @brief Enables or disables NACK transmission. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_NACK_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_NACK_Reset; - } -} - -/********************************************************************* - * @fn USART_HalfDuplexCmd - * - * @brief Enables or disables the USART Half Duplex communication. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_HDSEL_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_HDSEL_Reset; - } -} - -/********************************************************************* - * @fn USART_OverSampling8Cmd - * - * @brief Enables or disables the USART's 8x oversampling mode. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_OVER8_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_OVER8_Reset; - } -} - -/********************************************************************* - * @fn USART_OneBitMethodCmd - * - * @brief Enables or disables the USART's one bit sampling method. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_ONEBITE_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_ONEBITE_Reset; - } -} - -/********************************************************************* - * @fn USART_IrDAConfig - * - * @brief Configures the USART's IrDA interface. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_IrDAMode - specifies the IrDA mode. - * USART_IrDAMode_LowPower. - * USART_IrDAMode_Normal. - * - * @return none - */ -void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) -{ - USARTx->CTLR3 &= CTLR3_IRLP_Mask; - USARTx->CTLR3 |= USART_IrDAMode; -} - -/********************************************************************* - * @fn USART_IrDACmd - * - * @brief Enables or disables the USART's IrDA interface. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_IREN_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_IREN_Reset; - } -} - -/********************************************************************* - * @fn USART_GetFlagStatus - * - * @brief Checks whether the specified USART flag is set or not. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_FLAG - specifies the flag to check. - * USART_FLAG_CTS - CTS Change flag. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TXE - Transmit data register empty flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * USART_FLAG_IDLE - Idle Line detection flag. - * USART_FLAG_ORE - OverRun Error flag. - * USART_FLAG_NE - Noise Error flag. - * USART_FLAG_FE - Framing Error flag. - * USART_FLAG_PE - Parity Error flag. - * - * @return none - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - - if(USART_FLAG == USART_FLAG_CTS) - { - } - - if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearFlag - * - * @brief Clears the USARTx's pending flags. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_FLAG - specifies the flag to clear. - * USART_FLAG_CTS - CTS Change flag. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * - * @return none - */ -void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - if((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) - { - } - - USARTx->STATR = (uint16_t)~USART_FLAG; -} - -/********************************************************************* - * @fn USART_GetITStatus - * - * @brief Checks whether the specified USART interrupt has occurred or not. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_IT - specifies the USART interrupt source to check. - * USART_IT_CTS - CTS change interrupt. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Tansmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. - * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. - * USART_IT_NE - Noise Error interrupt. - * USART_IT_FE - Framing Error interrupt. - * USART_IT_PE - Parity Error interrupt. - * - * @return none - */ -ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - - if(USART_IT == USART_IT_CTS) - { - } - - usartreg = (((uint8_t)USART_IT) >> 0x05); - itmask = USART_IT & IT_Mask; - itmask = (uint32_t)0x01 << itmask; - - if(usartreg == 0x01) - { - itmask &= USARTx->CTLR1; - } - else if(usartreg == 0x02) - { - itmask &= USARTx->CTLR2; - } - else - { - itmask &= USARTx->CTLR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->STATR; - - if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearITPendingBit - * - * @brief Clears the USARTx's interrupt pending bits. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_IT - specifies the interrupt pending bit to clear. - * USART_IT_CTS - CTS change interrupt. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * - * @return none - */ -void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - - if(USART_IT == USART_IT_CTS) - { - } - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->STATR = (uint16_t)~itmask; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_usart.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/06 + * Description : This file provides all the USART firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_usart.h" +#include "ch32v20x_rcc.h" + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if(USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if(USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if(USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + tmpreg = (integerdivider / 100) << 4; + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return bitstatus: SET or RESET + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DATAR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_STATR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DATAR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return bitstatus: SET or RESET. + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_STATR register + * (USART_GetITStatus()) followed by a read operation to USART_DATAR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_STATR register (USART_GetITStatus()) followed by a write + * operation to USART_DATAR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_wwdg.c b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_wwdg.c index 522a871..9d3281b 100644 --- a/system/CH32V20x/SRC/Peripheral/src/ch32v20x_wwdg.c +++ b/system/CH32V20x/SRC/Peripheral/src/ch32v20x_wwdg.c @@ -1,139 +1,141 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_wwdg.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : This file provides all the WWDG firmware functions. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - **********************************************************************************/ -#include "ch32v20x_wwdg.h" -#include "ch32v20x_rcc.h" - -/* CTLR register bit mask */ -#define CTLR_WDGA_Set ((uint32_t)0x00000080) - -/* CFGR register bit mask */ -#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) -#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) -#define BIT_Mask ((uint8_t)0x7F) - -/********************************************************************* - * @fn WWDG_DeInit - * - * @brief Deinitializes the WWDG peripheral registers to their default reset values - * - * @return none - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/********************************************************************* - * @fn WWDG_SetPrescaler - * - * @brief Sets the WWDG Prescaler - * - * @param WWDG_Prescaler - specifies the WWDG Prescaler - * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 - * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 - * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 - * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 - * - * @return none - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; - tmpreg |= WWDG_Prescaler; - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_SetWindowValue - * - * @brief Sets the WWDG window value - * - * @param WindowValue - specifies the window value to be compared to the - * downcounter,which must be lower than 0x80 - * - * @return none - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - tmpreg = WWDG->CFGR & CFGR_W_Mask; - - tmpreg |= WindowValue & (uint32_t)BIT_Mask; - - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_EnableIT - * - * @brief Enables the WWDG Early Wakeup interrupt(EWI) - * - * @return none - */ -void WWDG_EnableIT(void) -{ - WWDG->CFGR |= (1 << 9); -} - -/********************************************************************* - * @fn WWDG_SetCounter - * - * @brief Sets the WWDG counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * - * @return none - */ -void WWDG_SetCounter(uint8_t Counter) -{ - WWDG->CTLR = Counter & BIT_Mask; -} - -/********************************************************************* - * @fn WWDG_Enable - * - * @brief Enables WWDG and load the counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * @return none - */ -void WWDG_Enable(uint8_t Counter) -{ - WWDG->CTLR = CTLR_WDGA_Set | Counter; -} - -/********************************************************************* - * @fn WWDG_GetFlagStatus - * - * @brief Checks whether the Early Wakeup interrupt flag is set or not - * - * @return The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - return (FlagStatus)(WWDG->STATR); -} - -/********************************************************************* - * @fn WWDG_ClearFlag - * - * @brief Clears Early Wakeup interrupt flag - * - * @return none - */ -void WWDG_ClearFlag(void) -{ - WWDG->STATR = (uint32_t)RESET; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_wwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file provides all the WWDG firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32v20x_wwdg.h" +#include "ch32v20x_rcc.h" + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/system/CH32V20x/SRC/Startup/startup_ch32v20x_D6.S b/system/CH32V20x/SRC/Startup/startup_ch32v20x_D6.S index 50de9cc..d723a5d 100644 --- a/system/CH32V20x/SRC/Startup/startup_ch32v20x_D6.S +++ b/system/CH32V20x/SRC/Startup/startup_ch32v20x_D6.S @@ -1,32 +1,22 @@ ;/********************************** (C) COPYRIGHT ******************************* ;* File Name : startup_ch32v20x_D6.s ;* Author : WCH -;* Version : V1.0.0 -;* Date : 2021/06/06 -;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8 +;* Version : V1.0.1 +;* Date : 2024/01/31 +;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8 ;* vector table for eclipse toolchain. +;********************************************************************************* ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -;* SPDX-License-Identifier: Apache-2.0 -;*******************************************************************************/ +;* Attention: This software (modified or not) and binary are used for +;* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + .section .init,"ax",@progbits .global _start .align 1 _start: - j handle_reset - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00100073 + .section .vector,"ax",@progbits .align 1 _vector_base: @@ -91,13 +81,12 @@ _vector_base: .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ - .word USBHD_IRQHandler /* USBHD Break */ - .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ + .word USBFS_IRQHandler /* USBFS Break */ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ .word UART4_IRQHandler /* UART4 */ .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ .option rvc; - .section .text.vector_handler, "ax", @progbits .weak NMI_Handler /* NMI */ .weak HardFault_Handler /* Hard Fault */ @@ -149,65 +138,67 @@ _vector_base: .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ - .weak USBHD_IRQHandler /* USBHD */ - .weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */ + .weak USBFS_IRQHandler /* USBFS */ + .weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */ .weak UART4_IRQHandler /* UART4 */ .weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ -NMI_Handler: 1: j 1b -HardFault_Handler: 1: j 1b -Ecall_M_Mode_Handler: 1: j 1b -Ecall_U_Mode_Handler: 1: j 1b -Break_Point_Handler: 1: j 1b -SysTick_Handler: 1: j 1b -SW_Handler: 1: j 1b -WWDG_IRQHandler: 1: j 1b -PVD_IRQHandler: 1: j 1b -TAMPER_IRQHandler: 1: j 1b -RTC_IRQHandler: 1: j 1b -FLASH_IRQHandler: 1: j 1b -RCC_IRQHandler: 1: j 1b -EXTI0_IRQHandler: 1: j 1b -EXTI1_IRQHandler: 1: j 1b -EXTI2_IRQHandler: 1: j 1b -EXTI3_IRQHandler: 1: j 1b -EXTI4_IRQHandler: 1: j 1b -DMA1_Channel1_IRQHandler: 1: j 1b -DMA1_Channel2_IRQHandler: 1: j 1b -DMA1_Channel3_IRQHandler: 1: j 1b -DMA1_Channel4_IRQHandler: 1: j 1b -DMA1_Channel5_IRQHandler: 1: j 1b -DMA1_Channel6_IRQHandler: 1: j 1b -DMA1_Channel7_IRQHandler: 1: j 1b -ADC1_2_IRQHandler: 1: j 1b -USB_HP_CAN1_TX_IRQHandler: 1: j 1b -USB_LP_CAN1_RX0_IRQHandler: 1: j 1b -CAN1_RX1_IRQHandler: 1: j 1b -CAN1_SCE_IRQHandler: 1: j 1b -EXTI9_5_IRQHandler: 1: j 1b -TIM1_BRK_IRQHandler: 1: j 1b -TIM1_UP_IRQHandler: 1: j 1b -TIM1_TRG_COM_IRQHandler: 1: j 1b -TIM1_CC_IRQHandler: 1: j 1b -TIM2_IRQHandler: 1: j 1b -TIM3_IRQHandler: 1: j 1b -TIM4_IRQHandler: 1: j 1b -I2C1_EV_IRQHandler: 1: j 1b -I2C1_ER_IRQHandler: 1: j 1b -I2C2_EV_IRQHandler: 1: j 1b -I2C2_ER_IRQHandler: 1: j 1b -SPI1_IRQHandler: 1: j 1b -SPI2_IRQHandler: 1: j 1b -USART1_IRQHandler: 1: j 1b -USART2_IRQHandler: 1: j 1b -USART3_IRQHandler: 1: j 1b -EXTI15_10_IRQHandler: 1: j 1b -RTCAlarm_IRQHandler: 1: j 1b -USBWakeUp_IRQHandler: 1: j 1b -USBHD_IRQHandler: 1: j 1b -USBHDWakeUp_IRQHandler: 1: j 1b -UART4_IRQHandler: 1: j 1b -DMA1_Channel8_IRQHandler: 1: j 1b +NMI_Handler: +HardFault_Handler: +Ecall_M_Mode_Handler: +Ecall_U_Mode_Handler: +Break_Point_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +TAMPER_IRQHandler: +RTC_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI0_IRQHandler: +EXTI1_IRQHandler: +EXTI2_IRQHandler: +EXTI3_IRQHandler: +EXTI4_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_2_IRQHandler: +USB_HP_CAN1_TX_IRQHandler: +USB_LP_CAN1_RX0_IRQHandler: +CAN1_RX1_IRQHandler: +CAN1_SCE_IRQHandler: +EXTI9_5_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +TIM3_IRQHandler: +TIM4_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +I2C2_EV_IRQHandler: +I2C2_ER_IRQHandler: +SPI1_IRQHandler: +SPI2_IRQHandler: +USART1_IRQHandler: +USART2_IRQHandler: +USART3_IRQHandler: +EXTI15_10_IRQHandler: +RTCAlarm_IRQHandler: +USBWakeUp_IRQHandler: +USBFS_IRQHandler: +USBFSWakeUp_IRQHandler: +UART4_IRQHandler: +DMA1_Channel8_IRQHandler: +1: + j 1b .section .text.handle_reset,"ax",@progbits .weak handle_reset @@ -220,7 +211,7 @@ handle_reset: 1: la sp, _eusrstack 2: - /* Load data section from flash to RAM */ +/* Load data section from flash to RAM */ la a0, _data_lma la a1, _data_vma la a2, _edata @@ -232,7 +223,7 @@ handle_reset: addi a1, a1, 4 bltu a1, a2, 1b 2: - /* Clear bss section */ +/* Clear bss section */ la a0, _sbss la a1, _ebss bgeu a0, a1, 2f @@ -241,25 +232,20 @@ handle_reset: addi a0, a0, 4 bltu a0, a1, 1b 2: +/* Configure pipelining and instruction prediction */ li t0, 0x1f csrw 0xbc0, t0 - - /* Enable nested and hardware stack */ +/* Enable interrupt nesting and hardware stack */ li t0, 0x3 csrw 0x804, t0 - - /* Enable interrupt */ +/* Enable global interrupt and configure privileged mode */ li t0, 0x88 - csrs mstatus, t0 - + csrw mstatus, t0 +/* Configure the interrupt vector table recognition mode and entry address mode */ la t0, _vector_base ori t0, t0, 3 csrw mtvec, t0 - la a0, __libc_fini_array - call atexit - call __libc_init_array - jal SystemInit la t0, main csrw mepc, t0 diff --git a/system/CH32V20x/SRC/Startup/startup_ch32v20x_D8.S b/system/CH32V20x/SRC/Startup/startup_ch32v20x_D8.S index 8cdfe8b..a22ff1a 100644 --- a/system/CH32V20x/SRC/Startup/startup_ch32v20x_D8.S +++ b/system/CH32V20x/SRC/Startup/startup_ch32v20x_D8.S @@ -1,8 +1,8 @@ ;/********************************** (C) COPYRIGHT ******************************* ;* File Name : startup_ch32v20x_D8.s ;* Author : WCH -;* Version : V1.0.0 -;* Date : 2021/06/06 +;* Version : V1.0.1 +;* Date : 2024/01/31 ;* Description : CH32V203RB ;* vector table for eclipse toolchain. ;********************************************************************************* @@ -16,19 +16,7 @@ .align 1 _start: j handle_reset - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00100073 + .section .vector,"ax",@progbits .align 1 _vector_base: @@ -93,8 +81,8 @@ _vector_base: .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ - .word USBHD_IRQHandler /* USBHD Break */ - .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ + .word USBFS_IRQHandler /* USBFS Break */ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ .word ETH_IRQHandler /* ETH global */ .word ETHWakeUp_IRQHandler /* ETH Wake up */ .word 0 /* BLE BB */ @@ -106,7 +94,6 @@ _vector_base: .word OSCWakeUp_IRQHandler /* OSC Wake Up */ .option rvc; - .section .text.vector_handler, "ax", @progbits .weak NMI_Handler /* NMI */ .weak HardFault_Handler /* Hard Fault */ @@ -158,8 +145,8 @@ _vector_base: .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ - .weak USBHD_IRQHandler /* USBHD */ - .weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */ + .weak USBFS_IRQHandler /* USBFS */ + .weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */ .weak ETH_IRQHandler /* ETH global */ .weak ETHWakeUp_IRQHandler /* ETHWakeUp */ .weak TIM5_IRQHandler /* TIM5 */ @@ -168,65 +155,67 @@ _vector_base: .weak OSC32KCal_IRQHandler /* OSC32 KCal */ .weak OSCWakeUp_IRQHandler /* OSC Wake Up */ -NMI_Handler: 1: j 1b -HardFault_Handler: 1: j 1b -Ecall_M_Mode_Handler: 1: j 1b -Ecall_U_Mode_Handler: 1: j 1b -Break_Point_Handler: 1: j 1b -SysTick_Handler: 1: j 1b -SW_Handler: 1: j 1b -WWDG_IRQHandler: 1: j 1b -PVD_IRQHandler: 1: j 1b -TAMPER_IRQHandler: 1: j 1b -RTC_IRQHandler: 1: j 1b -FLASH_IRQHandler: 1: j 1b -RCC_IRQHandler: 1: j 1b -EXTI0_IRQHandler: 1: j 1b -EXTI1_IRQHandler: 1: j 1b -EXTI2_IRQHandler: 1: j 1b -EXTI3_IRQHandler: 1: j 1b -EXTI4_IRQHandler: 1: j 1b -DMA1_Channel1_IRQHandler: 1: j 1b -DMA1_Channel2_IRQHandler: 1: j 1b -DMA1_Channel3_IRQHandler: 1: j 1b -DMA1_Channel4_IRQHandler: 1: j 1b -DMA1_Channel5_IRQHandler: 1: j 1b -DMA1_Channel6_IRQHandler: 1: j 1b -DMA1_Channel7_IRQHandler: 1: j 1b -ADC1_2_IRQHandler: 1: j 1b -USB_HP_CAN1_TX_IRQHandler: 1: j 1b -USB_LP_CAN1_RX0_IRQHandler: 1: j 1b -CAN1_RX1_IRQHandler: 1: j 1b -CAN1_SCE_IRQHandler: 1: j 1b -EXTI9_5_IRQHandler: 1: j 1b -TIM1_BRK_IRQHandler: 1: j 1b -TIM1_UP_IRQHandler: 1: j 1b -TIM1_TRG_COM_IRQHandler: 1: j 1b -TIM1_CC_IRQHandler: 1: j 1b -TIM2_IRQHandler: 1: j 1b -TIM3_IRQHandler: 1: j 1b -TIM4_IRQHandler: 1: j 1b -I2C1_EV_IRQHandler: 1: j 1b -I2C1_ER_IRQHandler: 1: j 1b -I2C2_EV_IRQHandler: 1: j 1b -I2C2_ER_IRQHandler: 1: j 1b -SPI1_IRQHandler: 1: j 1b -SPI2_IRQHandler: 1: j 1b -USART1_IRQHandler: 1: j 1b -USART2_IRQHandler: 1: j 1b -USART3_IRQHandler: 1: j 1b -EXTI15_10_IRQHandler: 1: j 1b -RTCAlarm_IRQHandler: 1: j 1b -USBWakeUp_IRQHandler: 1: j 1b -USBHD_IRQHandler: 1: j 1b -USBHDWakeUp_IRQHandler: 1: j 1b -ETH_IRQHandler: 1: j 1b -ETHWakeUp_IRQHandler: 1: j 1b -TIM5_IRQHandler: 1: j 1b -OSC32KCal_IRQHandler: 1: j 1b -OSCWakeUp_IRQHandler: 1: j 1b -UART4_IRQHandler: 1: j 1b -DMA1_Channel8_IRQHandler: 1: j 1b +NMI_Handler: +HardFault_Handler: +Ecall_M_Mode_Handler: +Ecall_U_Mode_Handler: +Break_Point_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +TAMPER_IRQHandler: +RTC_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI0_IRQHandler: +EXTI1_IRQHandler: +EXTI2_IRQHandler: +EXTI3_IRQHandler: +EXTI4_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_2_IRQHandler: +USB_HP_CAN1_TX_IRQHandler: +USB_LP_CAN1_RX0_IRQHandler: +CAN1_RX1_IRQHandler: +CAN1_SCE_IRQHandler: +EXTI9_5_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +TIM3_IRQHandler: +TIM4_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +I2C2_EV_IRQHandler: +I2C2_ER_IRQHandler: +SPI1_IRQHandler: +SPI2_IRQHandler: +USART1_IRQHandler: +USART2_IRQHandler: +USART3_IRQHandler: +EXTI15_10_IRQHandler: +RTCAlarm_IRQHandler: +USBWakeUp_IRQHandler: +USBFS_IRQHandler: +USBFSWakeUp_IRQHandler: +ETH_IRQHandler: +ETHWakeUp_IRQHandler: +TIM5_IRQHandler: +OSC32KCal_IRQHandler: +OSCWakeUp_IRQHandler: +UART4_IRQHandler: +DMA1_Channel8_IRQHandler: +1: + j 1b .section .text.handle_reset,"ax",@progbits .weak handle_reset @@ -239,7 +228,7 @@ handle_reset: 1: la sp, _eusrstack 2: - /* Load data section from flash to RAM */ +/* Load data section from flash to RAM */ la a0, _data_lma la a1, _data_vma la a2, _edata @@ -251,7 +240,7 @@ handle_reset: addi a1, a1, 4 bltu a1, a2, 1b 2: - /* Clear bss section */ +/* Clear bss section */ la a0, _sbss la a1, _ebss bgeu a0, a1, 2f @@ -260,24 +249,19 @@ handle_reset: addi a0, a0, 4 bltu a0, a1, 1b 2: +/* Configure pipelining and instruction prediction */ li t0, 0x1f csrw 0xbc0, t0 - - /* Enable nested and hardware stack */ +/* Enable interrupt nesting and hardware stack */ li t0, 0x3 csrw 0x804, t0 - - /* Enable interrupt */ +/* Enable global interrupt and configure privileged mode */ li t0, 0x88 - csrs mstatus, t0 - + csrw mstatus, t0 +/* Configure the interrupt vector table recognition mode and entry address mode */ la t0, _vector_base ori t0, t0, 3 csrw mtvec, t0 - - la a0, __libc_fini_array - call atexit - call __libc_init_array jal SystemInit la t0, main diff --git a/system/CH32V20x/SRC/Startup/startup_ch32v20x_D8W.S b/system/CH32V20x/SRC/Startup/startup_ch32v20x_D8W.S index f1a7610..8c63101 100644 --- a/system/CH32V20x/SRC/Startup/startup_ch32v20x_D8W.S +++ b/system/CH32V20x/SRC/Startup/startup_ch32v20x_D8W.S @@ -1,8 +1,8 @@ ;/********************************** (C) COPYRIGHT ******************************* ;* File Name : startup_ch32v20x_D8W.s ;* Author : WCH -;* Version : V1.0.0 -;* Date : 2021/06/06 +;* Version : V1.0.1 +;* Date : 2023/11/11 ;* Description : CH32V208x ;* vector table for eclipse toolchain. ;********************************************************************************* @@ -16,19 +16,7 @@ .align 1 _start: j handle_reset - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00100073 + .section .vector,"ax",@progbits .align 1 _vector_base: @@ -93,8 +81,8 @@ _vector_base: .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ - .word USBHD_IRQHandler /* USBHD Break */ - .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ + .word USBFS_IRQHandler /* USBFS Break */ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ .word ETH_IRQHandler /* ETH global */ .word ETHWakeUp_IRQHandler /* ETH Wake up */ .word BB_IRQHandler /* BLE BB */ @@ -106,7 +94,6 @@ _vector_base: .word OSCWakeUp_IRQHandler /* OSC Wake Up */ .option rvc; - .section .text.vector_handler, "ax", @progbits .weak NMI_Handler /* NMI */ .weak HardFault_Handler /* Hard Fault */ @@ -158,8 +145,8 @@ _vector_base: .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ - .weak USBHD_IRQHandler /* USBHD */ - .weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */ + .weak USBFS_IRQHandler /* USBFS */ + .weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */ .weak ETH_IRQHandler /* ETH global */ .weak ETHWakeUp_IRQHandler /* ETHWakeUp */ .weak BB_IRQHandler /* BLE BB */ @@ -170,67 +157,69 @@ _vector_base: .weak OSC32KCal_IRQHandler /* OSC32 KCal */ .weak OSCWakeUp_IRQHandler /* OSC Wake Up */ -NMI_Handler: 1: j 1b -HardFault_Handler: 1: j 1b -Ecall_M_Mode_Handler: 1: j 1b -Ecall_U_Mode_Handler: 1: j 1b -Break_Point_Handler: 1: j 1b -SysTick_Handler: 1: j 1b -SW_Handler: 1: j 1b -WWDG_IRQHandler: 1: j 1b -PVD_IRQHandler: 1: j 1b -TAMPER_IRQHandler: 1: j 1b -RTC_IRQHandler: 1: j 1b -FLASH_IRQHandler: 1: j 1b -RCC_IRQHandler: 1: j 1b -EXTI0_IRQHandler: 1: j 1b -EXTI1_IRQHandler: 1: j 1b -EXTI2_IRQHandler: 1: j 1b -EXTI3_IRQHandler: 1: j 1b -EXTI4_IRQHandler: 1: j 1b -DMA1_Channel1_IRQHandler: 1: j 1b -DMA1_Channel2_IRQHandler: 1: j 1b -DMA1_Channel3_IRQHandler: 1: j 1b -DMA1_Channel4_IRQHandler: 1: j 1b -DMA1_Channel5_IRQHandler: 1: j 1b -DMA1_Channel6_IRQHandler: 1: j 1b -DMA1_Channel7_IRQHandler: 1: j 1b -ADC1_2_IRQHandler: 1: j 1b -USB_HP_CAN1_TX_IRQHandler: 1: j 1b -USB_LP_CAN1_RX0_IRQHandler: 1: j 1b -CAN1_RX1_IRQHandler: 1: j 1b -CAN1_SCE_IRQHandler: 1: j 1b -EXTI9_5_IRQHandler: 1: j 1b -TIM1_BRK_IRQHandler: 1: j 1b -TIM1_UP_IRQHandler: 1: j 1b -TIM1_TRG_COM_IRQHandler: 1: j 1b -TIM1_CC_IRQHandler: 1: j 1b -TIM2_IRQHandler: 1: j 1b -TIM3_IRQHandler: 1: j 1b -TIM4_IRQHandler: 1: j 1b -I2C1_EV_IRQHandler: 1: j 1b -I2C1_ER_IRQHandler: 1: j 1b -I2C2_EV_IRQHandler: 1: j 1b -I2C2_ER_IRQHandler: 1: j 1b -SPI1_IRQHandler: 1: j 1b -SPI2_IRQHandler: 1: j 1b -USART1_IRQHandler: 1: j 1b -USART2_IRQHandler: 1: j 1b -USART3_IRQHandler: 1: j 1b -EXTI15_10_IRQHandler: 1: j 1b -RTCAlarm_IRQHandler: 1: j 1b -USBWakeUp_IRQHandler: 1: j 1b -USBHD_IRQHandler: 1: j 1b -USBHDWakeUp_IRQHandler: 1: j 1b -ETH_IRQHandler: 1: j 1b -ETHWakeUp_IRQHandler: 1: j 1b -BB_IRQHandler: 1: j 1b -LLE_IRQHandler: 1: j 1b -TIM5_IRQHandler: 1: j 1b -UART4_IRQHandler: 1: j 1b -DMA1_Channel8_IRQHandler: 1: j 1b -OSC32KCal_IRQHandler: 1: j 1b -OSCWakeUp_IRQHandler: 1: j 1b +NMI_Handler: +HardFault_Handler: +Ecall_M_Mode_Handler: +Ecall_U_Mode_Handler: +Break_Point_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +TAMPER_IRQHandler: +RTC_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI0_IRQHandler: +EXTI1_IRQHandler: +EXTI2_IRQHandler: +EXTI3_IRQHandler: +EXTI4_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_2_IRQHandler: +USB_HP_CAN1_TX_IRQHandler: +USB_LP_CAN1_RX0_IRQHandler: +CAN1_RX1_IRQHandler: +CAN1_SCE_IRQHandler: +EXTI9_5_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +TIM3_IRQHandler: +TIM4_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +I2C2_EV_IRQHandler: +I2C2_ER_IRQHandler: +SPI1_IRQHandler: +SPI2_IRQHandler: +USART1_IRQHandler: +USART2_IRQHandler: +USART3_IRQHandler: +EXTI15_10_IRQHandler: +RTCAlarm_IRQHandler: +USBWakeUp_IRQHandler: +USBFS_IRQHandler: +USBFSWakeUp_IRQHandler: +ETH_IRQHandler: +ETHWakeUp_IRQHandler: +BB_IRQHandler: +LLE_IRQHandler: +TIM5_IRQHandler: +UART4_IRQHandler: +DMA1_Channel8_IRQHandler: +OSC32KCal_IRQHandler: +OSCWakeUp_IRQHandler: +1: + j 1b .section .text.handle_reset,"ax",@progbits .weak handle_reset @@ -243,7 +232,7 @@ handle_reset: 1: la sp, _eusrstack 2: - /* Load data section from flash to RAM */ +/* Load data section from flash to RAM */ la a0, _data_lma la a1, _data_vma la a2, _edata @@ -255,7 +244,7 @@ handle_reset: addi a1, a1, 4 bltu a1, a2, 1b 2: - /* Clear bss section */ +/* Clear bss section */ la a0, _sbss la a1, _ebss bgeu a0, a1, 2f @@ -264,25 +253,20 @@ handle_reset: addi a0, a0, 4 bltu a0, a1, 1b 2: +/* Configure pipelining and instruction prediction */ li t0, 0x1f csrw 0xbc0, t0 - - /* Enable nested and hardware stack */ +/* Enable interrupt nesting and hardware stack */ li t0, 0x3 csrw 0x804, t0 - - /* Enable interrupt */ +/* Enable global interrupt and configure privileged mode */ li t0, 0x88 - csrs mstatus, t0 - + csrw mstatus, t0 +/* Configure the interrupt vector table recognition mode and entry address mode */ la t0, _vector_base ori t0, t0, 3 csrw mtvec, t0 - la a0, __libc_fini_array - call atexit - call __libc_init_array - jal SystemInit la t0, main csrw mepc, t0 diff --git a/system/CH32V20x/USER/ch32v20x_conf.h b/system/CH32V20x/USER/ch32v20x_conf.h index 05dffe6..dfd5e64 100644 --- a/system/CH32V20x/USER/ch32v20x_conf.h +++ b/system/CH32V20x/USER/ch32v20x_conf.h @@ -1,47 +1,42 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_conf.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : Library configuration file. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __CH32V20x_CONF_H -#define __CH32V20x_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v20x_adc.h" -#include "ch32v20x_bkp.h" -#include "ch32v20x_can.h" -#include "ch32v20x_crc.h" -#include "ch32v20x_dbgmcu.h" -#include "ch32v20x_dma.h" -#include "ch32v20x_exti.h" -#include "ch32v20x_flash.h" -#include "ch32v20x_gpio.h" -#include "ch32v20x_i2c.h" -#include "ch32v20x_iwdg.h" -#include "ch32v20x_pwr.h" -#include "ch32v20x_rcc.h" -#include "ch32v20x_rtc.h" -#include "ch32v20x_spi.h" -#include "ch32v20x_tim.h" -#include "ch32v20x_usart.h" -#include "ch32v20x_wwdg.h" -#include "ch32v20x_it.h" -#include "ch32v20x_misc.h" - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V20x_CONF_H */ - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : Library configuration file. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_CONF_H +#define __CH32V20x_CONF_H + +#include "ch32v20x_adc.h" +#include "ch32v20x_bkp.h" +#include "ch32v20x_can.h" +#include "ch32v20x_crc.h" +#include "ch32v20x_dbgmcu.h" +#include "ch32v20x_dma.h" +#include "ch32v20x_exti.h" +#include "ch32v20x_flash.h" +#include "ch32v20x_gpio.h" +#include "ch32v20x_i2c.h" +#include "ch32v20x_iwdg.h" +#include "ch32v20x_pwr.h" +#include "ch32v20x_rcc.h" +#include "ch32v20x_rtc.h" +#include "ch32v20x_spi.h" +#include "ch32v20x_tim.h" +#include "ch32v20x_usart.h" +#include "ch32v20x_wwdg.h" +#include "ch32v20x_it.h" +#include "ch32v20x_misc.h" + + +#endif /* __CH32V20x_CONF_H */ + + + + + diff --git a/system/CH32V20x/USER/ch32v20x_it.c b/system/CH32V20x/USER/ch32v20x_it.c index d5ad6f2..44aaf8f 100644 --- a/system/CH32V20x/USER/ch32v20x_it.c +++ b/system/CH32V20x/USER/ch32v20x_it.c @@ -1,75 +1,46 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v20x_it.c - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : Main Interrupt Service Routines. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#include "ch32v20x_it.h" - -void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void Ecall_U_Mode_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void Ecall_M_Mode_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); - -/********************************************************************* - * @fn NMI_Handler - * - * @brief This function handles NMI exception. - * - * @return none - */ -void NMI_Handler(void) -{ -} - -/********************************************************************* - * @fn HardFault_Handler - * - * @brief This function handles Hard Fault exception. - * - * @return none - */ -void HardFault_Handler(void) -{ - while (1) - { - - } -} - - -/********************************************************************* - * @fn Ecall_U_Mode_Handler - * - * @brief This function handles user mode ecall exception. - * - * @return none - */ -void Ecall_U_Mode_Handler(void) -{ - while(1) - { - - } -} - -/********************************************************************* - * @fn Ecall_M_Mode_Handler - * - * @brief This function handles mashine mode ecall exception. - * - * @return none - */ -void Ecall_M_Mode_Handler(void) -{ - while(1) - { - - } -} - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_it.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/29 + * Description : Main Interrupt Service Routines. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_it.h" + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ + while (1) + { + } +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + NVIC_SystemReset(); + while (1) + { + } +} + + diff --git a/system/CH32V20x/USER/ch32v20x_it.h b/system/CH32V20x/USER/ch32v20x_it.h index 73094c1..f68b203 100644 --- a/system/CH32V20x/USER/ch32v20x_it.h +++ b/system/CH32V20x/USER/ch32v20x_it.h @@ -4,25 +4,17 @@ * Version : V1.0.0 * Date : 2021/06/06 * Description : This file contains the headers of the interrupt handlers. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ #ifndef __CH32V20x_IT_H #define __CH32V20x_IT_H -#ifdef __cplusplus - extern "C" { -#endif - #include "debug.h" - -#ifdef __cplusplus -} -#endif - - #endif /* __CH32V20x_IT_H */ diff --git a/system/CH32V20x/USER/system_ch32v20x.c b/system/CH32V20x/USER/system_ch32v20x.c index 749d6ea..d115b23 100644 --- a/system/CH32V20x/USER/system_ch32v20x.c +++ b/system/CH32V20x/USER/system_ch32v20x.c @@ -6,9 +6,11 @@ * Description : CH32V20x Device Peripheral Access Layer System Source File. * For HSE = 32Mhz (CH32V208x/CH32V203RBT6) * For HSE = 8Mhz (other CH32V203x) - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *********************************************************************************/ +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ #include "ch32v20x.h" /* @@ -29,7 +31,7 @@ //#define SYSCLK_FREQ_72MHz_HSI 72000000 //#define SYSCLK_FREQ_96MHz_HSI 96000000 //#define SYSCLK_FREQ_120MHz_HSI 120000000 -// #define SYSCLK_FREQ_144MHz_HSI 144000000 +//#define SYSCLK_FREQ_144MHz_HSI 144000000 /* Clock Definitions */ #ifdef SYSCLK_FREQ_HSE @@ -109,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } @@ -157,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } @@ -203,6 +205,7 @@ void SystemCoreClockUpdate (void) */ static void SetSysClock(void) { + //GPIO_IPD_Unused(); #ifdef SYSCLK_FREQ_HSE SetSysClockToHSE(); #elif defined SYSCLK_FREQ_48MHz_HSE @@ -279,7 +282,11 @@ static void SetSysClockToHSE(void) /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; - /* Select HSE as system clock source */ + /* Select HSE as system clock source + * CH32V20x_D6 (HSE=8MHz) + * CH32V20x_D8 (HSE=32MHz) + * CH32V20x_D8W (HSE=32MHz) + */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; @@ -336,7 +343,10 @@ static void SetSysClockTo48_HSE(void) /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHz) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHz) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHz) + */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); @@ -404,7 +414,10 @@ static void SetSysClockTo56_HSE(void) /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHz) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHz) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHz) + */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); @@ -473,7 +486,10 @@ static void SetSysClockTo72_HSE(void) /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHz) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHz) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHz) + */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); @@ -543,7 +559,10 @@ static void SetSysClockTo96_HSE(void) /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */ + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHz) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHz) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHz) + */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); @@ -619,7 +638,10 @@ static void SetSysClockTo120_HSE(void) /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */ + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHz) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHz) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHz) + */ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); @@ -687,7 +709,10 @@ static void SetSysClockTo144_HSE(void) /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHz) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHz) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHz) + */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); diff --git a/system/CH32V20x/USER/system_ch32v20x.h b/system/CH32V20x/USER/system_ch32v20x.h index 1020832..8475e44 100644 --- a/system/CH32V20x/USER/system_ch32v20x.h +++ b/system/CH32V20x/USER/system_ch32v20x.h @@ -1,30 +1,32 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : system_ch32v20x.h - * Author : WCH - * Version : V1.0.0 - * Date : 2021/06/06 - * Description : CH32V20x Device Peripheral Access Layer System Header File. - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *******************************************************************************/ -#ifndef __SYSTEM_ch32v20x_H -#define __SYSTEM_ch32v20x_H - -#ifdef __cplusplus - extern "C" { -#endif - -extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ - -/* System_Exported_Functions */ -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V20x_SYSTEM_H */ - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v20x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : CH32V20x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_ch32v20x_H +#define __SYSTEM_ch32v20x_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V20x_SYSTEM_H */ + + + diff --git a/system/CH32V30x/SRC/Core/core_riscv.c b/system/CH32V30x/SRC/Core/core_riscv.c index 0622a8b..592ce3b 100644 --- a/system/CH32V30x/SRC/Core/core_riscv.c +++ b/system/CH32V30x/SRC/Core/core_riscv.c @@ -1,392 +1,392 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : core_riscv.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : RISC-V Core Peripheral Access Layer Source File -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/********************************************************************* - * @fn __get_FFLAGS - * - * @brief Return the Floating-Point Accrued Exceptions - * - * @return fflags value - */ -uint32_t __get_FFLAGS(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "fflags" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_FFLAGS - * - * @brief Set the Floating-Point Accrued Exceptions - * - * @param value - set FFLAGS value - * - * @return none - */ -void __set_FFLAGS(uint32_t value) -{ - __ASM volatile ("csrw fflags, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_FRM - * - * @brief Return the Floating-Point Dynamic Rounding Mode - * - * @return frm value - */ -uint32_t __get_FRM(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "frm" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_FRM - * - * @brief Set the Floating-Point Dynamic Rounding Mode - * - * @param value - set frm value - * - * @return none - */ -void __set_FRM(uint32_t value) -{ - __ASM volatile ("csrw frm, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_FCSR - * - * @brief Return the Floating-Point Control and Status Register - * - * @return fcsr value - */ -uint32_t __get_FCSR(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "fcsr" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_FCSR - * - * @brief Set the Floating-Point Dynamic Rounding Mode - * - * @param value - set fcsr value - * - * @return none - */ -void __set_FCSR(uint32_t value) -{ - __ASM volatile ("csrw fcsr, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MSTATUS - * - * @brief Return the Machine Status Register - * - * @return mstatus value - */ -uint32_t __get_MSTATUS(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MSTATUS - * - * @brief Set the Machine Status Register - * - * @param value - set mstatus value - * - * @return none - */ -void __set_MSTATUS(uint32_t value) -{ - __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MISA - * - * @brief Return the Machine ISA Register - * - * @return misa value - */ -uint32_t __get_MISA(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MISA - * - * @brief Set the Machine ISA Register - * - * @param value - set misa value - * - * @return none - */ -void __set_MISA(uint32_t value) -{ - __ASM volatile ("csrw misa, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MTVEC - * - * @brief Return the Machine Trap-Vector Base-Address Register - * - * @return mtvec value - */ -uint32_t __get_MTVEC(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MTVEC - * - * @brief Set the Machine Trap-Vector Base-Address Register - * - * @param value - set mtvec value - * - * @return none - */ -void __set_MTVEC(uint32_t value) -{ - __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MSCRATCH - * - * @brief Return the Machine Seratch Register - * - * @return mscratch value - */ -uint32_t __get_MSCRATCH(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MSCRATCH - * - * @brief Set the Machine Seratch Register - * - * @param value - set mscratch value - * - * @return none - */ -void __set_MSCRATCH(uint32_t value) -{ - __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MEPC - * - * @brief Return the Machine Exception Program Register - * - * @return mepc value - */ -uint32_t __get_MEPC(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Exception Program Register - * - * @return mepc value - */ -void __set_MEPC(uint32_t value) -{ - __ASM volatile ("csrw mepc, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MCAUSE - * - * @brief Return the Machine Cause Register - * - * @return mcause value - */ -uint32_t __get_MCAUSE(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Cause Register - * - * @return mcause value - */ -void __set_MCAUSE(uint32_t value) -{ - __ASM volatile ("csrw mcause, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MTVAL - * - * @brief Return the Machine Trap Value Register - * - * @return mtval value - */ -uint32_t __get_MTVAL(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MTVAL - * - * @brief Set the Machine Trap Value Register - * - * @return mtval value - */ -void __set_MTVAL(uint32_t value) -{ - __ASM volatile ("csrw mtval, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MVENDORID - * - * @brief Return Vendor ID Register - * - * @return mvendorid value - */ -uint32_t __get_MVENDORID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_MARCHID - * - * @brief Return Machine Architecture ID Register - * - * @return marchid value - */ -uint32_t __get_MARCHID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_MIMPID - * - * @brief Return Machine Implementation ID Register - * - * @return mimpid value - */ -uint32_t __get_MIMPID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_MHARTID - * - * @brief Return Hart ID Register - * - * @return mhartid value - */ -uint32_t __get_MHARTID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_SP - * - * @brief Return SP Register - * - * @return SP value - */ -uint32_t __get_SP(void) -{ - uint32_t result; - - __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); - return (result); -} - +/********************************** (C) COPYRIGHT ******************************* +* File Name : core_riscv.c +* Author : WCH +* Version : V1.0.1 +* Date : 2023/11/11 +* Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32V30x +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/********************************************************************* + * @fn __get_FFLAGS + * + * @brief Return the Floating-Point Accrued Exceptions + * + * @return fflags value + */ +uint32_t __get_FFLAGS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "fflags" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_FFLAGS + * + * @brief Set the Floating-Point Accrued Exceptions + * + * @param value - set FFLAGS value + * + * @return none + */ +void __set_FFLAGS(uint32_t value) +{ + __ASM volatile ("csrw fflags, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_FRM + * + * @brief Return the Floating-Point Dynamic Rounding Mode + * + * @return frm value + */ +uint32_t __get_FRM(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "frm" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_FRM + * + * @brief Set the Floating-Point Dynamic Rounding Mode + * + * @param value - set frm value + * + * @return none + */ +void __set_FRM(uint32_t value) +{ + __ASM volatile ("csrw frm, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_FCSR + * + * @brief Return the Floating-Point Control and Status Register + * + * @return fcsr value + */ +uint32_t __get_FCSR(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "fcsr" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_FCSR + * + * @brief Set the Floating-Point Dynamic Rounding Mode + * + * @param value - set fcsr value + * + * @return none + */ +void __set_FCSR(uint32_t value) +{ + __ASM volatile ("csrw fcsr, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile ("csrw misa, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile ("csrw mepc, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile ("csrw mcause, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile ("csrw mtval, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); + return (result); +} + diff --git a/system/CH32V30x/SRC/Core/core_riscv.h b/system/CH32V30x/SRC/Core/core_riscv.h index e69d1fe..bc68298 100644 --- a/system/CH32V30x/SRC/Core/core_riscv.h +++ b/system/CH32V30x/SRC/Core/core_riscv.h @@ -1,582 +1,597 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : core_riscv.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : RISC-V Core Peripheral Access Layer Header File for CH32V30x -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CORE_RISCV_H__ -#define __CORE_RISCV_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* IO definitions */ -#ifdef __cplusplus - #define __I volatile /* defines 'read only' permissions */ -#else - #define __I volatile const /* defines 'read only' permissions */ -#endif -#define __O volatile /* defines 'write only' permissions */ -#define __IO volatile /* defines 'read / write' permissions */ - -/* Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef __I uint64_t vuc64; /* Read Only */ -typedef __I uint32_t vuc32; /* Read Only */ -typedef __I uint16_t vuc16; /* Read Only */ -typedef __I uint8_t vuc8; /* Read Only */ - -typedef const uint64_t uc64; /* Read Only */ -typedef const uint32_t uc32; /* Read Only */ -typedef const uint16_t uc16; /* Read Only */ -typedef const uint8_t uc8; /* Read Only */ - -typedef __I int64_t vsc64; /* Read Only */ -typedef __I int32_t vsc32; /* Read Only */ -typedef __I int16_t vsc16; /* Read Only */ -typedef __I int8_t vsc8; /* Read Only */ - -typedef const int64_t sc64; /* Read Only */ -typedef const int32_t sc32; /* Read Only */ -typedef const int16_t sc16; /* Read Only */ -typedef const int8_t sc8; /* Read Only */ - -typedef __IO uint64_t vu64; -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef uint64_t u64; -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef __IO int64_t vs64; -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef int64_t s64; -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -#define RV_STATIC_INLINE static inline - -/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ -typedef struct{ - __I uint32_t ISR[8]; - __I uint32_t IPR[8]; - __IO uint32_t ITHRESDR; - __IO uint32_t RESERVED; - __IO uint32_t CFGR; - __I uint32_t GISR; - __IO uint8_t VTFIDR[4]; - uint8_t RESERVED0[12]; - __IO uint32_t VTFADDR[4]; - uint8_t RESERVED1[0x90]; - __O uint32_t IENR[8]; - uint8_t RESERVED2[0x60]; - __O uint32_t IRER[8]; - uint8_t RESERVED3[0x60]; - __O uint32_t IPSR[8]; - uint8_t RESERVED4[0x60]; - __O uint32_t IPRR[8]; - uint8_t RESERVED5[0x60]; - __IO uint32_t IACTR[8]; - uint8_t RESERVED6[0xE0]; - __IO uint8_t IPRIOR[256]; - uint8_t RESERVED7[0x810]; - __IO uint32_t SCTLR; -}PFIC_Type; - -/* memory mapped structure for SysTick */ -typedef struct -{ - __IO u32 CTLR; - __IO u32 SR; - __IO u64 CNT; - __IO u64 CMP; -}SysTick_Type; - - -#define PFIC ((PFIC_Type *) 0xE000E000 ) -#define NVIC PFIC -#define NVIC_KEY1 ((uint32_t)0xFA050000) -#define NVIC_KEY2 ((uint32_t)0xBCAF0000) -#define NVIC_KEY3 ((uint32_t)0xBEEF0000) - -#define SysTick ((SysTick_Type *) 0xE000F000) - -/********************************************************************* - * @fn __enable_irq - * - * @brief Enable Global Interrupt - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() -{ - __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) ); -} - -/********************************************************************* - * @fn __disable_irq - * - * @brief Disable Global Interrupt - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() -{ - __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) ); -} - -/********************************************************************* - * @fn __NOP - * - * @brief nop - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() -{ - __asm volatile ("nop"); -} - -/********************************************************************* - * @fn NVIC_EnableIRQ - * - * @brief Enable Interrupt - * - * @param IRQn: Interrupt Numbers - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_DisableIRQ - * - * @brief Disable Interrupt - * - * @param IRQn: Interrupt Numbers - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_GetStatusIRQ - * - * @brief Get Interrupt Enable State - * - * @param IRQn: Interrupt Numbers - * - * @return 1 - Interrupt Enable - * 0 - Interrupt Disable - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_GetPendingIRQ - * - * @brief Get Interrupt Pending State - * - * @param IRQn: Interrupt Numbers - * - * @return 1 - Interrupt Pending Enable - * 0 - Interrupt Pending Disable - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_SetPendingIRQ - * - * @brief Set Interrupt Pending - * - * @param IRQn: Interrupt Numbers - * - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_ClearPendingIRQ - * - * @brief Clear Interrupt Pending - * - * @param IRQn: Interrupt Numbers - * - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_GetActive - * - * @brief Get Interrupt Active State - * - * @param IRQn: Interrupt Numbers - * - * @return 1 - Interrupt Active - * 0 - Interrupt No Active - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_SetPriority - * - * @brief Set Interrupt Priority - * - * @param IRQn - Interrupt Numbers - * priority - - * bit[7] - pre-emption priority - * bit[6:5] - subpriority - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) -{ - NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; -} - -/********************************************************************* - * @fn __WFI - * - * @brief Wait for Interrupt - * - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) -{ - NVIC->SCTLR &= ~(1<<3); // wfi - asm volatile ("wfi"); -} - -/********************************************************************* - * @fn _SEV - * - * @brief Set Event - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) -{ - uint32_t t; - - t = NVIC->SCTLR; - NVIC->SCTLR |= (1<<3)|(1<<5); - NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); -} - -/********************************************************************* - * @fn _WFE - * - * @brief Wait for Events - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) -{ - NVIC->SCTLR |= (1<<3); - asm volatile ("wfi"); -} - -/********************************************************************* - * @fn __WFE - * - * @brief Wait for Events - * - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) -{ - _SEV(); - _WFE(); - _WFE(); -} - -/********************************************************************* - * @fn SetVTFIRQ - * - * @brief Set VTF Interrupt - * - * @param add - VTF interrupt service function base address. - * IRQn -Interrupt Numbers - * num - VTF Interrupt Numbers - * NewState - DISABLE or ENABLE - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ - if(num > 3) return ; - - if (NewState != DISABLE) - { - NVIC->VTFIDR[num] = IRQn; - NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); - } - else{ - NVIC->VTFIDR[num] = IRQn; - NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); - } -} - -/********************************************************************* - * @fn NVIC_SystemReset - * - * @brief Initiate a system reset request - * - * @return None - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) -{ - NVIC->CFGR = NVIC_KEY3|(1<<7); -} - -/********************************************************************* - * @fn __AMOADD_W - * - * @brief Atomic Add with 32bit value - * Atomically ADD 32bit value with value in memory using amoadd.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be ADDed - * - * @return return memory value + add value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amoadd.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOAND_W - * - * @brief Atomic And with 32bit value - * Atomically AND 32bit value with value in memory using amoand.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be ANDed - * - * @return return memory value & and value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amoand.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOMAX_W - * - * @brief Atomic signed MAX with 32bit value - * Atomically signed max compare 32bit value with value in memory using amomax.d. - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared - * - * @return return the bigger value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amomax.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOMAXU_W - * - * @brief Atomic unsigned MAX with 32bit value - * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared - * - * @return return the bigger value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) -{ - uint32_t result; - - __asm volatile ("amomaxu.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOMIN_W - * - * @brief Atomic signed MIN with 32bit value - * Atomically signed min compare 32bit value with value in memory using amomin.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared - * - * @return return the smaller value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amomin.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOMINU_W - * - * @brief Atomic unsigned MIN with 32bit value - * Atomically unsigned min compare 32bit value with value in memory using amominu.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared - * - * @return return the smaller value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) -{ - uint32_t result; - - __asm volatile ("amominu.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOOR_W - * - * @brief Atomic OR with 32bit value - * Atomically OR 32bit value with value in memory using amoor.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be ORed - * - * @return return memory value | and value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amoor.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOSWAP_W - * - * @brief Atomically swap new 32bit value into memory using amoswap.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * newval - New value to be stored into the address - * - * @return return the original value in memory - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) -{ - uint32_t result; - - __asm volatile ("amoswap.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); - return result; -} - -/********************************************************************* - * @fn __AMOXOR_W - * - * @brief Atomic XOR with 32bit value - * Atomically XOR 32bit value with value in memory using amoxor.d. - * - * @param addr - Address pointer to data, address need to be 4byte aligned - * value - value to be XORed - * - * @return return memory value ^ and value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amoxor.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/* Core_Exported_Functions */ -extern uint32_t __get_FFLAGS(void); -extern void __set_FFLAGS(uint32_t value); -extern uint32_t __get_FRM(void); -extern void __set_FRM(uint32_t value); -extern uint32_t __get_FCSR(void); -extern void __set_FCSR(uint32_t value); -extern uint32_t __get_MSTATUS(void); -extern void __set_MSTATUS(uint32_t value); -extern uint32_t __get_MISA(void); -extern void __set_MISA(uint32_t value); -extern uint32_t __get_MTVEC(void); -extern void __set_MTVEC(uint32_t value); -extern uint32_t __get_MSCRATCH(void); -extern void __set_MSCRATCH(uint32_t value); -extern uint32_t __get_MEPC(void); -extern void __set_MEPC(uint32_t value); -extern uint32_t __get_MCAUSE(void); -extern void __set_MCAUSE(uint32_t value); -extern uint32_t __get_MTVAL(void); -extern void __set_MTVAL(uint32_t value); -extern uint32_t __get_MVENDORID(void); -extern uint32_t __get_MARCHID(void); -extern uint32_t __get_MIMPID(void); -extern uint32_t __get_MHARTID(void); -extern uint32_t __get_SP(void); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : core_riscv.h +* Author : WCH +* Version : V1.0.1 +* Date : 2024/03/06 +* Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32V30x +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint64_t vuc64; /* Read Only */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint64_t uc64; /* Read Only */ +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int64_t vsc64; /* Read Only */ +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int64_t sc64; /* Read Only */ +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint64_t vu64; +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int64_t vs64; +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int64_t s64; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + __IO uint64_t CMP; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000 ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + +#define SysTick ((SysTick_Type *) 0xE000F000) + +/********************************************************************* + * @fn __enable_irq + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrs 0x800, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __disable_irq + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrc 0x800, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Enable + * 0 - Interrupt Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) + * priority - bit[7:5] - Preemption Priority + * bit[4:0] - Reserve + * interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) + * priority - bit[7:6] - Preemption Priority + * bit[5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + uint32_t t; + + t = NVIC->SCTLR; + NVIC->SCTLR |= (1<<3)|(1<<5); + NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + NVIC->SCTLR |= (1<<3); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param add - VTF interrupt service function base address. + * IRQn -Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState) +{ + if(num > 3) return ; + + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + +/********************************************************************* + * @fn __AMOADD_W + * + * @brief Atomic Add with 32bit value + * Atomically ADD 32bit value with value in memory using amoadd.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ADDed + * + * @return return memory value + add value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoadd.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOAND_W + * + * @brief Atomic And with 32bit value + * Atomically AND 32bit value with value in memory using amoand.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ANDed + * + * @return return memory value & and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoand.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAX_W + * + * @brief Atomic signed MAX with 32bit value + * Atomically signed max compare 32bit value with value in memory using amomax.d. + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomax.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAXU_W + * + * @brief Atomic unsigned MAX with 32bit value + * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amomaxu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMIN_W + * + * @brief Atomic signed MIN with 32bit value + * Atomically signed min compare 32bit value with value in memory using amomin.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomin.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMINU_W + * + * @brief Atomic unsigned MIN with 32bit value + * Atomically unsigned min compare 32bit value with value in memory using amominu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amominu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOOR_W + * + * @brief Atomic OR with 32bit value + * Atomically OR 32bit value with value in memory using amoor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ORed + * + * @return return memory value | and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOSWAP_W + * + * @brief Atomically swap new 32bit value into memory using amoswap.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * newval - New value to be stored into the address + * + * @return return the original value in memory + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) +{ + uint32_t result; + + __asm volatile ("amoswap.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); + return result; +} + +/********************************************************************* + * @fn __AMOXOR_W + * + * @brief Atomic XOR with 32bit value + * Atomically XOR 32bit value with value in memory using amoxor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be XORed + * + * @return return memory value ^ and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoxor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/* Core_Exported_Functions */ +extern uint32_t __get_FFLAGS(void); +extern void __set_FFLAGS(uint32_t value); +extern uint32_t __get_FRM(void); +extern void __set_FRM(uint32_t value); +extern uint32_t __get_FCSR(void); +extern void __set_FCSR(uint32_t value); +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MTVAL(void); +extern void __set_MTVAL(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/system/CH32V30x/SRC/Debug/debug.c b/system/CH32V30x/SRC/Debug/debug.c index 0abd731..1444fcf 100644 --- a/system/CH32V30x/SRC/Debug/debug.c +++ b/system/CH32V30x/SRC/Debug/debug.c @@ -1,201 +1,256 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : debug.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for UART -* Printf , Delay functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "debug.h" - -static uint8_t p_us = 0; -static uint16_t p_ms = 0; - -/********************************************************************* - * @fn Delay_Init - * - * @brief Initializes Delay Funcation. - * - * @return none - */ -void Delay_Init(void) -{ - p_us = SystemCoreClock / 8000000; - p_ms = (uint16_t)p_us * 1000; -} - -/********************************************************************* - * @fn Delay_Us - * - * @brief Microsecond Delay Time. - * - * @param n - Microsecond number. - * - * @return None - */ -void Delay_Us(uint32_t n) -{ - uint32_t i; - - SysTick->SR &= ~(1 << 0); - i = (uint32_t)n * p_us; - - SysTick->CMP = i; - SysTick->CTLR |= (1 << 4); - SysTick->CTLR |= (1 << 5) | (1 << 0); - - while((SysTick->SR & (1 << 0)) != (1 << 0)) - ; - SysTick->CTLR &= ~(1 << 0); -} - -/********************************************************************* - * @fn Delay_Ms - * - * @brief Millisecond Delay Time. - * - * @param n - Millisecond number. - * - * @return None - */ -void Delay_Ms(uint32_t n) -{ - uint32_t i; - - SysTick->SR &= ~(1 << 0); - i = (uint32_t)n * p_ms; - - SysTick->CMP = i; - SysTick->CTLR |= (1 << 4); - SysTick->CTLR |= (1 << 5) | (1 << 0); - - while((SysTick->SR & (1 << 0)) != (1 << 0)) - ; - SysTick->CTLR &= ~(1 << 0); -} - -/********************************************************************* - * @fn USART_Printf_Init - * - * @brief Initializes the USARTx peripheral. - * - * @param baudrate - USART communication baud rate. - * - * @return None - */ -void USART_Printf_Init(uint32_t baudrate) -{ - GPIO_InitTypeDef GPIO_InitStructure; - USART_InitTypeDef USART_InitStructure; - -#if(DEBUG == DEBUG_UART1) - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - -#elif(DEBUG == DEBUG_UART2) - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - -#elif(DEBUG == DEBUG_UART3) - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOB, &GPIO_InitStructure); - -#endif - - USART_InitStructure.USART_BaudRate = baudrate; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_No; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Tx; - -#if(DEBUG == DEBUG_UART1) - USART_Init(USART1, &USART_InitStructure); - USART_Cmd(USART1, ENABLE); - -#elif(DEBUG == DEBUG_UART2) - USART_Init(USART2, &USART_InitStructure); - USART_Cmd(USART2, ENABLE); - -#elif(DEBUG == DEBUG_UART3) - USART_Init(USART3, &USART_InitStructure); - USART_Cmd(USART3, ENABLE); - -#endif -} - -/********************************************************************* - * @fn _write - * - * @brief Support Printf Function - * - * @param *buf - UART send Data. - * size - Data length - * - * @return size: Data length - */ - -#if 1 -__attribute__((used)) int _write(int fd, char *buf, int size) -{ - int i; - - for(i = 0; i < size; i++) - { -#if(DEBUG == DEBUG_UART1) - while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); - USART_SendData(USART1, *buf++); -#elif(DEBUG == DEBUG_UART2) - while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); - USART_SendData(USART2, *buf++); -#elif(DEBUG == DEBUG_UART3) - while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); - USART_SendData(USART3, *buf++); -#endif - } - - return size; -} -#endif - -/********************************************************************* - * @fn _sbrk - * - * @brief Change the spatial position of data segment. - * - * @return size: Data length - */ -__attribute__((used)) void *_sbrk(ptrdiff_t incr) -{ - extern char _end[]; - extern char _heap_end[]; - static char *curbrk = _end; - - if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) - return NULL - 1; - - curbrk += incr; - return curbrk - incr; -} - -void _fini() {} -void _init() {} - +/********************************** (C) COPYRIGHT ******************************* +* File Name : debug.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for UART +* Printf , Delay functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "debug.h" + +static uint8_t p_us = 0; +static uint16_t p_ms = 0; + +#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE0000380) +#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE0000384) + +/********************************************************************* + * @fn Delay_Init + * + * @brief Initializes Delay Funcation. + * + * @return none + */ +void Delay_Init(void) +{ + p_us = SystemCoreClock / 8000000; + p_ms = (uint16_t)p_us * 1000; +} + +/********************************************************************* + * @fn Delay_Us + * + * @brief Microsecond Delay Time. + * + * @param n - Microsecond number. + * + * @return None + */ +void Delay_Us(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_us; + + SysTick->CMP = i; + SysTick->CTLR |= (1 << 4); + SysTick->CTLR |= (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)) + ; + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn Delay_Ms + * + * @brief Millisecond Delay Time. + * + * @param n - Millisecond number. + * + * @return None + */ +void Delay_Ms(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_ms; + + SysTick->CMP = i; + SysTick->CTLR |= (1 << 4); + SysTick->CTLR |= (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)) + ; + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn USART_Printf_Init + * + * @brief Initializes the USARTx peripheral. + * + * @param baudrate - USART communication baud rate. + * + * @return None + */ +void USART_Printf_Init(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + +#if(DEBUG == DEBUG_UART1) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART2) + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART3) + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + +#endif + + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx; + +#if(DEBUG == DEBUG_UART1) + USART_Init(USART1, &USART_InitStructure); + USART_Cmd(USART1, ENABLE); + +#elif(DEBUG == DEBUG_UART2) + USART_Init(USART2, &USART_InitStructure); + USART_Cmd(USART2, ENABLE); + +#elif(DEBUG == DEBUG_UART3) + USART_Init(USART3, &USART_InitStructure); + USART_Cmd(USART3, ENABLE); + +#endif +} + +/********************************************************************* + * @fn SDI_Printf_Enable + * + * @brief Initializes the SDI printf Function. + * + * @param None + * + * @return None + */ +void SDI_Printf_Enable(void) +{ + *(DEBUG_DATA0_ADDRESS) = 0; + Delay_Init(); + Delay_Ms(1); +} + +/********************************************************************* + * @fn _write + * + * @brief Support Printf Function + * + * @param *buf - UART send Data. + * size - Data length + * + * @return size: Data length + */ +#if 0 +__attribute__((used)) int _write(int fd, char *buf, int size) +{ + int i = 0; + +#if (SDI_PRINT == SDI_PR_OPEN) + int writeSize = size; + + do + { + + /** + * data0 data1 8 bytes + * data0 The lowest byte storage length, the maximum is 7 + * + */ + + while( (*(DEBUG_DATA0_ADDRESS) != 0u)) + { + + } + + if(writeSize>7) + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + i += 7; + writeSize -= 7; + } + else + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + writeSize = 0; + } + + } while (writeSize); + + +#else + for(i = 0; i < size; i++) + { +#if(DEBUG == DEBUG_UART1) + while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); + USART_SendData(USART1, *buf++); +#elif(DEBUG == DEBUG_UART2) + while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); + USART_SendData(USART2, *buf++); +#elif(DEBUG == DEBUG_UART3) + while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); + USART_SendData(USART3, *buf++); +#endif + } +#endif + return size; +} +#endif + +/********************************************************************* + * @fn _sbrk + * + * @brief Change the spatial position of data segment. + * + * @return size: Data length + */ +__attribute__((used)) void *_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} + +void _fini() {} +void _init() {} + diff --git a/system/CH32V30x/SRC/Debug/debug.h b/system/CH32V30x/SRC/Debug/debug.h index 3e0738e..1c60731 100644 --- a/system/CH32V30x/SRC/Debug/debug.h +++ b/system/CH32V30x/SRC/Debug/debug.h @@ -1,46 +1,55 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : debug.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for UART -* Printf , Delay functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __DEBUG_H -#define __DEBUG_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "stdio.h" -#include "ch32v30x.h" - -/* UART Printf Definition */ -#define DEBUG_UART1 1 -#define DEBUG_UART2 2 -#define DEBUG_UART3 3 - -/* DEBUG UATR Definition */ -#ifndef DEBUG -#define DEBUG DEBUG_UART1 -#endif - - -void Delay_Init(void); -void Delay_Us (uint32_t n); -void Delay_Ms (uint32_t n); -void USART_Printf_Init(uint32_t baudrate); - -#ifdef __cplusplus -} -#endif - -#endif - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : debug.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for UART +* Printf , Delay functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __DEBUG_H +#define __DEBUG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stdio.h" +#include "ch32v30x.h" + +/* UART Printf Definition */ +#define DEBUG_UART1 1 +#define DEBUG_UART2 2 +#define DEBUG_UART3 3 + +/* DEBUG UATR Definition */ +#ifndef DEBUG +#define DEBUG DEBUG_UART1 +#endif + +/* SDI Printf Definition */ +#define SDI_PR_CLOSE 0 +#define SDI_PR_OPEN 1 + +#ifndef SDI_PRINT +#define SDI_PRINT SDI_PR_CLOSE +#endif + + +void Delay_Init(void); +void Delay_Us (uint32_t n); +void Delay_Ms (uint32_t n); +void USART_Printf_Init(uint32_t baudrate); +void SDI_Printf_Enable(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x.h index 4f95963..58233c8 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x.h @@ -1,5252 +1,6649 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : CH32V30x Device Peripheral Access Layer Header File. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_H -#define __CH32V30x_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if !defined(CH32V30x_D8) && !defined(CH32V30x_D8C) -//#define CH32V30x_D8 /* CH32V303x */ -#define CH32V30x_D8C /* CH32V307x-CH32V305x */ - -#endif - -#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ - -#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ - -/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x1000) /* Time out for HSE start up */ - -#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ - -/* CH32V30x Standard Peripheral Library version number */ -#define __CH32V30x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */ -#define __CH32V30x_STDPERIPH_VERSION_SUB (0x02) /* [7:0] sub version */ -#define __CH32V30x_STDPERIPH_VERSION ( (__CH32V30x_STDPERIPH_VERSION_MAIN << 8)\ - |(__CH32V30x_STDPERIPH_VERSION_SUB << 0)) - - -/* Interrupt Number Definition, according to the selected device */ -typedef enum IRQn -{ - /****** RISC-V Processor Exceptions Numbers *******************************************************/ - NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ - EXC_IRQn = 3, /* 3 Exception Interrupt */ - Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ - Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ - Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ - SysTicK_IRQn = 12, /* 12 System timer Interrupt */ - Software_IRQn = 14, /* 14 software Interrupt */ - - /****** RISC-V specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 16, /* Window WatchDog Interrupt */ - PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 18, /* Tamper Interrupt */ - RTC_IRQn = 19, /* RTC global Interrupt */ - FLASH_IRQn = 20, /* FLASH global Interrupt */ - RCC_IRQn = 21, /* RCC global Interrupt */ - EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ - EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ - EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ - EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ - EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ - ADC_IRQn = 34, /* ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ - TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 44, /* TIM2 global Interrupt */ - TIM3_IRQn = 45, /* TIM3 global Interrupt */ - TIM4_IRQn = 46, /* TIM4 global Interrupt */ - I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ - I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ - I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ - I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ - SPI1_IRQn = 51, /* SPI1 global Interrupt */ - SPI2_IRQn = 52, /* SPI2 global Interrupt */ - USART1_IRQn = 53, /* USART1 global Interrupt */ - USART2_IRQn = 54, /* USART2 global Interrupt */ - USART3_IRQn = 55, /* USART3 global Interrupt */ - EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ - -#ifdef CH32V30x_D8 - TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ - TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */ - RNG_IRQn = 63, /* RNG global Interrupt */ - FSMC_IRQn = 64, /* FSMC global Interrupt */ - SDIO_IRQn = 65, /* SDIO global Interrupt */ - TIM5_IRQn = 66, /* TIM5 global Interrupt */ - SPI3_IRQn = 67, /* SPI3 global Interrupt */ - UART4_IRQn = 68, /* UART4 global Interrupt */ - UART5_IRQn = 69, /* UART5 global Interrupt */ - TIM6_IRQn = 70, /* TIM6 global Interrupt */ - TIM7_IRQn = 71, /* TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */ - OTG_FS_IRQn = 83, /* OTGFS global Interrupt */ - UART6_IRQn = 87, /* UART6 global Interrupt */ - UART7_IRQn = 88, /* UART7 global Interrupt */ - UART8_IRQn = 89, /* UART8 global Interrupt */ - TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */ - TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */ - TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */ - TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */ - TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */ - TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */ - TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */ - TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */ - DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */ - DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */ - DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */ - DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */ - DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */ - DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */ - -#elif defined (CH32V30x_D8C) - USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ - TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */ - RNG_IRQn = 63, /* RNG global Interrupt */ - FSMC_IRQn = 64, /* FSMC global Interrupt */ - SDIO_IRQn = 65, /* SDIO global Interrupt */ - TIM5_IRQn = 66, /* TIM5 global Interrupt */ - SPI3_IRQn = 67, /* SPI3 global Interrupt */ - UART4_IRQn = 68, /* UART4 global Interrupt */ - UART5_IRQn = 69, /* UART5 global Interrupt */ - TIM6_IRQn = 70, /* TIM6 global Interrupt */ - TIM7_IRQn = 71, /* TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */ - ETH_IRQn = 77, /* ETH global Interrupt */ - ETH_WKUP_IRQn = 78, /* ETH WakeUp Interrupt */ - CAN2_TX_IRQn = 79, /* CAN2 TX Interrupts */ - CAN2_RX0_IRQn = 80, /* CAN2 RX0 Interrupts */ - CAN2_RX1_IRQn = 81, /* CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 82, /* CAN2 SCE Interrupt */ - OTG_FS_IRQn = 83, /* OTGFS global Interrupt */ - USBHSWakeup_IRQn = 84, /* USBHS WakeUp Interrupt */ - USBHS_IRQn = 85, /* USBHS global Interrupt */ - DVP_IRQn = 86, /* DVP global Interrupt */ - UART6_IRQn = 87, /* UART6 global Interrupt */ - UART7_IRQn = 88, /* UART7 global Interrupt */ - UART8_IRQn = 89, /* UART8 global Interrupt */ - TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */ - TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */ - TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */ - TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */ - TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */ - TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */ - TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */ - TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */ - DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */ - DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */ - DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */ - DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */ - DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */ - DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */ - -#endif -} IRQn_Type; - -#define HardFault_IRQn EXC_IRQn -#define ADC1_2_IRQn ADC_IRQn - - -#include -#include "core_riscv.h" -#include "system_ch32v30x.h" - - -/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSI_Value HSI_VALUE -#define HSE_Value HSE_VALUE -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT - -/* Analog to Digital Converter */ -typedef struct -{ - __IO uint32_t STATR; - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t SAMPTR1; - __IO uint32_t SAMPTR2; - __IO uint32_t IOFR1; - __IO uint32_t IOFR2; - __IO uint32_t IOFR3; - __IO uint32_t IOFR4; - __IO uint32_t WDHTR; - __IO uint32_t WDLTR; - __IO uint32_t RSQR1; - __IO uint32_t RSQR2; - __IO uint32_t RSQR3; - __IO uint32_t ISQR; - __IO uint32_t IDATAR1; - __IO uint32_t IDATAR2; - __IO uint32_t IDATAR3; - __IO uint32_t IDATAR4; - __IO uint32_t RDATAR; -} ADC_TypeDef; - -/* Backup Registers */ -typedef struct -{ - uint32_t RESERVED0; - __IO uint16_t DATAR1; - uint16_t RESERVED1; - __IO uint16_t DATAR2; - uint16_t RESERVED2; - __IO uint16_t DATAR3; - uint16_t RESERVED3; - __IO uint16_t DATAR4; - uint16_t RESERVED4; - __IO uint16_t DATAR5; - uint16_t RESERVED5; - __IO uint16_t DATAR6; - uint16_t RESERVED6; - __IO uint16_t DATAR7; - uint16_t RESERVED7; - __IO uint16_t DATAR8; - uint16_t RESERVED8; - __IO uint16_t DATAR9; - uint16_t RESERVED9; - __IO uint16_t DATAR10; - uint16_t RESERVED10; - __IO uint16_t OCTLR; - uint16_t RESERVED11; - __IO uint16_t TPCTLR; - uint16_t RESERVED12; - __IO uint16_t TPCSR; - uint16_t RESERVED13[5]; - __IO uint16_t DATAR11; - uint16_t RESERVED14; - __IO uint16_t DATAR12; - uint16_t RESERVED15; - __IO uint16_t DATAR13; - uint16_t RESERVED16; - __IO uint16_t DATAR14; - uint16_t RESERVED17; - __IO uint16_t DATAR15; - uint16_t RESERVED18; - __IO uint16_t DATAR16; - uint16_t RESERVED19; - __IO uint16_t DATAR17; - uint16_t RESERVED20; - __IO uint16_t DATAR18; - uint16_t RESERVED21; - __IO uint16_t DATAR19; - uint16_t RESERVED22; - __IO uint16_t DATAR20; - uint16_t RESERVED23; - __IO uint16_t DATAR21; - uint16_t RESERVED24; - __IO uint16_t DATAR22; - uint16_t RESERVED25; - __IO uint16_t DATAR23; - uint16_t RESERVED26; - __IO uint16_t DATAR24; - uint16_t RESERVED27; - __IO uint16_t DATAR25; - uint16_t RESERVED28; - __IO uint16_t DATAR26; - uint16_t RESERVED29; - __IO uint16_t DATAR27; - uint16_t RESERVED30; - __IO uint16_t DATAR28; - uint16_t RESERVED31; - __IO uint16_t DATAR29; - uint16_t RESERVED32; - __IO uint16_t DATAR30; - uint16_t RESERVED33; - __IO uint16_t DATAR31; - uint16_t RESERVED34; - __IO uint16_t DATAR32; - uint16_t RESERVED35; - __IO uint16_t DATAR33; - uint16_t RESERVED36; - __IO uint16_t DATAR34; - uint16_t RESERVED37; - __IO uint16_t DATAR35; - uint16_t RESERVED38; - __IO uint16_t DATAR36; - uint16_t RESERVED39; - __IO uint16_t DATAR37; - uint16_t RESERVED40; - __IO uint16_t DATAR38; - uint16_t RESERVED41; - __IO uint16_t DATAR39; - uint16_t RESERVED42; - __IO uint16_t DATAR40; - uint16_t RESERVED43; - __IO uint16_t DATAR41; - uint16_t RESERVED44; - __IO uint16_t DATAR42; - uint16_t RESERVED45; -} BKP_TypeDef; - -/* Controller Area Network TxMailBox */ -typedef struct -{ - __IO uint32_t TXMIR; - __IO uint32_t TXMDTR; - __IO uint32_t TXMDLR; - __IO uint32_t TXMDHR; -} CAN_TxMailBox_TypeDef; - -/* Controller Area Network FIFOMailBox */ -typedef struct -{ - __IO uint32_t RXMIR; - __IO uint32_t RXMDTR; - __IO uint32_t RXMDLR; - __IO uint32_t RXMDHR; -} CAN_FIFOMailBox_TypeDef; - -/* Controller Area Network FilterRegister */ -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/* Controller Area Network */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t STATR; - __IO uint32_t TSTATR; - __IO uint32_t RFIFO0; - __IO uint32_t RFIFO1; - __IO uint32_t INTENR; - __IO uint32_t ERRSR; - __IO uint32_t BTIMR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FCTLR; - __IO uint32_t FMCFGR; - uint32_t RESERVED2; - __IO uint32_t FSCFGR; - uint32_t RESERVED3; - __IO uint32_t FAFIFOR; - uint32_t RESERVED4; - __IO uint32_t FWR; - uint32_t RESERVED5[8]; - CAN_FilterRegister_TypeDef sFilterRegister[28]; -} CAN_TypeDef; - -/* CRC Calculation Unit */ -typedef struct -{ - __IO uint32_t DATAR; - __IO uint8_t IDATAR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CTLR; -} CRC_TypeDef; - -/* Digital to Analog Converter */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t SWTR; - __IO uint32_t R12BDHR1; - __IO uint32_t L12BDHR1; - __IO uint32_t R8BDHR1; - __IO uint32_t R12BDHR2; - __IO uint32_t L12BDHR2; - __IO uint32_t R8BDHR2; - __IO uint32_t RD12BDHR; - __IO uint32_t LD12BDHR; - __IO uint32_t RD8BDHR; - __IO uint32_t DOR1; - __IO uint32_t DOR2; -} DAC_TypeDef; - -/* DMA Channel Controller */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t CNTR; - __IO uint32_t PADDR; - __IO uint32_t MADDR; -} DMA_Channel_TypeDef; - -/* DMA Controller */ -typedef struct -{ - __IO uint32_t INTFR; - __IO uint32_t INTFCR; -} DMA_TypeDef; - -/* External Interrupt/Event Controller */ -typedef struct -{ - __IO uint32_t INTENR; - __IO uint32_t EVENR; - __IO uint32_t RTENR; - __IO uint32_t FTENR; - __IO uint32_t SWIEVR; - __IO uint32_t INTFR; -} EXTI_TypeDef; - -/* FLASH Registers */ -typedef struct -{ - __IO uint32_t ACTLR; - __IO uint32_t KEYR; - __IO uint32_t OBKEYR; - __IO uint32_t STATR; - __IO uint32_t CTLR; - __IO uint32_t ADDR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WPR; - __IO uint32_t MODEKEYR; -} FLASH_TypeDef; - -/* Option Bytes Registers */ -typedef struct -{ - __IO uint16_t RDPR; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRPR0; - __IO uint16_t WRPR1; - __IO uint16_t WRPR2; - __IO uint16_t WRPR3; -} OB_TypeDef; - -/* FSMC Bank1 Registers */ -typedef struct -{ - __IO uint32_t BTCR[8]; -} FSMC_Bank1_TypeDef; - -/* FSMC Bank1E Registers */ -typedef struct -{ - __IO uint32_t BWTR[7]; -} FSMC_Bank1E_TypeDef; - -/* FSMC Bank2 Registers */ -typedef struct -{ - __IO uint32_t PCR2; - __IO uint32_t SR2; - __IO uint32_t PMEM2; - __IO uint32_t PATT2; - uint32_t RESERVED0; - __IO uint32_t ECCR2; -} FSMC_Bank2_TypeDef; - -/* General Purpose I/O */ -typedef struct -{ - __IO uint32_t CFGLR; - __IO uint32_t CFGHR; - __IO uint32_t INDR; - __IO uint32_t OUTDR; - __IO uint32_t BSHR; - __IO uint32_t BCR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/* Alternate Function I/O */ -typedef struct -{ - __IO uint32_t ECR; - __IO uint32_t PCFR1; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t PCFR2; -} AFIO_TypeDef; - -/* Inter Integrated Circuit Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t OADDR1; - uint16_t RESERVED2; - __IO uint16_t OADDR2; - uint16_t RESERVED3; - __IO uint16_t DATAR; - uint16_t RESERVED4; - __IO uint16_t STAR1; - uint16_t RESERVED5; - __IO uint16_t STAR2; - uint16_t RESERVED6; - __IO uint16_t CKCFGR; - uint16_t RESERVED7; - __IO uint16_t RTR; - uint16_t RESERVED8; -} I2C_TypeDef; - -/* Independent WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t PSCR; - __IO uint32_t RLDR; - __IO uint32_t STATR; -} IWDG_TypeDef; - -/* Power Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/* Reset and Clock Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR0; - __IO uint32_t INTR; - __IO uint32_t APB2PRSTR; - __IO uint32_t APB1PRSTR; - __IO uint32_t AHBPCENR; - __IO uint32_t APB2PCENR; - __IO uint32_t APB1PCENR; - __IO uint32_t BDCTLR; - __IO uint32_t RSTSCKR; - - __IO uint32_t AHBRSTR; - __IO uint32_t CFGR2; -} RCC_TypeDef; - -/* Real-Time Clock */ -typedef struct -{ - __IO uint16_t CTLRH; - uint16_t RESERVED0; - __IO uint16_t CTLRL; - uint16_t RESERVED1; - __IO uint16_t PSCRH; - uint16_t RESERVED2; - __IO uint16_t PSCRL; - uint16_t RESERVED3; - __IO uint16_t DIVH; - uint16_t RESERVED4; - __IO uint16_t DIVL; - uint16_t RESERVED5; - __IO uint16_t CNTH; - uint16_t RESERVED6; - __IO uint16_t CNTL; - uint16_t RESERVED7; - __IO uint16_t ALRMH; - uint16_t RESERVED8; - __IO uint16_t ALRML; - uint16_t RESERVED9; -} RTC_TypeDef; - -/* SDIO Registers */ -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLKCR; - __IO uint32_t ARG; - __IO uint32_t CMD; - __I uint32_t RESPCMD; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __I uint32_t RESP4; - __IO uint32_t DTIMER; - __IO uint32_t DLEN; - __IO uint32_t DCTRL; - __I uint32_t DCOUNT; - __I uint32_t STA; - __IO uint32_t ICR; - __IO uint32_t MASK; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} SDIO_TypeDef; - -/* Serial Peripheral Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t STATR; - uint16_t RESERVED2; - __IO uint16_t DATAR; - uint16_t RESERVED3; - __IO uint16_t CRCR; - uint16_t RESERVED4; - __IO uint16_t RCRCR; - uint16_t RESERVED5; - __IO uint16_t TCRCR; - uint16_t RESERVED6; - __IO uint16_t I2SCFGR; - uint16_t RESERVED7; - __IO uint16_t I2SPR; - uint16_t RESERVED8; - __IO uint16_t HSCR; - uint16_t RESERVED9; -} SPI_TypeDef; - -/* TIM */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t SMCFGR; - uint16_t RESERVED2; - __IO uint16_t DMAINTENR; - uint16_t RESERVED3; - __IO uint16_t INTFR; - uint16_t RESERVED4; - __IO uint16_t SWEVGR; - uint16_t RESERVED5; - __IO uint16_t CHCTLR1; - uint16_t RESERVED6; - __IO uint16_t CHCTLR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ATRLR; - uint16_t RESERVED11; - __IO uint16_t RPTCR; - uint16_t RESERVED12; - __IO uint16_t CH1CVR; - uint16_t RESERVED13; - __IO uint16_t CH2CVR; - uint16_t RESERVED14; - __IO uint16_t CH3CVR; - uint16_t RESERVED15; - __IO uint16_t CH4CVR; - uint16_t RESERVED16; - __IO uint16_t BDTR; - uint16_t RESERVED17; - __IO uint16_t DMACFGR; - uint16_t RESERVED18; - __IO uint16_t DMAADR; - uint16_t RESERVED19; -} TIM_TypeDef; - -/* Universal Synchronous Asynchronous Receiver Transmitter */ -typedef struct -{ - __IO uint16_t STATR; - uint16_t RESERVED0; - __IO uint16_t DATAR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CTLR1; - uint16_t RESERVED3; - __IO uint16_t CTLR2; - uint16_t RESERVED4; - __IO uint16_t CTLR3; - uint16_t RESERVED5; - __IO uint16_t GPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/* Window WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR; - __IO uint32_t STATR; -} WWDG_TypeDef; - -/* Enhanced Registers */ -typedef struct -{ - __IO uint32_t EXTEN_CTR; -} EXTEN_TypeDef; - -/* OPA Registers */ -typedef struct -{ - __IO uint32_t CR; -} OPA_TypeDef; - -/* RNG Registers */ -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t SR; - __IO uint32_t DR; -} RNG_TypeDef; - -/* DVP Registers */ -typedef struct -{ - __IO uint8_t CR0; - __IO uint8_t CR1; - __IO uint8_t IER; - __IO uint8_t Reserved0; - __IO uint16_t ROW_NUM; - __IO uint16_t COL_NUM; - __IO uint32_t DMA_BUF0; - __IO uint32_t DMA_BUF1; - __IO uint8_t IFR; - __IO uint8_t STATUS; - __IO uint16_t Reserved1; - __IO uint16_t ROW_CNT; - __IO uint16_t Reserved2; - __IO uint16_t HOFFCNT; - __IO uint16_t VST; - __IO uint16_t CAPCNT; - __IO uint16_t VLINE; - __IO uint32_t DR; -} DVP_TypeDef; - -/* USBHS Registers */ -typedef struct -{ - __IO uint8_t CONTROL; - __IO uint8_t HOST_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_AD; - __IO uint16_t FRAME_NO; - __IO uint8_t SUSPEND; - __IO uint8_t RESERVED0; - __IO uint8_t SPEED_TYPE; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint16_t RX_LEN; - __IO uint16_t RESERVED1; - __IO uint32_t ENDP_CONFIG; - __IO uint32_t ENDP_TYPE; - __IO uint32_t BUF_MODE; - __IO uint32_t UEP0_DMA; - __IO uint32_t UEP1_RX_DMA; - __IO uint32_t UEP2_RX_DMA; - __IO uint32_t UEP3_RX_DMA; - __IO uint32_t UEP4_RX_DMA; - __IO uint32_t UEP5_RX_DMA; - __IO uint32_t UEP6_RX_DMA; - __IO uint32_t UEP7_RX_DMA; - __IO uint32_t UEP8_RX_DMA; - __IO uint32_t UEP9_RX_DMA; - __IO uint32_t UEP10_RX_DMA; - __IO uint32_t UEP11_RX_DMA; - __IO uint32_t UEP12_RX_DMA; - __IO uint32_t UEP13_RX_DMA; - __IO uint32_t UEP14_RX_DMA; - __IO uint32_t UEP15_RX_DMA; - __IO uint32_t UEP1_TX_DMA; - __IO uint32_t UEP2_TX_DMA; - __IO uint32_t UEP3_TX_DMA; - __IO uint32_t UEP4_TX_DMA; - __IO uint32_t UEP5_TX_DMA; - __IO uint32_t UEP6_TX_DMA; - __IO uint32_t UEP7_TX_DMA; - __IO uint32_t UEP8_TX_DMA; - __IO uint32_t UEP9_TX_DMA; - __IO uint32_t UEP10_TX_DMA; - __IO uint32_t UEP11_TX_DMA; - __IO uint32_t UEP12_TX_DMA; - __IO uint32_t UEP13_TX_DMA; - __IO uint32_t UEP14_TX_DMA; - __IO uint32_t UEP15_TX_DMA; - __IO uint16_t UEP0_MAX_LEN; - __IO uint16_t RESERVED2; - __IO uint16_t UEP1_MAX_LEN; - __IO uint16_t RESERVED3; - __IO uint16_t UEP2_MAX_LEN; - __IO uint16_t RESERVED4; - __IO uint16_t UEP3_MAX_LEN; - __IO uint16_t RESERVED5; - __IO uint16_t UEP4_MAX_LEN; - __IO uint16_t RESERVED6; - __IO uint16_t UEP5_MAX_LEN; - __IO uint16_t RESERVED7; - __IO uint16_t UEP6_MAX_LEN; - __IO uint16_t RESERVED8; - __IO uint16_t UEP7_MAX_LEN; - __IO uint16_t RESERVED9; - __IO uint16_t UEP8_MAX_LEN; - __IO uint16_t RESERVED10; - __IO uint16_t UEP9_MAX_LEN; - __IO uint16_t RESERVED11; - __IO uint16_t UEP10_MAX_LEN; - __IO uint16_t RESERVED12; - __IO uint16_t UEP11_MAX_LEN; - __IO uint16_t RESERVED13; - __IO uint16_t UEP12_MAX_LEN; - __IO uint16_t RESERVED14; - __IO uint16_t UEP13_MAX_LEN; - __IO uint16_t RESERVED15; - __IO uint16_t UEP14_MAX_LEN; - __IO uint16_t RESERVED16; - __IO uint16_t UEP15_MAX_LEN; - __IO uint16_t RESERVED17; - __IO uint16_t UEP0_TX_LEN; - __IO uint8_t UEP0_TX_CTRL; - __IO uint8_t UEP0_RX_CTRL; - __IO uint16_t UEP1_TX_LEN; - __IO uint8_t UEP1_TX_CTRL; - __IO uint8_t UEP1_RX_CTRL; - __IO uint16_t UEP2_TX_LEN; - __IO uint8_t UEP2_TX_CTRL; - __IO uint8_t UEP2_RX_CTRL; - __IO uint16_t UEP3_TX_LEN; - __IO uint8_t UEP3_TX_CTRL; - __IO uint8_t UEP3_RX_CTRL; - __IO uint16_t UEP4_TX_LEN; - __IO uint8_t UEP4_TX_CTRL; - __IO uint8_t UEP4_RX_CTRL; - __IO uint16_t UEP5_TX_LEN; - __IO uint8_t UEP5_TX_CTRL; - __IO uint8_t UEP5_RX_CTRL; - __IO uint16_t UEP6_TX_LEN; - __IO uint8_t UEP6_TX_CTRL; - __IO uint8_t UEP6_RX_CTRL; - __IO uint16_t UEP7_TX_LEN; - __IO uint8_t UEP7_TX_CTRL; - __IO uint8_t UEP7_RX_CTRL; - __IO uint16_t UEP8_TX_LEN; - __IO uint8_t UEP8_TX_CTRL; - __IO uint8_t UEP8_RX_CTRL; - __IO uint16_t UEP9_TX_LEN; - __IO uint8_t UEP9_TX_CTRL; - __IO uint8_t UEP9_RX_CTRL; - __IO uint16_t UEP10_TX_LEN; - __IO uint8_t UEP10_TX_CTRL; - __IO uint8_t UEP10_RX_CTRL; - __IO uint16_t UEP11_TX_LEN; - __IO uint8_t UEP11_TX_CTRL; - __IO uint8_t UEP11_RX_CTRL; - __IO uint16_t UEP12_TX_LEN; - __IO uint8_t UEP12_TX_CTRL; - __IO uint8_t UEP12_RX_CTRL; - __IO uint16_t UEP13_TX_LEN; - __IO uint8_t UEP13_TX_CTRL; - __IO uint8_t UEP13_RX_CTRL; - __IO uint16_t UEP14_TX_LEN; - __IO uint8_t UEP14_TX_CTRL; - __IO uint8_t UEP14_RX_CTRL; - __IO uint16_t UEP15_TX_LEN; - __IO uint8_t UEP15_TX_CTRL; - __IO uint8_t UEP15_RX_CTRL; -} USBHSD_TypeDef; - -typedef struct __attribute__((packed)) -{ - __IO uint8_t CONTROL; - __IO uint8_t HOST_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_AD; - __IO uint16_t FRAME_NO; - __IO uint8_t SUSPEND; - __IO uint8_t RESERVED0; - __IO uint8_t SPEED_TYPE; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint16_t RX_LEN; - __IO uint16_t RESERVED1; - __IO uint32_t HOST_EP_CONFIG; - __IO uint32_t HOST_EP_TYPE; - __IO uint32_t RESERVED2; - __IO uint32_t RESERVED3; - __IO uint32_t RESERVED4; - __IO uint32_t HOST_RX_DMA; - __IO uint32_t RESERVED5; - __IO uint32_t RESERVED6; - __IO uint32_t RESERVED7; - __IO uint32_t RESERVED8; - __IO uint32_t RESERVED9; - __IO uint32_t RESERVED10; - __IO uint32_t RESERVED11; - __IO uint32_t RESERVED12; - __IO uint32_t RESERVED13; - __IO uint32_t RESERVED14; - __IO uint32_t RESERVED15; - __IO uint32_t RESERVED16; - __IO uint32_t RESERVED17; - __IO uint32_t RESERVED18; - __IO uint32_t RESERVED19; - __IO uint32_t HOST_TX_DMA; - __IO uint32_t RESERVED20; - __IO uint32_t RESERVED21; - __IO uint32_t RESERVED22; - __IO uint32_t RESERVED23; - __IO uint32_t RESERVED24; - __IO uint32_t RESERVED25; - __IO uint32_t RESERVED26; - __IO uint32_t RESERVED27; - __IO uint32_t RESERVED28; - __IO uint32_t RESERVED29; - __IO uint32_t RESERVED30; - __IO uint32_t RESERVED31; - __IO uint32_t RESERVED32; - __IO uint32_t RESERVED33; - __IO uint16_t HOST_RX_MAX_LEN; - __IO uint16_t RESERVED34; - __IO uint32_t RESERVED35; - __IO uint32_t RESERVED36; - __IO uint32_t RESERVED37; - __IO uint32_t RESERVED38; - __IO uint32_t RESERVED39; - __IO uint32_t RESERVED40; - __IO uint32_t RESERVED41; - __IO uint32_t RESERVED42; - __IO uint32_t RESERVED43; - __IO uint32_t RESERVED44; - __IO uint32_t RESERVED45; - __IO uint32_t RESERVED46; - __IO uint32_t RESERVED47; - __IO uint32_t RESERVED48; - __IO uint32_t RESERVED49; - __IO uint8_t HOST_EP_PID; - __IO uint8_t RESERVED50; - __IO uint8_t RESERVED51; - __IO uint8_t HOST_RX_CTRL; - __IO uint16_t HOST_TX_LEN; - __IO uint8_t HOST_TX_CTRL; - __IO uint8_t RESERVED52; - __IO uint16_t HOST_SPLIT_DATA; -} USBHSH_TypeDef; - - -/* USBOTG_FS Registers */ -typedef struct -{ - __IO uint8_t BASE_CTRL; - __IO uint8_t UDEV_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_ADDR; - __IO uint8_t Reserve0; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint16_t RX_LEN; - __IO uint16_t Reserve1; - __IO uint8_t UEP4_1_MOD; - __IO uint8_t UEP2_3_MOD; - __IO uint8_t UEP5_6_MOD; - __IO uint8_t UEP7_MOD; - __IO uint32_t UEP0_DMA; - __IO uint32_t UEP1_DMA; - __IO uint32_t UEP2_DMA; - __IO uint32_t UEP3_DMA; - __IO uint32_t UEP4_DMA; - __IO uint32_t UEP5_DMA; - __IO uint32_t UEP6_DMA; - __IO uint32_t UEP7_DMA; - __IO uint16_t UEP0_TX_LEN; - __IO uint8_t UEP0_TX_CTRL; - __IO uint8_t UEP0_RX_CTRL; - __IO uint16_t UEP1_TX_LEN; - __IO uint8_t UEP1_TX_CTRL; - __IO uint8_t UEP1_RX_CTRL; - __IO uint16_t UEP2_TX_LEN; - __IO uint8_t UEP2_TX_CTRL; - __IO uint8_t UEP2_RX_CTRL; - __IO uint16_t UEP3_TX_LEN; - __IO uint8_t UEP3_TX_CTRL; - __IO uint8_t UEP3_RX_CTRL; - __IO uint16_t UEP4_TX_LEN; - __IO uint8_t UEP4_TX_CTRL; - __IO uint8_t UEP4_RX_CTRL; - __IO uint16_t UEP5_TX_LEN; - __IO uint8_t UEP5_TX_CTRL; - __IO uint8_t UEP5_RX_CTRL; - __IO uint16_t UEP6_TX_LEN; - __IO uint8_t UEP6_TX_CTRL; - __IO uint8_t UEP6_RX_CTRL; - __IO uint16_t UEP7_TX_LEN; - __IO uint8_t UEP7_TX_CTRL; - __IO uint8_t UEP7_RX_CTRL; - __IO uint32_t Reserve2; - __IO uint32_t OTG_CR; - __IO uint32_t OTG_SR; -}USBOTG_FS_TypeDef; - -typedef struct __attribute__((packed)) -{ - __IO uint8_t BASE_CTRL; - __IO uint8_t HOST_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_ADDR; - __IO uint8_t Reserve0; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint16_t RX_LEN; - __IO uint16_t Reserve1; - __IO uint8_t Reserve2; - __IO uint8_t HOST_EP_MOD; - __IO uint16_t Reserve3; - __IO uint32_t Reserve4; - __IO uint32_t Reserve5; - __IO uint32_t HOST_RX_DMA; - __IO uint32_t HOST_TX_DMA; - __IO uint32_t Reserve6; - __IO uint32_t Reserve7; - __IO uint32_t Reserve8; - __IO uint32_t Reserve9; - __IO uint32_t Reserve10; - __IO uint16_t Reserve11; - __IO uint16_t HOST_SETUP; - __IO uint8_t HOST_EP_PID; - __IO uint8_t Reserve12; - __IO uint8_t Reserve13; - __IO uint8_t HOST_RX_CTRL; - __IO uint16_t HOST_TX_LEN; - __IO uint8_t HOST_TX_CTRL; - __IO uint8_t Reserve14; - __IO uint32_t Reserve15; - __IO uint32_t Reserve16; - __IO uint32_t Reserve17; - __IO uint32_t Reserve18; - __IO uint32_t Reserve19; - __IO uint32_t OTG_CR; - __IO uint32_t OTG_SR; -}USBOTGH_FS_TypeDef; - -/* Ethernet MAC */ -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - uint32_t RESERVED8[567]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - uint32_t RESERVED9[9]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - - - -/* Peripheral memory map */ -#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /* FSMC registers base address */ - - -#define APB1PERIPH_BASE (PERIPH_BASE) -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define UART6_BASE (APB1PERIPH_BASE + 0x1800) -#define UART7_BASE (APB1PERIPH_BASE + 0x1C00) -#define UART8_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) -#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) -#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) -#define SDIO_BASE (APB2PERIPH_BASE + 0x8000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) -#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x046C) -#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x0480) -#define DMA2_Channel8_BASE (AHBPERIPH_BASE + 0x0490) -#define DMA2_Channel9_BASE (AHBPERIPH_BASE + 0x04A0) -#define DMA2_Channel10_BASE (AHBPERIPH_BASE + 0x04B0) -#define DMA2_Channel11_BASE (AHBPERIPH_BASE + 0x04C0) -#define DMA2_EXTEN_BASE (AHBPERIPH_BASE + 0x04D0) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) -#define USBHS_BASE (AHBPERIPH_BASE + 0x3400) -#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) -#define OPA_BASE (AHBPERIPH_BASE + 0x3804) -#define RNG_BASE (AHBPERIPH_BASE + 0x3C00) - -#define ETH_BASE (AHBPERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -#define USBFS_BASE ((uint32_t)0x50000000) -#define DVP_BASE ((uint32_t)0x50050000) - -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) - -#define OB_BASE ((uint32_t)0x1FFFF800) - -/* Peripheral declaration */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define UART6 ((USART_TypeDef *) UART6_BASE) -#define UART7 ((USART_TypeDef *) UART7_BASE) -#define UART8 ((USART_TypeDef *) UART8_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define BKP ((BKP_TypeDef *) BKP_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) - -#define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define TKey1 ((ADC_TypeDef *) ADC1_BASE) -#define TKey2 ((ADC_TypeDef *) ADC2_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) - -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_EXTEN ((DMA_TypeDef *) DMA2_EXTEN_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) -#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) -#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) -#define DMA2_Channel9 ((DMA_Channel_TypeDef *) DMA2_Channel9_BASE) -#define DMA2_Channel10 ((DMA_Channel_TypeDef *) DMA2_Channel10_BASE) -#define DMA2_Channel11 ((DMA_Channel_TypeDef *) DMA2_Channel11_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define USBHSD ((USBHSD_TypeDef *) USBHS_BASE) -#define USBHSH ((USBHSH_TypeDef *) USBHS_BASE) -#define USBOTG_FS ((USBOTG_FS_TypeDef *)USBFS_BASE) -#define USBOTG_H_FS ((USBOTGH_FS_TypeDef *)USBFS_BASE) -#define EXTEN ((EXTEN_TypeDef *) EXTEN_BASE) -#define OPA ((OPA_TypeDef *) OPA_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) - -#define DVP ((DVP_TypeDef *) DVP_BASE) - -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) - -#define OB ((OB_TypeDef *) OB_BASE) - -/******************************************************************************/ -/* Peripheral Registers Bits Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* Analog to Digital Converter */ -/******************************************************************************/ - -/******************** Bit definition for ADC_STATR register ********************/ -#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ -#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ -#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ -#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ -#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ - -/******************* Bit definition for ADC_CTLR1 register ********************/ -#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ -#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ -#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ -#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ -#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ -#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ -#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ -#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ - -#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ -#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ - -#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ -#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ -#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ - -#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ -#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ - -/******************* Bit definition for ADC_CTLR2 register ********************/ -#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ -#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ -#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ -#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ -#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ -#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ - -#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ - -#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ -#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ -#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ - -#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ -#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ -#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ -#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ - -/****************** Bit definition for ADC_SAMPTR1 register *******************/ -#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ - -/****************** Bit definition for ADC_SAMPTR2 register *******************/ -#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ - -#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ -#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ -#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ - -/****************** Bit definition for ADC_IOFR1 register *******************/ -#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_IOFR2 register *******************/ -#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_IOFR3 register *******************/ -#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_IOFR4 register *******************/ -#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_WDHTR register ********************/ -#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ - -/******************* Bit definition for ADC_WDLTR register ********************/ -#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ - -/******************* Bit definition for ADC_RSQR1 register *******************/ -#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ -#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ - -/******************* Bit definition for ADC_RSQR2 register *******************/ -#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_RSQR3 register *******************/ -#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_ISQR register *******************/ -#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ -#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ - -/******************* Bit definition for ADC_IDATAR1 register *******************/ -#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR2 register *******************/ -#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR3 register *******************/ -#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR4 register *******************/ -#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************** Bit definition for ADC_RDATAR register ********************/ -#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ -#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ - -/******************************************************************************/ -/* Backup registers */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DATAR1 register ********************/ -#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR2 register ********************/ -#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR3 register ********************/ -#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR4 register ********************/ -#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR5 register ********************/ -#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR6 register ********************/ -#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR7 register ********************/ -#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR8 register ********************/ -#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR9 register ********************/ -#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR10 register *******************/ -#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR11 register *******************/ -#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR12 register *******************/ -#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR13 register *******************/ -#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR14 register *******************/ -#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR15 register *******************/ -#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR16 register *******************/ -#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR17 register *******************/ -#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ - -/****************** Bit definition for BKP_DATAR18 register ********************/ -#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR19 register *******************/ -#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR20 register *******************/ -#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR21 register *******************/ -#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR22 register *******************/ -#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR23 register *******************/ -#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR24 register *******************/ -#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR25 register *******************/ -#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR26 register *******************/ -#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR27 register *******************/ -#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR28 register *******************/ -#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR29 register *******************/ -#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR30 register *******************/ -#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR31 register *******************/ -#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR32 register *******************/ -#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR33 register *******************/ -#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR34 register *******************/ -#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR35 register *******************/ -#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR36 register *******************/ -#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR37 register *******************/ -#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR38 register *******************/ -#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR39 register *******************/ -#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR40 register *******************/ -#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR41 register *******************/ -#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ - -/******************* Bit definition for BKP_DATAR42 register *******************/ -#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ - -/****************** Bit definition for BKP_OCTLR register *******************/ -#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ -#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ -#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ -#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_TPCTLR register ********************/ -#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ -#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ - -/******************* Bit definition for BKP_TPCSR register ********************/ -#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ -#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ -#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ -#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ -#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ - -/******************************************************************************/ -/* Controller Area Network */ -/******************************************************************************/ - -/******************* Bit definition for CAN_CTLR register ********************/ -#define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */ -#define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */ -#define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */ -#define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */ -#define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */ -#define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */ -#define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */ -#define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */ -#define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */ - -/******************* Bit definition for CAN_STATR register ********************/ -#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ -#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ -#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ -#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ -#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ -#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ -#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ -#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ -#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ - -/******************* Bit definition for CAN_TSTATR register ********************/ -#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ -#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ -#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ -#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ -#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ -#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ -#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ -#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ -#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ -#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ -#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ -#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ -#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ -#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ -#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ -#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ - -#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ -#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ -#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ -#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ - -#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ -#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ - -/******************* Bit definition for CAN_RFIFO0 register *******************/ -#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ -#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ -#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ -#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ - -/******************* Bit definition for CAN_RFIFO1 register *******************/ -#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ -#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ -#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ -#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ - -/******************** Bit definition for CAN_INTENR register *******************/ -#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ -#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ -#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ -#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ -#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ -#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ -#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ -#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ -#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ -#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ -#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ -#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ -#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ -#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ - -/******************** Bit definition for CAN_ERRSR register *******************/ -#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ -#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ -#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ - -#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ -#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ - -#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ -#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ - -/******************* Bit definition for CAN_BTIMR register ********************/ -#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) /* Baud Rate Prescaler */ -#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) /* Time Segment 1 */ -#define CAN_BTIMR_TS2 ((uint32_t)0x00700000) /* Time Segment 2 */ -#define CAN_BTIMR_SJW ((uint32_t)0x03000000) /* Resynchronization Jump Width */ -#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */ -#define CAN_BTIMR_SILM ((uint32_t)0x80000000) /* Silent Mode */ - -/****************** Bit definition for CAN_TXMI0R register ********************/ -#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ -#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/****************** Bit definition for CAN_TXMDT0R register *******************/ -#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ -#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/****************** Bit definition for CAN_TXMDL0R register *******************/ -#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/****************** Bit definition for CAN_TXMDH0R register *******************/ -#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_TXMI1R register *******************/ -#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ -#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TXMDT1R register ******************/ -#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ -#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_TXMDL1R register ******************/ -#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_TXMDH1R register ******************/ -#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_TXMI2R register *******************/ -#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ -#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TXMDT2R register ******************/ -#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ -#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_TXMDL2R register ******************/ -#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_TXMDH2R register ******************/ -#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_RXMI0R register *******************/ -#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ -#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RXMDT0R register ******************/ -#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ -#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_RXMDL0R register ******************/ -#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_RXMDH0R register ******************/ -#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_RXMI1R register *******************/ -#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ -#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ -#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ -#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RXMDT1R register ******************/ -#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ -#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ -#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ - -/******************* Bit definition for CAN_RXMDL1R register ******************/ -#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ -#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ -#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ -#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ - -/******************* Bit definition for CAN_RXMDH1R register ******************/ -#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ -#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ -#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ -#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ - -/******************* Bit definition for CAN_FCTLR register ********************/ -#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ - -/******************* Bit definition for CAN_FMCFGR register *******************/ -#define CAN_FMCFGR_FBM ((uint16_t)0x3FFF) /* Filter Mode */ -#define CAN_FMCFGR_FBM0 ((uint16_t)0x0001) /* Filter Init Mode bit 0 */ -#define CAN_FMCFGR_FBM1 ((uint16_t)0x0002) /* Filter Init Mode bit 1 */ -#define CAN_FMCFGR_FBM2 ((uint16_t)0x0004) /* Filter Init Mode bit 2 */ -#define CAN_FMCFGR_FBM3 ((uint16_t)0x0008) /* Filter Init Mode bit 3 */ -#define CAN_FMCFGR_FBM4 ((uint16_t)0x0010) /* Filter Init Mode bit 4 */ -#define CAN_FMCFGR_FBM5 ((uint16_t)0x0020) /* Filter Init Mode bit 5 */ -#define CAN_FMCFGR_FBM6 ((uint16_t)0x0040) /* Filter Init Mode bit 6 */ -#define CAN_FMCFGR_FBM7 ((uint16_t)0x0080) /* Filter Init Mode bit 7 */ -#define CAN_FMCFGR_FBM8 ((uint16_t)0x0100) /* Filter Init Mode bit 8 */ -#define CAN_FMCFGR_FBM9 ((uint16_t)0x0200) /* Filter Init Mode bit 9 */ -#define CAN_FMCFGR_FBM10 ((uint16_t)0x0400) /* Filter Init Mode bit 10 */ -#define CAN_FMCFGR_FBM11 ((uint16_t)0x0800) /* Filter Init Mode bit 11 */ -#define CAN_FMCFGR_FBM12 ((uint16_t)0x1000) /* Filter Init Mode bit 12 */ -#define CAN_FMCFGR_FBM13 ((uint16_t)0x2000) /* Filter Init Mode bit 13 */ - -/******************* Bit definition for CAN_FSCFGR register *******************/ -#define CAN_FSCFGR_FSC ((uint16_t)0x3FFF) /* Filter Scale Configuration */ -#define CAN_FSCFGR_FSC0 ((uint16_t)0x0001) /* Filter Scale Configuration bit 0 */ -#define CAN_FSCFGR_FSC1 ((uint16_t)0x0002) /* Filter Scale Configuration bit 1 */ -#define CAN_FSCFGR_FSC2 ((uint16_t)0x0004) /* Filter Scale Configuration bit 2 */ -#define CAN_FSCFGR_FSC3 ((uint16_t)0x0008) /* Filter Scale Configuration bit 3 */ -#define CAN_FSCFGR_FSC4 ((uint16_t)0x0010) /* Filter Scale Configuration bit 4 */ -#define CAN_FSCFGR_FSC5 ((uint16_t)0x0020) /* Filter Scale Configuration bit 5 */ -#define CAN_FSCFGR_FSC6 ((uint16_t)0x0040) /* Filter Scale Configuration bit 6 */ -#define CAN_FSCFGR_FSC7 ((uint16_t)0x0080) /* Filter Scale Configuration bit 7 */ -#define CAN_FSCFGR_FSC8 ((uint16_t)0x0100) /* Filter Scale Configuration bit 8 */ -#define CAN_FSCFGR_FSC9 ((uint16_t)0x0200) /* Filter Scale Configuration bit 9 */ -#define CAN_FSCFGR_FSC10 ((uint16_t)0x0400) /* Filter Scale Configuration bit 10 */ -#define CAN_FSCFGR_FSC11 ((uint16_t)0x0800) /* Filter Scale Configuration bit 11 */ -#define CAN_FSCFGR_FSC12 ((uint16_t)0x1000) /* Filter Scale Configuration bit 12 */ -#define CAN_FSCFGR_FSC13 ((uint16_t)0x2000) /* Filter Scale Configuration bit 13 */ - -/****************** Bit definition for CAN_FAFIFOR register *******************/ -#define CAN_FAFIFOR_FFA ((uint16_t)0x3FFF) /* Filter FIFO Assignment */ -#define CAN_FAFIFOR_FFA0 ((uint16_t)0x0001) /* Filter FIFO Assignment for Filter 0 */ -#define CAN_FAFIFOR_FFA1 ((uint16_t)0x0002) /* Filter FIFO Assignment for Filter 1 */ -#define CAN_FAFIFOR_FFA2 ((uint16_t)0x0004) /* Filter FIFO Assignment for Filter 2 */ -#define CAN_FAFIFOR_FFA3 ((uint16_t)0x0008) /* Filter FIFO Assignment for Filter 3 */ -#define CAN_FAFIFOR_FFA4 ((uint16_t)0x0010) /* Filter FIFO Assignment for Filter 4 */ -#define CAN_FAFIFOR_FFA5 ((uint16_t)0x0020) /* Filter FIFO Assignment for Filter 5 */ -#define CAN_FAFIFOR_FFA6 ((uint16_t)0x0040) /* Filter FIFO Assignment for Filter 6 */ -#define CAN_FAFIFOR_FFA7 ((uint16_t)0x0080) /* Filter FIFO Assignment for Filter 7 */ -#define CAN_FAFIFOR_FFA8 ((uint16_t)0x0100) /* Filter FIFO Assignment for Filter 8 */ -#define CAN_FAFIFOR_FFA9 ((uint16_t)0x0200) /* Filter FIFO Assignment for Filter 9 */ -#define CAN_FAFIFOR_FFA10 ((uint16_t)0x0400) /* Filter FIFO Assignment for Filter 10 */ -#define CAN_FAFIFOR_FFA11 ((uint16_t)0x0800) /* Filter FIFO Assignment for Filter 11 */ -#define CAN_FAFIFOR_FFA12 ((uint16_t)0x1000) /* Filter FIFO Assignment for Filter 12 */ -#define CAN_FAFIFOR_FFA13 ((uint16_t)0x2000) /* Filter FIFO Assignment for Filter 13 */ - -/******************* Bit definition for CAN_FWR register *******************/ -#define CAN_FWR_FACT ((uint16_t)0x3FFF) /* Filter Active */ -#define CAN_FWR_FACT0 ((uint16_t)0x0001) /* Filter 0 Active */ -#define CAN_FWR_FACT1 ((uint16_t)0x0002) /* Filter 1 Active */ -#define CAN_FWR_FACT2 ((uint16_t)0x0004) /* Filter 2 Active */ -#define CAN_FWR_FACT3 ((uint16_t)0x0008) /* Filter 3 Active */ -#define CAN_FWR_FACT4 ((uint16_t)0x0010) /* Filter 4 Active */ -#define CAN_FWR_FACT5 ((uint16_t)0x0020) /* Filter 5 Active */ -#define CAN_FWR_FACT6 ((uint16_t)0x0040) /* Filter 6 Active */ -#define CAN_FWR_FACT7 ((uint16_t)0x0080) /* Filter 7 Active */ -#define CAN_FWR_FACT8 ((uint16_t)0x0100) /* Filter 8 Active */ -#define CAN_FWR_FACT9 ((uint16_t)0x0200) /* Filter 9 Active */ -#define CAN_FWR_FACT10 ((uint16_t)0x0400) /* Filter 10 Active */ -#define CAN_FWR_FACT11 ((uint16_t)0x0800) /* Filter 11 Active */ -#define CAN_FWR_FACT12 ((uint16_t)0x1000) /* Filter 12 Active */ -#define CAN_FWR_FACT13 ((uint16_t)0x2000) /* Filter 13 Active */ - -/******************* Bit definition for CAN_F0R1 register *******************/ -#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F1R1 register *******************/ -#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F2R1 register *******************/ -#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F3R1 register *******************/ -#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F4R1 register *******************/ -#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F5R1 register *******************/ -#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F6R1 register *******************/ -#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F7R1 register *******************/ -#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F8R1 register *******************/ -#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F9R1 register *******************/ -#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F10R1 register ******************/ -#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F11R1 register ******************/ -#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F12R1 register ******************/ -#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F13R1 register ******************/ -#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F0R2 register *******************/ -#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F1R2 register *******************/ -#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F2R2 register *******************/ -#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F3R2 register *******************/ -#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F4R2 register *******************/ -#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F5R2 register *******************/ -#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F6R2 register *******************/ -#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F7R2 register *******************/ -#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F8R2 register *******************/ -#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F9R2 register *******************/ -#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F10R2 register ******************/ -#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F11R2 register ******************/ -#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F12R2 register ******************/ -#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - -/******************* Bit definition for CAN_F13R2 register ******************/ -#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ -#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ -#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ -#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ -#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ -#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ -#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ -#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ -#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ -#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ -#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ -#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ -#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ -#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ -#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ -#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ -#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ -#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ -#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ -#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ -#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ -#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ -#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ -#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ -#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ -#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ -#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ -#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ -#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ -#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ -#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ -#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ - - - -/******************************************************************************/ -/* CRC Calculation Unit */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DATAR register *********************/ -#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ - - -/******************* Bit definition for CRC_IDATAR register ********************/ -#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ - - -/******************** Bit definition for CRC_CTLR register ********************/ -#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ - -/******************************************************************************/ -/* Digital to Analog Converter */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CTLR register ********************/ -#define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */ -#define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */ -#define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */ - -#define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */ -#define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */ -#define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */ - -#define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */ -#define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */ -#define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */ -#define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */ - -#define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */ -#define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */ -#define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */ - -#define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */ -#define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */ - -#define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */ - -/***************** Bit definition for DAC_SWTR register ******************/ -#define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */ -#define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */ - -/***************** Bit definition for DAC_R12BDHR1 register ******************/ -#define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */ - -/***************** Bit definition for DAC_L12BDHR1 register ******************/ -#define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */ - -/****************** Bit definition for DAC_R8BDHR1 register ******************/ -#define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */ - -/***************** Bit definition for DAC_R12BDHR2 register ******************/ -#define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_L12BDHR2 register ******************/ -#define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_R8BDHR2 register ******************/ -#define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */ - -/***************** Bit definition for DAC_RD12BDHR register ******************/ -#define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ -#define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_LD12BDHR register ******************/ -#define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ -#define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_RD8BDHR register ******************/ -#define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */ -#define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */ - -/******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */ - -/******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */ - -/******************************************************************************/ -/* DMA Controller */ -/******************************************************************************/ - -/******************* Bit definition for DMA_INTFR register ********************/ -#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ -#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ -#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ -#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ -#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ -#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ -#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ -#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ -#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ -#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ -#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ -#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ -#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ -#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ -#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ -#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ -#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ -#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ -#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ -#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ -#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ -#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ -#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ -#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ -#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ -#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ -#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ -#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ - -#define DMA_GIF8 ((uint32_t)0x00000001) /* Channel 8 Global interrupt flag */ -#define DMA_TCIF8 ((uint32_t)0x00000002) /* Channel 8 Transfer Complete flag */ -#define DMA_HTIF8 ((uint32_t)0x00000004) /* Channel 8 Half Transfer flag */ -#define DMA_TEIF8 ((uint32_t)0x00000008) /* Channel 8 Transfer Error flag */ -#define DMA_GIF9 ((uint32_t)0x00000010) /* Channel 9 Global interrupt flag */ -#define DMA_TCIF9 ((uint32_t)0x00000020) /* Channel 9 Transfer Complete flag */ -#define DMA_HTIF9 ((uint32_t)0x00000040) /* Channel 9 Half Transfer flag */ -#define DMA_TEIF9 ((uint32_t)0x00000080) /* Channel 9 Transfer Error flag */ -#define DMA_GIF10 ((uint32_t)0x00000100) /* Channel 10 Global interrupt flag */ -#define DMA_TCIF10 ((uint32_t)0x00000200) /* Channel 10 Transfer Complete flag */ -#define DMA_HTIF10 ((uint32_t)0x00000400) /* Channel 10 Half Transfer flag */ -#define DMA_TEIF10 ((uint32_t)0x00000800) /* Channel 10 Transfer Error flag */ -#define DMA_GIF11 ((uint32_t)0x00001000) /* Channel 11 Global interrupt flag */ -#define DMA_TCIF11 ((uint32_t)0x00002000) /* Channel 11 Transfer Complete flag */ -#define DMA_HTIF11 ((uint32_t)0x00004000) /* Channel 11 Half Transfer flag */ -#define DMA_TEIF11 ((uint32_t)0x00008000) /* Channel 11 Transfer Error flag */ - -/******************* Bit definition for DMA_INTFCR register *******************/ -#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ -#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ -#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ -#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ -#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ -#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ -#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ -#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ -#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ -#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ -#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ -#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ -#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ -#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ -#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ -#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ -#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ -#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ -#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ -#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ -#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ -#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ -#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ -#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ -#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ -#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ -#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ -#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CFGR1 register *******************/ -#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ -#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ -#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR2 register *******************/ -#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR3 register *******************/ -#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG4 register *******************/ -#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/****************** Bit definition for DMA_CFG5 register *******************/ -#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/******************* Bit definition for DMA_CFG6 register *******************/ -#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG7 register *******************/ -#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/****************** Bit definition for DMA_CNTR1 register ******************/ -#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR2 register ******************/ -#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR3 register ******************/ -#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR4 register ******************/ -#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR5 register ******************/ -#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR6 register ******************/ -#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR7 register ******************/ -#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_PADDR1 register *******************/ -#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR2 register *******************/ -#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR3 register *******************/ -#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR4 register *******************/ -#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR5 register *******************/ -#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR6 register *******************/ -#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR7 register *******************/ -#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_MADDR1 register *******************/ -#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR2 register *******************/ -#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR3 register *******************/ -#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR4 register *******************/ -#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR5 register *******************/ -#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR6 register *******************/ -#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR7 register *******************/ -#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - - -/******************************************************************************/ -/* External Interrupt/Event Controller */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_INTENR register *******************/ -#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ -#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ -#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ -#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ -#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ -#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ -#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ -#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ -#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ -#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ -#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ -#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ -#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ -#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ -#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ -#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ -#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ -#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ -#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ -#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ - -/******************* Bit definition for EXTI_EVENR register *******************/ -#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ -#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ -#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ -#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ -#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ -#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ -#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ -#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ -#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ -#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ -#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ -#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ -#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ -#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ -#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ -#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ -#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ -#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ -#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ -#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ - -/****************** Bit definition for EXTI_RTENR register *******************/ -#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ -#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ -#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ -#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ -#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ -#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ -#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ -#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ -#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ -#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ -#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ -#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ -#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ -#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ -#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ -#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ -#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ -#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ -#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ -#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_FTENR register *******************/ -#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ -#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ -#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ -#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ -#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ -#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ -#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ -#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ -#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ -#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ -#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ -#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ -#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ -#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ -#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ -#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ -#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ -#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ -#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ -#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_SWIEVR register ******************/ -#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ -#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ -#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ -#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ -#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ -#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ -#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ -#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ -#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ -#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ -#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ -#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ -#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ -#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ -#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ -#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ -#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ -#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ -#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ -#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ - -/******************* Bit definition for EXTI_INTFR register ********************/ -#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ -#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ -#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ -#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ -#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ -#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ -#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ -#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ -#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ -#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ -#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ -#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ -#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ -#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ -#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ -#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ -#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ -#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ -#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ -#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ - -/******************************************************************************/ -/* FLASH and Option Bytes Registers */ -/******************************************************************************/ - - -/******************* Bit definition for FLASH_ACTLR register ******************/ - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ - -/***************** Bit definition for FLASH_OBKEYR register ****************/ -#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ - -/****************** Bit definition for FLASH_STATR register *******************/ -#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ -#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ -#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ -#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ - -/******************* Bit definition for FLASH_CTLR register *******************/ -#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */ -#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */ -#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ -#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ -#define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ -#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ -#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ -#define FLASH_CTLR_OPTWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ -#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ -#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ -#define FLASH_CTLR_FAST_LOCK ((uint32_t)0x00008000) /* Fast Lock */ -#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */ -#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */ -#define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */ -#define FLASH_CTLR_PAGE_BER64 ((uint32_t)0x00080000) /* Block Erase 64K */ -#define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */ - -/******************* Bit definition for FLASH_ADDR register *******************/ -#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ - -#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ -#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ -#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /* BFB2 */ - -/****************** Bit definition for FLASH_WPR register ******************/ -#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ - -/****************** Bit definition for FLASH_RDPR register *******************/ -#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ -#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_WRPR0 register ******************/ -#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR1 register ******************/ -#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR2 register ******************/ -#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR3 register ******************/ -#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ - -/******************************************************************************/ -/* General Purpose and Alternate Function I/O */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CFGLR register *******************/ -#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_CFGHR register *******************/ -#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_INDR register *******************/ -#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ -#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ -#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ -#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ -#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ -#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ -#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ -#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ -#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ -#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ -#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ -#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ -#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ -#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ -#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ -#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ - -/******************* Bit definition for GPIO_OUTDR register *******************/ -#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ -#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ -#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ -#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ -#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ -#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ -#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ -#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ -#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ -#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ -#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ -#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ -#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ -#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ -#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ -#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSHR register *******************/ -#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ -#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ -#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ -#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ -#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ -#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ -#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ -#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ -#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ -#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ -#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ -#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ -#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ -#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ -#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ -#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ - -#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ -#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ -#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ -#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ -#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ -#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ -#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ -#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ -#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ -#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ -#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ -#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ -#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ -#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ -#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ -#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BCR register *******************/ -#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ -#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ -#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ -#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ -#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ -#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ -#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ -#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ -#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ -#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ -#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ -#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ -#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ -#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ -#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ -#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ -#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ -#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ -#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ -#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ -#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ -#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ -#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ -#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ -#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ -#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ -#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ -#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ -#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ -#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ -#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ -#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ - - -/****************** Bit definition for AFIO_ECR register *******************/ -#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ -#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ -#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ -#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ -#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ - -#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ -#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ -#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ -#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ -#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ -#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ -#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ -#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ -#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ -#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ -#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ -#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ -#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ -#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ -#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ -#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ - -#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ -#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ -#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ -#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ - -#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ -#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ -#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ -#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ -#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ - -#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ - -/****************** Bit definition for AFIO_PCFR1register *******************/ -#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ -#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ -#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ -#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ - -#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ - -#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ -#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ - -#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ - -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ - -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ - -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ - -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ - -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ - -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ - -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ - -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ - -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ - -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ - -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ - -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ - -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ - -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ - -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ - -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ - -/******************************************************************************/ -/* Independent WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_CTLR register ********************/ -#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PSCR register ********************/ -#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ -#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ -#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ -#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ - -/******************* Bit definition for IWDG_RLDR register *******************/ -#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ - -/******************* Bit definition for IWDG_STATR register ********************/ -#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ -#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ - -/******************************************************************************/ -/* Inter-integrated Circuit Interface */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CTLR1 register ********************/ -#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ -#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ -#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ -#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ -#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ -#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ -#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ -#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ -#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ -#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ -#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ -#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ -#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ -#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ - -/******************* Bit definition for I2C_CTLR2 register ********************/ -#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ - -#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ -#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ -#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ -#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ -#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ - -/******************* Bit definition for I2C_OADDR1 register *******************/ -#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ -#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ - -#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ -#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ -#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ -#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ -#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ - -#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OADDR2 register *******************/ -#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ -#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ - -/******************** Bit definition for I2C_DATAR register ********************/ -#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ - -/******************* Bit definition for I2C_STAR1 register ********************/ -#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ -#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ -#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ -#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ -#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ -#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ -#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ -#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ -#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ -#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ -#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ -#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ -#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ -#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ - -/******************* Bit definition for I2C_STAR2 register ********************/ -#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ -#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ -#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ -#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ -#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ -#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ -#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ -#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ - -/******************* Bit definition for I2C_CKCFGR register ********************/ -#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ -#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ - -/****************** Bit definition for I2C_RTR register *******************/ -#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ - - -/******************************************************************************/ -/* Power Control */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CTLR register ********************/ -#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ -#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ -#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ -#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ -#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ - -#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ -#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ - -#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */ -#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */ -#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */ -#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */ -#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */ -#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */ -#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */ -#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */ - -#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ - - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ - - - -/******************************************************************************/ -/* Reset and Clock Control */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CTLR register ********************/ -#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ -#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ -#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ -#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ -#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ -#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ -#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ -#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ -#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ -#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ - - -/******************* Bit definition for RCC_CFGR0 register *******************/ -#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ -#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ -#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ -#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ - -#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ -#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ -#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ - -#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ -#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ -#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ - -#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ -#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ -#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ -#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ -#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ -#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ -#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ -#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ -#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ - -#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ -#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ - -#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ -#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ -#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ -#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ -#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ - -#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ -#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ -#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ - -#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ -#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ -#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ -#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ -#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ - -#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ -#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ -#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ -#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ - -#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ - -#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ - -#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ -#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ - -#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ -#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ - -#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ -#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ - -/* CH32V303x */ -#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ -#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ -#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ -#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ -#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ -#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ -#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ -#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ -#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ -#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ -#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ -#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ -#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ -#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ -#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ -#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ -/* CH32V307x-CH32V305x */ -#define RCC_PLLMULL18_EXTEN ((uint32_t)0x00000000) /* PLL input clock*18 */ -#define RCC_PLLMULL3_EXTEN ((uint32_t)0x00040000) /* PLL input clock*3 */ -#define RCC_PLLMULL4_EXTEN ((uint32_t)0x00080000) /* PLL input clock*4 */ -#define RCC_PLLMULL5_EXTEN ((uint32_t)0x000C0000) /* PLL input clock*5 */ -#define RCC_PLLMULL6_EXTEN ((uint32_t)0x00100000) /* PLL input clock*6 */ -#define RCC_PLLMULL7_EXTEN ((uint32_t)0x00140000) /* PLL input clock*7 */ -#define RCC_PLLMULL8_EXTEN ((uint32_t)0x00180000) /* PLL input clock*8 */ -#define RCC_PLLMULL9_EXTEN ((uint32_t)0x001C0000) /* PLL input clock*9 */ -#define RCC_PLLMULL10_EXTEN ((uint32_t)0x00200000) /* PLL input clock10 */ -#define RCC_PLLMULL11_EXTEN ((uint32_t)0x00240000) /* PLL input clock*11 */ -#define RCC_PLLMULL12_EXTEN ((uint32_t)0x00280000) /* PLL input clock*12 */ -#define RCC_PLLMULL13_EXTEN ((uint32_t)0x002C0000) /* PLL input clock*13 */ -#define RCC_PLLMULL14_EXTEN ((uint32_t)0x00300000) /* PLL input clock*14 */ -#define RCC_PLLMULL6_5_EXTEN ((uint32_t)0x00340000) /* PLL input clock*6.5 */ -#define RCC_PLLMULL15_EXTEN ((uint32_t)0x00380000) /* PLL input clock*15 */ -#define RCC_PLLMULL16_EXTEN ((uint32_t)0x003C0000) /* PLL input clock*16 */ - -#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ - -#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ -#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ -#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ -#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ - -/******************* Bit definition for RCC_INTR register ********************/ -#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ -#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ -#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ -#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ -#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ -#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ -#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ -#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ -#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ -#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ -#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ -#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ -#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ -#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ -#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ -#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ -#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ - - -/***************** Bit definition for RCC_APB2PRSTR register *****************/ -#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ -#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ -#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ -#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ -#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ -#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ - - -#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ - - -#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ -#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ -#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ - -#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ - -/***************** Bit definition for RCC_APB1PRSTR register *****************/ -#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ -#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ -#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ -#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ -#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ - -#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ - - -#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ -#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ - - -#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ -#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ -#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ -#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ - -#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ - -/****************** Bit definition for RCC_AHBPCENR register ******************/ -#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ -#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ -#define RCC_FLITFEN ((uint16_t)0x0010) /* FLITF clock enable */ -#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ -#define RCC_USBHD ((uint16_t)0x1000) - -/****************** Bit definition for RCC_APB2PCENR register *****************/ -#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ -#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ -#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ -#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ -#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ -#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ - -#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ - - -#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ -#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ -#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ - -/***************** Bit definition for RCC_APB1PCENR register ******************/ -#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ -#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ -#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ -#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ -#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ - -#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ -#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ - - -#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ - -/******************* Bit definition for RCC_BDCTLR register *******************/ -#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ -#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ -#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ - -#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ -#define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */ -#define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */ -#define RCC_RTCSEL_HSE ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ -#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ - -/******************* Bit definition for RCC_RSTSCKR register ********************/ -#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ -#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ -#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ -#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ -#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ -#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ -#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ -#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ -#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ - -/******************************************************************************/ -/* RNG */ -/******************************************************************************/ -/******************** Bit definition for RNG_CR register *******************/ -#define RNG_CR_RNGEN ((uint32_t)0x00000004) -#define RNG_CR_IE ((uint32_t)0x00000008) - -/******************** Bit definition for RNG_SR register *******************/ -#define RNG_SR_DRDY ((uint32_t)0x00000001) -#define RNG_SR_CECS ((uint32_t)0x00000002) -#define RNG_SR_SECS ((uint32_t)0x00000004) -#define RNG_SR_CEIS ((uint32_t)0x00000020) -#define RNG_SR_SEIS ((uint32_t)0x00000040) - -/******************************************************************************/ -/* Real-Time Clock */ -/******************************************************************************/ - -/******************* Bit definition for RTC_CTLRH register ********************/ -#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ -#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ -#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ - -/******************* Bit definition for RTC_CTLRL register ********************/ -#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ -#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ -#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ -#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ -#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ -#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ - -/******************* Bit definition for RTC_PSCH register *******************/ -#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ - -/******************* Bit definition for RTC_PRLL register *******************/ -#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ - -/******************* Bit definition for RTC_DIVH register *******************/ -#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ - -/******************* Bit definition for RTC_DIVL register *******************/ -#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ - -/******************* Bit definition for RTC_CNTH register *******************/ -#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ - -/******************* Bit definition for RTC_CNTL register *******************/ -#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ - -/******************* Bit definition for RTC_ALRMH register *******************/ -#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ - -/******************* Bit definition for RTC_ALRML register *******************/ -#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ - -/******************************************************************************/ -/* Serial Peripheral Interface */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CTLR1 register ********************/ -#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ -#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ -#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ - -#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ -#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ -#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ -#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ - -#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ -#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ -#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ -#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ -#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ -#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ -#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ -#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ -#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ -#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CTLR2 register ********************/ -#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ -#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ -#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ -#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ -#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ -#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_STATR register ********************/ -#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ -#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ -#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ -#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ -#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ -#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ -#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ -#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ - -/******************** Bit definition for SPI_DATAR register ********************/ -#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ - -/******************* Bit definition for SPI_CRCR register ******************/ -#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ - -/****************** Bit definition for SPI_RCRCR register ******************/ -#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ - -/****************** Bit definition for SPI_TCRCR register ******************/ -#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ - -/****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ - -#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ -#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ - -/****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ -#define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ - -/******************************************************************************/ -/* TIM */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CTLR1 register ********************/ -#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ -#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ -#define TIM_URS ((uint16_t)0x0004) /* Update request source */ -#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ -#define TIM_DIR ((uint16_t)0x0010) /* Direction */ - -#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ - -#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ - -#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ -#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ - -/******************* Bit definition for TIM_CTLR2 register ********************/ -#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ -#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ -#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ - -#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ -#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ -#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ -#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ -#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ -#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ -#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ -#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ -#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIM_SMCFGR register *******************/ -#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ - -#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ -#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ - -#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ -#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ - -#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ -#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ - -/******************* Bit definition for TIM_DMAINTENR register *******************/ -#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ -#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ -#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ -#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ -#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ -#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ -#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ -#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ -#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ -#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ -#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ -#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ -#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ -#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ -#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ - -/******************** Bit definition for TIM_INTFR register ********************/ -#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ -#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ -#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ -#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ -#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ -#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ -#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ -#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ -#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ -#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ -#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ -#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIM_SWEVGR register ********************/ -#define TIM_UG ((uint8_t)0x01) /* Update Generation */ -#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ -#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ -#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ -#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ -#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ -#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ -#define TIM_BG ((uint8_t)0x80) /* Break Generation */ - -/****************** Bit definition for TIM_CHCTLR1 register *******************/ -#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ -#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ - -#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ - -#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ -#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ - -#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ - - -#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/****************** Bit definition for TIM_CHCTLR2 register *******************/ -#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ -#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ - -#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ - -#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ -#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ - -#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ - - -#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ -#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ -#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ -#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ -#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ -#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ -#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ -#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ -#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ -#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ -#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ -#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ -#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ -#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ -#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ - -/******************* Bit definition for TIM_ATRLR register ********************/ -#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ - -/******************* Bit definition for TIM_RPTCR register ********************/ -#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ - -/******************* Bit definition for TIM_CH1CVR register *******************/ -#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ - -/******************* Bit definition for TIM_CH2CVR register *******************/ -#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ - -/******************* Bit definition for TIM_CH3CVR register *******************/ -#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ - -/******************* Bit definition for TIM_CH4CVR register *******************/ -#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ -#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ -#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ -#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ - -#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ -#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ -#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ -#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ -#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ -#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ -#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ - -/******************* Bit definition for TIM_DMACFGR register ********************/ -#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ -#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ - -#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ -#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ - -/******************* Bit definition for TIM_DMAADR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ - -/******************************************************************************/ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/******************************************************************************/ - -/******************* Bit definition for USART_STATR register *******************/ -#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ -#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ -#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ -#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ -#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ -#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ -#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ -#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ -#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ -#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ - -/******************* Bit definition for USART_DATAR register *******************/ -#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ - -/****************** Bit definition for USART_CTLR1 register *******************/ -#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ -#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ -#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ -#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ -#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ -#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ -#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ -#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ -#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ -#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ -#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ -#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ -#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ -#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ -#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ - -/****************** Bit definition for USART_CTLR2 register *******************/ -#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ -#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ -#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ -#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ -#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ -#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ -#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ - -#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ -#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ -#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ - -/****************** Bit definition for USART_CTLR3 register *******************/ -#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ -#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ -#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ -#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ -#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ -#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ -#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ -#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ -#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ -#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ -#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ -#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ - -/****************** Bit definition for USART_GPR register ******************/ -#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ -#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ -#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ -#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ -#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ -#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ -#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ -#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ -#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ - -#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ - -/******************************************************************************/ -/* Window WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CTLR register ********************/ -#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ -#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ -#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ -#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ -#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ -#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ -#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ - -#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ - -/******************* Bit definition for WWDG_CFGR register *******************/ -#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ -#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ -#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ -#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ -#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ -#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ -#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ -#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ - -#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ -#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ - -#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_STATR register ********************/ -#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ - -/******************************************************************************/ -/* ENHANCED FUNNCTION */ -/******************************************************************************/ - -/**************************** Enhanced register *****************************/ -#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */ -#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */ -#define EXTEN_ETH_10M_EN ((uint32_t)0x00000004) /* Bit 2 */ -#define EXTEN_ETH_RGMII_SEL ((uint32_t)0x00000008) /* Bit 3 */ -#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ -#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ -#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ - -#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */ -#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ -#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define EXTEN_LDO_TRIM ((uint32_t)0x00000C00) /* LDO_TRIM[1:0] bits */ -#define EXTEN_LDO_TRIM0 ((uint32_t)0x00000400) /* Bit 0 */ -#define EXTEN_LDO_TRIM1 ((uint32_t)0x00000800) /* Bit 1 */ - - -/******************************************************************************/ -/* DVP */ -/******************************************************************************/ - -/******************* Bit definition for DVP_CR0 register ********************/ -#define RB_DVP_ENABLE 0x01 // RW, DVP enable -#define RB_DVP_V_POLAR 0x02 // RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert -#define RB_DVP_H_POLAR 0x04 // RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert -#define RB_DVP_P_POLAR 0x08 // RW, DVP PCLK polarity control: 1 = invert, 0 = not invert -#define RB_DVP_MSK_DAT_MOD 0x30 -#define RB_DVP_D8_MOD 0x00 // RW, DVP 8bits data mode -#define RB_DVP_D10_MOD 0x10 // RW, DVP 10bits data mode -#define RB_DVP_D12_MOD 0x20 // RW, DVP 12bits data mode -#define RB_DVP_JPEG 0x40 // RW, DVP JPEG mode - -/******************* Bit definition for DVP_CR1 register ********************/ -#define RB_DVP_DMA_EN 0x01 // RW, DVP dma enable -#define RB_DVP_ALL_CLR 0x02 // RW, DVP all clear, high action -#define RB_DVP_RCV_CLR 0x04 // RW, DVP receive logic clear, high action -#define RB_DVP_BUF_TOG 0x08 // RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0 -#define RB_DVP_CM 0x10 // RW, DVP capture mode -#define RB_DVP_CROP 0x20 // RW, DVP Crop feature enable -#define RB_DVP_FCRC 0xC0 // RW, DVP frame capture rate control: -#define DVP_RATE_100P 0x00 //00 = every frame captured (100%) -#define DVP_RATE_50P 0x40 //01 = every alternate frame captured (50%) -#define DVP_RATE_25P 0x80 //10 = one frame in four frame captured (25%) - -/******************* Bit definition for DVP_IER register ********************/ -#define RB_DVP_IE_STR_FRM 0x01 // RW, DVP frame start interrupt enable -#define RB_DVP_IE_ROW_DONE 0x02 // RW, DVP row received done interrupt enable -#define RB_DVP_IE_FRM_DONE 0x04 // RW, DVP frame received done interrupt enable -#define RB_DVP_IE_FIFO_OV 0x08 // RW, DVP receive fifo overflow interrupt enable -#define RB_DVP_IE_STP_FRM 0x10 // RW, DVP frame stop interrupt enable - -/******************* Bit definition for DVP_IFR register ********************/ -#define RB_DVP_IF_STR_FRM 0x01 // RW1, interrupt flag for DVP frame start -#define RB_DVP_IF_ROW_DONE 0x02 // RW1, interrupt flag for DVP row receive done -#define RB_DVP_IF_FRM_DONE 0x04 // RW1, interrupt flag for DVP frame receive done -#define RB_DVP_IF_FIFO_OV 0x08 // RW1, interrupt flag for DVP receive fifo overflow -#define RB_DVP_IF_STP_FRM 0x10 // RW1, interrupt flag for DVP frame stop - -/******************* Bit definition for DVP_STATUS register ********************/ -#define RB_DVP_FIFO_RDY 0x01 // RO, DVP receive fifo ready -#define RB_DVP_FIFO_FULL 0x02 // RO, DVP receive fifo full -#define RB_DVP_FIFO_OV 0x04 // RO, DVP receive fifo overflow -#define RB_DVP_MSK_FIFO_CNT 0x70 // RO, DVP receive fifo count - - - -#include "ch32v30x_conf.h" - - -#ifdef __cplusplus -} -#endif - -#endif - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x.h +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/22 +* Description : CH32V30x Device Peripheral Access Layer Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_H +#define __CH32V30x_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if !defined(CH32V30x_D8) && !defined(CH32V30x_D8C) +//#define CH32V30x_D8 /* CH32V303x */ +#define CH32V30x_D8C /* CH32V307x-CH32V305x-CH32V317x */ + +#endif + +#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#ifndef HSE_VALUE +#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ +#endif + +/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x1000) /* Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ + +/* CH32V30x Standard Peripheral Library version number */ +#define __CH32V30x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */ +#define __CH32V30x_STDPERIPH_VERSION_SUB (0x07) /* [7:0] sub version */ +#define __CH32V30x_STDPERIPH_VERSION ( (__CH32V30x_STDPERIPH_VERSION_MAIN << 8)\ + |(__CH32V30x_STDPERIPH_VERSION_SUB << 0)) + + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + +#ifdef CH32V30x_D8 + TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ + TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */ + RNG_IRQn = 63, /* RNG global Interrupt */ + SDIO_IRQn = 65, /* SDIO global Interrupt */ + TIM5_IRQn = 66, /* TIM5 global Interrupt */ + SPI3_IRQn = 67, /* SPI3 global Interrupt */ + UART4_IRQn = 68, /* UART4 global Interrupt */ + UART5_IRQn = 69, /* UART5 global Interrupt */ + TIM6_IRQn = 70, /* TIM6 global Interrupt */ + TIM7_IRQn = 71, /* TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */ + USBFS_IRQn = 83, /* USBFS global Interrupt */ + UART6_IRQn = 87, /* UART6 global Interrupt */ + UART7_IRQn = 88, /* UART7 global Interrupt */ + UART8_IRQn = 89, /* UART8 global Interrupt */ + TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */ + TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */ + TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */ + TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */ + TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */ + TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */ + TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */ + TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */ + DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */ + DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */ + DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */ + DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */ + DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */ + +#elif defined (CH32V30x_D8C) + USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ + TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */ + RNG_IRQn = 63, /* RNG global Interrupt */ + SDIO_IRQn = 65, /* SDIO global Interrupt */ + TIM5_IRQn = 66, /* TIM5 global Interrupt */ + SPI3_IRQn = 67, /* SPI3 global Interrupt */ + UART4_IRQn = 68, /* UART4 global Interrupt */ + UART5_IRQn = 69, /* UART5 global Interrupt */ + TIM6_IRQn = 70, /* TIM6 global Interrupt */ + TIM7_IRQn = 71, /* TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 77, /* ETH global Interrupt */ + ETH_WKUP_IRQn = 78, /* ETH WakeUp Interrupt */ + CAN2_TX_IRQn = 79, /* CAN2 TX Interrupts */ + CAN2_RX0_IRQn = 80, /* CAN2 RX0 Interrupts */ + CAN2_RX1_IRQn = 81, /* CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 82, /* CAN2 SCE Interrupt */ + USBFS_IRQn = 83, /* USBFS global Interrupt */ + USBHSWakeup_IRQn = 84, /* USBHS WakeUp Interrupt */ + USBHS_IRQn = 85, /* USBHS global Interrupt */ + DVP_IRQn = 86, /* DVP global Interrupt */ + UART6_IRQn = 87, /* UART6 global Interrupt */ + UART7_IRQn = 88, /* UART7 global Interrupt */ + UART8_IRQn = 89, /* UART8 global Interrupt */ + TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */ + TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */ + TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */ + TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */ + TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */ + TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */ + TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */ + TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */ + DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */ + DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */ + DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */ + DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */ + DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */ + +#endif +} IRQn_Type; + +#define HardFault_IRQn EXC_IRQn +#define ADC1_2_IRQn ADC_IRQn + +#define SysTicK_IRQn SysTick_IRQn +#define OTG_FS_IRQn USBFS_IRQn +#define OTG_FS_IRQHandler USBFS_IRQHandler + +#define USBHD_IRQHandler USBFS_IRQHandler + +#define USBOTG_FS USBFSD +#define USBOTG_H_FS USBFSH + +#include +#include "core_riscv.h" +#include "system_ch32v30x.h" + + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + uint32_t RESERVED0; + __IO uint32_t AUX; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13[5]; + __IO uint16_t DATAR11; + uint16_t RESERVED14; + __IO uint16_t DATAR12; + uint16_t RESERVED15; + __IO uint16_t DATAR13; + uint16_t RESERVED16; + __IO uint16_t DATAR14; + uint16_t RESERVED17; + __IO uint16_t DATAR15; + uint16_t RESERVED18; + __IO uint16_t DATAR16; + uint16_t RESERVED19; + __IO uint16_t DATAR17; + uint16_t RESERVED20; + __IO uint16_t DATAR18; + uint16_t RESERVED21; + __IO uint16_t DATAR19; + uint16_t RESERVED22; + __IO uint16_t DATAR20; + uint16_t RESERVED23; + __IO uint16_t DATAR21; + uint16_t RESERVED24; + __IO uint16_t DATAR22; + uint16_t RESERVED25; + __IO uint16_t DATAR23; + uint16_t RESERVED26; + __IO uint16_t DATAR24; + uint16_t RESERVED27; + __IO uint16_t DATAR25; + uint16_t RESERVED28; + __IO uint16_t DATAR26; + uint16_t RESERVED29; + __IO uint16_t DATAR27; + uint16_t RESERVED30; + __IO uint16_t DATAR28; + uint16_t RESERVED31; + __IO uint16_t DATAR29; + uint16_t RESERVED32; + __IO uint16_t DATAR30; + uint16_t RESERVED33; + __IO uint16_t DATAR31; + uint16_t RESERVED34; + __IO uint16_t DATAR32; + uint16_t RESERVED35; + __IO uint16_t DATAR33; + uint16_t RESERVED36; + __IO uint16_t DATAR34; + uint16_t RESERVED37; + __IO uint16_t DATAR35; + uint16_t RESERVED38; + __IO uint16_t DATAR36; + uint16_t RESERVED39; + __IO uint16_t DATAR37; + uint16_t RESERVED40; + __IO uint16_t DATAR38; + uint16_t RESERVED41; + __IO uint16_t DATAR39; + uint16_t RESERVED42; + __IO uint16_t DATAR40; + uint16_t RESERVED43; + __IO uint16_t DATAR41; + uint16_t RESERVED44; + __IO uint16_t DATAR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/* Controller Area Network TxMailBox */ +typedef struct +{ + __IO uint32_t TXMIR; + __IO uint32_t TXMDTR; + __IO uint32_t TXMDLR; + __IO uint32_t TXMDHR; +} CAN_TxMailBox_TypeDef; + +/* Controller Area Network FIFOMailBox */ +typedef struct +{ + __IO uint32_t RXMIR; + __IO uint32_t RXMDTR; + __IO uint32_t RXMDLR; + __IO uint32_t RXMDHR; +} CAN_FIFOMailBox_TypeDef; + +/* Controller Area Network FilterRegister */ +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/* Controller Area Network */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t STATR; + __IO uint32_t TSTATR; + __IO uint32_t RFIFO0; + __IO uint32_t RFIFO1; + __IO uint32_t INTENR; + __IO uint32_t ERRSR; + __IO uint32_t BTIMR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FCTLR; + __IO uint32_t FMCFGR; + uint32_t RESERVED2; + __IO uint32_t FSCFGR; + uint32_t RESERVED3; + __IO uint32_t FAFIFOR; + uint32_t RESERVED4; + __IO uint32_t FWR; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[28]; +} CAN_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + +/* Digital to Analog Converter */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SWTR; + __IO uint32_t R12BDHR1; + __IO uint32_t L12BDHR1; + __IO uint32_t R8BDHR1; + __IO uint32_t R12BDHR2; + __IO uint32_t L12BDHR2; + __IO uint32_t R8BDHR2; + __IO uint32_t RD12BDHR; + __IO uint32_t LD12BDHR; + __IO uint32_t RD8BDHR; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + +/* DMA Channel Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* FSMC Bank1 Registers */ +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/* FSMC Bank1E Registers */ +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/* FSMC Bank2 Registers */ +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + +/* SDIO Registers */ +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[5]; + __IO uint32_t DCTRL2; + uint32_t RESERVED2[7]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DMACFGR; + uint16_t RESERVED18; + __IO uint16_t DMAADR; + uint16_t RESERVED19; + __IO uint16_t AUX; + uint16_t RESERVED20; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; + __IO uint16_t CTLR4; + uint16_t RESERVED7; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; + uint32_t RESERVED0; + __IO uint32_t EXTEN_CTR2; +} EXTEN_TypeDef; + +/* OPA Registers */ +typedef struct +{ + __IO uint32_t CR; +} OPA_TypeDef; + +/* RNG Registers */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t DR; +} RNG_TypeDef; + +/* DVP Registers */ +typedef struct +{ + __IO uint8_t CR0; + __IO uint8_t CR1; + __IO uint8_t IER; + __IO uint8_t Reserved0; + __IO uint16_t ROW_NUM; + __IO uint16_t COL_NUM; + __IO uint32_t DMA_BUF0; + __IO uint32_t DMA_BUF1; + __IO uint8_t IFR; + __IO uint8_t STATUS; + __IO uint16_t Reserved1; + __IO uint16_t ROW_CNT; + __IO uint16_t Reserved2; + __IO uint16_t HOFFCNT; + __IO uint16_t VST; + __IO uint16_t CAPCNT; + __IO uint16_t VLINE; + __IO uint32_t DR; +} DVP_TypeDef; + +/* USBHS Registers */ +typedef struct +{ + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t ENDP_CONFIG; + __IO uint32_t ENDP_TYPE; + __IO uint32_t BUF_MODE; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_RX_DMA; + __IO uint32_t UEP2_RX_DMA; + __IO uint32_t UEP3_RX_DMA; + __IO uint32_t UEP4_RX_DMA; + __IO uint32_t UEP5_RX_DMA; + __IO uint32_t UEP6_RX_DMA; + __IO uint32_t UEP7_RX_DMA; + __IO uint32_t UEP8_RX_DMA; + __IO uint32_t UEP9_RX_DMA; + __IO uint32_t UEP10_RX_DMA; + __IO uint32_t UEP11_RX_DMA; + __IO uint32_t UEP12_RX_DMA; + __IO uint32_t UEP13_RX_DMA; + __IO uint32_t UEP14_RX_DMA; + __IO uint32_t UEP15_RX_DMA; + __IO uint32_t UEP1_TX_DMA; + __IO uint32_t UEP2_TX_DMA; + __IO uint32_t UEP3_TX_DMA; + __IO uint32_t UEP4_TX_DMA; + __IO uint32_t UEP5_TX_DMA; + __IO uint32_t UEP6_TX_DMA; + __IO uint32_t UEP7_TX_DMA; + __IO uint32_t UEP8_TX_DMA; + __IO uint32_t UEP9_TX_DMA; + __IO uint32_t UEP10_TX_DMA; + __IO uint32_t UEP11_TX_DMA; + __IO uint32_t UEP12_TX_DMA; + __IO uint32_t UEP13_TX_DMA; + __IO uint32_t UEP14_TX_DMA; + __IO uint32_t UEP15_TX_DMA; + __IO uint16_t UEP0_MAX_LEN; + __IO uint16_t RESERVED2; + __IO uint16_t UEP1_MAX_LEN; + __IO uint16_t RESERVED3; + __IO uint16_t UEP2_MAX_LEN; + __IO uint16_t RESERVED4; + __IO uint16_t UEP3_MAX_LEN; + __IO uint16_t RESERVED5; + __IO uint16_t UEP4_MAX_LEN; + __IO uint16_t RESERVED6; + __IO uint16_t UEP5_MAX_LEN; + __IO uint16_t RESERVED7; + __IO uint16_t UEP6_MAX_LEN; + __IO uint16_t RESERVED8; + __IO uint16_t UEP7_MAX_LEN; + __IO uint16_t RESERVED9; + __IO uint16_t UEP8_MAX_LEN; + __IO uint16_t RESERVED10; + __IO uint16_t UEP9_MAX_LEN; + __IO uint16_t RESERVED11; + __IO uint16_t UEP10_MAX_LEN; + __IO uint16_t RESERVED12; + __IO uint16_t UEP11_MAX_LEN; + __IO uint16_t RESERVED13; + __IO uint16_t UEP12_MAX_LEN; + __IO uint16_t RESERVED14; + __IO uint16_t UEP13_MAX_LEN; + __IO uint16_t RESERVED15; + __IO uint16_t UEP14_MAX_LEN; + __IO uint16_t RESERVED16; + __IO uint16_t UEP15_MAX_LEN; + __IO uint16_t RESERVED17; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint16_t UEP8_TX_LEN; + __IO uint8_t UEP8_TX_CTRL; + __IO uint8_t UEP8_RX_CTRL; + __IO uint16_t UEP9_TX_LEN; + __IO uint8_t UEP9_TX_CTRL; + __IO uint8_t UEP9_RX_CTRL; + __IO uint16_t UEP10_TX_LEN; + __IO uint8_t UEP10_TX_CTRL; + __IO uint8_t UEP10_RX_CTRL; + __IO uint16_t UEP11_TX_LEN; + __IO uint8_t UEP11_TX_CTRL; + __IO uint8_t UEP11_RX_CTRL; + __IO uint16_t UEP12_TX_LEN; + __IO uint8_t UEP12_TX_CTRL; + __IO uint8_t UEP12_RX_CTRL; + __IO uint16_t UEP13_TX_LEN; + __IO uint8_t UEP13_TX_CTRL; + __IO uint8_t UEP13_RX_CTRL; + __IO uint16_t UEP14_TX_LEN; + __IO uint8_t UEP14_TX_CTRL; + __IO uint8_t UEP14_RX_CTRL; + __IO uint16_t UEP15_TX_LEN; + __IO uint8_t UEP15_TX_CTRL; + __IO uint8_t UEP15_RX_CTRL; +} USBHSD_TypeDef; + +typedef struct __attribute__((packed)) +{ + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t HOST_EP_CONFIG; + __IO uint32_t HOST_EP_TYPE; + __IO uint32_t RESERVED2; + __IO uint32_t RESERVED3; + __IO uint32_t RESERVED4; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t RESERVED5; + __IO uint32_t RESERVED6; + __IO uint32_t RESERVED7; + __IO uint32_t RESERVED8; + __IO uint32_t RESERVED9; + __IO uint32_t RESERVED10; + __IO uint32_t RESERVED11; + __IO uint32_t RESERVED12; + __IO uint32_t RESERVED13; + __IO uint32_t RESERVED14; + __IO uint32_t RESERVED15; + __IO uint32_t RESERVED16; + __IO uint32_t RESERVED17; + __IO uint32_t RESERVED18; + __IO uint32_t RESERVED19; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t RESERVED20; + __IO uint32_t RESERVED21; + __IO uint32_t RESERVED22; + __IO uint32_t RESERVED23; + __IO uint32_t RESERVED24; + __IO uint32_t RESERVED25; + __IO uint32_t RESERVED26; + __IO uint32_t RESERVED27; + __IO uint32_t RESERVED28; + __IO uint32_t RESERVED29; + __IO uint32_t RESERVED30; + __IO uint32_t RESERVED31; + __IO uint32_t RESERVED32; + __IO uint32_t RESERVED33; + __IO uint16_t HOST_RX_MAX_LEN; + __IO uint16_t RESERVED34; + __IO uint32_t RESERVED35; + __IO uint32_t RESERVED36; + __IO uint32_t RESERVED37; + __IO uint32_t RESERVED38; + __IO uint32_t RESERVED39; + __IO uint32_t RESERVED40; + __IO uint32_t RESERVED41; + __IO uint32_t RESERVED42; + __IO uint32_t RESERVED43; + __IO uint32_t RESERVED44; + __IO uint32_t RESERVED45; + __IO uint32_t RESERVED46; + __IO uint32_t RESERVED47; + __IO uint32_t RESERVED48; + __IO uint32_t RESERVED49; + __IO uint8_t HOST_EP_PID; + __IO uint8_t RESERVED50; + __IO uint8_t RESERVED51; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t RESERVED52; + __IO uint16_t HOST_SPLIT_DATA; +} USBHSH_TypeDef; + + +/* USBOTG_FS Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint32_t Reserve2; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +}USBFSD_TypeDef; + +typedef struct __attribute__((packed)) +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t Reserve2; + __IO uint8_t HOST_EP_MOD; + __IO uint16_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t Reserve6; + __IO uint32_t Reserve7; + __IO uint32_t Reserve8; + __IO uint32_t Reserve9; + __IO uint32_t Reserve10; + __IO uint16_t Reserve11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + __IO uint8_t Reserve12; + __IO uint8_t Reserve13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t Reserve14; + __IO uint32_t Reserve15; + __IO uint32_t Reserve16; + __IO uint32_t Reserve17; + __IO uint32_t Reserve18; + __IO uint32_t Reserve19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +}USBFSH_TypeDef; + +/* Ethernet MAC */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED2[14]; + __IO uint32_t MACCFG0; + uint32_t RESERVED10[25]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + + + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /* FSMC registers base address */ + + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define UART6_BASE (APB1PERIPH_BASE + 0x1800) +#define UART7_BASE (APB1PERIPH_BASE + 0x1C00) +#define UART8_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) +#define SDIO_BASE (APB2PERIPH_BASE + 0x8000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x046C) +#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x0480) +#define DMA2_Channel8_BASE (AHBPERIPH_BASE + 0x0490) +#define DMA2_Channel9_BASE (AHBPERIPH_BASE + 0x04A0) +#define DMA2_Channel10_BASE (AHBPERIPH_BASE + 0x04B0) +#define DMA2_Channel11_BASE (AHBPERIPH_BASE + 0x04C0) +#define DMA2_EXTEN_BASE (AHBPERIPH_BASE + 0x04D0) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define USBHS_BASE (AHBPERIPH_BASE + 0x3400) +#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) +#define OPA_BASE (AHBPERIPH_BASE + 0x3804) +#define RNG_BASE (AHBPERIPH_BASE + 0x3C00) + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define USBFS_BASE ((uint32_t)0x50000000) +#define DVP_BASE ((uint32_t)0x50050000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) + +#define OB_BASE ((uint32_t)0x1FFFF800) +#define FEATURE_SIGN ((uint32_t)0x1FFFF7D0) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define UART6 ((USART_TypeDef *) UART6_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) + +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TKey1 ((ADC_TypeDef *) ADC1_BASE) +#define TKey2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_EXTEN ((DMA_TypeDef *) DMA2_EXTEN_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) +#define DMA2_Channel9 ((DMA_Channel_TypeDef *) DMA2_Channel9_BASE) +#define DMA2_Channel10 ((DMA_Channel_TypeDef *) DMA2_Channel10_BASE) +#define DMA2_Channel11 ((DMA_Channel_TypeDef *) DMA2_Channel11_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define USBHSD ((USBHSD_TypeDef *) USBHS_BASE) +#define USBHSH ((USBHSH_TypeDef *) USBHS_BASE) +#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE) +#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE) +#define EXTEN ((EXTEN_TypeDef *) EXTEN_BASE) +#define OPA ((OPA_TypeDef *) OPA_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) + +#define DVP ((DVP_TypeDef *) DVP_BASE) + +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) + +#define OB ((OB_TypeDef *) OB_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +#define ADC_TKENABLE ((uint32_t)0x01000000) /*TKEY enable*/ +#define ADC_TKITUNE ((uint32_t)0x02000000) +#define ADC_BUFEN ((uint32_t)0x04000000) + +#define ADC_PGA ((uint32_t)0x18000000) +#define ADC_PGA_0 ((uint32_t)0x08000000) +#define ADC_PGA_1 ((uint32_t)0x10000000) +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************** Bit definition for ADC_AUX register ********************/ +#define ADC_SMP_SEL_0 ((uint32_t)0x00000001) /* channel_0 */ +#define ADC_SMP_SEL_1 ((uint32_t)0x00000002) /* channel_1 */ +#define ADC_SMP_SEL_2 ((uint32_t)0x00000004) /* channel_2 */ +#define ADC_SMP_SEL_3 ((uint32_t)0x00000008) /* channel_3 */ +#define ADC_SMP_SEL_4 ((uint32_t)0x00000010) /* channel_4 */ +#define ADC_SMP_SEL_5 ((uint32_t)0x00000020) /* channel_5 */ +#define ADC_SMP_SEL_6 ((uint32_t)0x00000040) /* channel_6 */ +#define ADC_SMP_SEL_7 ((uint32_t)0x00000080) /* channel_7 */ +#define ADC_SMP_SEL_8 ((uint32_t)0x00000100) /* channel_8 */ +#define ADC_SMP_SEL_9 ((uint32_t)0x00000200) /* channel_9 */ +#define ADC_SMP_SEL_10 ((uint32_t)0x00000400) /* channel_10 */ +#define ADC_SMP_SEL_11 ((uint32_t)0x00000800) /* channel_11 */ +#define ADC_SMP_SEL_12 ((uint32_t)0x00001000) /* channel_12 */ +#define ADC_SMP_SEL_13 ((uint32_t)0x00002000) /* channel_13 */ +#define ADC_SMP_SEL_14 ((uint32_t)0x00004000) /* channel_14 */ +#define ADC_SMP_SEL_15 ((uint32_t)0x00008000) /* channel_15 */ +#define ADC_SMP_SEL_16 ((uint32_t)0x00010000) /* channel_16 */ +#define ADC_SMP_SEL_17 ((uint32_t)0x00020000) /* channel_17 */ + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR11 register *******************/ +#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR12 register *******************/ +#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR13 register *******************/ +#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR14 register *******************/ +#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR15 register *******************/ +#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR16 register *******************/ +#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR17 register *******************/ +#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_DATAR18 register ********************/ +#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR19 register *******************/ +#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR20 register *******************/ +#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR21 register *******************/ +#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR22 register *******************/ +#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR23 register *******************/ +#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR24 register *******************/ +#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR25 register *******************/ +#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR26 register *******************/ +#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR27 register *******************/ +#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR28 register *******************/ +#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR29 register *******************/ +#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR30 register *******************/ +#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR31 register *******************/ +#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR32 register *******************/ +#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR33 register *******************/ +#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR34 register *******************/ +#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR35 register *******************/ +#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR36 register *******************/ +#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR37 register *******************/ +#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR38 register *******************/ +#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR39 register *******************/ +#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR40 register *******************/ +#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR41 register *******************/ +#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR42 register *******************/ +#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* Controller Area Network */ +/******************************************************************************/ + +/******************* Bit definition for CAN_CTLR register ********************/ +#define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */ +#define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */ +#define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */ +#define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */ +#define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */ +#define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */ +#define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */ +#define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */ +#define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */ +#define CAN_CTLR_DBF ((uint32_t)0x10000) + +/******************* Bit definition for CAN_STATR register ********************/ +#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ +#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ +#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ +#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ +#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ +#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ +#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ +#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTATR register ********************/ +#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ + +#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFIFO0 register *******************/ +#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ +#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ +#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ +#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFIFO1 register *******************/ +#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ +#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ +#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ +#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTENR register *******************/ +#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ +#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ERRSR register *******************/ +#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ +#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ +#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ + +#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ + +#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ + +/******************* Bit definition for CAN_TTCTLR register ********************/ +#define CAN_TTCTLR_TIMCMV ((uint32_t)0x0000FFFF) +#define CAN_TTCTLR_TIMRST ((uint32_t)0x00010000) +#define CAN_TTCTLR_MODE ((uint32_t)0x00020000) + +/******************* Bit definition for CAN_TTCNT register ********************/ +#define CAN_TTCNT_TIMCNT ((uint32_t)0x0000FFFF) + +/****************** Bit definition for CAN_TXMI0R register ********************/ +#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TXMDT0R register *******************/ +#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/****************** Bit definition for CAN_TXMDL0R register *******************/ +#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/****************** Bit definition for CAN_TXMDH0R register *******************/ +#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI1R register *******************/ +#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT1R register ******************/ +#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL1R register ******************/ +#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH1R register ******************/ +#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI2R register *******************/ +#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT2R register ******************/ +#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL2R register ******************/ +#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH2R register ******************/ +#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI0R register *******************/ +#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT0R register ******************/ +#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL0R register ******************/ +#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH0R register ******************/ +#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI1R register *******************/ +#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT1R register ******************/ +#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL1R register ******************/ +#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH1R register ******************/ +#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_FCTLR register ********************/ +#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ +#define CAN_FCTLR_CAN2SB ((uint16_t)0x3F00) + +/******************* Bit definition for CAN_FMCFGR register *******************/ +#define CAN_FMCFGR_FBM ((uint16_t)0x3FFF) /* Filter Mode */ +#define CAN_FMCFGR_FBM0 ((uint16_t)0x0001) /* Filter Init Mode bit 0 */ +#define CAN_FMCFGR_FBM1 ((uint16_t)0x0002) /* Filter Init Mode bit 1 */ +#define CAN_FMCFGR_FBM2 ((uint16_t)0x0004) /* Filter Init Mode bit 2 */ +#define CAN_FMCFGR_FBM3 ((uint16_t)0x0008) /* Filter Init Mode bit 3 */ +#define CAN_FMCFGR_FBM4 ((uint16_t)0x0010) /* Filter Init Mode bit 4 */ +#define CAN_FMCFGR_FBM5 ((uint16_t)0x0020) /* Filter Init Mode bit 5 */ +#define CAN_FMCFGR_FBM6 ((uint16_t)0x0040) /* Filter Init Mode bit 6 */ +#define CAN_FMCFGR_FBM7 ((uint16_t)0x0080) /* Filter Init Mode bit 7 */ +#define CAN_FMCFGR_FBM8 ((uint16_t)0x0100) /* Filter Init Mode bit 8 */ +#define CAN_FMCFGR_FBM9 ((uint16_t)0x0200) /* Filter Init Mode bit 9 */ +#define CAN_FMCFGR_FBM10 ((uint16_t)0x0400) /* Filter Init Mode bit 10 */ +#define CAN_FMCFGR_FBM11 ((uint16_t)0x0800) /* Filter Init Mode bit 11 */ +#define CAN_FMCFGR_FBM12 ((uint16_t)0x1000) /* Filter Init Mode bit 12 */ +#define CAN_FMCFGR_FBM13 ((uint16_t)0x2000) /* Filter Init Mode bit 13 */ +#define CAN_FMCFGR_FBM14 ((uint16_t)0x4000) /* Filter Init Mode bit 14 */ +#define CAN_FMCFGR_FBM15 ((uint16_t)0x8000) /* Filter Init Mode bit 15 */ +#define CAN_FMCFGR_FBM16 ((uint32_t)0x10000) /* Filter Init Mode bit 16 */ +#define CAN_FMCFGR_FBM17 ((uint32_t)0x20000) /* Filter Init Mode bit 17 */ +#define CAN_FMCFGR_FBM18 ((uint32_t)0x40000) /* Filter Init Mode bit 18 */ +#define CAN_FMCFGR_FBM19 ((uint32_t)0x80000) /* Filter Init Mode bit 19 */ +#define CAN_FMCFGR_FBM20 ((uint32_t)0x100000) /* Filter Init Mode bit 20 */ +#define CAN_FMCFGR_FBM21 ((uint32_t)0x200000) /* Filter Init Mode bit 21 */ +#define CAN_FMCFGR_FBM22 ((uint32_t)0x400000) /* Filter Init Mode bit 22 */ +#define CAN_FMCFGR_FBM23 ((uint32_t)0x800000) /* Filter Init Mode bit 23 */ +#define CAN_FMCFGR_FBM24 ((uint32_t)0x1000000) /* Filter Init Mode bit 24 */ +#define CAN_FMCFGR_FBM25 ((uint32_t)0x2000000) /* Filter Init Mode bit 25 */ +#define CAN_FMCFGR_FBM26 ((uint32_t)0x4000000) /* Filter Init Mode bit 26 */ +#define CAN_FMCFGR_FBM27 ((uint32_t)0x8000000) /* Filter Init Mode bit 27 */ + +/******************* Bit definition for CAN_FSCFGR register *******************/ +#define CAN_FSCFGR_FSC ((uint16_t)0x3FFF) /* Filter Scale Configuration */ +#define CAN_FSCFGR_FSC0 ((uint16_t)0x0001) /* Filter Scale Configuration bit 0 */ +#define CAN_FSCFGR_FSC1 ((uint16_t)0x0002) /* Filter Scale Configuration bit 1 */ +#define CAN_FSCFGR_FSC2 ((uint16_t)0x0004) /* Filter Scale Configuration bit 2 */ +#define CAN_FSCFGR_FSC3 ((uint16_t)0x0008) /* Filter Scale Configuration bit 3 */ +#define CAN_FSCFGR_FSC4 ((uint16_t)0x0010) /* Filter Scale Configuration bit 4 */ +#define CAN_FSCFGR_FSC5 ((uint16_t)0x0020) /* Filter Scale Configuration bit 5 */ +#define CAN_FSCFGR_FSC6 ((uint16_t)0x0040) /* Filter Scale Configuration bit 6 */ +#define CAN_FSCFGR_FSC7 ((uint16_t)0x0080) /* Filter Scale Configuration bit 7 */ +#define CAN_FSCFGR_FSC8 ((uint16_t)0x0100) /* Filter Scale Configuration bit 8 */ +#define CAN_FSCFGR_FSC9 ((uint16_t)0x0200) /* Filter Scale Configuration bit 9 */ +#define CAN_FSCFGR_FSC10 ((uint16_t)0x0400) /* Filter Scale Configuration bit 10 */ +#define CAN_FSCFGR_FSC11 ((uint16_t)0x0800) /* Filter Scale Configuration bit 11 */ +#define CAN_FSCFGR_FSC12 ((uint16_t)0x1000) /* Filter Scale Configuration bit 12 */ +#define CAN_FSCFGR_FSC13 ((uint16_t)0x2000) /* Filter Scale Configuration bit 13 */ +#define CAN_FSCFGR_FSC14 ((uint16_t)0x4000) /* Filter Scale Configuration bit 14 */ +#define CAN_FSCFGR_FSC15 ((uint16_t)0x8000) /* Filter Scale Configuration bit 15 */ +#define CAN_FSCFGR_FSC16 ((uint32_t)0x10000) /* Filter Scale Configuration bit 16 */ +#define CAN_FSCFGR_FSC17 ((uint32_t)0x20000) /* Filter Scale Configuration bit 17 */ +#define CAN_FSCFGR_FSC18 ((uint32_t)0x40000) /* Filter Scale Configuration bit 18 */ +#define CAN_FSCFGR_FSC19 ((uint32_t)0x80000) /* Filter Scale Configuration bit 19 */ +#define CAN_FSCFGR_FSC20 ((uint32_t)0x100000) /* Filter Scale Configuration bit 20 */ +#define CAN_FSCFGR_FSC21 ((uint32_t)0x200000) /* Filter Scale Configuration bit 21 */ +#define CAN_FSCFGR_FSC22 ((uint32_t)0x400000) /* Filter Scale Configuration bit 22 */ +#define CAN_FSCFGR_FSC23 ((uint32_t)0x800000) /* Filter Scale Configuration bit 23 */ +#define CAN_FSCFGR_FSC24 ((uint32_t)0x1000000) /* Filter Scale Configuration bit 24 */ +#define CAN_FSCFGR_FSC25 ((uint32_t)0x2000000) /* Filter Scale Configuration bit 25 */ +#define CAN_FSCFGR_FSC26 ((uint32_t)0x4000000) /* Filter Scale Configuration bit 26 */ +#define CAN_FSCFGR_FSC27 ((uint32_t)0x8000000) /* Filter Scale Configuration bit 27 */ + +/****************** Bit definition for CAN_FAFIFOR register *******************/ +#define CAN_FAFIFOR_FFA ((uint16_t)0x3FFF) /* Filter FIFO Assignment */ +#define CAN_FAFIFOR_FFA0 ((uint16_t)0x0001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FAFIFOR_FFA1 ((uint16_t)0x0002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FAFIFOR_FFA2 ((uint16_t)0x0004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FAFIFOR_FFA3 ((uint16_t)0x0008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FAFIFOR_FFA4 ((uint16_t)0x0010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FAFIFOR_FFA5 ((uint16_t)0x0020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FAFIFOR_FFA6 ((uint16_t)0x0040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FAFIFOR_FFA7 ((uint16_t)0x0080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FAFIFOR_FFA8 ((uint16_t)0x0100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FAFIFOR_FFA9 ((uint16_t)0x0200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FAFIFOR_FFA10 ((uint16_t)0x0400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FAFIFOR_FFA11 ((uint16_t)0x0800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FAFIFOR_FFA12 ((uint16_t)0x1000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FAFIFOR_FFA13 ((uint16_t)0x2000) /* Filter FIFO Assignment for Filter 13 */ +#define CAN_FAFIFOR_FFA14 ((uint32_t)0x4000) /* Filter FIFO Assignment for Filter 14 */ +#define CAN_FAFIFOR_FFA15 ((uint32_t)0x8000) /* Filter FIFO Assignment for Filter 15 */ +#define CAN_FAFIFOR_FFA16 ((uint32_t)0x10000) /* Filter FIFO Assignment for Filter 16 */ +#define CAN_FAFIFOR_FFA17 ((uint32_t)0x20000) /* Filter FIFO Assignment for Filter 17 */ +#define CAN_FAFIFOR_FFA18 ((uint32_t)0x40000) /* Filter FIFO Assignment for Filter 18 */ +#define CAN_FAFIFOR_FFA19 ((uint32_t)0x80000) /* Filter FIFO Assignment for Filter 19 */ +#define CAN_FAFIFOR_FFA20 ((uint32_t)0x100000) /* Filter FIFO Assignment for Filter 20 */ +#define CAN_FAFIFOR_FFA21 ((uint32_t)0x200000) /* Filter FIFO Assignment for Filter 21 */ +#define CAN_FAFIFOR_FFA22 ((uint32_t)0x400000) /* Filter FIFO Assignment for Filter 22 */ +#define CAN_FAFIFOR_FFA23 ((uint32_t)0x800000) /* Filter FIFO Assignment for Filter 23 */ +#define CAN_FAFIFOR_FFA24 ((uint32_t)0x1000000) /* Filter FIFO Assignment for Filter 24 */ +#define CAN_FAFIFOR_FFA25 ((uint32_t)0x2000000) /* Filter FIFO Assignment for Filter 25 */ +#define CAN_FAFIFOR_FFA26 ((uint32_t)0x4000000) /* Filter FIFO Assignment for Filter 26 */ +#define CAN_FAFIFOR_FFA27 ((uint32_t)0x8000000) /* Filter FIFO Assignment for Filter 27 */ + +/******************* Bit definition for CAN_FWR register *******************/ +#define CAN_FWR_FACT ((uint16_t)0x3FFF) /* Filter Active */ +#define CAN_FWR_FACT0 ((uint16_t)0x0001) /* Filter 0 Active */ +#define CAN_FWR_FACT1 ((uint16_t)0x0002) /* Filter 1 Active */ +#define CAN_FWR_FACT2 ((uint16_t)0x0004) /* Filter 2 Active */ +#define CAN_FWR_FACT3 ((uint16_t)0x0008) /* Filter 3 Active */ +#define CAN_FWR_FACT4 ((uint16_t)0x0010) /* Filter 4 Active */ +#define CAN_FWR_FACT5 ((uint16_t)0x0020) /* Filter 5 Active */ +#define CAN_FWR_FACT6 ((uint16_t)0x0040) /* Filter 6 Active */ +#define CAN_FWR_FACT7 ((uint16_t)0x0080) /* Filter 7 Active */ +#define CAN_FWR_FACT8 ((uint16_t)0x0100) /* Filter 8 Active */ +#define CAN_FWR_FACT9 ((uint16_t)0x0200) /* Filter 9 Active */ +#define CAN_FWR_FACT10 ((uint16_t)0x0400) /* Filter 10 Active */ +#define CAN_FWR_FACT11 ((uint16_t)0x0800) /* Filter 11 Active */ +#define CAN_FWR_FACT12 ((uint16_t)0x1000) /* Filter 12 Active */ +#define CAN_FWR_FACT13 ((uint16_t)0x2000) /* Filter 13 Active */ +#define CAN_FWR_FACT14 ((uint16_t)0x4000) /* Filter 14 Active */ +#define CAN_FWR_FACT15 ((uint16_t)0x8000) /* Filter 15 Active */ +#define CAN_FWR_FACT16 ((uint32_t)0x10000) /* Filter 16 Active */ +#define CAN_FWR_FACT17 ((uint32_t)0x20000) /* Filter 17 Active */ +#define CAN_FWR_FACT18 ((uint32_t)0x40000) /* Filter 18 Active */ +#define CAN_FWR_FACT19 ((uint32_t)0x80000) /* Filter 19 Active */ +#define CAN_FWR_FACT20 ((uint32_t)0x100000) /* Filter 20 Active */ +#define CAN_FWR_FACT21 ((uint32_t)0x200000) /* Filter 21 Active */ +#define CAN_FWR_FACT22 ((uint32_t)0x400000) /* Filter 22 Active */ +#define CAN_FWR_FACT23 ((uint32_t)0x800000) /* Filter 23 Active */ +#define CAN_FWR_FACT24 ((uint32_t)0x1000000) /* Filter 24 Active */ +#define CAN_FWR_FACT25 ((uint32_t)0x2000000) /* Filter 25 Active */ +#define CAN_FWR_FACT26 ((uint32_t)0x4000000) /* Filter 26 Active */ +#define CAN_FWR_FACT27 ((uint32_t)0x8000000) /* Filter 27 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F14R1 register ******************/ +#define CAN_F14R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F14R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F14R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F14R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F14R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F14R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F14R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F14R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F14R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F14R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F14R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F14R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F14R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F14R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F14R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F14R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F14R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F14R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F14R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F14R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F14R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F14R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F14R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F14R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F14R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F14R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F14R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F14R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F14R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F14R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F14R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F14R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F15R1 register *******************/ +#define CAN_F15R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F15R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F15R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F15R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F15R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F15R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F15R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F15R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F15R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F15R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F15R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F15R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F15R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F15R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F15R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F15R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F15R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F15R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F15R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F15R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F15R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F15R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F15R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F15R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F15R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F15R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F15R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F15R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F15R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F15R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F15R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F15R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F16R1 register *******************/ +#define CAN_F16R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F16R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F16R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F16R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F16R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F16R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F16R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F16R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F16R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F16R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F16R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F16R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F16R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F16R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F16R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F16R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F16R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F16R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F16R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F16R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F16R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F16R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F16R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F16R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F16R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F16R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F16R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F16R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F16R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F16R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F16R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F16R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F17R1 register *******************/ +#define CAN_F17R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F17R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F17R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F17R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F17R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F17R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F17R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F17R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F17R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F17R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F17R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F17R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F17R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F17R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F17R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F17R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F17R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F17R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F17R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F17R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F17R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F17R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F17R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F17R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F17R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F17R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F17R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F17R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F17R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F17R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F17R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F17R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F18R1 register *******************/ +#define CAN_F18R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F18R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F18R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F18R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F18R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F18R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F18R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F18R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F18R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F18R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F18R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F18R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F18R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F18R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F18R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F18R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F18R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F18R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F18R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F18R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F18R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F18R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F18R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F18R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F18R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F18R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F18R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F18R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F18R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F18R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F18R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F18R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F19R1 register *******************/ +#define CAN_F19R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F19R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F19R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F19R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F19R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F19R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F19R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F19R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F19R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F19R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F19R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F19R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F19R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F19R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F19R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F19R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F19R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F19R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F19R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F19R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F19R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F19R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F19R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F19R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F19R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F19R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F19R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F19R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F19R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F19R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F19R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F19R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F20R1 register *******************/ +#define CAN_F20R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F20R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F20R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F20R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F20R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F20R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F20R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F20R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F20R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F20R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F20R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F20R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F20R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F20R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F20R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F20R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F20R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F20R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F20R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F20R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F20R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F20R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F20R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F20R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F20R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F20R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F20R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F20R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F20R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F20R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F20R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F20R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F21R1 register *******************/ +#define CAN_F21R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F21R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F21R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F21R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F21R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F21R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F21R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F21R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F21R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F21R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F21R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F21R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F21R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F21R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F21R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F21R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F21R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F21R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F21R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F21R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F21R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F21R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F21R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F21R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F21R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F21R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F21R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F21R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F21R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F21R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F21R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F21R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F22R1 register *******************/ +#define CAN_F22R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F22R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F22R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F22R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F22R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F22R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F22R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F22R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F22R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F22R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F22R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F22R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F22R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F22R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F22R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F22R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F22R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F22R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F22R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F22R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F22R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F22R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F22R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F22R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F22R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F22R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F22R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F22R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F22R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F22R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F22R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F22R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F23R1 register ******************/ +#define CAN_F23R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F23R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F23R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F23R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F23R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F23R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F23R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F23R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F23R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F23R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F23R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F23R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F23R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F23R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F23R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F23R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F23R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F23R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F23R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F23R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F23R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F23R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F23R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F23R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F23R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F23R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F23R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F23R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F23R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F23R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F23R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F23R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F24R1 register ******************/ +#define CAN_F24R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F24R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F24R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F24R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F24R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F24R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F24R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F24R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F24R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F24R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F24R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F24R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F24R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F24R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F24R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F24R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F24R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F24R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F24R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F24R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F24R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F24R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F24R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F24R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F24R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F24R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F24R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F24R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F24R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F24R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F24R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F24R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F25R1 register ******************/ +#define CAN_F25R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F25R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F25R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F25R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F25R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F25R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F25R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F25R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F25R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F25R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F25R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F25R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F25R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F25R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F25R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F25R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F25R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F25R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F25R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F25R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F25R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F25R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F25R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F25R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F25R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F25R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F25R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F25R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F25R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F25R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F25R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F25R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F26R1 register ******************/ +#define CAN_F26R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F26R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F26R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F26R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F26R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F26R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F26R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F26R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F26R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F26R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F26R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F26R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F26R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F26R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F26R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F26R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F26R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F26R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F26R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F26R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F26R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F26R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F26R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F26R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F26R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F26R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F26R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F26R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F26R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F26R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F26R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F26R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F27R1 register ******************/ +#define CAN_F27R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F27R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F27R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F27R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F27R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F27R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F27R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F27R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F27R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F27R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F27R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F27R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F27R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F27R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F27R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F27R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F27R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F27R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F27R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F27R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F27R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F27R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F27R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F27R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F27R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F27R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F27R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F27R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F27R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F27R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F27R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F27R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F14R2 register *******************/ +#define CAN_F14R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F14R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F14R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F14R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F14R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F14R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F14R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F14R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F14R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F14R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F14R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F14R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F14R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F14R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F14R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F14R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F14R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F14R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F14R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F14R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F14R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F14R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F14R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F14R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F14R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F14R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F14R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F14R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F14R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F14R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F14R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F14R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F15R2 register *******************/ +#define CAN_F15R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F15R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F15R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F15R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F15R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F15R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F15R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F15R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F15R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F15R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F15R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F15R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F15R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F15R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F15R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F15R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F15R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F15R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F15R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F15R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F15R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F15R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F15R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F15R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F15R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F15R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F15R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F15R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F15R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F15R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F15R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F15R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F16R2 register *******************/ +#define CAN_F16R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F16R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F16R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F16R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F16R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F16R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F16R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F16R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F16R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F16R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F16R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F16R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F16R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F16R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F16R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F16R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F16R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F16R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F16R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F16R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F16R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F16R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F16R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F16R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F16R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F16R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F16R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F16R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F16R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F16R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F16R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F16R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F17R2 register *******************/ +#define CAN_F17R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F17R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F17R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F17R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F17R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F17R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F17R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F17R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F17R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F17R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F17R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F17R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F17R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F17R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F17R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F17R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F17R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F17R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F17R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F17R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F17R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F17R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F17R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F17R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F17R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F17R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F17R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F17R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F17R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F17R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F17R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F17R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F18R2 register *******************/ +#define CAN_F18R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F18R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F18R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F18R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F18R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F18R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F18R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F18R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F18R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F18R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F18R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F18R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F18R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F18R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F18R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F18R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F18R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F18R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F18R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F18R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F18R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F18R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F18R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F18R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F18R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F18R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F18R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F18R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F18R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F18R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F18R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F18R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F19R2 register *******************/ +#define CAN_F19R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F19R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F19R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F19R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F19R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F19R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F19R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F19R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F19R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F19R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F19R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F19R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F19R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F19R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F19R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F19R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F19R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F19R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F19R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F19R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F19R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F19R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F19R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F19R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F19R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F19R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F19R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F19R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F19R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F19R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F19R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F19R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F20R2 register *******************/ +#define CAN_F20R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F20R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F20R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F20R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F20R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F20R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F20R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F20R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F20R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F20R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F20R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F20R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F20R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F20R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F20R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F20R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F20R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F20R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F20R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F20R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F20R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F20R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F20R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F20R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F20R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F20R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F20R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F20R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F20R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F20R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F20R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F20R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F21R2 register *******************/ +#define CAN_F21R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F21R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F21R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F21R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F21R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F21R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F21R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F21R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F21R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F21R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F21R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F21R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F21R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F21R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F21R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F21R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F21R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F21R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F21R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F21R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F21R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F21R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F21R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F21R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F21R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F21R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F21R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F21R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F21R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F21R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F21R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F21R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F22R2 register *******************/ +#define CAN_F22R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F22R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F22R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F22R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F22R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F22R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F22R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F22R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F22R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F22R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F22R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F22R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F22R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F22R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F22R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F22R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F22R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F22R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F22R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F22R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F22R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F22R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F22R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F22R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F22R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F22R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F22R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F22R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F22R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F22R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F22R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F22R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F23R2 register *******************/ +#define CAN_F23R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F23R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F23R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F23R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F23R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F23R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F23R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F23R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F23R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F23R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F23R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F23R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F23R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F23R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F23R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F23R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F23R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F23R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F23R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F23R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F23R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F23R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F23R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F23R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F23R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F23R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F23R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F23R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F23R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F23R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F23R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F23R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F24R2 register ******************/ +#define CAN_F24R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F24R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F24R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F24R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F24R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F24R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F24R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F24R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F24R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F24R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F24R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F24R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F24R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F24R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F24R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F24R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F24R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F24R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F24R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F24R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F24R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F24R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F24R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F24R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F24R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F24R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F24R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F24R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F24R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F24R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F24R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F24R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F25R2 register ******************/ +#define CAN_F25R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F25R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F25R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F25R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F25R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F25R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F25R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F25R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F25R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F25R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F25R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F25R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F25R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F25R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F25R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F25R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F25R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F25R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F25R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F25R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F25R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F25R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F25R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F25R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F25R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F25R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F25R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F25R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F25R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F25R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F25R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F25R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F26R2 register ******************/ +#define CAN_F26R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F26R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F26R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F26R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F26R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F26R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F26R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F26R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F26R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F26R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F26R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F26R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F26R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F26R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F26R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F26R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F26R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F26R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F26R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F26R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F26R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F26R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F26R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F26R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F26R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F26R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F26R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F26R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F26R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F26R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F26R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F26R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F27R2 register ******************/ +#define CAN_F27R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F27R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F27R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F27R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F27R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F27R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F27R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F27R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F27R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F27R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F27R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F27R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F27R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F27R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F27R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F27R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F27R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F27R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F27R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F27R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F27R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F27R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F27R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F27R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F27R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F27R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F27R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F27R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F27R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F27R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F27R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F27R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + +/******************************************************************************/ +/* Digital to Analog Converter */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CTLR register ********************/ +#define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */ +#define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */ +#define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */ + +#define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */ +#define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */ + +#define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */ +#define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */ +#define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */ +#define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */ + +#define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */ +#define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */ +#define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */ + +#define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */ + +#define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTR register ******************/ +#define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */ +#define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */ + +/***************** Bit definition for DAC_R12BDHR1 register ******************/ +#define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR1 register ******************/ +#define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR1 register ******************/ +#define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_R12BDHR2 register ******************/ +#define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR2 register ******************/ +#define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR2 register ******************/ +#define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_RD12BDHR register ******************/ +#define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ +#define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_LD12BDHR register ******************/ +#define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ +#define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_RD8BDHR register ******************/ +#define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */ +#define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + +#define DMA_GIF8 ((uint32_t)0x00000001) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x00000002) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x00000004) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x00000008) /* Channel 8 Transfer Error flag */ +#define DMA_GIF9 ((uint32_t)0x00000010) /* Channel 9 Global interrupt flag */ +#define DMA_TCIF9 ((uint32_t)0x00000020) /* Channel 9 Transfer Complete flag */ +#define DMA_HTIF9 ((uint32_t)0x00000040) /* Channel 9 Half Transfer flag */ +#define DMA_TEIF9 ((uint32_t)0x00000080) /* Channel 9 Transfer Error flag */ +#define DMA_GIF10 ((uint32_t)0x00000100) /* Channel 10 Global interrupt flag */ +#define DMA_TCIF10 ((uint32_t)0x00000200) /* Channel 10 Transfer Complete flag */ +#define DMA_HTIF10 ((uint32_t)0x00000400) /* Channel 10 Half Transfer flag */ +#define DMA_TEIF10 ((uint32_t)0x00000800) /* Channel 10 Transfer Error flag */ +#define DMA_GIF11 ((uint32_t)0x00001000) /* Channel 11 Global interrupt flag */ +#define DMA_TCIF11 ((uint32_t)0x00002000) /* Channel 11 Transfer Complete flag */ +#define DMA_HTIF11 ((uint32_t)0x00004000) /* Channel 11 Half Transfer flag */ +#define DMA_TEIF11 ((uint32_t)0x00008000) /* Channel 11 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ +#define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */ +#define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */ +#define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */ +#define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR8 register ******************/ +#define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR8 register *******************/ +#define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR8 register *******************/ +#define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ +#define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ +#define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ +#define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ +#define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ +#define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ +#define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + + +/******************* Bit definition for FLASH_ACTLR register ******************/ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ +#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEYR_KEY2 ((uint32_t)0xCDEF89AB) + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_WRBSY ((uint8_t)0x02) +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_EHMODS ((uint8_t)0x80) + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */ +#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */ +#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ +#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ +#define FLASH_CTLR_OPTWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FAST_LOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */ +#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */ +#define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */ +#define FLASH_CTLR_PAGE_BER64 ((uint32_t)0x00080000) /* Block Erase 64K */ +#define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */ +#define FLASH_CTLR_RSENACT ((uint32_t)0x00400000) +#define FLASH_CTLR_EHMOD ((uint32_t)0x01000000) +#define FLASH_CTLR_SCKMOD ((uint32_t)0x02000000) + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_RAM_CODE_MOD ((uint16_t)0x0300) +#define FLASH_OBR_RAM_CODE_MOD_BIT1 ((uint16_t)0x0100) +#define FLASH_OBR_RAM_CODE_MOD_BIT2 ((uint16_t)0x0200) + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_MODEKEYR register ******************/ +#define FLASH_MODEKEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ +#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP1 ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP2 ((uint32_t)0x00000020) +#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ + +#define AFIO_PCFR1_ETH_REMAP ((uint32_t)0x00200000) + +#define AFIO_PCFR1_CAN2_REMAP ((uint32_t)0x00400000) + +#define AFIO_PCFR1_MII_RMII_REMAP ((uint32_t)0x00800000) + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + +#define AFIO_PCFR1_SPI3_REMAP ((uint32_t)0x10000000) + +#define AFIO_PCFR1_TIM2ITR1_REMAP ((uint32_t)0x20000000) + +#define AFIO_PCFR1_PTP_PPS_REMAP ((uint32_t)0x40000000) + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin *// + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ + +/****************** Bit definition for AFIO_PCFR2register *******************/ +#define AFIO_PCFR2_TIM8_REMAP ((uint32_t)0x00000004) + +#define AFIO_PCFR2_TIM9_REMAP ((uint32_t)0x00000018) +#define AFIO_PCFR2_TIM9_REMAP_0 ((uint32_t)0x00000008) +#define AFIO_PCFR2_TIM9_REMAP_1 ((uint32_t)0x00000010) + +#define AFIO_PCFR2_TIM9_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_TIM9_REMAP_PARTIALREMAP ((uint32_t)0x00000008) +#define AFIO_PCFR2_TIM9_REMAP_FULLREMAP ((uint32_t)0x00000010) + +#define AFIO_PCFR2_TIM10_REMAP ((uint32_t)0x00000060) +#define AFIO_PCFR2_TIM10_REMAP_0 ((uint32_t)0x00000020) +#define AFIO_PCFR2_TIM10_REMAP_1 ((uint32_t)0x00000040) + +#define AFIO_PCFR2_TIM10_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_TIM10_REMAP_PARTIALREMAP ((uint32_t)0x00000020) +#define AFIO_PCFR2_TIM10_REMAP_FULLREMAP ((uint32_t)0x00000040) + +#define AFIO_PCFR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) + + +#define AFIO_PCFR2_USART4_REMAP ((uint32_t)0x00030000) +#define AFIO_PCFR2_USART4_REMAP_0 ((uint32_t)0x00010000) +#define AFIO_PCFR2_USART4_REMAP_1 ((uint32_t)0x00020000) + +#define AFIO_PCFR2_USART4_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_USART4_REMAP_PARTIALREMAP ((uint32_t)0x00010000) +#define AFIO_PCFR2_USART4_REMAP_FULLREMAP ((uint32_t)0x00020000) + +#define AFIO_PCFR2_USART5_REMAP ((uint32_t)0x000C0000) +#define AFIO_PCFR2_USART5_REMAP_0 ((uint32_t)0x00040000) +#define AFIO_PCFR2_USART5_REMAP_1 ((uint32_t)0x00080000) + +#define AFIO_PCFR2_USART5_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_USART5_REMAP_PARTIALREMAP ((uint32_t)0x00040000) +#define AFIO_PCFR2_USART5_REMAP_FULLREMAP ((uint32_t)0x00080000) + +#define AFIO_PCFR2_USART6_REMAP ((uint32_t)0x00300000) +#define AFIO_PCFR2_USART6_REMAP_0 ((uint32_t)0x00100000) +#define AFIO_PCFR2_USART6_REMAP_1 ((uint32_t)0x00200000) + +#define AFIO_PCFR2_USART6_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_USART6_REMAP_PARTIALREMAP ((uint32_t)0x00100000) +#define AFIO_PCFR2_USART6_REMAP_FULLREMAP ((uint32_t)0x00200000) + +#define AFIO_PCFR2_USART7_REMAP ((uint32_t)0x00C00000) +#define AFIO_PCFR2_USART7_REMAP_0 ((uint32_t)0x00400000) +#define AFIO_PCFR2_USART7_REMAP_1 ((uint32_t)0x00800000) + +#define AFIO_PCFR2_USART7_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_USART7_REMAP_PARTIALREMAP ((uint32_t)0x00400000) +#define AFIO_PCFR2_USART7_REMAP_FULLREMAP ((uint32_t)0x00800000) + +#define AFIO_PCFR2_USART8_REMAP ((uint32_t)0x03000000) +#define AFIO_PCFR2_USART8_REMAP_0 ((uint32_t)0x01000000) +#define AFIO_PCFR2_USART8_REMAP_1 ((uint32_t)0x02000000) + +#define AFIO_PCFR2_USART8_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_USART8_REMAP_PARTIALREMAP ((uint32_t)0x01000000) +#define AFIO_PCFR2_USART8_REMAP_FULLREMAP ((uint32_t)0x02000000) + +#define AFIO_PCFR2_USART1_REMAP ((uint32_t)0x04000000) + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) +#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080) +#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0) +#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0) +#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0) + +#define PWR_CTLR_PLS_2V2 PWR_CTLR_PLS_MODE0 +#define PWR_CTLR_PLS_2V3 PWR_CTLR_PLS_MODE1 +#define PWR_CTLR_PLS_2V4 PWR_CTLR_PLS_MODE2 +#define PWR_CTLR_PLS_2V5 PWR_CTLR_PLS_MODE3 +#define PWR_CTLR_PLS_2V6 PWR_CTLR_PLS_MODE4 +#define PWR_CTLR_PLS_2V7 PWR_CTLR_PLS_MODE5 +#define PWR_CTLR_PLS_2V8 PWR_CTLR_PLS_MODE6 +#define PWR_CTLR_PLS_2V9 PWR_CTLR_PLS_MODE7 + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +#define PWR_CTLR_R2KSTY ((uint32_t)0x10000) +#define PWR_CTLR_R30KSTY ((uint32_t)0x20000) +#define PWR_CTLR_R2KVBAT ((uint32_t)0x40000) +#define PWR_CTLR_R30KVBAT ((uint32_t)0x80000) +#define PWR_CTLR_RAMLV ((uint32_t)0x100000) + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + + + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ +#define RCC_PLL2ON ((uint32_t)0x04000000) +#define RCC_PLL2RDY ((uint32_t)0x08000000) +#define RCC_PLL3ON ((uint32_t)0x10000000) +#define RCC_PLL3RDY ((uint32_t)0x20000000) + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +/* CH32V303x */ +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ +#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ +/* CH32V307x-CH32V305x */ +#define RCC_PLLMULL18_EXTEN ((uint32_t)0x00000000) /* PLL input clock*18 */ +#define RCC_PLLMULL3_EXTEN ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4_EXTEN ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5_EXTEN ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6_EXTEN ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7_EXTEN ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8_EXTEN ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9_EXTEN ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10_EXTEN ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11_EXTEN ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12_EXTEN ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13_EXTEN ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14_EXTEN ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL6_5_EXTEN ((uint32_t)0x00340000) /* PLL input clock*6.5 */ +#define RCC_PLLMULL15_EXTEN ((uint32_t)0x00380000) /* PLL input clock*15 */ +#define RCC_PLLMULL16_EXTEN ((uint32_t)0x003C0000) /* PLL input clock*16 */ + +#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ + +#define RCC_CFGR0_MCO ((uint32_t)0x0F000000) /* MCO[3:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define RCC_MCO_3 ((uint32_t)0x08000000) /* Bit 3 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ +#define RCC_CFGR0_MCO_PLL2 ((uint32_t)0x08000000) +#define RCC_CFGR0_MCO_PLL3D2 ((uint32_t)0x09000000) /* PLL3 clock divided by 2 selected as MCO source */ +#define RCC_CFGR0_MCO_XT1 ((uint32_t)0x0A000000) +#define RCC_CFGR0_MCO_PLL3 ((uint32_t)0x0B000000) + +#define RCC_CFGR0_ETHPRE ((uint32_t)0x10000000) +#define RCC_CFGR0_ADCDUTY ((uint32_t)0x80000000) +#define RCC_CFGR0_ADCDUTY_SEL ((uint32_t)0x40000000) + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_PLL2RDYF ((uint32_t)0x00000020) +#define RCC_PLL3RDYF ((uint32_t)0x00000040) +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_PLL2RDYIE ((uint32_t)0x00002000) +#define RCC_PLL3RDYIE ((uint32_t)0x00004000) +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_PLL2RDYC ((uint32_t)0x00200000) +#define RCC_PLL3RDYC ((uint32_t)0x00400000) +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_IOPERST ((uint32_t)0x00000040) +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_TIM8RST ((uint32_t)0x00002000) +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ +#define RCC_TIM9RST ((uint32_t)0x00080000) +#define RCC_TIM10RST ((uint32_t)0x00100000) + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_TIM5RST ((uint32_t)0x00000008) /* Timer 5 reset */ +#define RCC_TIM6RST ((uint32_t)0x00000010) /* Timer 6 reset */ +#define RCC_TIM7RST ((uint32_t)0x00000020) /* Timer 7 reset */ +#define RCC_USART6RST ((uint32_t)0x00000040) /* USART 2 reset */ +#define RCC_USART7RST ((uint32_t)0x00000080) /* USART 2 reset */ +#define RCC_USART8RST ((uint32_t)0x00000100) /* USART 2 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_SPI3RST ((uint32_t)0x00008000) /* SPI 3 reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_USART4RST ((uint32_t)0x00080000) /* USART 4 reset */ +#define RCC_USART5RST ((uint32_t)0x00100000) /* USART 5 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ +#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ +#define RCC_CAN2RST ((uint32_t)0x04000000) /* CAN2 reset */ +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ +#define RCC_DACRST ((uint32_t)0x20000000) /* DAC reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ +#define RCC_DMA2EN ((uint16_t)0x0002) +#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ +#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ +#define RCC_FSMCEN ((uint16_t)0x0100) +#define RCC_RNGEN ((uint16_t)0x0200) +#define RCC_SDIOEN ((uint16_t)0x0400) +#define RCC_USBHSEN ((uint16_t)0x0800) +#define RCC_OTGFSEN ((uint16_t)0x1000) +#define RCC_DVPEN ((uint16_t)0x2000) +#define RCC_ETHMACEN ((uint16_t)0x4000) +#define RCC_ETHMACTXEN ((uint16_t)0x8000) +#define RCC_ETHMACRXEN ((uint32_t)0x10000) +#define RCC_BLEC ((uint32_t)0x10000) +#define RCC_BLES ((uint32_t)0x20000) + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_IOPEEN ((uint32_t)0x00000040) +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_TIM8EN ((uint32_t)0x00002000) +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ +#define RCC_TIM9EN ((uint32_t)0x00080000) +#define RCC_TIM10EN ((uint32_t)0x00100000) + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_TIM4EN ((uint32_t)0x00000004) +#define RCC_TIM5EN ((uint32_t)0x00000008) +#define RCC_TIM6EN ((uint32_t)0x00000010) +#define RCC_TIM7EN ((uint32_t)0x00000020) +#define RCC_USART6EN ((uint32_t)0x00000040) +#define RCC_USART7EN ((uint32_t)0x00000080) +#define RCC_USART8EN ((uint32_t)0x00000100) +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_SPI2EN ((uint32_t)0x00004000) +#define RCC_SPI3EN ((uint32_t)0x00008000) +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_USART3EN ((uint32_t)0x00040000) +#define RCC_USART4EN ((uint32_t)0x00080000) +#define RCC_USART5EN ((uint32_t)0x00100000) +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ +#define RCC_I2C2EN ((uint32_t)0x00400000) +#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ +#define RCC_CAN1EN ((uint32_t)0x02000000) +#define RCC_CAN2EN ((uint32_t)0x04000000) +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ +#define RCC_DACEN ((uint32_t)0x20000000) + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */ +#define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */ +#define RCC_RTCSEL_HSE ((uint32_t)0x00000300) + +#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************* Bit definition for RCC_AHBRSTR register ********************/ +#define RCC_OTGFSRST ((uint32_t)0x00001000) +#define RCC_DVPRST ((uint32_t)0x00002000) +#define RCC_ETHMACRST ((uint32_t)0x00004000) + +/******************* Bit definition for RCC_CFGR2 register ********************/ +#define RCC_PREDIV1 ((uint32_t)0x0000000F) +#define RCC_PREDIV1_0 ((uint32_t)0x00000001) +#define RCC_PREDIV1_1 ((uint32_t)0x00000002) +#define RCC_PREDIV1_2 ((uint32_t)0x00000004) +#define RCC_PREDIV1_3 ((uint32_t)0x00000008) + +#define RCC_PREDIV2 ((uint32_t)0x000000F0) +#define RCC_PREDIV2_0 ((uint32_t)0x00000010) +#define RCC_PREDIV2_1 ((uint32_t)0x00000020) +#define RCC_PREDIV2_2 ((uint32_t)0x00000040) +#define RCC_PREDIV2_3 ((uint32_t)0x00000080) + +#define RCC_PLL2MUL ((uint32_t)0x00000F00) +#define RCC_PLL2MUL_0 ((uint32_t)0x00000100) +#define RCC_PLL2MUL_1 ((uint32_t)0x00000200) +#define RCC_PLL2MUL_2 ((uint32_t)0x00000400) +#define RCC_PLL2MUL_3 ((uint32_t)0x00000800) + +#define RCC_PLL3MUL ((uint32_t)0x0000F000) +#define RCC_PLL3MUL_0 ((uint32_t)0x00001000) +#define RCC_PLL3MUL_1 ((uint32_t)0x00002000) +#define RCC_PLL3MUL_2 ((uint32_t)0x00004000) +#define RCC_PLL3MUL_3 ((uint32_t)0x00008000) + +#define RCC_PREDIV1SRC ((uint32_t)0x00010000) +#define RCC_I2S2SRC ((uint32_t)0x00020000) +#define RCC_I2S3SRC ((uint32_t)0x00040000) +#define RCC_RNGSRC ((uint32_t)0x00080000) + +#define RCC_ETH1GSRC ((uint32_t)0x00300000) +#define RCC_ETH1GSRC_0 ((uint32_t)0x00100000) +#define RCC_ETH1GSRC_1 ((uint32_t)0x00200000) + +#define RCC_ETH1GEN ((uint32_t)0x00400000) + +#define RCC_USBHSDIV ((uint32_t)0x07000000) +#define RCC_USBHSDIV_0 ((uint32_t)0x01000000) +#define RCC_USBHSDIV_1 ((uint32_t)0x02000000) +#define RCC_USBHSDIV_2 ((uint32_t)0x04000000) + +#define RCC_USBHSPLLSRC ((uint32_t)0x08000000) + +#define RCC_USBHSCLK ((uint32_t)0x30000000) +#define RCC_USBHSCLK_0 ((uint32_t)0x10000000) +#define RCC_USBHSCLK_1 ((uint32_t)0x20000000) + +#define RCC_USBHSPLL ((uint32_t)0x40000000) +#define RCC_USBFSSRC ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_HSE_CAL_CTRL register ********************/ +#define RCC_HSEITRIM ((uint32_t)0x01000000) +#define RCC_HSEFAULT ((uint32_t)0x08000000) + +#define RCC_HSEC ((uint32_t)0x70000000) +#define RCC_HSEC_0 ((uint32_t)0x10000000) +#define RCC_HSEC_1 ((uint32_t)0x20000000) +#define RCC_HSEC_2 ((uint32_t)0x40000000) + +/******************* Bit definition for RCC_LSI32K_TUNE register ********************/ +#define RCC_HTUNE ((uint16_t)0x1000) +#define RCC_LTUNE ((uint16_t)0x0011) + +/******************* Bit definition for RCC_LSI32K_CAL_CFG register ********************/ +#define RCC_CNTVLU ((uint8_t)0x0F) +#define RCC_CNTVLU_0 ((uint8_t)0x01) +#define RCC_CNTVLU_1 ((uint8_t)0x02) +#define RCC_CNTVLU_2 ((uint8_t)0x04) +#define RCC_CNTVLU_3 ((uint8_t)0x08) +#define RCC_HALTMD ((uint8_t)0x10) +#define RCC_WKUPEN ((uint8_t)0x20) +#define RCC_LPEN ((uint8_t)0x40) + +/******************* Bit definition for RCC_LSI32K_CAL_STATR register ********************/ +#define RCC_CNTOV ((uint16_t)0x4000) +#define RCC_IFEND ((uint16_t)0x8000) + +/******************* Bit definition for RCC_LSI32K_CAL_CTRL register ********************/ +#define RCC_CALINTEN ((uint8_t)0x01) +#define RCC_CALEN ((uint8_t)0x02) +#define RCC_HALT ((uint8_t)0x80) + +/******************************************************************************/ +/* RNG */ +/******************************************************************************/ +/******************** Bit definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN ((uint32_t)0x00000004) +#define RNG_CR_IE ((uint32_t)0x00000008) + +/******************** Bit definition for RNG_SR register *******************/ +#define RNG_SR_DRDY ((uint32_t)0x00000001) +#define RNG_SR_CECS ((uint32_t)0x00000002) +#define RNG_SR_SECS ((uint32_t)0x00000004) +#define RNG_SR_CEIS ((uint32_t)0x00000020) +#define RNG_SR_SEIS ((uint32_t)0x00000040) + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCH register *******************/ +#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ + +/****************** Bit definition for SPI_HSCR register *******************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) +#define SPI_HSCR_HSRXEN2 ((uint16_t)0x0004) + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************* Bit definition for TIM_AUX register *******************/ +#define TIM_AUX_CAPCH2_ED ((uint16_t)0x0001) +#define TIM_AUX_CAPCH3_ED ((uint16_t)0x0002) +#define TIM_AUX_CAPCH4_ED ((uint16_t)0x0004) + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ +#define USART_STATR_RX_BUSY ((uint16_t)0x0400) +#define USART_STATR_MS_ERR ((uint16_t)0x0800) + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ +#define USART_CTLR1_M_EXT_0 ((uint16_t)0x4000) +#define USART_CTLR1_M_EXT_1 ((uint16_t)0x8000) +#define USART_CTLR1_M_EXT5 ((uint16_t)0xC000) +#define USART_CTLR1_M_EXT6 ((uint16_t)0x8000) +#define USART_CTLR1_M_EXT7 ((uint16_t)0x4000) + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/****************** Bit definition for USART_CTLR4 register ******************/ +#define USART_CTLR4_MS_ERRIE ((uint16_t)0x0002) +#define USART_CTLR4_CHECK_SEL ((uint16_t)0x000C) +#define USART_CTLR4_CHECK_MARKENABLE ((uint16_t)0x0008) +#define USART_CTLR4_CHECK_APACEENABLE ((uint16_t)0x000C) + +/******************************************************************************/ +/* OPA */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define OPA_EN1 ((uint32_t)0x0001) +#define OPA_MODE1 ((uint32_t)0x0002) +#define OPA_NSEL1 ((uint32_t)0x0004) +#define OPA_PSEL1 ((uint32_t)0x0008) +#define OPA_EN2 ((uint32_t)0x0010) +#define OPA_MODE2 ((uint32_t)0x0020) +#define OPA_NSEL2 ((uint32_t)0x0040) +#define OPA_PSEL2 ((uint32_t)0x0080) +#define OPA_EN3 ((uint32_t)0x0100) +#define OPA_MODE3 ((uint32_t)0x0200) +#define OPA_NSEL3 ((uint32_t)0x0400) +#define OPA_PSEL3 ((uint32_t)0x0800) +#define OPA_EN4 ((uint32_t)0x1000) +#define OPA_MODE4 ((uint32_t)0x2000) +#define OPA_NSEL4 ((uint32_t)0x4000) +#define OPA_PSEL4 ((uint32_t)0x8000) + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced CTLR1 register *****************************/ +#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */ +#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */ +#define EXTEN_ETH_10M_EN ((uint32_t)0x00000004) /* Bit 2 */ +#define EXTEN_ETH_RGMII_SEL ((uint32_t)0x00000008) /* Bit 3 */ +#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + +#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */ +#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ +#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define EXTEN_LDO_TRIM ((uint32_t)0x00000C00) /* LDO_TRIM[1:0] bits */ +#define EXTEN_LDO_TRIM0 ((uint32_t)0x00000400) /* Bit 0 */ +#define EXTEN_LDO_TRIM1 ((uint32_t)0x00000800) /* Bit 1 */ +#define EXTEN_HSEKPLP ((uint32_t)0x00001000) + +/**************************** Enhanced CTLR2 register *****************************/ +#define EXTEN_CTLR2_OPA1_HSMD ((uint32_t)0x00000001) +#define EXTEN_CTLR2_OPA2_HSMD ((uint32_t)0x00000002) +#define EXTEN_CTLR2_OPA3_HSMD ((uint32_t)0x00000004) +#define EXTEN_CTLR2_OPA4_HSMD ((uint32_t)0x00000008) + +/**************************** Enhanced FEATURE_SIGN register *****************************/ + +#define FEATURE_SIGN_VLEVEL ((uint32_t)0x00000001) + +/******************************************************************************/ +/* DVP */ +/******************************************************************************/ + +/******************* Bit definition for DVP_CR0 register ********************/ +#define RB_DVP_ENABLE 0x01 // RW, DVP enable +#define RB_DVP_V_POLAR 0x02 // RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_H_POLAR 0x04 // RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_P_POLAR 0x08 // RW, DVP PCLK polarity control: 1 = invert, 0 = not invert +#define RB_DVP_MSK_DAT_MOD 0x30 +#define RB_DVP_D8_MOD 0x00 // RW, DVP 8bits data mode +#define RB_DVP_D10_MOD 0x10 // RW, DVP 10bits data mode +#define RB_DVP_D12_MOD 0x20 // RW, DVP 12bits data mode +#define RB_DVP_JPEG 0x40 // RW, DVP JPEG mode + +/******************* Bit definition for DVP_CR1 register ********************/ +#define RB_DVP_DMA_EN 0x01 // RW, DVP dma enable +#define RB_DVP_ALL_CLR 0x02 // RW, DVP all clear, high action +#define RB_DVP_RCV_CLR 0x04 // RW, DVP receive logic clear, high action +#define RB_DVP_BUF_TOG 0x08 // RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0 +#define RB_DVP_CM 0x10 // RW, DVP capture mode +#define RB_DVP_CROP 0x20 // RW, DVP Crop feature enable +#define RB_DVP_FCRC 0xC0 // RW, DVP frame capture rate control: +#define DVP_RATE_100P 0x00 //00 = every frame captured (100%) +#define DVP_RATE_50P 0x40 //01 = every alternate frame captured (50%) +#define DVP_RATE_25P 0x80 //10 = one frame in four frame captured (25%) + +/******************* Bit definition for DVP_IER register ********************/ +#define RB_DVP_IE_STR_FRM 0x01 // RW, DVP frame start interrupt enable +#define RB_DVP_IE_ROW_DONE 0x02 // RW, DVP row received done interrupt enable +#define RB_DVP_IE_FRM_DONE 0x04 // RW, DVP frame received done interrupt enable +#define RB_DVP_IE_FIFO_OV 0x08 // RW, DVP receive fifo overflow interrupt enable +#define RB_DVP_IE_STP_FRM 0x10 // RW, DVP frame stop interrupt enable + +/******************* Bit definition for DVP_IFR register ********************/ +#define RB_DVP_IF_STR_FRM 0x01 // RW1, interrupt flag for DVP frame start +#define RB_DVP_IF_ROW_DONE 0x02 // RW1, interrupt flag for DVP row receive done +#define RB_DVP_IF_FRM_DONE 0x04 // RW1, interrupt flag for DVP frame receive done +#define RB_DVP_IF_FIFO_OV 0x08 // RW1, interrupt flag for DVP receive fifo overflow +#define RB_DVP_IF_STP_FRM 0x10 // RW1, interrupt flag for DVP frame stop + +/******************* Bit definition for DVP_STATUS register ********************/ +#define RB_DVP_FIFO_RDY 0x01 // RO, DVP receive fifo ready +#define RB_DVP_FIFO_FULL 0x02 // RO, DVP receive fifo full +#define RB_DVP_FIFO_OV 0x04 // RO, DVP receive fifo overflow +#define RB_DVP_MSK_FIFO_CNT 0x70 // RO, DVP receive fifo count + +/******************* Bit definition for DVP_ROW_CNT register ********************/ +#define RB_DVP_ROW_CNT ((uint16_t)0xFF + +/******************* Bit definition for DVP_HOFFCNT register ********************/ +#define RB_DVP_HOFFCNT ((uint16_t)0xFF + +/******************* Bit definition for DVP_VST register ********************/ +#define RB_DVP_VST ((uint16_t)0xFF + +/******************* Bit definition for DVP_CAPCNT register ********************/ +#define RB_DVP_CAPCNT ((uint16_t)0xFF + +/******************* Bit definition for DVP_VLINE register ********************/ +#define RB_DVP_VLINE ((uint16_t)0xFF + +/******************* Bit definition for DVP_DR register ********************/ +#define RB_DVP_DR ((uint16_t)0xFF + +/******************************************************************************/ +/* TKEY */ +/******************************************************************************/ + +/******************* Bit definition for TKEY_CHARGE1 register *******************/ +#define TKEY_CHARGE1_TKCG10 ((uint32_t)0x0007) +#define TKEY_CHARGE1_TKCG10_1C5 ((uint32_t)0x0000) +#define TKEY_CHARGE1_TKCG10_7C5 ((uint32_t)0x0001) +#define TKEY_CHARGE1_TKCG10_13C5 ((uint32_t)0x0002) +#define TKEY_CHARGE1_TKCG10_28C5 ((uint32_t)0x0003) +#define TKEY_CHARGE1_TKCG10_41C5 ((uint32_t)0x0004) +#define TKEY_CHARGE1_TKCG10_55C5 ((uint32_t)0x0005) +#define TKEY_CHARGE1_TKCG10_71C5 ((uint32_t)0x0006) +#define TKEY_CHARGE1_TKCG10_239C5 ((uint32_t)0x0007) + +#define TKEY_CHARGE1_TKCG11 ((uint32_t)0x0038) +#define TKEY_CHARGE1_TKCG11_1C5 ((uint32_t)0x0000) +#define TKEY_CHARGE1_TKCG11_7C5 ((uint32_t)0x0008) +#define TKEY_CHARGE1_TKCG11_13C5 ((uint32_t)0x0010) +#define TKEY_CHARGE1_TKCG11_28C5 ((uint32_t)0x0018) +#define TKEY_CHARGE1_TKCG11_41C5 ((uint32_t)0x0020) +#define TKEY_CHARGE1_TKCG11_55C5 ((uint32_t)0x0028) +#define TKEY_CHARGE1_TKCG11_71C5 ((uint32_t)0x0030) +#define TKEY_CHARGE1_TKCG11_239C5 ((uint32_t)0x0038) + +#define TKEY_CHARGE1_TKCG12 ((uint32_t)0x01C0) +#define TKEY_CHARGE1_TKCG12_1C5 ((uint32_t)0x0000) +#define TKEY_CHARGE1_TKCG12_7C5 ((uint32_t)0x0040) +#define TKEY_CHARGE1_TKCG12_13C5 ((uint32_t)0x0080) +#define TKEY_CHARGE1_TKCG12_28C5 ((uint32_t)0x00C0) +#define TKEY_CHARGE1_TKCG12_41C5 ((uint32_t)0x0100) +#define TKEY_CHARGE1_TKCG12_55C5 ((uint32_t)0x0140) +#define TKEY_CHARGE1_TKCG12_71C5 ((uint32_t)0x0180) +#define TKEY_CHARGE1_TKCG12_239C5 ((uint32_t)0x01C0) + +#define TKEY_CHARGE1_TKCG13 ((uint32_t)0x0E00) +#define TKEY_CHARGE1_TKCG13_1C5 ((uint32_t)0x0000) +#define TKEY_CHARGE1_TKCG13_7C5 ((uint32_t)0x0200) +#define TKEY_CHARGE1_TKCG13_13C5 ((uint32_t)0x0400) +#define TKEY_CHARGE1_TKCG13_28C5 ((uint32_t)0x0600) +#define TKEY_CHARGE1_TKCG13_41C5 ((uint32_t)0x0800) +#define TKEY_CHARGE1_TKCG13_55C5 ((uint32_t)0x0A00) +#define TKEY_CHARGE1_TKCG13_71C5 ((uint32_t)0x0C00) +#define TKEY_CHARGE1_TKCG13_239C5 ((uint32_t)0x0E00) + +#define TKEY_CHARGE1_TKCG14 ((uint32_t)0x7000) + +#define TKEY_CHARGE1_TKCG15 ((uint32_t)0x38000) +#define TKEY_CHARGE1_TKCG16 ((uint32_t)0x1C0000) +#define TKEY_CHARGE1_TKCG17 ((uint32_t)0xE00000) + + +#include "ch32v30x_conf.h" + + +#ifdef __cplusplus +} +#endif + +#endif + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_adc.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_adc.h index b0034ed..b906638 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_adc.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_adc.h @@ -1,230 +1,230 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_adc.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* ADC firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_ADC_H -#define __CH32V30x_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - - -/* ADC Init structure definition */ -typedef struct -{ - uint32_t ADC_Mode; /* Configures the ADC to operate in independent or - dual mode. - This parameter can be a value of @ref ADC_mode */ - - FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in - Scan (multichannels) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ - - uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. - This parameter can be a value of @ref ADC_OutputBuffer */ - - uint32_t ADC_Pga; /* Specifies the PGA gain multiple. - This parameter can be a value of @ref ADC_Pga */ -}ADC_InitTypeDef; - -/* ADC_mode */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) -#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) -#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) -#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) -#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) -#define ADC_Mode_RegSimult ((uint32_t)0x00060000) -#define ADC_Mode_FastInterl ((uint32_t)0x00070000) -#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) -#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) - -/* ADC_external_trigger_sources_for_regular_channels_conversion */ -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) - -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) - -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) - - -/* ADC_data_align */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) - -/* ADC_channels */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) - -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) - -/*ADC_output_buffer*/ -#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) -#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) - -/*ADC_pga*/ -#define ADC_Pga_1 ((uint32_t)0x00000000) -#define ADC_Pga_4 ((uint32_t)0x08000000) -#define ADC_Pga_16 ((uint32_t)0x10000000) -#define ADC_Pga_64 ((uint32_t)0x18000000) - -/* ADC_sampling_time */ -#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) -#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) -#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) -#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) -#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) -#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) -#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) -#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) - -/* ADC_external_trigger_sources_for_injected_channels_conversion */ -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) -#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) - -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) - -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) - - -/* ADC_injected_channel_selection */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) - -/* ADC_analog_watchdog_selection */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -/* ADC_interrupts_definition */ -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) - -/* ADC_flags_definition */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) - - -void ADC_DeInit(ADC_TypeDef* ADCx); -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -void ADC_ResetCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_StartCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetDualModeConversionValue(void); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); -s32 TempSensor_Volt_To_Temper(s32 Value); -void ADC_BufferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -int16_t Get_CalibrationValue(ADC_TypeDef* ADCx); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_adc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* ADC firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_ADC_H +#define __CH32V30x_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ + + uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. + This parameter can be a value of @ref ADC_OutputBuffer */ + + uint32_t ADC_Pga; /* Specifies the PGA gain multiple. + This parameter can be a value of @ref ADC_Pga */ +}ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) + + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +/*ADC_output_buffer*/ +#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) +#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) + +/*ADC_pga*/ +#define ADC_Pga_1 ((uint32_t)0x00000000) +#define ADC_Pga_4 ((uint32_t)0x08000000) +#define ADC_Pga_16 ((uint32_t)0x10000000) +#define ADC_Pga_64 ((uint32_t)0x18000000) + +/* ADC_sampling_time */ +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) + + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + + +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); +s32 TempSensor_Volt_To_Temper(s32 Value); +void ADC_BufferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +int16_t Get_CalibrationValue(ADC_TypeDef* ADCx); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_bkp.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_bkp.h index 898add4..83dab7a 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_bkp.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_bkp.h @@ -1,99 +1,99 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_bkp.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* BKP firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_BKP_H -#define __CH32V30x_BKP_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* Tamper_Pin_active_level */ -#define BKP_TamperPinLevel_High ((uint16_t)0x0000) -#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) - -/* RTC_output_source_to_output_on_the_Tamper_pin */ -#define BKP_RTCOutputSource_None ((uint16_t)0x0000) -#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) -#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) -#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) - -/* Data_Backup_Register */ -#define BKP_DR1 ((uint16_t)0x0004) -#define BKP_DR2 ((uint16_t)0x0008) -#define BKP_DR3 ((uint16_t)0x000C) -#define BKP_DR4 ((uint16_t)0x0010) -#define BKP_DR5 ((uint16_t)0x0014) -#define BKP_DR6 ((uint16_t)0x0018) -#define BKP_DR7 ((uint16_t)0x001C) -#define BKP_DR8 ((uint16_t)0x0020) -#define BKP_DR9 ((uint16_t)0x0024) -#define BKP_DR10 ((uint16_t)0x0028) -#define BKP_DR11 ((uint16_t)0x0040) -#define BKP_DR12 ((uint16_t)0x0044) -#define BKP_DR13 ((uint16_t)0x0048) -#define BKP_DR14 ((uint16_t)0x004C) -#define BKP_DR15 ((uint16_t)0x0050) -#define BKP_DR16 ((uint16_t)0x0054) -#define BKP_DR17 ((uint16_t)0x0058) -#define BKP_DR18 ((uint16_t)0x005C) -#define BKP_DR19 ((uint16_t)0x0060) -#define BKP_DR20 ((uint16_t)0x0064) -#define BKP_DR21 ((uint16_t)0x0068) -#define BKP_DR22 ((uint16_t)0x006C) -#define BKP_DR23 ((uint16_t)0x0070) -#define BKP_DR24 ((uint16_t)0x0074) -#define BKP_DR25 ((uint16_t)0x0078) -#define BKP_DR26 ((uint16_t)0x007C) -#define BKP_DR27 ((uint16_t)0x0080) -#define BKP_DR28 ((uint16_t)0x0084) -#define BKP_DR29 ((uint16_t)0x0088) -#define BKP_DR30 ((uint16_t)0x008C) -#define BKP_DR31 ((uint16_t)0x0090) -#define BKP_DR32 ((uint16_t)0x0094) -#define BKP_DR33 ((uint16_t)0x0098) -#define BKP_DR34 ((uint16_t)0x009C) -#define BKP_DR35 ((uint16_t)0x00A0) -#define BKP_DR36 ((uint16_t)0x00A4) -#define BKP_DR37 ((uint16_t)0x00A8) -#define BKP_DR38 ((uint16_t)0x00AC) -#define BKP_DR39 ((uint16_t)0x00B0) -#define BKP_DR40 ((uint16_t)0x00B4) -#define BKP_DR41 ((uint16_t)0x00B8) -#define BKP_DR42 ((uint16_t)0x00BC) - - -void BKP_DeInit(void); -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); -void BKP_TamperPinCmd(FunctionalState NewState); -void BKP_ITConfig(FunctionalState NewState); -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); -FlagStatus BKP_GetFlagStatus(void); -void BKP_ClearFlag(void); -ITStatus BKP_GetITStatus(void); -void BKP_ClearITPendingBit(void); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_bkp.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* BKP firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_BKP_H +#define __CH32V30x_BKP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* Tamper_Pin_active_level */ +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) + +/* RTC_output_source_to_output_on_the_Tamper_pin */ +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) + +/* Data_Backup_Register */ +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_can.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_can.h index 21f7bf0..a2bb731 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_can.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_can.h @@ -1,376 +1,376 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_can.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* CAN firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_CAN_H -#define __CH32V30x_CAN_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* CAN init structure definition */ -typedef struct -{ - uint16_t CAN_Prescaler; /* Specifies the length of a time quantum. - It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /* Specifies the CAN operating mode. - This parameter can be a value of - @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /* Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of - @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit - Segment 2. - This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /* Enable or disable the time triggered - communication mode. This parameter can be set - either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off - management. This parameter can be set either - to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or - DISABLE. */ - - FunctionalState CAN_NART; /* Enable or disable the no-automatic - retransmission mode. This parameter can be - set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE - or DISABLE. */ - - FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE - or DISABLE. */ -} CAN_InitTypeDef; - -/* CAN filter init structure definition */ -typedef struct -{ - uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /* Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /* Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/* CAN Tx message structure definition */ -typedef struct -{ - uint32_t StdId; /* Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /* Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /* Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /* Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /* Specifies the length of the frame that will be - transmitted. This parameter can be a value between - 0 to 8 */ - - uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ -} CanTxMsg; - -/* CAN Rx message structure definition */ -typedef struct -{ - uint32_t StdId; /* Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /* Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /* Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /* Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /* Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t FMI; /* Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanRxMsg; - -/* CAN_sleep_constants */ -#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */ -#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */ - -/* CAN_Mode */ -#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */ - -/* CAN_Operating_Mode */ -#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */ -#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */ -#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */ - -/* CAN_Mode_Status */ -#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */ -#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */ - -/* CAN_synchronisation_jump_width */ -#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ - -/* CAN_time_quantum_in_bit_segment_1 */ -#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ - -/* CAN_time_quantum_in_bit_segment_2 */ -#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ - -/* CAN_filter_mode */ -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */ - -/* CAN_filter_scale */ -#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */ - -/* CAN_filter_FIFO */ -#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */ -#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */ - -/* CAN_identifier_type */ -#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */ -#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */ - -/* CAN_remote_transmission_request */ -#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */ -#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */ - -/* CAN_transmit_constants */ -#define CAN_TxStatus_Failed ((uint8_t)0x00)/* CAN transmission failed */ -#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */ -#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */ -#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ - -/* CAN_receive_FIFO_number_constants */ -#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */ - -/* CAN_sleep_constants */ -#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */ -#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */ - -/* CAN_wake_up_constants */ -#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */ -#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */ - -/* CAN_Error_Code_constants */ -#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */ -#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */ -#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */ -#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */ -#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */ -#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */ -#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */ -#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */ - - -/* CAN_flags */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - * and CAN_ClearFlag() functions. - * If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. -*/ -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */ - -/* Receive Flags */ -#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */ -#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */ -#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */ -/* Note: - *When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. - *In this case the SLAK bit can be polled. -*/ - -/* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */ -#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */ - - -/* CAN_interrupts */ -#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/ - -/* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/ -#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/ - -/* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/ -#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/ -#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/ -#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/ -#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/ - -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME - -/* CAN_Legacy */ -#define CANINITFAILED CAN_InitStatus_Failed -#define CANINITOK CAN_InitStatus_Success -#define CAN_FilterFIFO0 CAN_Filter_FIFO0 -#define CAN_FilterFIFO1 CAN_Filter_FIFO1 -#define CAN_ID_STD CAN_Id_Standard -#define CAN_ID_EXT CAN_Id_Extended -#define CAN_RTR_DATA CAN_RTR_Data -#define CAN_RTR_REMOTE CAN_RTR_Remote -#define CANTXFAILE CAN_TxStatus_Failed -#define CANTXOK CAN_TxStatus_Ok -#define CANTXPENDING CAN_TxStatus_Pending -#define CAN_NO_MB CAN_TxStatus_NoMailBox -#define CANSLEEPFAILED CAN_Sleep_Failed -#define CANSLEEPOK CAN_Sleep_Ok -#define CANWAKEUPFAILED CAN_WakeUp_Failed -#define CANWAKEUPOK CAN_WakeUp_Ok - - -void CAN_DeInit(CAN_TypeDef* CANx); -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); -uint8_t CAN_Sleep(CAN_TypeDef* CANx); -uint8_t CAN_WakeUp(CAN_TypeDef* CANx); -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_can.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* CAN firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_CAN_H +#define __CH32V30x_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* CAN init structure definition */ +typedef struct +{ + uint16_t CAN_Prescaler; /* Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /* Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /* Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /* Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CAN_NART; /* Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitTypeDef; + +/* CAN filter init structure definition */ +typedef struct +{ + uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /* Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /* Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/* CAN Tx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/* CAN Rx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /* Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/* CAN_sleep_constants */ +#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */ + +/* CAN_Mode */ +#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */ + +/* CAN_Operating_Mode */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */ + +/* CAN_Mode_Status */ +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */ + +/* CAN_synchronisation_jump_width */ +#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ + +/* CAN_time_quantum_in_bit_segment_1 */ +#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_time_quantum_in_bit_segment_2 */ +#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ + +/* CAN_filter_mode */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */ + +/* CAN_filter_scale */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */ + +/* CAN_filter_FIFO */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */ + +/* CAN_identifier_type */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */ + +/* CAN_remote_transmission_request */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */ + +/* CAN_transmit_constants */ +#define CAN_TxStatus_Failed ((uint8_t)0x00)/* CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ + +/* CAN_receive_FIFO_number_constants */ +#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */ + +/* CAN_sleep_constants */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */ + +/* CAN_wake_up_constants */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */ + +/* CAN_Error_Code_constants */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */ + + +/* CAN_flags */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + * and CAN_ClearFlag() functions. + * If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. +*/ +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */ +/* Note: + *When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + *In this case the SLAK bit can be polled. +*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */ + + +/* CAN_interrupts */ +#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + +/* CAN_Legacy */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok + + +void CAN_DeInit(CAN_TypeDef* CANx); +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_crc.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_crc.h index 026378f..f032f9f 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_crc.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_crc.h @@ -1,39 +1,39 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_crc.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* CRC firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_CRC_H -#define __CH32V30x_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_crc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* CRC firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_CRC_H +#define __CH32V30x_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dac.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dac.h index ae7d7a8..0c6a79e 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dac.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dac.h @@ -1,122 +1,122 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_dac.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* DAC firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_DAC_H -#define __CH32V30x_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* DAC Init structure definition */ -typedef struct -{ - uint32_t DAC_Trigger; /* Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /* Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /* Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /* Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - - -/* DAC_trigger_selection */ -#define DAC_Trigger_None ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel - only in High-density devices*/ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */ - -/* DAC_wave_generation */ -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) - - -/* DAC_lfsrunmask_triangleamplitude */ -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */ - -/* DAC_output_buffer */ -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) - -/* DAC_Channel_selection */ -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) - -/* DAC_data_alignment */ -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) - -/* DAC_wave_generation */ -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) - - -void DAC_DeInit(void); -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); - -#ifdef __cplusplus -} -#endif - -#endif - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dac.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DAC firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_DAC_H +#define __CH32V30x_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* DAC Init structure definition */ +typedef struct +{ + uint32_t DAC_Trigger; /* Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /* Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /* Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /* Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + + +/* DAC_trigger_selection */ +#define DAC_Trigger_None ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel + only in High-density devices*/ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */ + +/* DAC_wave_generation */ +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) + + +/* DAC_lfsrunmask_triangleamplitude */ +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */ + +/* DAC_output_buffer */ +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) + +/* DAC_Channel_selection */ +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) + +/* DAC_data_alignment */ +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) + +/* DAC_wave_generation */ +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) + + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dbgmcu.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dbgmcu.h index fbb0ff0..2cffd3f 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dbgmcu.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dbgmcu.h @@ -1,60 +1,60 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_dbgmcu.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* DBGMCU firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_DBGMCU_H -#define __CH32V30x_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) -#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) -#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) -#define DBGMCU_TIM5_STOP ((uint32_t)0x00010000) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00020000) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00040000) -#define DBGMCU_TIM8_STOP ((uint32_t)0x00080000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) -#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) -#define DBGMCU_TIM9_STOP ((uint32_t)0x00400000) -#define DBGMCU_TIM10_STOP ((uint32_t)0x00800000) - -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -uint32_t __get_DEBUG_CR(void); -void __set_DEBUG_CR(uint32_t value); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -uint32_t DBGMCU_GetCHIPID( void ); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dbgmcu.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DBGMCU firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_DBGMCU_H +#define __CH32V30x_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00010000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00080000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) +#define DBGMCU_TIM9_STOP ((uint32_t)0x00400000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x00800000) + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +uint32_t __get_DEBUG_CR(void); +void __set_DEBUG_CR(uint32_t value); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +uint32_t DBGMCU_GetCHIPID( void ); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dma.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dma.h index 848e9fc..5c25494 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dma.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dma.h @@ -1,270 +1,270 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_dma.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* DMA firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_DMA_H -#define __CH32V30x_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* DMA Init structure definition */ -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode. - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -}DMA_InitTypeDef; - -/* DMA_data_transfer_direction */ -#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) - -/* DMA_peripheral_incremented_mode */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) - -/* DMA_memory_incremented_mode */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) - -/* DMA_peripheral_data_size */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) - -/* DMA_memory_data_size */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) - -/* DMA_circular_normal_mode */ -#define DMA_Mode_Circular ((uint32_t)0x00000020) -#define DMA_Mode_Normal ((uint32_t)0x00000000) - -/* DMA_priority_level */ -#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) -#define DMA_Priority_High ((uint32_t)0x00002000) -#define DMA_Priority_Medium ((uint32_t)0x00001000) -#define DMA_Priority_Low ((uint32_t)0x00000000) - -/* DMA_memory_to_memory */ -#define DMA_M2M_Enable ((uint32_t)0x00004000) -#define DMA_M2M_Disable ((uint32_t)0x00000000) - -/* DMA_interrupts_definition */ -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) - -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) - -#define DMA2_IT_GL1 ((uint32_t)0x10000001) -#define DMA2_IT_TC1 ((uint32_t)0x10000002) -#define DMA2_IT_HT1 ((uint32_t)0x10000004) -#define DMA2_IT_TE1 ((uint32_t)0x10000008) -#define DMA2_IT_GL2 ((uint32_t)0x10000010) -#define DMA2_IT_TC2 ((uint32_t)0x10000020) -#define DMA2_IT_HT2 ((uint32_t)0x10000040) -#define DMA2_IT_TE2 ((uint32_t)0x10000080) -#define DMA2_IT_GL3 ((uint32_t)0x10000100) -#define DMA2_IT_TC3 ((uint32_t)0x10000200) -#define DMA2_IT_HT3 ((uint32_t)0x10000400) -#define DMA2_IT_TE3 ((uint32_t)0x10000800) -#define DMA2_IT_GL4 ((uint32_t)0x10001000) -#define DMA2_IT_TC4 ((uint32_t)0x10002000) -#define DMA2_IT_HT4 ((uint32_t)0x10004000) -#define DMA2_IT_TE4 ((uint32_t)0x10008000) -#define DMA2_IT_GL5 ((uint32_t)0x10010000) -#define DMA2_IT_TC5 ((uint32_t)0x10020000) -#define DMA2_IT_HT5 ((uint32_t)0x10040000) -#define DMA2_IT_TE5 ((uint32_t)0x10080000) -#define DMA2_IT_GL6 ((uint32_t)0x10100000) -#define DMA2_IT_TC6 ((uint32_t)0x10200000) -#define DMA2_IT_HT6 ((uint32_t)0x10400000) -#define DMA2_IT_TE6 ((uint32_t)0x10800000) -#define DMA2_IT_GL7 ((uint32_t)0x11000000) -#define DMA2_IT_TC7 ((uint32_t)0x12000000) -#define DMA2_IT_HT7 ((uint32_t)0x14000000) -#define DMA2_IT_TE7 ((uint32_t)0x18000000) - -#define DMA2_IT_GL8 ((uint32_t)0x20000001) -#define DMA2_IT_TC8 ((uint32_t)0x20000002) -#define DMA2_IT_HT8 ((uint32_t)0x20000004) -#define DMA2_IT_TE8 ((uint32_t)0x20000008) -#define DMA2_IT_GL9 ((uint32_t)0x20000010) -#define DMA2_IT_TC9 ((uint32_t)0x20000020) -#define DMA2_IT_HT9 ((uint32_t)0x20000040) -#define DMA2_IT_TE9 ((uint32_t)0x20000080) -#define DMA2_IT_GL10 ((uint32_t)0x20000100) -#define DMA2_IT_TC10 ((uint32_t)0x20000200) -#define DMA2_IT_HT10 ((uint32_t)0x20000400) -#define DMA2_IT_TE10 ((uint32_t)0x20000800) -#define DMA2_IT_GL11 ((uint32_t)0x20001000) -#define DMA2_IT_TC11 ((uint32_t)0x20002000) -#define DMA2_IT_HT11 ((uint32_t)0x20004000) -#define DMA2_IT_TE11 ((uint32_t)0x20008000) - -/* DMA_flags_definition */ -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) - -#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) -#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) -#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) -#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) -#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) -#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) -#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) -#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) -#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) -#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) -#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) -#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) -#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) -#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) -#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) -#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) -#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) -#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) -#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) -#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) -#define DMA2_FLAG_GL6 ((uint32_t)0x10100000) -#define DMA2_FLAG_TC6 ((uint32_t)0x10200000) -#define DMA2_FLAG_HT6 ((uint32_t)0x10400000) -#define DMA2_FLAG_TE6 ((uint32_t)0x10800000) -#define DMA2_FLAG_GL7 ((uint32_t)0x11000000) -#define DMA2_FLAG_TC7 ((uint32_t)0x12000000) -#define DMA2_FLAG_HT7 ((uint32_t)0x14000000) -#define DMA2_FLAG_TE7 ((uint32_t)0x18000000) - -#define DMA2_FLAG_GL8 ((uint32_t)0x20000001) -#define DMA2_FLAG_TC8 ((uint32_t)0x20000002) -#define DMA2_FLAG_HT8 ((uint32_t)0x20000004) -#define DMA2_FLAG_TE8 ((uint32_t)0x20000008) -#define DMA2_FLAG_GL9 ((uint32_t)0x20000010) -#define DMA2_FLAG_TC9 ((uint32_t)0x20000020) -#define DMA2_FLAG_HT9 ((uint32_t)0x20000040) -#define DMA2_FLAG_TE9 ((uint32_t)0x20000080) -#define DMA2_FLAG_GL10 ((uint32_t)0x20000100) -#define DMA2_FLAG_TC10 ((uint32_t)0x20000200) -#define DMA2_FLAG_HT10 ((uint32_t)0x20000400) -#define DMA2_FLAG_TE10 ((uint32_t)0x20000800) -#define DMA2_FLAG_GL11 ((uint32_t)0x20001000) -#define DMA2_FLAG_TC11 ((uint32_t)0x20002000) -#define DMA2_FLAG_HT11 ((uint32_t)0x20004000) -#define DMA2_FLAG_TE11 ((uint32_t)0x20008000) - - -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); -void DMA_ClearFlag(uint32_t DMAy_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMAy_IT); -void DMA_ClearITPendingBit(uint32_t DMAy_IT); - -#ifdef __cplusplus -} -#endif - -#endif - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dma.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DMA firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_DMA_H +#define __CH32V30x_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) +#define DMA2_IT_GL6 ((uint32_t)0x10100000) +#define DMA2_IT_TC6 ((uint32_t)0x10200000) +#define DMA2_IT_HT6 ((uint32_t)0x10400000) +#define DMA2_IT_TE6 ((uint32_t)0x10800000) +#define DMA2_IT_GL7 ((uint32_t)0x11000000) +#define DMA2_IT_TC7 ((uint32_t)0x12000000) +#define DMA2_IT_HT7 ((uint32_t)0x14000000) +#define DMA2_IT_TE7 ((uint32_t)0x18000000) + +#define DMA2_IT_GL8 ((uint32_t)0x20000001) +#define DMA2_IT_TC8 ((uint32_t)0x20000002) +#define DMA2_IT_HT8 ((uint32_t)0x20000004) +#define DMA2_IT_TE8 ((uint32_t)0x20000008) +#define DMA2_IT_GL9 ((uint32_t)0x20000010) +#define DMA2_IT_TC9 ((uint32_t)0x20000020) +#define DMA2_IT_HT9 ((uint32_t)0x20000040) +#define DMA2_IT_TE9 ((uint32_t)0x20000080) +#define DMA2_IT_GL10 ((uint32_t)0x20000100) +#define DMA2_IT_TC10 ((uint32_t)0x20000200) +#define DMA2_IT_HT10 ((uint32_t)0x20000400) +#define DMA2_IT_TE10 ((uint32_t)0x20000800) +#define DMA2_IT_GL11 ((uint32_t)0x20001000) +#define DMA2_IT_TC11 ((uint32_t)0x20002000) +#define DMA2_IT_HT11 ((uint32_t)0x20004000) +#define DMA2_IT_TE11 ((uint32_t)0x20008000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) +#define DMA2_FLAG_GL6 ((uint32_t)0x10100000) +#define DMA2_FLAG_TC6 ((uint32_t)0x10200000) +#define DMA2_FLAG_HT6 ((uint32_t)0x10400000) +#define DMA2_FLAG_TE6 ((uint32_t)0x10800000) +#define DMA2_FLAG_GL7 ((uint32_t)0x11000000) +#define DMA2_FLAG_TC7 ((uint32_t)0x12000000) +#define DMA2_FLAG_HT7 ((uint32_t)0x14000000) +#define DMA2_FLAG_TE7 ((uint32_t)0x18000000) + +#define DMA2_FLAG_GL8 ((uint32_t)0x20000001) +#define DMA2_FLAG_TC8 ((uint32_t)0x20000002) +#define DMA2_FLAG_HT8 ((uint32_t)0x20000004) +#define DMA2_FLAG_TE8 ((uint32_t)0x20000008) +#define DMA2_FLAG_GL9 ((uint32_t)0x20000010) +#define DMA2_FLAG_TC9 ((uint32_t)0x20000020) +#define DMA2_FLAG_HT9 ((uint32_t)0x20000040) +#define DMA2_FLAG_TE9 ((uint32_t)0x20000080) +#define DMA2_FLAG_GL10 ((uint32_t)0x20000100) +#define DMA2_FLAG_TC10 ((uint32_t)0x20000200) +#define DMA2_FLAG_HT10 ((uint32_t)0x20000400) +#define DMA2_FLAG_TE10 ((uint32_t)0x20000800) +#define DMA2_FLAG_GL11 ((uint32_t)0x20001000) +#define DMA2_FLAG_TC11 ((uint32_t)0x20002000) +#define DMA2_FLAG_HT11 ((uint32_t)0x20004000) +#define DMA2_FLAG_TE11 ((uint32_t)0x20008000) + + +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dvp.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dvp.h index fde0693..7040d31 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dvp.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_dvp.h @@ -1,69 +1,69 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_dvp.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* DVP firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_DVP_H -#define __CH32V30x_DVP_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* DVP Data Mode */ -typedef enum -{ - Video_Mode = 0, - JPEG_Mode, -}DVP_Data_ModeTypeDef; - - -/* DVP DMA */ -typedef enum -{ - DVP_DMA_Disable = 0, - DVP_DMA_Enable, -}DVP_DMATypeDef; - -/* DVP FLAG and FIFO Reset */ -typedef enum -{ - DVP_FLAG_FIFO_RESET_Disable = 0, - DVP_FLAG_FIFO_RESET_Enable, -}DVP_FLAG_FIFO_RESETTypeDef; - -/* DVP RX Reset */ -typedef enum -{ - DVP_RX_RESET_Disable = 0, - DVP_RX_RESET_Enable, -}DVP_RX_RESETTypeDef; - - - -void DVP_INTCfg( uint8_t s, uint8_t i ); -void DVP_Mode( uint8_t s, DVP_Data_ModeTypeDef i); -void DVP_Cfg( DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j); - - - -#ifdef __cplusplus -} -#endif - -#endif - - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dvp.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DVP firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_DVP_H +#define __CH32V30x_DVP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* DVP Data Mode */ +typedef enum +{ + Video_Mode = 0, + JPEG_Mode, +}DVP_Data_ModeTypeDef; + + +/* DVP DMA */ +typedef enum +{ + DVP_DMA_Disable = 0, + DVP_DMA_Enable, +}DVP_DMATypeDef; + +/* DVP FLAG and FIFO Reset */ +typedef enum +{ + DVP_FLAG_FIFO_RESET_Disable = 0, + DVP_FLAG_FIFO_RESET_Enable, +}DVP_FLAG_FIFO_RESETTypeDef; + +/* DVP RX Reset */ +typedef enum +{ + DVP_RX_RESET_Disable = 0, + DVP_RX_RESET_Enable, +}DVP_RX_RESETTypeDef; + + + +void DVP_INTCfg( uint8_t s, uint8_t i ); +void DVP_Mode( uint8_t s, DVP_Data_ModeTypeDef i); +void DVP_Cfg( DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j); + + + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_eth.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_eth.h index 388f059..7bdf671 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_eth.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_eth.h @@ -1,1338 +1,1338 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_eth.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* ETH firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_ETH_H -#define __CH32V30x_ETH_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - - -#define PHY_10BASE_T_LINKED 1 -#define PHY_10BASE_T_NOT_LINKED 0 - -#define DMA_TPS_Mask ((uint32_t)0x00700000) -#define DMA_RPS_Mask ((uint32_t)0x000E0000) - -/* ETH Init structure definition */ -typedef struct { - uint32_t ETH_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY - The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) - and the mode (half/full-duplex). - This parameter can be a value of @ref ETH_AutoNegotiation */ - - uint32_t ETH_Watchdog; /* Selects or not the Watchdog timer - When enabled, the MAC allows no more then 2048 bytes to be received. - When disabled, the MAC can receive up to 16384 bytes. - This parameter can be a value of @ref ETH_watchdog */ - - uint32_t ETH_Jabber; /* Selects or not Jabber timer - When enabled, the MAC allows no more then 2048 bytes to be sent. - When disabled, the MAC can send up to 16384 bytes. - This parameter can be a value of @ref ETH_Jabber */ - - uint32_t ETH_InterFrameGap; /* Selects the minimum IFG between frames during transmission - This parameter can be a value of @ref ETH_Inter_Frame_Gap */ - - uint32_t ETH_CarrierSense; /* Selects or not the Carrier Sense - This parameter can be a value of @ref ETH_Carrier_Sense */ - - uint32_t ETH_Speed; /* Sets the Ethernet speed: 10/100 Mbps - This parameter can be a value of @ref ETH_Speed */ - - uint32_t ETH_ReceiveOwn; /* Selects or not the ReceiveOwn - ReceiveOwn allows the reception of frames when the TX_EN signal is asserted - in Half-Duplex mode - This parameter can be a value of @ref ETH_Receive_Own */ - - uint32_t ETH_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode - This parameter can be a value of @ref ETH_Loop_Back_Mode */ - - uint32_t ETH_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode - This parameter can be a value of @ref ETH_Duplex_Mode */ - - uint32_t ETH_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. - This parameter can be a value of @ref ETH_Checksum_Offload */ - - uint32_t ETH_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL, - when a colision occurs (Half-Duplex mode) - This parameter can be a value of @ref ETH_Retry_Transmission */ - - uint32_t ETH_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping - This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ - - uint32_t ETH_BackOffLimit; /* Selects the BackOff limit value - This parameter can be a value of @ref ETH_Back_Off_Limit */ - - uint32_t ETH_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode) - This parameter can be a value of @ref ETH_Deferral_Check */ - - uint32_t ETH_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering) - This parameter can be a value of @ref ETH_Receive_All */ - - uint32_t ETH_SourceAddrFilter; /* Selects the Source Address Filter mode - This parameter can be a value of @ref ETH_Source_Addr_Filter */ - - uint32_t ETH_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) - This parameter can be a value of @ref ETH_Pass_Control_Frames */ - - uint32_t ETH_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames - This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ - - uint32_t ETH_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames - This parameter can be a value of @ref ETH_Destination_Addr_Filter */ - - uint32_t ETH_PromiscuousMode; /* Selects or not the Promiscuous Mode - This parameter can be a value of @ref ETH_Promiscuous_Mode */ - - uint32_t ETH_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter - This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ - - uint32_t ETH_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter - This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ - - uint32_t ETH_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */ - - uint32_t ETH_HashTableLow; /* This field holds the lower 32 bits of Hash table. */ - - uint32_t ETH_PauseTime; /* This field holds the value to be used in the Pause Time field in the - transmit control frame */ - - uint32_t ETH_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames - This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ - - uint32_t ETH_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for - automatic retransmission of PAUSE Frame - This parameter can be a value of @ref ETH_Pause_Low_Threshold */ - - uint32_t ETH_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0 - unicast address and unique multicast address) - This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ - - uint32_t ETH_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and - disable its transmitter for a specified time (Pause Time) - This parameter can be a value of @ref ETH_Receive_Flow_Control */ - - uint32_t ETH_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) - or the MAC back-pressure operation (Half-Duplex mode) - This parameter can be a value of @ref ETH_Transmit_Flow_Control */ - - uint32_t ETH_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for - comparison and filtering - This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ - - uint32_t ETH_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */ - - uint32_t ETH_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames - This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ - - uint32_t ETH_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode - This parameter can be a value of @ref ETH_Receive_Store_Forward */ - - uint32_t ETH_FlushReceivedFrame; /* Enables or disables the flushing of received frames - This parameter can be a value of @ref ETH_Flush_Received_Frame */ - - uint32_t ETH_TransmitStoreForward; /* Enables or disables Transmit store and forward mode - This parameter can be a value of @ref ETH_Transmit_Store_Forward */ - - uint32_t ETH_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control - This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ - - uint32_t ETH_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames - This parameter can be a value of @ref ETH_Forward_Error_Frames */ - - uint32_t ETH_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error - and length less than 64 bytes) including pad-bytes and CRC) - This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ - - uint32_t ETH_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO - This parameter can be a value of @ref ETH_Receive_Threshold_Control */ - - uint32_t ETH_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second - frame of Transmit data even before obtaining the status for the first frame. - This parameter can be a value of @ref ETH_Second_Frame_Operate */ - - uint32_t ETH_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats - This parameter can be a value of @ref ETH_Address_Aligned_Beats */ - - uint32_t ETH_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers - This parameter can be a value of @ref ETH_Fixed_Burst */ - - uint32_t ETH_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction - This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ - - uint32_t ETH_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction - This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ - - uint32_t ETH_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */ - - uint32_t ETH_DMAArbitration; /* Selects the DMA Tx/Rx arbitration - This parameter can be a value of @ref ETH_DMA_Arbitration */ -}ETH_InitTypeDef; - - - -/* ETH delay.Just for Ethernet */ -#define _eth_delay_ ETH_Delay /* Default _eth_delay_ function with less precise timing */ - -/* definition for Ethernet frame */ -#define ETH_MAX_PACKET_SIZE 1536 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ -#define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define ETH_CRC 4 /* Ethernet CRC */ -#define ETH_EXTRA 2 /* Extra bytes in some cases */ -#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ -#define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */ -#define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */ -#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ - -/* ETH DMA structure definition */ -typedef struct -{ - uint32_t volatile Status; /* Status */ - uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ - uint32_t Buffer1Addr; /* Buffer1 address pointer */ - uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ -} ETH_DMADESCTypeDef; - -/** - DMA Tx Desciptor - ----------------------------------------------------------------------------------------------- - TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | - ----------------------------------------------------------------------------------------------- - TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | - ----------------------------------------------------------------------------------------------- - TDES2 | Buffer1 Address [31:0] | - ----------------------------------------------------------------------------------------------- - TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | - ------------------------------------------------------------------------------------------------ -*/ - - -/* Bit or field definition of TDES0 register (DMA Tx descriptor status register)*/ -#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /* Interrupt on Completion */ -#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /* Last Segment */ -#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /* First Segment */ -#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /* Disable CRC */ -#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /* Disable Padding */ -#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /* Transmit Time Stamp Enable */ -#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /* Checksum Insertion Control: 4 cases */ -#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /* Do Nothing: Checksum Engine is bypassed */ -#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /* IPV4 header Checksum Insertion */ -#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */ -#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */ -#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /* Transmit End of Ring */ -#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /* Second Address Chained */ -#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /* Tx Time Stamp Status */ -#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /* IP Header Error */ -#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ -#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /* Jabber Timeout */ -#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */ -#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /* Payload Checksum Error */ -#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */ -#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /* No Carrier: no carrier signal from the tranceiver */ -#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /* Late Collision: transmission aborted due to collision */ -#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */ -#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /* VLAN Frame */ -#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /* Collision Count */ -#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /* Excessive Deferral */ -#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /* Underflow Error: late data arrival from the memory */ -#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /* Deferred Bit */ - -/* Field definition of TDES1 register */ -#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /* Transmit Buffer2 Size */ -#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /* Transmit Buffer1 Size */ - -/* Field definition of TDES2 register */ -#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ - -/* Field definition of TDES3 register */ -#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ - -/** - DMA Rx Desciptor - --------------------------------------------------------------------------------------------------------------------- - RDES0 | OWN(31) | Status [30:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES2 | Buffer1 Address [31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | - ---------------------------------------------------------------------------------------------------------------------- -*/ - -/* Bit or field definition of RDES0 register (DMA Rx descriptor status register) */ -#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /* DA Filter Fail for the rx frame */ -#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /* Receive descriptor frame length */ -#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ -#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /* Desciptor error: no more descriptors for receive frame */ -#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /* SA Filter Fail for the received frame */ -#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /* Frame size not matching with length field */ -#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */ -#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /* VLAN Tag: received frame is a VLAN frame */ -#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /* First descriptor of the frame */ -#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /* Last descriptor of the frame */ -#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /* IPC Checksum Error: Rx Ipv4 header checksum error */ -#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /* Late collision occurred during reception */ -#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */ -#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */ -#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /* Receive error: error reported by MII interface */ -#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */ -#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /* CRC error */ -#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ - -/* Bit or field definition of RDES1 register */ -#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /* Disable Interrupt on Completion */ -#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /* Receive Buffer2 Size */ -#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /* Receive End of Ring */ -#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /* Second Address Chained */ -#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /* Receive Buffer1 Size */ - -/* Field definition of RDES2 register */ -#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ - -/* Field definition of RDES3 register */ -#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ - -/* Timeout threshold of Reading or writing PHY registers */ -#define PHY_READ_TO ((uint32_t)0x004FFFFF) -#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) - -/* Delay time after reset PHY */ -#define PHY_ResetDelay ((uint32_t)0x000FFFFF) - -/* Delay time after configure PHY */ -#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) - -/* PHY basic register */ -#define PHY_BCR 0x0 /*PHY transceiver Basic Control Register */ -#define PHY_BSR 0x01 /*PHY transceiver Basic Status Register*/ -#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisement Register */ -#define PHY_ANLPAR 0x05 /* Auto-Negotiation Link Partner Base Page Ability Register*/ -#define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ -#define PHY_BMCR PHY_BCR -#define PHY_BMSR PHY_BSR -#define PHY_STATUS 0x10 -#define PHY_MDIX 0x1E - -/* Bit or field definition for PHY basic control register */ -#define PHY_Reset ((uint16_t)0x8000) /* PHY Reset */ -#define PHY_Loopback ((uint16_t)0x4000) /* Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /* Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /* Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /* Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /* Set the half-duplex mode at 10 Mb/s */ -#define PHY_AutoNegotiation ((uint16_t)0x1000) /* Enable auto-negotiation function */ -#define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /* Restart auto-negotiation function */ -#define PHY_Powerdown ((uint16_t)0x0800) /* Select the power down mode */ -#define PHY_Isolate ((uint16_t)0x0400) /* Isolate PHY from MII */ - -/* Bit or field definition for PHY basic status register */ -#define PHY_AutoNego_Complete ((uint16_t)0x0020) /* Auto-Negotioation process completed */ -#define PHY_Linked_Status ((uint16_t)0x0004) /* Valid link established */ -#define PHY_Jabber_detection ((uint16_t)0x0002) /* Jabber condition detected */ -#define PHY_RMII_Mode ((uint16_t)0x0020) /* RMII */ - - -/* Internal 10BASE-T PHY 50R*4 pull-up resistance enable or disable */ -#define ETH_Internal_Pull_Up_Res_Enable ((uint32_t)0x00100000) -#define ETH_Internal_Pull_Up_Res_Disable ((uint32_t)0x00000000) - -/* MAC autoNegotiation enable or disable */ -#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) -#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) - -/* MAC watchdog enable or disable */ -#define ETH_Watchdog_Enable ((uint32_t)0x00000000) -#define ETH_Watchdog_Disable ((uint32_t)0x00800000) - -/* Bit description - MAC jabber enable or disable */ -#define ETH_Jabber_Enable ((uint32_t)0x00000000) -#define ETH_Jabber_Disable ((uint32_t)0x00400000) - -/* Value of minimum IFG between frames during transmission */ -#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /* minimum IFG between frames during transmission is 96Bit */ -#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /* minimum IFG between frames during transmission is 88Bit */ -#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /* minimum IFG between frames during transmission is 80Bit */ -#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /* minimum IFG between frames during transmission is 72Bit */ -#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /* minimum IFG between frames during transmission is 64Bit */ -#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */ -#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */ -#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */ - -/* MAC carrier sense enable or disable */ -#define ETH_CarrierSense_Enable ((uint32_t)0x00000000) -#define ETH_CarrierSense_Disable ((uint32_t)0x00010000) - -/* MAC speed */ -#define ETH_Speed_10M ((uint32_t)0x00000000) -#define ETH_Speed_100M ((uint32_t)0x00004000) -#define ETH_Speed_1000M ((uint32_t)0x00008000) - -/* MAC receive own enable or disable */ -#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) -#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) - -/* MAC Loopback mode enable or disable */ -#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) -#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) - -/* MAC fullDuplex or halfDuplex */ -#define ETH_Mode_FullDuplex ((uint32_t)0x00000800) -#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) - -/* MAC offload checksum enable or disable */ -#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) -#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) - -/* MAC transmission retry enable or disable */ -#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) -#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) - -/* MAC automatic pad CRC strip enable or disable */ -#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) -#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) - -/* MAC backoff limitation */ -#define ETH_BackOffLimit_10 ((uint32_t)0x00000000) -#define ETH_BackOffLimit_8 ((uint32_t)0x00000020) -#define ETH_BackOffLimit_4 ((uint32_t)0x00000040) -#define ETH_BackOffLimit_1 ((uint32_t)0x00000060) - -/* MAC deferral check enable or disable */ -#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) -#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) - -/* Bit description : MAC receive all frame enable or disable */ -#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) -#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) - -/* MAC backoff limitation */ -#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) -#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) -#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) - -/* MAC Pass control frames */ -#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ -#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ -#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ - -/* MAC broadcast frames reception */ -#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) -#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) - -/* MAC destination address filter */ -#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) -#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) - -/* MAC Promiscuous mode enable or disable */ -#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) -#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) - -/* MAC multicast frames filter */ -#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) -#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) -#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) -#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) - -/* MAC unicast frames filter */ -#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) -#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) -#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) - -/* Bit description : MAC zero quanta pause */ -#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) -#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) - -/* Field description : MAC pause low threshold */ -#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ -#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ -#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ -#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ - -/* MAC unicast pause frame detect enable or disable*/ -#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) -#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) - -/* MAC receive flow control frame enable or disable */ -#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) -#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) - -/* MAC transmit flow control enable or disable */ -#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) -#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) - -/* MAC VLAN tag comparison */ -#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) -#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) - -/* MAC flag */ -#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /* Time stamp trigger flag (on MAC) */ -#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /* MMC transmit flag */ -#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /* MMC receive flag */ -#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /* MMC flag (on MAC) */ -#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /* PMT flag (on MAC) */ - -/* MAC interrupt */ -#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /* Time stamp trigger interrupt (on MAC) */ -#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /* MMC transmit interrupt */ -#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /* MMC receive interrupt */ -#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /* MMC interrupt (on MAC) */ -#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /* PMT interrupt (on MAC) */ - -/* MAC address */ -#define ETH_MAC_Address0 ((uint32_t)0x00000000) -#define ETH_MAC_Address1 ((uint32_t)0x00000008) -#define ETH_MAC_Address2 ((uint32_t)0x00000010) -#define ETH_MAC_Address3 ((uint32_t)0x00000018) - -/* MAC address filter select */ -#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) -#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) - -/* MAC address mask */ -#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ - - -/******************************************************************************/ -/* */ -/* MAC Descriptor Register */ -/* */ -/******************************************************************************/ - -/* DMA descriptor segment */ -#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /* Last Segment */ -#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /* First Segment */ - -/* DMA descriptor checksum setting */ -#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /* Checksum engine bypass */ -#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /* IPv4 header checksum insertion */ -#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ -#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ - -/* DMA RX & TX buffer */ -#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /* DMA Rx Desc Buffer1 */ -#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /* DMA Rx Desc Buffer2 */ - - -/******************************************************************************/ -/* */ -/* ETH DMA Register */ -/* */ -/******************************************************************************/ - -/* DMA drop TCPIP checksum error frame enable or disable */ -#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) -#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) - -/* DMA receive store forward enable or disable */ -#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) -#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) - -/* DMA flush received frame enable or disable */ -#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) -#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) - -/* DMA transmit store forward enable or disable */ -#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) -#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) - -/* DMA transmit threshold control */ -#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ -#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ -#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ -#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ -#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ -#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ -#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ -#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ - -/* DMA forward error frames */ -#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) -#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) - -/* DMA forward undersized good frames enable or disable */ -#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) -#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) - -/* DMA receive threshold control */ -#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ -#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ -#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ -#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ - -/* DMA second frame operate enable or disable */ -#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) -#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) - -/* Address aligned beats enable or disable */ -#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) -#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) - -/* DMA Fixed burst enable or disable */ -#define ETH_FixedBurst_Enable ((uint32_t)0x00010000) -#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) - - -/* RX DMA burst length */ -#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ -#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ -#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ -#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ - - -/* TX DMA burst length */ -#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ -#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ -#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ -#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ - -/* DMA arbitration_round robin */ -#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) -#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) -#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) -#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) -#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) - -/* DMA interrupt FALG */ -#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ -#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ -#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ -#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ -#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /* Normal interrupt summary flag */ -#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary flag */ -#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /* Early receive flag */ -#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /* Fatal bus error flag */ -#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /* Early transmit flag */ -#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout flag */ -#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /* Receive process stopped flag */ -#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable flag */ -#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /* Receive flag */ -#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /* Underflow flag */ -#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /* Overflow flag */ -#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout flag */ -#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable flag */ -#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /* Transmit process stopped flag */ -#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /* Transmit flag */ - -/* DMA interrupt */ -#define ETH_DMA_IT_PHYLINK ((uint32_t)0x80000000) /* Internal PHY link status change interrupt */ -#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ -#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ -#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ -#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ -#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /* Early receive interrupt */ -#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /* Fatal bus error interrupt */ -#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /* Early transmit interrupt */ -#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt */ -#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /* Receive process stopped interrupt */ -#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt */ -#define ETH_DMA_IT_R ((uint32_t)0x00000040) /* Receive interrupt */ -#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /* Underflow interrupt */ -#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /* Overflow interrupt */ -#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt */ -#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt */ -#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /* Transmit process stopped interrupt */ -#define ETH_DMA_IT_T ((uint32_t)0x00000001) /* Transmit interrupt */ - -/* DMA transmit process */ -#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ -#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ -#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ -#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ -#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Desciptor unavailabe */ -#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ - -/* DMA receive Process */ -#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ -#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ -#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ -#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Desciptor unavailable */ -#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ -#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ - -/* DMA overflow */ -#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ -#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ - - -/********************************************************************************* -* Ethernet PMT defines -**********************************************************************************/ - -/* PMT flag */ -#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */ -#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ -#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ - -/********************************************************************************* -* Ethernet MMC defines -**********************************************************************************/ - -/* MMC TX interrupt flag */ -#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /* When Tx good frame counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /* When Tx good multi col counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /* When Tx good single col counter reaches half the maximum value */ - -/* MMC RX interrupt flag */ -#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /* When Rx alignment error counter reaches half the maximum value */ -#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /* When Rx crc error counter reaches half the maximum value */ - - -/* MMC description */ -#define ETH_MMCCR ((uint32_t)0x00000100) /* MMC CR register */ -#define ETH_MMCRIR ((uint32_t)0x00000104) /* MMC RIR register */ -#define ETH_MMCTIR ((uint32_t)0x00000108) /* MMC TIR register */ -#define ETH_MMCRIMR ((uint32_t)0x0000010C) /* MMC RIMR register */ -#define ETH_MMCTIMR ((uint32_t)0x00000110) /* MMC TIMR register */ -#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /* MMC TGFSCCR register */ -#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /* MMC TGFMSCCR register */ -#define ETH_MMCTGFCR ((uint32_t)0x00000168) /* MMC TGFCR register */ -#define ETH_MMCRFCECR ((uint32_t)0x00000194) /* MMC RFCECR register */ -#define ETH_MMCRFAECR ((uint32_t)0x00000198) /* MMC RFAECR register */ -#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /* MMC RGUFCR register */ - - -/********************************************************************************* -* Ethernet PTP defines -**********************************************************************************/ - -/* PTP fine update method or coarse Update method */ -#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /* Fine Update method */ -#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /* Coarse Update method */ - - -/* PTP time stamp control */ -#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /* Addend Register Update */ -#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /* Time Stamp Interrupt Trigger */ -#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /* Time Stamp Update */ -#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /* Time Stamp Initialize */ - -/* PTP positive/negative time value */ -#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /* Positive time value */ -#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /* Negative time value */ - - -/******************************************************************************/ -/* */ -/* PTP Register */ -/* */ -/******************************************************************************/ -#define ETH_PTPTSCR ((uint32_t)0x00000700) /* PTP TSCR register */ -#define ETH_PTPSSIR ((uint32_t)0x00000704) /* PTP SSIR register */ -#define ETH_PTPTSHR ((uint32_t)0x00000708) /* PTP TSHR register */ -#define ETH_PTPTSLR ((uint32_t)0x0000070C) /* PTP TSLR register */ -#define ETH_PTPTSHUR ((uint32_t)0x00000710) /* PTP TSHUR register */ -#define ETH_PTPTSLUR ((uint32_t)0x00000714) /* PTP TSLUR register */ -#define ETH_PTPTSAR ((uint32_t)0x00000718) /* PTP TSAR register */ -#define ETH_PTPTTHR ((uint32_t)0x0000071C) /* PTP TTHR register */ -#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ - -#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ -#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ -#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ -#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ - #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ - #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ - #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ - #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ - #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ - #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ - #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ - #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ - #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ -#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ - #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ - #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ - #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ - #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ - #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ - #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ -#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ -#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ -#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ -#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ -#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ -#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ -#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ -#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ -#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ -#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ -#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ -#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ -#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ -#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ -#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ - - -/******************************************************************************/ -/* */ -/* ETH MAC Register */ -/* */ -/******************************************************************************/ -#define ETH_MACCR_WD ((unsigned int)0x00800000) /* Watchdog disable */ -#define ETH_MACCR_JD ((unsigned int)0x00400000) /* Jabber disable */ -#define ETH_MACCR_IFG ((unsigned int)0x000E0000) /* Inter-frame gap */ -#define ETH_MACCR_IFG_96Bit ((unsigned int)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ - #define ETH_MACCR_IFG_88Bit ((unsigned int)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ - #define ETH_MACCR_IFG_80Bit ((unsigned int)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ - #define ETH_MACCR_IFG_72Bit ((unsigned int)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ - #define ETH_MACCR_IFG_64Bit ((unsigned int)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ - #define ETH_MACCR_IFG_56Bit ((unsigned int)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ - #define ETH_MACCR_IFG_48Bit ((unsigned int)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ - #define ETH_MACCR_IFG_40Bit ((unsigned int)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ -#define ETH_MACCR_CSD ((unsigned int)0x00010000) /* Carrier sense disable (during transmission) */ -#define ETH_MACCR_FES ((unsigned int)0x00004000) /* Fast ethernet speed */ -#define ETH_MACCR_ROD ((unsigned int)0x00002000) /* Receive own disable */ -#define ETH_MACCR_LM ((unsigned int)0x00001000) /* loopback mode */ -#define ETH_MACCR_DM ((unsigned int)0x00000800) /* Duplex mode */ -#define ETH_MACCR_IPCO ((unsigned int)0x00000400) /* IP Checksum offload */ -#define ETH_MACCR_RD ((unsigned int)0x00000200) /* Retry disable */ -#define ETH_MACCR_APCS ((unsigned int)0x00000080) /* Automatic Pad/CRC stripping */ -#define ETH_MACCR_BL ((unsigned int)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before reschedulinga transmission attempt during retries after a collision: 0 =< r <2^k */ - #define ETH_MACCR_BL_10 ((unsigned int)0x00000000) /* k = min (n, 10) */ - #define ETH_MACCR_BL_8 ((unsigned int)0x00000020) /* k = min (n, 8) */ - #define ETH_MACCR_BL_4 ((unsigned int)0x00000040) /* k = min (n, 4) */ - #define ETH_MACCR_BL_1 ((unsigned int)0x00000060) /* k = min (n, 1) */ -#define ETH_MACCR_DC ((unsigned int)0x00000010) /* Defferal check */ -#define ETH_MACCR_TE ((unsigned int)0x00000008) /* Transmitter enable */ -#define ETH_MACCR_RE ((unsigned int)0x00000004) /* Receiver enable */ - -#define ETH_MACFFR_RA ((unsigned int)0x80000000) /* Receive all */ -#define ETH_MACFFR_HPF ((unsigned int)0x00000400) /* Hash or perfect filter */ -#define ETH_MACFFR_SAF ((unsigned int)0x00000200) /* Source address filter enable */ -#define ETH_MACFFR_SAIF ((unsigned int)0x00000100) /* SA inverse filtering */ -#define ETH_MACFFR_PCF ((unsigned int)0x000000C0) /* Pass control frames: 3 cases */ - #define ETH_MACFFR_PCF_BlockAll ((unsigned int)0x00000040) /* MAC filters all control frames from reaching the application */ - #define ETH_MACFFR_PCF_ForwardAll ((unsigned int)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ - #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((unsigned int)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ -#define ETH_MACFFR_BFD ((unsigned int)0x00000020) /* Broadcast frame disable */ -#define ETH_MACFFR_PAM ((unsigned int)0x00000010) /* Pass all mutlicast */ -#define ETH_MACFFR_DAIF ((unsigned int)0x00000008) /* DA Inverse filtering */ -#define ETH_MACFFR_HM ((unsigned int)0x00000004) /* Hash multicast */ -#define ETH_MACFFR_HU ((unsigned int)0x00000002) /* Hash unicast */ -#define ETH_MACFFR_PM ((unsigned int)0x00000001) /* Promiscuous mode */ - -#define ETH_MACHTHR_HTH ((unsigned int)0xFFFFFFFF) /* Hash table high */ -#define ETH_MACHTLR_HTL ((unsigned int)0xFFFFFFFF) /* Hash table low */ - -#define ETH_MACMIIAR_PA ((unsigned int)0x0000F800) /* Physical layer address */ -#define ETH_MACMIIAR_MR ((unsigned int)0x000007C0) /* MII register in the selected PHY */ -#define ETH_MACMIIAR_CR ((unsigned int)0x0000001C) /* CR clock range: 6 cases */ - #define ETH_MACMIIAR_CR_Div42 ((unsigned int)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ - #define ETH_MACMIIAR_CR_Div16 ((unsigned int)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ - #define ETH_MACMIIAR_CR_Div26 ((unsigned int)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ -#define ETH_MACMIIAR_MW ((unsigned int)0x00000002) /* MII write */ -#define ETH_MACMIIAR_MB ((unsigned int)0x00000001) /* MII busy */ -#define ETH_MACMIIDR_MD ((unsigned int)0x0000FFFF) /* MII data: read/write data from/to PHY */ -#define ETH_MACFCR_PT ((unsigned int)0xFFFF0000) /* Pause time */ -#define ETH_MACFCR_ZQPD ((unsigned int)0x00000080) /* Zero-quanta pause disable */ -#define ETH_MACFCR_PLT ((unsigned int)0x00000030) /* Pause low threshold: 4 cases */ - #define ETH_MACFCR_PLT_Minus4 ((unsigned int)0x00000000) /* Pause time minus 4 slot times */ - #define ETH_MACFCR_PLT_Minus28 ((unsigned int)0x00000010) /* Pause time minus 28 slot times */ - #define ETH_MACFCR_PLT_Minus144 ((unsigned int)0x00000020) /* Pause time minus 144 slot times */ - #define ETH_MACFCR_PLT_Minus256 ((unsigned int)0x00000030) /* Pause time minus 256 slot times */ -#define ETH_MACFCR_UPFD ((unsigned int)0x00000008) /* Unicast pause frame detect */ -#define ETH_MACFCR_RFCE ((unsigned int)0x00000004) /* Receive flow control enable */ -#define ETH_MACFCR_TFCE ((unsigned int)0x00000002) /* Transmit flow control enable */ -#define ETH_MACFCR_FCBBPA ((unsigned int)0x00000001) /* Flow control busy/backpressure activate */ - -#define ETH_MACVLANTR_VLANTC ((unsigned int)0x00010000) /* 12-bit VLAN tag comparison */ -#define ETH_MACVLANTR_VLANTI ((unsigned int)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ - -#define ETH_MACRWUFFR_D ((unsigned int)0xFFFFFFFF) /* Wake-up frame filter register data */ -/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. -Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ - -/* -Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask -Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask -Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask -Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask -Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - - RSVD - Filter1 Command - RSVD - Filter0 Command -Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset -Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 -Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ - -#define ETH_MACPMTCSR_WFFRPR ((unsigned int)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_MACPMTCSR_GU ((unsigned int)0x00000200) /* Global Unicast */ -#define ETH_MACPMTCSR_WFR ((unsigned int)0x00000040) /* Wake-Up Frame Received */ -#define ETH_MACPMTCSR_MPR ((unsigned int)0x00000020) /* Magic Packet Received */ -#define ETH_MACPMTCSR_WFE ((unsigned int)0x00000004) /* Wake-Up Frame Enable */ -#define ETH_MACPMTCSR_MPE ((unsigned int)0x00000002) /* Magic Packet Enable */ -#define ETH_MACPMTCSR_PD ((unsigned int)0x00000001) /* Power Down */ - -#define ETH_MACSR_TSTS ((unsigned int)0x00000200) /* Time stamp trigger status */ -#define ETH_MACSR_MMCTS ((unsigned int)0x00000040) /* MMC transmit status */ -#define ETH_MACSR_MMMCRS ((unsigned int)0x00000020) /* MMC receive status */ -#define ETH_MACSR_MMCS ((unsigned int)0x00000010) /* MMC status */ -#define ETH_MACSR_PMTS ((unsigned int)0x00000008) /* PMT status */ - -#define ETH_MACIMR_TSTIM ((unsigned int)0x00000200) /* Time stamp trigger interrupt mask */ -#define ETH_MACIMR_PMTIM ((unsigned int)0x00000008) /* PMT interrupt mask */ - -#define ETH_MACA0HR_MACA0H ((unsigned int)0x0000FFFF) /* MAC address0 high */ - -#define ETH_MACA0LR_MACA0L ((unsigned int)0xFFFFFFFF) /* MAC address0 low */ - -#define ETH_MACA1HR_AE ((unsigned int)0x80000000) /* Address enable */ -#define ETH_MACA1HR_SA ((unsigned int)0x40000000) /* Source address */ -#define ETH_MACA1HR_MBC ((unsigned int)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ - #define ETH_MACA1HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA1HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA1HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA1HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA1HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA1HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [7:0] */ -#define ETH_MACA1HR_MACA1H ((unsigned int)0x0000FFFF) /* MAC address1 high */ - -#define ETH_MACA1LR_MACA1L ((unsigned int)0xFFFFFFFF) /* MAC address1 low */ - -#define ETH_MACA2HR_AE ((unsigned int)0x80000000) /* Address enable */ -#define ETH_MACA2HR_SA ((unsigned int)0x40000000) /* Source address */ -#define ETH_MACA2HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ - #define ETH_MACA2HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA2HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA2HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA2HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA2HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA2HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ - -#define ETH_MACA2HR_MACA2H ((unsigned int)0x0000FFFF) /* MAC address1 high */ -#define ETH_MACA2LR_MACA2L ((unsigned int)0xFFFFFFFF) /* MAC address2 low */ - -#define ETH_MACA3HR_AE ((unsigned int)0x80000000) /* Address enable */ -#define ETH_MACA3HR_SA ((unsigned int)0x40000000) /* Source address */ -#define ETH_MACA3HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ - #define ETH_MACA3HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA3HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA3HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA3HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA3HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA3HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define ETH_MACA3HR_MACA3H ((unsigned int)0x0000FFFF) /* MAC address3 high */ -#define ETH_MACA3LR_MACA3L ((unsigned int)0xFFFFFFFF) /* MAC address3 low */ - -/******************************************************************************/ -/* -/* ETH MMC Register -/* -/******************************************************************************/ -#define ETH_MMCCR_MCFHP ((unsigned int)0x00000020) /* MMC counter Full-Half preset */ -#define ETH_MMCCR_MCP ((unsigned int)0x00000010) /* MMC counter preset */ -#define ETH_MMCCR_MCF ((unsigned int)0x00000008) /* MMC Counter Freeze */ -#define ETH_MMCCR_ROR ((unsigned int)0x00000004) /* Reset on Read */ -#define ETH_MMCCR_CSR ((unsigned int)0x00000002) /* Counter Stop Rollover */ -#define ETH_MMCCR_CR ((unsigned int)0x00000001) /* Counters Reset */ - -#define ETH_MMCRIR_RGUFS ((unsigned int)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIR_RFAES ((unsigned int)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIR_RFCES ((unsigned int)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ - -#define ETH_MMCTIR_TGFS ((unsigned int)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFMSCS ((unsigned int)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFSCS ((unsigned int)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ - -#define ETH_MMCRIMR_RGUFM ((unsigned int)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFAEM ((unsigned int)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFCEM ((unsigned int)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ - -#define ETH_MMCTIMR_TGFM ((unsigned int)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFMSCM ((unsigned int)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFSCM ((unsigned int)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ - -#define ETH_MMCTGFSCCR_TGFSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ - -#define ETH_MMCTGFMSCCR_TGFMSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ - -#define ETH_MMCTGFCR_TGFC ((unsigned int)0xFFFFFFFF) /* Number of good frames transmitted. */ - -#define ETH_MMCRFCECR_RFCEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with CRC error. */ - -#define ETH_MMCRFAECR_RFAEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ - -#define ETH_MMCRGUFCR_RGUFC ((unsigned int)0xFFFFFFFF) /* Number of good unicast frames received. */ - - -/******************************************************************************/ -/* -/* ETH Precise Clock Protocol Register -/* -/******************************************************************************/ -#define ETH_PTPTSCR_TSCNT ((unsigned int)0x00030000) /* Time stamp clock node type */ -#define ETH_PTPTSSR_TSSMRME ((unsigned int)0x00008000) /* Time stamp snapshot for message relevant to master enable */ -#define ETH_PTPTSSR_TSSEME ((unsigned int)0x00004000) /* Time stamp snapshot for event message enable */ -#define ETH_PTPTSSR_TSSIPV4FE ((unsigned int)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ -#define ETH_PTPTSSR_TSSIPV6FE ((unsigned int)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ -#define ETH_PTPTSSR_TSSPTPOEFE ((unsigned int)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ -#define ETH_PTPTSSR_TSPTPPSV2E ((unsigned int)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ -#define ETH_PTPTSSR_TSSSR ((unsigned int)0x00000200) /* Time stamp Sub-seconds rollover */ -#define ETH_PTPTSSR_TSSARFE ((unsigned int)0x00000100) /* Time stamp snapshot for all received frames enable */ - -#define ETH_PTPTSCR_TSARU ((unsigned int)0x00000020) /* Addend register update */ -#define ETH_PTPTSCR_TSITE ((unsigned int)0x00000010) /* Time stamp interrupt trigger enable */ -#define ETH_PTPTSCR_TSSTU ((unsigned int)0x00000008) /* Time stamp update */ -#define ETH_PTPTSCR_TSSTI ((unsigned int)0x00000004) /* Time stamp initialize */ -#define ETH_PTPTSCR_TSFCU ((unsigned int)0x00000002) /* Time stamp fine or coarse update */ -#define ETH_PTPTSCR_TSE ((unsigned int)0x00000001) /* Time stamp enable */ - -#define ETH_PTPSSIR_STSSI ((unsigned int)0x000000FF) /* System time Sub-second increment value */ - -#define ETH_PTPTSHR_STS ((unsigned int)0xFFFFFFFF) /* System Time second */ - -#define ETH_PTPTSLR_STPNS ((unsigned int)0x80000000) /* System Time Positive or negative time */ -#define ETH_PTPTSLR_STSS ((unsigned int)0x7FFFFFFF) /* System Time sub-seconds */ - -#define ETH_PTPTSHUR_TSUS ((unsigned int)0xFFFFFFFF) /* Time stamp update seconds */ - -#define ETH_PTPTSLUR_TSUPNS ((unsigned int)0x80000000) /* Time stamp update Positive or negative time */ -#define ETH_PTPTSLUR_TSUSS ((unsigned int)0x7FFFFFFF) /* Time stamp update sub-seconds */ - -#define ETH_PTPTSAR_TSA ((unsigned int)0xFFFFFFFF) /* Time stamp addend */ - -#define ETH_PTPTTHR_TTSH ((unsigned int)0xFFFFFFFF) /* Target time stamp high */ - -#define ETH_PTPTTLR_TTSL ((unsigned int)0xFFFFFFFF) /* Target time stamp low */ - -#define ETH_PTPTSSR_TSTTR ((unsigned int)0x00000020) /* Time stamp target time reached */ -#define ETH_PTPTSSR_TSSO ((unsigned int)0x00000010) /* Time stamp seconds overflow */ - -/******************************************************************************/ -/* -/* ETH DMA Register -/* -/******************************************************************************/ -#define ETH_DMABMR_AAB ((unsigned int)0x02000000) /* Address-Aligned beats */ -#define ETH_DMABMR_FPM ((unsigned int)0x01000000) /* 4xPBL mode */ -#define ETH_DMABMR_USP ((unsigned int)0x00800000) /* Use separate PBL */ -#define ETH_DMABMR_RDP ((unsigned int)0x007E0000) /* RxDMA PBL */ - #define ETH_DMABMR_RDP_1Beat ((unsigned int)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ - #define ETH_DMABMR_RDP_2Beat ((unsigned int)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ - #define ETH_DMABMR_RDP_4Beat ((unsigned int)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_8Beat ((unsigned int)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_16Beat ((unsigned int)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_32Beat ((unsigned int)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_4Beat ((unsigned int)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_4xPBL_8Beat ((unsigned int)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_4xPBL_16Beat ((unsigned int)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_4xPBL_32Beat ((unsigned int)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_64Beat ((unsigned int)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ - #define ETH_DMABMR_RDP_4xPBL_128Beat ((unsigned int)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ -#define ETH_DMABMR_FB ((unsigned int)0x00010000) /* Fixed Burst */ -#define ETH_DMABMR_RTPR ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_1_1 ((unsigned int)0x00000000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_2_1 ((unsigned int)0x00004000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_3_1 ((unsigned int)0x00008000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_4_1 ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ -#define ETH_DMABMR_PBL ((unsigned int)0x00003F00) /* Programmable burst length */ - #define ETH_DMABMR_PBL_1Beat ((unsigned int)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ - #define ETH_DMABMR_PBL_2Beat ((unsigned int)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ - #define ETH_DMABMR_PBL_4Beat ((unsigned int)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_8Beat ((unsigned int)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_16Beat ((unsigned int)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_32Beat ((unsigned int)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_4Beat ((unsigned int)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_4xPBL_8Beat ((unsigned int)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_4xPBL_16Beat ((unsigned int)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_4xPBL_32Beat ((unsigned int)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_64Beat ((unsigned int)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ - #define ETH_DMABMR_PBL_4xPBL_128Beat ((unsigned int)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ -#define ETH_DMABMR_EDE ((unsigned int)0x00000080) /* Enhanced Descriptor Enable */ -#define ETH_DMABMR_DSL ((unsigned int)0x0000007C) /* Descriptor Skip Length */ -#define ETH_DMABMR_DA ((unsigned int)0x00000002) /* DMA arbitration scheme */ -#define ETH_DMABMR_SR ((unsigned int)0x00000001) /* Software reset */ - -#define ETH_DMATPDR_TPD ((unsigned int)0xFFFFFFFF) /* Transmit poll demand */ - -#define ETH_DMARPDR_RPD ((unsigned int)0xFFFFFFFF) /* Receive poll demand */ - -#define ETH_DMARDLAR_SRL ((unsigned int)0xFFFFFFFF) /* Start of receive list */ - -#define ETH_DMATDLAR_STL ((unsigned int)0xFFFFFFFF) /* Start of transmit list */ - -#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ -#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ -#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ -#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ - #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ - #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ - #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ - #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ - #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ - #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ - #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ - #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ - #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ -#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ - #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ - #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ - #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ - #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ - #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ - #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ -#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ -#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ -#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ -#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ -#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ -#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ -#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ -#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ -#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ -#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ -#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ -#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ -#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ -#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ -#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ - -#define ETH_DMAOMR_DTCEFD ((unsigned int)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ -#define ETH_DMAOMR_RSF ((unsigned int)0x02000000) /* Receive store and forward */ -#define ETH_DMAOMR_DFRF ((unsigned int)0x01000000) /* Disable flushing of received frames */ -#define ETH_DMAOMR_TSF ((unsigned int)0x00200000) /* Transmit store and forward */ -#define ETH_DMAOMR_FTF ((unsigned int)0x00100000) /* Flush transmit FIFO */ -#define ETH_DMAOMR_TTC ((unsigned int)0x0001C000) /* Transmit threshold control */ - #define ETH_DMAOMR_TTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ - #define ETH_DMAOMR_TTC_128Bytes ((unsigned int)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ - #define ETH_DMAOMR_TTC_192Bytes ((unsigned int)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ - #define ETH_DMAOMR_TTC_256Bytes ((unsigned int)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ - #define ETH_DMAOMR_TTC_40Bytes ((unsigned int)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ - #define ETH_DMAOMR_TTC_32Bytes ((unsigned int)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ - #define ETH_DMAOMR_TTC_24Bytes ((unsigned int)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ - #define ETH_DMAOMR_TTC_16Bytes ((unsigned int)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ -#define ETH_DMAOMR_ST ((unsigned int)0x00002000) /* Start/stop transmission command */ -#define ETH_DMAOMR_FEF ((unsigned int)0x00000080) /* Forward error frames */ -#define ETH_DMAOMR_FUGF ((unsigned int)0x00000040) /* Forward undersized good frames */ -#define ETH_DMAOMR_RTC ((unsigned int)0x00000018) /* receive threshold control */ - #define ETH_DMAOMR_RTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ - #define ETH_DMAOMR_RTC_32Bytes ((unsigned int)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ - #define ETH_DMAOMR_RTC_96Bytes ((unsigned int)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ - #define ETH_DMAOMR_RTC_128Bytes ((unsigned int)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ -#define ETH_DMAOMR_OSF ((unsigned int)0x00000004) /* operate on second frame */ -#define ETH_DMAOMR_SR ((unsigned int)0x00000002) /* Start/stop receive */ - -#define ETH_DMAIER_NISE ((unsigned int)0x00010000) /* Normal interrupt summary enable */ -#define ETH_DMAIER_AISE ((unsigned int)0x00008000) /* Abnormal interrupt summary enable */ -#define ETH_DMAIER_ERIE ((unsigned int)0x00004000) /* Early receive interrupt enable */ -#define ETH_DMAIER_FBEIE ((unsigned int)0x00002000) /* Fatal bus error interrupt enable */ -#define ETH_DMAIER_ETIE ((unsigned int)0x00000400) /* Early transmit interrupt enable */ -#define ETH_DMAIER_RWTIE ((unsigned int)0x00000200) /* Receive watchdog timeout interrupt enable */ -#define ETH_DMAIER_RPSIE ((unsigned int)0x00000100) /* Receive process stopped interrupt enable */ -#define ETH_DMAIER_RBUIE ((unsigned int)0x00000080) /* Receive buffer unavailable interrupt enable */ -#define ETH_DMAIER_RIE ((unsigned int)0x00000040) /* Receive interrupt enable */ -#define ETH_DMAIER_TUIE ((unsigned int)0x00000020) /* Transmit Underflow interrupt enable */ -#define ETH_DMAIER_ROIE ((unsigned int)0x00000010) /* Receive Overflow interrupt enable */ -#define ETH_DMAIER_TJTIE ((unsigned int)0x00000008) /* Transmit jabber timeout interrupt enable */ -#define ETH_DMAIER_TBUIE ((unsigned int)0x00000004) /* Transmit buffer unavailable interrupt enable */ -#define ETH_DMAIER_TPSIE ((unsigned int)0x00000002) /* Transmit process stopped interrupt enable */ -#define ETH_DMAIER_TIE ((unsigned int)0x00000001) /* Transmit interrupt enable */ - -#define ETH_DMAMFBOCR_OFOC ((unsigned int)0x10000000) /* Overflow bit for FIFO overflow counter */ -#define ETH_DMAMFBOCR_MFA ((unsigned int)0x0FFE0000) /* Number of frames missed by the application */ -#define ETH_DMAMFBOCR_OMFC ((unsigned int)0x00010000) /* Overflow bit for missed frame counter */ -#define ETH_DMAMFBOCR_MFC ((unsigned int)0x0000FFFF) /* Number of frames missed by the controller */ - -#define ETH_DMACHTDR_HTDAP ((unsigned int)0xFFFFFFFF) /* Host transmit descriptor address pointer */ -#define ETH_DMACHRDR_HRDAP ((unsigned int)0xFFFFFFFF) /* Host receive descriptor address pointer */ -#define ETH_DMACHTBAR_HTBAP ((unsigned int)0xFFFFFFFF) /* Host transmit buffer address pointer */ -#define ETH_DMACHRBAR_HRBAP ((unsigned int)0xFFFFFFFF) /* Host receive buffer address pointer */ - - -#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ -#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ - -/* ETHERNET MACMIIAR register Mask */ -#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) - -/* ETHERNET MACCR register Mask */ -#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) - -/* ETHERNET MACFCR register Mask */ -#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) - -/* ETHERNET DMAOMR register Mask */ -#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) - -/* ETHERNET Remote Wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8 - -/* ETHERNET Missed frames counter Shift */ -#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 - -/* ETHERNET DMA Tx descriptors Collision Count Shift */ -#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 - -/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ -#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 - -/* ETHERNET DMA Rx descriptors Frame Length Shift */ -#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 - -/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ -#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 - -/* ETHERNET errors */ -#define ETH_ERROR ((uint32_t)0) -#define ETH_SUCCESS ((uint32_t)1) - - -void ETH_DeInit(void); -void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); -void ETH_SoftwareReset(void); -FlagStatus ETH_GetSoftwareResetStatus(void); -FlagStatus ETH_GetlinkStaus (void); -void ETH_Start(void); -uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength); -void delay_clk (uint32_t nCount); -void printf_dmasr (void); -void print_dmasr_tbus(void); -void print_dmasr_rps(void); -void print_dmasr_tps(void); -uint32_t ETH_HandleRxPkt(uint8_t *ppkt); -uint32_t ETH_GetRxPktSize(void); -void ETH_DropRxPkt(void); -uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg); -uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue); -uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState); - -void ETH_MACTransmissionCmd(FunctionalState NewState); -void ETH_MACReceptionCmd(FunctionalState NewState); -FlagStatus ETH_GetFlowControlBusyStatus(void); -void ETH_InitiatePauseControlFrame(void); -void ETH_BackPressureActivationCmd(FunctionalState NewState); -FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); -ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); -void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); -void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr); -void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr); -void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); -void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); -void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); - -void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount); -void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount); -FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); -uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); -void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); -void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); -void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment); -void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); -void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); -void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); -void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); -void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); -void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); -void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); -void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); -void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount); -FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); -void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); -uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); -void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); -void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); -void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); -uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); - -FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); -void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); -ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); -void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); -uint32_t ETH_GetTransmitProcessState(void); -uint32_t ETH_GetReceiveProcessState(void); -void ETH_FlushTransmitFIFO(void); -FlagStatus ETH_GetFlushTransmitFIFOStatus(void); -void ETH_DMATransmissionCmd(FunctionalState NewState); -void ETH_DMAReceptionCmd(FunctionalState NewState); -void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); -FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); -uint32_t ETH_GetRxOverflowMissedFrameCounter(void); -uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); -uint32_t ETH_GetCurrentTxDescStartAddress(void); -uint32_t ETH_GetCurrentRxDescStartAddress(void); -uint32_t ETH_GetCurrentTxBufferAddress(void); -uint32_t ETH_GetCurrentRxBufferAddress(void); -void ETH_ResumeDMATransmission(void); -void ETH_ResumeDMAReception(void); - -void ETH_ResetWakeUpFrameFilterRegisterPointer(void); -void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); -void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); -FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); -void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); -void ETH_MagicPacketDetectionCmd(FunctionalState NewState); -void ETH_PowerDownCmd(FunctionalState NewState); - -void ETH_MMCCounterFreezeCmd(FunctionalState NewState); -void ETH_MMCResetOnReadCmd(FunctionalState NewState); -void ETH_MMCCounterRolloverCmd(FunctionalState NewState); -void ETH_MMCCountersReset(void); -void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); -ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); -uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); - -uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab); -uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab); -void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); -void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); -void ETH_EnablePTPTimeStampAddend(void); -void ETH_EnablePTPTimeStampInterruptTrigger(void); -void ETH_EnablePTPTimeStampUpdate(void); -void ETH_InitializePTPTimeStamp(void); -void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod); -void ETH_PTPTimeStampCmd(FunctionalState NewState); -FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG); -void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue); -void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue); -void ETH_SetPTPTimeStampAddend(uint32_t Value); -void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue); -uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg); -void RGMII_TXC_Delay(uint8_t clock_polarity,uint8_t delay_time); - -#ifdef __cplusplus -} -#endif - -#endif - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_eth.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* ETH firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_ETH_H +#define __CH32V30x_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +#define PHY_10BASE_T_LINKED 1 +#define PHY_10BASE_T_NOT_LINKED 0 + +#define DMA_TPS_Mask ((uint32_t)0x00700000) +#define DMA_RPS_Mask ((uint32_t)0x000E0000) + +/* ETH Init structure definition */ +typedef struct { + uint32_t ETH_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex). + This parameter can be a value of @ref ETH_AutoNegotiation */ + + uint32_t ETH_Watchdog; /* Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref ETH_watchdog */ + + uint32_t ETH_Jabber; /* Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref ETH_Jabber */ + + uint32_t ETH_InterFrameGap; /* Selects the minimum IFG between frames during transmission + This parameter can be a value of @ref ETH_Inter_Frame_Gap */ + + uint32_t ETH_CarrierSense; /* Selects or not the Carrier Sense + This parameter can be a value of @ref ETH_Carrier_Sense */ + + uint32_t ETH_Speed; /* Sets the Ethernet speed: 10/100 Mbps + This parameter can be a value of @ref ETH_Speed */ + + uint32_t ETH_ReceiveOwn; /* Selects or not the ReceiveOwn + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode + This parameter can be a value of @ref ETH_Receive_Own */ + + uint32_t ETH_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode + This parameter can be a value of @ref ETH_Loop_Back_Mode */ + + uint32_t ETH_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref ETH_Duplex_Mode */ + + uint32_t ETH_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. + This parameter can be a value of @ref ETH_Checksum_Offload */ + + uint32_t ETH_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a colision occurs (Half-Duplex mode) + This parameter can be a value of @ref ETH_Retry_Transmission */ + + uint32_t ETH_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping + This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ + + uint32_t ETH_BackOffLimit; /* Selects the BackOff limit value + This parameter can be a value of @ref ETH_Back_Off_Limit */ + + uint32_t ETH_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode) + This parameter can be a value of @ref ETH_Deferral_Check */ + + uint32_t ETH_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering) + This parameter can be a value of @ref ETH_Receive_All */ + + uint32_t ETH_SourceAddrFilter; /* Selects the Source Address Filter mode + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + + uint32_t ETH_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + This parameter can be a value of @ref ETH_Pass_Control_Frames */ + + uint32_t ETH_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames + This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ + + uint32_t ETH_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + + uint32_t ETH_PromiscuousMode; /* Selects or not the Promiscuous Mode + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + + uint32_t ETH_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ + + uint32_t ETH_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ + + uint32_t ETH_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */ + + uint32_t ETH_HashTableLow; /* This field holds the lower 32 bits of Hash table. */ + + uint32_t ETH_PauseTime; /* This field holds the value to be used in the Pause Time field in the + transmit control frame */ + + uint32_t ETH_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames + This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ + + uint32_t ETH_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame + This parameter can be a value of @ref ETH_Pause_Low_Threshold */ + + uint32_t ETH_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address) + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + + uint32_t ETH_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + + uint32_t ETH_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + + uint32_t ETH_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering + This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ + + uint32_t ETH_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */ + + uint32_t ETH_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames + This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ + + uint32_t ETH_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode + This parameter can be a value of @ref ETH_Receive_Store_Forward */ + + uint32_t ETH_FlushReceivedFrame; /* Enables or disables the flushing of received frames + This parameter can be a value of @ref ETH_Flush_Received_Frame */ + + uint32_t ETH_TransmitStoreForward; /* Enables or disables Transmit store and forward mode + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + + uint32_t ETH_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control + This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ + + uint32_t ETH_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames + This parameter can be a value of @ref ETH_Forward_Error_Frames */ + + uint32_t ETH_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ + + uint32_t ETH_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO + This parameter can be a value of @ref ETH_Receive_Threshold_Control */ + + uint32_t ETH_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. + This parameter can be a value of @ref ETH_Second_Frame_Operate */ + + uint32_t ETH_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats + This parameter can be a value of @ref ETH_Address_Aligned_Beats */ + + uint32_t ETH_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers + This parameter can be a value of @ref ETH_Fixed_Burst */ + + uint32_t ETH_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction + This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ + + uint32_t ETH_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction + This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ + + uint32_t ETH_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */ + + uint32_t ETH_DMAArbitration; /* Selects the DMA Tx/Rx arbitration + This parameter can be a value of @ref ETH_DMA_Arbitration */ +}ETH_InitTypeDef; + + + +/* ETH delay.Just for Ethernet */ +#define _eth_delay_ ETH_Delay /* Default _eth_delay_ function with less precise timing */ + +/* definition for Ethernet frame */ +#define ETH_MAX_PACKET_SIZE 1536 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /* Ethernet CRC */ +#define ETH_EXTRA 2 /* Extra bytes in some cases */ +#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ + +/* ETH DMA structure definition */ +typedef struct +{ + uint32_t volatile Status; /* Status */ + uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /* Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ +} ETH_DMADESCTypeDef; + +/** + DMA Tx Desciptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ------------------------------------------------------------------------------------------------ +*/ + + +/* Bit or field definition of TDES0 register (DMA Tx descriptor status register)*/ +#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /* Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /* Last Segment */ +#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /* First Segment */ +#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /* Disable CRC */ +#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /* Disable Padding */ +#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /* Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /* Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /* Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /* IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /* Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /* Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /* Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /* IP Header Error */ +#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /* Jabber Timeout */ +#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /* Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /* No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /* Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /* VLAN Frame */ +#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /* Collision Count */ +#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /* Excessive Deferral */ +#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /* Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /* Deferred Bit */ + +/* Field definition of TDES1 register */ +#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /* Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /* Transmit Buffer1 Size */ + +/* Field definition of TDES2 register */ +#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of TDES3 register */ +#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/** + DMA Rx Desciptor + --------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ---------------------------------------------------------------------------------------------------------------------- +*/ + +/* Bit or field definition of RDES0 register (DMA Rx descriptor status register) */ +#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /* DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /* Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /* Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /* SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /* Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /* VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /* First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /* Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /* IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /* Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /* Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /* CRC error */ +#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/* Bit or field definition of RDES1 register */ +#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /* Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /* Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /* Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /* Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /* Receive Buffer1 Size */ + +/* Field definition of RDES2 register */ +#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of RDES3 register */ +#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/* Timeout threshold of Reading or writing PHY registers */ +#define PHY_READ_TO ((uint32_t)0x004FFFFF) +#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) + +/* Delay time after reset PHY */ +#define PHY_ResetDelay ((uint32_t)0x000FFFFF) + +/* Delay time after configure PHY */ +#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) + +/* PHY basic register */ +#define PHY_BCR 0x0 /*PHY transceiver Basic Control Register */ +#define PHY_BSR 0x01 /*PHY transceiver Basic Status Register*/ +#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisement Register */ +#define PHY_ANLPAR 0x05 /* Auto-Negotiation Link Partner Base Page Ability Register*/ +#define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ +#define PHY_BMCR PHY_BCR +#define PHY_BMSR PHY_BSR +#define PHY_STATUS 0x10 +#define PHY_MDIX 0x1E + +/* Bit or field definition for PHY basic control register */ +#define PHY_Reset ((uint16_t)0x8000) /* PHY Reset */ +#define PHY_Loopback ((uint16_t)0x4000) /* Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /* Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /* Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /* Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /* Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((uint16_t)0x1000) /* Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /* Restart auto-negotiation function */ +#define PHY_Powerdown ((uint16_t)0x0800) /* Select the power down mode */ +#define PHY_Isolate ((uint16_t)0x0400) /* Isolate PHY from MII */ + +/* Bit or field definition for PHY basic status register */ +#define PHY_AutoNego_Complete ((uint16_t)0x0020) /* Auto-Negotioation process completed */ +#define PHY_Linked_Status ((uint16_t)0x0004) /* Valid link established */ +#define PHY_Jabber_detection ((uint16_t)0x0002) /* Jabber condition detected */ +#define PHY_RMII_Mode ((uint16_t)0x0020) /* RMII */ + + +/* Internal 10BASE-T PHY 50R*4 pull-up resistance enable or disable */ +#define ETH_Internal_Pull_Up_Res_Enable ((uint32_t)0x00100000) +#define ETH_Internal_Pull_Up_Res_Disable ((uint32_t)0x00000000) + +/* MAC autoNegotiation enable or disable */ +#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) +#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) + +/* MAC watchdog enable or disable */ +#define ETH_Watchdog_Enable ((uint32_t)0x00000000) +#define ETH_Watchdog_Disable ((uint32_t)0x00800000) + +/* Bit description - MAC jabber enable or disable */ +#define ETH_Jabber_Enable ((uint32_t)0x00000000) +#define ETH_Jabber_Disable ((uint32_t)0x00400000) + +/* Value of minimum IFG between frames during transmission */ +#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /* minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /* minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /* minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /* minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /* minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */ + +/* MAC carrier sense enable or disable */ +#define ETH_CarrierSense_Enable ((uint32_t)0x00000000) +#define ETH_CarrierSense_Disable ((uint32_t)0x00010000) + +/* MAC speed */ +#define ETH_Speed_10M ((uint32_t)0x00000000) +#define ETH_Speed_100M ((uint32_t)0x00004000) +#define ETH_Speed_1000M ((uint32_t)0x00008000) + +/* MAC receive own enable or disable */ +#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) +#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) + +/* MAC Loopback mode enable or disable */ +#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) +#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) + +/* MAC fullDuplex or halfDuplex */ +#define ETH_Mode_FullDuplex ((uint32_t)0x00000800) +#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) + +/* MAC offload checksum enable or disable */ +#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) +#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) + +/* MAC transmission retry enable or disable */ +#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) +#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) + +/* MAC automatic pad CRC strip enable or disable */ +#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) + +/* MAC backoff limitation */ +#define ETH_BackOffLimit_10 ((uint32_t)0x00000000) +#define ETH_BackOffLimit_8 ((uint32_t)0x00000020) +#define ETH_BackOffLimit_4 ((uint32_t)0x00000040) +#define ETH_BackOffLimit_1 ((uint32_t)0x00000060) + +/* MAC deferral check enable or disable */ +#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) +#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) + +/* Bit description : MAC receive all frame enable or disable */ +#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) +#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) + +/* MAC backoff limitation */ +#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) +#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) + +/* MAC Pass control frames */ +#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ + +/* MAC broadcast frames reception */ +#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) + +/* MAC destination address filter */ +#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) + +/* MAC Promiscuous mode enable or disable */ +#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) +#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) + +/* MAC multicast frames filter */ +#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) +#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) + +/* MAC unicast frames filter */ +#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) + +/* Bit description : MAC zero quanta pause */ +#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) + +/* Field description : MAC pause low threshold */ +#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ + +/* MAC unicast pause frame detect enable or disable*/ +#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) + +/* MAC receive flow control frame enable or disable */ +#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) + +/* MAC transmit flow control enable or disable */ +#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) +#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) + +/* MAC VLAN tag comparison */ +#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) +#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) + +/* MAC flag */ +#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /* Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /* MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /* MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /* MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /* PMT flag (on MAC) */ + +/* MAC interrupt */ +#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /* Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /* MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /* MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /* MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /* PMT interrupt (on MAC) */ + +/* MAC address */ +#define ETH_MAC_Address0 ((uint32_t)0x00000000) +#define ETH_MAC_Address1 ((uint32_t)0x00000008) +#define ETH_MAC_Address2 ((uint32_t)0x00000010) +#define ETH_MAC_Address3 ((uint32_t)0x00000018) + +/* MAC address filter select */ +#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) +#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) + +/* MAC address mask */ +#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ + + +/******************************************************************************/ +/* */ +/* MAC Descriptor Register */ +/* */ +/******************************************************************************/ + +/* DMA descriptor segment */ +#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /* Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /* First Segment */ + +/* DMA descriptor checksum setting */ +#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /* Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /* IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + +/* DMA RX & TX buffer */ +#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /* DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /* DMA Rx Desc Buffer2 */ + + +/******************************************************************************/ +/* */ +/* ETH DMA Register */ +/* */ +/******************************************************************************/ + +/* DMA drop TCPIP checksum error frame enable or disable */ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) + +/* DMA receive store forward enable or disable */ +#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) + +/* DMA flush received frame enable or disable */ +#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) + +/* DMA transmit store forward enable or disable */ +#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) +#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) + +/* DMA transmit threshold control */ +#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ + +/* DMA forward error frames */ +#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) + +/* DMA forward undersized good frames enable or disable */ +#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) + +/* DMA receive threshold control */ +#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ + +/* DMA second frame operate enable or disable */ +#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) +#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) + +/* Address aligned beats enable or disable */ +#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) + +/* DMA Fixed burst enable or disable */ +#define ETH_FixedBurst_Enable ((uint32_t)0x00010000) +#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) + + +/* RX DMA burst length */ +#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ + + +/* TX DMA burst length */ +#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ + +/* DMA arbitration_round robin */ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) + +/* DMA interrupt FALG */ +#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /* Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /* Early receive flag */ +#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /* Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /* Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /* Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /* Receive flag */ +#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /* Underflow flag */ +#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /* Overflow flag */ +#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /* Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /* Transmit flag */ + +/* DMA interrupt */ +#define ETH_DMA_IT_PHYLINK ((uint32_t)0x80000000) /* Internal PHY link status change interrupt */ +#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /* Early receive interrupt */ +#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /* Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /* Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /* Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((uint32_t)0x00000040) /* Receive interrupt */ +#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /* Underflow interrupt */ +#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /* Overflow interrupt */ +#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /* Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((uint32_t)0x00000001) /* Transmit interrupt */ + +/* DMA transmit process */ +#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ + +/* DMA receive Process */ +#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ + +/* DMA overflow */ +#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ + + +/********************************************************************************* +* Ethernet PMT defines +**********************************************************************************/ + +/* PMT flag */ +#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ + +/********************************************************************************* +* Ethernet MMC defines +**********************************************************************************/ + +/* MMC TX interrupt flag */ +#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /* When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /* When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /* When Tx good single col counter reaches half the maximum value */ + +/* MMC RX interrupt flag */ +#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /* When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /* When Rx crc error counter reaches half the maximum value */ + + +/* MMC description */ +#define ETH_MMCCR ((uint32_t)0x00000100) /* MMC CR register */ +#define ETH_MMCRIR ((uint32_t)0x00000104) /* MMC RIR register */ +#define ETH_MMCTIR ((uint32_t)0x00000108) /* MMC TIR register */ +#define ETH_MMCRIMR ((uint32_t)0x0000010C) /* MMC RIMR register */ +#define ETH_MMCTIMR ((uint32_t)0x00000110) /* MMC TIMR register */ +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /* MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /* MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((uint32_t)0x00000168) /* MMC TGFCR register */ +#define ETH_MMCRFCECR ((uint32_t)0x00000194) /* MMC RFCECR register */ +#define ETH_MMCRFAECR ((uint32_t)0x00000198) /* MMC RFAECR register */ +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /* MMC RGUFCR register */ + + +/********************************************************************************* +* Ethernet PTP defines +**********************************************************************************/ + +/* PTP fine update method or coarse Update method */ +#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /* Fine Update method */ +#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /* Coarse Update method */ + + +/* PTP time stamp control */ +#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /* Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /* Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /* Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /* Time Stamp Initialize */ + +/* PTP positive/negative time value */ +#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /* Positive time value */ +#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /* Negative time value */ + + +/******************************************************************************/ +/* */ +/* PTP Register */ +/* */ +/******************************************************************************/ +#define ETH_PTPTSCR ((uint32_t)0x00000700) /* PTP TSCR register */ +#define ETH_PTPSSIR ((uint32_t)0x00000704) /* PTP SSIR register */ +#define ETH_PTPTSHR ((uint32_t)0x00000708) /* PTP TSHR register */ +#define ETH_PTPTSLR ((uint32_t)0x0000070C) /* PTP TSLR register */ +#define ETH_PTPTSHUR ((uint32_t)0x00000710) /* PTP TSHUR register */ +#define ETH_PTPTSLUR ((uint32_t)0x00000714) /* PTP TSLUR register */ +#define ETH_PTPTSAR ((uint32_t)0x00000718) /* PTP TSAR register */ +#define ETH_PTPTTHR ((uint32_t)0x0000071C) /* PTP TTHR register */ +#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ + +#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ + #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ + + +/******************************************************************************/ +/* */ +/* ETH MAC Register */ +/* */ +/******************************************************************************/ +#define ETH_MACCR_WD ((unsigned int)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((unsigned int)0x00400000) /* Jabber disable */ +#define ETH_MACCR_IFG ((unsigned int)0x000E0000) /* Inter-frame gap */ +#define ETH_MACCR_IFG_96Bit ((unsigned int)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ + #define ETH_MACCR_IFG_88Bit ((unsigned int)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ + #define ETH_MACCR_IFG_80Bit ((unsigned int)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ + #define ETH_MACCR_IFG_72Bit ((unsigned int)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ + #define ETH_MACCR_IFG_64Bit ((unsigned int)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ + #define ETH_MACCR_IFG_56Bit ((unsigned int)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ + #define ETH_MACCR_IFG_48Bit ((unsigned int)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ + #define ETH_MACCR_IFG_40Bit ((unsigned int)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((unsigned int)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((unsigned int)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((unsigned int)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((unsigned int)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((unsigned int)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((unsigned int)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((unsigned int)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((unsigned int)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((unsigned int)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before reschedulinga transmission attempt during retries after a collision: 0 =< r <2^k */ + #define ETH_MACCR_BL_10 ((unsigned int)0x00000000) /* k = min (n, 10) */ + #define ETH_MACCR_BL_8 ((unsigned int)0x00000020) /* k = min (n, 8) */ + #define ETH_MACCR_BL_4 ((unsigned int)0x00000040) /* k = min (n, 4) */ + #define ETH_MACCR_BL_1 ((unsigned int)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((unsigned int)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((unsigned int)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((unsigned int)0x00000004) /* Receiver enable */ + +#define ETH_MACFFR_RA ((unsigned int)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((unsigned int)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((unsigned int)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((unsigned int)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((unsigned int)0x000000C0) /* Pass control frames: 3 cases */ + #define ETH_MACFFR_PCF_BlockAll ((unsigned int)0x00000040) /* MAC filters all control frames from reaching the application */ + #define ETH_MACFFR_PCF_ForwardAll ((unsigned int)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ + #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((unsigned int)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((unsigned int)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((unsigned int)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((unsigned int)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((unsigned int)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((unsigned int)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((unsigned int)0x00000001) /* Promiscuous mode */ + +#define ETH_MACHTHR_HTH ((unsigned int)0xFFFFFFFF) /* Hash table high */ +#define ETH_MACHTLR_HTL ((unsigned int)0xFFFFFFFF) /* Hash table low */ + +#define ETH_MACMIIAR_PA ((unsigned int)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((unsigned int)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((unsigned int)0x0000001C) /* CR clock range: 6 cases */ + #define ETH_MACMIIAR_CR_Div42 ((unsigned int)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ + #define ETH_MACMIIAR_CR_Div16 ((unsigned int)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ETH_MACMIIAR_CR_Div26 ((unsigned int)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((unsigned int)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((unsigned int)0x00000001) /* MII busy */ +#define ETH_MACMIIDR_MD ((unsigned int)0x0000FFFF) /* MII data: read/write data from/to PHY */ +#define ETH_MACFCR_PT ((unsigned int)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((unsigned int)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((unsigned int)0x00000030) /* Pause low threshold: 4 cases */ + #define ETH_MACFCR_PLT_Minus4 ((unsigned int)0x00000000) /* Pause time minus 4 slot times */ + #define ETH_MACFCR_PLT_Minus28 ((unsigned int)0x00000010) /* Pause time minus 28 slot times */ + #define ETH_MACFCR_PLT_Minus144 ((unsigned int)0x00000020) /* Pause time minus 144 slot times */ + #define ETH_MACFCR_PLT_Minus256 ((unsigned int)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((unsigned int)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((unsigned int)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((unsigned int)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((unsigned int)0x00000001) /* Flow control busy/backpressure activate */ + +#define ETH_MACVLANTR_VLANTC ((unsigned int)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((unsigned int)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +#define ETH_MACRWUFFR_D ((unsigned int)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. +Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ + +/* +Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask +Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask +Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask +Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask +Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command +Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset +Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 +Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +#define ETH_MACPMTCSR_WFFRPR ((unsigned int)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((unsigned int)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((unsigned int)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((unsigned int)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((unsigned int)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((unsigned int)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((unsigned int)0x00000001) /* Power Down */ + +#define ETH_MACSR_TSTS ((unsigned int)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((unsigned int)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((unsigned int)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((unsigned int)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((unsigned int)0x00000008) /* PMT status */ + +#define ETH_MACIMR_TSTIM ((unsigned int)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((unsigned int)0x00000008) /* PMT interrupt mask */ + +#define ETH_MACA0HR_MACA0H ((unsigned int)0x0000FFFF) /* MAC address0 high */ + +#define ETH_MACA0LR_MACA0L ((unsigned int)0xFFFFFFFF) /* MAC address0 low */ + +#define ETH_MACA1HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((unsigned int)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ + #define ETH_MACA1HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA1HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA1HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA1HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA1HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA1HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((unsigned int)0x0000FFFF) /* MAC address1 high */ + +#define ETH_MACA1LR_MACA1L ((unsigned int)0xFFFFFFFF) /* MAC address1 low */ + +#define ETH_MACA2HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ + +#define ETH_MACA2HR_MACA2H ((unsigned int)0x0000FFFF) /* MAC address1 high */ +#define ETH_MACA2LR_MACA2L ((unsigned int)0xFFFFFFFF) /* MAC address2 low */ + +#define ETH_MACA3HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ + #define ETH_MACA3HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA3HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA3HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA3HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA3HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA3HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((unsigned int)0x0000FFFF) /* MAC address3 high */ +#define ETH_MACA3LR_MACA3L ((unsigned int)0xFFFFFFFF) /* MAC address3 low */ + +/******************************************************************************/ +/* +/* ETH MMC Register +/* +/******************************************************************************/ +#define ETH_MMCCR_MCFHP ((unsigned int)0x00000020) /* MMC counter Full-Half preset */ +#define ETH_MMCCR_MCP ((unsigned int)0x00000010) /* MMC counter preset */ +#define ETH_MMCCR_MCF ((unsigned int)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((unsigned int)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((unsigned int)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((unsigned int)0x00000001) /* Counters Reset */ + +#define ETH_MMCRIR_RGUFS ((unsigned int)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((unsigned int)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((unsigned int)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +#define ETH_MMCTIR_TGFS ((unsigned int)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((unsigned int)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((unsigned int)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +#define ETH_MMCRIMR_RGUFM ((unsigned int)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((unsigned int)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((unsigned int)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +#define ETH_MMCTIMR_TGFM ((unsigned int)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((unsigned int)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((unsigned int)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +#define ETH_MMCTGFSCCR_TGFSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +#define ETH_MMCTGFMSCCR_TGFMSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +#define ETH_MMCTGFCR_TGFC ((unsigned int)0xFFFFFFFF) /* Number of good frames transmitted. */ + +#define ETH_MMCRFCECR_RFCEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +#define ETH_MMCRFAECR_RFAEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +#define ETH_MMCRGUFCR_RGUFC ((unsigned int)0xFFFFFFFF) /* Number of good unicast frames received. */ + + +/******************************************************************************/ +/* +/* ETH Precise Clock Protocol Register +/* +/******************************************************************************/ +#define ETH_PTPTSCR_TSCNT ((unsigned int)0x00030000) /* Time stamp clock node type */ +#define ETH_PTPTSSR_TSSMRME ((unsigned int)0x00008000) /* Time stamp snapshot for message relevant to master enable */ +#define ETH_PTPTSSR_TSSEME ((unsigned int)0x00004000) /* Time stamp snapshot for event message enable */ +#define ETH_PTPTSSR_TSSIPV4FE ((unsigned int)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTPTSSR_TSSIPV6FE ((unsigned int)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTPTSSR_TSSPTPOEFE ((unsigned int)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTPTSSR_TSPTPPSV2E ((unsigned int)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ +#define ETH_PTPTSSR_TSSSR ((unsigned int)0x00000200) /* Time stamp Sub-seconds rollover */ +#define ETH_PTPTSSR_TSSARFE ((unsigned int)0x00000100) /* Time stamp snapshot for all received frames enable */ + +#define ETH_PTPTSCR_TSARU ((unsigned int)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((unsigned int)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((unsigned int)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((unsigned int)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((unsigned int)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((unsigned int)0x00000001) /* Time stamp enable */ + +#define ETH_PTPSSIR_STSSI ((unsigned int)0x000000FF) /* System time Sub-second increment value */ + +#define ETH_PTPTSHR_STS ((unsigned int)0xFFFFFFFF) /* System Time second */ + +#define ETH_PTPTSLR_STPNS ((unsigned int)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((unsigned int)0x7FFFFFFF) /* System Time sub-seconds */ + +#define ETH_PTPTSHUR_TSUS ((unsigned int)0xFFFFFFFF) /* Time stamp update seconds */ + +#define ETH_PTPTSLUR_TSUPNS ((unsigned int)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((unsigned int)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +#define ETH_PTPTSAR_TSA ((unsigned int)0xFFFFFFFF) /* Time stamp addend */ + +#define ETH_PTPTTHR_TTSH ((unsigned int)0xFFFFFFFF) /* Target time stamp high */ + +#define ETH_PTPTTLR_TTSL ((unsigned int)0xFFFFFFFF) /* Target time stamp low */ + +#define ETH_PTPTSSR_TSTTR ((unsigned int)0x00000020) /* Time stamp target time reached */ +#define ETH_PTPTSSR_TSSO ((unsigned int)0x00000010) /* Time stamp seconds overflow */ + +/******************************************************************************/ +/* +/* ETH DMA Register +/* +/******************************************************************************/ +#define ETH_DMABMR_AAB ((unsigned int)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((unsigned int)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((unsigned int)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((unsigned int)0x007E0000) /* RxDMA PBL */ + #define ETH_DMABMR_RDP_1Beat ((unsigned int)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ + #define ETH_DMABMR_RDP_2Beat ((unsigned int)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ + #define ETH_DMABMR_RDP_4Beat ((unsigned int)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_8Beat ((unsigned int)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_16Beat ((unsigned int)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_32Beat ((unsigned int)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_4Beat ((unsigned int)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_4xPBL_8Beat ((unsigned int)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_4xPBL_16Beat ((unsigned int)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_4xPBL_32Beat ((unsigned int)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_64Beat ((unsigned int)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ + #define ETH_DMABMR_RDP_4xPBL_128Beat ((unsigned int)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((unsigned int)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_1_1 ((unsigned int)0x00000000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_2_1 ((unsigned int)0x00004000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_3_1 ((unsigned int)0x00008000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_4_1 ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((unsigned int)0x00003F00) /* Programmable burst length */ + #define ETH_DMABMR_PBL_1Beat ((unsigned int)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ + #define ETH_DMABMR_PBL_2Beat ((unsigned int)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ + #define ETH_DMABMR_PBL_4Beat ((unsigned int)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_8Beat ((unsigned int)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_16Beat ((unsigned int)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_32Beat ((unsigned int)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_4Beat ((unsigned int)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_4xPBL_8Beat ((unsigned int)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_4xPBL_16Beat ((unsigned int)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_4xPBL_32Beat ((unsigned int)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_64Beat ((unsigned int)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ + #define ETH_DMABMR_PBL_4xPBL_128Beat ((unsigned int)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_EDE ((unsigned int)0x00000080) /* Enhanced Descriptor Enable */ +#define ETH_DMABMR_DSL ((unsigned int)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((unsigned int)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((unsigned int)0x00000001) /* Software reset */ + +#define ETH_DMATPDR_TPD ((unsigned int)0xFFFFFFFF) /* Transmit poll demand */ + +#define ETH_DMARPDR_RPD ((unsigned int)0xFFFFFFFF) /* Receive poll demand */ + +#define ETH_DMARDLAR_SRL ((unsigned int)0xFFFFFFFF) /* Start of receive list */ + +#define ETH_DMATDLAR_STL ((unsigned int)0xFFFFFFFF) /* Start of transmit list */ + +#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ + #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ + +#define ETH_DMAOMR_DTCEFD ((unsigned int)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((unsigned int)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((unsigned int)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((unsigned int)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((unsigned int)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((unsigned int)0x0001C000) /* Transmit threshold control */ + #define ETH_DMAOMR_TTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ + #define ETH_DMAOMR_TTC_128Bytes ((unsigned int)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ + #define ETH_DMAOMR_TTC_192Bytes ((unsigned int)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ + #define ETH_DMAOMR_TTC_256Bytes ((unsigned int)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ + #define ETH_DMAOMR_TTC_40Bytes ((unsigned int)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ + #define ETH_DMAOMR_TTC_32Bytes ((unsigned int)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ + #define ETH_DMAOMR_TTC_24Bytes ((unsigned int)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ + #define ETH_DMAOMR_TTC_16Bytes ((unsigned int)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((unsigned int)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((unsigned int)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((unsigned int)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((unsigned int)0x00000018) /* receive threshold control */ + #define ETH_DMAOMR_RTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ + #define ETH_DMAOMR_RTC_32Bytes ((unsigned int)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ + #define ETH_DMAOMR_RTC_96Bytes ((unsigned int)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ + #define ETH_DMAOMR_RTC_128Bytes ((unsigned int)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((unsigned int)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((unsigned int)0x00000002) /* Start/stop receive */ + +#define ETH_DMAIER_NISE ((unsigned int)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((unsigned int)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((unsigned int)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((unsigned int)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((unsigned int)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((unsigned int)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((unsigned int)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((unsigned int)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((unsigned int)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((unsigned int)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((unsigned int)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((unsigned int)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((unsigned int)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((unsigned int)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((unsigned int)0x00000001) /* Transmit interrupt enable */ + +#define ETH_DMAMFBOCR_OFOC ((unsigned int)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((unsigned int)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((unsigned int)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((unsigned int)0x0000FFFF) /* Number of frames missed by the controller */ + +#define ETH_DMACHTDR_HTDAP ((unsigned int)0xFFFFFFFF) /* Host transmit descriptor address pointer */ +#define ETH_DMACHRDR_HRDAP ((unsigned int)0xFFFFFFFF) /* Host receive descriptor address pointer */ +#define ETH_DMACHTBAR_HTBAP ((unsigned int)0xFFFFFFFF) /* Host transmit buffer address pointer */ +#define ETH_DMACHRBAR_HRBAP ((unsigned int)0xFFFFFFFF) /* Host receive buffer address pointer */ + + +#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ + +/* ETHERNET MACMIIAR register Mask */ +#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) + +/* ETHERNET MACCR register Mask */ +#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) + +/* ETHERNET MACFCR register Mask */ +#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) + +/* ETHERNET DMAOMR register Mask */ +#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) + +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8 + +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 + +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 + +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 + +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET errors */ +#define ETH_ERROR ((uint32_t)0) +#define ETH_SUCCESS ((uint32_t)1) + + +void ETH_DeInit(void); +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); +void ETH_SoftwareReset(void); +FlagStatus ETH_GetSoftwareResetStatus(void); +FlagStatus ETH_GetlinkStaus (void); +void ETH_Start(void); +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength); +void delay_clk (uint32_t nCount); +void printf_dmasr (void); +void print_dmasr_tbus(void); +void print_dmasr_rps(void); +void print_dmasr_tps(void); +uint32_t ETH_HandleRxPkt(uint8_t *ppkt); +uint32_t ETH_GetRxPktSize(void); +void ETH_DropRxPkt(void); +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg); +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue); +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState); + +void ETH_MACTransmissionCmd(FunctionalState NewState); +void ETH_MACReceptionCmd(FunctionalState NewState); +FlagStatus ETH_GetFlowControlBusyStatus(void); +void ETH_InitiatePauseControlFrame(void); +void ETH_BackPressureActivationCmd(FunctionalState NewState); +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr); +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr); +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); + +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount); +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount); +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment); +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount); +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); + +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); +uint32_t ETH_GetTransmitProcessState(void); +uint32_t ETH_GetReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +FlagStatus ETH_GetFlushTransmitFIFOStatus(void); +void ETH_DMATransmissionCmd(FunctionalState NewState); +void ETH_DMAReceptionCmd(FunctionalState NewState); +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); +uint32_t ETH_GetRxOverflowMissedFrameCounter(void); +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); +uint32_t ETH_GetCurrentTxDescStartAddress(void); +uint32_t ETH_GetCurrentRxDescStartAddress(void); +uint32_t ETH_GetCurrentTxBufferAddress(void); +uint32_t ETH_GetCurrentRxBufferAddress(void); +void ETH_ResumeDMATransmission(void); +void ETH_ResumeDMAReception(void); + +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); +void ETH_MagicPacketDetectionCmd(FunctionalState NewState); +void ETH_PowerDownCmd(FunctionalState NewState); + +void ETH_MMCCounterFreezeCmd(FunctionalState NewState); +void ETH_MMCResetOnReadCmd(FunctionalState NewState); +void ETH_MMCCounterRolloverCmd(FunctionalState NewState); +void ETH_MMCCountersReset(void); +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); + +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab); +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab); +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +void ETH_EnablePTPTimeStampAddend(void); +void ETH_EnablePTPTimeStampInterruptTrigger(void); +void ETH_EnablePTPTimeStampUpdate(void); +void ETH_InitializePTPTimeStamp(void); +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod); +void ETH_PTPTimeStampCmd(FunctionalState NewState); +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG); +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue); +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue); +void ETH_SetPTPTimeStampAddend(uint32_t Value); +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue); +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg); +void RGMII_TXC_Delay(uint8_t clock_polarity,uint8_t delay_time); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_exti.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_exti.h index 1e65983..438ff82 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_exti.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_exti.h @@ -1,92 +1,92 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_exti.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* EXTI firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_EXTI_H -#define __CH32V30x_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* EXTI mode enumeration */ -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -/* EXTI Trigger enumeration */ -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -/* EXTI Init Structure definition */ -typedef struct -{ - uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - - -/* EXTI_Lines */ -#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD/USBFS OTG - Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */ -#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBHS Wakeup event */ - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_exti.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* EXTI firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_EXTI_H +#define __CH32V30x_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD/USBFS OTG + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBHS Wakeup event */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_flash.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_flash.h index ba58259..ba31c0c 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_flash.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_flash.h @@ -1,144 +1,148 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_flash.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the FLASH -* firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_FLASH_H -#define __CH32V30x_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* FLASH Status */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT -}FLASH_Status; - - -/* Write Protect */ -#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */ - -#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ - -/* Option_Bytes_IWatchdog */ -#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ -#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ - -/* Option_Bytes_nRST_STOP */ -#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ - -/* Option_Bytes_nRST_STDBY */ -#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ - -/* FLASH_Interrupts */ -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ - -/* FLASH_Flags */ -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ - -/* FLASH_Access_CLK */ -#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Access Clock = SYSTEM/2 */ -#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* FLASH Access Clock = SYSTEM */ - - -/*Functions used for all devices*/ -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors); -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); -uint32_t FLASH_GetUserOptionByte(void); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); -void FLASH_Unlock_Fast(void); -void FLASH_Lock_Fast(void); -void FLASH_ErasePage_Fast(uint32_t Page_Address); -void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); -void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address); -void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t* pbuf); -void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK); -void FLASH_Enhance_Mode(FunctionalState NewState); - -/* New function used for all devices */ -void FLASH_UnlockBank1(void); -void FLASH_LockBank1(void); -FLASH_Status FLASH_EraseAllBank1Pages(void); -FLASH_Status FLASH_GetBank1Status(void); -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); - -#ifdef __cplusplus -} -#endif - - -#endif - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_flash.h +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/24 +* Description : This file contains all the functions prototypes for the FLASH +* firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_FLASH_H +#define __CH32V30x_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +}FLASH_Status; + + +/* Write Protect */ +#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 1 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 2 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 3 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 4 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 5 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 6 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 7 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 8 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 9 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 10 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 11 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 12 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 13 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 14 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 15 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 16 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 17 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 18 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 19 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 20 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 21 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 22 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 23 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 24 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 25 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 26 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 27 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 28 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 29 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 30 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 31 to 127 */ + +#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/* FLASH_Access_CLK */ +#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Access Clock = SYSTEM/2 */ +#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* FLASH Access Clock = SYSTEM */ + + +/*Functions used for all devices*/ +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t* pbuf); +void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK); +void FLASH_Enhance_Mode(FunctionalState NewState); + +/* New function used for all devices */ +void FLASH_UnlockBank1(void); +void FLASH_LockBank1(void); +FLASH_Status FLASH_EraseAllBank1Pages(void); +FLASH_Status FLASH_GetBank1Status(void); +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); + +#ifdef __cplusplus +} +#endif + + +#endif + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_fsmc.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_fsmc.h index e96e472..231c60e 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_fsmc.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_fsmc.h @@ -1,289 +1,276 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_fsmc.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the FSMC -* firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_FSMC_H -#define __CH32V30x_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - - -#include "ch32v30x.h" - - -/* FSMC Init structure definition */ -typedef struct -{ - uint32_t FSMC_AddressSetupTime; /* Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 0xF. - @note: It is not used with synchronous NOR Flash memories. */ - - uint32_t FSMC_AddressHoldTime; /* Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 0 and 0xF. - @note: It is not used with synchronous NOR Flash memories.*/ - - uint32_t FSMC_DataSetupTime; /* Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 0 and 0xFF. - @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FSMC_BusTurnAroundDuration; /* Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 0xF. - @note: It is only used for multiplexed NOR Flash memories. */ - - uint32_t FSMC_CLKDivision; /* Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 0xF. - @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FSMC_DataLatency; /* Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The value of this parameter depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 0xF in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FSMC_AccessMode; /* Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ -}FSMC_NORSRAMTimingInitTypeDef; - - -typedef struct -{ - uint32_t FSMC_Bank; /* Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t FSMC_DataAddressMux; /* Specifies whether the address and data values are - multiplexed on the databus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t FSMC_MemoryType; /* Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width. - This parameter can be a value of @ref FSMC_Data_Width */ - - uint32_t FSMC_BurstAccessMode; /* Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t FSMC_AsynchronousWait; /* Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ - - uint32_t FSMC_WaitSignalPolarity; /* Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t FSMC_WrapMode; /* Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ - - uint32_t FSMC_WaitSignalActive; /* Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t FSMC_WriteOperation; /* Enables or disables the write operation in the selected bank by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t FSMC_WaitSignal; /* Enables or disables the wait-state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t FSMC_ExtendedMode; /* Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t FSMC_WriteBurst; /* Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /* Timing Parameters for write and read access if the ExtendedMode is not used*/ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /* Timing Parameters for write access if the ExtendedMode is used*/ -}FSMC_NORSRAMInitTypeDef; - - -typedef struct -{ - uint32_t FSMC_SetupTime; /* Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 0xFF.*/ - - uint32_t FSMC_WaitSetupTime; /* Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HoldSetupTime; /* Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command deassertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HiZSetupTime; /* Defines the number of HCLK clock cycles during which the - databus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ -}FSMC_NAND_PCCARDTimingInitTypeDef; - - -typedef struct -{ - uint32_t FSMC_Bank; /* Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - - uint32_t FSMC_Waitfeature; /* Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width. - This parameter can be any value of @ref FSMC_Data_Width */ - - uint32_t FSMC_ECC; /* Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ - - uint32_t FSMC_ECCPageSize; /* Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ - - uint32_t FSMC_TCLRSetupTime; /* Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /* Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /* FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */ -}FSMC_NANDInitTypeDef; - - -/* FSMC_NORSRAM_Bank */ -#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) - -/* FSMC_NAND_Bank */ -#define FSMC_Bank2_NAND ((uint32_t)0x00000010) - -/* FSMC_Data_Address_Bus_Multiplexing */ -#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) - -/* FSMC_Memory_Type */ -#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) - -/* FSMC_Data_Width */ -#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) - -/* FSMC_Burst_Access_Mode */ -#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) - -/* FSMC_AsynchronousWait */ -#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) -#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) - -/* FSMC_Wait_Signal_Polarity */ -#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) - -/* FSMC_Wrap_Mode */ -#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) - -/* FSMC_Wait_Timing */ -#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) - -/* FSMC_Write_Operation */ -#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) - -/* FSMC_Wait_Signal */ -#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) - -/* FSMC_Extended_Mode */ -#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -/* FSMC_Write_Burst */ -#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) - -/* FSMC_Access_Mode */ -#define FSMC_AccessMode_A ((uint32_t)0x00000000) -#define FSMC_AccessMode_B ((uint32_t)0x10000000) -#define FSMC_AccessMode_C ((uint32_t)0x20000000) -#define FSMC_AccessMode_D ((uint32_t)0x30000000) - -/* FSMC_Wait_feature */ -#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) - -/* FSMC_ECC */ -#define FSMC_ECC_Disable ((uint32_t)0x00000000) -#define FSMC_ECC_Enable ((uint32_t)0x00000040) - -/* FSMC_ECC_Page_Size */ -#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) - -/* FSMC_Interrupt_sources */ -#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FSMC_IT_Level ((uint32_t)0x00000010) -#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) - -/* FSMC_Flags */ -#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FSMC_FLAG_Level ((uint32_t)0x00000002) -#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) - - -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); -void FSMC_NANDDeInit(uint32_t FSMC_Bank); -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); -uint32_t FSMC_GetECC(uint32_t FSMC_Bank); -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_fsmc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file contains all the functions prototypes for the FSMC +* firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_FSMC_H +#define __CH32V30x_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#include "ch32v30x.h" + + +/* FSMC Init structure definition */ +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /* Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /* Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /* Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /* Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note: It is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /* Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /* Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The value of this parameter depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /* Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + + +typedef struct +{ + uint32_t FSMC_Bank; /* Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /* Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /* Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /* Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_AsynchronousWait; /* Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FSMC_AsynchronousWait */ + + uint32_t FSMC_WaitSignalPolarity; /* Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WrapMode; /* Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t FSMC_WaitSignalActive; /* Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /* Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /* Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /* Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /* Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /* Timing Parameters for write and read access if the ExtendedMode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /* Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + + +typedef struct +{ + uint32_t FSMC_SetupTime; /* Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /* Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /* Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /* Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + + +typedef struct +{ + uint32_t FSMC_Bank; /* Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /* Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /* Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /* Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /* Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /* Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /* FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + + +/* FSMC_NORSRAM_Bank */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) + +/* FSMC_NAND_Bank */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) + +/* FSMC_Data_Address_Bus_Multiplexing */ +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) + +/* FSMC_Memory_Type */ +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) + +/* FSMC_Data_Width */ +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) + +/* FSMC_Burst_Access_Mode */ +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) + +/* FSMC_AsynchronousWait */ +#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) + +/* FSMC_Wait_Signal_Polarity */ +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) + +/* FSMC_Wrap_Mode */ +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) + +/* FSMC_Wait_Timing */ +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) + +/* FSMC_Write_Operation */ +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) + +/* FSMC_Wait_Signal */ +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) + +/* FSMC_Extended_Mode */ +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +/* FSMC_Write_Burst */ +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) + +/* FSMC_Access_Mode */ +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) + +/* FSMC_Wait_feature */ +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) + +/* FSMC_ECC */ +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) + +/* FSMC_ECC_Page_Size */ +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) + +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) + + +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_gpio.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_gpio.h index f5c21b0..1d9fb92 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_gpio.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_gpio.h @@ -1,197 +1,198 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_gpio.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* GPIO firmware library. -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_GPIO_H -#define __CH32V30x_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* Output Maximum frequency selection */ -typedef enum -{ - GPIO_Speed_10MHz = 1, - GPIO_Speed_2MHz, - GPIO_Speed_50MHz -}GPIOSpeed_TypeDef; - -/* Configuration Mode enumeration */ -typedef enum -{ GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 -}GPIOMode_TypeDef; - -/* GPIO Init structure definition */ -typedef struct -{ - uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -}GPIO_InitTypeDef; - -/* Bit_SET and Bit_RESET enumeration */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -}BitAction; - -/* GPIO_pins_define */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - -/* GPIO_Remap_define */ -/* PCFR1 */ -#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ -#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ -#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */ -#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ -#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ -#define GPIO_PartialRemap1_USART3 ((uint32_t)0x00140020) /* USART3 Partial1 Alternate Function mapping */ -#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ -#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ -#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ -#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ -#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ -#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ -#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */ -#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */ -#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */ -#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ -#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ -#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected - to TIM2 Internal Trigger 1 for calibration - (only for Connectivity line devices) */ -#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ - -/* PCFR2 */ -#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */ -#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */ -#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */ -#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */ -#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */ -#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */ -#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */ -#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */ -#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */ - - -/* GPIO_Port_Sources */ -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOB ((uint8_t)0x01) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) -#define GPIO_PortSourceGPIOD ((uint8_t)0x03) -#define GPIO_PortSourceGPIOE ((uint8_t)0x04) -#define GPIO_PortSourceGPIOF ((uint8_t)0x05) -#define GPIO_PortSourceGPIOG ((uint8_t)0x06) - -/* GPIO_Pin_sources */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -/* Ethernet_Media_Interface */ -#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) -#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) - - -void GPIO_DeInit(GPIO_TypeDef* GPIOx); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_EventOutputCmd(FunctionalState NewState); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_gpio.h +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file contains all the functions prototypes for the +* GPIO firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_GPIO_H +#define __CH32V30x_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; + +/* Configuration Mode enumeration */ +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +/* PCFR1 */ +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ +#define GPIO_PartialRemap1_USART3 ((uint32_t)0x00140020) /* USART3 Partial1 Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD0PD1 ((uint32_t)0x00008000) /* PD0 and PD1 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */ +#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */ +#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected + to TIM2 Internal Trigger 1 for calibration + (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ +#define GPIO_Remap_PD01 GPIO_Remap_PD0PD1 + +/* PCFR2 */ +#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */ +#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */ +#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */ +#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */ +#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */ + + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +/* Ethernet_Media_Interface */ +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) + + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_i2c.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_i2c.h index 7b4b1a2..8a9a97f 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_i2c.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_i2c.h @@ -1,439 +1,439 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_i2c.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* I2C firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_I2C_H -#define __CH32V30x_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* I2C Init structure definition */ -typedef struct -{ - uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /* Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /* Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /* Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/* I2C_mode */ -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) - -/* I2C_duty_cycle_in_fast_mode */ -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ - -/* I2C_acknowledgement */ -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) - -/* I2C_transfer_direction */ -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) - -/* I2C_acknowledged_address */ -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) - -/* I2C_registers */ -#define I2C_Register_CTLR1 ((uint8_t)0x00) -#define I2C_Register_CTLR2 ((uint8_t)0x04) -#define I2C_Register_OADDR1 ((uint8_t)0x08) -#define I2C_Register_OADDR2 ((uint8_t)0x0C) -#define I2C_Register_DATAR ((uint8_t)0x10) -#define I2C_Register_STAR1 ((uint8_t)0x14) -#define I2C_Register_STAR2 ((uint8_t)0x18) -#define I2C_Register_CKCFGR ((uint8_t)0x1C) -#define I2C_Register_RTR ((uint8_t)0x20) - -/* I2C_SMBus_alert_pin_level */ -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) - -/* I2C_PEC_position */ -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) - -/* I2C_NACK_position */ -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) - -/* I2C_interrupts_definition */ -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) - -/* I2C_interrupts_definition */ -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -/* SR2 register flags */ -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/* SR1 register flags */ -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - - -/****************I2C Master Events (Events grouped in order of communication)********************/ - -/******************************************************************************************************************** - * @brief Start communicate - * - * After master use I2C_GenerateSTART() function sending the START condition,the master - * has to wait for event 5(the Start condition has been correctly - * released on the I2C bus ). - * - */ -/* EVT5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/******************************************************************************************************************** - * @brief Address Acknowledge - * - * When start condition correctly released on the bus(check EVT5), the - * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate - * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will be set: - * - * - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (after generating the START - * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. - * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent - * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part - * of the 10-bit address (LSB) . Then master should wait for event 6. - * - * - */ - -/* EVT6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/*EVT9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/******************************************************************************************************************** - * @brief Communication events - * - * If START condition has generated and slave address - * been acknowledged. then the master has to check one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EVT7 then use - * I2C_ReceiveData() function to read the data received from the slave . - * - * 2) Master Transmitter mode: The master use I2C_SendData() function to send data - * then to wait on event EVT8 or EVT8_2. - * These two events are similar: - * - EVT8 means that the data has been written in the data register and is - * being shifted out. - * - EVT8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EVT8 is sufficient for the application. - * Using EVT8_2 will leads to a slower communication speed but will more reliable . - * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission - * - * - * Note: - * In case the user software does not guarantee that this event EVT7 is managed before - * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. - * - * - */ - -/* Master Receive mode */ -/* EVT7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master Transmitter mode*/ -/* EVT8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* EVT8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - - -/******************I2C Slave Events (Events grouped in order of communication)******************/ - -/******************************************************************************************************************** - * @brief Start Communicate events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a start condition of master device generate on the bus. - * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. - * - * - * - * a) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * b) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * c) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* EVT1 */ -/* a) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* b) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* c) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/******************************************************************************************************************** - * @brief Communication events - * - * Wait on one of these events when EVT1 has already been checked : - * - * - Slave Receiver mode: - * - EVT2--The device is expecting to receive a data byte . - * - EVT4--The device is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EVT3--When a byte has been transmitted by the slave and the Master is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee - * the EVT3 is managed before the current byte end of transfer The second one can optionally - * be used. - * - EVT3_2--When the master sends a NACK to tell slave device that data transmission - * shall end . The slave device has to stop sending - * data bytes and wait a Stop condition from bus. - * - * Note: - * If the user software does not guarantee that the event 2 is - * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time . - * In this case the communication will be slower. - * - */ - -/* Slave Receiver mode*/ -/* EVT2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* EVT4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave Transmitter mode*/ -/* EVT3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/*EVT3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - - -void I2C_DeInit(I2C_TypeDef* I2Cx); -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); - - -/***************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * profit the application requirements and constraints: - * - * - * a) First way: - * Using I2C_CheckEvent() function: - * It compares the status registers (STARR1 and STAR2) content to a given event - * (can be the combination of more flags). - * If the current status registers includes the given flags will return SUCCESS. - * and if the current status registers miss flags will returns ERROR. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (CH32FV2x-V3xRM). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs besides to the monitored error, - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * in corrupted state. it is suggeted to use error interrupts to monitor the error - * events and handle them in IRQ handler. - * - * - * Note: - * The following functions are recommended for error management: : - * - I2C_ITConfig() main function of configure and enable the error interrupts. - * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions - * to determine which error occurred. - * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() - * \ I2C_GenerateStop() will be use to clear the error flag and source, - * and return to correct communication status. - * - * - * b) Second way: - * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. - * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). - * - When to use: - * - * - This function is suitable for the same applications above but it - * don't have the limitations of I2C_GetFlagStatus() function . - * The returned value could be compared to events already defined in the - * library (CH32V30x_i2c.h) or to custom values defined by user. - * - This function can be used to monitor the status of multiple flags simultaneously. - * - Contrary to the I2C_CheckEvent () function, this function can choose the time to - * accept the event according to the user's needs (when all event flags are set and - * no other flags are set, or only when the required flags are set) - * - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * c) Third way: - * Using the function I2C_GetFlagStatus() get the status of - * one single flag . - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed . - * - * - Limitations: - * - Call this function to access the status register. Some flag bits may be cleared. - * - Function may need to be called twice or more in order to monitor one single event. - */ - - - -/********************************************************* - * - * a) Basic state monitoring(First way) - ******************************************************** - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/********************************************************* - * - * b) Advanced state monitoring(Second way:) - ******************************************************** - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/********************************************************* - * - * c) Flag-based state monitoring(Third way) - ********************************************************* - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_i2c.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* I2C firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_I2C_H +#define __CH32V30x_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); + + +/***************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * profit the application requirements and constraints: + * + * + * a) First way: + * Using I2C_CheckEvent() function: + * It compares the status registers (STARR1 and STAR2) content to a given event + * (can be the combination of more flags). + * If the current status registers includes the given flags will return SUCCESS. + * and if the current status registers miss flags will returns ERROR. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (CH32FV2x-V3xRM). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs besides to the monitored error, + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * in corrupted state. it is suggeted to use error interrupts to monitor the error + * events and handle them in IRQ handler. + * + * + * Note: + * The following functions are recommended for error management: : + * - I2C_ITConfig() main function of configure and enable the error interrupts. + * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions + * to determine which error occurred. + * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() + * \ I2C_GenerateStop() will be use to clear the error flag and source, + * and return to correct communication status. + * + * + * b) Second way: + * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. + * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). + * - When to use: + * + * - This function is suitable for the same applications above but it + * don't have the limitations of I2C_GetFlagStatus() function . + * The returned value could be compared to events already defined in the + * library (CH32V30x_i2c.h) or to custom values defined by user. + * - This function can be used to monitor the status of multiple flags simultaneously. + * - Contrary to the I2C_CheckEvent () function, this function can choose the time to + * accept the event according to the user's needs (when all event flags are set and + * no other flags are set, or only when the required flags are set) + * + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * c) Third way: + * Using the function I2C_GetFlagStatus() get the status of + * one single flag . + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed . + * + * - Limitations: + * - Call this function to access the status register. Some flag bits may be cleared. + * - Function may need to be called twice or more in order to monitor one single event. + */ + + + +/********************************************************* + * + * a) Basic state monitoring(First way) + ******************************************************** + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/********************************************************* + * + * b) Advanced state monitoring(Second way:) + ******************************************************** + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/********************************************************* + * + * c) Flag-based state monitoring(Third way) + ********************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_iwdg.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_iwdg.h index e506d75..3a52e33 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_iwdg.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_iwdg.h @@ -1,58 +1,58 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_iwdg.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* IWDG firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_IWDG_H -#define __CH32V30x_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* IWDG_WriteAccess */ -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) - -/* IWDG_prescaler */ -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) - -/* IWDG_Flag */ -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) - - -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_Enable(void); -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_iwdg.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* IWDG firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_IWDG_H +#define __CH32V30x_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_misc.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_misc.h index 2c7e59f..11fdd98 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_misc.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_misc.h @@ -1,48 +1,93 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_misc.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* miscellaneous firmware library functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30X_MISC_H -#define __CH32V30X_MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* NVIC Init Structure definition */ -typedef struct -{ - uint8_t NVIC_IRQChannel; - uint8_t NVIC_IRQChannelPreemptionPriority; - uint8_t NVIC_IRQChannelSubPriority; - FunctionalState NVIC_IRQChannelCmd; -} NVIC_InitTypeDef; - - -/* Preemption_Priority_Group */ -#define NVIC_PriorityGroup_0 ((uint32_t)0x00) -#define NVIC_PriorityGroup_1 ((uint32_t)0x01) -#define NVIC_PriorityGroup_2 ((uint32_t)0x02) -#define NVIC_PriorityGroup_3 ((uint32_t)0x03) -#define NVIC_PriorityGroup_4 ((uint32_t)0x04) - - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); - -#ifdef __cplusplus -} -#endif - -#endif - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_misc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file contains all the functions prototypes for the +* miscellaneous firmware library functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30X_MISC_H +#define __CH32V30X_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* CSR_INTSYSCR_INEST_definition */ +#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#define INTSYSCR_INEST_EN_2Level 0x01 /* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) */ +#define INTSYSCR_INEST_EN_4Level 0x02 /* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) */ +#define INTSYSCR_INEST_EN_8Level 0x03 /* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) */ + +/* Check the configuration of CSR(0x804) in the startup file(.S) + * interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) + * priority - bit[7:5] - Preemption Priority + * bit[4:0] - Reserve + * interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) + * priority - bit[7:6] - Preemption Priority + * bit[5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + */ + +#ifndef INTSYSCR_INEST +#define INTSYSCR_INEST INTSYSCR_INEST_EN_4Level +#endif + +/* NVIC Init Structure definition + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + * interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 3. + * NVIC_IRQChannelSubPriority - range from 0 to 1. + * + * interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 7. + * NVIC_IRQChannelSubPriority - range range is 0. + */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Preemption_Priority_Group */ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_2Level) +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) */ +#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_8Level) +#define NVIC_PriorityGroup_3 ((uint32_t)0x03) /* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) */ +#else +#define NVIC_PriorityGroup_2 ((uint32_t)0x02) /* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) */ +#endif + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_opa.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_opa.h index 40e71b8..2be4b28 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_opa.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_opa.h @@ -1,77 +1,77 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_opa.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* OPA firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_OPA_H -#define __CH32V30x_OPA_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -#define OPA_PSEL_OFFSET 3 -#define OPA_NSEL_OFFSET 2 -#define OPA_MODE_OFFSET 1 - - -/* OPA member enumeration */ -typedef enum -{ - OPA1=0, - OPA2, - OPA3, - OPA4 -}OPA_Num_TypeDef; - -/* OPA PSEL enumeration */ -typedef enum -{ - CHP0=0, - CHP1 -}OPA_PSEL_TypeDef; - -/* OPA NSEL enumeration */ -typedef enum -{ - CHN0=0, - CHN1 -}OPA_NSEL_TypeDef; - -/* OPA out channel enumeration */ -typedef enum -{ - OUT_IO_OUT0=0, - OUT_IO_OUT1 -}OPA_Mode_TypeDef; - -/* OPA Init Structure definition */ -typedef struct -{ - OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ - OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ - OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ - OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ -}OPA_InitTypeDef; - - -void OPA_DeInit(void); -void OPA_Init(OPA_InitTypeDef* OPA_InitStruct); -void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct); -void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_opa.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* OPA firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_OPA_H +#define __CH32V30x_OPA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +#define OPA_PSEL_OFFSET 3 +#define OPA_NSEL_OFFSET 2 +#define OPA_MODE_OFFSET 1 + + +/* OPA member enumeration */ +typedef enum +{ + OPA1=0, + OPA2, + OPA3, + OPA4 +}OPA_Num_TypeDef; + +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0=0, + CHP1 +}OPA_PSEL_TypeDef; + +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0=0, + CHN1 +}OPA_NSEL_TypeDef; + +/* OPA out channel enumeration */ +typedef enum +{ + OUT_IO_OUT0=0, + OUT_IO_OUT1 +}OPA_Mode_TypeDef; + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ +}OPA_InitTypeDef; + + +void OPA_DeInit(void); +void OPA_Init(OPA_InitTypeDef* OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct); +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_pwr.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_pwr.h index 49e65ee..64f20e7 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_pwr.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_pwr.h @@ -1,66 +1,77 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_pwr.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the PWR -* firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_PWR_H -#define __CH32V30x_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* PVD_detection_level */ -#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) -#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) -#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) -#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) -#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) -#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) -#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) -#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) - -/* Regulator_state_is_STOP_mode */ -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower ((uint32_t)0x00000001) - -/* STOP_mode_entry */ -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) - -/* PWR_Flag */ -#define PWR_FLAG_WU ((uint32_t)0x00000001) -#define PWR_FLAG_SB ((uint32_t)0x00000002) -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) - - -void PWR_DeInit(void); -void PWR_BackupAccessCmd(FunctionalState NewState); -void PWR_PVDCmd(FunctionalState NewState); -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_WakeUpPinCmd(FunctionalState NewState); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); -void PWR_EnterSTANDBYMode_RAM(void); -void PWR_EnterSTANDBYMode_RAM_LV(void); -void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); -void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); -void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); - -#ifdef __cplusplus -} -#endif - -#endif - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_pwr.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the PWR +* firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_PWR_H +#define __CH32V30x_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* PVD_detection_level */ +#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080) +#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0) + + + +#define PWR_PVDLevel_2V2 PWR_PVDLevel_MODE0 +#define PWR_PVDLevel_2V3 PWR_PVDLevel_MODE1 +#define PWR_PVDLevel_2V4 PWR_PVDLevel_MODE2 +#define PWR_PVDLevel_2V5 PWR_PVDLevel_MODE3 +#define PWR_PVDLevel_2V6 PWR_PVDLevel_MODE4 +#define PWR_PVDLevel_2V7 PWR_PVDLevel_MODE5 +#define PWR_PVDLevel_2V8 PWR_PVDLevel_MODE6 +#define PWR_PVDLevel_2V9 PWR_PVDLevel_MODE7 + +/* Regulator_state_is_STOP_mode */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); +void PWR_EnterSTANDBYMode_RAM(void); +void PWR_EnterSTANDBYMode_RAM_LV(void); +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); +void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_rcc.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_rcc.h index 7729e7d..24f22e7 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_rcc.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_rcc.h @@ -1,458 +1,464 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_rcc.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the RCC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_RCC_H -#define __CH32V30x_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* RCC_Exported_Types */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ - uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/* HSE_configuration */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00010000) -#define RCC_HSE_Bypass ((uint32_t)0x00040000) - -/* PLL_entry_clock_source */ -#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) - -#ifdef CH32V30x_D8 -#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) -#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) - -#else -#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) - -#endif - -/* PLL_multiplication_factor */ -#ifdef CH32V30x_D8 -#define RCC_PLLMul_2 ((uint32_t)0x00000000) -#define RCC_PLLMul_3 ((uint32_t)0x00040000) -#define RCC_PLLMul_4 ((uint32_t)0x00080000) -#define RCC_PLLMul_5 ((uint32_t)0x000C0000) -#define RCC_PLLMul_6 ((uint32_t)0x00100000) -#define RCC_PLLMul_7 ((uint32_t)0x00140000) -#define RCC_PLLMul_8 ((uint32_t)0x00180000) -#define RCC_PLLMul_9 ((uint32_t)0x001C0000) -#define RCC_PLLMul_10 ((uint32_t)0x00200000) -#define RCC_PLLMul_11 ((uint32_t)0x00240000) -#define RCC_PLLMul_12 ((uint32_t)0x00280000) -#define RCC_PLLMul_13 ((uint32_t)0x002C0000) -#define RCC_PLLMul_14 ((uint32_t)0x00300000) -#define RCC_PLLMul_15 ((uint32_t)0x00340000) -#define RCC_PLLMul_16 ((uint32_t)0x00380000) -#define RCC_PLLMul_18 ((uint32_t)0x003C0000) - -#else -#define RCC_PLLMul_18_EXTEN ((uint32_t)0x00000000) -#define RCC_PLLMul_3_EXTEN ((uint32_t)0x00040000) -#define RCC_PLLMul_4_EXTEN ((uint32_t)0x00080000) -#define RCC_PLLMul_5_EXTEN ((uint32_t)0x000C0000) -#define RCC_PLLMul_6_EXTEN ((uint32_t)0x00100000) -#define RCC_PLLMul_7_EXTEN ((uint32_t)0x00140000) -#define RCC_PLLMul_8_EXTEN ((uint32_t)0x00180000) -#define RCC_PLLMul_9_EXTEN ((uint32_t)0x001C0000) -#define RCC_PLLMul_10_EXTEN ((uint32_t)0x00200000) -#define RCC_PLLMul_11_EXTEN ((uint32_t)0x00240000) -#define RCC_PLLMul_12_EXTEN ((uint32_t)0x00280000) -#define RCC_PLLMul_13_EXTEN ((uint32_t)0x002C0000) -#define RCC_PLLMul_14_EXTEN ((uint32_t)0x00300000) -#define RCC_PLLMul_6_5_EXTEN ((uint32_t)0x00340000) -#define RCC_PLLMul_15_EXTEN ((uint32_t)0x00380000) -#define RCC_PLLMul_16_EXTEN ((uint32_t)0x003C0000) - -#endif - -/* PREDIV1_division_factor */ -#ifdef CH32V30x_D8C -#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) -#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) -#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) -#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) -#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) -#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) -#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) -#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) -#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) -#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) -#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) -#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) -#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) -#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) -#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) -#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) - -#endif - -/* PREDIV1_clock_source */ -#ifdef CH32V30x_D8C -#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) -#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) - -#endif - -/* PREDIV2_division_factor */ -#ifdef CH32V30x_D8C -#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) -#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) -#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) -#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) -#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) -#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) -#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) -#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) -#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) -#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) -#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) -#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) -#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) -#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) -#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) -#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) - -#endif - -/* PLL2_multiplication_factor */ -#ifdef CH32V30x_D8C -#define RCC_PLL2Mul_2_5 ((uint32_t)0x00000000) -#define RCC_PLL2Mul_12_5 ((uint32_t)0x00000100) -#define RCC_PLL2Mul_4 ((uint32_t)0x00000200) -#define RCC_PLL2Mul_5 ((uint32_t)0x00000300) -#define RCC_PLL2Mul_6 ((uint32_t)0x00000400) -#define RCC_PLL2Mul_7 ((uint32_t)0x00000500) -#define RCC_PLL2Mul_8 ((uint32_t)0x00000600) -#define RCC_PLL2Mul_9 ((uint32_t)0x00000700) -#define RCC_PLL2Mul_10 ((uint32_t)0x00000800) -#define RCC_PLL2Mul_11 ((uint32_t)0x00000900) -#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) -#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) -#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) -#define RCC_PLL2Mul_15 ((uint32_t)0x00000D00) -#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) -#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) - -#endif - -/* PLL3_multiplication_factor */ -#ifdef CH32V30x_D8C -#define RCC_PLL3Mul_2_5 ((uint32_t)0x00000000) -#define RCC_PLL3Mul_12_5 ((uint32_t)0x00001000) -#define RCC_PLL3Mul_4 ((uint32_t)0x00002000) -#define RCC_PLL3Mul_5 ((uint32_t)0x00003000) -#define RCC_PLL3Mul_6 ((uint32_t)0x00004000) -#define RCC_PLL3Mul_7 ((uint32_t)0x00005000) -#define RCC_PLL3Mul_8 ((uint32_t)0x00006000) -#define RCC_PLL3Mul_9 ((uint32_t)0x00007000) -#define RCC_PLL3Mul_10 ((uint32_t)0x00008000) -#define RCC_PLL3Mul_11 ((uint32_t)0x00009000) -#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) -#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) -#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) -#define RCC_PLL3Mul_15 ((uint32_t)0x0000D000) -#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) -#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) - -#endif - -/* System_clock_source */ -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) - -/* AHB_clock_source */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) - -/* APB1_APB2_clock_source */ -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00000400) -#define RCC_HCLK_Div4 ((uint32_t)0x00000500) -#define RCC_HCLK_Div8 ((uint32_t)0x00000600) -#define RCC_HCLK_Div16 ((uint32_t)0x00000700) - -/* RCC_Interrupt_source */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) - -#ifdef CH32V30x_D8C -#define RCC_IT_PLL2RDY ((uint8_t)0x20) -#define RCC_IT_PLL3RDY ((uint8_t)0x40) - -#endif - -/* USB_OTG_FS_clock_source */ -#define RCC_OTGFSCLKSource_PLLCLK_Div1 ((uint8_t)0x00) -#define RCC_OTGFSCLKSource_PLLCLK_Div2 ((uint8_t)0x01) -#define RCC_OTGFSCLKSource_PLLCLK_Div3 ((uint8_t)0x02) - -/* I2S2_clock_source */ -#ifdef CH32V30x_D8C -#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) -#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) - -#endif - -/* I2S3_clock_source */ -#ifdef CH32V30x_D8C -#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) -#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) - -#endif - -/* ADC_clock_source */ -#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) -#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) -#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) -#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) - -/* LSE_configuration */ -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) - -/* RTC_clock_source */ -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) - -/* AHB_peripheral */ -#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) -#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) -#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) -#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) -#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200) -#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) -#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800) -#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) -#define RCC_AHBPeriph_DVP ((uint32_t)0x00002000) -#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) -#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) -#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) - -/* APB2_peripheral */ -#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) -#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) -#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) - -/* APB1_peripheral */ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040) -#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080) -#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_USB ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) - -/* Clock_source_to_output_on_MCO_pin */ -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) -#define RCC_MCO_HSE ((uint8_t)0x06) -#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) - -#ifdef CH32V30x_D8C -#define RCC_MCO_PLL2CLK ((uint8_t)0x08) -#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) -#define RCC_MCO_XT1 ((uint8_t)0x0A) -#define RCC_MCO_PLL3CLK ((uint8_t)0x0B) - -#endif - -/* RCC_Flag */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -#ifdef CH32V30x_D8C -#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) -#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) - -#endif - -/* SysTick_clock_source */ -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) - -/* RNG_clock_source */ -#ifdef CH32V30x_D8C -#define RCC_RNGCLKSource_SYSCLK ((uint32_t)0x00) -#define RCC_RNGCLKSource_PLL3_VCO ((uint32_t)0x01) - -#endif - -/* ETH1G_clock_source */ -#ifdef CH32V30x_D8C -#define RCC_ETH1GCLKSource_PLL2_VCO ((uint32_t)0x00) -#define RCC_ETH1GCLKSource_PLL3_VCO ((uint32_t)0x01) -#define RCC_ETH1GCLKSource_PB1_IN ((uint32_t)0x02) - -#endif - -/* USBFS_clock_source */ -#ifdef CH32V30x_D8C -#define RCC_USBPLL_Div1 ((uint32_t)0x00) -#define RCC_USBPLL_Div2 ((uint32_t)0x01) -#define RCC_USBPLL_Div3 ((uint32_t)0x02) -#define RCC_USBPLL_Div4 ((uint32_t)0x03) -#define RCC_USBPLL_Div5 ((uint32_t)0x04) -#define RCC_USBPLL_Div6 ((uint32_t)0x05) -#define RCC_USBPLL_Div7 ((uint32_t)0x06) -#define RCC_USBPLL_Div8 ((uint32_t)0x07) - -#endif - -/* USBHSPLL_clock_source */ -#ifdef CH32V30x_D8C -#define RCC_HSBHSPLLCLKSource_HSE ((uint32_t)0x00) -#define RCC_HSBHSPLLCLKSource_HSI ((uint32_t)0x01) - -#endif - -/* USBHSPLLCKREF_clock_select */ -#ifdef CH32V30x_D8C -#define RCC_USBHSPLLCKREFCLK_3M ((uint32_t)0x00) -#define RCC_USBHSPLLCKREFCLK_4M ((uint32_t)0x01) -#define RCC_USBHSPLLCKREFCLK_8M ((uint32_t)0x02) -#define RCC_USBHSPLLCKREFCLK_5M ((uint32_t)0x03) - -#endif - -/* OTGUSBCLK48M_clock_source */ -#define RCC_USBCLK48MCLKSource_PLLCLK ((uint32_t)0x00) -#define RCC_USBCLK48MCLKSource_USBPHY ((uint32_t)0x01) - - -void RCC_DeInit(void); -void RCC_HSEConfig(uint32_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCO); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); -void RCC_ADCCLKADJcmd(FunctionalState NewState); -void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); -void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource); - -#ifdef CH32V30x_D8C -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); -void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); -void RCC_PLL2Config(uint32_t RCC_PLL2Mul); -void RCC_PLL2Cmd(FunctionalState NewState); -void RCC_PLL3Config(uint32_t RCC_PLL3Mul); -void RCC_PLL3Cmd(FunctionalState NewState); -void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); -void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource); -void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource); -void RCC_ETH1G_125Mcmd(FunctionalState NewState); -void RCC_USBHSConfig(uint32_t RCC_USBHS); -void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource); -void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource); -void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState); - -#endif - -#ifdef __cplusplus -} -#endif - -#endif - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rcc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_RCC_H +#define __CH32V30x_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) + +#ifdef CH32V30x_D8 +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + +#else +#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) + +#endif + +/* PLL_multiplication_factor */ +#ifdef CH32V30x_D8 +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) +#define RCC_PLLMul_18 ((uint32_t)0x003C0000) + +#else +#define RCC_PLLMul_18_EXTEN ((uint32_t)0x00000000) +#define RCC_PLLMul_3_EXTEN ((uint32_t)0x00040000) +#define RCC_PLLMul_4_EXTEN ((uint32_t)0x00080000) +#define RCC_PLLMul_5_EXTEN ((uint32_t)0x000C0000) +#define RCC_PLLMul_6_EXTEN ((uint32_t)0x00100000) +#define RCC_PLLMul_7_EXTEN ((uint32_t)0x00140000) +#define RCC_PLLMul_8_EXTEN ((uint32_t)0x00180000) +#define RCC_PLLMul_9_EXTEN ((uint32_t)0x001C0000) +#define RCC_PLLMul_10_EXTEN ((uint32_t)0x00200000) +#define RCC_PLLMul_11_EXTEN ((uint32_t)0x00240000) +#define RCC_PLLMul_12_EXTEN ((uint32_t)0x00280000) +#define RCC_PLLMul_13_EXTEN ((uint32_t)0x002C0000) +#define RCC_PLLMul_14_EXTEN ((uint32_t)0x00300000) +#define RCC_PLLMul_6_5_EXTEN ((uint32_t)0x00340000) +#define RCC_PLLMul_15_EXTEN ((uint32_t)0x00380000) +#define RCC_PLLMul_16_EXTEN ((uint32_t)0x003C0000) + +#endif + +/* PREDIV1_division_factor */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) +#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) +#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) +#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) +#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) +#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) +#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) +#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) +#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) +#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) +#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) +#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) +#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) +#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) +#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) +#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) + +#endif + +/* PREDIV1_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) +#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) + +#endif + +/* PREDIV2_division_factor */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) +#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) +#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) +#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) +#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) +#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) +#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) +#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) +#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) +#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) +#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) +#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) +#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) +#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) +#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) +#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) + +#endif + +/* PLL2_multiplication_factor */ +#ifdef CH32V30x_D8C +#define RCC_PLL2Mul_2_5 ((uint32_t)0x00000000) +#define RCC_PLL2Mul_12_5 ((uint32_t)0x00000100) +#define RCC_PLL2Mul_4 ((uint32_t)0x00000200) +#define RCC_PLL2Mul_5 ((uint32_t)0x00000300) +#define RCC_PLL2Mul_6 ((uint32_t)0x00000400) +#define RCC_PLL2Mul_7 ((uint32_t)0x00000500) +#define RCC_PLL2Mul_8 ((uint32_t)0x00000600) +#define RCC_PLL2Mul_9 ((uint32_t)0x00000700) +#define RCC_PLL2Mul_10 ((uint32_t)0x00000800) +#define RCC_PLL2Mul_11 ((uint32_t)0x00000900) +#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) +#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) +#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) +#define RCC_PLL2Mul_15 ((uint32_t)0x00000D00) +#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) +#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) + +#endif + +/* PLL3_multiplication_factor */ +#ifdef CH32V30x_D8C +#define RCC_PLL3Mul_2_5 ((uint32_t)0x00000000) +#define RCC_PLL3Mul_12_5 ((uint32_t)0x00001000) +#define RCC_PLL3Mul_4 ((uint32_t)0x00002000) +#define RCC_PLL3Mul_5 ((uint32_t)0x00003000) +#define RCC_PLL3Mul_6 ((uint32_t)0x00004000) +#define RCC_PLL3Mul_7 ((uint32_t)0x00005000) +#define RCC_PLL3Mul_8 ((uint32_t)0x00006000) +#define RCC_PLL3Mul_9 ((uint32_t)0x00007000) +#define RCC_PLL3Mul_10 ((uint32_t)0x00008000) +#define RCC_PLL3Mul_11 ((uint32_t)0x00009000) +#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) +#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) +#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) +#define RCC_PLL3Mul_15 ((uint32_t)0x0000D000) +#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) +#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) + +#endif + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) + +/* APB1_APB2_clock_source */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +#ifdef CH32V30x_D8C +#define RCC_IT_PLL2RDY ((uint8_t)0x20) +#define RCC_IT_PLL3RDY ((uint8_t)0x40) + +#endif + +/* USBFS_clock_source */ +#define RCC_USBFSCLKSource_PLLCLK_Div1 ((uint8_t)0x00) +#define RCC_USBFSCLKSource_PLLCLK_Div2 ((uint8_t)0x01) +#define RCC_USBFSCLKSource_PLLCLK_Div3 ((uint8_t)0x02) + +#define RCC_OTGFSCLKSource_PLLCLK_Div1 RCC_USBFSCLKSource_PLLCLK_Div1 +#define RCC_OTGFSCLKSource_PLLCLK_Div2 RCC_USBFSCLKSource_PLLCLK_Div2 +#define RCC_OTGFSCLKSource_PLLCLK_Div3 RCC_USBFSCLKSource_PLLCLK_Div3 + +/* I2S2_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) +#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) + +#endif + +/* I2S3_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) +#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) + +#endif + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) +#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200) +#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) +#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800) +#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000) +#define RCC_AHBPeriph_DVP ((uint32_t)0x00002000) +#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) +#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) +#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) +#define RCC_AHBPeriph_OTG_FS RCC_AHBPeriph_USBFS + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040) +#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080) +#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +#ifdef CH32V30x_D8C +#define RCC_MCO_PLL2CLK ((uint8_t)0x08) +#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) +#define RCC_MCO_XT1 ((uint8_t)0x0A) +#define RCC_MCO_PLL3CLK ((uint8_t)0x0B) + +#endif + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#ifdef CH32V30x_D8C +#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) +#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) + +#endif + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +/* RNG_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_RNGCLKSource_SYSCLK ((uint32_t)0x00) +#define RCC_RNGCLKSource_PLL3_VCO ((uint32_t)0x01) + +#endif + +/* ETH1G_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_ETH1GCLKSource_PLL2_VCO ((uint32_t)0x00) +#define RCC_ETH1GCLKSource_PLL3_VCO ((uint32_t)0x01) +#define RCC_ETH1GCLKSource_PB1_IN ((uint32_t)0x02) + +#endif + +/* USBFS_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_USBPLL_Div1 ((uint32_t)0x00) +#define RCC_USBPLL_Div2 ((uint32_t)0x01) +#define RCC_USBPLL_Div3 ((uint32_t)0x02) +#define RCC_USBPLL_Div4 ((uint32_t)0x03) +#define RCC_USBPLL_Div5 ((uint32_t)0x04) +#define RCC_USBPLL_Div6 ((uint32_t)0x05) +#define RCC_USBPLL_Div7 ((uint32_t)0x06) +#define RCC_USBPLL_Div8 ((uint32_t)0x07) + +#endif + +/* USBHSPLL_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_HSBHSPLLCLKSource_HSE ((uint32_t)0x00) +#define RCC_HSBHSPLLCLKSource_HSI ((uint32_t)0x01) + +#endif + +/* USBHSPLLCKREF_clock_select */ +#ifdef CH32V30x_D8C +#define RCC_USBHSPLLCKREFCLK_3M ((uint32_t)0x00) +#define RCC_USBHSPLLCKREFCLK_4M ((uint32_t)0x01) +#define RCC_USBHSPLLCKREFCLK_8M ((uint32_t)0x02) +#define RCC_USBHSPLLCKREFCLK_5M ((uint32_t)0x03) + +#endif + +/* OTGUSBCLK48M_clock_source */ +#define RCC_USBCLK48MCLKSource_PLLCLK ((uint32_t)0x00) +#define RCC_USBCLK48MCLKSource_USBPHY ((uint32_t)0x01) + + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); +void RCC_ADCCLKADJcmd(FunctionalState NewState); +void RCC_USBFSCLKConfig(uint32_t RCC_USBFSCLKSource); +void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource); +#define RCC_OTGFSCLKConfig RCC_USBFSCLKConfig + +#ifdef CH32V30x_D8C +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); +void RCC_PLL2Config(uint32_t RCC_PLL2Mul); +void RCC_PLL2Cmd(FunctionalState NewState); +void RCC_PLL3Config(uint32_t RCC_PLL3Mul); +void RCC_PLL3Cmd(FunctionalState NewState); +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource); +void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource); +void RCC_ETH1G_125Mcmd(FunctionalState NewState); +void RCC_USBHSConfig(uint32_t RCC_USBHS); +void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource); +void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource); +void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_rng.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_rng.h index 3163c89..51a6455 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_rng.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_rng.h @@ -1,43 +1,43 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_rng.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* RNG firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_RNG_H -#define __CH32V30x_RNG_H - -#ifdef __cplusplus - extern "C" { -#endif -#include "ch32v30x.h" - - /* RNG_flags_definition*/ -#define RNG_FLAG_DRDY ((uint8_t)0x0001) /* Data ready */ -#define RNG_FLAG_CECS ((uint8_t)0x0002) /* Clock error current status */ -#define RNG_FLAG_SECS ((uint8_t)0x0004) /* Seed error current status */ - -/* RNG_interrupts_definition */ -#define RNG_IT_CEI ((uint8_t)0x20) /* Clock error interrupt */ -#define RNG_IT_SEI ((uint8_t)0x40) /* Seed error interrupt */ - - -void RNG_Cmd(FunctionalState NewState); -uint32_t RNG_GetRandomNumber(void); -void RNG_ITConfig(FunctionalState NewState); -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); -void RNG_ClearFlag(uint8_t RNG_FLAG); -ITStatus RNG_GetITStatus(uint8_t RNG_IT); -void RNG_ClearITPendingBit(uint8_t RNG_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rng.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* RNG firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_RNG_H +#define __CH32V30x_RNG_H + +#ifdef __cplusplus + extern "C" { +#endif +#include "ch32v30x.h" + + /* RNG_flags_definition*/ +#define RNG_FLAG_DRDY ((uint8_t)0x0001) /* Data ready */ +#define RNG_FLAG_CECS ((uint8_t)0x0002) /* Clock error current status */ +#define RNG_FLAG_SECS ((uint8_t)0x0004) /* Seed error current status */ + +/* RNG_interrupts_definition */ +#define RNG_IT_CEI ((uint8_t)0x20) /* Clock error interrupt */ +#define RNG_IT_SEI ((uint8_t)0x40) /* Seed error interrupt */ + + +void RNG_Cmd(FunctionalState NewState); +uint32_t RNG_GetRandomNumber(void); +void RNG_ITConfig(FunctionalState NewState); +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); +void RNG_ClearFlag(uint8_t RNG_FLAG); +ITStatus RNG_GetITStatus(uint8_t RNG_IT); +void RNG_ClearITPendingBit(uint8_t RNG_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_rtc.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_rtc.h index 3e17385..79d3090 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_rtc.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_rtc.h @@ -1,56 +1,56 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_rtc.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the RTC -* firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_RTC_H -#define __CH32V30x_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - - -/* RTC_interrupts_define */ -#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ -#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ -#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ - -/* RTC_interrupts_flags */ -#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ -#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ -#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ -#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ -#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ - - -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); -void RTC_EnterConfigMode(void); -void RTC_ExitConfigMode(void); -uint32_t RTC_GetCounter(void); -void RTC_SetCounter(uint32_t CounterValue); -void RTC_SetPrescaler(uint32_t PrescalerValue); -void RTC_SetAlarm(uint32_t AlarmValue); -uint32_t RTC_GetDivider(void); -void RTC_WaitForLastTask(void); -void RTC_WaitForSynchro(void); -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); -void RTC_ClearFlag(uint16_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint16_t RTC_IT); -void RTC_ClearITPendingBit(uint16_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rtc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the RTC +* firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_RTC_H +#define __CH32V30x_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* RTC_interrupts_define */ +#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ + +/* RTC_interrupts_flags */ +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ + + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_sdio.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_sdio.h index 1494962..2d331e0 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_sdio.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_sdio.h @@ -1,256 +1,266 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_sdio.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the SDIO -* firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_SDIO_H -#define __CH32V30x_SDIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* SDIO Init structure definition */ -typedef struct -{ - uint32_t SDIO_ClockEdge; /* Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDIO_Clock_Edge */ - - uint32_t SDIO_ClockBypass; /* Specifies whether the SDIO Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDIO_Clock_Bypass */ - - uint32_t SDIO_ClockPowerSave; /* Specifies whether SDIO Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDIO_Clock_Power_Save */ - - uint32_t SDIO_BusWide; /* Specifies the SDIO bus width. - This parameter can be a value of @ref SDIO_Bus_Wide */ - - uint32_t SDIO_HardwareFlowControl; /* Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ - - uint8_t SDIO_ClockDiv; /* Specifies the clock frequency of the SDIO controller. - This parameter can be a value between 0x00 and 0xFF. */ - -} SDIO_InitTypeDef; - - -typedef struct -{ - uint32_t SDIO_Argument; /* Specifies the SDIO command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register */ - - uint32_t SDIO_CmdIndex; /* Specifies the SDIO command index. It must be lower than 0x40. */ - - uint32_t SDIO_Response; /* Specifies the SDIO response type. - This parameter can be a value of @ref SDIO_Response_Type */ - - uint32_t SDIO_Wait; /* Specifies whether SDIO wait-for-interrupt request is enabled or disabled. - This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ - - uint32_t SDIO_CPSM; /* Specifies whether SDIO Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_CPSM_State */ -} SDIO_CmdInitTypeDef; - -typedef struct -{ - uint32_t SDIO_DataTimeOut; /* Specifies the data timeout period in card bus clock periods. */ - - uint32_t SDIO_DataLength; /* Specifies the number of data bytes to be transferred. */ - - uint32_t SDIO_DataBlockSize; /* Specifies the data block size for block transfer. - This parameter can be a value of @ref SDIO_Data_Block_Size */ - - uint32_t SDIO_TransferDir; /* Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDIO_Transfer_Direction */ - - uint32_t SDIO_TransferMode; /* Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDIO_Transfer_Type */ - - uint32_t SDIO_DPSM; /* Specifies whether SDIO Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_DPSM_State */ -} SDIO_DataInitTypeDef; - - -/* SDIO_Clock_Edge */ -#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) -#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) - -/* SDIO_Clock_Bypass */ -#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) -#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) - -/* SDIO_Clock_Power_Save */ -#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) -#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) - -/* SDIO_Bus_Wide */ -#define SDIO_BusWide_1b ((uint32_t)0x00000000) -#define SDIO_BusWide_4b ((uint32_t)0x00000800) -#define SDIO_BusWide_8b ((uint32_t)0x00001000) - -/* SDIO_Hardware_Flow_Control */ -#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) -#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) - -/* SDIO_Power_State */ -#define SDIO_PowerState_OFF ((uint32_t)0x00000000) -#define SDIO_PowerState_ON ((uint32_t)0x00000003) - -/* SDIO_Interrupt_sources */ -#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) -#define SDIO_IT_CMDREND ((uint32_t)0x00000040) -#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_IT_DATAEND ((uint32_t)0x00000100) -#define SDIO_IT_STBITERR ((uint32_t)0x00000200) -#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) -#define SDIO_IT_CMDACT ((uint32_t)0x00000800) -#define SDIO_IT_TXACT ((uint32_t)0x00001000) -#define SDIO_IT_RXACT ((uint32_t)0x00002000) -#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) -#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) -#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) -#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) - -/* SDIO_Response_Type */ -#define SDIO_Response_No ((uint32_t)0x00000000) -#define SDIO_Response_Short ((uint32_t)0x00000040) -#define SDIO_Response_Long ((uint32_t)0x000000C0) - -/* SDIO_Wait_Interrupt_State */ -#define SDIO_Wait_No ((uint32_t)0x00000000) -#define SDIO_Wait_IT ((uint32_t)0x00000100) -#define SDIO_Wait_Pend ((uint32_t)0x00000200) - -/* SDIO_CPSM_State */ -#define SDIO_CPSM_Disable ((uint32_t)0x00000000) -#define SDIO_CPSM_Enable ((uint32_t)0x00000400) - -/* SDIO_Response_Registers */ -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) - -/* SDIO_Data_Block_Size */ -#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) -#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) -#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) -#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) -#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) -#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) -#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) -#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) -#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) -#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) -#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) -#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) -#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) -#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) -#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) - -/* SDIO_Transfer_Direction */ -#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) -#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) - -/* SDIO_Transfer_Type */ -#define SDIO_TransferMode_Block ((uint32_t)0x00000000) -#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) - -/* SDIO_DPSM_State */ -#define SDIO_DPSM_Disable ((uint32_t)0x00000000) -#define SDIO_DPSM_Enable ((uint32_t)0x00000001) - -/* SDIO_Flags */ -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) -#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) -#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) -#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) -#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) - -/* SDIO_Read_Wait_Mode */ -#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) -#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) - - -void SDIO_DeInit(void); -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ClockCmd(FunctionalState NewState); -void SDIO_SetPowerState(uint32_t SDIO_PowerState); -uint32_t SDIO_GetPowerState(void); -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); -void SDIO_DMACmd(FunctionalState NewState); -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); -uint8_t SDIO_GetCommandResponse(void); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -uint32_t SDIO_GetDataCounter(void); -uint32_t SDIO_ReadData(void); -void SDIO_WriteData(uint32_t Data); -uint32_t SDIO_GetFIFOCount(void); -void SDIO_StartSDIOReadWait(FunctionalState NewState); -void SDIO_StopSDIOReadWait(FunctionalState NewState); -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -void SDIO_SetSDIOOperation(FunctionalState NewState); -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); -void SDIO_CommandCompletionCmd(FunctionalState NewState); -void SDIO_CEATAITCmd(FunctionalState NewState); -void SDIO_SendCEATACmd(FunctionalState NewState); -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); -void SDIO_ClearFlag(uint32_t SDIO_FLAG); -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); -void SDIO_ClearITPendingBit(uint32_t SDIO_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_sdio.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the SDIO +* firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_SDIO_H +#define __CH32V30x_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* SDIO Init structure definition */ +typedef struct +{ + uint32_t SDIO_ClockEdge; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /* Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /* Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /* Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /* Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /* Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + + +typedef struct +{ + uint32_t SDIO_Argument; /* Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /* Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /* Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /* Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /* Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /* Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /* Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /* Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /* Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /* Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /* Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + + +/* SDIO_Clock_Edge */ +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) + +/* SDIO_Clock_Bypass */ +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) + +/* SDIO_Clock_Power_Save */ +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) + +/* SDIO_Bus_Wide */ +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) + +/* SDIO_Hardware_Flow_Control */ +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) + +/* SDIO_Power_State */ +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) + +/* SDIO_Interrupt_sources */ +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) + +/* SDIO_Response_Type */ +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) + +/* SDIO_Wait_Interrupt_State */ +#define SDIO_Wait_No ((uint32_t)0x00000000) +#define SDIO_Wait_IT ((uint32_t)0x00000100) +#define SDIO_Wait_Pend ((uint32_t)0x00000200) + +/* SDIO_CPSM_State */ +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) + +/* SDIO_Response_Registers */ +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) + +/* SDIO_Data_Block_Size */ +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) + +/* SDIO_Transfer_Direction */ +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) + +/* SDIO_Transfer_Type */ +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) + +/* SDIO_DPSM_State */ +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) + +/* SDIO_Flags */ +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) + +/* SDIO_Read_Wait_Mode */ +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) + +#define SDIO_DataControl_DTEN ((uint32_t)0x00000001) +#define SDIO_DataControl_DTDIR ((uint32_t)0x00000002) +#define SDIO_DataControl_DTMODE ((uint32_t)0x00000004) +#define SDIO_DataControl_DMAEN ((uint32_t)0x00000008) +#define SDIO_DataControl_DBLOCKSIZE ((uint32_t)0x000000F0) +#define SDIO_DataControl_RWSTART ((uint32_t)0x00000100) +#define SDIO_DataControl_RWSTOP ((uint32_t)0x00000200) +#define SDIO_DataControl_RWMOD ((uint32_t)0x00000400) +#define SDIO_DataControl_SDIOEN ((uint32_t)0x00000800) + + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_spi.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_spi.h index 46493a5..71a40fa 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_spi.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_spi.h @@ -1,231 +1,231 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_spi.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* SPI firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_SPI_H -#define __CH32V30x_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* SPI Init structure definition */ -typedef struct -{ - uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /* Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /* Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /* Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/* I2S Init structure definition */ -typedef struct -{ - - uint16_t I2S_Mode; /* Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/* SPI_data_direction */ -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) - -/* SPI_mode */ -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) - -/* SPI_data_size */ -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) - -/* SPI_Clock_Polarity */ -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) - -/* SPI_Clock_Phase */ -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) - -/* SPI_Slave_Select_management */ -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) - -/* SPI_BaudRate_Prescaler */ -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) - -/* SPI_MSB_LSB_transmission */ -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) - -/* I2S_Mode */ -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) - -/* I2S_Standard */ -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) - -/* I2S_Data_Format */ -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) - -/* I2S_MCLK_Output */ -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) - -/* I2S_Audio_Frequency */ -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -/* I2S_Clock_Polarity */ -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) - -/* SPI_I2S_DMA_transfer_requests */ -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) - -/* SPI_NSS_internal_software_management */ -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) - -/* SPI_CRC_Transmit_Receive */ -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) - -/* SPI_direction_transmit_receive */ -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) - -/* SPI_I2S_interrupts_definition */ -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) -#define I2S_IT_UDR ((uint8_t)0x53) - -/* SPI_I2S_flags_definition */ -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) - - -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_spi.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* SPI firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_SPI_H +#define __CH32V30x_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/* I2S Init structure definition */ +typedef struct +{ + + uint16_t I2S_Mode; /* Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB_transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* I2S_Mode */ +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) + +/* I2S_Standard */ +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) + +/* I2S_Data_Format */ +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) + +/* I2S_MCLK_Output */ +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) + +/* I2S_Audio_Frequency */ +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +/* I2S_Clock_Polarity */ +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_tim.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_tim.h index 06f36d0..2b33247 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_tim.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_tim.h @@ -1,517 +1,517 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_tim.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* TIM firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_TIM_H -#define __CH32V30x_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - -/* TIM Time Base Init structure definition */ -typedef struct -{ - uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /* Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint16_t TIM_Period; /* Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /* Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/* TIM Output Compare Init structure definition */ -typedef struct -{ - uint16_t TIM_OCMode; /* Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_state - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /* Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/* TIM Input Capture Init structure definition */ -typedef struct -{ - uint16_t TIM_Channel; /* Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /* Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /* Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/* BDTR structure definition */ -typedef struct -{ - uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. - This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. - This parameter can be a value of @ref Lock_level */ - - uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/* TIM_Output_Compare_and_PWM_modes */ -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) - -/* TIM_One_Pulse_Mode */ -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) - -/* TIM_Channel */ -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -/* TIM_Clock_Division_CKD */ -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) - -/* TIM_Counter_Mode */ -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) - -/* TIM_Output_Compare_Polarity */ -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) - -/* TIM_Output_Compare_N_Polarity */ -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) - -/* TIM_Output_Compare_state */ -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) - -/* TIM_Output_Compare_N_state */ -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) - -/* TIM_Capture_Compare_state */ -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) - -/* TIM_Capture_Compare_N_state */ -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) - -/* Break_Input_enable_disable */ -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) - -/* Break_Polarity */ -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) - -/* TIM_AOE_Bit_Set_Reset */ -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) - -/* Lock_level */ -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) - -/* OSSI_Off_State_Selection_for_Idle_mode_state */ -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) - -/* OSSR_Off_State_Selection_for_Run_mode_state */ -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Idle_State */ -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Output_Compare_N_Idle_State */ -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Input_Capture_Polarity */ -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) - -/* TIM_Input_Capture_Selection */ -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ - -/* TIM_Input_Capture_Prescaler */ -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ - -/* TIM_interrupt_sources */ -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) - -/* TIM_DMA_Base_address */ -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) - -/* TIM_DMA_Burst_Length */ -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) - -/* TIM_DMA_sources */ -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) - -/* TIM_External_Trigger_Prescaler */ -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) - -/* TIM_Internal_Trigger_Selection */ -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) - -/* TIM_TIx_External_Clock_Source */ -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/* TIM_External_Trigger_Polarity */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) - -/* TIM_Prescaler_Reload_Mode */ -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) - -/* TIM_Forced_Action */ -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) - -/* TIM_Encoder_Mode */ -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) - -/* TIM_Event_Source */ -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) - -/* TIM_Update_Source */ -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ - -/* TIM_Output_Compare_Preload_State */ -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Fast_State */ -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Clear_State */ -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) - -/* TIM_Trigger_Output_Source */ -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) - -/* TIM_Slave_Mode */ -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) - -/* TIM_Master_Slave_Mode */ -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) - -/* TIM_Flags */ -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) - -/* TIM_Legacy */ -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers - - -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); -uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_tim.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* TIM firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_TIM_H +#define __CH32V30x_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + + +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_usart.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_usart.h index 0467d5f..3e03594 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_usart.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_usart.h @@ -1,197 +1,195 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_usart.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the -* USART firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_USART_H -#define __CH32V30x_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - - -/* USART Init Structure definition */ -typedef struct -{ - uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /* Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/* USART Clock Init Structure definition */ -typedef struct -{ - - uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* USART_Word_Length */ -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -/* USART_Stop_Bits */ -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) - -/* USART_Parity */ -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) - -/* USART_Mode */ -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) - -/* USART_Hardware_Flow_Control */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) - -/* USART_Clock */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) - -/* USART_Clock_Polarity */ -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) - -/* USART_Clock_Phase */ -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) - -/* USART_Last_Bit */ -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) - -/* USART_Interrupt_definition */ -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) - -#define USART_IT_ORE USART_IT_ORE_ER - -/* USART_DMA_Requests */ -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) - -/* USART_WakeUp_methods */ -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) - -/* USART_LIN_Break_Detection_Length */ -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) - -/* USART_IrDA_Low_Power */ -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) - -/* USART_Flags */ -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) - - -void USART_DeInit(USART_TypeDef* USARTx); -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); -void USART_SendBreak(USART_TypeDef* USARTx); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_usart.h +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file contains all the functions prototypes for the +* USART firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_USART_H +#define __CH32V30x_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + + +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_usb.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_usb.h new file mode 100644 index 0000000..72f8a95 --- /dev/null +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_usb.h @@ -0,0 +1,834 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : system_ch32v30x.h +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/22 +* Description : CH32V30x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#ifndef __CH32V30x_USB_H +#define __CH32V30x_USB_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*******************************************************************************/ +/* Header File */ +#include "stdint.h" + +/*******************************************************************************/ +/* USB Communication Related Macro Definition */ +/* USB Endpoint0 Size */ +#ifndef DEFAULT_ENDP0_SIZE +#define DEFAULT_ENDP0_SIZE 8 // default maximum packet size for endpoint 0 +#endif +#ifndef MAX_PACKET_SIZE +#define MAX_PACKET_SIZE 64 // maximum packet size +#endif + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_NYET 0x06 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_DATA2 0x07 +#define USB_PID_MDATA 0x0F +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif + +/* Bit Define for USB Request Type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 +#define USB_REQ_TYP_OUT 0x00 +#define USB_REQ_TYP_READ 0x80 +#define USB_REQ_TYP_WRITE 0x00 +#define USB_REQ_TYP_MASK 0x60 +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB Descriptor Type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB Device Class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_IMAGE 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB Hub Class Request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub Class Feature Selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB UDisk */ +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + + +/******************************************************************************/ +/* USBHS Clock Configuration Related Macro Definition */ +#define USB_CLK_SRC 0x80000000 +#define USBHS_PLL_ALIVE 0x40000000 +#define USBHS_PLL_CKREF_MASK 0x30000000 +#define USBHS_PLL_CKREF_3M 0x00000000 +#define USBHS_PLL_CKREF_4M 0x10000000 +#define USBHS_PLL_CKREF_8M 0x20000000 +#define USBHS_PLL_CKREF_5M 0x30000000 +#define USBHS_PLL_SRC 0x08000000 +#define USBHS_PLL_SRC_PRE_MASK 0x07000000 +#define USBHS_PLL_SRC_PRE_DIV1 0x00000000 +#define USBHS_PLL_SRC_PRE_DIV2 0x01000000 +#define USBHS_PLL_SRC_PRE_DIV3 0x02000000 +#define USBHS_PLL_SRC_PRE_DIV4 0x03000000 +#define USBHS_PLL_SRC_PRE_DIV5 0x04000000 +#define USBHS_PLL_SRC_PRE_DIV6 0x05000000 +#define USBHS_PLL_SRC_PRE_DIV7 0x06000000 +#define USBHS_PLL_SRC_PRE_DIV8 0x07000000 + + +/*******************************************************************************/ +/* USBHS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBHS_UC_HOST_MODE 0x80 +#define USBHS_UC_SPEED_TYPE 0x60 +#define USBHS_UC_SPEED_LOW 0x40 +#define USBHS_UC_SPEED_FULL 0x00 +#define USBHS_UC_SPEED_HIGH 0x20 +#define USBHS_UC_DEV_PU_EN 0x10 +#define USBHS_UC_INT_BUSY 0x08 +#define USBHS_UC_RESET_SIE 0x04 +#define USBHS_UC_CLR_ALL 0x02 +#define USBHS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBHS_UIE_DEV_NAK 0x80 +#define USBHS_UIE_ISO_ACT 0x40 +#define USBHS_UIE_SETUP_ACT 0x20 +#define USBHS_UIE_FIFO_OV 0x10 +#define USBHS_UIE_SOF_ACT 0x08 +#define USBHS_UIE_SUSPEND 0x04 +#define USBHS_UIE_TRANSFER 0x02 +#define USBHS_UIE_DETECT 0x01 +#define USBHS_UIE_BUS_RST 0x01 + +/* R16_USB_DEV_AD */ +#define USBHS_MASK_USB_ADDR 0x7F + +/* R16_USB_FRAME_NO */ +#define USBHS_MICRO_FRAME_NUM 0xE000 +#define USBHS_SOF_FRAME_NUM 0x07FF + +/* R8_USB_SUSPEND */ +#define USBHS_USB_LINESTATE 0x30 +#define USBHS_USB_WAKEUP_ST 0x04 +#define USBHS_USB_SYS_MOD 0x03 + +/* R8_USB_SPEED_TYPE */ +#define USBHS_USB_SPEED_TYPE 0x03 +#define USBHS_USB_SPEED_LOW 0x02 +#define USBHS_USB_SPEED_FULL 0x00 +#define USBHS_USB_SPEED_HIGH 0x01 + +/* R8_USB_MIS_ST */ +#define USBHS_UMS_SOF_PRES 0x80 +#define USBHS_UMS_SOF_ACT 0x40 +#define USBHS_UMS_SIE_FREE 0x20 +#define USBHS_UMS_R_FIFO_RDY 0x10 +#define USBHS_UMS_BUS_RESET 0x08 +#define USBHS_UMS_SUSPEND 0x04 +#define USBHS_UMS_DEV_ATTACH 0x02 +#define USBHS_UMS_SPLIT_CAN 0x01 + +/* R8_USB_INT_FG */ +#define USBHS_UIF_ISO_ACT 0x40 +#define USBHS_UIF_SETUP_ACT 0x20 +#define USBHS_UIF_FIFO_OV 0x10 +#define USBHS_UIF_HST_SOF 0x08 +#define USBHS_UIF_SUSPEND 0x04 +#define USBHS_UIF_TRANSFER 0x02 +#define USBHS_UIF_DETECT 0x01 +#define USBHS_UIF_BUS_RST 0x01 + +/* R8_USB_INT_ST */ +#define USBHS_UIS_IS_NAK 0x80 +#define USBHS_UIS_TOG_OK 0x40 +#define USBHS_UIS_TOKEN_MASK 0x30 +#define USBHS_UIS_TOKEN_OUT 0x00 +#define USBHS_UIS_TOKEN_SOF 0x10 +#define USBHS_UIS_TOKEN_IN 0x20 +#define USBHS_UIS_TOKEN_SETUP 0x30 +#define USBHS_UIS_ENDP_MASK 0x0F +#define USBHS_UIS_H_RES_MASK 0x0F + +/* R16_USB_RX_LEN */ +#define USBHS_USB_RX_LEN 0xFFFF + +/* R32_UEP_CONFIG */ +#define USBHS_UEP15_R_EN 0x80000000 +#define USBHS_UEP14_R_EN 0x40000000 +#define USBHS_UEP13_R_EN 0x20000000 +#define USBHS_UEP12_R_EN 0x10000000 +#define USBHS_UEP11_R_EN 0x08000000 +#define USBHS_UEP10_R_EN 0x04000000 +#define USBHS_UEP9_R_EN 0x02000000 +#define USBHS_UEP8_R_EN 0x01000000 +#define USBHS_UEP7_R_EN 0x00800000 +#define USBHS_UEP6_R_EN 0x00400000 +#define USBHS_UEP5_R_EN 0x00200000 +#define USBHS_UEP4_R_EN 0x00100000 +#define USBHS_UEP3_R_EN 0x00080000 +#define USBHS_UEP2_R_EN 0x00040000 +#define USBHS_UEP1_R_EN 0x00020000 +#define USBHS_UEP0_R_EN 0x00010000 +#define USBHS_UEP15_T_EN 0x00008000 +#define USBHS_UEP14_T_EN 0x00004000 +#define USBHS_UEP13_T_EN 0x00002000 +#define USBHS_UEP12_T_EN 0x00001000 +#define USBHS_UEP11_T_EN 0x00000800 +#define USBHS_UEP10_T_EN 0x00000400 +#define USBHS_UEP9_T_EN 0x00000200 +#define USBHS_UEP8_T_EN 0x00000100 +#define USBHS_UEP7_T_EN 0x00000080 +#define USBHS_UEP6_T_EN 0x00000040 +#define USBHS_UEP5_T_EN 0x00000020 +#define USBHS_UEP4_T_EN 0x00000010 +#define USBHS_UEP3_T_EN 0x00000008 +#define USBHS_UEP2_T_EN 0x00000004 +#define USBHS_UEP1_T_EN 0x00000002 +#define USBHS_UEP0_T_EN 0x00000001 + +/* R32_UEP_TYPE */ +#define USBHS_UEP15_R_TYPE 0x80000000 +#define USBHS_UEP14_R_TYPE 0x40000000 +#define USBHS_UEP13_R_TYPE 0x20000000 +#define USBHS_UEP12_R_TYPE 0x10000000 +#define USBHS_UEP11_R_TYPE 0x08000000 +#define USBHS_UEP10_R_TYPE 0x04000000 +#define USBHS_UEP9_R_TYPE 0x02000000 +#define USBHS_UEP8_R_TYPE 0x01000000 +#define USBHS_UEP7_R_TYPE 0x00800000 +#define USBHS_UEP6_R_TYPE 0x00400000 +#define USBHS_UEP5_R_TYPE 0x00200000 +#define USBHS_UEP4_R_TYPE 0x00100000 +#define USBHS_UEP3_R_TYPE 0x00080000 +#define USBHS_UEP2_R_TYPE 0x00040000 +#define USBHS_UEP1_R_TYPE 0x00020000 +#define USBHS_UEP0_R_TYPE 0x00010000 +#define USBHS_UEP15_T_TYPE 0x00008000 +#define USBHS_UEP14_T_TYPE 0x00004000 +#define USBHS_UEP13_T_TYPE 0x00002000 +#define USBHS_UEP12_T_TYPE 0x00001000 +#define USBHS_UEP11_T_TYPE 0x00000800 +#define USBHS_UEP10_T_TYPE 0x00000400 +#define USBHS_UEP9_T_TYPE 0x00000200 +#define USBHS_UEP8_T_TYPE 0x00000100 +#define USBHS_UEP7_T_TYPE 0x00000080 +#define USBHS_UEP6_T_TYPE 0x00000040 +#define USBHS_UEP5_T_TYPE 0x00000020 +#define USBHS_UEP4_T_TYPE 0x00000010 +#define USBHS_UEP3_T_TYPE 0x00000008 +#define USBHS_UEP2_T_TYPE 0x00000004 +#define USBHS_UEP1_T_TYPE 0x00000002 +#define USBHS_UEP0_T_TYPE 0x00000001 + +/* R32_UEP_BUF_MOD */ +#define USBHS_UEP15_ISO_BUF_MOD 0x80000000 +#define USBHS_UEP14_ISO_BUF_MOD 0x40000000 +#define USBHS_UEP13_ISO_BUF_MOD 0x20000000 +#define USBHS_UEP12_ISO_BUF_MOD 0x10000000 +#define USBHS_UEP11_ISO_BUF_MOD 0x08000000 +#define USBHS_UEP10_ISO_BUF_MOD 0x04000000 +#define USBHS_UEP9_ISO_BUF_MOD 0x02000000 +#define USBHS_UEP8_ISO_BUF_MOD 0x01000000 +#define USBHS_UEP7_ISO_BUF_MOD 0x00800000 +#define USBHS_UEP6_ISO_BUF_MOD 0x00400000 +#define USBHS_UEP5_ISO_BUF_MOD 0x00200000 +#define USBHS_UEP4_ISO_BUF_MOD 0x00100000 +#define USBHS_UEP3_ISO_BUF_MOD 0x00080000 +#define USBHS_UEP2_ISO_BUF_MOD 0x00040000 +#define USBHS_UEP1_ISO_BUF_MOD 0x00020000 +#define USBHS_UEP0_ISO_BUF_MOD 0x00010000 +#define USBHS_UEP15_BUF_MOD 0x00008000 +#define USBHS_UEP14_BUF_MOD 0x00004000 +#define USBHS_UEP13_BUF_MOD 0x00002000 +#define USBHS_UEP12_BUF_MOD 0x00001000 +#define USBHS_UEP11_BUF_MOD 0x00000800 +#define USBHS_UEP10_BUF_MOD 0x00000400 +#define USBHS_UEP9_BUF_MOD 0x00000200 +#define USBHS_UEP8_BUF_MOD 0x00000100 +#define USBHS_UEP7_BUF_MOD 0x00000080 +#define USBHS_UEP6_BUF_MOD 0x00000040 +#define USBHS_UEP5_BUF_MOD 0x00000020 +#define USBHS_UEP4_BUF_MOD 0x00000010 +#define USBHS_UEP3_BUF_MOD 0x00000008 +#define USBHS_UEP2_BUF_MOD 0x00000004 +#define USBHS_UEP1_BUF_MOD 0x00000002 +#define USBHS_UEP0_BUF_MOD 0x00000001 + +/* R32_UEP0_DMA */ +#define USBHS_UEP0_DMA 0x0000FFFF + +/* R32_UEPn_TX_DMA, n=1-15 */ +#define USBHS_UEPn_TX_DMA 0x0000FFFF + +/* R32_UEPn_RX_DMA, n=1-15 */ +#define USBHS_UEPn_RX_DMA 0x0000FFFF + +/* R16_UEPn_MAX_LEN, n=0-15 */ +#define USBHS_UEPn_MAX_LEN 0x07FF + +/* R16_UEPn_T_LEN, n=0-15 */ +#define USBHS_UEPn_T_LEN 0x07FF + +/* R8_UEPn_TX_CTRL, n=0-15 */ +#define USBHS_UEP_T_TOG_AUTO 0x20 +#define USBHS_UEP_T_TOG_MASK 0x18 +#define USBHS_UEP_T_TOG_DATA0 0x00 +#define USBHS_UEP_T_TOG_DATA1 0x08 +#define USBHS_UEP_T_TOG_DATA2 0x10 +#define USBHS_UEP_T_TOG_MDATA 0x18 +#define USBHS_UEP_T_RES_MASK 0x03 +#define USBHS_UEP_T_RES_ACK 0x00 +#define USBHS_UEP_T_RES_NYET 0x01 +#define USBHS_UEP_T_RES_NAK 0x02 +#define USBHS_UEP_T_RES_STALL 0x03 + +/* R8_UEPn_TX_CTRL, n=0-15 */ +#define USBHS_UEP_R_TOG_AUTO 0x20 +#define USBHS_UEP_R_TOG_MASK 0x18 +#define USBHS_UEP_R_TOG_DATA0 0x00 +#define USBHS_UEP_R_TOG_DATA1 0x08 +#define USBHS_UEP_R_TOG_DATA2 0x10 +#define USBHS_UEP_R_TOG_MDATA 0x18 +#define USBHS_UEP_R_RES_MASK 0x03 +#define USBHS_UEP_R_RES_ACK 0x00 +#define USBHS_UEP_R_RES_NYET 0x01 +#define USBHS_UEP_R_RES_NAK 0x02 +#define USBHS_UEP_R_RES_STALL 0x03 + +/* R8_UHOST_CTRL */ +#define USBHS_UH_SOF_EN 0x80 +#define USBHS_UH_SOF_FREE 0x40 +#define USBHS_UH_PHY_SUSPENDM 0x10 +#define USBHS_UH_REMOTE_WKUP 0x08 +#define USBHS_UH_TX_BUS_RESUME 0x04 +#define USBHS_UH_TX_BUS_SUSPEND 0x02 +#define USBHS_UH_TX_BUS_RESET 0x01 + +/* R32_UH_CONFIG */ +#define USBHS_UH_EP_RX_EN 0x00040000 +#define USBHS_UH_EP_TX_EN 0x00000008 + +/* R32_UH_EP_TYPE */ +#define USBHS_UH_EP_RX_TYPE 0x00040000 +#define USBHS_UH_EP_TX_TYPE 0x00000008 + +/* R32_UH_RX_DMA */ +#define USBHS_UH_RX_DMA 0x0000FFFC + +/* R32_UH_TX_DMA */ +#define USBHS_UH_TX_DMA 0x0000FFFF + +/* R16_UH_RX_MAX_LEN */ +#define USBHS_UH_RX_MAX_LEN 0x07FF + +/* R8_UH_EP_PID */ +#define USBHS_UH_TOKEN_MASK 0xF0 +#define USBHS_UH_ENDP_MASK 0x0F + +/* R8_UH_RX_CTRL */ +#define USBHS_UH_R_DATA_NO 0x40 +#define USBHS_UH_R_TOG_AUTO 0x20 +#define USBHS_UH_R_TOG_MASK 0x18 +#define USBHS_UH_R_TOG_DATA0 0x00 +#define USBHS_UH_R_TOG_DATA1 0x08 +#define USBHS_UH_R_TOG_DATA2 0x10 +#define USBHS_UH_R_TOG_MDATA 0x18 +#define USBHS_UH_R_RES_NO 0x04 +#define USBHS_UH_R_RES_MASK 0x03 +#define USBHS_UH_R_RES_ACK 0x00 +#define USBHS_UH_R_RES_NYET 0x01 +#define USBHS_UH_R_RES_NAK 0x02 +#define USBHS_UH_R_RES_STALL 0x03 + +/* R16_UH_TX_LEN */ +#define USBHS_UH_TX_LEN 0x07FF + +/* R8_UH_TX_CTRL */ +#define USBHS_UH_T_DATA_NO 0x40 +#define USBHS_UH_T_AUTO_TOG 0x20 +#define USBHS_UH_T_TOG_MASK 0x18 +#define USBHS_UH_T_TOG_DATA0 0x00 +#define USBHS_UH_T_TOG_DATA1 0x08 +#define USBHS_UH_T_TOG_DATA2 0x10 +#define USBHS_UH_T_TOG_MDATA 0x18 +#define USBHS_UH_T_RES_NO 0x04 +#define USBHS_UH_T_RES_MASK 0x03 +#define USBHS_UH_T_RES_ACK 0x00 +#define USBHS_UH_T_RES_NYET 0x01 +#define USBHS_UH_T_RES_NAK 0x02 +#define USBHS_UH_T_RES_STALL 0x03 + +/* R16_UH_SPLIT_DATA */ +#define USBHS_UH_SPLIT_DATA 0x0FFF + + +/*******************************************************************************/ +/* USBFS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBFS_UC_HOST_MODE 0x80 +#define USBFS_UC_LOW_SPEED 0x40 +#define USBFS_UC_DEV_PU_EN 0x20 +#define USBFS_UC_SYS_CTRL_MASK 0x30 +#define USBFS_UC_SYS_CTRL0 0x00 +#define USBFS_UC_SYS_CTRL1 0x10 +#define USBFS_UC_SYS_CTRL2 0x20 +#define USBFS_UC_SYS_CTRL3 0x30 +#define USBFS_UC_INT_BUSY 0x08 +#define USBFS_UC_RESET_SIE 0x04 +#define USBFS_UC_CLR_ALL 0x02 +#define USBFS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBFS_UIE_DEV_SOF 0x80 +#define USBFS_UIE_DEV_NAK 0x40 +#define USBFS_1WIRE_MODE 0x20 +#define USBFS_UIE_FIFO_OV 0x10 +#define USBFS_UIE_HST_SOF 0x08 +#define USBFS_UIE_SUSPEND 0x04 +#define USBFS_UIE_TRANSFER 0x02 +#define USBFS_UIE_DETECT 0x01 +#define USBFS_UIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +/* R8_USB_MIS_ST */ +#define USBFS_UMS_SOF_PRES 0x80 +#define USBFS_UMS_SOF_ACT 0x40 +#define USBFS_UMS_SIE_FREE 0x20 +#define USBFS_UMS_R_FIFO_RDY 0x10 +#define USBFS_UMS_BUS_RESET 0x08 +#define USBFS_UMS_SUSPEND 0x04 +#define USBFS_UMS_DM_LEVEL 0x02 +#define USBFS_UMS_DEV_ATTACH 0x01 + +/* R8_USB_INT_FG */ +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* R8_USB_INT_ST */ +#define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_SOF 0x10 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +/* R32_USB_OTG_CR */ +#define USBFS_CR_SESS_VTH 0x20 +#define USBFS_CR_VBUS_VTH 0x10 +#define USBFS_CR_OTG_EN 0x08 +#define USBFS_CR_IDPU 0x04 +#define USBFS_CR_CHARGE_VBUS 0x02 +#define USBFS_CR_DISCHAR_VBUS 0x01 + +/* R32_USB_OTG_SR */ +#define USBFS_SR_ID_DIG 0x08 +#define USBFS_SR_SESS_END 0x04 +#define USBFS_SR_SESS_VLD 0x02 +#define USBFS_SR_VBUS_VLD 0x01 + +/* R8_UDEV_CTRL */ +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* R8_UEP4_1_MOD */ +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +#define USBFS_UEP4_BUF_MOD 0x01 + +/* R8_UEP2_3_MOD */ +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* R8_UEP5_6_MOD */ +#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +/* R8_UEP7_MOD */ +#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +/* R8_UEPn_TX_CTRL */ +#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK 0x00 +#define USBFS_UEP_T_RES_NONE 0x01 +#define USBFS_UEP_T_RES_NAK 0x02 +#define USBFS_UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +// host aux setup + +/* R8_UEPn_RX_CTRL, n=0-7 */ +#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK 0x00 +#define USBFS_UEP_R_RES_NONE 0x01 +#define USBFS_UEP_R_RES_NAK 0x02 +#define USBFS_UEP_R_RES_STALL 0x03 +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +/* R8_UHOST_CTRL */ +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +/* R32_UH_EP_MOD */ +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +/* R16_UH_SETUP */ +#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable + +/* R8_UH_EP_PID */ +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + +/* R8_UH_RX_CTRL */ +#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +/* R8_UH_TX_CTRL */ +#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + + +/*******************************************************************************/ +/* Struct Definition */ + +/* USB Setup Request */ +typedef struct __attribute__((packed)) _USB_SETUP_REQ +{ + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + +/* USB Device Descriptor */ +typedef struct __attribute__((packed)) _USB_DEVICE_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + +/* USB Configuration Descriptor */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + +/* USB Interface Descriptor */ +typedef struct __attribute__((packed)) _USB_INTERF_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + +/* USB Endpoint Descriptor */ +typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSizeL; + uint8_t wMaxPacketSizeH; + uint8_t bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + +/* USB Configuration Descriptor Set */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG +{ + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[ 1 ]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + +/* USB HUB Descriptor */ +typedef struct __attribute__((packed)) _USB_HUB_DESCR +{ + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint8_t wHubCharacteristicsL; + uint8_t wHubCharacteristicsH; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + +/* USB HID Descriptor */ +typedef struct __attribute__((packed)) _USB_HID_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bDescriptorTypeX; + uint8_t wDescriptorLengthL; + uint8_t wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CBW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCBW_DataLen; + uint8_t mCBW_Flag; + uint8_t mCBW_LUN; + uint8_t mCBW_CB_Len; + uint8_t mCBW_CB_Buf[ 16 ]; +} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CSW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCSW_Residue; + uint8_t mCSW_Status; +} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; + + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V30x_USB_H */ diff --git a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_wwdg.h b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_wwdg.h index 809b2ec..40377c3 100644 --- a/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_wwdg.h +++ b/system/CH32V30x/SRC/Peripheral/inc/ch32v30x_wwdg.h @@ -1,44 +1,44 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_wwdg.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains all the functions prototypes for the WWDG -* firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_WWDG_H -#define __CH32V30x_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "ch32v30x.h" - - -/* WWDG_Prescaler */ -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) - - -void WWDG_DeInit(void); -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); -void WWDG_Enable(uint8_t Counter); -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_wwdg.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the WWDG +* firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_WWDG_H +#define __CH32V30x_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_adc.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_adc.c index 54ed35e..221f13f 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_adc.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_adc.c @@ -1,1182 +1,1182 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_adc.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the ADC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_adc.h" -#include "ch32v30x_rcc.h" - -/* ADC DISCNUM mask */ -#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) -#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) - -/* ADC JAUTO mask */ -#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) -#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) - -/* ADC AWDCH mask */ -#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) - -/* CTLR1 register Mask */ -#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) - -/* ADC ADON mask */ -#define CTLR2_ADON_Set ((uint32_t)0x00000001) -#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CTLR2_DMA_Set ((uint32_t)0x00000100) -#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) - -/* ADC RSTCAL mask */ -#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) - -/* ADC CAL mask */ -#define CTLR2_CAL_Set ((uint32_t)0x00000004) - -/* ADC SWSTART mask */ -#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) - -/* ADC EXTTRIG mask */ -#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) - -/* ADC JEXTSEL mask */ -#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTART mask */ -#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) - -/* ADC TSPD mask */ -#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) -#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) - -/* CTLR2 register Mask */ -#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) - -/* ADC SQx mask */ -#define RSQR3_SQ_Set ((uint32_t)0x0000001F) -#define RSQR2_SQ_Set ((uint32_t)0x0000001F) -#define RSQR1_SQ_Set ((uint32_t)0x0000001F) - -/* RSQR1 register Mask */ -#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define ISQR_JSQ_Set ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define ISQR_JL_Set ((uint32_t)0x00300000) -#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) -#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) - -/* ADC IDATARx registers offset */ -#define IDATAR_Offset ((uint8_t)0x28) - -/* ADC1 RDATAR register base address */ -#define RDATAR_ADDRESS ((uint32_t)0x4001244C) - -/********************************************************************* - * @fn ADC_DeInit - * - * @brief Deinitializes the ADCx peripheral registers to their default - * reset values. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return none - */ -void ADC_DeInit(ADC_TypeDef *ADCx) -{ - if(ADCx == ADC1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); - } - else if(ADCx == ADC2) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); - } -} - -/********************************************************************* - * @fn ADC_Init - * - * @brief Initializes the ADCx peripheral according to the specified - * parameters in the ADC_InitStruct. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | - (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); - ADCx->CTLR1 = tmpreg1; - - tmpreg1 = ADCx->CTLR2; - tmpreg1 &= CTLR2_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - ADCx->CTLR2 = tmpreg1; - - tmpreg1 = ADCx->RSQR1; - tmpreg1 &= RSQR1_CLEAR_Mask; - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); - tmpreg1 |= (uint32_t)tmpreg2 << 20; - ADCx->RSQR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_StructInit - * - * @brief Fills each ADC_InitStruct member with its default value. - * - * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) -{ - ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStruct->ADC_NbrOfChannel = 1; -} - -/********************************************************************* - * @fn ADC_Cmd - * - * @brief Enables or disables the specified ADC peripheral. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_ADON_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_ADON_Reset; - } -} - -/********************************************************************* - * @fn ADC_DMACmd - * - * @brief Enables or disables the specified ADC DMA request. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_DMA_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_DMA_Reset; - } -} - -/********************************************************************* - * @fn ADC_ITConfig - * - * @brief Enables or disables the specified ADC interrupts. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)ADC_IT; - - if(NewState != DISABLE) - { - ADCx->CTLR1 |= itmask; - } - else - { - ADCx->CTLR1 &= (~(uint32_t)itmask); - } -} - -/********************************************************************* - * @fn ADC_ResetCalibration - * - * @brief Resets the selected ADC calibration registers. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return none - */ -void ADC_ResetCalibration(ADC_TypeDef *ADCx) -{ - ADCx->CTLR2 |= CTLR2_RSTCAL_Set; -} - -/********************************************************************* - * @fn ADC_GetResetCalibrationStatus - * - * @brief Gets the selected ADC reset calibration registers status. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_StartCalibration - * - * @brief Starts the selected ADC calibration process. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return None - */ -void ADC_StartCalibration(ADC_TypeDef *ADCx) -{ - ADCx->CTLR2 |= CTLR2_CAL_Set; -} - -/********************************************************************* - * @fn ADC_GetCalibrationStatus - * - * @brief Gets the selected ADC calibration status. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_SoftwareStartConvCmd - * - * @brief Enables or disables the selected ADC software start conversion. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartConvStatus - * - * @brief Gets the selected ADC Software start conversion Status. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_DiscModeChannelCountConfig - * - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * Number - specifies the discontinuous mode regular channel - * count value(1-8). - * - * @return None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_DISCNUM_Reset; - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - ADCx->CTLR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_DiscModeCmd - * - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_DISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_DISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_RegularChannelConfig - * - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_10 - ADC Channel10 selected. - * ADC_Channel_11 - ADC Channel11 selected. - * ADC_Channel_12 - ADC Channel12 selected. - * ADC_Channel_13 - ADC Channel13 selected. - * ADC_Channel_14 - ADC Channel14 selected. - * ADC_Channel_15 - ADC Channel15 selected. - * ADC_Channel_16 - ADC Channel16 selected. - * ADC_Channel_17 - ADC Channel17 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. - * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. - * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. - * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. - * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. - * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. - * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. - * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. - * - * @return None - */ -void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - if(Rank < 7) - { - tmpreg1 = ADCx->RSQR3; - tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - tmpreg1 |= tmpreg2; - ADCx->RSQR3 = tmpreg1; - } - else if(Rank < 13) - { - tmpreg1 = ADCx->RSQR2; - tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - tmpreg1 |= tmpreg2; - ADCx->RSQR2 = tmpreg1; - } - else - { - tmpreg1 = ADCx->RSQR1; - tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - tmpreg1 |= tmpreg2; - ADCx->RSQR1 = tmpreg1; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigConvCmd - * - * @brief Enables or disables the ADCx conversion through external trigger. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetConversionValue - * - * @brief Returns the last ADCx conversion result data for regular channel. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return ADCx->RDATAR - The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) -{ - return (uint16_t)ADCx->RDATAR; -} - -/********************************************************************* - * @fn ADC_GetDualModeConversionValue - * - * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. - * - * @return RDATAR_ADDRESS - The Data conversion value. - */ -uint32_t ADC_GetDualModeConversionValue(void) -{ - return (*(__IO uint32_t *)RDATAR_ADDRESS); -} - -/********************************************************************* - * @fn ADC_AutoInjectedConvCmd - * - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JAUTO_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JAUTO_Reset; - } -} - -/********************************************************************* - * @fn ADC_InjectedDiscModeCmd - * - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JDISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvConfig - * - * @brief Configures the ADCx external trigger for injected channels conversion. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start - * injected conversion. - * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. - * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. - * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. - * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. - * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. - * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. - * ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 - External interrupt - * line 15 event selected. - * ADC_ExternalTrigInjecConv_None: Injected conversion started - * by software and not by external trigger. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR2; - tmpreg &= CTLR2_JEXTSEL_Reset; - tmpreg |= ADC_ExternalTrigInjecConv; - ADCx->CTLR2 = tmpreg; -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvCmd - * - * @brief Enables or disables the ADCx injected channels conversion through - * external trigger. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_SoftwareStartInjectedConvCmd - * - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartInjectedConvCmdStatus - * - * @brief Gets the selected ADC Software start injected conversion Status. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_InjectedChannelConfig - * - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_10 - ADC Channel10 selected. - * ADC_Channel_11 - ADC Channel11 selected. - * ADC_Channel_12 - ADC Channel12 selected. - * ADC_Channel_13 - ADC Channel13 selected. - * ADC_Channel_14 - ADC Channel14 selected. - * ADC_Channel_15 - ADC Channel15 selected. - * ADC_Channel_16 - ADC Channel16 selected. - * ADC_Channel_17 - ADC Channel17 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 4. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. - * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. - * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. - * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. - * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. - * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. - * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. - * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. - * - * @return None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - tmpreg1 = ADCx->ISQR; - tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; - tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 |= tmpreg2; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_InjectedSequencerLengthConfig - * - * @brief Configures the sequencer length for injected channels. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * Length - The sequencer length. - * This parameter must be a number between 1 to 4. - * - * @return None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->ISQR; - tmpreg1 &= ISQR_JL_Reset; - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_SetInjectedOffset - * - * @brief Set the injected channels conversion value offset. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_InjectedChannel: the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * Offset - the offset value for the selected ADC injected channel. - * This parameter must be a 12bit value. - * - * @return None - */ -void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - *(__IO uint32_t *)tmp = (uint32_t)Offset; -} - -/********************************************************************* - * @fn ADC_GetInjectedConversionValue - * - * @brief Returns the ADC injected channel conversion result. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_InjectedChannel - the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * - * @return tmp - The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + IDATAR_Offset; - - return (uint16_t)(*(__IO uint32_t *)tmp); -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogCmd - * - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_AnalogWatchdog - the ADC analog watchdog configuration. - * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a - * single regular channel. - * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a - * single injected channel. - * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog - * on a single regular or injected channel. - * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all - * regular channel. - * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all - * injected channel. - * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on - * all regular and injected channels. - * ADC_AnalogWatchdog_None - No channel guarded by the analog - * watchdog. - * - * @return none - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDMode_Reset; - tmpreg |= ADC_AnalogWatchdog; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogThresholdsConfig - * - * @brief Configures the high and low thresholds of the analog watchdog. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * HighThreshold - the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * LowThreshold - the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * - * @return none - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - ADCx->WDHTR = HighThreshold; - ADCx->WDLTR = LowThreshold; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogSingleChannelConfig - * - * @brief Configures the analog watchdog guarded single channel. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_10 - ADC Channel10 selected. - * ADC_Channel_11 - ADC Channel11 selected. - * ADC_Channel_12 - ADC Channel12 selected. - * ADC_Channel_13 - ADC Channel13 selected. - * ADC_Channel_14 - ADC Channel14 selected. - * ADC_Channel_15 - ADC Channel15 selected. - * ADC_Channel_16 - ADC Channel16 selected. - * ADC_Channel_17 - ADC Channel17 selected. - * - * @return None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDCH_Reset; - tmpreg |= ADC_Channel; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_TempSensorVrefintCmd - * - * @brief Enables or disables the temperature sensor and Vrefint channel. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADC1->CTLR2 |= CTLR2_TSVREFE_Set; - } - else - { - ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetFlagStatus - * - * @brief Checks whether the specified ADC flag is set or not. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to check. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearFlag - * - * @brief Clears the ADCx's pending flags. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to clear. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return none - */ -void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - ADCx->STATR = ~(uint32_t)ADC_FLAG; -} - -/********************************************************************* - * @fn ADC_GetITStatus - * - * @brief Checks whether the specified ADC interrupt has occurred or not. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt source to check. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return FlagStatus: SET or RESET. - */ -ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - itmask = ADC_IT >> 8; - enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); - - if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearITPendingBit - * - * @brief Clears the ADCx's interrupt pending bits. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt pending bit to clear. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return none - */ -void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)(ADC_IT >> 8); - ADCx->STATR = ~(uint32_t)itmask; -} - -/********************************************************************* - * @fn TempSensor_Volt_To_Temper - * - * @brief Internal Temperature Sensor Voltage to temperature. - * - * @param Value - Voltage Value(mv). - * - * @return Temper - Temperature Value. - */ -s32 TempSensor_Volt_To_Temper(s32 Value) -{ - s32 Temper, Refer_Volt, Refer_Temper; - s32 k = 43; - - Refer_Volt = (s32)((*(u32 *)0x1FFFF720) & 0x0000FFFF); - Refer_Temper = (s32)(((*(u32 *)0x1FFFF720) >> 16) & 0x0000FFFF); - - Temper = Refer_Temper - ((Value - Refer_Volt) * 10 + (k >> 1)) / k; - - return Temper; -} - -/********************************************************************* - * @fn ADC_BufferCmd - * - * @brief Enables or disables the ADCx buffer. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= (1 << 26); - } - else - { - ADCx->CTLR1 &= ~(1 << 26); - } -} - -/********************************************************************* - * @fn Get_CalibrationValue - * - * @brief Get ADCx Calibration Value. - * - * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. - * - * @return CalibrationValue - */ -int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) -{ - __IO uint8_t i, j; - uint16_t buf[10]; - __IO uint16_t t; - - for(i = 0; i < 10; i++) - { - ADC_ResetCalibration(ADCx); - while(ADC_GetResetCalibrationStatus(ADCx)) - ; - ADC_StartCalibration(ADCx); - while(ADC_GetCalibrationStatus(ADCx)) - ; - buf[i] = ADCx->RDATAR; - } - - for(i = 0; i < 10; i++) - { - for(j = 0; j < 9; j++) - { - if(buf[j] > buf[j + 1]) - { - t = buf[j]; - buf[j] = buf[j + 1]; - buf[j + 1] = t; - } - } - } - - t = 0; - for(i = 0; i < 6; i++) - { - t += buf[i + 2]; - } - - t = (t / 6) + ((t % 6) / 3); - - return (int16_t)(2048 - (int16_t)t); -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_adc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the ADC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_adc.h" +#include "ch32v30x_rcc.h" + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } + else if(ADCx == ADC2) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | + (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_ResetCalibration + * + * @brief Resets the selected ADC calibration registers. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return none + */ +void ADC_ResetCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_RSTCAL_Set; +} + +/********************************************************************* + * @fn ADC_GetResetCalibrationStatus + * + * @brief Gets the selected ADC reset calibration registers status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_StartCalibration + * + * @brief Starts the selected ADC calibration process. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return None + */ +void ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_CAL_Set; +} + +/********************************************************************* + * @fn ADC_GetCalibrationStatus + * + * @brief Gets the selected ADC calibration status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_GetDualModeConversionValue + * + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * + * @return RDATAR_ADDRESS - The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + return (*(__IO uint32_t *)RDATAR_ADDRESS); +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. + * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. + * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. + * ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 - External interrupt + * line 15 event selected. + * ADC_ExternalTrigInjecConv_None: Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 4. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 12bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_TempSensorVrefintCmd + * + * @brief Enables or disables the temperature sensor and Vrefint channel. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADC1->CTLR2 |= CTLR2_TSVREFE_Set; + } + else + { + ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn TempSensor_Volt_To_Temper + * + * @brief Internal Temperature Sensor Voltage to temperature. + * + * @param Value - Voltage Value(mv). + * + * @return Temper - Temperature Value. + */ +s32 TempSensor_Volt_To_Temper(s32 Value) +{ + s32 Temper, Refer_Volt, Refer_Temper; + s32 k = 43; + + Refer_Volt = (s32)((*(u32 *)0x1FFFF720) & 0x0000FFFF); + Refer_Temper = (s32)(((*(u32 *)0x1FFFF720) >> 16) & 0x0000FFFF); + + Temper = Refer_Temper - ((Value - Refer_Volt) * 10 + (k >> 1)) / k; + + return Temper; +} + +/********************************************************************* + * @fn ADC_BufferCmd + * + * @brief Enables or disables the ADCx buffer. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= (1 << 26); + } + else + { + ADCx->CTLR1 &= ~(1 << 26); + } +} + +/********************************************************************* + * @fn Get_CalibrationValue + * + * @brief Get ADCx Calibration Value. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return CalibrationValue + */ +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) +{ + __IO uint8_t i, j; + uint16_t buf[10]; + __IO uint16_t t; + + for(i = 0; i < 10; i++) + { + ADC_ResetCalibration(ADCx); + while(ADC_GetResetCalibrationStatus(ADCx)) + ; + ADC_StartCalibration(ADCx); + while(ADC_GetCalibrationStatus(ADCx)) + ; + buf[i] = ADCx->RDATAR; + } + + for(i = 0; i < 10; i++) + { + for(j = 0; j < 9; j++) + { + if(buf[j] > buf[j + 1]) + { + t = buf[j]; + buf[j] = buf[j + 1]; + buf[j + 1] = t; + } + } + } + + t = 0; + for(i = 0; i < 6; i++) + { + t += buf[i + 2]; + } + + t = (t / 6) + ((t % 6) / 3); + + return (int16_t)(2048 - (int16_t)t); +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_bkp.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_bkp.c index 50da947..3573561 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_bkp.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_bkp.c @@ -1,244 +1,244 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_bkp.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the BKP firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_bkp.h" -#include "ch32v30x_rcc.h" - -/* BKP registers bit mask */ - -/* OCTLR register bit mask */ -#define OCTLR_CAL_MASK ((uint16_t)0xFF80) -#define OCTLR_MASK ((uint16_t)0xFC7F) - -/********************************************************************* - * @fn BKP_DeInit - * - * @brief Deinitializes the BKP peripheral registers to their default reset values. - * - * @return none - */ -void BKP_DeInit(void) -{ - RCC_BackupResetCmd(ENABLE); - RCC_BackupResetCmd(DISABLE); -} - -/********************************************************************* - * @fn BKP_TamperPinLevelConfig - * - * @brief Configures the Tamper Pin active level. - * - * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. - * BKP_TamperPinLevel_High - Tamper pin active on high level. - * BKP_TamperPinLevel_Low - Tamper pin active on low level. - * - * @return none - */ -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) -{ - if(BKP_TamperPinLevel) - { - BKP->TPCTLR |= (1 << 1); - } - else - { - BKP->TPCTLR &= ~(1 << 1); - } -} - -/********************************************************************* - * @fn BKP_TamperPinCmd - * - * @brief Enables or disables the Tamper Pin activation. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void BKP_TamperPinCmd(FunctionalState NewState) -{ - if(NewState) - { - BKP->TPCTLR |= (1 << 0); - } - else - { - BKP->TPCTLR &= ~(1 << 0); - } -} - -/********************************************************************* - * @fn BKP_ITConfig - * - * @brief Enables or disables the Tamper Pin Interrupt. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void BKP_ITConfig(FunctionalState NewState) -{ - if(NewState) - { - BKP->TPCSR |= (1 << 2); - } - else - { - BKP->TPCSR &= ~(1 << 2); - } -} - -/********************************************************************* - * @fn BKP_RTCOutputConfig - * - * @brief Select the RTC output source to output on the Tamper pin. - * - * @param BKP_RTCOutputSource - specifies the RTC output source. - * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. - * BKP_RTCOutputSource_CalibClock - output the RTC clock with - * frequency divided by 64 on the Tamper pin. - * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal - * on the Tamper pin. - * BKP_RTCOutputSource_Second - output the RTC Second pulse - * signal on the Tamper pin. - * - * @return none - */ -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) -{ - uint16_t tmpreg = 0; - - tmpreg = BKP->OCTLR; - tmpreg &= OCTLR_MASK; - tmpreg |= BKP_RTCOutputSource; - BKP->OCTLR = tmpreg; -} - -/********************************************************************* - * @fn BKP_SetRTCCalibrationValue - * - * @brief Sets RTC Clock Calibration value. - * - * @param CalibrationValue - specifies the RTC Clock Calibration value. - * This parameter must be a number between 0 and 0x1F. - * - * @return none - */ -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) -{ - uint16_t tmpreg = 0; - - tmpreg = BKP->OCTLR; - tmpreg &= OCTLR_CAL_MASK; - tmpreg |= CalibrationValue; - BKP->OCTLR = tmpreg; -} - -/********************************************************************* - * @fn BKP_WriteBackupRegister - * - * @brief Writes user data to the specified Data Backup Register. - * - * @param BKP_DR - specifies the Data Backup Register. - * Data - data to write. - * - * @return none - */ -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - *(__IO uint32_t *)tmp = Data; -} - -/********************************************************************* - * @fn BKP_ReadBackupRegister - * - * @brief Reads data from the specified Data Backup Register. - * - * @param BKP_DR - specifies the Data Backup Register. - * This parameter can be BKP_DRx where x=[1, 42]. - * - * @return none - */ -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - return (*(__IO uint16_t *)tmp); -} - -/********************************************************************* - * @fn BKP_GetFlagStatus - * - * @brief Checks whether the Tamper Pin Event flag is set or not. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus BKP_GetFlagStatus(void) -{ - if(BKP->TPCSR & (1 << 8)) - { - return SET; - } - else - { - return RESET; - } -} - -/********************************************************************* - * @fn BKP_ClearFlag - * - * @brief Clears Tamper Pin Event pending flag. - * - * @return none - */ -void BKP_ClearFlag(void) -{ - BKP->TPCSR |= BKP_CTE; -} - -/********************************************************************* - * @fn BKP_GetITStatus - * - * @brief Checks whether the Tamper Pin Interrupt has occurred or not. - * - * @return ITStatus - SET or RESET. - */ -ITStatus BKP_GetITStatus(void) -{ - if(BKP->TPCSR & (1 << 9)) - { - return SET; - } - else - { - return RESET; - } -} - -/********************************************************************* - * @fn BKP_ClearITPendingBit - * - * @brief Clears Tamper Pin Interrupt pending bit. - * - * @return none - */ -void BKP_ClearITPendingBit(void) -{ - BKP->TPCSR |= BKP_CTI; -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_bkp.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file provides all the BKP firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_bkp.h" +#include "ch32v30x_rcc.h" + +/* BKP registers bit mask */ + +/* OCTLR register bit mask */ +#define OCTLR_CAL_MASK ((uint16_t)0xFF80) +#define OCTLR_MASK ((uint16_t)0xFC7F) + +/********************************************************************* + * @fn BKP_DeInit + * + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * + * @return none + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/********************************************************************* + * @fn BKP_TamperPinLevelConfig + * + * @brief Configures the Tamper Pin active level. + * + * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. + * BKP_TamperPinLevel_High - Tamper pin active on high level. + * BKP_TamperPinLevel_Low - Tamper pin active on low level. + * + * @return none + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + if(BKP_TamperPinLevel) + { + BKP->TPCTLR |= (1 << 1); + } + else + { + BKP->TPCTLR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn BKP_TamperPinCmd + * + * @brief Enables or disables the Tamper Pin activation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCTLR |= (1 << 0); + } + else + { + BKP->TPCTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn BKP_ITConfig + * + * @brief Enables or disables the Tamper Pin Interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_ITConfig(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCSR |= (1 << 2); + } + else + { + BKP->TPCSR &= ~(1 << 2); + } +} + +/********************************************************************* + * @fn BKP_RTCOutputConfig + * + * @brief Select the RTC output source to output on the Tamper pin. + * + * @param BKP_RTCOutputSource - specifies the RTC output source. + * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. + * BKP_RTCOutputSource_CalibClock - output the RTC clock with + * frequency divided by 64 on the Tamper pin. + * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal + * on the Tamper pin. + * BKP_RTCOutputSource_Second - output the RTC Second pulse + * signal on the Tamper pin. + * + * @return none + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_MASK; + tmpreg |= BKP_RTCOutputSource; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_SetRTCCalibrationValue + * + * @brief Sets RTC Clock Calibration value. + * + * @param CalibrationValue - specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x7F. + * + * @return none + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_CAL_MASK; + tmpreg |= CalibrationValue; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_WriteBackupRegister + * + * @brief Writes user data to the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * Data - data to write. + * + * @return none + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn BKP_ReadBackupRegister + * + * @brief Reads data from the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * This parameter can be BKP_DRx where x=[1, 42]. + * + * @return none + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn BKP_GetFlagStatus + * + * @brief Checks whether the Tamper Pin Event flag is set or not. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus BKP_GetFlagStatus(void) +{ + if(BKP->TPCSR & (1 << 8)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearFlag + * + * @brief Clears Tamper Pin Event pending flag. + * + * @return none + */ +void BKP_ClearFlag(void) +{ + BKP->TPCSR |= BKP_CTE; +} + +/********************************************************************* + * @fn BKP_GetITStatus + * + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * + * @return ITStatus - SET or RESET. + */ +ITStatus BKP_GetITStatus(void) +{ + if(BKP->TPCSR & (1 << 9)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearITPendingBit + * + * @brief Clears Tamper Pin Interrupt pending bit. + * + * @return none + */ +void BKP_ClearITPendingBit(void) +{ + BKP->TPCSR |= BKP_CTI; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_can.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_can.c index 7fe1026..b6d3d8c 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_can.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_can.c @@ -1,1218 +1,1218 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_can.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the CAN firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_can.h" -#include "ch32v30x_rcc.h" - -/* CAN CTLR Register bits */ -#define CTLR_DBF ((uint32_t)0x00010000) - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) - -/* CAN FCTLR Register bits */ -#define FCTLR_FINIT ((uint32_t)0x00000001) - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) - -/* Flags in TSTATR register */ -#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) -/* Flags in RFIFO1 register */ -#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) -/* Flags in RFIFO0 register */ -#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) -/* Flags in STATR register */ -#define CAN_FLAGS_STATR ((uint32_t)0x01000000) -/* Flags in ERRSR register */ -#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - -#define CAN_MODE_MASK ((uint32_t)0x00000003) - -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - -/********************************************************************* - * @fn CAN_DeInit - * - * @brief Deinitializes the CAN peripheral registers to their default reset - * values. - * - * @param CANx - where x can be 1 or 2 to select the CAN peripheral. - * - * @return none - */ -void CAN_DeInit(CAN_TypeDef *CANx) -{ - if(CANx == CAN1) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); - } - else - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); - } -} - -/********************************************************************* - * @fn CAN_Init - * - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_InitStruct - pointer to a CAN_InitTypeDef structure that - * contains the configuration information for the CAN peripheral. - * - * @return InitStatus - CAN InitStatus state. - * CAN_InitStatus_Failed. - * CAN_InitStatus_Success. - */ -uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - uint32_t wait_ack = 0x00000000; - - CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); - CANx->CTLR |= CAN_CTLR_INRQ; - - while(((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - if((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - if(CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_TTCM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; - } - - if(CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_ABOM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; - } - - if(CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_AWUM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; - } - - if(CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->CTLR |= CAN_CTLR_NART; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; - } - - if(CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->CTLR |= CAN_CTLR_RFLM; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFLM; - } - - if(CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->CTLR |= CAN_CTLR_TXFP; - } - else - { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; - } - - CANx->BTIMR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | - ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | - ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; - wait_ack = 0; - - while(((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - if((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success; - } - } - - return InitStatus; -} - -/********************************************************************* - * @fn CAN_FilterInit - * - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_FilterInitStruct. - * - * @param CAN_FilterInitStruct - pointer to a CAN_FilterInitTypeDef - * structure that contains the configuration information. - * - * @return none - */ -void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - CAN1->FCTLR |= FCTLR_FINIT; - CAN1->FWR &= ~(uint32_t)filter_number_bit_pos; - - if(CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - CAN1->FSCFGR &= ~(uint32_t)filter_number_bit_pos; - - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if(CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - CAN1->FSCFGR |= filter_number_bit_pos; - - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - if(CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos; - } - else - { - CAN1->FMCFGR |= (uint32_t)filter_number_bit_pos; - } - - if(CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - CAN1->FAFIFOR &= ~(uint32_t)filter_number_bit_pos; - } - - if(CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - CAN1->FAFIFOR |= (uint32_t)filter_number_bit_pos; - } - - if(CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FWR |= filter_number_bit_pos; - } - - CAN1->FCTLR &= ~FCTLR_FINIT; -} - -/********************************************************************* - * @fn CAN_StructInit - * - * @brief Fills each CAN_InitStruct member with its default value. - * - * @param CAN_InitStruct - pointer to a CAN_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct) -{ - CAN_InitStruct->CAN_TTCM = DISABLE; - CAN_InitStruct->CAN_ABOM = DISABLE; - CAN_InitStruct->CAN_AWUM = DISABLE; - CAN_InitStruct->CAN_NART = DISABLE; - CAN_InitStruct->CAN_RFLM = DISABLE; - CAN_InitStruct->CAN_TXFP = DISABLE; - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - CAN_InitStruct->CAN_Prescaler = 1; -} - -/********************************************************************* - * @fn CAN_SlaveStartBank - * - * @brief This function applies only to CH32 Connectivity line devices. - * - * @param CAN_BankNumber - Select the start slave bank filter from 1..27. - * - * @return none - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - CAN1->FCTLR |= FCTLR_FINIT; - CAN1->FCTLR &= (uint32_t)0xFFFFC0F1; - CAN1->FCTLR |= (uint32_t)(CAN_BankNumber) << 8; - CAN1->FCTLR &= ~FCTLR_FINIT; -} - -/********************************************************************* - * @fn CAN_DBGFreeze - * - * @brief Enables or disables the DBG Freeze for CAN. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - CANx->CTLR |= CTLR_DBF; - } - else - { - CANx->CTLR &= ~CTLR_DBF; - } -} - -/********************************************************************* - * @fn CAN_TTComModeCmd - * - * @brief Enables or disabes the CAN Time TriggerOperation communication mode. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * NewState - ENABLE or DISABLE. - * Note- - * DLC must be programmed as 8 in order Time Stamp (2 bytes) to be - * sent over the CAN bus. - * - * @return none - */ -void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - CANx->CTLR |= CAN_CTLR_TTCM; - - CANx->sTxMailBox[0].TXMDTR |= ((uint32_t)CAN_TXMDT0R_TGT); - CANx->sTxMailBox[1].TXMDTR |= ((uint32_t)CAN_TXMDT1R_TGT); - CANx->sTxMailBox[2].TXMDTR |= ((uint32_t)CAN_TXMDT2R_TGT); - } - else - { - CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTCM); - - CANx->sTxMailBox[0].TXMDTR &= ((uint32_t)~CAN_TXMDT0R_TGT); - CANx->sTxMailBox[1].TXMDTR &= ((uint32_t)~CAN_TXMDT1R_TGT); - CANx->sTxMailBox[2].TXMDTR &= ((uint32_t)~CAN_TXMDT2R_TGT); - } -} - -/********************************************************************* - * @fn CAN_Transmit - * - * @brief Initiates the transmission of a message. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * TxMessage - pointer to a structure which contains CAN Id, CAN - * DLC and CAN data. - * - * @return transmit_mailbox - The number of the mailbox that is used for - * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage) -{ - uint8_t transmit_mailbox = 0; - - if((CANx->TSTATR & CAN_TSTATR_TME0) == CAN_TSTATR_TME0) - { - transmit_mailbox = 0; - } - else if((CANx->TSTATR & CAN_TSTATR_TME1) == CAN_TSTATR_TME1) - { - transmit_mailbox = 1; - } - else if((CANx->TSTATR & CAN_TSTATR_TME2) == CAN_TSTATR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if(transmit_mailbox != CAN_TxStatus_NoMailBox) - { - CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; - if(TxMessage->IDE == CAN_Id_Standard) - { - CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | - TxMessage->RTR); - } - else - { - CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | - TxMessage->IDE | - TxMessage->RTR); - } - - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; - - CANx->sTxMailBox[transmit_mailbox].TXMDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TXMDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; - } - - return transmit_mailbox; -} - -/********************************************************************* - * @fn CAN_TransmitStatus - * - * @brief Checks the transmission of a message. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * TransmitMailbox - the number of the mailbox that is used for - * transmission. - * - * @return state - - * CAN_TxStatus_Ok. - * CAN_TxStatus_Failed. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - switch(TransmitMailbox) - { - case(CAN_TXMAILBOX_0): - state = CANx->TSTATR & (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0); - break; - - case(CAN_TXMAILBOX_1): - state = CANx->TSTATR & (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1); - break; - - case(CAN_TXMAILBOX_2): - state = CANx->TSTATR & (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2); - break; - - default: - state = CAN_TxStatus_Failed; - break; - } - - switch(state) - { - case(0x0): - state = CAN_TxStatus_Pending; - break; - - case(CAN_TSTATR_RQCP0 | CAN_TSTATR_TME0): - state = CAN_TxStatus_Failed; - break; - - case(CAN_TSTATR_RQCP1 | CAN_TSTATR_TME1): - state = CAN_TxStatus_Failed; - break; - - case(CAN_TSTATR_RQCP2 | CAN_TSTATR_TME2): - state = CAN_TxStatus_Failed; - break; - - case(CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0): - state = CAN_TxStatus_Ok; - break; - - case(CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1): - state = CAN_TxStatus_Ok; - break; - - case(CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2): - state = CAN_TxStatus_Ok; - break; - - default: - state = CAN_TxStatus_Failed; - break; - } - - return (uint8_t)state; -} - -/********************************************************************* - * @fn CAN_CancelTransmit - * - * @brief Cancels a transmit request. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * Mailbox - Mailbox number. - * CAN_TXMAILBOX_0. - * CAN_TXMAILBOX_1. - * CAN_TXMAILBOX_2. - * - * @return none - */ -void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox) -{ - switch(Mailbox) - { - case(CAN_TXMAILBOX_0): - CANx->TSTATR |= CAN_TSTATR_ABRQ0; - break; - - case(CAN_TXMAILBOX_1): - CANx->TSTATR |= CAN_TSTATR_ABRQ1; - break; - - case(CAN_TXMAILBOX_2): - CANx->TSTATR |= CAN_TSTATR_ABRQ2; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn CAN_Receive - * - * @brief Receives a message. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * FIFONumber - Receive FIFO number. - * CAN_FIFO0. - * CAN_FIFO1. - * RxMessage - pointer to a structure receive message which contains - * CAN Id, CAN DLC, CAN datas and FMI number. - * - * @return none - */ -void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage) -{ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; - - if(RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 24); - - if(FIFONumber == CAN_FIFO0) - { - CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; - } - else - { - CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; - } -} - -/********************************************************************* - * @fn CAN_FIFORelease - * - * @brief Releases the specified FIFO. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * FIFONumber - Receive FIFO number. - * CAN_FIFO0. - * CAN_FIFO1. - * - * @return none - */ -void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber) -{ - if(FIFONumber == CAN_FIFO0) - { - CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; - } - else - { - CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; - } -} - -/********************************************************************* - * @fn CAN_MessagePending - * - * @brief Returns the number of pending messages. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * FIFONumber - Receive FIFO number. - * CAN_FIFO0. - * CAN_FIFO1. - * - * @return message_pending: which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber) -{ - uint8_t message_pending = 0; - - if(FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RFIFO0 & (uint32_t)0x03); - } - else if(FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RFIFO1 & (uint32_t)0x03); - } - else - { - message_pending = 0; - } - - return message_pending; -} - -/********************************************************************* - * @fn CAN_OperatingModeRequest - * - * @brief Select the CAN Operation mode. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_OperatingMode - CAN Operating Mode. - * CAN_OperatingMode_Initialization. - * CAN_OperatingMode_Normal. - * CAN_OperatingMode_Sleep. - * - * @return status - - * CAN_ModeStatus_Failed - CAN failed entering the specific mode. - * CAN_ModeStatus_Success - CAN Succeed entering the specific mode. - */ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode) -{ - uint8_t status = CAN_ModeStatus_Failed; - uint32_t timeout = INAK_TIMEOUT; - - if(CAN_OperatingMode == CAN_OperatingMode_Initialization) - { - CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SLEEP)) | CAN_CTLR_INRQ); - - while(((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) && (timeout != 0)) - { - timeout--; - } - if((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if(CAN_OperatingMode == CAN_OperatingMode_Normal) - { - CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SLEEP | CAN_CTLR_INRQ)); - - while(((CANx->STATR & CAN_MODE_MASK) != 0) && (timeout != 0)) - { - timeout--; - } - if((CANx->STATR & CAN_MODE_MASK) != 0) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if(CAN_OperatingMode == CAN_OperatingMode_Sleep) - { - CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); - - while(((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) && (timeout != 0)) - { - timeout--; - } - if((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else - { - status = CAN_ModeStatus_Failed; - } - - return (uint8_t)status; -} - -/********************************************************************* - * @fn CAN_Sleep - * - * @brief Enters the low power mode. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return sleepstatus - - * CAN_Sleep_Ok. - * CAN_Sleep_Failed. - */ -uint8_t CAN_Sleep(CAN_TypeDef *CANx) -{ - uint8_t sleepstatus = CAN_Sleep_Failed; - - CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); - - if((CANx->STATR & (CAN_STATR_SLAK | CAN_STATR_INAK)) == CAN_STATR_SLAK) - { - sleepstatus = CAN_Sleep_Ok; - } - - return (uint8_t)sleepstatus; -} - -/********************************************************************* - * @fn CAN_WakeUp - * - * @brief Wakes the CAN up. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return wakeupstatus - - * CAN_WakeUp_Ok. - * CAN_WakeUp_Failed. - */ -uint8_t CAN_WakeUp(CAN_TypeDef *CANx) -{ - uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CAN_WakeUp_Failed; - - CANx->CTLR &= ~(uint32_t)CAN_CTLR_SLEEP; - - while(((CANx->STATR & CAN_STATR_SLAK) == CAN_STATR_SLAK) && (wait_slak != 0x00)) - { - wait_slak--; - } - if((CANx->STATR & CAN_STATR_SLAK) != CAN_STATR_SLAK) - { - wakeupstatus = CAN_WakeUp_Ok; - } - - return (uint8_t)wakeupstatus; -} - -/********************************************************************* - * @fn CAN_GetLastErrorCode - * - * @brief Returns the CANx's last error code (LEC). - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return errorcode - specifies the Error code. - * CAN_ErrorCode_NoErr - No Error. - * CAN_ErrorCode_StuffErr - Stuff Error. - * CAN_ErrorCode_FormErr - Form Error. - * CAN_ErrorCode_ACKErr - Acknowledgment Error. - * CAN_ErrorCode_BitRecessiveErr - Bit Recessive Error. - * CAN_ErrorCode_BitDominantErr - Bit Dominant Error. - * CAN_ErrorCode_CRCErr - CRC Error. - * CAN_ErrorCode_SoftwareSetErr - Software Set Error. - */ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx) -{ - uint8_t errorcode = 0; - - errorcode = (((uint8_t)CANx->ERRSR) & (uint8_t)CAN_ERRSR_LEC); - - return errorcode; -} - -/********************************************************************* - * @fn CAN_GetReceiveErrorCounter - * - * @brief Returns the CANx Receive Error Counter (REC). - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * Note- - * In case of an error during reception, this counter is incremented - * by 1 or by 8 depending on the error condition as defined by the CAN - * standard. After every successful reception, the counter is - * decremented by 1 or reset to 120 if its value was higher than 128. - * When the counter value exceeds 127, the CAN controller enters the - * error passive state. - * @return counter - CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx) -{ - uint8_t counter = 0; - - counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_REC) >> 24); - - return counter; -} - -/********************************************************************* - * @fn CAN_GetLSBTransmitErrorCounter - * - * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * - * @return counter - LSB of the 9-bit CAN Transmit Error Counter. - */ -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx) -{ - uint8_t counter = 0; - - counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_TEC) >> 16); - - return counter; -} - -/********************************************************************* - * @fn CAN_ITConfig - * - * @brief Enables or disables the specified CANx interrupts. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_IT - specifies the CAN interrupt sources to be enabled or disabled. - * CAN_IT_TME. - * CAN_IT_FMP0. - * CAN_IT_FF0. - * CAN_IT_FOV0. - * CAN_IT_FMP1. - * CAN_IT_FF1. - * CAN_IT_FOV1. - * CAN_IT_EWG. - * CAN_IT_EPV. - * CAN_IT_LEC. - * CAN_IT_ERR. - * CAN_IT_WKU. - * CAN_IT_SLK. - * NewState - ENABLE or DISABLE. - * - * @return counter - LSB of the 9-bit CAN Transmit Error Counter. - */ -void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - CANx->INTENR |= CAN_IT; - } - else - { - CANx->INTENR &= ~CAN_IT; - } -} - -/********************************************************************* - * @fn CAN_GetFlagStatus - * - * @brief Checks whether the specified CAN flag is set or not. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_FLAG - specifies the flag to check. - * CAN_FLAG_EWG. - * CAN_FLAG_EPV. - * CAN_FLAG_BOF. - * CAN_FLAG_RQCP0. - * CAN_FLAG_RQCP1. - * CAN_FLAG_RQCP2. - * CAN_FLAG_FMP1. - * CAN_FLAG_FF1. - * CAN_FLAG_FOV1. - * CAN_FLAG_FMP0. - * CAN_FLAG_FF0. - * CAN_FLAG_FOV0. - * CAN_FLAG_WKU. - * CAN_FLAG_SLAK. - * CAN_FLAG_LEC. - * NewState - ENABLE or DISABLE. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((CAN_FLAG & CAN_FLAGS_ERRSR) != (uint32_t)RESET) - { - if((CANx->ERRSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_STATR) != (uint32_t)RESET) - { - if((CANx->STATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) - { - if((CANx->TSTATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) - { - if((CANx->RFIFO0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((uint32_t)(CANx->RFIFO1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - - return bitstatus; -} - -/********************************************************************* - * @fn CAN_ClearFlag - * - * @brief Clears the CAN's pending flags. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_FLAG - specifies the flag to clear. - * CAN_FLAG_RQCP0. - * CAN_FLAG_RQCP1. - * CAN_FLAG_RQCP2. - * CAN_FLAG_FF1. - * CAN_FLAG_FOV1. - * CAN_FLAG_FF0. - * CAN_FLAG_FOV0. - * CAN_FLAG_WKU. - * CAN_FLAG_SLAK. - * CAN_FLAG_LEC. - * - * @return none - */ -void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG) -{ - uint32_t flagtmp = 0; - - if(CAN_FLAG == CAN_FLAG_LEC) - { - CANx->ERRSR = (uint32_t)RESET; - } - else - { - flagtmp = CAN_FLAG & 0x000FFFFF; - - if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) - { - CANx->RFIFO0 = (uint32_t)(flagtmp); - } - else if((CAN_FLAG & CAN_FLAGS_RFIFO1) != (uint32_t)RESET) - { - CANx->RFIFO1 = (uint32_t)(flagtmp); - } - else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) - { - CANx->TSTATR = (uint32_t)(flagtmp); - } - else - { - CANx->STATR = (uint32_t)(flagtmp); - } - } -} - -/********************************************************************* - * @fn CAN_GetITStatus - * - * @brief Checks whether the specified CANx interrupt has occurred or not. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_IT - specifies the CAN interrupt source to check. - * CAN_IT_TME. - * CAN_IT_FMP0. - * CAN_IT_FF0. - * CAN_IT_FOV0. - * CAN_IT_FMP1. - * CAN_IT_FF1. - * CAN_IT_FOV1. - * CAN_IT_WKU. - * CAN_IT_SLK. - * CAN_IT_EWG. - * CAN_IT_EPV. - * CAN_IT_BOF. - * CAN_IT_LEC. - * CAN_IT_ERR. - * - * @return ITStatus - SET or RESET. - */ -ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT) -{ - ITStatus itstatus = RESET; - - if((CANx->INTENR & CAN_IT) != RESET) - { - switch(CAN_IT) - { - case CAN_IT_TME: - itstatus = CheckITStatus(CANx->TSTATR, CAN_TSTATR_RQCP0 | CAN_TSTATR_RQCP1 | CAN_TSTATR_RQCP2); - break; - - case CAN_IT_FMP0: - itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FMP0); - break; - - case CAN_IT_FF0: - itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FULL0); - break; - - case CAN_IT_FOV0: - itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FOVR0); - break; - - case CAN_IT_FMP1: - itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FMP1); - break; - - case CAN_IT_FF1: - itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FULL1); - break; - - case CAN_IT_FOV1: - itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FOVR1); - break; - - case CAN_IT_WKU: - itstatus = CheckITStatus(CANx->STATR, CAN_STATR_WKUI); - break; - - case CAN_IT_SLK: - itstatus = CheckITStatus(CANx->STATR, CAN_STATR_SLAKI); - break; - - case CAN_IT_EWG: - itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EWGF); - break; - - case CAN_IT_EPV: - itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EPVF); - break; - - case CAN_IT_BOF: - itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_BOFF); - break; - - case CAN_IT_LEC: - itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_LEC); - break; - - case CAN_IT_ERR: - itstatus = CheckITStatus(CANx->STATR, CAN_STATR_ERRI); - break; - - default: - itstatus = RESET; - break; - } - } - else - { - itstatus = RESET; - } - - return itstatus; -} - -/********************************************************************* - * @fn CAN_ClearITPendingBit - * - * @brief Clears the CANx's interrupt pending bits. - * - * @param CANx - where x can be 1 to select the CAN peripheral. - * CAN_IT - specifies the interrupt pending bit to clear. - * CAN_IT_TME. - * CAN_IT_FF0. - * CAN_IT_FOV0. - * CAN_IT_FF1. - * CAN_IT_FOV1. - * CAN_IT_WKU. - * CAN_IT_SLK. - * CAN_IT_EWG. - * CAN_IT_EPV. - * CAN_IT_BOF. - * CAN_IT_LEC. - * CAN_IT_ERR. - * - * @return none - */ -void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT) -{ - switch(CAN_IT) - { - case CAN_IT_TME: - CANx->TSTATR = CAN_TSTATR_RQCP0 | CAN_TSTATR_RQCP1 | CAN_TSTATR_RQCP2; - break; - - case CAN_IT_FF0: - CANx->RFIFO0 = CAN_RFIFO0_FULL0; - break; - - case CAN_IT_FOV0: - CANx->RFIFO0 = CAN_RFIFO0_FOVR0; - break; - - case CAN_IT_FF1: - CANx->RFIFO1 = CAN_RFIFO1_FULL1; - break; - - case CAN_IT_FOV1: - CANx->RFIFO1 = CAN_RFIFO1_FOVR1; - break; - - case CAN_IT_WKU: - CANx->STATR = CAN_STATR_WKUI; - break; - - case CAN_IT_SLK: - CANx->STATR = CAN_STATR_SLAKI; - break; - - case CAN_IT_EWG: - CANx->STATR = CAN_STATR_ERRI; - break; - - case CAN_IT_EPV: - CANx->STATR = CAN_STATR_ERRI; - break; - - case CAN_IT_BOF: - CANx->STATR = CAN_STATR_ERRI; - break; - - case CAN_IT_LEC: - CANx->ERRSR = RESET; - CANx->STATR = CAN_STATR_ERRI; - break; - - case CAN_IT_ERR: - CANx->ERRSR = RESET; - CANx->STATR = CAN_STATR_ERRI; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn CheckITStatus - * - * @brief Checks whether the CAN interrupt has occurred or not. - * - * @param CAN_Reg - specifies the CAN interrupt register to check - * It_Bit - specifies the interrupt source bit to check. - * - * @return ITStatus - SET or RESET. - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - pendingbitstatus = SET; - } - else - { - pendingbitstatus = RESET; - } - - return pendingbitstatus; -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_can.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the CAN firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_can.h" +#include "ch32v30x_rcc.h" + +/* CAN CTLR Register bits */ +#define CTLR_DBF ((uint32_t)0x00010000) + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) + +/* CAN FCTLR Register bits */ +#define FCTLR_FINIT ((uint32_t)0x00000001) + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + +/* Flags in TSTATR register */ +#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) +/* Flags in RFIFO1 register */ +#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) +/* Flags in RFIFO0 register */ +#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) +/* Flags in STATR register */ +#define CAN_FLAGS_STATR ((uint32_t)0x01000000) +/* Flags in ERRSR register */ +#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +#define CAN_MODE_MASK ((uint32_t)0x00000003) + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/********************************************************************* + * @fn CAN_DeInit + * + * @brief Deinitializes the CAN peripheral registers to their default reset + * values. + * + * @param CANx - where x can be 1 or 2 to select the CAN peripheral. + * + * @return none + */ +void CAN_DeInit(CAN_TypeDef *CANx) +{ + if(CANx == CAN1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/********************************************************************* + * @fn CAN_Init + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_InitStruct - pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * + * @return InitStatus - CAN InitStatus state. + * CAN_InitStatus_Failed. + * CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + + CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); + CANx->CTLR |= CAN_CTLR_INRQ; + + while(((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + if(CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; + } + + if(CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_ABOM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; + } + + if(CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_AWUM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; + } + + if(CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->CTLR |= CAN_CTLR_NART; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; + } + + if(CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_RFLM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFLM; + } + + if(CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TXFP; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; + } + + CANx->BTIMR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; + wait_ack = 0; + + while(((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success; + } + } + + return InitStatus; +} + +/********************************************************************* + * @fn CAN_FilterInit + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * + * @param CAN_FilterInitStruct - pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration information. + * + * @return none + */ +void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FWR &= ~(uint32_t)filter_number_bit_pos; + + if(CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + CAN1->FSCFGR &= ~(uint32_t)filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if(CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + CAN1->FSCFGR |= filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + if(CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos; + } + else + { + CAN1->FMCFGR |= (uint32_t)filter_number_bit_pos; + } + + if(CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + CAN1->FAFIFOR &= ~(uint32_t)filter_number_bit_pos; + } + + if(CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + CAN1->FAFIFOR |= (uint32_t)filter_number_bit_pos; + } + + if(CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FWR |= filter_number_bit_pos; + } + + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_StructInit + * + * @brief Fills each CAN_InitStruct member with its default value. + * + * @param CAN_InitStruct - pointer to a CAN_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct) +{ + CAN_InitStruct->CAN_TTCM = DISABLE; + CAN_InitStruct->CAN_ABOM = DISABLE; + CAN_InitStruct->CAN_AWUM = DISABLE; + CAN_InitStruct->CAN_NART = DISABLE; + CAN_InitStruct->CAN_RFLM = DISABLE; + CAN_InitStruct->CAN_TXFP = DISABLE; + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + CAN_InitStruct->CAN_Prescaler = 1; +} + +/********************************************************************* + * @fn CAN_SlaveStartBank + * + * @brief This function applies only to CH32 Connectivity line devices. + * + * @param CAN_BankNumber - Select the start slave bank filter from 1..27. + * + * @return none + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FCTLR &= (uint32_t)0xFFFFC0F1; + CAN1->FCTLR |= (uint32_t)(CAN_BankNumber) << 8; + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_DBGFreeze + * + * @brief Enables or disables the DBG Freeze for CAN. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + CANx->CTLR |= CTLR_DBF; + } + else + { + CANx->CTLR &= ~CTLR_DBF; + } +} + +/********************************************************************* + * @fn CAN_TTComModeCmd + * + * @brief Enables or disabes the CAN Time TriggerOperation communication mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * Note- + * DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * + * @return none + */ +void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + + CANx->sTxMailBox[0].TXMDTR |= ((uint32_t)CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR |= ((uint32_t)CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR |= ((uint32_t)CAN_TXMDT2R_TGT); + } + else + { + CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTCM); + + CANx->sTxMailBox[0].TXMDTR &= ((uint32_t)~CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR &= ((uint32_t)~CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR &= ((uint32_t)~CAN_TXMDT2R_TGT); + } +} + +/********************************************************************* + * @fn CAN_Transmit + * + * @brief Initiates the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TxMessage - pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * + * @return transmit_mailbox - The number of the mailbox that is used for + * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage) +{ + uint8_t transmit_mailbox = 0; + + if((CANx->TSTATR & CAN_TSTATR_TME0) == CAN_TSTATR_TME0) + { + transmit_mailbox = 0; + } + else if((CANx->TSTATR & CAN_TSTATR_TME1) == CAN_TSTATR_TME1) + { + transmit_mailbox = 1; + } + else if((CANx->TSTATR & CAN_TSTATR_TME2) == CAN_TSTATR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if(transmit_mailbox != CAN_TxStatus_NoMailBox) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; + if(TxMessage->IDE == CAN_Id_Standard) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | + TxMessage->RTR); + } + else + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | + TxMessage->IDE | + TxMessage->RTR); + } + + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; + + CANx->sTxMailBox[transmit_mailbox].TXMDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TXMDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; + } + + return transmit_mailbox; +} + +/********************************************************************* + * @fn CAN_TransmitStatus + * + * @brief Checks the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TransmitMailbox - the number of the mailbox that is used for + * transmission. + * + * @return state - + * CAN_TxStatus_Ok. + * CAN_TxStatus_Failed. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + switch(TransmitMailbox) + { + case(CAN_TXMAILBOX_0): + state = CANx->TSTATR & (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0); + break; + + case(CAN_TXMAILBOX_1): + state = CANx->TSTATR & (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1); + break; + + case(CAN_TXMAILBOX_2): + state = CANx->TSTATR & (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2); + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + switch(state) + { + case(0x0): + state = CAN_TxStatus_Pending; + break; + + case(CAN_TSTATR_RQCP0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Failed; + break; + + case(CAN_TSTATR_RQCP1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Failed; + break; + + case(CAN_TSTATR_RQCP2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Failed; + break; + + case(CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Ok; + break; + + case(CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Ok; + break; + + case(CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Ok; + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + return (uint8_t)state; +} + +/********************************************************************* + * @fn CAN_CancelTransmit + * + * @brief Cancels a transmit request. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Mailbox - Mailbox number. + * CAN_TXMAILBOX_0. + * CAN_TXMAILBOX_1. + * CAN_TXMAILBOX_2. + * + * @return none + */ +void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox) +{ + switch(Mailbox) + { + case(CAN_TXMAILBOX_0): + CANx->TSTATR |= CAN_TSTATR_ABRQ0; + break; + + case(CAN_TXMAILBOX_1): + CANx->TSTATR |= CAN_TSTATR_ABRQ1; + break; + + case(CAN_TXMAILBOX_2): + CANx->TSTATR |= CAN_TSTATR_ABRQ2; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn CAN_Receive + * + * @brief Receives a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * RxMessage - pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * + * @return none + */ +void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage) +{ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + if(RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 24); + + if(FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_FIFORelease + * + * @brief Releases the specified FIFO. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return none + */ +void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber) +{ + if(FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_MessagePending + * + * @brief Returns the number of pending messages. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return message_pending: which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber) +{ + uint8_t message_pending = 0; + + if(FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RFIFO0 & (uint32_t)0x03); + } + else if(FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RFIFO1 & (uint32_t)0x03); + } + else + { + message_pending = 0; + } + + return message_pending; +} + +/********************************************************************* + * @fn CAN_OperatingModeRequest + * + * @brief Select the CAN Operation mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_OperatingMode - CAN Operating Mode. + * CAN_OperatingMode_Initialization. + * CAN_OperatingMode_Normal. + * CAN_OperatingMode_Sleep. + * + * @return status - + * CAN_ModeStatus_Failed - CAN failed entering the specific mode. + * CAN_ModeStatus_Success - CAN Succeed entering the specific mode. + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + uint32_t timeout = INAK_TIMEOUT; + + if(CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SLEEP)) | CAN_CTLR_INRQ); + + while(((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) && (timeout != 0)) + { + timeout--; + } + if((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if(CAN_OperatingMode == CAN_OperatingMode_Normal) + { + CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SLEEP | CAN_CTLR_INRQ)); + + while(((CANx->STATR & CAN_MODE_MASK) != 0) && (timeout != 0)) + { + timeout--; + } + if((CANx->STATR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if(CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + while(((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) && (timeout != 0)) + { + timeout--; + } + if((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t)status; +} + +/********************************************************************* + * @fn CAN_Sleep + * + * @brief Enters the low power mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return sleepstatus - + * CAN_Sleep_Ok. + * CAN_Sleep_Failed. + */ +uint8_t CAN_Sleep(CAN_TypeDef *CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + if((CANx->STATR & (CAN_STATR_SLAK | CAN_STATR_INAK)) == CAN_STATR_SLAK) + { + sleepstatus = CAN_Sleep_Ok; + } + + return (uint8_t)sleepstatus; +} + +/********************************************************************* + * @fn CAN_WakeUp + * + * @brief Wakes the CAN up. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return wakeupstatus - + * CAN_WakeUp_Ok. + * CAN_WakeUp_Failed. + */ +uint8_t CAN_WakeUp(CAN_TypeDef *CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + CANx->CTLR &= ~(uint32_t)CAN_CTLR_SLEEP; + + while(((CANx->STATR & CAN_STATR_SLAK) == CAN_STATR_SLAK) && (wait_slak != 0x00)) + { + wait_slak--; + } + if((CANx->STATR & CAN_STATR_SLAK) != CAN_STATR_SLAK) + { + wakeupstatus = CAN_WakeUp_Ok; + } + + return (uint8_t)wakeupstatus; +} + +/********************************************************************* + * @fn CAN_GetLastErrorCode + * + * @brief Returns the CANx's last error code (LEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return errorcode - specifies the Error code. + * CAN_ErrorCode_NoErr - No Error. + * CAN_ErrorCode_StuffErr - Stuff Error. + * CAN_ErrorCode_FormErr - Form Error. + * CAN_ErrorCode_ACKErr - Acknowledgment Error. + * CAN_ErrorCode_BitRecessiveErr - Bit Recessive Error. + * CAN_ErrorCode_BitDominantErr - Bit Dominant Error. + * CAN_ErrorCode_CRCErr - CRC Error. + * CAN_ErrorCode_SoftwareSetErr - Software Set Error. + */ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx) +{ + uint8_t errorcode = 0; + + errorcode = (((uint8_t)CANx->ERRSR) & (uint8_t)CAN_ERRSR_LEC); + + return errorcode; +} + +/********************************************************************* + * @fn CAN_GetReceiveErrorCounter + * + * @brief Returns the CANx Receive Error Counter (REC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Note- + * In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @return counter - CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx) +{ + uint8_t counter = 0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_REC) >> 24); + + return counter; +} + +/********************************************************************* + * @fn CAN_GetLSBTransmitErrorCounter + * + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx) +{ + uint8_t counter = 0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_TEC) >> 16); + + return counter; +} + +/********************************************************************* + * @fn CAN_ITConfig + * + * @brief Enables or disables the specified CANx interrupts. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt sources to be enabled or disabled. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_LEC. + * CAN_IT_ERR. + * CAN_IT_WKU. + * CAN_IT_SLK. + * NewState - ENABLE or DISABLE. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + CANx->INTENR |= CAN_IT; + } + else + { + CANx->INTENR &= ~CAN_IT; + } +} + +/********************************************************************* + * @fn CAN_GetFlagStatus + * + * @brief Checks whether the specified CAN flag is set or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to check. + * CAN_FLAG_EWG. + * CAN_FLAG_EPV. + * CAN_FLAG_BOF. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FMP1. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FMP0. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * NewState - ENABLE or DISABLE. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((CAN_FLAG & CAN_FLAGS_ERRSR) != (uint32_t)RESET) + { + if((CANx->ERRSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_STATR) != (uint32_t)RESET) + { + if((CANx->STATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) + { + if((CANx->TSTATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) + { + if((CANx->RFIFO0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((uint32_t)(CANx->RFIFO1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/********************************************************************* + * @fn CAN_ClearFlag + * + * @brief Clears the CAN's pending flags. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to clear. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * + * @return none + */ +void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp = 0; + + if(CAN_FLAG == CAN_FLAG_LEC) + { + CANx->ERRSR = (uint32_t)RESET; + } + else + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) + { + CANx->RFIFO0 = (uint32_t)(flagtmp); + } + else if((CAN_FLAG & CAN_FLAGS_RFIFO1) != (uint32_t)RESET) + { + CANx->RFIFO1 = (uint32_t)(flagtmp); + } + else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) + { + CANx->TSTATR = (uint32_t)(flagtmp); + } + else + { + CANx->STATR = (uint32_t)(flagtmp); + } + } +} + +/********************************************************************* + * @fn CAN_GetITStatus + * + * @brief Checks whether the specified CANx interrupt has occurred or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt source to check. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return ITStatus - SET or RESET. + */ +ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + + if((CANx->INTENR & CAN_IT) != RESET) + { + switch(CAN_IT) + { + case CAN_IT_TME: + itstatus = CheckITStatus(CANx->TSTATR, CAN_TSTATR_RQCP0 | CAN_TSTATR_RQCP1 | CAN_TSTATR_RQCP2); + break; + + case CAN_IT_FMP0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FMP0); + break; + + case CAN_IT_FF0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FULL0); + break; + + case CAN_IT_FOV0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FOVR0); + break; + + case CAN_IT_FMP1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FMP1); + break; + + case CAN_IT_FF1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FULL1); + break; + + case CAN_IT_FOV1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FOVR1); + break; + + case CAN_IT_WKU: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_WKUI); + break; + + case CAN_IT_SLK: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_SLAKI); + break; + + case CAN_IT_EWG: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EWGF); + break; + + case CAN_IT_EPV: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EPVF); + break; + + case CAN_IT_BOF: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_BOFF); + break; + + case CAN_IT_LEC: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_LEC); + break; + + case CAN_IT_ERR: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_ERRI); + break; + + default: + itstatus = RESET; + break; + } + } + else + { + itstatus = RESET; + } + + return itstatus; +} + +/********************************************************************* + * @fn CAN_ClearITPendingBit + * + * @brief Clears the CANx's interrupt pending bits. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the interrupt pending bit to clear. + * CAN_IT_TME. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return none + */ +void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT) +{ + switch(CAN_IT) + { + case CAN_IT_TME: + CANx->TSTATR = CAN_TSTATR_RQCP0 | CAN_TSTATR_RQCP1 | CAN_TSTATR_RQCP2; + break; + + case CAN_IT_FF0: + CANx->RFIFO0 = CAN_RFIFO0_FULL0; + break; + + case CAN_IT_FOV0: + CANx->RFIFO0 = CAN_RFIFO0_FOVR0; + break; + + case CAN_IT_FF1: + CANx->RFIFO1 = CAN_RFIFO1_FULL1; + break; + + case CAN_IT_FOV1: + CANx->RFIFO1 = CAN_RFIFO1_FOVR1; + break; + + case CAN_IT_WKU: + CANx->STATR = CAN_STATR_WKUI; + break; + + case CAN_IT_SLK: + CANx->STATR = CAN_STATR_SLAKI; + break; + + case CAN_IT_EWG: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_EPV: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_BOF: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_LEC: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_ERR: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn CheckITStatus + * + * @brief Checks whether the CAN interrupt has occurred or not. + * + * @param CAN_Reg - specifies the CAN interrupt register to check + * It_Bit - specifies the interrupt source bit to check. + * + * @return ITStatus - SET or RESET. + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + pendingbitstatus = SET; + } + else + { + pendingbitstatus = RESET; + } + + return pendingbitstatus; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_crc.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_crc.c index d44ad21..6cca827 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_crc.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_crc.c @@ -1,100 +1,100 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_crc.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the CRC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_crc.h" - -/********************************************************************* - * @fn CRC_ResetDR - * - * @brief Resets the CRC Data register (DR). - * - * @return none - */ -void CRC_ResetDR(void) -{ - CRC->CTLR = CRC_CTLR_RESET; -} - -/********************************************************************* - * @fn CRC_CalcCRC - * - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * - * @param Data - data word(32-bit) to compute its CRC. - * - * @return 32-bit CRC. - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DATAR = Data; - - return (CRC->DATAR); -} - -/********************************************************************* - * @fn CRC_CalcBlockCRC - * - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * - * @param pBuffer - pointer to the buffer containing the data to be computed. - * BufferLength - length of the buffer to be computed. - * - * @return 32-bit CRC. - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DATAR = pBuffer[index]; - } - - return (CRC->DATAR); -} - -/********************************************************************* - * @fn CRC_GetCRC - * - * @brief Returns the current CRC value. - * - * @return 32-bit CRC. - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DATAR); -} - -/********************************************************************* - * @fn CRC_SetIDRegister - * - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * - * @param IDValue - 8-bit value to be stored in the ID register. - * - * @return none - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDATAR = IDValue; -} - -/********************************************************************* - * @fn CRC_GetIDRegister - * - * @brief Returns the 8-bit data stored in the Independent Data(ID) register. - * - * @return 8-bit value of the ID register. - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDATAR); -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_crc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the CRC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_crc.h" + +/********************************************************************* + * @fn CRC_ResetDR + * + * @brief Resets the CRC Data register (DR). + * + * @return none + */ +void CRC_ResetDR(void) +{ + CRC->CTLR = CRC_CTLR_RESET; +} + +/********************************************************************* + * @fn CRC_CalcCRC + * + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * + * @param Data - data word(32-bit) to compute its CRC. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DATAR = Data; + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_CalcBlockCRC + * + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * + * @param pBuffer - pointer to the buffer containing the data to be computed. + * BufferLength - length of the buffer to be computed. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DATAR = pBuffer[index]; + } + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_GetCRC + * + * @brief Returns the current CRC value. + * + * @return 32-bit CRC. + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_SetIDRegister + * + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * + * @param IDValue - 8-bit value to be stored in the ID register. + * + * @return none + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDATAR = IDValue; +} + +/********************************************************************* + * @fn CRC_GetIDRegister + * + * @brief Returns the 8-bit data stored in the Independent Data(ID) register. + * + * @return 8-bit value of the ID register. + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDATAR); +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dac.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dac.c index 529ece7..8e47de9 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dac.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dac.c @@ -1,304 +1,304 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_dac.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the DAC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_dac.h" -#include "ch32v30x_rcc.h" - -/* CTLR register Mask */ -#define CTLR_CLEAR_MASK ((uint32_t)0x00000FFE) - -/* DAC Dual Channels SWTR masks */ -#define DUAL_SWTR_SET ((uint32_t)0x00000003) -#define DUAL_SWTR_RESET ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) - -/********************************************************************* - * @fn DAC_DeInit - * - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * - * @return none - */ -void DAC_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/********************************************************************* - * @fn DAC_Init - * - * @brief Initializes the DAC peripheral according to the specified parameters in - * the DAC_InitStruct. - * - * @param DAC_Channel - the selected DAC channel. - * DAC_Channel_1 - DAC Channel1 selected - * DAC_Channel_2 - DAC Channel2 selected - * DAC_InitStruct - pointer to a DAC_InitTypeDef structure. - * - * @return none - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - tmpreg1 = DAC->CTLR; - tmpreg1 &= ~(CTLR_CLEAR_MASK << DAC_Channel); - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); - tmpreg1 |= tmpreg2 << DAC_Channel; - DAC->CTLR = tmpreg1; -} - -/********************************************************************* - * @fn DAC_StructInit - * - * @brief Fills each DAC_InitStruct member with its default value. - * - * @param DAC_InitStruct - pointer to a DAC_InitTypeDef structure which will be initialized. - * - * @return none - */ -void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct) -{ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/********************************************************************* - * @fn DAC_Cmd - * - * @brief Enables or disables the specified DAC channel. - * - * @param DAC_Channel - the selected DAC channel. - * DAC_Channel_1 - DAC Channel1 selected - * DAC_Channel_2 - DAC Channel2 selected - * NewState - new state of the DAC channel(ENABLE or DISABLE). - * - * @return none - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DAC->CTLR |= (DAC_EN1 << DAC_Channel); - } - else - { - DAC->CTLR &= ~(DAC_EN1 << DAC_Channel); - } -} - -/********************************************************************* - * @fn DAC_DMACmd - * - * @brief Enables or disables the specified DAC channel DMA request. - * - * @param DAC_Channel - the selected DAC channel. - * DAC_Channel_1 - DAC Channel1 selected - * DAC_Channel_2 - DAC Channel2 selected - * NewState - new state of the DAC channel(ENABLE or DISABLE). - * - * @return none - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DAC->CTLR |= (DAC_DMAEN1 << DAC_Channel); - } - else - { - DAC->CTLR &= ~(DAC_DMAEN1 << DAC_Channel); - } -} - -/********************************************************************* - * @fn DAC_SoftwareTriggerCmd - * - * @brief Enables or disables the selected DAC channel software trigger. - * - * @param DAC_Channel - the selected DAC channel. - * DAC_Channel_1 - DAC Channel1 selected - * DAC_Channel_2 - DAC Channel2 selected - * NewState - new state of the DAC channel(ENABLE or DISABLE). - * - * @return none - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DAC->SWTR |= (uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - DAC->SWTR &= ~((uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/********************************************************************* - * @fn DAC_DualSoftwareTriggerCmd - * - * @brief Enables or disables the two DAC channel software trigger. - * - * @param NewState - new state of the DAC channel(ENABLE or DISABLE). - * - * @return none - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DAC->SWTR |= DUAL_SWTR_SET; - } - else - { - DAC->SWTR &= DUAL_SWTR_RESET; - } -} - -/********************************************************************* - * @fn DAC_WaveGenerationCmd - * - * @brief Enables or disables the selected DAC channel wave generation. - * - * @param DAC_Channel - the selected DAC channel. - * DAC_Channel_1 - DAC Channel1 selected - * DAC_Channel_2 - DAC Channel2 selected - * DAC_Wave - Specifies the wave type to enable or disable. - * DAC_Wave_Noise - noise wave generation - * DAC_Wave_Triangle - triangle wave generation - * NewState - new state of the DAC channel(ENABLE or DISABLE). - * - * @return none - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DAC->CTLR |= DAC_Wave << DAC_Channel; - } - else - { - DAC->CTLR &= ~(DAC_Wave << DAC_Channel); - } -} - -/********************************************************************* - * @fn DAC_SetChannel1Data - * - * @brief Set the specified data holding register value for DAC channel1. - * - * @param DAC_Align - Specifies the data alignment for DAC channel1. - * DAC_Align_8b_R - 8bit right data alignment selected - * DAC_Align_12b_L - 12bit left data alignment selected - * DAC_Align_12b_R - 12bit right data alignment selected - * Data - Data to be loaded in the selected data holding register. - * - * @return none - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_OFFSET + DAC_Align; - - *(__IO uint32_t *)tmp = Data; -} - -/********************************************************************* - * @fn DAC_SetChannel2Data - * - * @brief Set the specified data holding register value for DAC channel2. - * - * @param DAC_Align - Specifies the data alignment for DAC channel1. - * DAC_Align_8b_R - 8bit right data alignment selected - * DAC_Align_12b_L - 12bit left data alignment selected - * DAC_Align_12b_R - 12bit right data alignment selected - * Data - Data to be loaded in the selected data holding register. - * - * @return none - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_OFFSET + DAC_Align; - - *(__IO uint32_t *)tmp = Data; -} - -/********************************************************************* - * @fn DAC_SetDualChannelData - * - * @brief Set the specified data holding register value for two DAC. - * - * @param DAC_Align - Specifies the data alignment for DAC channel1. - * DAC_Align_8b_R - 8bit right data alignment selected - * DAC_Align_12b_L - 12bit left data alignment selected - * DAC_Align_12b_R - 12bit right data alignment selected - * Data - Data to be loaded in the selected data holding register. - * Data1 - Data for DAC Channel1. - * Data2 - Data for DAC Channel2 - * - * @return none - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - if(DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_OFFSET + DAC_Align; - - *(__IO uint32_t *)tmp = data; -} - -/********************************************************************* - * @fn DAC_GetDataOutputValue - * - * @brief Returns the last data output value of the selected DAC channel. - * - * @param DAC_Channel - the selected DAC channel. - * DAC_Channel_1 - DAC Channel1 selected - * DAC_Channel_2 - DAC Channel2 selected - * - * @return none - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)DAC_BASE; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - return (uint16_t)(*(__IO uint32_t *)tmp); -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dac.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DAC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_dac.h" +#include "ch32v30x_rcc.h" + +/* CTLR register Mask */ +#define CTLR_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTR masks */ +#define DUAL_SWTR_SET ((uint32_t)0x00000003) +#define DUAL_SWTR_RESET ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) +#define DHR12RD_OFFSET ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) + +/********************************************************************* + * @fn DAC_DeInit + * + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * + * @return none + */ +void DAC_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/********************************************************************* + * @fn DAC_Init + * + * @brief Initializes the DAC peripheral according to the specified parameters in + * the DAC_InitStruct. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * DAC_InitStruct - pointer to a DAC_InitTypeDef structure. + * + * @return none + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + tmpreg1 = DAC->CTLR; + tmpreg1 &= ~(CTLR_CLEAR_MASK << DAC_Channel); + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); + tmpreg1 |= tmpreg2 << DAC_Channel; + DAC->CTLR = tmpreg1; +} + +/********************************************************************* + * @fn DAC_StructInit + * + * @brief Fills each DAC_InitStruct member with its default value. + * + * @param DAC_InitStruct - pointer to a DAC_InitTypeDef structure which will be initialized. + * + * @return none + */ +void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct) +{ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/********************************************************************* + * @fn DAC_Cmd + * + * @brief Enables or disables the specified DAC channel. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->CTLR |= (DAC_EN1 << DAC_Channel); + } + else + { + DAC->CTLR &= ~(DAC_EN1 << DAC_Channel); + } +} + +/********************************************************************* + * @fn DAC_DMACmd + * + * @brief Enables or disables the specified DAC channel DMA request. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->CTLR |= (DAC_DMAEN1 << DAC_Channel); + } + else + { + DAC->CTLR &= ~(DAC_DMAEN1 << DAC_Channel); + } +} + +/********************************************************************* + * @fn DAC_SoftwareTriggerCmd + * + * @brief Enables or disables the selected DAC channel software trigger. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->SWTR |= (uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + DAC->SWTR &= ~((uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/********************************************************************* + * @fn DAC_DualSoftwareTriggerCmd + * + * @brief Enables or disables the two DAC channel software trigger. + * + * @param NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->SWTR |= DUAL_SWTR_SET; + } + else + { + DAC->SWTR &= DUAL_SWTR_RESET; + } +} + +/********************************************************************* + * @fn DAC_WaveGenerationCmd + * + * @brief Enables or disables the selected DAC channel wave generation. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * DAC_Wave - Specifies the wave type to enable or disable. + * DAC_Wave_Noise - noise wave generation + * DAC_Wave_Triangle - triangle wave generation + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->CTLR |= DAC_Wave << DAC_Channel; + } + else + { + DAC->CTLR &= ~(DAC_Wave << DAC_Channel); + } +} + +/********************************************************************* + * @fn DAC_SetChannel1Data + * + * @brief Set the specified data holding register value for DAC channel1. + * + * @param DAC_Align - Specifies the data alignment for DAC channel1. + * DAC_Align_8b_R - 8bit right data alignment selected + * DAC_Align_12b_L - 12bit left data alignment selected + * DAC_Align_12b_R - 12bit right data alignment selected + * Data - Data to be loaded in the selected data holding register. + * + * @return none + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn DAC_SetChannel2Data + * + * @brief Set the specified data holding register value for DAC channel2. + * + * @param DAC_Align - Specifies the data alignment for DAC channel1. + * DAC_Align_8b_R - 8bit right data alignment selected + * DAC_Align_12b_L - 12bit left data alignment selected + * DAC_Align_12b_R - 12bit right data alignment selected + * Data - Data to be loaded in the selected data holding register. + * + * @return none + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_OFFSET + DAC_Align; + + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn DAC_SetDualChannelData + * + * @brief Set the specified data holding register value for two DAC. + * + * @param DAC_Align - Specifies the data alignment for DAC channel1. + * DAC_Align_8b_R - 8bit right data alignment selected + * DAC_Align_12b_L - 12bit left data alignment selected + * DAC_Align_12b_R - 12bit right data alignment selected + * Data - Data to be loaded in the selected data holding register. + * Data1 - Data for DAC Channel1. + * Data2 - Data for DAC Channel2 + * + * @return none + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + if(DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_OFFSET + DAC_Align; + + *(__IO uint32_t *)tmp = data; +} + +/********************************************************************* + * @fn DAC_GetDataOutputValue + * + * @brief Returns the last data output value of the selected DAC channel. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * + * @return none + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + return (uint16_t)(*(__IO uint32_t *)tmp); +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dbgmcu.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dbgmcu.c index 3c88707..a560eca 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dbgmcu.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dbgmcu.c @@ -1,125 +1,129 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_dbgmcu.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the DBGMCU firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_dbgmcu.h" - -#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) - -/********************************************************************* - * @fn DBGMCU_GetREVID - * - * @brief Returns the device revision identifier. - * - * @return Revision identifier. - */ -uint32_t DBGMCU_GetREVID(void) -{ - return ((*(uint32_t *)0x1FFFF704) >> 16); -} - -/********************************************************************* - * @fn DBGMCU_GetDEVID - * - * @brief Returns the device identifier. - * - * @return Device identifier. - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); -} - -/********************************************************************* - * @fn __get_DEBUG_CR - * - * @brief Return the DEBUGE Control Register - * - * @return DEBUGE Control value - */ -uint32_t __get_DEBUG_CR(void) -{ - uint32_t result; - - __asm volatile("csrr %0,""0x7C0" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_DEBUG_CR - * - * @brief Set the DEBUGE Control Register - * - * @param value - set DEBUGE Control value - * - * @return none - */ -void __set_DEBUG_CR(uint32_t value) -{ - __asm volatile("csrw 0x7C0, %0" : : "r"(value)); -} - - -/********************************************************************* - * @fn DBGMCU_Config - * - * @brief Configures the specified peripheral and low power mode behavior - * when the MCU under Debug mode. - * - * @param DBGMCU_Periph - specifies the peripheral and low power mode. - * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted - * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted - * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted - * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - uint32_t val; - - if(NewState != DISABLE) - { - __set_DEBUG_CR(DBGMCU_Periph); - } - else - { - val = __get_DEBUG_CR(); - val &= ~(uint32_t)DBGMCU_Periph; - __set_DEBUG_CR(val); - } - -} - -/********************************************************************* - * @fn DBGMCU_GetCHIPID - * - * @brief Returns the CHIP identifier. - * - * @return Device identifier. - * ChipID List- - * CH32V303CBT6-0x303305x4 - * CH32V303RBT6-0x303205x4 - * CH32V303RCT6-0x303105x4 - * CH32V303VCT6-0x303005x4 - * CH32V305FBP6-0x305205x8 - * CH32V305RBT6-0x305005x8 - * CH32V305GBU6-0x305B05x8 - * CH32V307WCU6-0x307305x8 - * CH32V307FBP6-0x307205x8 - * CH32V307RCT6-0x307105x8 - * CH32V307VCT6-0x307005x8 - */ -uint32_t DBGMCU_GetCHIPID( void ) -{ - return( *( uint32_t * )0x1FFFF704 ); -} - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dbgmcu.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/28 +* Description : This file provides all the DBGMCU firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_dbgmcu.h" + +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) >> 16); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); +} + +/********************************************************************* + * @fn __get_DEBUG_CR + * + * @brief Return the DEBUGE Control Register + * + * @return DEBUGE Control value + */ +uint32_t __get_DEBUG_CR(void) +{ + uint32_t result; + + __asm volatile("csrr %0,""0x7C0" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_DEBUG_CR + * + * @brief Set the DEBUGE Control Register + * + * @param value - set DEBUGE Control value + * + * @return none + */ +void __set_DEBUG_CR(uint32_t value) +{ + __asm volatile("csrw 0x7C0, %0" : : "r"(value)); +} + + +/********************************************************************* + * @fn DBGMCU_Config + * + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * + * @param DBGMCU_Periph - specifies the peripheral and low power mode. + * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted + * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted + * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted + * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + uint32_t val; + + if(NewState != DISABLE) + { + __set_DEBUG_CR(DBGMCU_Periph); + } + else + { + val = __get_DEBUG_CR(); + val &= ~(uint32_t)DBGMCU_Periph; + __set_DEBUG_CR(val); + } + +} + +/********************************************************************* + * @fn DBGMCU_GetCHIPID + * + * @brief Returns the CHIP identifier. + * + * @return Device identifier. + * ChipID List- + * CH32V303CBT6-0x303305x4 + * CH32V303RBT6-0x303205x4 + * CH32V303RCT6-0x303105x4 + * CH32V303VCT6-0x303005x4 + * CH32V305FBP6-0x305205x8 + * CH32V305RBT6-0x305005x8 + * CH32V305GBU6-0x305B05x8 + * CH32V305CCT6-0x305C05x8 + * CH32V307WCU6-0x307305x8 + * CH32V307FBP6-0x307205x8 + * CH32V307RCT6-0x307105x8 + * CH32V307VCT6-0x307005x8 + * CH32V317VCT6-0x3170B5X8 + * CH32V317WCU6-0x3173B5X8 + * CH32V317TCU6-0x3175B5X8 + */ +uint32_t DBGMCU_GetCHIPID( void ) +{ + return( *( uint32_t * )0x1FFFF704 ); +} + diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dma.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dma.c index 1b5cbe8..d44d08e 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dma.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dma.c @@ -1,692 +1,692 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_dma.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the DMA firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_dma.h" -#include "ch32v30x_rcc.h" - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) -#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) -#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) -#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) -#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) -#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) -#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) - -/* DMA2 Channelx interrupt pending bit masks */ -#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) -#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) -#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) -#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) -#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) -#define DMA2_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) -#define DMA2_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) -#define DMA2_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) -#define DMA2_Channel9_IT_Mask ((uint32_t)(DMA_GIF9 | DMA_TCIF9 | DMA_HTIF9 | DMA_TEIF9)) -#define DMA2_Channel10_IT_Mask ((uint32_t)(DMA_GIF10 | DMA_TCIF10 | DMA_HTIF10 | DMA_TEIF10)) -#define DMA2_Channel11_IT_Mask ((uint32_t)(DMA_GIF11 | DMA_TCIF11 | DMA_HTIF11 | DMA_TEIF11)) - -/* DMA2 FLAG mask */ -#define FLAG_Mask ((uint32_t)0x10000000) -#define DMA2_EXTEN_FLAG_Mask ((uint32_t)0x20000000) - -/* DMA registers Masks */ -#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) - -/********************************************************************* - * @fn DMA_DeInit - * - * @brief Deinitializes the DMAy Channelx registers to their default - * reset values. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * - * @return none - */ -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) -{ - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - DMAy_Channelx->CFGR = 0; - DMAy_Channelx->CNTR = 0; - DMAy_Channelx->PADDR = 0; - DMAy_Channelx->MADDR = 0; - if(DMAy_Channelx == DMA1_Channel1) - { - DMA1->INTFCR |= DMA1_Channel1_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel2) - { - DMA1->INTFCR |= DMA1_Channel2_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel3) - { - DMA1->INTFCR |= DMA1_Channel3_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel4) - { - DMA1->INTFCR |= DMA1_Channel4_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel5) - { - DMA1->INTFCR |= DMA1_Channel5_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel6) - { - DMA1->INTFCR |= DMA1_Channel6_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel7) - { - DMA1->INTFCR |= DMA1_Channel7_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel1) - { - DMA2->INTFCR |= DMA2_Channel1_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel2) - { - DMA2->INTFCR |= DMA2_Channel2_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel3) - { - DMA2->INTFCR |= DMA2_Channel3_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel4) - { - DMA2->INTFCR |= DMA2_Channel4_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel5) - { - DMA2->INTFCR |= DMA2_Channel5_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel6) - { - DMA2->INTFCR |= DMA2_Channel6_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel7) - { - DMA2->INTFCR |= DMA2_Channel7_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel8) - { - DMA2_EXTEN->INTFCR |= DMA2_Channel8_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel9) - { - DMA2_EXTEN->INTFCR |= DMA2_Channel9_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel10) - { - DMA2_EXTEN->INTFCR |= DMA2_Channel10_IT_Mask; - } - else if(DMAy_Channelx == DMA2_Channel11) - { - DMA2_EXTEN->INTFCR |= DMA2_Channel11_IT_Mask; - } -} - -/********************************************************************* - * @fn DMA_Init - * - * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - tmpreg = DMAy_Channelx->CFGR; - tmpreg &= CFGR_CLEAR_Mask; - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - DMAy_Channelx->CFGR = tmpreg; - DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; - DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; - DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/********************************************************************* - * @fn DMA_StructInit - * - * @brief Fills each DMA_InitStruct member with its default value. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) -{ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - DMA_InitStruct->DMA_BufferSize = 0; - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/********************************************************************* - * @fn DMA_Cmd - * - * @brief Enables or disables the specified DMAy Channelx. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_CFGR1_EN; - } - else - { - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - } -} - -/********************************************************************* - * @fn DMA_ITConfig - * - * @brief Enables or disables the specified DMAy Channelx interrupts. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * DMA_IT - specifies the DMA interrupts sources to be enabled - * or disabled. - * DMA_IT_TC - Transfer complete interrupt mask - * DMA_IT_HT - Half transfer interrupt mask - * DMA_IT_TE - Transfer error interrupt mask - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_IT; - } - else - { - DMAy_Channelx->CFGR &= ~DMA_IT; - } -} - -/********************************************************************* - * @fn DMA_SetCurrDataCounter - * - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * DataNumber - The number of data units in the current DMAy Channelx - * transfer. - * - * @return none - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) -{ - DMAy_Channelx->CNTR = DataNumber; -} - -/********************************************************************* - * @fn DMA_GetCurrDataCounter - * - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be - * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. - * - * @return DataNumber - The number of remaining data units in the current - * DMAy Channelx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) -{ - return ((uint16_t)(DMAy_Channelx->CNTR)); -} - -/********************************************************************* - * @fn DMA_GetFlagStatus - * - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. - * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. - * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. - * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. - * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. - * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. - * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. - * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. - * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. - * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. - * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. - * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. - * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. - * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. - * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. - * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. - * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. - * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. - * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. - * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. - * DMA2_FLAG_GL6 - DMA2 Channel6 global flag. - * DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag. - * DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag. - * DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag. - * DMA2_FLAG_GL7 - DMA2 Channel7 global flag. - * DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag. - * DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag. - * DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag. - * DMA2_FLAG_GL8 - DMA2 Channel8 global flag. - * DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag. - * DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag. - * DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag. - * DMA2_FLAG_GL9 - DMA2 Channel9 global flag. - * DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag. - * DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag. - * DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag. - * DMA2_FLAG_GL10 - DMA2 Channel10 global flag. - * DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag. - * DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag. - * DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag. - * DMA2_FLAG_GL11 - DMA2 Channel11 global flag. - * DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag. - * DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag. - * DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag. - * - * @return The new state of DMAy_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask) - { - tmpreg = DMA2->INTFR; - } - else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) - { - tmpreg = DMA2_EXTEN->INTFR; - } - else - { - tmpreg = DMA1->INTFR; - } - - if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearFlag - * - * @brief Clears the DMAy Channelx's pending flags. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. - * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. - * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. - * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. - * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. - * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. - * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. - * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. - * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. - * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. - * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. - * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. - * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. - * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. - * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. - * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. - * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. - * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. - * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. - * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. - * DMA2_FLAG_GL6 - DMA2 Channel6 global flag. - * DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag. - * DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag. - * DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag. - * DMA2_FLAG_GL7 - DMA2 Channel7 global flag. - * DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag. - * DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag. - * DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag. - * DMA2_FLAG_GL8 - DMA2 Channel8 global flag. - * DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag. - * DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag. - * DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag. - * DMA2_FLAG_GL9 - DMA2 Channel9 global flag. - * DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag. - * DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag. - * DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag. - * DMA2_FLAG_GL10 - DMA2 Channel10 global flag. - * DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag. - * DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag. - * DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag. - * DMA2_FLAG_GL11 - DMA2 Channel11 global flag. - * DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag. - * DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag. - * DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag. - * - * @return none - */ -void DMA_ClearFlag(uint32_t DMAy_FLAG) -{ - if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask) - { - DMA2->INTFCR = DMAy_FLAG; - } - else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) - { - DMA2_EXTEN->INTFCR = DMAy_FLAG; - } - else - { - DMA1->INTFCR = DMAy_FLAG; - } -} - -/********************************************************************* - * @fn DMA_GetITStatus - * - * @brief Checks whether the specified DMAy Channelx interrupt has - * occurred or not. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * DMA2_IT_GL1 - DMA2 Channel1 global flag. - * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. - * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. - * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. - * DMA2_IT_GL2 - DMA2 Channel2 global flag. - * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. - * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. - * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. - * DMA2_IT_GL3 - DMA2 Channel3 global flag. - * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. - * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. - * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. - * DMA2_IT_GL4 - DMA2 Channel4 global flag. - * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. - * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. - * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. - * DMA2_IT_GL5 - DMA2 Channel5 global flag. - * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. - * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. - * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. - * DMA2_IT_GL6 - DMA2 Channel6 global flag. - * DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag. - * DMA2_IT_HT6 - DMA2 Channel6 half transfer flag. - * DMA2_IT_TE6 - DMA2 Channel6 transfer error flag. - * DMA2_IT_GL7 - DMA2 Channel7 global flag. - * DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag. - * DMA2_IT_HT7 - DMA2 Channel7 half transfer flag. - * DMA2_IT_TE7 - DMA2 Channel7 transfer error flag. - * DMA2_IT_GL8 - DMA2 Channel8 global flag. - * DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag. - * DMA2_IT_HT8 - DMA2 Channel8 half transfer flag. - * DMA2_IT_TE8 - DMA2 Channel8 transfer error flag. - * DMA2_IT_GL9 - DMA2 Channel9 global flag. - * DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag. - * DMA2_IT_HT9 - DMA2 Channel9 half transfer flag. - * DMA2_IT_TE9 - DMA2 Channel9 transfer error flag. - * DMA2_IT_GL10 - DMA2 Channel10 global flag. - * DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag. - * DMA2_IT_HT10 - DMA2 Channel10 half transfer flag. - * DMA2_IT_TE10 - DMA2 Channel10 transfer error flag. - * DMA2_IT_GL11 - DMA2 Channel11 global flag. - * DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag. - * DMA2_IT_HT11 - DMA2 Channel11 half transfer flag. - * DMA2_IT_TE11 - DMA2 Channel11 transfer error flag. - * - * @return The new state of DMAy_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMAy_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - if((DMAy_IT & FLAG_Mask) == FLAG_Mask) - { - tmpreg = DMA2->INTFR; - } - else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) - { - tmpreg = DMA2_EXTEN->INTFR; - } - else - { - tmpreg = DMA1->INTFR; - } - - if((tmpreg & DMAy_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearITPendingBit - * - * @brief Clears the DMAy Channelx's interrupt pending bits. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * DMA2_IT_GL1 - DMA2 Channel1 global flag. - * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. - * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. - * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. - * DMA2_IT_GL2 - DMA2 Channel2 global flag. - * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. - * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. - * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. - * DMA2_IT_GL3 - DMA2 Channel3 global flag. - * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. - * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. - * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. - * DMA2_IT_GL4 - DMA2 Channel4 global flag. - * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. - * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. - * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. - * DMA2_IT_GL5 - DMA2 Channel5 global flag. - * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. - * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. - * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. - * DMA2_IT_GL6 - DMA2 Channel6 global flag. - * DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag. - * DMA2_IT_HT6 - DMA2 Channel6 half transfer flag. - * DMA2_IT_TE6 - DMA2 Channel6 transfer error flag. - * DMA2_IT_GL7 - DMA2 Channel7 global flag. - * DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag. - * DMA2_IT_HT7 - DMA2 Channel7 half transfer flag. - * DMA2_IT_TE7 - DMA2 Channel7 transfer error flag. - * DMA2_IT_GL8 - DMA2 Channel8 global flag. - * DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag. - * DMA2_IT_HT8 - DMA2 Channel8 half transfer flag. - * DMA2_IT_TE8 - DMA2 Channel8 transfer error flag. - * DMA2_IT_GL9 - DMA2 Channel9 global flag. - * DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag. - * DMA2_IT_HT9 - DMA2 Channel9 half transfer flag. - * DMA2_IT_TE9 - DMA2 Channel9 transfer error flag. - * DMA2_IT_GL10 - DMA2 Channel10 global flag. - * DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag. - * DMA2_IT_HT10 - DMA2 Channel10 half transfer flag. - * DMA2_IT_TE10 - DMA2 Channel10 transfer error flag. - * DMA2_IT_GL11 - DMA2 Channel11 global flag. - * DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag. - * DMA2_IT_HT11 - DMA2 Channel11 half transfer flag. - * DMA2_IT_TE11 - DMA2 Channel11 transfer error flag. - * - * @return none - */ -void DMA_ClearITPendingBit(uint32_t DMAy_IT) -{ - if((DMAy_IT & FLAG_Mask) == FLAG_Mask) - { - DMA2->INTFCR = DMAy_IT; - } - else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) - { - DMA2_EXTEN->INTFCR = DMAy_IT; - } - else - { - DMA1->INTFCR = DMAy_IT; - } -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dma.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DMA firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_dma.h" +#include "ch32v30x_rcc.h" + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA2_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA2_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA2_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) +#define DMA2_Channel9_IT_Mask ((uint32_t)(DMA_GIF9 | DMA_TCIF9 | DMA_HTIF9 | DMA_TEIF9)) +#define DMA2_Channel10_IT_Mask ((uint32_t)(DMA_GIF10 | DMA_TCIF10 | DMA_HTIF10 | DMA_TEIF10)) +#define DMA2_Channel11_IT_Mask ((uint32_t)(DMA_GIF11 | DMA_TCIF11 | DMA_HTIF11 | DMA_TEIF11)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) +#define DMA2_EXTEN_FLAG_Mask ((uint32_t)0x20000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel1) + { + DMA2->INTFCR |= DMA2_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel2) + { + DMA2->INTFCR |= DMA2_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel3) + { + DMA2->INTFCR |= DMA2_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel4) + { + DMA2->INTFCR |= DMA2_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel5) + { + DMA2->INTFCR |= DMA2_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel6) + { + DMA2->INTFCR |= DMA2_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel7) + { + DMA2->INTFCR |= DMA2_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel8) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel8_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel9) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel9_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel10) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel10_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel11) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel11_IT_Mask; + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. + * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. + * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. + * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. + * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_FLAG_GL6 - DMA2 Channel6 global flag. + * DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_FLAG_GL7 - DMA2 Channel7 global flag. + * DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_FLAG_GL8 - DMA2 Channel8 global flag. + * DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_FLAG_GL9 - DMA2 Channel9 global flag. + * DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_FLAG_GL10 - DMA2 Channel10 global flag. + * DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_FLAG_GL11 - DMA2 Channel11 global flag. + * DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag. + * + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask) + { + tmpreg = DMA2->INTFR; + } + else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + tmpreg = DMA2_EXTEN->INTFR; + } + else + { + tmpreg = DMA1->INTFR; + } + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. + * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. + * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. + * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. + * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_FLAG_GL6 - DMA2 Channel6 global flag. + * DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_FLAG_GL7 - DMA2 Channel7 global flag. + * DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_FLAG_GL8 - DMA2 Channel8 global flag. + * DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_FLAG_GL9 - DMA2 Channel9 global flag. + * DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_FLAG_GL10 - DMA2 Channel10 global flag. + * DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_FLAG_GL11 - DMA2 Channel11 global flag. + * DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag. + * + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask) + { + DMA2->INTFCR = DMAy_FLAG; + } + else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + DMA2_EXTEN->INTFCR = DMAy_FLAG; + } + else + { + DMA1->INTFCR = DMAy_FLAG; + } +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_IT_GL2 - DMA2 Channel2 global flag. + * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_IT_GL3 - DMA2 Channel3 global flag. + * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_IT_GL4 - DMA2 Channel4 global flag. + * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_IT_GL5 - DMA2 Channel5 global flag. + * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_IT_GL6 - DMA2 Channel6 global flag. + * DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_IT_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_IT_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_IT_GL7 - DMA2 Channel7 global flag. + * DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_IT_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_IT_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_IT_GL8 - DMA2 Channel8 global flag. + * DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_IT_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_IT_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_IT_GL9 - DMA2 Channel9 global flag. + * DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_IT_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_IT_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_IT_GL10 - DMA2 Channel10 global flag. + * DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_IT_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_IT_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_IT_GL11 - DMA2 Channel11 global flag. + * DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_IT_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_IT_TE11 - DMA2 Channel11 transfer error flag. + * + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + if((DMAy_IT & FLAG_Mask) == FLAG_Mask) + { + tmpreg = DMA2->INTFR; + } + else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + tmpreg = DMA2_EXTEN->INTFR; + } + else + { + tmpreg = DMA1->INTFR; + } + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_IT_GL2 - DMA2 Channel2 global flag. + * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_IT_GL3 - DMA2 Channel3 global flag. + * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_IT_GL4 - DMA2 Channel4 global flag. + * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_IT_GL5 - DMA2 Channel5 global flag. + * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_IT_GL6 - DMA2 Channel6 global flag. + * DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_IT_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_IT_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_IT_GL7 - DMA2 Channel7 global flag. + * DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_IT_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_IT_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_IT_GL8 - DMA2 Channel8 global flag. + * DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_IT_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_IT_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_IT_GL9 - DMA2 Channel9 global flag. + * DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_IT_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_IT_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_IT_GL10 - DMA2 Channel10 global flag. + * DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_IT_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_IT_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_IT_GL11 - DMA2 Channel11 global flag. + * DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_IT_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_IT_TE11 - DMA2 Channel11 transfer error flag. + * + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + if((DMAy_IT & FLAG_Mask) == FLAG_Mask) + { + DMA2->INTFCR = DMAy_IT; + } + else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + DMA2_EXTEN->INTFCR = DMAy_IT; + } + else + { + DMA1->INTFCR = DMAy_IT; + } +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dvp.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dvp.c index 225f981..b2134af 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dvp.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_dvp.c @@ -1,135 +1,135 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_dvp.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the DVP firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_dvp.h" - -/********************************************************************* - * @fn DVP_INTCfg - * - * @brief DVP interrupt configuration - * - * @param s - interrupt enable - * ENABLE - * DISABLE - * i - interrupt type - * RB_DVP_IE_STP_FRM - * RB_DVP_IE_FIFO_OV - * RB_DVP_IE_FRM_DONE - * RB_DVP_IE_ROW_DONE - * RB_DVP_IE_STR_FRM - * - * @return none - */ -void DVP_INTCfg(uint8_t s, uint8_t i) -{ - if(s) - { - DVP->IER |= i; - } - else - { - DVP->IER &= ~i; - } -} - -/********************************************************************* - * @fn DVP_Mode - * - * @brief DVP mode - * - * @param s - data bit width - * RB_DVP_D8_MOD - * RB_DVP_D10_MOD - * RB_DVP_D12_MOD - * i - interrupt type - * Video_Mode - * JPEG_Mode - * - * @return none - */ -void DVP_Mode(uint8_t s, DVP_Data_ModeTypeDef i) -{ - DVP->CR0 &= ~RB_DVP_MSK_DAT_MOD; - - if(s) - { - DVP->CR0 |= s; - } - else - { - DVP->CR0 &= ~(3 << 4); - } - - if(i) - { - DVP->CR0 |= RB_DVP_JPEG; - } - else - { - DVP->CR0 &= ~RB_DVP_JPEG; - } -} - -/********************************************************************* - * @fn DVP_Cfg - * - * @brief DVP configuration - * - * @param s - DMA enable control - * DVP_DMA_Enable - * DVP_DMA_Disable - * i - DVP all clear - * DVP_FLAG_FIFO_RESET_Enable - * DVP_FLAG_FIFO_RESET_Disable - * j - receive reset enable - * DVP_RX_RESET_Enable - * DVP_RX_RESET_Disable - * - * @return none - */ -void DVP_Cfg(DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j) -{ - switch(s) - { - case DVP_DMA_Enable: - DVP->CR1 |= RB_DVP_DMA_EN; - break; - case DVP_DMA_Disable: - DVP->CR1 &= ~RB_DVP_DMA_EN; - break; - default: - break; - } - - switch(i) - { - case DVP_RX_RESET_Enable: - DVP->CR1 |= RB_DVP_ALL_CLR; - break; - case DVP_RX_RESET_Disable: - DVP->CR1 &= ~RB_DVP_ALL_CLR; - break; - default: - break; - } - - switch(j) - { - case DVP_RX_RESET_Enable: - DVP->CR1 |= RB_DVP_RCV_CLR; - break; - case DVP_RX_RESET_Disable: - DVP->CR1 &= ~RB_DVP_RCV_CLR; - break; - default: - break; - } -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dvp.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DVP firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_dvp.h" + +/********************************************************************* + * @fn DVP_INTCfg + * + * @brief DVP interrupt configuration + * + * @param s - interrupt enable + * ENABLE + * DISABLE + * i - interrupt type + * RB_DVP_IE_STP_FRM + * RB_DVP_IE_FIFO_OV + * RB_DVP_IE_FRM_DONE + * RB_DVP_IE_ROW_DONE + * RB_DVP_IE_STR_FRM + * + * @return none + */ +void DVP_INTCfg(uint8_t s, uint8_t i) +{ + if(s) + { + DVP->IER |= i; + } + else + { + DVP->IER &= ~i; + } +} + +/********************************************************************* + * @fn DVP_Mode + * + * @brief DVP mode + * + * @param s - data bit width + * RB_DVP_D8_MOD + * RB_DVP_D10_MOD + * RB_DVP_D12_MOD + * i - interrupt type + * Video_Mode + * JPEG_Mode + * + * @return none + */ +void DVP_Mode(uint8_t s, DVP_Data_ModeTypeDef i) +{ + DVP->CR0 &= ~RB_DVP_MSK_DAT_MOD; + + if(s) + { + DVP->CR0 |= s; + } + else + { + DVP->CR0 &= ~(3 << 4); + } + + if(i) + { + DVP->CR0 |= RB_DVP_JPEG; + } + else + { + DVP->CR0 &= ~RB_DVP_JPEG; + } +} + +/********************************************************************* + * @fn DVP_Cfg + * + * @brief DVP configuration + * + * @param s - DMA enable control + * DVP_DMA_Enable + * DVP_DMA_Disable + * i - DVP all clear + * DVP_FLAG_FIFO_RESET_Enable + * DVP_FLAG_FIFO_RESET_Disable + * j - receive reset enable + * DVP_RX_RESET_Enable + * DVP_RX_RESET_Disable + * + * @return none + */ +void DVP_Cfg(DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j) +{ + switch(s) + { + case DVP_DMA_Enable: + DVP->CR1 |= RB_DVP_DMA_EN; + break; + case DVP_DMA_Disable: + DVP->CR1 &= ~RB_DVP_DMA_EN; + break; + default: + break; + } + + switch(i) + { + case DVP_RX_RESET_Enable: + DVP->CR1 |= RB_DVP_ALL_CLR; + break; + case DVP_RX_RESET_Disable: + DVP->CR1 &= ~RB_DVP_ALL_CLR; + break; + default: + break; + } + + switch(j) + { + case DVP_RX_RESET_Enable: + DVP->CR1 |= RB_DVP_RCV_CLR; + break; + case DVP_RX_RESET_Disable: + DVP->CR1 &= ~RB_DVP_RCV_CLR; + break; + default: + break; + } +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_eth.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_eth.c index 6b8b0ee..30f20b7 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_eth.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_eth.c @@ -1,2523 +1,2523 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_eth.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the ETH firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_eth.h" -#include "ch32v30x_rcc.h" - -ETH_DMADESCTypeDef *DMATxDescToSet; -ETH_DMADESCTypeDef *DMARxDescToGet; -ETH_DMADESCTypeDef *DMAPTPTxDescToSet; -ETH_DMADESCTypeDef *DMAPTPRxDescToGet; - -/********************************************************************* - * @fn ETH_DeInit - * - * @brief ETH hardware initialize again. - * - * @return none - */ -#ifdef CH32V30x_D8C -void ETH_DeInit(void) -{ - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE); -} - -#endif - -/********************************************************************* - * @fn ETH_StructInit - * - * @brief Fills each ETH_InitStruct member with its default value. - * - * @param ETH_InitStruct - pointer to a ETH_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void ETH_StructInit(ETH_InitTypeDef *ETH_InitStruct) -{ - /*------------------------ MAC -----------------------------------*/ - ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; - ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; - ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; - ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; - ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; - ETH_InitStruct->ETH_Speed = ETH_Speed_10M; - ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; - ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; - ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; - ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; - ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; - ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; - ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; - ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; - ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; - ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; - ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; - ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; - ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; - ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; - ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; - ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; - ETH_InitStruct->ETH_HashTableHigh = 0x0; - ETH_InitStruct->ETH_HashTableLow = 0x0; - ETH_InitStruct->ETH_PauseTime = 0x0; - ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; - ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; - ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; - ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; - ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; - ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; - ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; - /*------------------------ DMA -----------------------------------*/ - ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; - ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; - ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; - ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; - ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; - ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; - ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; - ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; - ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; - ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; - ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; - ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; - ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; - ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; - ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; -} - -/********************************************************************* - * @fn ETH_Start - * - * @brief Enables ENET MAC and DMA reception/transmission. - * - * @return none - */ -void ETH_Start(void) -{ - ETH_MACTransmissionCmd(ENABLE); - ETH_FlushTransmitFIFO(); - ETH_MACReceptionCmd(ENABLE); - ETH_DMATransmissionCmd(ENABLE); - ETH_DMAReceptionCmd(ENABLE); -} - -/********************************************************************* - * @fn ETH_HandleTxPkt - * - * @brief Transmits a packet, from application buffer, pointed by ppkt. - * - * @param ppkt - pointer to the application's packet buffer to transmit. - * FrameLength - Tx Packet size. - * - * @return ETH_ERROR - in case of Tx desc owned by DMA. - * ETH_SUCCESS - for correct transmission. - */ -uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) -{ - uint32_t offset = 0; - - if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) - { - return ETH_ERROR; - } - - for(offset = 0; offset < FrameLength; offset++) - { - (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset)); - } - - DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); - DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; - DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; - - if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) - { - ETH->DMASR = ETH_DMASR_TBUS; - ETH->DMATPDR = 0; - } - - if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) - { - DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr); - } - else - { - if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) - { - DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); - } - else - { - DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); - } - } - - return ETH_SUCCESS; -} - -/********************************************************************* - * @fn ETH_HandleRxPkt - * - * @brief Receives a packet and copies it to memory pointed by ppkt. - * - * @param ppkt - pointer to the application packet receive buffer. - * - * @return ETH_ERROR - if there is error in reception - * framelength - received packet size if packet reception is correct - */ -uint32_t ETH_HandleRxPkt(uint8_t *ppkt) -{ - uint32_t offset = 0, framelength = 0; - - if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) - { - return ETH_ERROR; - } - - if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) - { - framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; - - for(offset = 0; offset < framelength; offset++) - { - (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset)); - } - } - else - { - framelength = ETH_ERROR; - } - - DMARxDescToGet->Status = ETH_DMARxDesc_OWN; - - if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) - { - ETH->DMASR = ETH_DMASR_RBUS; - ETH->DMARPDR = 0; - } - - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) - { - DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr); - } - else - { - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) - { - DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); - } - else - { - DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); - } - } - - return (framelength); -} - -/********************************************************************* - * @fn ETH_GetRxPktSize - * - * @brief Get the size of received the received packet. - * - * @return framelength - received packet size - */ -uint32_t ETH_GetRxPktSize(void) -{ - uint32_t frameLength = 0; - if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) - { - frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); - } - - return frameLength; -} - -/********************************************************************* - * @fn ETH_DropRxPkt - * - * @brief Drop a Received packet. - * - * @return none - */ -void ETH_DropRxPkt(void) -{ - DMARxDescToGet->Status = ETH_DMARxDesc_OWN; - - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) - { - DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr); - } - else - { - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) - { - DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); - } - else - { - DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); - } - } -} - -/********************************************************************* - * @fn ETH_ReadPHYRegister - * - * @brief Read a PHY register. - * - * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. - * PHYReg - PHY register address, is the index of one of the 32 PHY register. - * - * @return ETH_ERROR - in case of timeout. - * MAC MIIDR register value - Data read from the selected PHY register. - */ -uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) -{ - uint32_t tmpreg = 0; - __IO uint32_t timeout = 0; - - tmpreg = ETH->MACMIIAR; - tmpreg &= ~MACMIIAR_CR_MASK; - tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA); - tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR); - tmpreg &= ~ETH_MACMIIAR_MW; - tmpreg |= ETH_MACMIIAR_MB; - ETH->MACMIIAR = tmpreg; - - do - { - timeout++; - tmpreg = ETH->MACMIIAR; - } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); - - if(timeout == PHY_READ_TO) - { - return (uint16_t)ETH_ERROR; - } - - return (uint16_t)(ETH->MACMIIDR); -} - -/********************************************************************* - * @fn ETH_WritePHYRegister - * - * @brief Write to a PHY register. - * - * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. - * PHYReg - PHY register address, is the index of one of the 32 PHY register. - * PHYValue - the value to write. - * - * @return ETH_ERROR - in case of timeout. - * ETH_SUCCESS - for correct write - */ -uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) -{ - uint32_t tmpreg = 0; - __IO uint32_t timeout = 0; - - tmpreg = ETH->MACMIIAR; - tmpreg &= ~MACMIIAR_CR_MASK; - tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA); - tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR); - tmpreg |= ETH_MACMIIAR_MW; - tmpreg |= ETH_MACMIIAR_MB; - ETH->MACMIIDR = PHYValue; - ETH->MACMIIAR = tmpreg; - - do - { - timeout++; - tmpreg = ETH->MACMIIAR; - } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); - - if(timeout >= PHY_WRITE_TO) - { - return ETH_ERROR; - } - - return ETH_SUCCESS; -} - -/********************************************************************* - * @fn ETH_PHYLoopBackCmd - * - * @brief Enables or disables the PHY loopBack mode. - * - * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. - * NewState - new state of the PHY loopBack mode. - * - * @return ETH_ERROR - in case of bad PHY configuration. - * ETH_SUCCESS - for correct PHY configuration. - */ -uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) -{ - uint16_t tmpreg = 0; - - tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); - - if(NewState != DISABLE) - { - tmpreg |= PHY_Loopback; - } - else - { - tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); - } - - if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) - { - return ETH_SUCCESS; - } - else - { - return ETH_ERROR; - } -} - -/********************************************************************* - * @fn ETH_MACTransmissionCmd - * - * @brief Enables or disables the MAC transmission. - * - * @param NewState - new state of the MAC transmission. - * - * @return none - */ -void ETH_MACTransmissionCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->MACCR |= ETH_MACCR_TE; - } - else - { - ETH->MACCR &= ~ETH_MACCR_TE; - } -} - -/********************************************************************* - * @fn ETH_MACReceptionCmd - * - * @brief Enables or disables the MAC reception. - * - * @param NewState - new state of the MAC reception. - * - * @return none - */ -void ETH_MACReceptionCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->MACCR |= ETH_MACCR_RE; - } - else - { - ETH->MACCR &= ~ETH_MACCR_RE; - } -} - -/********************************************************************* - * @fn ETH_GetFlowControlBusyStatus - * - * @brief Enables or disables the MAC reception. - * - * @return The new state of flow control busy status bit (SET or RESET). - */ -FlagStatus ETH_GetFlowControlBusyStatus(void) -{ - FlagStatus bitstatus = RESET; - - if((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn ETH_InitiatePauseControlFrame - * - * @brief Initiate a Pause Control Frame (Full-duplex only). - * - * @return none - */ -void ETH_InitiatePauseControlFrame(void) -{ - ETH->MACFCR |= ETH_MACFCR_FCBBPA; -} - -/********************************************************************* - * @fn ETH_BackPressureActivationCmd - * - * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). - * - * @param NewState - new state of the MAC BackPressure operation activation. - * - * @return none - */ -void ETH_BackPressureActivationCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->MACFCR |= ETH_MACFCR_FCBBPA; - } - else - { - ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; - } -} - -/********************************************************************* - * @fn ETH_GetMACFlagStatus - * - * @brief Checks whether the specified ETHERNET MAC flag is set or not. - * - * @param ETH_MAC_FLAG - specifies the flag to check. - * - * @return The new state of ETHERNET MAC flag (SET or RESET). - */ -FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn ETH_GetMACITStatus - * - * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. - * - * @param ETH_MAC_IT - specifies the interrupt source to check. - * - * @return The new state of ETHERNET MAC interrupt (SET or RESET). - */ -ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) -{ - FlagStatus bitstatus = RESET; - - if((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ETH_MACITConfig - * - * @brief Enables or disables the specified ETHERNET MAC interrupts. - * - * @param ETH_MAC_IT - specifies the interrupt source to check. - * NewState - new state of the specified ETHERNET MAC interrupts. - * - * @return none - */ -void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); - } - else - { - ETH->MACIMR |= ETH_MAC_IT; - } -} - -/********************************************************************* - * @fn ETH_MACAddressConfig - * - * @brief Configures the selected MAC address. - * - * @param MacAddr - The MAC addres to configure. - * ETH_MAC_Address0 - MAC Address0 - * ETH_MAC_Address1 - MAC Address1 - * ETH_MAC_Address2 - MAC Address2 - * ETH_MAC_Address3 - MAC Address3 - * Addr - Pointer on MAC address buffer data (6 bytes). - * - * @return none - */ -void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) -{ - uint32_t tmpreg; - - tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; - tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; - - (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg; -} - -/********************************************************************* - * @fn ETH_GetMACAddress - * - * @brief Get the selected MAC address. - * - * @param MacAddr - The MAC address to return. - * ETH_MAC_Address0 - MAC Address0 - * ETH_MAC_Address1 - MAC Address1 - * ETH_MAC_Address2 - MAC Address2 - * ETH_MAC_Address3 - MAC Address3 - * Addr - Pointer on MAC address buffer data (6 bytes). - * - * @return none - */ -void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) -{ - uint32_t tmpreg; - - tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)); - - Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); - Addr[4] = (tmpreg & (uint8_t)0xFF); - tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr)); - Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); - Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); - Addr[1] = ((tmpreg >> 8) & (uint8_t)0xFF); - Addr[0] = (tmpreg & (uint8_t)0xFF); -} - -/********************************************************************* - * @fn ETH_MACAddressPerfectFilterCmd - * - * @brief Enables or disables the Address filter module uses the specified. - * - * @param MacAddr - The MAC address to return. - * ETH_MAC_Address0 - MAC Address0 - * ETH_MAC_Address1 - MAC Address1 - * ETH_MAC_Address2 - MAC Address2 - * ETH_MAC_Address3 - MAC Address3 - * NewState - new state of the specified ETHERNET MAC address use. - * - * @return none - */ -void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE; - } - else - { - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_AE); - } -} - -/********************************************************************* - * @fn ETH_MACAddressFilterConfig - * - * @brief Set the filter type for the specified ETHERNET MAC address. - * - * @param MacAddr - specifies the ETHERNET MAC address. - * ETH_MAC_Address0 - MAC Address0 - * ETH_MAC_Address1 - MAC Address1 - * ETH_MAC_Address2 - MAC Address2 - * ETH_MAC_Address3 - MAC Address3 - * Filter - specifies the used frame received field for comparaison. - * ETH_MAC_AddressFilter_SA - MAC Address is used to compare with the - * SA fields of the received frame. - * ETH_MAC_AddressFilter_DA - MAC Address is used to compare with the - * DA fields of the received frame. - * - * @return none - */ -void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) -{ - if(Filter != ETH_MAC_AddressFilter_DA) - { - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA; - } - else - { - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_SA); - } -} - -/********************************************************************* - * @fn ETH_MACAddressMaskBytesFilterConfig - * - * @brief Set the filter type for the specified ETHERNET MAC address. - * - * @param MacAddr - specifies the ETHERNET MAC address. - * ETH_MAC_Address1 - MAC Address1 - * ETH_MAC_Address2 - MAC Address2 - * ETH_MAC_Address3 - MAC Address3 - * MaskByte - specifies the used address bytes for comparaison - * ETH_MAC_AddressMask_Byte5 - Mask MAC Address high reg bits [7:0]. - * ETH_MAC_AddressMask_Byte4 - Mask MAC Address low reg bits [31:24]. - * ETH_MAC_AddressMask_Byte3 - Mask MAC Address low reg bits [23:16]. - * ETH_MAC_AddressMask_Byte2 - Mask MAC Address low reg bits [15:8]. - * ETH_MAC_AddressMask_Byte1 - Mask MAC Address low reg bits [7:0]. - * - * @return none - */ -void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) -{ - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_MBC); - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte; -} - -/********************************************************************* - * @fn ETH_DMATxDescChainInit - * - * @brief Initializes the DMA Tx descriptors in chain mode. - * - * @param DMATxDescTab - Pointer on the first Tx desc list - * TxBuff - Pointer on the first TxBuffer list - * TxBuffCount - Number of the used Tx desc in the list - * - * @return none - */ -void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) -{ - uint32_t i = 0; - ETH_DMADESCTypeDef *DMATxDesc; - - DMATxDescToSet = DMATxDescTab; - - for(i = 0; i < TxBuffCount; i++) - { - DMATxDesc = DMATxDescTab + i; - DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC; - DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); - - if(i < (TxBuffCount - 1)) - { - DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); - } - else - { - DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab; - } - } - - ETH->DMATDLAR = (uint32_t)DMATxDescTab; -} - -/********************************************************************* - * @fn ETH_DMATxDescRingInit - * - * @brief Initializes the DMA Tx descriptors in ring mode. - * - * @param DMATxDescTab - Pointer on the first Tx desc list. - * TxBuff1 - Pointer on the first TxBuffer1 list. - * TxBuff2 - Pointer on the first TxBuffer2 list. - * TxBuffCount - Number of the used Tx desc in the list. - * - * @return none - */ -void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) -{ - uint32_t i = 0; - ETH_DMADESCTypeDef *DMATxDesc; - - DMATxDescToSet = DMATxDescTab; - - for(i = 0; i < TxBuffCount; i++) - { - DMATxDesc = DMATxDescTab + i; - DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i * ETH_MAX_PACKET_SIZE]); - DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i * ETH_MAX_PACKET_SIZE]); - - if(i == (TxBuffCount - 1)) - { - DMATxDesc->Status = ETH_DMATxDesc_TER; - } - } - - ETH->DMATDLAR = (uint32_t)DMATxDescTab; -} - -/********************************************************************* - * @fn ETH_GetDMATxDescFlagStatus - * - * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. - * - * @param DMATxDesc - pointer on a DMA Tx descriptor - * ETH_DMATxDescFlag - specifies the flag to check. - * ETH_DMATxDesc_OWN - OWN bit - descriptor is owned by DMA engine - * ETH_DMATxDesc_IC - Interrupt on completetion - * ETH_DMATxDesc_LS - Last Segment - * ETH_DMATxDesc_FS - First Segment - * ETH_DMATxDesc_DC - Disable CRC - * ETH_DMATxDesc_DP - Disable Pad - * ETH_DMATxDesc_TTSE - Transmit Time Stamp Enable - * ETH_DMATxDesc_TER - Transmit End of Ring - * ETH_DMATxDesc_TCH - Second Address Chained - * ETH_DMATxDesc_TTSS - Tx Time Stamp Status - * ETH_DMATxDesc_IHE - IP Header Error - * ETH_DMATxDesc_ES - Error summary - * ETH_DMATxDesc_JT - Jabber Timeout - * ETH_DMATxDesc_FF - Frame Flushed - DMA/MTL flushed the frame due to SW flush - * ETH_DMATxDesc_PCE - Payload Checksum Error - * ETH_DMATxDesc_LCA - Loss of Carrier - carrier lost during tramsmission - * ETH_DMATxDesc_NC - No Carrier - no carrier signal from the tranceiver - * ETH_DMATxDesc_LCO - Late Collision - transmission aborted due to collision - * ETH_DMATxDesc_EC - Excessive Collision - transmission aborted after 16 collisions - * ETH_DMATxDesc_VF - VLAN Frame - * ETH_DMATxDesc_CC - Collision Count - * ETH_DMATxDesc_ED - Excessive Deferral - * ETH_DMATxDesc_UF - Underflow Error - late data arrival from the memory - * ETH_DMATxDesc_DB - Deferred Bit - * - * @return The new state of ETH_DMATxDescFlag (SET or RESET). - */ -FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) -{ - FlagStatus bitstatus = RESET; - - if((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ETH_GetDMATxDescCollisionCount - * - * @brief Returns the specified ETHERNET DMA Tx Desc collision count. - * - * @param pointer on a DMA Tx descriptor. - * - * @return The Transmit descriptor collision counter value. - */ -uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) -{ - return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); -} - -/********************************************************************* - * @fn ETH_SetDMATxDescOwnBit - * - * @brief Set the specified DMA Tx Desc Own bit. - * - * @param DMATxDesc - Pointer on a Tx desc - * - * @return none - */ -void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) -{ - DMATxDesc->Status |= ETH_DMATxDesc_OWN; -} - -/********************************************************************* - * @fn ETH_DMATxDescTransmitITConfig - * - * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. - * - * @param Pointer on a Tx desc. - * NewState - new state of the DMA Tx Desc transmit interrupt. - * - * @return none - */ -void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMATxDesc->Status |= ETH_DMATxDesc_IC; - } - else - { - DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_IC); - } -} - -/********************************************************************* - * @fn ETH_DMATxDescFrameSegmentConfig - * - * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. - * - * @param PDMATxDesc - Pointer on a Tx desc. - * ETH_DMATxDesc_FirstSegment - actual Tx desc contain first segment. - * - * @return none - */ -void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) -{ - DMATxDesc->Status |= DMATxDesc_FrameSegment; -} - -/********************************************************************* - * @fn ETH_DMATxDescChecksumInsertionConfig - * - * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. - * - * @param DMATxDesc - pointer on a DMA Tx descriptor. - * DMATxDesc_Checksum - specifies is the DMA Tx desc checksum insertion. - * - * @return none - */ -void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) -{ - DMATxDesc->Status |= DMATxDesc_Checksum; -} - -/********************************************************************* - * @fn ETH_DMATxDescCRCCmd - * - * @brief Enables or disables the DMA Tx Desc CRC. - * - * @param DMATxDesc - pointer on a DMA Tx descriptor - * NewState - new state of the specified DMA Tx Desc CRC. - * - * @return none - */ -void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); - } - else - { - DMATxDesc->Status |= ETH_DMATxDesc_DC; - } -} - -/********************************************************************* - * @fn ETH_DMATxDescEndOfRingCmd - * - * @brief Enables or disables the DMA Tx Desc end of ring. - * - * @param DMATxDesc - pointer on a DMA Tx descriptor. - * NewState - new state of the specified DMA Tx Desc end of ring. - * - * @return none - */ -void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMATxDesc->Status |= ETH_DMATxDesc_TER; - } - else - { - DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); - } -} - -/********************************************************************* - * @fn ETH_DMATxDescSecondAddressChainedCmd - * - * @brief Enables or disables the DMA Tx Desc second address chained. - * - * @param DMATxDesc - pointer on a DMA Tx descriptor - * NewState - new state of the specified DMA Tx Desc second address chained. - * - * @return none - */ -void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMATxDesc->Status |= ETH_DMATxDesc_TCH; - } - else - { - DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TCH); - } -} - -/********************************************************************* - * @fn ETH_DMATxDescShortFramePaddingCmd - * - * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. - * - * @param DMATxDesc - pointer on a DMA Tx descriptor. - * NewState - new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes. - * - * @return none - */ -void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); - } - else - { - DMATxDesc->Status |= ETH_DMATxDesc_DP; - } -} - -/********************************************************************* - * @fn ETH_DMATxDescTimeStampCmd - * - * @brief Enables or disables the DMA Tx Desc time stamp. - * - * @param DMATxDesc - pointer on a DMA Tx descriptor - * NewState - new state of the specified DMA Tx Desc time stamp. - * - * @return none - */ -void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMATxDesc->Status |= ETH_DMATxDesc_TTSE; - } - else - { - DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TTSE); - } -} - -/********************************************************************* - * @fn ETH_DMATxDescBufferSizeConfig - * - * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. - * - * @param DMATxDesc - Pointer on a Tx desc. - * BufferSize1 - specifies the Tx desc buffer1 size. - * RxBuff2 - Pointer on the first RxBuffer2 list - * BufferSize2 - specifies the Tx desc buffer2 size (put "0" if not used). - * - * @return none - */ -void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) -{ - DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); -} - -/********************************************************************* - * @fn ETH_DMARxDescChainInit - * - * @brief Initializes the DMA Rx descriptors in chain mode. - * - * @param DMARxDescTab - Pointer on the first Rx desc list. - * RxBuff - Pointer on the first RxBuffer list. - * RxBuffCount - Number of the used Rx desc in the list. - * - * @return none - */ -void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) -{ - uint32_t i = 0; - ETH_DMADESCTypeDef *DMARxDesc; - - DMARxDescToGet = DMARxDescTab; - - for(i = 0; i < RxBuffCount; i++) - { - DMARxDesc = DMARxDescTab + i; - DMARxDesc->Status = ETH_DMARxDesc_OWN; - DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); - - if(i < (RxBuffCount - 1)) - { - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); - } - else - { - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); - } - } - - ETH->DMARDLAR = (uint32_t)DMARxDescTab; -} - -/********************************************************************* - * @fn ETH_DMARxDescRingInit - * - * @brief Initializes the DMA Rx descriptors in ring mode. - * - * @param DMARxDescTab - Pointer on the first Rx desc list. - * RxBuff1 - Pointer on the first RxBuffer1 list. - * RxBuff2 - Pointer on the first RxBuffer2 list - * RxBuffCount - Number of the used Rx desc in the list. - * - * @return none - */ -void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) -{ - uint32_t i = 0; - ETH_DMADESCTypeDef *DMARxDesc; - - DMARxDescToGet = DMARxDescTab; - - for(i = 0; i < RxBuffCount; i++) - { - DMARxDesc = DMARxDescTab + i; - DMARxDesc->Status = ETH_DMARxDesc_OWN; - DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i * ETH_MAX_PACKET_SIZE]); - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i * ETH_MAX_PACKET_SIZE]); - - if(i == (RxBuffCount - 1)) - { - DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; - } - } - - ETH->DMARDLAR = (uint32_t)DMARxDescTab; -} - -/********************************************************************* - * @fn ETH_GetDMARxDescFlagStatus - * - * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. - * - * @param DMARxDesc - pointer on a DMA Rx descriptor. - * ETH_DMARxDescFlag - specifies the flag to check. - * ETH_DMARxDesc_OWN - OWN bit: descriptor is owned by DMA engine - * ETH_DMARxDesc_AFM - DA Filter Fail for the rx frame - * ETH_DMARxDesc_ES - Error summary - * ETH_DMARxDesc_DE - Desciptor error: no more descriptors for receive frame - * ETH_DMARxDesc_SAF - SA Filter Fail for the received frame - * ETH_DMARxDesc_LE - Frame size not matching with length field - * ETH_DMARxDesc_OE - Overflow Error: Frame was damaged due to buffer overflow - * ETH_DMARxDesc_VLAN - VLAN Tag: received frame is a VLAN frame - * ETH_DMARxDesc_FS - First descriptor of the frame - * ETH_DMARxDesc_LS - Last descriptor of the frame - * ETH_DMARxDesc_IPV4HCE - IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error - * ETH_DMARxDesc_LC - Late collision occurred during reception - * ETH_DMARxDesc_FT - Frame type - Ethernet, otherwise 802.3 - * ETH_DMARxDesc_RWT - Receive Watchdog Timeout: watchdog timer expired during reception - * ETH_DMARxDesc_RE - Receive error: error reported by MII interface - * ETH_DMARxDesc_DE - Dribble bit error: frame contains non int multiple of 8 bits - * ETH_DMARxDesc_CE - CRC error - * ETH_DMARxDesc_MAMPCE - Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error - * - * @return The new state of ETH_DMARxDescFlag (SET or RESET). - */ -FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) -{ - FlagStatus bitstatus = RESET; - - if((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ETH_SetDMARxDescOwnBit - * - * @brief Set the specified DMA Rx Desc Own bit. - * - * @param DMARxDesc - Pointer on a Rx desc - * - * @return none - */ -void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) -{ - DMARxDesc->Status |= ETH_DMARxDesc_OWN; -} - -/********************************************************************* - * @fn ETH_GetDMARxDescFrameLength - * - * @brief Returns the specified DMA Rx Desc frame length. - * - * @param DMARxDesc - pointer on a DMA Rx descriptor - * - * @return The Rx descriptor received frame length. - */ -uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) -{ - return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); -} - -/********************************************************************* - * @fn ETH_DMARxDescReceiveITConfig - * - * @brief Enables or disables the specified DMA Rx Desc receive interrupt. - * - * @param DMARxDesc - Pointer on a Rx desc - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_DIC); - } - else - { - DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; - } -} - -/********************************************************************* - * @fn ETH_DMARxDescEndOfRingCmd - * - * @brief Enables or disables the DMA Rx Desc end of ring. - * - * @param DMARxDesc - pointer on a DMA Rx descriptor. - * NewState - new state of the specified DMA Rx Desc end of ring. - * - * @return none - */ -void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; - } - else - { - DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RER); - } -} - -/********************************************************************* - * @fn ETH_DMARxDescSecondAddressChainedCmd - * - * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. - * - * @param DMARxDesc - pointer on a DMA Rx descriptor. - * NewState - new state of the specified DMA Rx Desc second address chained. - * - * @return none - */ -void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; - } - else - { - DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RCH); - } -} - -/********************************************************************* - * @fn ETH_GetDMARxDescBufferSize - * - * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. - * - * @param DMARxDesc - pointer on a DMA Rx descriptor. - * DMARxDesc_Buffer - specifies the DMA Rx Desc buffer. - * ETH_DMARxDesc_Buffer1 - DMA Rx Desc Buffer1 - * ETH_DMARxDesc_Buffer2 - DMA Rx Desc Buffer2 - * - * @return The Receive descriptor frame length. - */ -uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) -{ - if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) - { - return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); - } - else - { - return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); - } -} - -/********************************************************************* - * @fn ETH_SoftwareReset - * - * @brief Resets all MAC subsystem internal registers and logic. - * - * @return none - */ -void ETH_SoftwareReset(void) -{ - ETH->DMABMR |= ETH_DMABMR_SR; -} - -/********************************************************************* - * @fn ETH_GetSoftwareResetStatus - * - * @brief Checks whether the ETHERNET software reset bit is set or not. - * - * @return The new state of DMA Bus Mode register SR bit (SET or RESET). - */ -FlagStatus ETH_GetSoftwareResetStatus(void) -{ - FlagStatus bitstatus = RESET; - if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ETH_GetlinkStaus - * - * @brief Checks whether the internal 10BASE-T PHY is link or not. - * - * @return Internal 10BASE-T PHY is link or not. - */ -FlagStatus ETH_GetlinkStaus(void) -{ - FlagStatus bitstatus = RESET; - - if((ETH->DMASR & 0x80000000) != (uint32_t)RESET) - { - bitstatus = PHY_10BASE_T_LINKED; - } - else - { - bitstatus = PHY_10BASE_T_NOT_LINKED; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ETH_GetDMAFlagStatus - * - * @brief Checks whether the specified ETHERNET DMA flag is set or not. - * - * @param ETH_DMA_FLAG - specifies the flag to check. - * ETH_DMA_FLAG_TST - Time-stamp trigger flag - * ETH_DMA_FLAG_PMT - PMT flag - * ETH_DMA_FLAG_MMC - MMC flag - * ETH_DMA_FLAG_DataTransferError - Error bits 0-data buffer, 1-desc. access - * ETH_DMA_FLAG_ReadWriteError - Error bits 0-write trnsf, 1-read transfr - * ETH_DMA_FLAG_AccessError - Error bits 0-Rx DMA, 1-Tx DMA - * ETH_DMA_FLAG_NIS - Normal interrupt summary flag - * ETH_DMA_FLAG_AIS - Abnormal interrupt summary flag - * ETH_DMA_FLAG_ER - Early receive flag - * ETH_DMA_FLAG_FBE - Fatal bus error flag - * ETH_DMA_FLAG_ET - Early transmit flag - * ETH_DMA_FLAG_RWT - Receive watchdog timeout flag - * ETH_DMA_FLAG_RPS - Receive process stopped flag - * ETH_DMA_FLAG_RBU - Receive buffer unavailable flag - * ETH_DMA_FLAG_R - Receive flag - * ETH_DMA_FLAG_TU - Underflow flag - * ETH_DMA_FLAG_RO - Overflow flag - * ETH_DMA_FLAG_TJT - Transmit jabber timeout flag - * ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag - * ETH_DMA_FLAG_TPS - Transmit process stopped flag - * ETH_DMA_FLAG_T - Transmit flag - * - * @return Internal 10BASE-T PHY is link or not. - */ -FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn ETH_DMAClearFlag - * - * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. - * - * @param ETH_DMA_FLAG - specifies the flag to clear. - * ETH_DMA_FLAG_NIS - Normal interrupt summary flag - * ETH_DMA_FLAG_AIS - Abnormal interrupt summary flag - * ETH_DMA_FLAG_ER - Early receive flag - * ETH_DMA_FLAG_FBE - Fatal bus error flag - * ETH_DMA_FLAG_ETI - Early transmit flag - * ETH_DMA_FLAG_RWT - Receive watchdog timeout flag - * ETH_DMA_FLAG_RPS - Receive process stopped flag - * ETH_DMA_FLAG_RBU - Receive buffer unavailable flag - * ETH_DMA_FLAG_R - Receive flag - * ETH_DMA_FLAG_TU - Transmit Underflow flag - * ETH_DMA_FLAG_RO - Receive Overflow flag - * ETH_DMA_FLAG_TJT - Transmit jabber timeout flag - * ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag - * ETH_DMA_FLAG_TPS - Transmit process stopped flag - * ETH_DMA_FLAG_T - Transmit flag - * - * @return none - */ -void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) -{ - ETH->DMASR = (uint32_t)ETH_DMA_FLAG; -} - -/********************************************************************* - * @fn ETH_GetDMAITStatus - * - * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. - * - * @param ETH_DMA_IT - specifies the interrupt pending bit to clear. - * ETH_DMA_IT_TST - Time-stamp trigger interrupt - * ETH_DMA_IT_PMT - PMT interrupt - * ETH_DMA_IT_MMC - MMC interrupt - * ETH_DMA_IT_NIS - Normal interrupt summary - * ETH_DMA_IT_AIS - Abnormal interrupt summary - * ETH_DMA_IT_ER - Early receive interrupt - * ETH_DMA_IT_FBE - Fatal bus error interrupt - * ETH_DMA_IT_ET - Early transmit interrupt - * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt - * ETH_DMA_IT_RPS - Receive process stopped interrupt - * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt - * ETH_DMA_IT_R - Receive interrupt - * ETH_DMA_IT_TU - Underflow interrupt - * ETH_DMA_IT_RO - Overflow interrupt - * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt - * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt - * ETH_DMA_IT_TPS - Transmit process stopped interrupt - * ETH_DMA_IT_T - Transmit interrupt - * - * @return The new state of ETH_DMA_IT (SET or RESET). - */ -ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) -{ - ITStatus bitstatus = RESET; - - if((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn ETH_DMAClearITPendingBit - * - * @brief Clears the ETHERNET"s DMA IT pending bit. - * - * @param ETH_DMA_IT - specifies the interrupt pending bit to clear. - * ETH_DMA_IT_NIS - Normal interrupt summary - * ETH_DMA_IT_AIS - Abnormal interrupt summary - * ETH_DMA_IT_ER - Early receive interrupt - * ETH_DMA_IT_FBE - Fatal bus error interrupt - * ETH_DMA_IT_ETI - Early transmit interrupt - * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt - * ETH_DMA_IT_RPS - Receive process stopped interrupt - * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt - * ETH_DMA_IT_R - Receive interrupt - * ETH_DMA_IT_TU - Transmit Underflow interrupt - * ETH_DMA_IT_RO - Receive Overflow interrupt - * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt - * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt - * ETH_DMA_IT_TPS - Transmit process stopped interrupt - * ETH_DMA_IT_T - Transmit interrupt - * - * @return none - */ -void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) -{ - ETH->DMASR = (uint32_t)ETH_DMA_IT; -} - -/********************************************************************* - * @fn ETH_GetTransmitProcessState - * - * @brief Returns the ETHERNET DMA Transmit Process State. - * - * @return The new ETHERNET DMA Transmit Process State - - * ETH_DMA_TransmitProcess_Stopped - Stopped - Reset or Stop Tx Command issued - * ETH_DMA_TransmitProcess_Fetching - Running - fetching the Tx descriptor - * ETH_DMA_TransmitProcess_Waiting - Running - waiting for status - * ETH_DMA_TransmitProcess_Reading - unning - reading the data from host memory - * ETH_DMA_TransmitProcess_Suspended - Suspended - Tx Desciptor unavailabe - * ETH_DMA_TransmitProcess_Closing - Running - closing Rx descriptor - */ -uint32_t ETH_GetTransmitProcessState(void) -{ - return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); -} - -/********************************************************************* - * @fn ETH_GetReceiveProcessState - * - * @brief Returns the ETHERNET DMA Receive Process State. - * - * @return The new ETHERNET DMA Receive Process State: - * ETH_DMA_ReceiveProcess_Stopped - Stopped - Reset or Stop Rx Command issued - * ETH_DMA_ReceiveProcess_Fetching - Running - fetching the Rx descriptor - * ETH_DMA_ReceiveProcess_Waiting - Running - waiting for packet - * ETH_DMA_ReceiveProcess_Suspended - Suspended - Rx Desciptor unavailable - * ETH_DMA_ReceiveProcess_Closing - Running - closing descriptor - * ETH_DMA_ReceiveProcess_Queuing - Running - queuing the recieve frame into host memory - */ -uint32_t ETH_GetReceiveProcessState(void) -{ - return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); -} - -/********************************************************************* - * @fn ETH_FlushTransmitFIFO - * - * @brief Clears the ETHERNET transmit FIFO. - * - * @return none - */ -void ETH_FlushTransmitFIFO(void) -{ - ETH->DMAOMR |= ETH_DMAOMR_FTF; -} - -/********************************************************************* - * @fn ETH_GetFlushTransmitFIFOStatus - * - * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not. - * - * @return The new state of ETHERNET flush transmit FIFO bit (SET or RESET). - */ -FlagStatus ETH_GetFlushTransmitFIFOStatus(void) -{ - FlagStatus bitstatus = RESET; - if((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn ETH_DMATransmissionCmd - * - * @brief Enables or disables the DMA transmission. - * - * @param NewState - new state of the DMA transmission. - * - * @return none - */ -void ETH_DMATransmissionCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->DMAOMR |= ETH_DMAOMR_ST; - } - else - { - ETH->DMAOMR &= ~ETH_DMAOMR_ST; - } -} - -/********************************************************************* - * @fn ETH_DMAReceptionCmd - * - * @brief Enables or disables the DMA reception. - * - * @param NewState - new state of the DMA reception. - * - * @return none - */ -void ETH_DMAReceptionCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->DMAOMR |= ETH_DMAOMR_SR; - } - else - { - ETH->DMAOMR &= ~ETH_DMAOMR_SR; - } -} - -/********************************************************************* - * @fn ETH_DMAITConfig - * - * @brief Enables or disables the specified ETHERNET DMA interrupts. - * - * @param ETH_DMA_IT - specifies the ETHERNET DMA interrupt sources to be enabled or disabled. - * ETH_DMA_IT_NIS - Normal interrupt summary - * ETH_DMA_IT_AIS - Abnormal interrupt summary - * ETH_DMA_IT_ER - Early receive interrupt - * ETH_DMA_IT_FBE - Fatal bus error interrupt - * ETH_DMA_IT_ET - Early transmit interrupt - * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt - * ETH_DMA_IT_RPS - Receive process stopped interrupt - * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt - * ETH_DMA_IT_R - Receive interrupt - * ETH_DMA_IT_TU - Underflow interrupt - * ETH_DMA_IT_RO - Overflow interrupt - * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt - * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt - * ETH_DMA_IT_TPS - Transmit process stopped interrupt - * ETH_DMA_IT_T - Transmit interrupt - * ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter - * ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter - * NewState - new state of the specified ETHERNET DMA interrupts. - * - * @return new state of the specified ETHERNET DMA interrupts. - */ -void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->DMAIER |= ETH_DMA_IT; - } - else - { - ETH->DMAIER &= (~(uint32_t)ETH_DMA_IT); - } -} - -/********************************************************************* - * @fn ETH_GetDMAOverflowStatus - * - * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. - * - * @param ETH_DMA_Overflow - specifies the DMA overflow flag to check. - * ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter - * ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter - * - * @return The new state of ETHERNET DMA overflow Flag (SET or RESET). - */ -FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) -{ - FlagStatus bitstatus = RESET; - - if((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn ETH_GetRxOverflowMissedFrameCounter - * - * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. - * - * @return The value of Rx overflow Missed Frame Counter. - */ -uint32_t ETH_GetRxOverflowMissedFrameCounter(void) -{ - return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >> ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT)); -} - -/********************************************************************* - * @fn ETH_GetBufferUnavailableMissedFrameCounter - * - * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. - * - * @return The value of Buffer unavailable Missed Frame Counter. - */ -uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) -{ - return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); -} - -/********************************************************************* - * @fn ETH_GetCurrentTxDescStartAddress - * - * @brief Get the ETHERNET DMA DMACHTDR register value. - * - * @return The value of the current Tx desc start address. - */ -uint32_t ETH_GetCurrentTxDescStartAddress(void) -{ - return ((uint32_t)(ETH->DMACHTDR)); -} - -/********************************************************************* - * @fn ETH_GetCurrentRxDescStartAddress - * - * @brief Get the ETHERNET DMA DMACHRDR register value. - * - * @return The value of the current Rx desc start address. - */ -uint32_t ETH_GetCurrentRxDescStartAddress(void) -{ - return ((uint32_t)(ETH->DMACHRDR)); -} - -/********************************************************************* - * @fn ETH_GetCurrentTxBufferAddress - * - * @brief Get the ETHERNET DMA DMACHTBAR register value. - * - * @return The value of the current Tx buffer address. - */ -uint32_t ETH_GetCurrentTxBufferAddress(void) -{ - return (DMATxDescToSet->Buffer1Addr); -} - -/********************************************************************* - * @fn ETH_GetCurrentRxBufferAddress - * - * @brief Get the ETHERNET DMA DMACHRBAR register value. - * - * @return The value of the current Rx buffer address. - */ -uint32_t ETH_GetCurrentRxBufferAddress(void) -{ - return ((uint32_t)(ETH->DMACHRBAR)); -} - -/********************************************************************* - * @fn ETH_ResumeDMATransmission - * - * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register - * - * @return none - */ -void ETH_ResumeDMATransmission(void) -{ - ETH->DMATPDR = 0; -} - -/********************************************************************* - * @fn ETH_ResumeDMAReception - * - * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register. - * - * @return none - */ -void ETH_ResumeDMAReception(void) -{ - ETH->DMARPDR = 0; -} - -/********************************************************************* - * @fn ETH_ResetWakeUpFrameFilterRegisterPointer - * - * @brief Reset Wakeup frame filter register pointer. - * - * @return none - */ -void ETH_ResetWakeUpFrameFilterRegisterPointer(void) -{ - ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; -} - -/********************************************************************* - * @fn ETH_SetWakeUpFrameFilterRegister - * - * @brief Populates the remote wakeup frame registers. - * - * @param Buffer - Pointer on remote WakeUp Frame Filter Register buffer data (8 words). - * - * @return none - */ -void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) -{ - uint32_t i = 0; - - for(i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) - { - ETH->MACRWUFFR = Buffer[i]; - } -} - -/********************************************************************* - * @fn ETH_GlobalUnicastWakeUpCmd - * - * @brief Enables or disables any unicast packet filtered by the MAC address. - * - * @param NewState - new state of the MAC Global Unicast Wake-Up. - * - * @return none - */ -void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; - } - else - { - ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; - } -} - -/********************************************************************* - * @fn ETH_GetPMTFlagStatus - * - * @brief Checks whether the specified ETHERNET PMT flag is set or not. - * - * @param ETH_PMT_FLAG - specifies the flag to check. - * - * @return The new state of ETHERNET PMT Flag (SET or RESET). - */ -FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ETH_WakeUpFrameDetectionCmd - * - * @brief Enables or disables the MAC Wake-Up Frame Detection. - * - * @param NewState - new state of the MAC Wake-Up Frame Detection. - * - * @return none - */ -void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; - } - else - { - ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; - } -} - -/********************************************************************* - * @fn ETH_MagicPacketDetectionCmd - * - * @brief Enables or disables the MAC Magic Packet Detection. - * - * @param NewState - new state of the MAC Magic Packet Detection. - * - * @return none - */ -void ETH_MagicPacketDetectionCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; - } - else - { - ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; - } -} - -/********************************************************************* - * @fn ETH_PowerDownCmd - * - * @brief Enables or disables the MAC Power Down. - * - * @param NewState - new state of the MAC Power Down. - * - * @return none - */ -void ETH_PowerDownCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; - } - else - { - ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; - } -} - -/********************************************************************* - * @fn ETH_MMCCounterFreezeCmd - * - * @brief Enables or disables the MMC Counter Freeze. - * - * @param NewState - new state of the MMC Counter Freeze. - * - * @return none - */ -void ETH_MMCCounterFreezeCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->MMCCR |= ETH_MMCCR_MCF; - } - else - { - ETH->MMCCR &= ~ETH_MMCCR_MCF; - } -} - -/********************************************************************* - * @fn ETH_MMCResetOnReadCmd - * - * @brief Enables or disables the MMC Reset On Read. - * - * @param NewState - new state of the MMC Reset On Read. - * - * @return none - */ -void ETH_MMCResetOnReadCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->MMCCR |= ETH_MMCCR_ROR; - } - else - { - ETH->MMCCR &= ~ETH_MMCCR_ROR; - } -} - -/********************************************************************* - * @fn ETH_MMCCounterRolloverCmd - * - * @brief Enables or disables the MMC Counter Stop Rollover. - * - * @param NewState - new state of the MMC Counter Stop Rollover. - * - * @return none - */ -void ETH_MMCCounterRolloverCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->MMCCR &= ~ETH_MMCCR_CSR; - } - else - { - ETH->MMCCR |= ETH_MMCCR_CSR; - } -} - -/********************************************************************* - * @fn ETH_MMCCountersReset - * - * @brief Resets the MMC Counters. - * - * @return none - */ -void ETH_MMCCountersReset(void) -{ - ETH->MMCCR |= ETH_MMCCR_CR; -} - -/********************************************************************* - * @fn ETH_MMCITConfig - * - * @brief Enables or disables the specified ETHERNET MMC interrupts. - * - * @param ETH_MMC_IT - specifies the ETHERNET MMC interrupt. - * ETH_MMC_IT_TGF - When Tx good frame counter reaches half the maximum value. - * ETH_MMC_IT_TGFMSC - When Tx good multi col counter reaches half the maximum value. - * ETH_MMC_IT_TGFSC - When Tx good single col counter reaches half the maximum value. - * ETH_MMC_IT_RGUF - When Rx good unicast frames counter reaches half the maximum value. - * ETH_MMC_IT_RFAE - When Rx alignment error counter reaches half the maximum value. - * ETH_MMC_IT_RFCE - When Rx crc error counter reaches half the maximum value. - * NewState - new state of the specified ETHERNET MMC interrupts. - * - * @return none - */ -void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) -{ - if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) - { - ETH_MMC_IT &= 0xEFFFFFFF; - - if(NewState != DISABLE) - { - ETH->MMCRIMR &= (~(uint32_t)ETH_MMC_IT); - } - else - { - ETH->MMCRIMR |= ETH_MMC_IT; - } - } - else - { - if(NewState != DISABLE) - { - ETH->MMCTIMR &= (~(uint32_t)ETH_MMC_IT); - } - else - { - ETH->MMCTIMR |= ETH_MMC_IT; - } - } -} - -/********************************************************************* - * @fn ETH_GetMMCITStatus - * - * @brief Checks whether the specified ETHERNET MMC IT is set or not. - * - * @param ETH_MMC_IT - specifies the ETHERNET MMC interrupt. - * ETH_MMC_IT_TxFCGC - When Tx good frame counter reaches half the maximum value. - * ETH_MMC_IT_TxMCGC - When Tx good multi col counter reaches half the maximum value. - * ETH_MMC_IT_TxSCGC - When Tx good single col counter reaches half the maximum value . - * ETH_MMC_IT_RxUGFC - When Rx good unicast frames counter reaches half the maximum value. - * ETH_MMC_IT_RxAEC - When Rx alignment error counter reaches half the maximum value. - * ETH_MMC_IT_RxCEC - When Rx crc error counter reaches half the maximum value. - * - * @return The value of ETHERNET MMC IT (SET or RESET). - */ -ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) -{ - ITStatus bitstatus = RESET; - - if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) - { - if((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - - return bitstatus; -} - -/********************************************************************* - * @fn ETH_GetMMCRegister - * - * @brief Get the specified ETHERNET MMC register value. - * - * @param ETH_MMCReg - specifies the ETHERNET MMC register. - * ETH_MMCCR - MMC CR register - * ETH_MMCRIR - MMC RIR register - * ETH_MMCTIR - MMC TIR register - * ETH_MMCRIMR - MMC RIMR register - * ETH_MMCTIMR - MMC TIMR register - * ETH_MMCTGFSCCR - MMC TGFSCCR register - * ETH_MMCTGFMSCCR - MMC TGFMSCCR register - * ETH_MMCTGFCR - MMC TGFCR register - * ETH_MMCRFCECR - MMC RFCECR register - * ETH_MMCRFAECR - MMC RFAECR register - * ETH_MMCRGUFCR - MMC RGUFCRregister - * - * @return The value of ETHERNET MMC Register value. - */ -uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) -{ - return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); -} - -/********************************************************************* - * @fn ETH_EnablePTPTimeStampAddend - * - * @brief Updated the PTP block for fine correction with the Time Stamp Addend register value. - * - * @return none - */ -void ETH_EnablePTPTimeStampAddend(void) -{ - ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; -} - -/********************************************************************* - * @fn ETH_EnablePTPTimeStampInterruptTrigger - * - * @brief Enable the PTP Time Stamp interrupt trigger - * - * @return none - */ -void ETH_EnablePTPTimeStampInterruptTrigger(void) -{ - ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; -} - -/********************************************************************* - * @fn ETH_EnablePTPTimeStampUpdate - * - * @brief Updated the PTP system time with the Time Stamp Update register value. - * - * @return none - */ -void ETH_EnablePTPTimeStampUpdate(void) -{ - ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; -} - -/********************************************************************* - * @fn ETH_InitializePTPTimeStamp - * - * @brief Initialize the PTP Time Stamp. - * - * @return none - */ -void ETH_InitializePTPTimeStamp(void) -{ - ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; -} - -/********************************************************************* - * @fn ETH_PTPUpdateMethodConfig - * - * @brief Selects the PTP Update method. - * - * @param UpdateMethod - the PTP Update method. - * - * @return none - */ -void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) -{ - if(UpdateMethod != ETH_PTP_CoarseUpdate) - { - ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU; - } - else - { - ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); - } -} - -/********************************************************************* - * @fn ETH_PTPTimeStampCmd - * - * @brief Enables or disables the PTP time stamp for transmit and receive frames. - * - * @param NewState - new state of the PTP time stamp for transmit and receive frames. - * - * @return none - */ -void ETH_PTPTimeStampCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ETH->PTPTSCR |= ETH_PTPTSCR_TSE; - } - else - { - ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE); - } -} - -/********************************************************************* - * @fn ETH_GetPTPFlagStatus - * - * @brief Checks whether the specified ETHERNET PTP flag is set or not. - * - * @param The new state of ETHERNET PTP Flag (SET or RESET). - * - * @return none - */ -FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn ETH_SetPTPSubSecondIncrement - * - * @brief Sets the system time Sub-Second Increment value. - * - * @param SubSecondValue - specifies the PTP Sub-Second Increment Register value. - * - * @return none - */ -void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) -{ - ETH->PTPSSIR = SubSecondValue; -} - -/********************************************************************* - * @fn ETH_SetPTPTimeStampUpdate - * - * @brief Sets the Time Stamp update sign and values. - * - * @param Sign - specifies the PTP Time update value sign. - * SecondValue - specifies the PTP Time update second value. - * SubSecondValue - specifies the PTP Time update sub-second value. - * - * @return none - */ -void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) -{ - ETH->PTPTSHUR = SecondValue; - ETH->PTPTSLUR = Sign | SubSecondValue; -} - -/********************************************************************* - * @fn ETH_SetPTPTimeStampAddend - * - * @brief Sets the Time Stamp Addend value. - * - * @param Value - specifies the PTP Time Stamp Addend Register value. - * - * @return none - */ -void ETH_SetPTPTimeStampAddend(uint32_t Value) -{ - /* Set the PTP Time Stamp Addend Register */ - ETH->PTPTSAR = Value; -} - -/********************************************************************* - * @fn ETH_SetPTPTargetTime - * - * @brief Sets the Target Time registers values. - * - * @param HighValue - specifies the PTP Target Time High Register value. - * LowValue - specifies the PTP Target Time Low Register value. - * - * @return none - */ -void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) -{ - ETH->PTPTTHR = HighValue; - ETH->PTPTTLR = LowValue; -} - -/********************************************************************* - * @fn ETH_GetPTPRegister - * - * @brief Get the specified ETHERNET PTP register value. - * - * @param ETH_PTPReg - specifies the ETHERNET PTP register. - * ETH_PTPTSCR - Sub-Second Increment Register - * ETH_PTPSSIR - Sub-Second Increment Register - * ETH_PTPTSHR - Time Stamp High Register - * ETH_PTPTSLR - Time Stamp Low Register - * ETH_PTPTSHUR - Time Stamp High Update Register - * ETH_PTPTSLUR - Time Stamp Low Update Register - * ETH_PTPTSAR - Time Stamp Addend Register - * ETH_PTPTTHR - Target Time High Register - * ETH_PTPTTLR - Target Time Low Register - * - * @return The value of ETHERNET PTP Register value. - */ -uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) -{ - return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); -} - -/********************************************************************* - * @fn ETH_DMAPTPTxDescChainInit - * - * @brief Initializes the DMA Tx descriptors in chain mode with PTP. - * - * @param DMATxDescTab - Pointer on the first Tx desc list. - * DMAPTPTxDescTab - Pointer on the first PTP Tx desc list. - * TxBuff - Pointer on the first TxBuffer list. - * TxBuffCount - Number of the used Tx desc in the list. - * - * @return none. - */ -void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, - uint8_t *TxBuff, uint32_t TxBuffCount) -{ - uint32_t i = 0; - ETH_DMADESCTypeDef *DMATxDesc; - - DMATxDescToSet = DMATxDescTab; - DMAPTPTxDescToSet = DMAPTPTxDescTab; - - for(i = 0; i < TxBuffCount; i++) - { - DMATxDesc = DMATxDescTab + i; - DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; - DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); - - if(i < (TxBuffCount - 1)) - { - DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); - } - else - { - DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab; - } - - (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr; - (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; - } - - (&DMAPTPTxDescTab[i - 1])->Status = (uint32_t)DMAPTPTxDescTab; - - ETH->DMATDLAR = (uint32_t)DMATxDescTab; -} - -/********************************************************************* - * @fn ETH_DMAPTPRxDescChainInit - * - * @brief Initializes the DMA Rx descriptors in chain mode. - * - * @param DMARxDescTab - Pointer on the first Rx desc list. - * DMAPTPRxDescTab - Pointer on the first PTP Rx desc list. - * RxBuff - Pointer on the first RxBuffer list. - * RxBuffCount - Number of the used Rx desc in the list. - * - * @return none. - */ -void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, - uint8_t *RxBuff, uint32_t RxBuffCount) -{ - uint32_t i = 0; - ETH_DMADESCTypeDef *DMARxDesc; - - DMARxDescToGet = DMARxDescTab; - DMAPTPRxDescToGet = DMAPTPRxDescTab; - - for(i = 0; i < RxBuffCount; i++) - { - DMARxDesc = DMARxDescTab + i; - DMARxDesc->Status = ETH_DMARxDesc_OWN; - DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); - - if(i < (RxBuffCount - 1)) - { - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); - } - else - { - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); - } - - (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr; - (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; - } - - (&DMAPTPRxDescTab[i - 1])->Status = (uint32_t)DMAPTPRxDescTab; - ETH->DMARDLAR = (uint32_t)DMARxDescTab; -} - -/********************************************************************* - * @fn ETH_HandlePTPTxPkt - * - * @brief Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values. - * - * @param ppkt - pointer to application packet buffer to transmit. - * FrameLength - Tx Packet size. - * PTPTxTab - Pointer on the first PTP Tx table to store Time stamp values. - * - * @return none. - */ -uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) -{ - uint32_t offset = 0, timeout = 0; - - if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) - { - return ETH_ERROR; - } - - for(offset = 0; offset < FrameLength; offset++) - { - (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset)); - } - - DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF); - DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; - DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; - - if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) - { - ETH->DMASR = ETH_DMASR_TBUS; - ETH->DMATPDR = 0; - } - - do - { - timeout++; - } while(!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); - - if(timeout == PHY_READ_TO) - { - return ETH_ERROR; - } - - DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; - *PTPTxTab++ = DMATxDescToSet->Buffer1Addr; - *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr; - - if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) - { - DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Buffer2NextDescAddr); - if(DMAPTPTxDescToSet->Status != 0) - { - DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Status); - } - else - { - DMAPTPTxDescToSet++; - } - } - else - { - if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) - { - DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); - DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); - } - else - { - DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); - DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); - } - } - - return ETH_SUCCESS; -} - -/********************************************************************* - * @fn ETH_HandlePTPRxPkt - * - * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values. - * - * @param ppkt - pointer to application packet receive buffer. - * PTPRxTab - Pointer on the first PTP Rx table to store Time stamp values. - * - * @return ETH_ERROR - if there is error in reception. - * framelength - received packet size if packet reception is correct. - */ -uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) -{ - uint32_t offset = 0, framelength = 0; - - if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) - { - return ETH_ERROR; - } - if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) - { - framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; - - for(offset = 0; offset < framelength; offset++) - { - (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset)); - } - } - else - { - framelength = ETH_ERROR; - } - - if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) - { - ETH->DMASR = ETH_DMASR_RBUS; - ETH->DMARPDR = 0; - } - - *PTPRxTab++ = DMARxDescToGet->Buffer1Addr; - *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr; - DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; - - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) - { - DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Buffer2NextDescAddr); - if(DMAPTPRxDescToGet->Status != 0) - { - DMAPTPRxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Status); - } - else - { - DMAPTPRxDescToGet++; - } - } - else - { - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) - { - DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); - } - else - { - DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); - } - } - - return (framelength); -} - -/********************************************************************* - * @fn RGMII_TXC_Delay - * - * @brief Delay time. - * - * @return none - */ -void RGMII_TXC_Delay(uint8_t clock_polarity, uint8_t delay_time) -{ - if(clock_polarity) - { - ETH->MACCR |= (uint32_t)(1 << 1); - } - else - { - ETH->MACCR &= ~(uint32_t)(1 << 1); - } - if(delay_time <= 7) - { - ETH->MACCR |= (uint32_t)(delay_time << 29); - } -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_eth.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the ETH firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_eth.h" +#include "ch32v30x_rcc.h" + +ETH_DMADESCTypeDef *DMATxDescToSet; +ETH_DMADESCTypeDef *DMARxDescToGet; +ETH_DMADESCTypeDef *DMAPTPTxDescToSet; +ETH_DMADESCTypeDef *DMAPTPRxDescToGet; + +/********************************************************************* + * @fn ETH_DeInit + * + * @brief ETH hardware initialize again. + * + * @return none + */ +#ifdef CH32V30x_D8C +void ETH_DeInit(void) +{ + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE); +} + +#endif + +/********************************************************************* + * @fn ETH_StructInit + * + * @brief Fills each ETH_InitStruct member with its default value. + * + * @param ETH_InitStruct - pointer to a ETH_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void ETH_StructInit(ETH_InitTypeDef *ETH_InitStruct) +{ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; + ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; + ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + /*------------------------ DMA -----------------------------------*/ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; + ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; + ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; + ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; + ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; +} + +/********************************************************************* + * @fn ETH_Start + * + * @brief Enables ENET MAC and DMA reception/transmission. + * + * @return none + */ +void ETH_Start(void) +{ + ETH_MACTransmissionCmd(ENABLE); + ETH_FlushTransmitFIFO(); + ETH_MACReceptionCmd(ENABLE); + ETH_DMATransmissionCmd(ENABLE); + ETH_DMAReceptionCmd(ENABLE); +} + +/********************************************************************* + * @fn ETH_HandleTxPkt + * + * @brief Transmits a packet, from application buffer, pointed by ppkt. + * + * @param ppkt - pointer to the application's packet buffer to transmit. + * FrameLength - Tx Packet size. + * + * @return ETH_ERROR - in case of Tx desc owned by DMA. + * ETH_SUCCESS - for correct transmission. + */ +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) +{ + uint32_t offset = 0; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + for(offset = 0; offset < FrameLength; offset++) + { + (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset)); + } + + DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_TBUS; + ETH->DMATPDR = 0; + } + + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr); + } + else + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + } + else + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_HandleRxPkt + * + * @brief Receives a packet and copies it to memory pointed by ppkt. + * + * @param ppkt - pointer to the application packet receive buffer. + * + * @return ETH_ERROR - if there is error in reception + * framelength - received packet size if packet reception is correct + */ +uint32_t ETH_HandleRxPkt(uint8_t *ppkt) +{ + uint32_t offset = 0, framelength = 0; + + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + for(offset = 0; offset < framelength; offset++) + { + (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset)); + } + } + else + { + framelength = ETH_ERROR; + } + + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_RBUS; + ETH->DMARPDR = 0; + } + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr); + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return (framelength); +} + +/********************************************************************* + * @fn ETH_GetRxPktSize + * + * @brief Get the size of received the received packet. + * + * @return framelength - received packet size + */ +uint32_t ETH_GetRxPktSize(void) +{ + uint32_t frameLength = 0; + if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); + } + + return frameLength; +} + +/********************************************************************* + * @fn ETH_DropRxPkt + * + * @brief Drop a Received packet. + * + * @return none + */ +void ETH_DropRxPkt(void) +{ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr); + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } +} + +/********************************************************************* + * @fn ETH_ReadPHYRegister + * + * @brief Read a PHY register. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * PHYReg - PHY register address, is the index of one of the 32 PHY register. + * + * @return ETH_ERROR - in case of timeout. + * MAC MIIDR register value - Data read from the selected PHY register. + */ +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + + tmpreg = ETH->MACMIIAR; + tmpreg &= ~MACMIIAR_CR_MASK; + tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA); + tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR); + tmpreg &= ~ETH_MACMIIAR_MW; + tmpreg |= ETH_MACMIIAR_MB; + ETH->MACMIIAR = tmpreg; + + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); + + if(timeout == PHY_READ_TO) + { + return (uint16_t)ETH_ERROR; + } + + return (uint16_t)(ETH->MACMIIDR); +} + +/********************************************************************* + * @fn ETH_WritePHYRegister + * + * @brief Write to a PHY register. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * PHYReg - PHY register address, is the index of one of the 32 PHY register. + * PHYValue - the value to write. + * + * @return ETH_ERROR - in case of timeout. + * ETH_SUCCESS - for correct write + */ +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + + tmpreg = ETH->MACMIIAR; + tmpreg &= ~MACMIIAR_CR_MASK; + tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA); + tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR); + tmpreg |= ETH_MACMIIAR_MW; + tmpreg |= ETH_MACMIIAR_MB; + ETH->MACMIIDR = PHYValue; + ETH->MACMIIAR = tmpreg; + + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); + + if(timeout >= PHY_WRITE_TO) + { + return ETH_ERROR; + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_PHYLoopBackCmd + * + * @brief Enables or disables the PHY loopBack mode. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * NewState - new state of the PHY loopBack mode. + * + * @return ETH_ERROR - in case of bad PHY configuration. + * ETH_SUCCESS - for correct PHY configuration. + */ +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) +{ + uint16_t tmpreg = 0; + + tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + + if(NewState != DISABLE) + { + tmpreg |= PHY_Loopback; + } + else + { + tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); + } + + if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) + { + return ETH_SUCCESS; + } + else + { + return ETH_ERROR; + } +} + +/********************************************************************* + * @fn ETH_MACTransmissionCmd + * + * @brief Enables or disables the MAC transmission. + * + * @param NewState - new state of the MAC transmission. + * + * @return none + */ +void ETH_MACTransmissionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACCR |= ETH_MACCR_TE; + } + else + { + ETH->MACCR &= ~ETH_MACCR_TE; + } +} + +/********************************************************************* + * @fn ETH_MACReceptionCmd + * + * @brief Enables or disables the MAC reception. + * + * @param NewState - new state of the MAC reception. + * + * @return none + */ +void ETH_MACReceptionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACCR |= ETH_MACCR_RE; + } + else + { + ETH->MACCR &= ~ETH_MACCR_RE; + } +} + +/********************************************************************* + * @fn ETH_GetFlowControlBusyStatus + * + * @brief Enables or disables the MAC reception. + * + * @return The new state of flow control busy status bit (SET or RESET). + */ +FlagStatus ETH_GetFlowControlBusyStatus(void) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_InitiatePauseControlFrame + * + * @brief Initiate a Pause Control Frame (Full-duplex only). + * + * @return none + */ +void ETH_InitiatePauseControlFrame(void) +{ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; +} + +/********************************************************************* + * @fn ETH_BackPressureActivationCmd + * + * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). + * + * @param NewState - new state of the MAC BackPressure operation activation. + * + * @return none + */ +void ETH_BackPressureActivationCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACFCR |= ETH_MACFCR_FCBBPA; + } + else + { + ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; + } +} + +/********************************************************************* + * @fn ETH_GetMACFlagStatus + * + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * + * @param ETH_MAC_FLAG - specifies the flag to check. + * + * @return The new state of ETHERNET MAC flag (SET or RESET). + */ +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetMACITStatus + * + * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. + * + * @param ETH_MAC_IT - specifies the interrupt source to check. + * + * @return The new state of ETHERNET MAC interrupt (SET or RESET). + */ +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_MACITConfig + * + * @brief Enables or disables the specified ETHERNET MAC interrupts. + * + * @param ETH_MAC_IT - specifies the interrupt source to check. + * NewState - new state of the specified ETHERNET MAC interrupts. + * + * @return none + */ +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); + } + else + { + ETH->MACIMR |= ETH_MAC_IT; + } +} + +/********************************************************************* + * @fn ETH_MACAddressConfig + * + * @brief Configures the selected MAC address. + * + * @param MacAddr - The MAC addres to configure. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Addr - Pointer on MAC address buffer data (6 bytes). + * + * @return none + */ +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + + tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; + tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; + + (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg; +} + +/********************************************************************* + * @fn ETH_GetMACAddress + * + * @brief Get the selected MAC address. + * + * @param MacAddr - The MAC address to return. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Addr - Pointer on MAC address buffer data (6 bytes). + * + * @return none + */ +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + + tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)); + + Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[4] = (tmpreg & (uint8_t)0xFF); + tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr)); + Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); + Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); + Addr[1] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[0] = (tmpreg & (uint8_t)0xFF); +} + +/********************************************************************* + * @fn ETH_MACAddressPerfectFilterCmd + * + * @brief Enables or disables the Address filter module uses the specified. + * + * @param MacAddr - The MAC address to return. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * NewState - new state of the specified ETHERNET MAC address use. + * + * @return none + */ +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE; + } + else + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_AE); + } +} + +/********************************************************************* + * @fn ETH_MACAddressFilterConfig + * + * @brief Set the filter type for the specified ETHERNET MAC address. + * + * @param MacAddr - specifies the ETHERNET MAC address. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Filter - specifies the used frame received field for comparaison. + * ETH_MAC_AddressFilter_SA - MAC Address is used to compare with the + * SA fields of the received frame. + * ETH_MAC_AddressFilter_DA - MAC Address is used to compare with the + * DA fields of the received frame. + * + * @return none + */ +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) +{ + if(Filter != ETH_MAC_AddressFilter_DA) + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA; + } + else + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_SA); + } +} + +/********************************************************************* + * @fn ETH_MACAddressMaskBytesFilterConfig + * + * @brief Set the filter type for the specified ETHERNET MAC address. + * + * @param MacAddr - specifies the ETHERNET MAC address. + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * MaskByte - specifies the used address bytes for comparaison + * ETH_MAC_AddressMask_Byte5 - Mask MAC Address high reg bits [7:0]. + * ETH_MAC_AddressMask_Byte4 - Mask MAC Address low reg bits [31:24]. + * ETH_MAC_AddressMask_Byte3 - Mask MAC Address low reg bits [23:16]. + * ETH_MAC_AddressMask_Byte2 - Mask MAC Address low reg bits [15:8]. + * ETH_MAC_AddressMask_Byte1 - Mask MAC Address low reg bits [7:0]. + * + * @return none + */ +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) +{ + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_MBC); + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte; +} + +/********************************************************************* + * @fn ETH_DMATxDescChainInit + * + * @brief Initializes the DMA Tx descriptors in chain mode. + * + * @param DMATxDescTab - Pointer on the first Tx desc list + * TxBuff - Pointer on the first TxBuffer list + * TxBuffCount - Number of the used Tx desc in the list + * + * @return none + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (TxBuffCount - 1)) + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab; + } + } + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_DMATxDescRingInit + * + * @brief Initializes the DMA Tx descriptors in ring mode. + * + * @param DMATxDescTab - Pointer on the first Tx desc list. + * TxBuff1 - Pointer on the first TxBuffer1 list. + * TxBuff2 - Pointer on the first TxBuffer2 list. + * TxBuffCount - Number of the used Tx desc in the list. + * + * @return none + */ +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i * ETH_MAX_PACKET_SIZE]); + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i * ETH_MAX_PACKET_SIZE]); + + if(i == (TxBuffCount - 1)) + { + DMATxDesc->Status = ETH_DMATxDesc_TER; + } + } + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_GetDMATxDescFlagStatus + * + * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * ETH_DMATxDescFlag - specifies the flag to check. + * ETH_DMATxDesc_OWN - OWN bit - descriptor is owned by DMA engine + * ETH_DMATxDesc_IC - Interrupt on completetion + * ETH_DMATxDesc_LS - Last Segment + * ETH_DMATxDesc_FS - First Segment + * ETH_DMATxDesc_DC - Disable CRC + * ETH_DMATxDesc_DP - Disable Pad + * ETH_DMATxDesc_TTSE - Transmit Time Stamp Enable + * ETH_DMATxDesc_TER - Transmit End of Ring + * ETH_DMATxDesc_TCH - Second Address Chained + * ETH_DMATxDesc_TTSS - Tx Time Stamp Status + * ETH_DMATxDesc_IHE - IP Header Error + * ETH_DMATxDesc_ES - Error summary + * ETH_DMATxDesc_JT - Jabber Timeout + * ETH_DMATxDesc_FF - Frame Flushed - DMA/MTL flushed the frame due to SW flush + * ETH_DMATxDesc_PCE - Payload Checksum Error + * ETH_DMATxDesc_LCA - Loss of Carrier - carrier lost during tramsmission + * ETH_DMATxDesc_NC - No Carrier - no carrier signal from the tranceiver + * ETH_DMATxDesc_LCO - Late Collision - transmission aborted due to collision + * ETH_DMATxDesc_EC - Excessive Collision - transmission aborted after 16 collisions + * ETH_DMATxDesc_VF - VLAN Frame + * ETH_DMATxDesc_CC - Collision Count + * ETH_DMATxDesc_ED - Excessive Deferral + * ETH_DMATxDesc_UF - Underflow Error - late data arrival from the memory + * ETH_DMATxDesc_DB - Deferred Bit + * + * @return The new state of ETH_DMATxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) +{ + FlagStatus bitstatus = RESET; + + if((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetDMATxDescCollisionCount + * + * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * + * @param pointer on a DMA Tx descriptor. + * + * @return The Transmit descriptor collision counter value. + */ +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) +{ + return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); +} + +/********************************************************************* + * @fn ETH_SetDMATxDescOwnBit + * + * @brief Set the specified DMA Tx Desc Own bit. + * + * @param DMATxDesc - Pointer on a Tx desc + * + * @return none + */ +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATxDesc_OWN; +} + +/********************************************************************* + * @fn ETH_DMATxDescTransmitITConfig + * + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * + * @param Pointer on a Tx desc. + * NewState - new state of the DMA Tx Desc transmit interrupt. + * + * @return none + */ +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_IC; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_IC); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescFrameSegmentConfig + * + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * + * @param PDMATxDesc - Pointer on a Tx desc. + * ETH_DMATxDesc_FirstSegment - actual Tx desc contain first segment. + * + * @return none + */ +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) +{ + DMATxDesc->Status |= DMATxDesc_FrameSegment; +} + +/********************************************************************* + * @fn ETH_DMATxDescChecksumInsertionConfig + * + * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * DMATxDesc_Checksum - specifies is the DMA Tx desc checksum insertion. + * + * @return none + */ +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) +{ + DMATxDesc->Status |= DMATxDesc_Checksum; +} + +/********************************************************************* + * @fn ETH_DMATxDescCRCCmd + * + * @brief Enables or disables the DMA Tx Desc CRC. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc CRC. + * + * @return none + */ +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); + } + else + { + DMATxDesc->Status |= ETH_DMATxDesc_DC; + } +} + +/********************************************************************* + * @fn ETH_DMATxDescEndOfRingCmd + * + * @brief Enables or disables the DMA Tx Desc end of ring. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * NewState - new state of the specified DMA Tx Desc end of ring. + * + * @return none + */ +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TER; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescSecondAddressChainedCmd + * + * @brief Enables or disables the DMA Tx Desc second address chained. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc second address chained. + * + * @return none + */ +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TCH; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TCH); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescShortFramePaddingCmd + * + * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * NewState - new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @return none + */ +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); + } + else + { + DMATxDesc->Status |= ETH_DMATxDesc_DP; + } +} + +/********************************************************************* + * @fn ETH_DMATxDescTimeStampCmd + * + * @brief Enables or disables the DMA Tx Desc time stamp. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc time stamp. + * + * @return none + */ +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TTSE; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TTSE); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescBufferSizeConfig + * + * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. + * + * @param DMATxDesc - Pointer on a Tx desc. + * BufferSize1 - specifies the Tx desc buffer1 size. + * RxBuff2 - Pointer on the first RxBuffer2 list + * BufferSize2 - specifies the Tx desc buffer2 size (put "0" if not used). + * + * @return none + */ +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) +{ + DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); +} + +/********************************************************************* + * @fn ETH_DMARxDescChainInit + * + * @brief Initializes the DMA Rx descriptors in chain mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * RxBuff - Pointer on the first RxBuffer list. + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none + */ +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (RxBuffCount - 1)) + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_DMARxDescRingInit + * + * @brief Initializes the DMA Rx descriptors in ring mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * RxBuff1 - Pointer on the first RxBuffer1 list. + * RxBuff2 - Pointer on the first RxBuffer2 list + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none + */ +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i * ETH_MAX_PACKET_SIZE]); + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i * ETH_MAX_PACKET_SIZE]); + + if(i == (RxBuffCount - 1)) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + } + + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_GetDMARxDescFlagStatus + * + * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * ETH_DMARxDescFlag - specifies the flag to check. + * ETH_DMARxDesc_OWN - OWN bit: descriptor is owned by DMA engine + * ETH_DMARxDesc_AFM - DA Filter Fail for the rx frame + * ETH_DMARxDesc_ES - Error summary + * ETH_DMARxDesc_DE - Desciptor error: no more descriptors for receive frame + * ETH_DMARxDesc_SAF - SA Filter Fail for the received frame + * ETH_DMARxDesc_LE - Frame size not matching with length field + * ETH_DMARxDesc_OE - Overflow Error: Frame was damaged due to buffer overflow + * ETH_DMARxDesc_VLAN - VLAN Tag: received frame is a VLAN frame + * ETH_DMARxDesc_FS - First descriptor of the frame + * ETH_DMARxDesc_LS - Last descriptor of the frame + * ETH_DMARxDesc_IPV4HCE - IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * ETH_DMARxDesc_LC - Late collision occurred during reception + * ETH_DMARxDesc_FT - Frame type - Ethernet, otherwise 802.3 + * ETH_DMARxDesc_RWT - Receive Watchdog Timeout: watchdog timer expired during reception + * ETH_DMARxDesc_RE - Receive error: error reported by MII interface + * ETH_DMARxDesc_DE - Dribble bit error: frame contains non int multiple of 8 bits + * ETH_DMARxDesc_CE - CRC error + * ETH_DMARxDesc_MAMPCE - Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + * + * @return The new state of ETH_DMARxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) +{ + FlagStatus bitstatus = RESET; + + if((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_SetDMARxDescOwnBit + * + * @brief Set the specified DMA Rx Desc Own bit. + * + * @param DMARxDesc - Pointer on a Rx desc + * + * @return none + */ +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) +{ + DMARxDesc->Status |= ETH_DMARxDesc_OWN; +} + +/********************************************************************* + * @fn ETH_GetDMARxDescFrameLength + * + * @brief Returns the specified DMA Rx Desc frame length. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor + * + * @return The Rx descriptor received frame length. + */ +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) +{ + return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); +} + +/********************************************************************* + * @fn ETH_DMARxDescReceiveITConfig + * + * @brief Enables or disables the specified DMA Rx Desc receive interrupt. + * + * @param DMARxDesc - Pointer on a Rx desc + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_DIC); + } + else + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; + } +} + +/********************************************************************* + * @fn ETH_DMARxDescEndOfRingCmd + * + * @brief Enables or disables the DMA Rx Desc end of ring. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * NewState - new state of the specified DMA Rx Desc end of ring. + * + * @return none + */ +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + else + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RER); + } +} + +/********************************************************************* + * @fn ETH_DMARxDescSecondAddressChainedCmd + * + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * NewState - new state of the specified DMA Rx Desc second address chained. + * + * @return none + */ +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; + } + else + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RCH); + } +} + +/********************************************************************* + * @fn ETH_GetDMARxDescBufferSize + * + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * DMARxDesc_Buffer - specifies the DMA Rx Desc buffer. + * ETH_DMARxDesc_Buffer1 - DMA Rx Desc Buffer1 + * ETH_DMARxDesc_Buffer2 - DMA Rx Desc Buffer2 + * + * @return The Receive descriptor frame length. + */ +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) +{ + if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) + { + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); + } + else + { + return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); + } +} + +/********************************************************************* + * @fn ETH_SoftwareReset + * + * @brief Resets all MAC subsystem internal registers and logic. + * + * @return none + */ +void ETH_SoftwareReset(void) +{ + ETH->DMABMR |= ETH_DMABMR_SR; +} + +/********************************************************************* + * @fn ETH_GetSoftwareResetStatus + * + * @brief Checks whether the ETHERNET software reset bit is set or not. + * + * @return The new state of DMA Bus Mode register SR bit (SET or RESET). + */ +FlagStatus ETH_GetSoftwareResetStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetlinkStaus + * + * @brief Checks whether the internal 10BASE-T PHY is link or not. + * + * @return Internal 10BASE-T PHY is link or not. + */ +FlagStatus ETH_GetlinkStaus(void) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMASR & 0x80000000) != (uint32_t)RESET) + { + bitstatus = PHY_10BASE_T_LINKED; + } + else + { + bitstatus = PHY_10BASE_T_NOT_LINKED; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetDMAFlagStatus + * + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * + * @param ETH_DMA_FLAG - specifies the flag to check. + * ETH_DMA_FLAG_TST - Time-stamp trigger flag + * ETH_DMA_FLAG_PMT - PMT flag + * ETH_DMA_FLAG_MMC - MMC flag + * ETH_DMA_FLAG_DataTransferError - Error bits 0-data buffer, 1-desc. access + * ETH_DMA_FLAG_ReadWriteError - Error bits 0-write trnsf, 1-read transfr + * ETH_DMA_FLAG_AccessError - Error bits 0-Rx DMA, 1-Tx DMA + * ETH_DMA_FLAG_NIS - Normal interrupt summary flag + * ETH_DMA_FLAG_AIS - Abnormal interrupt summary flag + * ETH_DMA_FLAG_ER - Early receive flag + * ETH_DMA_FLAG_FBE - Fatal bus error flag + * ETH_DMA_FLAG_ET - Early transmit flag + * ETH_DMA_FLAG_RWT - Receive watchdog timeout flag + * ETH_DMA_FLAG_RPS - Receive process stopped flag + * ETH_DMA_FLAG_RBU - Receive buffer unavailable flag + * ETH_DMA_FLAG_R - Receive flag + * ETH_DMA_FLAG_TU - Underflow flag + * ETH_DMA_FLAG_RO - Overflow flag + * ETH_DMA_FLAG_TJT - Transmit jabber timeout flag + * ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag + * ETH_DMA_FLAG_TPS - Transmit process stopped flag + * ETH_DMA_FLAG_T - Transmit flag + * + * @return Internal 10BASE-T PHY is link or not. + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMAClearFlag + * + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * + * @param ETH_DMA_FLAG - specifies the flag to clear. + * ETH_DMA_FLAG_NIS - Normal interrupt summary flag + * ETH_DMA_FLAG_AIS - Abnormal interrupt summary flag + * ETH_DMA_FLAG_ER - Early receive flag + * ETH_DMA_FLAG_FBE - Fatal bus error flag + * ETH_DMA_FLAG_ETI - Early transmit flag + * ETH_DMA_FLAG_RWT - Receive watchdog timeout flag + * ETH_DMA_FLAG_RPS - Receive process stopped flag + * ETH_DMA_FLAG_RBU - Receive buffer unavailable flag + * ETH_DMA_FLAG_R - Receive flag + * ETH_DMA_FLAG_TU - Transmit Underflow flag + * ETH_DMA_FLAG_RO - Receive Overflow flag + * ETH_DMA_FLAG_TJT - Transmit jabber timeout flag + * ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag + * ETH_DMA_FLAG_TPS - Transmit process stopped flag + * ETH_DMA_FLAG_T - Transmit flag + * + * @return none + */ +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) +{ + ETH->DMASR = (uint32_t)ETH_DMA_FLAG; +} + +/********************************************************************* + * @fn ETH_GetDMAITStatus + * + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * + * @param ETH_DMA_IT - specifies the interrupt pending bit to clear. + * ETH_DMA_IT_TST - Time-stamp trigger interrupt + * ETH_DMA_IT_PMT - PMT interrupt + * ETH_DMA_IT_MMC - MMC interrupt + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ET - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Underflow interrupt + * ETH_DMA_IT_RO - Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * + * @return The new state of ETH_DMA_IT (SET or RESET). + */ +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) +{ + ITStatus bitstatus = RESET; + + if((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMAClearITPendingBit + * + * @brief Clears the ETHERNET"s DMA IT pending bit. + * + * @param ETH_DMA_IT - specifies the interrupt pending bit to clear. + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ETI - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Transmit Underflow interrupt + * ETH_DMA_IT_RO - Receive Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * + * @return none + */ +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) +{ + ETH->DMASR = (uint32_t)ETH_DMA_IT; +} + +/********************************************************************* + * @fn ETH_GetTransmitProcessState + * + * @brief Returns the ETHERNET DMA Transmit Process State. + * + * @return The new ETHERNET DMA Transmit Process State - + * ETH_DMA_TransmitProcess_Stopped - Stopped - Reset or Stop Tx Command issued + * ETH_DMA_TransmitProcess_Fetching - Running - fetching the Tx descriptor + * ETH_DMA_TransmitProcess_Waiting - Running - waiting for status + * ETH_DMA_TransmitProcess_Reading - unning - reading the data from host memory + * ETH_DMA_TransmitProcess_Suspended - Suspended - Tx Desciptor unavailabe + * ETH_DMA_TransmitProcess_Closing - Running - closing Rx descriptor + */ +uint32_t ETH_GetTransmitProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); +} + +/********************************************************************* + * @fn ETH_GetReceiveProcessState + * + * @brief Returns the ETHERNET DMA Receive Process State. + * + * @return The new ETHERNET DMA Receive Process State: + * ETH_DMA_ReceiveProcess_Stopped - Stopped - Reset or Stop Rx Command issued + * ETH_DMA_ReceiveProcess_Fetching - Running - fetching the Rx descriptor + * ETH_DMA_ReceiveProcess_Waiting - Running - waiting for packet + * ETH_DMA_ReceiveProcess_Suspended - Suspended - Rx Desciptor unavailable + * ETH_DMA_ReceiveProcess_Closing - Running - closing descriptor + * ETH_DMA_ReceiveProcess_Queuing - Running - queuing the recieve frame into host memory + */ +uint32_t ETH_GetReceiveProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); +} + +/********************************************************************* + * @fn ETH_FlushTransmitFIFO + * + * @brief Clears the ETHERNET transmit FIFO. + * + * @return none + */ +void ETH_FlushTransmitFIFO(void) +{ + ETH->DMAOMR |= ETH_DMAOMR_FTF; +} + +/********************************************************************* + * @fn ETH_GetFlushTransmitFIFOStatus + * + * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not. + * + * @return The new state of ETHERNET flush transmit FIFO bit (SET or RESET). + */ +FlagStatus ETH_GetFlushTransmitFIFOStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMATransmissionCmd + * + * @brief Enables or disables the DMA transmission. + * + * @param NewState - new state of the DMA transmission. + * + * @return none + */ +void ETH_DMATransmissionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAOMR |= ETH_DMAOMR_ST; + } + else + { + ETH->DMAOMR &= ~ETH_DMAOMR_ST; + } +} + +/********************************************************************* + * @fn ETH_DMAReceptionCmd + * + * @brief Enables or disables the DMA reception. + * + * @param NewState - new state of the DMA reception. + * + * @return none + */ +void ETH_DMAReceptionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAOMR |= ETH_DMAOMR_SR; + } + else + { + ETH->DMAOMR &= ~ETH_DMAOMR_SR; + } +} + +/********************************************************************* + * @fn ETH_DMAITConfig + * + * @brief Enables or disables the specified ETHERNET DMA interrupts. + * + * @param ETH_DMA_IT - specifies the ETHERNET DMA interrupt sources to be enabled or disabled. + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ET - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Underflow interrupt + * ETH_DMA_IT_RO - Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter + * ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter + * NewState - new state of the specified ETHERNET DMA interrupts. + * + * @return new state of the specified ETHERNET DMA interrupts. + */ +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAIER |= ETH_DMA_IT; + } + else + { + ETH->DMAIER &= (~(uint32_t)ETH_DMA_IT); + } +} + +/********************************************************************* + * @fn ETH_GetDMAOverflowStatus + * + * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * + * @param ETH_DMA_Overflow - specifies the DMA overflow flag to check. + * ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter + * ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter + * + * @return The new state of ETHERNET DMA overflow Flag (SET or RESET). + */ +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetRxOverflowMissedFrameCounter + * + * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. + * + * @return The value of Rx overflow Missed Frame Counter. + */ +uint32_t ETH_GetRxOverflowMissedFrameCounter(void) +{ + return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >> ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT)); +} + +/********************************************************************* + * @fn ETH_GetBufferUnavailableMissedFrameCounter + * + * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. + * + * @return The value of Buffer unavailable Missed Frame Counter. + */ +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) +{ + return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); +} + +/********************************************************************* + * @fn ETH_GetCurrentTxDescStartAddress + * + * @brief Get the ETHERNET DMA DMACHTDR register value. + * + * @return The value of the current Tx desc start address. + */ +uint32_t ETH_GetCurrentTxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHTDR)); +} + +/********************************************************************* + * @fn ETH_GetCurrentRxDescStartAddress + * + * @brief Get the ETHERNET DMA DMACHRDR register value. + * + * @return The value of the current Rx desc start address. + */ +uint32_t ETH_GetCurrentRxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHRDR)); +} + +/********************************************************************* + * @fn ETH_GetCurrentTxBufferAddress + * + * @brief Get the ETHERNET DMA DMACHTBAR register value. + * + * @return The value of the current Tx buffer address. + */ +uint32_t ETH_GetCurrentTxBufferAddress(void) +{ + return (DMATxDescToSet->Buffer1Addr); +} + +/********************************************************************* + * @fn ETH_GetCurrentRxBufferAddress + * + * @brief Get the ETHERNET DMA DMACHRBAR register value. + * + * @return The value of the current Rx buffer address. + */ +uint32_t ETH_GetCurrentRxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHRBAR)); +} + +/********************************************************************* + * @fn ETH_ResumeDMATransmission + * + * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register + * + * @return none + */ +void ETH_ResumeDMATransmission(void) +{ + ETH->DMATPDR = 0; +} + +/********************************************************************* + * @fn ETH_ResumeDMAReception + * + * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register. + * + * @return none + */ +void ETH_ResumeDMAReception(void) +{ + ETH->DMARPDR = 0; +} + +/********************************************************************* + * @fn ETH_ResetWakeUpFrameFilterRegisterPointer + * + * @brief Reset Wakeup frame filter register pointer. + * + * @return none + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; +} + +/********************************************************************* + * @fn ETH_SetWakeUpFrameFilterRegister + * + * @brief Populates the remote wakeup frame registers. + * + * @param Buffer - Pointer on remote WakeUp Frame Filter Register buffer data (8 words). + * + * @return none + */ +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) +{ + uint32_t i = 0; + + for(i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) + { + ETH->MACRWUFFR = Buffer[i]; + } +} + +/********************************************************************* + * @fn ETH_GlobalUnicastWakeUpCmd + * + * @brief Enables or disables any unicast packet filtered by the MAC address. + * + * @param NewState - new state of the MAC Global Unicast Wake-Up. + * + * @return none + */ +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; + } +} + +/********************************************************************* + * @fn ETH_GetPMTFlagStatus + * + * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * + * @param ETH_PMT_FLAG - specifies the flag to check. + * + * @return The new state of ETHERNET PMT Flag (SET or RESET). + */ +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_WakeUpFrameDetectionCmd + * + * @brief Enables or disables the MAC Wake-Up Frame Detection. + * + * @param NewState - new state of the MAC Wake-Up Frame Detection. + * + * @return none + */ +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; + } +} + +/********************************************************************* + * @fn ETH_MagicPacketDetectionCmd + * + * @brief Enables or disables the MAC Magic Packet Detection. + * + * @param NewState - new state of the MAC Magic Packet Detection. + * + * @return none + */ +void ETH_MagicPacketDetectionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; + } +} + +/********************************************************************* + * @fn ETH_PowerDownCmd + * + * @brief Enables or disables the MAC Power Down. + * + * @param NewState - new state of the MAC Power Down. + * + * @return none + */ +void ETH_PowerDownCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; + } +} + +/********************************************************************* + * @fn ETH_MMCCounterFreezeCmd + * + * @brief Enables or disables the MMC Counter Freeze. + * + * @param NewState - new state of the MMC Counter Freeze. + * + * @return none + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR |= ETH_MMCCR_MCF; + } + else + { + ETH->MMCCR &= ~ETH_MMCCR_MCF; + } +} + +/********************************************************************* + * @fn ETH_MMCResetOnReadCmd + * + * @brief Enables or disables the MMC Reset On Read. + * + * @param NewState - new state of the MMC Reset On Read. + * + * @return none + */ +void ETH_MMCResetOnReadCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR |= ETH_MMCCR_ROR; + } + else + { + ETH->MMCCR &= ~ETH_MMCCR_ROR; + } +} + +/********************************************************************* + * @fn ETH_MMCCounterRolloverCmd + * + * @brief Enables or disables the MMC Counter Stop Rollover. + * + * @param NewState - new state of the MMC Counter Stop Rollover. + * + * @return none + */ +void ETH_MMCCounterRolloverCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR &= ~ETH_MMCCR_CSR; + } + else + { + ETH->MMCCR |= ETH_MMCCR_CSR; + } +} + +/********************************************************************* + * @fn ETH_MMCCountersReset + * + * @brief Resets the MMC Counters. + * + * @return none + */ +void ETH_MMCCountersReset(void) +{ + ETH->MMCCR |= ETH_MMCCR_CR; +} + +/********************************************************************* + * @fn ETH_MMCITConfig + * + * @brief Enables or disables the specified ETHERNET MMC interrupts. + * + * @param ETH_MMC_IT - specifies the ETHERNET MMC interrupt. + * ETH_MMC_IT_TGF - When Tx good frame counter reaches half the maximum value. + * ETH_MMC_IT_TGFMSC - When Tx good multi col counter reaches half the maximum value. + * ETH_MMC_IT_TGFSC - When Tx good single col counter reaches half the maximum value. + * ETH_MMC_IT_RGUF - When Rx good unicast frames counter reaches half the maximum value. + * ETH_MMC_IT_RFAE - When Rx alignment error counter reaches half the maximum value. + * ETH_MMC_IT_RFCE - When Rx crc error counter reaches half the maximum value. + * NewState - new state of the specified ETHERNET MMC interrupts. + * + * @return none + */ +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) +{ + if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + ETH_MMC_IT &= 0xEFFFFFFF; + + if(NewState != DISABLE) + { + ETH->MMCRIMR &= (~(uint32_t)ETH_MMC_IT); + } + else + { + ETH->MMCRIMR |= ETH_MMC_IT; + } + } + else + { + if(NewState != DISABLE) + { + ETH->MMCTIMR &= (~(uint32_t)ETH_MMC_IT); + } + else + { + ETH->MMCTIMR |= ETH_MMC_IT; + } + } +} + +/********************************************************************* + * @fn ETH_GetMMCITStatus + * + * @brief Checks whether the specified ETHERNET MMC IT is set or not. + * + * @param ETH_MMC_IT - specifies the ETHERNET MMC interrupt. + * ETH_MMC_IT_TxFCGC - When Tx good frame counter reaches half the maximum value. + * ETH_MMC_IT_TxMCGC - When Tx good multi col counter reaches half the maximum value. + * ETH_MMC_IT_TxSCGC - When Tx good single col counter reaches half the maximum value . + * ETH_MMC_IT_RxUGFC - When Rx good unicast frames counter reaches half the maximum value. + * ETH_MMC_IT_RxAEC - When Rx alignment error counter reaches half the maximum value. + * ETH_MMC_IT_RxCEC - When Rx crc error counter reaches half the maximum value. + * + * @return The value of ETHERNET MMC IT (SET or RESET). + */ +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) +{ + ITStatus bitstatus = RESET; + + if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + if((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetMMCRegister + * + * @brief Get the specified ETHERNET MMC register value. + * + * @param ETH_MMCReg - specifies the ETHERNET MMC register. + * ETH_MMCCR - MMC CR register + * ETH_MMCRIR - MMC RIR register + * ETH_MMCTIR - MMC TIR register + * ETH_MMCRIMR - MMC RIMR register + * ETH_MMCTIMR - MMC TIMR register + * ETH_MMCTGFSCCR - MMC TGFSCCR register + * ETH_MMCTGFMSCCR - MMC TGFMSCCR register + * ETH_MMCTGFCR - MMC TGFCR register + * ETH_MMCRFCECR - MMC RFCECR register + * ETH_MMCRFAECR - MMC RFAECR register + * ETH_MMCRGUFCR - MMC RGUFCRregister + * + * @return The value of ETHERNET MMC Register value. + */ +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) +{ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampAddend + * + * @brief Updated the PTP block for fine correction with the Time Stamp Addend register value. + * + * @return none + */ +void ETH_EnablePTPTimeStampAddend(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampInterruptTrigger + * + * @brief Enable the PTP Time Stamp interrupt trigger + * + * @return none + */ +void ETH_EnablePTPTimeStampInterruptTrigger(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampUpdate + * + * @brief Updated the PTP system time with the Time Stamp Update register value. + * + * @return none + */ +void ETH_EnablePTPTimeStampUpdate(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; +} + +/********************************************************************* + * @fn ETH_InitializePTPTimeStamp + * + * @brief Initialize the PTP Time Stamp. + * + * @return none + */ +void ETH_InitializePTPTimeStamp(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; +} + +/********************************************************************* + * @fn ETH_PTPUpdateMethodConfig + * + * @brief Selects the PTP Update method. + * + * @param UpdateMethod - the PTP Update method. + * + * @return none + */ +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) +{ + if(UpdateMethod != ETH_PTP_CoarseUpdate) + { + ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU; + } + else + { + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); + } +} + +/********************************************************************* + * @fn ETH_PTPTimeStampCmd + * + * @brief Enables or disables the PTP time stamp for transmit and receive frames. + * + * @param NewState - new state of the PTP time stamp for transmit and receive frames. + * + * @return none + */ +void ETH_PTPTimeStampCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->PTPTSCR |= ETH_PTPTSCR_TSE; + } + else + { + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE); + } +} + +/********************************************************************* + * @fn ETH_GetPTPFlagStatus + * + * @brief Checks whether the specified ETHERNET PTP flag is set or not. + * + * @param The new state of ETHERNET PTP Flag (SET or RESET). + * + * @return none + */ +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_SetPTPSubSecondIncrement + * + * @brief Sets the system time Sub-Second Increment value. + * + * @param SubSecondValue - specifies the PTP Sub-Second Increment Register value. + * + * @return none + */ +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) +{ + ETH->PTPSSIR = SubSecondValue; +} + +/********************************************************************* + * @fn ETH_SetPTPTimeStampUpdate + * + * @brief Sets the Time Stamp update sign and values. + * + * @param Sign - specifies the PTP Time update value sign. + * SecondValue - specifies the PTP Time update second value. + * SubSecondValue - specifies the PTP Time update sub-second value. + * + * @return none + */ +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) +{ + ETH->PTPTSHUR = SecondValue; + ETH->PTPTSLUR = Sign | SubSecondValue; +} + +/********************************************************************* + * @fn ETH_SetPTPTimeStampAddend + * + * @brief Sets the Time Stamp Addend value. + * + * @param Value - specifies the PTP Time Stamp Addend Register value. + * + * @return none + */ +void ETH_SetPTPTimeStampAddend(uint32_t Value) +{ + /* Set the PTP Time Stamp Addend Register */ + ETH->PTPTSAR = Value; +} + +/********************************************************************* + * @fn ETH_SetPTPTargetTime + * + * @brief Sets the Target Time registers values. + * + * @param HighValue - specifies the PTP Target Time High Register value. + * LowValue - specifies the PTP Target Time Low Register value. + * + * @return none + */ +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) +{ + ETH->PTPTTHR = HighValue; + ETH->PTPTTLR = LowValue; +} + +/********************************************************************* + * @fn ETH_GetPTPRegister + * + * @brief Get the specified ETHERNET PTP register value. + * + * @param ETH_PTPReg - specifies the ETHERNET PTP register. + * ETH_PTPTSCR - Sub-Second Increment Register + * ETH_PTPSSIR - Sub-Second Increment Register + * ETH_PTPTSHR - Time Stamp High Register + * ETH_PTPTSLR - Time Stamp Low Register + * ETH_PTPTSHUR - Time Stamp High Update Register + * ETH_PTPTSLUR - Time Stamp Low Update Register + * ETH_PTPTSAR - Time Stamp Addend Register + * ETH_PTPTTHR - Target Time High Register + * ETH_PTPTTLR - Target Time Low Register + * + * @return The value of ETHERNET PTP Register value. + */ +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) +{ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); +} + +/********************************************************************* + * @fn ETH_DMAPTPTxDescChainInit + * + * @brief Initializes the DMA Tx descriptors in chain mode with PTP. + * + * @param DMATxDescTab - Pointer on the first Tx desc list. + * DMAPTPTxDescTab - Pointer on the first PTP Tx desc list. + * TxBuff - Pointer on the first TxBuffer list. + * TxBuffCount - Number of the used Tx desc in the list. + * + * @return none. + */ +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, + uint8_t *TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + DMAPTPTxDescToSet = DMAPTPTxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (TxBuffCount - 1)) + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab; + } + + (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr; + (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; + } + + (&DMAPTPTxDescTab[i - 1])->Status = (uint32_t)DMAPTPTxDescTab; + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_DMAPTPRxDescChainInit + * + * @brief Initializes the DMA Rx descriptors in chain mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * DMAPTPRxDescTab - Pointer on the first PTP Rx desc list. + * RxBuff - Pointer on the first RxBuffer list. + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none. + */ +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, + uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + DMAPTPRxDescToGet = DMAPTPRxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (RxBuffCount - 1)) + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + + (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr; + (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; + } + + (&DMAPTPRxDescTab[i - 1])->Status = (uint32_t)DMAPTPRxDescTab; + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_HandlePTPTxPkt + * + * @brief Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values. + * + * @param ppkt - pointer to application packet buffer to transmit. + * FrameLength - Tx Packet size. + * PTPTxTab - Pointer on the first PTP Tx table to store Time stamp values. + * + * @return none. + */ +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) +{ + uint32_t offset = 0, timeout = 0; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + for(offset = 0; offset < FrameLength; offset++) + { + (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset)); + } + + DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF); + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_TBUS; + ETH->DMATPDR = 0; + } + + do + { + timeout++; + } while(!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); + + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + + DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; + *PTPTxTab++ = DMATxDescToSet->Buffer1Addr; + *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Buffer2NextDescAddr); + if(DMAPTPTxDescToSet->Status != 0) + { + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Status); + } + else + { + DMAPTPTxDescToSet++; + } + } + else + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + } + else + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_HandlePTPRxPkt + * + * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values. + * + * @param ppkt - pointer to application packet receive buffer. + * PTPRxTab - Pointer on the first PTP Rx table to store Time stamp values. + * + * @return ETH_ERROR - if there is error in reception. + * framelength - received packet size if packet reception is correct. + */ +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) +{ + uint32_t offset = 0, framelength = 0; + + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + for(offset = 0; offset < framelength; offset++) + { + (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset)); + } + } + else + { + framelength = ETH_ERROR; + } + + if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_RBUS; + ETH->DMARPDR = 0; + } + + *PTPRxTab++ = DMARxDescToGet->Buffer1Addr; + *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr; + DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Buffer2NextDescAddr); + if(DMAPTPRxDescToGet->Status != 0) + { + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Status); + } + else + { + DMAPTPRxDescToGet++; + } + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return (framelength); +} + +/********************************************************************* + * @fn RGMII_TXC_Delay + * + * @brief Delay time. + * + * @return none + */ +void RGMII_TXC_Delay(uint8_t clock_polarity, uint8_t delay_time) +{ + if(clock_polarity) + { + ETH->MACCR |= (uint32_t)(1 << 1); + } + else + { + ETH->MACCR &= ~(uint32_t)(1 << 1); + } + if(delay_time <= 7) + { + ETH->MACCR |= (uint32_t)(delay_time << 29); + } +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_exti.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_exti.c index 7f10cbf..5ce2cb8 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_exti.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_exti.c @@ -1,182 +1,182 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_exti.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the EXTI firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_exti.h" - -/* No interrupt selected */ -#define EXTI_LINENONE ((uint32_t)0x00000) - -/********************************************************************* - * @fn EXTI_DeInit - * - * @brief Deinitializes the EXTI peripheral registers to their default - * reset values. - * - * @return none. - */ -void EXTI_DeInit(void) -{ - EXTI->INTENR = 0x00000000; - EXTI->EVENR = 0x00000000; - EXTI->RTENR = 0x00000000; - EXTI->FTENR = 0x00000000; - EXTI->INTFR = 0x000FFFFF; -} - -/********************************************************************* - * @fn EXTI_Init - * - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * - * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) -{ - uint32_t tmp = 0; - - tmp = (uint32_t)EXTI_BASE; - if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; - if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/********************************************************************* - * @fn EXTI_StructInit - * - * @brief Fills each EXTI_InitStruct member with its reset value. - * - * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/********************************************************************* - * @fn EXTI_GenerateSWInterrupt - * - * @brief Generates a Software interrupt. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none. - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - EXTI->SWIEVR |= EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetFlagStatus - * - * @brief Checks whether the specified EXTI line flag is set or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearFlag - * - * @brief Clears the EXTI's line pending flags. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetITStatus - * - * @brief Checks whether the specified EXTI line is asserted or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = EXTI->INTENR & EXTI_Line; - if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearITPendingBit - * - * @brief Clears the EXTI's line pending bits. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_exti.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the EXTI firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_exti.h" + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x000FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_flash.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_flash.c index 2a64ed5..5e3c0eb 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_flash.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_flash.c @@ -1,967 +1,1223 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_flash.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the FLASH firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_flash.h" - -/* Flash Control Register bits */ -#define CR_PG_Set ((uint32_t)0x00000001) -#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) -#define CR_FAST_LOCK_Set ((uint32_t)0x00008000) -#define CR_PAGE_PG ((uint32_t)0x00010000) -#define CR_PAGE_ER ((uint32_t)0x00020000) -#define CR_BER32 ((uint32_t)0x00040000) -#define CR_BER64 ((uint32_t)0x00080000) -#define CR_PG_STRT ((uint32_t)0x00200000) - -/* FLASH Status Register bits */ -#define SR_BSY ((uint32_t)0x00000001) -#define SR_WR_BSY ((uint32_t)0x00000002) -#define SR_WRPRTERR ((uint32_t)0x00000010) -#define SR_EOP ((uint32_t)0x00000020) - -/* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) -#define OB_USER_BFB2 ((uint16_t)0x0008) - -/* FLASH Keys */ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) - -/* FLASH BANK address */ -#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) - -/* Delay definition */ -#define EraseTimeout ((uint32_t)0x000B0000) -#define ProgramTimeout ((uint32_t)0x00005000) - -/********************************************************************* - * @fn FLASH_Unlock - * - * @brief Unlocks the FLASH Program Erase Controller. - * - * @return none - */ -void FLASH_Unlock(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -/********************************************************************* - * @fn FLASH_UnlockBank1 - * - * @brief Unlocks the FLASH Bank1 Program Erase Controller. - * equivalent to FLASH_Unlock function. - * - * @return none - */ -void FLASH_UnlockBank1(void) -{ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -/********************************************************************* - * @fn FLASH_Lock - * - * @brief Locks the FLASH Program Erase Controller. - * - * @return none - */ -void FLASH_Lock(void) -{ - FLASH->CTLR |= CR_LOCK_Set; -} - -/********************************************************************* - * @fn FLASH_LockBank1 - * - * @brief Locks the FLASH Bank1 Program Erase Controller. - * - * @return none - */ -void FLASH_LockBank1(void) -{ - FLASH->CTLR |= CR_LOCK_Set; -} - -/********************************************************************* - * @fn FLASH_ErasePage - * - * @brief Erases a specified FLASH page(page size 4KB). - * - * @param Page_Address - The page address to be erased. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_PER_Set; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_PER_Reset; - } - - return status; -} - -/********************************************************************* - * @fn FLASH_EraseAllPages - * - * @brief Erases all FLASH pages. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_MER_Set; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_MER_Reset; - } - - return status; -} - -/********************************************************************* - * @fn FLASH_EraseAllBank1Pages - * - * @brief Erases all Bank1 FLASH pages. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllBank1Pages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_MER_Set; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - FLASH->CTLR &= CR_MER_Reset; - } - return status; -} - -/********************************************************************* - * @fn FLASH_EraseOptionBytes - * - * @brief Erases the FLASH option bytes. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseOptionBytes(void) -{ - uint16_t rdptmp = RDP_Key; - uint32_t Address = 0x1FFFF800; - __IO uint8_t i; - - FLASH_Status status = FLASH_COMPLETE; - if(FLASH_GetReadOutProtectionStatus() != RESET) - { - rdptmp = 0x00; - } - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR &= CR_OPTER_Reset; - FLASH->CTLR |= CR_OPTPG_Set; - OB->RDPR = (uint16_t)rdptmp; - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - FLASH->CTLR &= CR_OPTPG_Reset; - } - } - - /* Write 0xFF */ - FLASH->CTLR |= CR_OPTPG_Set; - - for(i = 0; i < 8; i++) - { - *(uint16_t *)(Address + 2 * i) = 0x00FF; - while(FLASH->STATR & SR_BSY) - ; - } - - FLASH->CTLR &= ~CR_OPTPG_Set; - } - return status; -} - -/********************************************************************* - * @fn FLASH_ProgramWord - * - * @brief Programs a word at a specified address. - * - * @param Address - specifies the address to be programmed. - * Data - specifies the data to be programmed. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_PG_Set; - - *(__IO uint16_t *)Address = (uint16_t)Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - tmp = Address + 2; - *(__IO uint16_t *)tmp = Data >> 16; - status = FLASH_WaitForLastOperation(ProgramTimeout); - FLASH->CTLR &= CR_PG_Reset; - } - else - { - FLASH->CTLR &= CR_PG_Reset; - } - } - - return status; -} - -/********************************************************************* - * @fn FLASH_ProgramHalfWord - * - * @brief Programs a half word at a specified address. - * - * @param Address - specifies the address to be programmed. - * Data - specifies the data to be programmed. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_PG_Set; - *(__IO uint16_t *)Address = Data; - status = FLASH_WaitForLastOperation(ProgramTimeout); - FLASH->CTLR &= CR_PG_Reset; - } - - return status; -} - -/********************************************************************* - * @fn FLASH_ProgramOptionByteData - * - * @brief Programs a half word at a specified Option Byte Data address. - * - * @param Address - specifies the address to be programmed. - * Data - specifies the data to be programmed. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t Addr = 0x1FFFF800; - __IO uint8_t i; - uint16_t pbuf[8]; - - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - - /* Read optionbytes */ - for(i = 0; i < 8; i++) - { - pbuf[i] = *(uint16_t *)(Addr + 2 * i); - } - - /* Erase optionbytes */ - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_OPTER_Set; - - /* Write optionbytes */ - pbuf[((Address - 0x1FFFF800) / 2)] = ((((uint16_t) ~(Data)) << 8) | ((uint16_t)Data)); - - FLASH->CTLR |= CR_OPTPG_Set; - - for(i = 0; i < 8; i++) - { - *(uint16_t *)(Addr + 2 * i) = pbuf[i]; - while(FLASH->STATR & SR_BSY) - ; - } - - FLASH->CTLR &= ~CR_OPTPG_Set; - } - - return status; -} - -/********************************************************************* - * @fn FLASH_EnableWriteProtection - * - * @brief Write protects the desired sectors - * - * @param FLASH_Sectors - specifies the address of the pages to be write protected. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors) -{ - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; - FLASH_Status status = FLASH_COMPLETE; - uint32_t Addr = 0x1FFFF800; - __IO uint8_t i; - uint16_t pbuf[8]; - - FLASH_Sectors = (uint32_t)(~FLASH_Sectors); - WRP0_Data = (uint16_t)(FLASH_Sectors & WRP0_Mask); - WRP1_Data = (uint16_t)((FLASH_Sectors & WRP1_Mask) >> 8); - WRP2_Data = (uint16_t)((FLASH_Sectors & WRP2_Mask) >> 16); - WRP3_Data = (uint16_t)((FLASH_Sectors & WRP3_Mask) >> 24); - - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - - /* Read optionbytes */ - for(i = 0; i < 8; i++) - { - pbuf[i] = *(uint16_t *)(Addr + 2 * i); - } - - /* Erase optionbytes */ - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_OPTER_Set; - - /* Write optionbytes */ - pbuf[4] = WRP0_Data; - pbuf[5] = WRP1_Data; - pbuf[6] = WRP2_Data; - pbuf[7] = WRP3_Data; - - FLASH->CTLR |= CR_OPTPG_Set; - for(i = 0; i < 8; i++) - { - *(uint16_t *)(Addr + 2 * i) = pbuf[i]; - while(FLASH->STATR & SR_BSY) - ; - } - FLASH->CTLR &= ~CR_OPTPG_Set; - } - return status; -} - -/********************************************************************* - * @fn FLASH_ReadOutProtection - * - * @brief Enables or disables the read out protection. - * - * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t Addr = 0x1FFFF800; - __IO uint8_t i; - uint16_t pbuf[8]; - - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - - /* Read optionbytes */ - for(i = 0; i < 8; i++) - { - pbuf[i] = *(uint16_t *)(Addr + 2 * i); - } - - /* Erase optionbytes */ - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_OPTER_Set; - - /* Write optionbytes */ - if(NewState == DISABLE) - pbuf[0] = 0x5AA5; - else - pbuf[0] = 0x00FF; - - FLASH->CTLR |= CR_OPTPG_Set; - for(i = 0; i < 8; i++) - { - *(uint16_t *)(Addr + 2 * i) = pbuf[i]; - while(FLASH->STATR & SR_BSY) - ; - } - FLASH->CTLR &= ~CR_OPTPG_Set; - } - return status; -} - -/********************************************************************* - * @fn FLASH_UserOptionByteConfig - * - * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. - * - * @param OB_IWDG - Selects the IWDG mode - * OB_IWDG_SW - Software IWDG selected - * OB_IWDG_HW - Hardware IWDG selected - * OB_STOP - Reset event when entering STOP mode. - * OB_STOP_NoRST - No reset generated when entering in STOP - * OB_STOP_RST - Reset generated when entering in STOP - * OB_STDBY - Reset event when entering Standby mode. - * OB_STDBY_NoRST - No reset generated when entering in STANDBY - * OB_STDBY_RST - Reset generated when entering in STANDBY - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t Addr = 0x1FFFF800; - __IO uint8_t i; - uint16_t pbuf[8]; - - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Read optionbytes */ - for(i = 0; i < 8; i++) - { - pbuf[i] = *(uint16_t *)(Addr + 2 * i); - } - - /* Erase optionbytes */ - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_OPTER_Set; - - /* Write optionbytes */ - pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); - - FLASH->CTLR |= CR_OPTPG_Set; - for(i = 0; i < 8; i++) - { - *(uint16_t *)(Addr + 2 * i) = pbuf[i]; - while(FLASH->STATR & SR_BSY) - ; - } - FLASH->CTLR &= ~CR_OPTPG_Set; - } - return status; -} - -/********************************************************************* - * @fn FLASH_GetUserOptionByte - * - * @brief Returns the FLASH User Option Bytes values. - * - * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint32_t FLASH_GetUserOptionByte(void) -{ - return (uint32_t)(FLASH->OBR >> 2); -} - -/********************************************************************* - * @fn FLASH_GetWriteProtectionOptionByte - * - * @brief Returns the FLASH Write Protection Option Bytes Register value. - * - * @return The FLASH Write Protection Option Bytes Register value. - */ -uint32_t FLASH_GetWriteProtectionOptionByte(void) -{ - return (uint32_t)(FLASH->WPR); -} - -/********************************************************************* - * @fn FLASH_GetReadOutProtectionStatus - * - * @brief Checks whether the FLASH Read Out Protection Status is set or not. - * - * @return FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetReadOutProtectionStatus(void) -{ - FlagStatus readoutstatus = RESET; - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - readoutstatus = SET; - } - else - { - readoutstatus = RESET; - } - return readoutstatus; -} - -/********************************************************************* - * @fn FLASH_ITConfig - * - * @brief Enables or disables the specified FLASH interrupts. - * - * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. - * FLASH_IT_ERROR - FLASH Error Interrupt - * FLASH_IT_EOP - FLASH end of operation Interrupt - * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). - * - * @return FLASH Prefetch Buffer Status (SET or RESET). - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - FLASH->CTLR |= FLASH_IT; - } - else - { - FLASH->CTLR &= ~(uint32_t)FLASH_IT; - } -} - -/********************************************************************* - * @fn FLASH_GetFlagStatus - * - * @brief Checks whether the specified FLASH flag is set or not. - * - * @param FLASH_FLAG - specifies the FLASH flag to check. - * FLASH_FLAG_BSY - FLASH Busy flag - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * FLASH_FLAG_OPTERR - FLASH Option Byte error flag - * - * @return The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - return bitstatus; -} - -/********************************************************************* - * @fn FLASH_ClearFlag - * - * @brief Clears the FLASH's pending flags. - * - * @param FLASH_FLAG - specifies the FLASH flags to clear. - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * - * @return none - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - FLASH->STATR = FLASH_FLAG; -} - -/********************************************************************* - * @fn FLASH_GetStatus - * - * @brief Returns the FLASH Status. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_GetBank1Status - * - * @brief Returns the FLASH Bank1 Status. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetBank1Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_WaitForLastOperation - * - * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_WaitForLastBank1Operation - * - * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_Unlock_Fast - * - * @brief Unlocks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Unlock_Fast(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - - /* Fast program mode unlock */ - FLASH->MODEKEYR = FLASH_KEY1; - FLASH->MODEKEYR = FLASH_KEY2; -} - -/********************************************************************* - * @fn FLASH_Lock_Fast - * - * @brief Locks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Lock_Fast(void) -{ - FLASH->CTLR |= CR_FAST_LOCK_Set; -} - -/********************************************************************* - * @fn FLASH_ErasePage_Fast - * - * @brief Erases a specified FLASH page (1page = 256Byte). - * - * @param Page_Address - The page address to be erased. - * - * @return none - */ -void FLASH_ErasePage_Fast(uint32_t Page_Address) -{ - Page_Address &= 0xFFFFFF00; - - FLASH->CTLR |= CR_PAGE_ER; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_ER; -} - -/********************************************************************* - * @fn FLASH_EraseBlock_32K_Fast - * - * @brief Erases a specified FLASH Block (1Block = 32KByte). - * - * @param Block_Address - The block address to be erased. - * - * @return none - */ -void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) -{ - Block_Address &= 0xFFFF8000; - - FLASH->CTLR |= CR_BER32; - FLASH->ADDR = Block_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_BER32; -} - -/********************************************************************* - * @fn FLASH_EraseBlock_64K_Fast - * - * @brief Erases a specified FLASH Block (1Block = 64KByte). - * - * @param Block_Address - The block address to be erased. - * - * @return none - */ -void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address) -{ - Block_Address &= 0xFFFF0000; - - FLASH->CTLR |= CR_BER64; - FLASH->ADDR = Block_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_BER64; -} - -/********************************************************************* - * @fn FLASH_ProgramPage_Fast - * - * @brief Program a specified FLASH page (1page = 256Byte). - * - * @param Page_Address - The page address to be programed. - * - * @return none - */ -void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf) -{ - uint8_t size = 64; - - Page_Address &= 0xFFFFFF00; - - FLASH->CTLR |= CR_PAGE_PG; - while(FLASH->STATR & SR_BSY) - ; - while(FLASH->STATR & SR_WR_BSY) - ; - - while(size) - { - *(uint32_t *)Page_Address = *(uint32_t *)pbuf; - Page_Address += 4; - pbuf += 1; - size -= 1; - while(FLASH->STATR & SR_WR_BSY) - ; - } - - FLASH->CTLR |= CR_PG_STRT; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; -} - -/********************************************************************* - * @fn FLASH_Access_Clock_Cfg - * - * @brief Config FLASH Access Clock(Need to unlock ) - * - * @param FLASH_Access_CLK - - * FLASH_Access_SYSTEM_HALF - System clock/2 - * FLASH_Access_SYSTEM - System clock - * - * @return none - */ -void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK) -{ - FLASH->CTLR &= ~(1 << 25); - FLASH->CTLR |= FLASH_Access_CLK; -} - -/********************************************************************* - * @fn FLASH_Enhance_Mode - * - * @brief Read FLASH Enhance Mode - * - * @param - * Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). - * - * @return none - */ -void FLASH_Enhance_Mode(FunctionalState NewState) -{ - if(NewState) - { - FLASH->CTLR |= (1 << 24); - } - else - { - FLASH->CTLR &= ~(1 << 24); - FLASH->CTLR |= (1 << 22); - } -} - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_flash.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/24 +* Description : This file provides all the FLASH firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_flash.h" + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FLOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BER32 ((uint32_t)0x00040000) +#define CR_PG_STRT ((uint32_t)0x00200000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WR_BSY ((uint32_t)0x00000002) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00005000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x78000) + +/* FLASH Size */ +#define Size_256B 0x100 +#define Size_4KB 0x1000 +#define Size_32KB 0x8000 + +/********************************************************************* + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program Erase Controller. + * + * @return none + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_UnlockBank1 + * + * @brief Unlocks the FLASH Bank1 Program Erase Controller. + * equivalent to FLASH_Unlock function. + * + * @return none + */ +void FLASH_UnlockBank1(void) +{ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return none + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/********************************************************************* + * @fn FLASH_LockBank1 + * + * @brief Locks the FLASH Bank1 Program Erase Controller. + * + * @return none + */ +void FLASH_LockBank1(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/********************************************************************* + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page(page size 4KB). + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EraseAllBank1Pages + * + * @brief Erases all Bank1 FLASH pages. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank1Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + return status; +} + +/********************************************************************* + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + uint32_t Address = 0x1FFFF800; + __IO uint8_t i; + + FLASH_Status status = FLASH_COMPLETE; + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= CR_OPTER_Reset; + FLASH->CTLR |= CR_OPTPG_Set; + OB->RDPR = (uint16_t)rdptmp; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + + /* Write 0xFF */ + FLASH->CTLR |= CR_OPTPG_Set; + + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Address + 2 * i) = 0x00FF; + while(FLASH->STATR & SR_BSY) + ; + } + + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramWord + * + * @brief Programs a word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + + *(__IO uint16_t *)Address = (uint16_t)Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + tmp = Address + 2; + *(__IO uint16_t *)tmp = Data >> 16; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + else + { + FLASH->CTLR &= CR_PG_Reset; + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramHalfWord + * + * @brief Programs a half word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + *(__IO uint16_t *)Address = Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramOptionByteData + * + * @brief Programs a half word at a specified Option Byte Data address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[((Address - 0x1FFFF800) / 2)] = ((((uint16_t) ~(Data)) << 8) | ((uint16_t)Data)); + + FLASH->CTLR |= CR_OPTPG_Set; + + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + + FLASH->CTLR &= ~CR_OPTPG_Set; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Sectors - specifies the address of the pages to be write protected. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + FLASH_Sectors = (uint32_t)(~FLASH_Sectors); + WRP0_Data = (uint16_t)(FLASH_Sectors & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Sectors & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Sectors & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Sectors & WRP3_Mask) >> 24); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[4] = WRP0_Data; + pbuf[5] = WRP1_Data; + pbuf[6] = WRP2_Data; + pbuf[7] = WRP3_Data; + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_ReadOutProtection + * + * @brief Enables or disables the read out protection. + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + if(NewState == DISABLE) + pbuf[0] = 0x5AA5; + else + pbuf[0] = 0x00FF; + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. + * + * @param OB_IWDG - Selects the IWDG mode + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STOP - Reset event when entering STOP mode. + * OB_STOP_NoRST - No reset generated when entering in STOP + * OB_STOP_RST - Reset generated when entering in STOP + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY + * OB_STDBY_RST - Reset generated when entering in STANDBY + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + uint16_t temp; + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + temp=pbuf[1]&(~0x7); + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)temp))); + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt + * FLASH_IT_EOP - FLASH end of operation Interrupt + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + FLASH->STATR = FLASH_FLAG; +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_FLOCK_Set; +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + Page_Address &= 0xFFFFFF00; + + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_ER; +} + +/********************************************************************* + * @fn FLASH_EraseBlock_32K_Fast + * + * @brief Erases a specified FLASH Block (1Block = 32KByte). + * + * @param Block_Address - The block address to be erased. + * + * @return none + */ +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) +{ + Block_Address &= 0xFFFF8000; + + FLASH->CTLR |= CR_BER32; + FLASH->ADDR = Block_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_BER32; +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf) +{ + uint8_t size = 64; + + Page_Address &= 0xFFFFFF00; + + FLASH->CTLR |= CR_PAGE_PG; + while(FLASH->STATR & SR_BSY) + ; + while(FLASH->STATR & SR_WR_BSY) + ; + + while(size) + { + *(uint32_t *)Page_Address = *(uint32_t *)pbuf; + Page_Address += 4; + pbuf += 1; + size -= 1; + while(FLASH->STATR & SR_WR_BSY) + ; + } + + FLASH->CTLR |= CR_PG_STRT; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_Access_Clock_Cfg + * + * @brief Config FLASH Access Clock(Need to unlock ) + * + * @param FLASH_Access_CLK - + * FLASH_Access_SYSTEM_HALF - System clock/2 + * FLASH_Access_SYSTEM - System clock + * + * @return none + */ +void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK) +{ + FLASH->CTLR &= ~(1 << 25); + FLASH->CTLR |= FLASH_Access_CLK; +} + +/********************************************************************* + * @fn FLASH_Enhance_Mode + * + * @brief Read FLASH Enhance Mode + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return none + */ +void FLASH_Enhance_Mode(FunctionalState NewState) +{ + if(NewState) + { + FLASH->CTLR |= (1 << 24); + } + else + { + FLASH->CTLR &= ~(1 << 24); + FLASH->CTLR |= (1 << 22); + } +} + +/********************************************************************* + * @fn ROM_ERASE + * + * @brief Select erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Cnt - Erases count. + * Erase_Size - Erases size select.The returned value can be: + * Size_32KB, Size_4KB, Size_256B. + * + * @return none. + */ +static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) +{ + do{ + if(Erase_Size == Size_32KB) + { + FLASH->CTLR |= CR_BER32; + } + else if(Erase_Size == Size_4KB) + { + FLASH->CTLR |= CR_PER_Set; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR |= CR_PAGE_ER; + } + + FLASH->ADDR = StartAddr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + + if(Erase_Size == Size_32KB) + { + FLASH->CTLR &= ~CR_BER32; + StartAddr += Size_32KB; + } + else if(Erase_Size == Size_4KB) + { + FLASH->CTLR &= ~CR_PER_Set; + StartAddr += Size_4KB; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR &= ~CR_PAGE_ER; + StartAddr += Size_256B; + } + }while(--Cnt); +} + +/********************************************************************* + * @fn FLASH_ROM_ERASE + * + * @brief Erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Length - Erases Flash start Length(Length%256 == 0). + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length) +{ + uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + Addr0 = StartAddr; + + if(Length >= Size_32KB) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_4KB) + { + Length0 = Size_4KB - (Addr0 & (Size_4KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_256B) + { + Length0 = Length; + } + + /* Erase 32KB */ + if(Length0 >= Size_32KB)//front + { + Length = Length0; + if(Addr0 & (Size_32KB - 1)) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB); + } + + if(Length1 >= Size_32KB)//back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_32KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1))); + Length1 = (StartAddr + Length1) & (Size_32KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB); + } + + /* Erase 4KB */ + if(Length0 >= Size_4KB) //front + { + Length = Length0; + if(Addr0 & (Size_4KB - 1)) + { + Length0 = Size_4KB - (Addr0 & (Size_4KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 12), Size_4KB); + } + + if(Length1 >= Size_4KB) //back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_4KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_4KB - 1))); + Length1 = (StartAddr + Length1) & (Size_4KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 12), Size_4KB); + } + + /* Erase 256B */ + if(Length0)//front + { + ROM_ERASE(Addr0, (Length0 >> 8), Size_256B); + } + + if(Length1)//back + { + ROM_ERASE(Addr1, (Length1 >> 8), Size_256B); + } + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + +/********************************************************************* + * @fn FLASH_ROM_WRITE + * + * @brief Writes a specified FLASH . + * + * @param StartAddr - Writes Flash start address(StartAddr%256 == 0). + * Length - Writes Flash start Length(Length%256 == 0). + * pbuf - Writes Flash value buffer. + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length) +{ + uint32_t i; + uint8_t size; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + i = Length >> 8; + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + do{ + FLASH->CTLR |= CR_PAGE_PG; + while(FLASH->STATR & SR_BSY) + ; + while(FLASH->STATR & SR_WR_BSY) + ; + size = 64; + while(size) + { + *(uint32_t *)StartAddr = *(uint32_t *)pbuf; + StartAddr += 4; + pbuf += 1; + size -= 1; + while(FLASH->STATR & SR_WR_BSY) + ; + } + + FLASH->CTLR |= CR_PG_STRT; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + }while(--i); + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_fsmc.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_fsmc.c index 5dc20f6..bb95db0 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_fsmc.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_fsmc.c @@ -1,503 +1,380 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_fsmc.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the FSMC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_fsmc.h" -#include "ch32v30x_rcc.h" - -/* FSMC BCRx Mask */ -#define BCR_MBKEN_Set ((uint32_t)0x00000001) -#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_Set ((uint32_t)0x00000040) - -/* FSMC PCRx Mask */ -#define PCR_PBKEN_Set ((uint32_t)0x00000004) -#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_Set ((uint32_t)0x00000040) -#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) -#define PCR_MemoryType_NAND ((uint32_t)0x00000008) - -/********************************************************************* - * @fn FSMC_NORSRAMDeInit - * - * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default - * reset values. - * - * @param FSMC_Bank- - * FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1. - * - * @return none - */ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) -{ - if(FSMC_Bank == FSMC_Bank1_NORSRAM1) - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; - } - else - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; - } - FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; - FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; -} - -/********************************************************************* - * @fn FSMC_NANDDeInit - * - * @brief Deinitializes the FSMC NAND Banks registers to their default - * reset values. - * - * @param FSMC_Bank - - * FSMC_Bank2_NAND - FSMC Bank2 NAND. - * - * @return none - */ -void FSMC_NANDDeInit(uint32_t FSMC_Bank) -{ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 = 0x00000018; - FSMC_Bank2->SR2 = 0x00000040; - FSMC_Bank2->PMEM2 = 0xFCFCFCFC; - FSMC_Bank2->PATT2 = 0xFCFCFCFC; - } -} - -/********************************************************************* - * @fn FSMC_NORSRAMInit - * - * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. - * - * @param SMC_NORSRAMInitStruct:pointer to a FSMC_NORSRAMInitTypeDef - * structure that contains the configuration information for the FSMC NOR/SRAM - * specified Banks. - * - * @return none - */ -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct) -{ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | - FSMC_NORSRAMInitStruct->FSMC_MemoryType | - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | - FSMC_NORSRAMInitStruct->FSMC_WrapMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | - FSMC_NORSRAMInitStruct->FSMC_WriteOperation | - FSMC_NORSRAMInitStruct->FSMC_WaitSignal | - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | - FSMC_NORSRAMInitStruct->FSMC_WriteBurst; - - if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) - { - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; - } - - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank + 1] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; - - if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; - } - else - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; - } -} - -/********************************************************************* - * @fn FSMC_NANDInit - * - * @brief Initializes the FSMC NAND Banks according to the specified - * parameters in the FSMC_NANDInitStruct. - * - * @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef - * structure that contains the configuration information for the FSMC - * NAND specified Banks. - * - * @return none - */ -void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | - PCR_MemoryType_NAND | - FSMC_NANDInitStruct->FSMC_MemoryDataWidth | - FSMC_NANDInitStruct->FSMC_ECC | - FSMC_NANDInitStruct->FSMC_ECCPageSize | - (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9) | - (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); - - tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 = tmppcr; - FSMC_Bank2->PMEM2 = tmppmem; - FSMC_Bank2->PATT2 = tmppatt; - } -} - -/********************************************************************* - * @fn FSMC_NORSRAMStructInit - * - * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. - * - * @param FSMC_NORSRAMInitStruct - pointer to a FSMC_NORSRAMInitTypeDef - * structure which will be initialized. - * - * @return none - */ -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct) -{ - FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; - FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; -} - -/********************************************************************* - * @fn FSMC_NANDStructInit - * - * @brief Fills each FSMC_NANDInitStruct member with its default value. - * - * @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef - * structure which will be initialized. - * - * @return none - */ -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct) -{ - FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; - FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; - FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/********************************************************************* - * @fn FSMC_NORSRAMCmd - * - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * - * @param FSMC_Bank - specifies the FSMC Bank to be used - * FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1 - * FSMC_Bank1_NORSRAM2 - FSMC Bank1 NOR/SRAM2 - * FSMC_Bank1_NORSRAM3 - FSMC Bank1 NOR/SRAM3 - * FSMC_Bank1_NORSRAM4 - FSMC Bank1 NOR/SRAM4 - * NewState:ENABLE or DISABLE. - * - * @return none - */ -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; - } - else - { - FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; - } -} - -/********************************************************************* - * @fn FSMC_NANDCmd - * - * @brief Enables or disables the specified NAND Memory Bank. - * - * @param FSMC_Bank - specifies the FSMC Bank to be used - * FSMC_Bank2_NAND - FSMC Bank2 NAND - * FSMC_Bank3_NAND - FSMC Bank3 NAND - * NewStat - ENABLE or DISABLE. - * - * @return none - */ -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; - } - } - else - { - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; - } - } -} - -/********************************************************************* - * @fn FSMC_NANDECCCmd - * - * @brief Enables or disables the FSMC NAND ECC feature. - * - * @param FSMC_Bank - specifies the FSMC Bank to be used - * FSMC_Bank2_NAND - FSMC Bank2 NAND - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; - } - } - else - { - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; - } - } -} - -/********************************************************************* - * @fn FSMC_GetECC - * - * @brief Returns the error correction code register value. - * - * @param FSMC_Bank - specifies the FSMC Bank to be used - * FSMC_Bank2_NAND - FSMC Bank2 NAND - * NewState - ENABLE or DISABLE. - * - * @return eccval - The Error Correction Code (ECC) value. - */ -uint32_t FSMC_GetECC(uint32_t FSMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - eccval = FSMC_Bank2->ECCR2; - } - - return (eccval); -} - -/********************************************************************* - * @fn FSMC_ITConfig - * - * @brief Enables or disables the specified FSMC interrupts. - * - * @param FSMC_Bank - specifies the FSMC Bank to be used - * FSMC_Bank2_NAND - FSMC Bank2 NAND - * FSMC_IT - specifies the FSMC interrupt sources to be enabled or disabled. - * FSMC_IT_RisingEdge - Rising edge detection interrupt. - * FSMC_IT_Level - Level edge detection interrupt. - * FSMC_IT_FallingEdge - Falling edge detection interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 |= FSMC_IT; - } - } - else - { - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; - } - } -} - -/********************************************************************* - * @fn FSMC_GetFlagStatus - * - * @brief Checks whether the specified FSMC flag is set or not. - * - * @param FSMC_Bank - specifies the FSMC Bank to be used - * FSMC_Bank2_NAND - FSMC Bank2 NAND - * FSMC_FLAG - specifies the flag to check. - * FSMC_FLAG_RisingEdge - Rising egde detection Flag. - * FSMC_FLAG_Level - Level detection Flag. - * FSMC_FLAG_FallingEdge - Falling egde detection Flag. - * FSMC_FLAG_FEMPT - Fifo empty Flag. - * NewState - ENABLE or DISABLE. - * - * @return FlagStatus - The new state of FSMC_FLAG (SET or RESET). - */ -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - - if((tmpsr & FSMC_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn FSMC_ClearFlag - * - * @brief Clears the FSMC's pending flags. - * - * @param FSMC_Bank - specifies the FSMC Bank to be used - * FSMC_Bank2_NAND - FSMC Bank2 NAND - * FSMC_FLAG - specifies the flag to check. - * FSMC_FLAG_RisingEdge - Rising egde detection Flag. - * FSMC_FLAG_Level - Level detection Flag. - * FSMC_FLAG_FallingEdge - Falling egde detection Flag. - * - * @return none - */ -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~FSMC_FLAG; - } -} - -/********************************************************************* - * @fn FSMC_GetITStatus - * - * @brief Checks whether the specified FSMC interrupt has occurred or not. - * - * @param FSMC_Bank - specifies the FSMC Bank to be used - * FSMC_Bank2_NAND - FSMC Bank2 NAND - * FSMC_IT - specifies the FSMC interrupt source to check. - * FSMC_IT_RisingEdge - Rising edge detection interrupt. - * FSMC_IT_Level - Level edge detection interrupt. - * FSMC_IT_FallingEdge - Falling edge detection interrupt. - * - * @return ITStatus - The new state of FSMC_IT (SET or RESET). - */ -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - - itstatus = tmpsr & FSMC_IT; - - itenable = tmpsr & (FSMC_IT >> 3); - if((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn FSMC_ClearITPendingBit - * - * @brief Clears the FSMC's interrupt pending bits. - * - * @param FSMC_Bank - specifies the FSMC Bank to be used - * FSMC_Bank2_NAND - FSMC Bank2 NAND - * FSMC_IT - specifies the FSMC interrupt source to check. - * FSMC_IT_RisingEdge - Rising edge detection interrupt. - * FSMC_IT_Level - Level edge detection interrupt. - * FSMC_IT_FallingEdge - Falling edge detection interrupt. - * - * @return none - */ -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); - } -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_fsmc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file provides all the FSMC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_fsmc.h" +#include "ch32v30x_rcc.h" + +/* FSMC BCRx Mask */ +#define BCR_MBKEN_Set ((uint32_t)0x00000001) +#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_Set ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_Set ((uint32_t)0x00000004) +#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_Set ((uint32_t)0x00000040) +#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) +#define PCR_MemoryType_NAND ((uint32_t)0x00000008) + +/********************************************************************* + * @fn FSMC_NORSRAMDeInit + * + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * + * @param FSMC_Bank- + * FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1. + * + * @return none + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/********************************************************************* + * @fn FSMC_NANDDeInit + * + * @brief Deinitializes the FSMC NAND Banks registers to their default + * reset values. + * + * @param FSMC_Bank - + * FSMC_Bank2_NAND - FSMC Bank2 NAND. + * + * @return none + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } +} + +/********************************************************************* + * @fn FSMC_NORSRAMInit + * + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * + * @param SMC_NORSRAMInitStruct:pointer to a FSMC_NORSRAMInitTypeDef + * structure that contains the configuration information for the FSMC NOR/SRAM + * specified Banks. + * + * @return none + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct) +{ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; + } + + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank + 1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/********************************************************************* + * @fn FSMC_NANDInit + * + * @brief Initializes the FSMC NAND Banks according to the specified + * parameters in the FSMC_NANDInitStruct. + * + * @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef + * structure that contains the configuration information for the FSMC + * NAND specified Banks. + * + * @return none + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MemoryType_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } +} + +/********************************************************************* + * @fn FSMC_NORSRAMStructInit + * + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * + * @param FSMC_NORSRAMInitStruct - pointer to a FSMC_NORSRAMInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct) +{ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/********************************************************************* + * @fn FSMC_NANDStructInit + * + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * + * @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct) +{ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/********************************************************************* + * @fn FSMC_NORSRAMCmd + * + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1 + * FSMC_Bank1_NORSRAM2 - FSMC Bank1 NOR/SRAM2 + * FSMC_Bank1_NORSRAM3 - FSMC Bank1 NOR/SRAM3 + * FSMC_Bank1_NORSRAM4 - FSMC Bank1 NOR/SRAM4 + * NewState:ENABLE or DISABLE. + * + * @return none + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; + } + else + { + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; + } +} + +/********************************************************************* + * @fn FSMC_NANDCmd + * + * @brief Enables or disables the specified NAND Memory Bank. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * NewStat - ENABLE or DISABLE. + * + * @return none + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; + } + } + else + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; + } + } +} + +/********************************************************************* + * @fn FSMC_NANDECCCmd + * + * @brief Enables or disables the FSMC NAND ECC feature. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; + } + } + else + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; + } + } +} + +/********************************************************************* + * @fn FSMC_GetECC + * + * @brief Returns the error correction code register value. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * NewState - ENABLE or DISABLE. + * + * @return eccval - The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + eccval = FSMC_Bank2->ECCR2; + } + + return (eccval); +} + +/********************************************************************* + * @fn FSMC_GetFlagStatus + * + * @brief Checks whether the specified FSMC flag is set or not. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_FLAG - specifies the flag to check. + * FSMC_FLAG_FEMPT - Fifo empty Flag. + * NewState - ENABLE or DISABLE. + * + * @return FlagStatus - The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + + if((tmpsr & FSMC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_gpio.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_gpio.c index b947940..c5cf381 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_gpio.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_gpio.c @@ -1,568 +1,895 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_gpio.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the GPIO firmware functions. -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_gpio.h" -#include "ch32v30x_rcc.h" - -/* MASK */ -#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) - -/********************************************************************* - * @fn GPIO_DeInit - * - * @brief Deinitializes the GPIOx peripheral registers to their default - * reset values. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @return none - */ -void GPIO_DeInit(GPIO_TypeDef *GPIOx) -{ - if(GPIOx == GPIOA) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); - } - else if(GPIOx == GPIOB) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); - } - else if(GPIOx == GPIOC) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); - } - else if(GPIOx == GPIOD) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); - } - else if(GPIOx == GPIOE) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); - } -} - -/********************************************************************* - * @fn GPIO_AFIODeInit - * - * @brief Deinitializes the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * - * @return none - */ -void GPIO_AFIODeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); -} - -/********************************************************************* - * @fn GPIO_Init - * - * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. - * - * @return none - */ -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - - if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - { - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } - - if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) - { - tmpreg = GPIOx->CFGLR; - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << pinpos); - } - else - { - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CFGLR = tmpreg; - } - - if(GPIO_InitStruct->GPIO_Pin > 0x00FF) - { - tmpreg = GPIOx->CFGHR; - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x08)); - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - } - } - GPIOx->CFGHR = tmpreg; - } -} - -/********************************************************************* - * @fn GPIO_StructInit - * - * @brief Fills each GPIO_InitStruct member with its default - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) -{ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/********************************************************************* - * @fn GPIO_ReadInputDataBit - * - * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @param GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * - * @return The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadInputData - * - * @brief Reads the specified GPIO input data port. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @return The output port pin value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) -{ - return ((uint16_t)GPIOx->INDR); -} - -/********************************************************************* - * @fn GPIO_ReadOutputDataBit - * - * @brief Reads the specified output data port bit. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadOutputData - * - * @brief Reads the specified GPIO output data port. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @return GPIO output port pin value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) -{ - return ((uint16_t)GPIOx->OUTDR); -} - -/********************************************************************* - * @fn GPIO_SetBits - * - * @brief Sets the selected data port bits. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BSHR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_ResetBits - * - * @brief Clears the selected data port bits. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BCR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_WriteBit - * - * @brief Sets or clears the selected data port bit. - * - * @param GPIO_Pin - specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * BitVal - specifies the value to be written to the selected bit. - * Bit_RESET - to clear the port pin. - * Bit_SET - to set the port pin. - * - * @return none - */ -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - if(BitVal != Bit_RESET) - { - GPIOx->BSHR = GPIO_Pin; - } - else - { - GPIOx->BCR = GPIO_Pin; - } -} - -/********************************************************************* - * @fn GPIO_Write - * - * @brief Writes data to the specified GPIO data port. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * PortVal - specifies the value to be written to the port output data register. - * - * @return none - */ -void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) -{ - GPIOx->OUTDR = PortVal; -} - -/********************************************************************* - * @fn GPIO_PinLockConfig - * - * @brief Locks GPIO Pins configuration registers. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - - tmp |= GPIO_Pin; - GPIOx->LCKR = tmp; - GPIOx->LCKR = GPIO_Pin; - GPIOx->LCKR = tmp; - tmp = GPIOx->LCKR; - tmp = GPIOx->LCKR; -} - -/********************************************************************* - * @fn GPIO_EventOutputConfig - * - * @brief Selects the GPIO pin used as Event output. - * - * @param GPIO_PortSource - selects the GPIO port to be used as source - * for Event output. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). - * GPIO_PinSource - specifies the pin for the Event output. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * - * @return none - */ -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmpreg = 0x00; - - tmpreg = AFIO->ECR; - tmpreg &= ECR_PORTPINCONFIG_MASK; - tmpreg |= (uint32_t)GPIO_PortSource << 0x04; - tmpreg |= GPIO_PinSource; - AFIO->ECR = tmpreg; -} - -/********************************************************************* - * @fn GPIO_EventOutputCmd - * - * @brief Enables or disables the Event Output. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void GPIO_EventOutputCmd(FunctionalState NewState) -{ - if(NewState) - { - AFIO->ECR |= (1 << 7); - } - else - { - AFIO->ECR &= ~(1 << 7); - } -} - -/********************************************************************* - * @fn GPIO_PinRemapConfig - * - * @brief Changes the mapping of the specified pin. - * - * @param GPIO_Remap - selects the pin to remap. - * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping - * GPIO_Remap_I2C1 - I2C1 Alternate Function mapping - * GPIO_Remap_USART1 - USART1 Alternate Function mapping - * GPIO_Remap_USART2 - USART2 Alternate Function mapping - * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping - * GPIO_PartialRemap1_USART3 - USART3 Partial1 Alternate Function mapping - * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping - * GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping - * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping - * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping - * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping - * GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping - * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping - * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping - * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping - * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping - * GPIO_Remap_PD01 - PD01 Alternate Function mapping - * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping - * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping - * GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping - * GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping - * GPIO_Remap_ETH - Ethernet remapping - * GPIO_Remap_CAN2 - CAN2 remapping - * GPIO_Remap_MII_RMII_SEL - MII or RMII selection - * GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST - * GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled - * GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP) - * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected - * to TIM2 Internal Trigger 1 for calibration - * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) - * GPIO_Remap_TIM8 - TIM8 Alternate Function mapping - * GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping - * GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping - * GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping - * GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping - * GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping - * GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping - * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping - * GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping - * GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping - * GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping - * GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping - * GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping - * GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping - * GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping - * GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping - * GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) -{ - uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - tmpreg = AFIO->PCFR2; - } - else - { - tmpreg = AFIO->PCFR1; - } - - tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - tmp = GPIO_Remap & LSB_MASK; - - /* Clear bit */ - if((GPIO_Remap & 0x80000000) == 0x80000000) - { /* PCFR2 */ - if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */ - { - tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10); - tmpreg &= ~tmp1; - } - else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - } - else /* [31:0] 1bit */ - { - tmpreg &= ~(tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10)); - } - } - else - { /* PCFR1 */ - if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */ - { - tmpreg &= DBGAFR_SWJCFG_MASK; - AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; - } - else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - else /* [31:0] 1bit */ - { - tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - } - - /* Set bit */ - if(NewState != DISABLE) - { - tmpreg |= (tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10)); - } - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - AFIO->PCFR2 = tmpreg; - } - else - { - AFIO->PCFR1 = tmpreg; - } -} - -/********************************************************************* - * @fn GPIO_EXTILineConfig - * - * @brief Selects the GPIO pin used as EXTI Line. - * - * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). - * GPIO_PinSource - specifies the EXTI line to be configured. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * - * @return none - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmp = 0x00; - - tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); - AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; - AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); -} - -/********************************************************************* - * @fn GPIO_ETH_MediaInterfaceConfig - * - * @brief Selects the Ethernet media interface. - * - * @param GPIO_ETH_MediaInterface - specifies the Media Interface mode. - * GPIO_ETH_MediaInterface_MII - MII mode - * GPIO_ETH_MediaInterface_RMII - RMII mode - * - * @return none - */ -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) -{ - if(GPIO_ETH_MediaInterface) - { - AFIO->PCFR1 |= (1 << 23); - } - else - { - AFIO->PCFR1 &= ~(1 << 23); - } -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_gpio.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/06 +* Description : This file provides all the GPIO firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_gpio.h" +#include "ch32v30x_rcc.h" + +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if(GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } + + if(GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CFGHR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CFGHR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return The output port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->INDR); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->OUTDR); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BSHR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * BitVal - specifies the value to be written to the selected bit. + * Bit_RESET - to clear the port pin. + * Bit_SET - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = GPIO_Pin; + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_EventOutputConfig + * + * @brief Selects the GPIO pin used as Event output. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * GPIO_PinSource - specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + + tmpreg = AFIO->ECR; + tmpreg &= ECR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->ECR = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EventOutputCmd + * + * @brief Enables or disables the Event Output. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + if(NewState) + { + AFIO->ECR |= (1 << 7); + } + else + { + AFIO->ECR &= ~(1 << 7); + } +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping + * GPIO_Remap_SPI3 - SPI3 Alternate Function mapping(CH32V30X_D8,CH32V30X_D8C) + * GPIO_Remap_I2C1 - I2C1 Alternate Function mapping + * GPIO_Remap_USART1 - USART1 Alternate Function mapping + * GPIO_Remap_USART2 - USART2 Alternate Function mapping + * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping + * GPIO_PartialRemap1_USART3 - USART3 Partial1 Alternate Function mapping + * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping + * GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping + * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping + * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping + * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap_PD0PD1 - PD0 and PD1 Alternate Function mapping + * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping + * GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping + * GPIO_Remap_ETH - Ethernet remapping + * GPIO_Remap_CAN2 - CAN2 remapping + * GPIO_Remap_MII_RMII_SEL - MII or RMII selection + * GPIO_Remap_SWJ_Disable - Full SWJ Disabled + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected + * to TIM2 Internal Trigger 1 for calibration + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) + * GPIO_Remap_TIM8 - TIM8 Alternate Function mapping + * GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping + * GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping + * GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping + * GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping + * GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping + * GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping + * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping + * GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping + * GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping + * GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping + * GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping + * GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping + * GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping + * GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping + * GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping + * GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->PCFR2; + } + else + { + tmpreg = AFIO->PCFR1; + } + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + /* Clear bit */ + if((GPIO_Remap & 0x80000000) == 0x80000000) + { /* PCFR2 */ + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */ + { + tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10); + tmpreg &= ~tmp1; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + } + else /* [31:0] 1bit */ + { + tmpreg &= ~(tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10)); + } + } + else + { /* PCFR1 */ + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */ + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else /* [31:0] 1bit */ + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg |= (tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10)); + } + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->PCFR2 = tmpreg; + } + else + { + AFIO->PCFR1 = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/********************************************************************* + * @fn GPIO_ETH_MediaInterfaceConfig + * + * @brief Selects the Ethernet media interface. + * + * @param GPIO_ETH_MediaInterface - specifies the Media Interface mode. + * GPIO_ETH_MediaInterface_MII - MII mode + * GPIO_ETH_MediaInterface_RMII - RMII mode + * + * @return none + */ +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) +{ + if(GPIO_ETH_MediaInterface) + { + AFIO->PCFR1 |= (1 << 23); + } + else + { + AFIO->PCFR1 &= ~(1 << 23); + } +} +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-down. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC|\ + RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE, ENABLE); + chip = *( uint32_t * )0x1FFFF704 & (~0x000000F0); + switch(chip) + { +#ifdef CH32V30x_D8 + case 0x30330504: //CH32V303CBT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30320504: //CH32V303RBT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30310504: //CH32V303RCT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30300504: //CH32V303VCT6 + { + break; + } +#elif defined (CH32V30x_D8C) + case 0x30520508: //CH32V305FBP6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_8|GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x305C0508: //CH32V305CCT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30500508: //CH32V305RBT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30710508: //CH32V307RCT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30730508: //CH32V307WCU6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x3173B508: //CH32V317WCU6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x3175B508: //CH32V317TCU6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_10; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30700508: //CH32V307VCT6 + { + break; + } + case 0x3170B508: //CH32V317VCT6 + { + break; + } +#endif + default: + { + break; + } + } +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_i2c.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_i2c.c index 9150d4e..2b6fab4 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_i2c.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_i2c.c @@ -1,1008 +1,1012 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_i2c.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the I2C firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_i2c.h" -#include "ch32v30x_rcc.h" - -/* I2C SPE mask */ -#define CTLR1_PE_Set ((uint16_t)0x0001) -#define CTLR1_PE_Reset ((uint16_t)0xFFFE) - -/* I2C START mask */ -#define CTLR1_START_Set ((uint16_t)0x0100) -#define CTLR1_START_Reset ((uint16_t)0xFEFF) - -/* I2C STOP mask */ -#define CTLR1_STOP_Set ((uint16_t)0x0200) -#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) - -/* I2C ACK mask */ -#define CTLR1_ACK_Set ((uint16_t)0x0400) -#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) - -/* I2C ENGC mask */ -#define CTLR1_ENGC_Set ((uint16_t)0x0040) -#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) - -/* I2C SWRST mask */ -#define CTLR1_SWRST_Set ((uint16_t)0x8000) -#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) - -/* I2C PEC mask */ -#define CTLR1_PEC_Set ((uint16_t)0x1000) -#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) - -/* I2C ENPEC mask */ -#define CTLR1_ENPEC_Set ((uint16_t)0x0020) -#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) - -/* I2C ENARP mask */ -#define CTLR1_ENARP_Set ((uint16_t)0x0010) -#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) - -/* I2C NOSTRETCH mask */ -#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) -#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) - -/* I2C registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) - -/* I2C DMAEN mask */ -#define CTLR2_DMAEN_Set ((uint16_t)0x0800) -#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) - -/* I2C LAST mask */ -#define CTLR2_LAST_Set ((uint16_t)0x1000) -#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) - -/* I2C FREQ mask */ -#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) - -/* I2C ADD0 mask */ -#define OADDR1_ADD0_Set ((uint16_t)0x0001) -#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) - -/* I2C ENDUAL mask */ -#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) -#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) - -/* I2C ADD2 mask */ -#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) - -/* I2C F/S mask */ -#define CKCFGR_FS_Set ((uint16_t)0x8000) - -/* I2C CCR mask */ -#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) - -/* I2C FLAG mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) - -/* I2C Interrupt Enable mask */ -#define ITEN_Mask ((uint32_t)0x07000000) - -/********************************************************************* - * @fn I2C_DeInit - * - * @brief Deinitializes the I2Cx peripheral registers to their default - * reset values. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return none - */ -void I2C_DeInit(I2C_TypeDef *I2Cx) -{ - if(I2Cx == I2C1) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); - } - else - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); - } -} - -/********************************************************************* - * @fn I2C_Init - * - * @brief Initializes the I2Cx peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified I2C peripheral. - * - * @return none - */ -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) -{ - uint16_t tmpreg = 0, freqrange = 0; - uint16_t result = 0x04; - uint32_t pclk1 = 8000000; - - RCC_ClocksTypeDef rcc_clocks; - - tmpreg = I2Cx->CTLR2; - tmpreg &= CTLR2_FREQ_Reset; - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - I2Cx->CTLR2 = tmpreg; - - I2Cx->CTLR1 &= CTLR1_PE_Reset; - tmpreg = 0; - - if(I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - - if(result < 0x04) - { - result = 0x04; - } - - tmpreg |= result; - I2Cx->RTR = freqrange + 1; - } - else - { - if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - result |= I2C_DutyCycle_16_9; - } - - if((result & CKCFGR_CCR_Set) == 0) - { - result |= (uint16_t)0x0001; - } - - tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); - I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - I2Cx->CKCFGR = tmpreg; - I2Cx->CTLR1 |= CTLR1_PE_Set; - - tmpreg = I2Cx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - I2Cx->CTLR1 = tmpreg; - - I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/********************************************************************* - * @fn I2C_StructInit - * - * @brief Fills each I2C_InitStruct member with its default value. - * - * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) -{ - I2C_InitStruct->I2C_ClockSpeed = 5000; - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStruct->I2C_OwnAddress1 = 0; - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/********************************************************************* - * @fn I2C_Cmd - * - * @brief Enables or disables the specified I2C peripheral. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PE_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PE_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMACmd - * - * @brief Enables or disables the specified I2C DMA requests. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_DMAEN_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMALastTransferCmd - * - * @brief Specifies if the next DMA transfer will be the last one. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_LAST_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_LAST_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTART - * - * @brief Generates I2Cx communication START condition. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_START_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_START_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTOP - * - * @brief Generates I2Cx communication STOP condition. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_STOP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_STOP_Reset; - } -} - -/********************************************************************* - * @fn I2C_AcknowledgeConfig - * - * @brief Enables or disables the specified I2C acknowledge feature. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ACK_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ACK_Reset; - } -} - -/********************************************************************* - * @fn I2C_OwnAddress2Config - * - * @brief Configures the specified I2C own address2. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * Address - specifies the 7bit I2C own address2. - * - * @return none - */ -void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - tmpreg = I2Cx->OADDR2; - tmpreg &= OADDR2_ADD2_Reset; - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - I2Cx->OADDR2 = tmpreg; -} - -/********************************************************************* - * @fn I2C_DualAddressCmd - * - * @brief Enables or disables the specified I2C dual addressing mode. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; - } - else - { - I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; - } -} - -/********************************************************************* - * @fn I2C_GeneralCallCmd - * - * @brief Enables or disables the specified I2C general call feature. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENGC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENGC_Reset; - } -} - -/********************************************************************* - * @fn I2C_ITConfig - * - * @brief Enables or disables the specified I2C interrupts. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. - * I2C_IT_BUF - Buffer interrupt mask. - * I2C_IT_EVT - Event interrupt mask. - * I2C_IT_ERR - Error interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= I2C_IT; - } - else - { - I2Cx->CTLR2 &= (uint16_t)~I2C_IT; - } -} - -/********************************************************************* - * @fn I2C_SendData - * - * @brief Sends a data byte through the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * Data - Byte to be transmitted. - * - * @return none - */ -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) -{ - I2Cx->DATAR = Data; -} - -/********************************************************************* - * @fn I2C_ReceiveData - * - * @brief Returns the most recent received data by the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) -{ - return (uint8_t)I2Cx->DATAR; -} - -/********************************************************************* - * @fn I2C_Send7bitAddress - * - * @brief Transmits the address byte to select the slave device. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * Address - specifies the slave address which will be transmitted. - * I2C_Direction - specifies whether the I2C device will be a - * Transmitter or a Receiver. - * I2C_Direction_Transmitter - Transmitter mode. - * I2C_Direction_Receiver - Receiver mode. - * - * @return none - */ -void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - if(I2C_Direction != I2C_Direction_Transmitter) - { - Address |= OADDR1_ADD0_Set; - } - else - { - Address &= OADDR1_ADD0_Reset; - } - - I2Cx->DATAR = Address; -} - -/********************************************************************* - * @fn I2C_ReadRegister - * - * @brief Reads the specified I2C register and returns its value. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_Register - specifies the register to read. - * I2C_Register_CTLR1. - * I2C_Register_CTLR2. - * I2C_Register_OADDR1. - * I2C_Register_OADDR2. - * I2C_Register_DATAR. - * I2C_Register_STAR1. - * I2C_Register_STAR2. - * I2C_Register_CKCFGR. - * I2C_Register_RTR. - * - * @return none - */ -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)I2Cx; - tmp += I2C_Register; - - return (*(__IO uint16_t *)tmp); -} - -/********************************************************************* - * @fn I2C_SoftwareResetCmd - * - * @brief Enables or disables the specified I2C software reset. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_SWRST_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_SWRST_Reset; - } -} - -/********************************************************************* - * @fn I2C_NACKPositionConfig - * - * @brief Selects the specified I2C NACK position in master receiver mode. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_NACKPosition - specifies the NACK position. - * I2C_NACKPosition_Next - indicates that the next byte will be - * the last received byte. - * I2C_NACKPosition_Current - indicates that current byte is the - * last received byte. - * Note- - * This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * @return none - */ -void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) -{ - if(I2C_NACKPosition == I2C_NACKPosition_Next) - { - I2Cx->CTLR1 |= I2C_NACKPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_NACKPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_SMBusAlertConfig - * - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_SMBusAlert - specifies SMBAlert pin level. - * I2C_SMBusAlert_Low - SMBAlert pin driven low. - * I2C_SMBusAlert_High - SMBAlert pin driven high. - * - * @return none - */ -void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert) -{ - if(I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - I2Cx->CTLR1 |= I2C_SMBusAlert_Low; - } - else - { - I2Cx->CTLR1 &= I2C_SMBusAlert_High; - } -} - -/********************************************************************* - * @fn I2C_TransmitPEC - * - * @brief Enables or disables the specified I2C PEC transfer. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_PECPositionConfig - * - * @brief Selects the specified I2C PEC position. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_PECPosition - specifies the PEC position. - * I2C_PECPosition_Next - indicates that the next byte is PEC. - * I2C_PECPosition_Current - indicates that current byte is PEC. - * - * @return none - */ -void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) -{ - if(I2C_PECPosition == I2C_PECPosition_Next) - { - I2Cx->CTLR1 |= I2C_PECPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_PECPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_CalculatePEC - * - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * - * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENPEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_GetPEC - * - * @brief Returns the PEC value for the specified I2C. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) -{ - return ((I2Cx->STAR2) >> 8); -} - -/********************************************************************* - * @fn I2C_ARPCmd - * - * @brief Enables or disables the specified I2C ARP. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return The PEC value. - */ -void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENARP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENARP_Reset; - } -} - -/********************************************************************* - * @fn I2C_StretchClockCmd - * - * @brief Enables or disables the specified I2C Clock stretching. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState == DISABLE) - { - I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; - } -} - -/********************************************************************* - * @fn I2C_FastModeDutyCycleConfig - * - * @brief Selects the specified I2C fast mode duty cycle. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_DutyCycle - specifies the fast mode duty cycle. - * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. - * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. - * - * @return none - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) -{ - if(I2C_DutyCycle != I2C_DutyCycle_16_9) - { - I2Cx->CKCFGR &= I2C_DutyCycle_2; - } - else - { - I2Cx->CKCFGR |= I2C_DutyCycle_16_9; - } -} - -/********************************************************************* - * @fn I2C_CheckEvent - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. - * I2C_EVENT: specifies the event to be checked. - * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. - * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. - * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. - * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. - * I2C_EVENT_MASTER_MODE_SELECT - EVT5. - * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. - * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. - * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. - * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. - * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. - * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. - * - * @return ErrorStatus - READY or NoREADY. - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = NoREADY; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - - lastevent = (flag1 | flag2) & FLAG_Mask; - - if((lastevent & I2C_EVENT) == I2C_EVENT) - { - status = READY; - } - else - { - status = NoREADY; - } - - return status; -} - -/********************************************************************* - * @fn I2C_GetLastEvent - * - * @brief Returns the last I2Cx Event. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * - * @return none - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - lastevent = (flag1 | flag2) & FLAG_Mask; - - return lastevent; -} - -/********************************************************************* - * @fn I2C_GetFlagStatus - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to check. - * I2C_FLAG_DUALF - Dual flag (Slave mode). - * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). - * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). - * I2C_FLAG_GENCALL - General call header flag (Slave mode). - * I2C_FLAG_TRA - Transmitter/Receiver flag. - * I2C_FLAG_BUSY - Bus busy flag. - * I2C_FLAG_MSL - Master/Slave flag. - * I2C_FLAG_SMBALERT - SMBus Alert flag. - * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * I2C_FLAG_TXE - Data register empty flag (Transmitter). - * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. - * I2C_FLAG_STOPF - Stop detection flag (Slave mode). - * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). - * I2C_FLAG_BTF - Byte transfer finished flag. - * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDA". - * I2C_FLAG_SB - Start bit flag (Master mode). - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - i2cxbase = (uint32_t)I2Cx; - i2creg = I2C_FLAG >> 28; - I2C_FLAG &= FLAG_Mask; - - if(i2creg != 0) - { - i2cxbase += 0x14; - } - else - { - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearFlag - * - * @brief Clears the I2Cx's pending flags. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to clear. - * I2C_FLAG_SMBALERT - SMBus Alert flag. - * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * Note- - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DATAR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DATAR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SATR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR - * register (I2C_SendData()). - * @return none - */ -void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - - flagpos = I2C_FLAG & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} - -/********************************************************************* - * @fn I2C_GetITStatus - * - * @brief Checks whether the specified I2C interrupt has occurred or not. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * II2C_IT - specifies the interrupt source to check. - * I2C_IT_SMBALERT - SMBus Alert flag. - * I2C_IT_TIMEOUT - Timeout or Tlow error flag. - * I2C_IT_PECERR - PEC error in reception flag. - * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). - * I2C_IT_AF - Acknowledge failure flag. - * I2C_IT_ARLO - Arbitration lost flag (Master mode). - * I2C_IT_BERR - Bus error flag. - * I2C_IT_TXE - Data register empty flag (Transmitter). - * I2C_IT_RXNE - Data register not empty (Receiver) flag. - * I2C_IT_STOPF - Stop detection flag (Slave mode). - * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). - * I2C_IT_BTF - Byte transfer finished flag. - * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched - * flag (Slave mode)"ENDAD". - * I2C_IT_SB - Start bit flag (Master mode). - * - * @return none - */ -ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); - I2C_IT &= FLAG_Mask; - - if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearITPendingBit - * - * @brief Clears the I2Cx interrupt pending bits. - * - * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. - * I2C_IT - specifies the interrupt pending bit to clear. - * I2C_IT_SMBALERT - SMBus Alert interrupt. - * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. - * I2C_IT_PECERR - PEC error in reception interrupt. - * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). - * I2C_IT_AF - Acknowledge failure interrupt. - * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). - * I2C_IT_BERR - Bus error interrupt. - * Note- - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DATAR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DATAR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_STAR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DATAR register (I2C_SendData()). - * - * @return none - */ -void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - - flagpos = I2C_IT & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_i2c.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file provides all the I2C firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_i2c.h" +#include "ch32v30x_rcc.h" + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } + else + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + if(freqrange >= 60) + { + freqrange = 60; + } + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + I2Cx->RTR = freqrange + 1; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * I2C_Register_RTR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * Note- + * This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_SMBusAlertConfig + * + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_SMBusAlert - specifies SMBAlert pin level. + * I2C_SMBusAlert_Low - SMBAlert pin driven low. + * I2C_SMBusAlert_High - SMBAlert pin driven high. + * + * @return none + */ +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert) +{ + if(I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + I2Cx->CTLR1 |= I2C_SMBusAlert_Low; + } + else + { + I2Cx->CTLR1 &= I2C_SMBusAlert_High; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. + * I2C_EVENT_MASTER_MODE_SELECT - EVT5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. + * + * @return ErrorStatus - READY or NoREADY. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = NoREADY; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = READY; + } + else + { + status = NoREADY; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). + * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SATR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR + * register (I2C_SendData()). + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_SMBALERT - SMBus Alert flag. + * I2C_IT_TIMEOUT - Timeout or Tlow error flag. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_SMBALERT - SMBus Alert interrupt. + * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_STAR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DATAR register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_iwdg.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_iwdg.c index 9c20578..a647ed7 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_iwdg.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_iwdg.c @@ -1,122 +1,123 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_iwdg.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the IWDG firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_iwdg.h" - -/* CTLR register bit mask */ -#define CTLR_KEY_Reload ((uint16_t)0xAAAA) -#define CTLR_KEY_Enable ((uint16_t)0xCCCC) - -/********************************************************************* - * @fn IWDG_WriteAccessCmd - * - * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. - * - * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR - * and IWDG_RLDR registers. - * - * @return none - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - IWDG->CTLR = IWDG_WriteAccess; -} - -/********************************************************************* - * @fn IWDG_SetPrescaler - * - * @brief Sets IWDG Prescaler value. - * - * @param IWDG_Prescaler - specifies the IWDG Prescaler value. - * IWDG_Prescaler_4 - IWDG prescaler set to 4. - * IWDG_Prescaler_8 - IWDG prescaler set to 8. - * IWDG_Prescaler_16 - IWDG prescaler set to 16. - * IWDG_Prescaler_32 - IWDG prescaler set to 32. - * IWDG_Prescaler_64 - IWDG prescaler set to 64. - * IWDG_Prescaler_128 - IWDG prescaler set to 128. - * IWDG_Prescaler_256 - IWDG prescaler set to 256. - * - * @return none - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - IWDG->PSCR = IWDG_Prescaler; -} - -/********************************************************************* - * @fn IWDG_SetReload - * - * @brief Sets IWDG Reload value. - * - * @param Reload - specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * - * @return none - */ -void IWDG_SetReload(uint16_t Reload) -{ - IWDG->RLDR = Reload; -} - -/********************************************************************* - * @fn IWDG_ReloadCounter - * - * @brief Reloads IWDG counter with value defined in the reload register. - * - * @return none - */ -void IWDG_ReloadCounter(void) -{ - IWDG->CTLR = CTLR_KEY_Reload; -} - -/********************************************************************* - * @fn IWDG_Enable - * - * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). - * - * @return none - */ -void IWDG_Enable(void) -{ - IWDG->CTLR = CTLR_KEY_Enable; -} - -/********************************************************************* - * @fn IWDG_GetFlagStatus - * - * @brief Checks whether the specified IWDG flag is set or not. - * - * @param IWDG_FLAG - specifies the flag to check. - * IWDG_FLAG_PVU - Prescaler Value Update on going. - * IWDG_FLAG_RVU - Reload Value Update on going. - * - * @return none - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_iwdg.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file provides all the IWDG firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_iwdg.h" + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; + while((RCC->RSTSCKR & 0x2)==RESET); +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_misc.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_misc.c index 162cc45..59bdc21 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_misc.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_misc.c @@ -1,109 +1,105 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_misc.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the miscellaneous firmware functions . -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_misc.h" - -__IO uint32_t NVIC_Priority_Group = 0; - -/********************************************************************* - * @fn NVIC_PriorityGroupConfig - * - * @brief Configures the priority grouping - pre-emption priority and subpriority. - * - * @param NVIC_PriorityGroup - specifies the priority grouping bits length. - * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority - * 4 bits for subpriority - * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority - * 3 bits for subpriority - * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority - * 2 bits for subpriority - * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority - * 1 bits for subpriority - * NVIC_PriorityGroup_4 - 4 bits for pre-emption priority - * 0 bits for subpriority - * - * @return none - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - NVIC_Priority_Group = NVIC_PriorityGroup; -} - -/********************************************************************* - * @fn NVIC_Init - * - * @brief Initializes the NVIC peripheral according to the specified parameters in - * the NVIC_InitStruct. - * - * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the - * configuration information for the specified NVIC peripheral. - * - * @return none - */ -void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) -{ - uint8_t tmppre = 0; - - if(NVIC_Priority_Group == NVIC_PriorityGroup_0) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); - } - else - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); - } - else - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3) - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); - } - else - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4)); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_4) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4); - } - - if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } - else - { - NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_misc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file provides all the miscellaneous firmware functions . +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_misc.h" + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 3 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 2 bits for subpriority + * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority + * 1 bits for subpriority + * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority + * 0 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + * interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 3. + * NVIC_IRQChannelSubPriority - range from 0 to 1. + * + * interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 7. + * NVIC_IRQChannelSubPriority - range range is 0. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); + } +#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_2Level) + if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority < 2) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + } +#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_4Level) + if(NVIC_Priority_Group == NVIC_PriorityGroup_2) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority < 4) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 6) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + } +#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_8Level) + if(NVIC_Priority_Group == NVIC_PriorityGroup_3) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority < 8) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 5) ); + } + } +#endif + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_opa.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_opa.c index ed84c00..b102200 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_opa.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_opa.c @@ -1,86 +1,86 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_opa.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the OPA firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_opa.h" - -#define OPA_MASK ((uint32_t)0x000F) -#define OPA_Total_NUM 4 - -/********************************************************************* - * @fn OPA_DeInit - * - * @brief Deinitializes the OPA peripheral registers to their default - * reset values. - * - * @return none - */ -void OPA_DeInit(void) -{ - OPA->CR = 0; -} - -/********************************************************************* - * @fn OPA_Init - * - * @brief Initializes the OPA peripheral according to the specified - * parameters in the OPA_InitStruct. - * - * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure - * - * @return none - */ -void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) -{ - uint32_t tmp = 0; - tmp = OPA->CR; - tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); - tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); - OPA->CR = tmp; -} - -/********************************************************************* - * @fn OPA_StructInit - * - * @brief Fills each OPA_StructInit member with its reset value. - * - * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure - * - * @return none - */ -void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) -{ - OPA_InitStruct->Mode = OUT_IO_OUT1; - OPA_InitStruct->PSEL = CHP0; - OPA_InitStruct->NSEL = CHN0; - OPA_InitStruct->OPA_NUM = OPA1; -} - -/********************************************************************* - * @fn OPA_Cmd - * - * @brief Enables or disables the specified OPA peripheral. - * - * @param OPA_NUM - Select OPA - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM)); - } - else - { - OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM)); - } -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_opa.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the OPA firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_opa.h" + +#define OPA_MASK ((uint32_t)0x000F) +#define OPA_Total_NUM 4 + +/********************************************************************* + * @fn OPA_DeInit + * + * @brief Deinitializes the OPA peripheral registers to their default + * reset values. + * + * @return none + */ +void OPA_DeInit(void) +{ + OPA->CR = 0; +} + +/********************************************************************* + * @fn OPA_Init + * + * @brief Initializes the OPA peripheral according to the specified + * parameters in the OPA_InitStruct. + * + * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) +{ + uint32_t tmp = 0; + tmp = OPA->CR; + tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); + tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); + OPA->CR = tmp; +} + +/********************************************************************* + * @fn OPA_StructInit + * + * @brief Fills each OPA_StructInit member with its reset value. + * + * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) +{ + OPA_InitStruct->Mode = OUT_IO_OUT1; + OPA_InitStruct->PSEL = CHP0; + OPA_InitStruct->NSEL = CHN0; + OPA_InitStruct->OPA_NUM = OPA1; +} + +/********************************************************************* + * @fn OPA_Cmd + * + * @brief Enables or disables the specified OPA peripheral. + * + * @param OPA_NUM - Select OPA + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM)); + } + else + { + OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM)); + } +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_pwr.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_pwr.c index 838d430..4dbab20 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_pwr.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_pwr.c @@ -1,361 +1,361 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_pwr.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the PWR firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_pwr.h" -#include "ch32v30x_rcc.h" - -/* PWR registers bit mask */ -/* CTLR register bit mask */ -#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) - -/********************************************************************* - * @fn PWR_DeInit - * - * @brief Deinitializes the PWR peripheral registers to their default - * reset values. - * - * @return none - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/********************************************************************* - * @fn PWR_BackupAccessCmd - * - * @brief Enables or disables access to the RTC and backup registers. - * - * @param NewState - new state of the access to the RTC and backup registers, - * This parameter can be: ENABLE or DISABLE. - * - * @return none - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (1 << 8); - } - else - { - PWR->CTLR &= ~(1 << 8); - } -} - -/********************************************************************* - * @fn PWR_PVDCmd - * - * @brief Enables or disables the Power Voltage Detector(PVD). - * - * @param NewState - new state of the PVD(ENABLE or DISABLE). - * - * @return none - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (1 << 4); - } - else - { - PWR->CTLR &= ~(1 << 4); - } -} - -/********************************************************************* - * @fn PWR_PVDLevelConfig - * - * @brief Configures the voltage threshold detected by the Power Voltage - * Detector(PVD). - * - * @param PWR_PVDLevel - specifies the PVD detection level - * PWR_PVDLevel_2V2 - PVD detection level set to 2.2V - * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V - * PWR_PVDLevel_2V4 - PVD detection level set to 2.4V - * PWR_PVDLevel_2V5 - PVD detection level set to 2.5V - * PWR_PVDLevel_2V6 - PVD detection level set to 2.6V - * PWR_PVDLevel_2V7 - PVD detection level set to 2.7V - * PWR_PVDLevel_2V8 - PVD detection level set to 2.8V - * PWR_PVDLevel_2V9 - PVD detection level set to 2.9V - * - * @return none - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_PLS_MASK; - tmpreg |= PWR_PVDLevel; - PWR->CTLR = tmpreg; -} - -/********************************************************************* - * @fn PWR_WakeUpPinCmd - * - * @brief Enables or disables the WakeUp Pin functionality. - * - * @param NewState - new state of the WakeUp Pin functionality - * (ENABLE or DISABLE). - * - * @return none - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CSR |= (1 << 8); - } - else - { - PWR->CSR &= ~(1 << 8); - } -} - -/********************************************************************* - * @fn PWR_EnterSTOPMode - * - * @brief Enters STOP mode. - * - * @param PWR_Regulator - specifies the regulator state in STOP mode. - * PWR_Regulator_ON - STOP mode with regulator ON - * PWR_Regulator_LowPower - STOP mode with regulator in low power mode - * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. - * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction - * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction - * - * @return none - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_DS_MASK; - tmpreg |= PWR_Regulator; - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - __WFI(); - } - else - { - __WFE(); - } - - NVIC->SCTLR &= ~(1 << 2); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode - * - * @brief Enters STANDBY mode. - * - * @return none - */ -void PWR_EnterSTANDBYMode(void) -{ - PWR->CTLR |= PWR_CTLR_CWUF; - PWR->CTLR |= PWR_CTLR_PDDS; - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_GetFlagStatus - * - * @brief Checks whether the specified PWR flag is set or not. - * - * @param PWR_FLAG - specifies the flag to check. - * PWR_FLAG_WU - Wake Up flag - * PWR_FLAG_SB - StandBy flag - * PWR_FLAG_PVDO - PVD Output - * - * @return The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn PWR_ClearFlag - * - * @brief Clears the PWR's pending flags. - * - * @param PWR_FLAG - specifies the flag to clear. - * PWR_FLAG_WU - Wake Up flag - * PWR_FLAG_SB - StandBy flag - * - * @return none - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - PWR->CTLR |= PWR_FLAG << 2; -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode_RAM - * - * @brief Enters STANDBY mode with RAM data retention function on. - * - * @return none - */ -void PWR_EnterSTANDBYMode_RAM(void) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - - tmpreg |= PWR_CTLR_CWUF; - tmpreg |= PWR_CTLR_PDDS; - - //2K+30K in standby w power. - tmpreg |= (0x1 << 16) | (0x1 << 17); - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode_RAM_LV - * - * @brief Enters STANDBY mode with RAM data retention function and LV mode on. - * - * @return none - */ -void PWR_EnterSTANDBYMode_RAM_LV(void) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - - tmpreg |= PWR_CTLR_CWUF; - tmpreg |= PWR_CTLR_PDDS; - - //2K+30K in standby power. - tmpreg |= (0x1 << 16) | (0x1 << 17); - //2K+30K in standby LV . - tmpreg |= (0x1 << 20); - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN - * - * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable). - * - * @return none - */ -void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - - tmpreg |= PWR_CTLR_CWUF; - tmpreg |= PWR_CTLR_PDDS; - - //2K+30K in standby power (VBAT Enable). - tmpreg |= (0x1 << 18) | (0x1 << 19); - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN - * - * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable). - * - * @return none - */ -void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - - tmpreg |= PWR_CTLR_CWUF; - tmpreg |= PWR_CTLR_PDDS; - - //2K+30K in standby power (VBAT Enable). - tmpreg |= (0x1 << 18) | (0x1 << 19); - //2K+30K in standby LV . - tmpreg |= (0x1 << 20); - - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - - -/********************************************************************* - * @fn PWR_EnterSTOPMode_RAM_LV - * - * @brief Enters STOP mode with RAM data retention function and LV mode on. - * - * @param PWR_Regulator - specifies the regulator state in STOP mode. - * PWR_Regulator_LowPower - STOP mode with regulator in low power mode - * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. - * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction - * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction - * - * @return none - */ -void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_DS_MASK; - tmpreg |= PWR_Regulator; - - tmpreg |= (0x1 << 20); - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - __WFI(); - } - else - { - __WFE(); - } - - NVIC->SCTLR &= ~(1 << 2); -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_pwr.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the PWR firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_pwr.h" +#include "ch32v30x_rcc.h" + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_BackupAccessCmd + * + * @brief Enables or disables access to the RTC and backup registers. + * + * @param NewState - new state of the access to the RTC and backup registers, + * This parameter can be: ENABLE or DISABLE. + * + * @return none + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 8); + } + else + { + PWR->CTLR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_PVDCmd + * + * @brief Enables or disables the Power Voltage Detector(PVD). + * + * @param NewState - new state of the PVD(ENABLE or DISABLE). + * + * @return none + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 4); + } + else + { + PWR->CTLR &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_MODE0 - PVD detection level set to mode 0. + * PWR_PVDLevel_MODE1 - PVD detection level set to mode 1. + * PWR_PVDLevel_MODE2 - PVD detection level set to mode 2. + * PWR_PVDLevel_MODE3 - PVD detection level set to mode 3. + * PWR_PVDLevel_MODE4 - PVD detection level set to mode 4. + * PWR_PVDLevel_MODE5 - PVD detection level set to mode 5. + * PWR_PVDLevel_MODE6 - PVD detection level set to mode 6. + * PWR_PVDLevel_MODE7 - PVD detection level set to mode 7. + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_WakeUpPinCmd + * + * @brief Enables or disables the WakeUp Pin functionality. + * + * @param NewState - new state of the WakeUp Pin functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CSR |= (1 << 8); + } + else + { + PWR->CSR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_EnterSTOPMode + * + * @brief Enters STOP mode. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_ON - STOP mode with regulator ON + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @return none + */ +void PWR_EnterSTANDBYMode(void) +{ + PWR->CTLR |= PWR_CTLR_CWUF; + PWR->CTLR |= PWR_CTLR_PDDS; + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * PWR_FLAG_PVDO - PVD Output + * + * @return The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn PWR_ClearFlag + * + * @brief Clears the PWR's pending flags. + * + * @param PWR_FLAG - specifies the flag to clear. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * + * @return none + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + PWR->CTLR |= PWR_FLAG << 2; +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM + * + * @brief Enters STANDBY mode with RAM data retention function on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby w power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + //2K+30K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + //2K+30K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + + +/********************************************************************* + * @fn PWR_EnterSTOPMode_RAM_LV + * + * @brief Enters STOP mode with RAM data retention function and LV mode on. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + + tmpreg |= (0x1 << 20); + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_rcc.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_rcc.c index a025eae..84085c4 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_rcc.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_rcc.c @@ -1,1477 +1,1477 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_rcc.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the RCC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_rcc.h" - -/* RCC registers bit address in the alias region */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* BDCTLR Register */ -#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) - -/* RCC registers bit mask */ - -/* CTLR register bit mask */ -#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) -#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CTLR_HSEON_Set ((uint32_t)0x00010000) -#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) -#define CFGR0_PLL_Mask_1 ((uint32_t)0xFFC2FFFF) - -#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) -#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) -#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) -#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) -#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) -#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) -#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) -#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) - -/* RSTSCKR register bit mask */ -#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) - -/* CFGR2 register bit mask */ -#define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) -#define CFGR2_PREDIV1 ((uint32_t)0x0000000F) -#define CFGR2_PREDIV2 ((uint32_t)0x000000F0) -#define CFGR2_PLL2MUL ((uint32_t)0x00000F00) -#define CFGR2_PLL3MUL ((uint32_t)0x0000F000) - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -/* INTR register byte 2 (Bits[15:8]) base address */ -#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* INTR register byte 3 (Bits[23:16]) base address */ -#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CFGR0 register byte 4 (Bits[31:24]) base address */ -#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) - -/* BDCTLR register base address */ -#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) - -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; - -/********************************************************************* - * @fn RCC_DeInit - * - * @brief Resets the RCC clock configuration to the default reset state. - * Note- - * HSE can not be stopped if it is used directly or through the PLL as system clock. - * @return none - */ -void RCC_DeInit(void) -{ - RCC->CTLR |= (uint32_t)0x00000001; - -#ifdef CH32V30x_D8C - RCC->CFGR0 &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR0 &= (uint32_t)0xF0FF0000; -#endif - - RCC->CTLR &= (uint32_t)0xFEF6FFFF; - RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; - -#ifdef CH32V30x_D8C - RCC->CTLR &= (uint32_t)0xEBFFFFFF; - RCC->INTR = 0x00FF0000; - RCC->CFGR2 = 0x00000000; -#else - RCC->INTR = 0x009F0000; -#endif -} - -/********************************************************************* - * @fn RCC_HSEConfig - * - * @brief Configures the External High Speed oscillator (HSE). - * - * @param RCC_HSE - - * RCC_HSE_OFF - HSE oscillator OFF. - * RCC_HSE_ON - HSE oscillator ON. - * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. - * Note- - * HSE can not be stopped if it is used directly or through the PLL as system clock. - * @return none - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - RCC->CTLR &= CTLR_HSEON_Reset; - RCC->CTLR &= CTLR_HSEBYP_Reset; - - switch(RCC_HSE) - { - case RCC_HSE_ON: - RCC->CTLR |= CTLR_HSEON_Set; - break; - - case RCC_HSE_Bypass: - RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn RCC_WaitForHSEStartUp - * - * @brief Waits for HSE start-up. - * - * @return READY - HSE oscillator is stable and ready to use. - * NoREADY - HSE oscillator not yet ready. - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - - ErrorStatus status = NoREADY; - FlagStatus HSEStatus = RESET; - - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = READY; - } - else - { - status = NoREADY; - } - - return (status); -} - -/********************************************************************* - * @fn RCC_AdjustHSICalibrationValue - * - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * - * @param HSICalibrationValue - specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * - * @return none - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CTLR; - tmpreg &= CTLR_HSITRIM_Mask; - tmpreg |= (uint32_t)HSICalibrationValue << 3; - RCC->CTLR = tmpreg; -} - -/********************************************************************* - * @fn RCC_HSICmd - * - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_HSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 0); - } - else - { - RCC->CTLR &= ~(1 << 0); - } -} - -/********************************************************************* - * @fn RCC_PLLConfig - * - * @brief Configures the PLL clock source and multiplication factor. - * - * @param RCC_PLLSource - specifies the PLL entry clock source. - * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 - * selected as PLL clock entry. - * RCC_PLLSource_PREDIV1 - PREDIV1 clock selected as PLL clock - * entry. - * RCC_PLLMul - specifies the PLL multiplication factor. - * This parameter can be RCC_PLLMul_x where x:[2,16]. - * For CH32V307 - - * RCC_PLLMul_18_EXTEN - * RCC_PLLMul_3_EXTEN - * RCC_PLLMul_4_EXTEN - * RCC_PLLMul_5_EXTEN - * RCC_PLLMul_6_EXTEN - * RCC_PLLMul_7_EXTEN - * RCC_PLLMul_8_EXTEN - * RCC_PLLMul_9_EXTEN - * RCC_PLLMul_10_EXTEN - * RCC_PLLMul_11_EXTEN - * RCC_PLLMul_12_EXTEN - * RCC_PLLMul_13_EXTEN - * RCC_PLLMul_14_EXTEN - * RCC_PLLMul_6_5_EXTEN - * RCC_PLLMul_15_EXTEN - * RCC_PLLMul_16_EXTEN - * For other CH32V30x - - * RCC_PLLMul_2 - * RCC_PLLMul_3 - * RCC_PLLMul_4 - * RCC_PLLMul_5 - * RCC_PLLMul_6 - * RCC_PLLMul_7 - * RCC_PLLMul_8 - * RCC_PLLMul_9 - * RCC_PLLMul_10 - * RCC_PLLMul_11 - * RCC_PLLMul_12 - * RCC_PLLMul_13 - * RCC_PLLMul_14 - * RCC_PLLMul_15 - * RCC_PLLMul_16 - * RCC_PLLMul_18 - * - * @return none - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - - if(((*(uint32_t *)0x1FFFF70C) & (1 << 14)) != (1 << 14)) - { /* for other CH32V30x */ - tmpreg &= CFGR0_PLL_Mask; - } - else - { /* for CH32V307 */ - tmpreg &= CFGR0_PLL_Mask_1; - } - - tmpreg |= RCC_PLLSource | RCC_PLLMul; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PLLCmd - * - * @brief Enables or disables the PLL. - * Note-The PLL can not be disabled if it is used as system clock. - * - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 24); - } - else - { - RCC->CTLR &= ~(1 << 24); - } -} - -/********************************************************************* - * @fn RCC_SYSCLKConfig - * - * @brief Configures the system clock (SYSCLK). - * - * @param RCC_SYSCLKSource - specifies the clock source used as system clock. - * RCC_SYSCLKSource_HSI - HSI selected as system clock. - * RCC_SYSCLKSource_HSE - HSE selected as system clock. - * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. - * - * @return none - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_SW_Mask; - tmpreg |= RCC_SYSCLKSource; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_GetSYSCLKSource - * - * @brief Returns the clock source used as system clock. - * - * @return 0x00 - HSI used as system clock. - * 0x04 - HSE used as system clock. - * 0x08 - PLL used as system clock. - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); -} - -/********************************************************************* - * @fn RCC_HCLKConfig - * - * @brief Configures the AHB clock (HCLK). - * - * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. - * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. - * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. - * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. - * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. - * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. - * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. - * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. - * RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512. - * - * @return none - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_HPRE_Reset_Mask; - tmpreg |= RCC_SYSCLK; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PCLK1Config - * - * @brief Configures the Low Speed APB clock (PCLK1). - * - * @param RCC_HCLK - defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * RCC_HCLK_Div1 - APB1 clock = HCLK. - * RCC_HCLK_Div2 - APB1 clock = HCLK/2. - * RCC_HCLK_Div4 - APB1 clock = HCLK/4. - * RCC_HCLK_Div8 - APB1 clock = HCLK/8. - * RCC_HCLK_Div16 - APB1 clock = HCLK/16. - * - * @return none - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_PPRE1_Reset_Mask; - tmpreg |= RCC_HCLK; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PCLK2Config - * - * @brief Configures the High Speed APB clock (PCLK2). - * - * @param RCC_HCLK - defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * RCC_HCLK_Div1 - APB2 clock = HCLK. - * RCC_HCLK_Div2 - APB2 clock = HCLK/2. - * RCC_HCLK_Div4 - APB2 clock = HCLK/4. - * RCC_HCLK_Div8 - APB2 clock = HCLK/8. - * RCC_HCLK_Div16 - APB2 clock = HCLK/16. - * - * @return none - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_PPRE2_Reset_Mask; - tmpreg |= RCC_HCLK << 3; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_ITConfig - * - * @brief Enables or disables the specified RCC interrupts. - * - * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/********************************************************************* - * @fn RCC_ADCCLKConfig - * - * @brief Configures the ADC clock (ADCCLK). - * - * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from - * the APB2 clock (PCLK2). - * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. - * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. - * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. - * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. - * - * @return none - */ -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_ADCPRE_Reset_Mask; - tmpreg |= RCC_PCLK2; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_LSEConfig - * - * @brief Configures the External Low Speed oscillator (LSE). - * - * @param RCC_LSE - specifies the new state of the LSE. - * RCC_LSE_OFF - LSE oscillator OFF. - * RCC_LSE_ON - LSE oscillator ON. - * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. - * - * @return none - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; - *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; - - switch(RCC_LSE) - { - case RCC_LSE_ON: - *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_ON; - break; - - case RCC_LSE_Bypass: - *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn RCC_LSICmd - * - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * Note- - * LSI can not be disabled if the IWDG is running. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_LSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->RSTSCKR |= (1 << 0); - } - else - { - RCC->RSTSCKR &= ~(1 << 0); - } -} - -/********************************************************************* - * @fn RCC_RTCCLKConfig - * - * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. - * - * @param RCC_RTCCLKSource - specifies the RTC clock source. - * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. - * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. - * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. - * Note- - * Once the RTC clock is selected it can't be changed unless the Backup domain is reset. - * @return none - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - RCC->BDCTLR |= RCC_RTCCLKSource; -} - -/********************************************************************* - * @fn RCC_RTCCLKCmd - * - * @brief This function must be used only after the RTC clock was selected - * using the RCC_RTCCLKConfig function. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->BDCTLR |= (1 << 15); - } - else - { - RCC->BDCTLR &= ~(1 << 15); - } -} - -/********************************************************************* - * @fn RCC_GetClocksFreq - * - * @brief The result of this function could be not correct when using - * fractional value for HSE crystal. - * - * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @return none - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; - uint8_t Pll_6_5 = 0; - -#ifdef CH32V30x_D8C - uint8_t Pll2mull = 0; - -#endif - - tmp = RCC->CFGR0 & CFGR0_SWS_Mask; - - switch(tmp) - { - case 0x00: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - - case 0x04: - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - - case 0x08: - pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; - pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; - - pllmull = (pllmull >> 18) + 2; - - if(((*(uint32_t *)0x1FFFF70C) & (1 << 14)) != (1 << 14)) - { /* for other CH32V30x */ - if(pllmull == 17) - pllmull = 18; - } - else - { /* for CH32V307 */ - if(pllmull == 2) - pllmull = 18; - if(pllmull == 15) - { - pllmull = 13; /* *6.5 */ - Pll_6_5 = 1; - } - if(pllmull == 16) - pllmull = 15; - if(pllmull == 17) - pllmull = 16; - } - - if(pllsource == 0x00) - { - if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) - { - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE)*pllmull; - } - else - { - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; - } - } - else - { -#ifdef CH32V30x_D8 - if((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) - { - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; - } - else - { - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; - } -#else - if(RCC->CFGR2 & (1<<16)){ /* PLL2 */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE/(((RCC->CFGR2 & 0xF0)>>4) + 1); /* PREDIV2 */ - - Pll2mull = (uint8_t)((RCC->CFGR2 & 0xF00)>>8); - - if(Pll2mull == 0) RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency * 5)>>1; - else if(Pll2mull == 1) RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency * 25)>>1; - else if(Pll2mull == 15) RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency * 20; - else RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency * (Pll2mull + 2); - - RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */ - } - else{/* HSE */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */ - } - - RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency * pllmull; - -#endif - } - - if(Pll_6_5 == 1) - RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency / 2); - - break; - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - - tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; - tmp = tmp >> 11; - presc = APBAHBPrescTable[tmp]; - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; - tmp = tmp >> 14; - presc = ADCPrescTable[tmp]; - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; -} - -/********************************************************************* - * @fn RCC_AHBPeriphClockCmd - * - * @brief Enables or disables the AHB peripheral clock. - * - * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. - * RCC_AHBPeriph_DMA1. - * RCC_AHBPeriph_DMA2. - * RCC_AHBPeriph_SRAM. - * RCC_AHBPeriph_CRC. - * RCC_AHBPeriph_FSMC - * RCC_AHBPeriph_RNG - * RCC_AHBPeriph_SDIO - * RCC_AHBPeriph_USBHS - * RCC_AHBPeriph_OTG_FS - * RCC_AHBPeriph_DVP - * RCC_AHBPeriph_ETH_MAC - * RCC_AHBPeriph_ETH_MAC_Tx - * RCC_AHBPeriph_ETH_MAC_Rx - * Note- - * SRAM clock can be disabled only during sleep mode. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->AHBPCENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBPCENR &= ~RCC_AHBPeriph; - } -} - -/********************************************************************* - * @fn RCC_APB2PeriphClockCmd - * - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * - * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. - * RCC_APB2Periph_AFIO. - * RCC_APB2Periph_GPIOA. - * RCC_APB2Periph_GPIOB. - * RCC_APB2Periph_GPIOC. - * RCC_APB2Periph_GPIOD. - * RCC_APB2Periph_GPIOE - * RCC_APB2Periph_ADC1. - * RCC_APB2Periph_ADC2 - * RCC_APB2Periph_TIM1. - * RCC_APB2Periph_SPI1. - * RCC_APB2Periph_TIM8 - * RCC_APB2Periph_USART1. - * RCC_APB2Periph_TIM9 - * RCC_APB2Periph_TIM10 - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->APB2PCENR |= RCC_APB2Periph; - } - else - { - RCC->APB2PCENR &= ~RCC_APB2Periph; - } -} - -/********************************************************************* - * @fn RCC_APB1PeriphClockCmd - * - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * - * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. - * RCC_APB1Periph_TIM2. - * RCC_APB1Periph_TIM3. - * RCC_APB1Periph_TIM4. - * RCC_APB1Periph_TIM5 - * RCC_APB1Periph_TIM6 - * RCC_APB1Periph_TIM7 - * RCC_APB1Periph_UART6 - * RCC_APB1Periph_UART7 - * RCC_APB1Periph_UART8 - * RCC_APB1Periph_WWDG. - * RCC_APB1Periph_SPI2. - * RCC_APB1Periph_SPI3. - * RCC_APB1Periph_USART2. - * RCC_APB1Periph_USART3. - * RCC_APB1Periph_UART4 - * RCC_APB1Periph_UART5 - * RCC_APB1Periph_I2C1. - * RCC_APB1Periph_I2C2. - * RCC_APB1Periph_USB. - * RCC_APB1Periph_CAN1. - * RCC_APB1Periph_BKP. - * RCC_APB1Periph_PWR. - * RCC_APB1Periph_DAC. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->APB1PCENR |= RCC_APB1Periph; - } - else - { - RCC->APB1PCENR &= ~RCC_APB1Periph; - } -} - -/********************************************************************* - * @fn RCC_APB2PeriphResetCmd - * - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * - * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. - * RCC_APB2Periph_AFIO. - * RCC_APB2Periph_GPIOA. - * RCC_APB2Periph_GPIOB. - * RCC_APB2Periph_GPIOC. - * RCC_APB2Periph_GPIOD. - * RCC_APB2Periph_GPIOE - * RCC_APB2Periph_ADC1. - * RCC_APB2Periph_ADC2 - * RCC_APB2Periph_TIM1. - * RCC_APB2Periph_SPI1. - * RCC_APB2Periph_TIM8 - * RCC_APB2Periph_USART1. - * RCC_APB2Periph_TIM9 - * RCC_APB2Periph_TIM10 - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->APB2PRSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2PRSTR &= ~RCC_APB2Periph; - } -} - -/********************************************************************* - * @fn RCC_APB1PeriphResetCmd - * - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * - * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. - * RCC_APB1Periph_TIM2. - * RCC_APB1Periph_TIM3. - * RCC_APB1Periph_TIM4. - * RCC_APB1Periph_TIM5 - * RCC_APB1Periph_TIM6 - * RCC_APB1Periph_TIM7 - * RCC_APB1Periph_UART6 - * RCC_APB1Periph_UART7 - * RCC_APB1Periph_UART8 - * RCC_APB1Periph_WWDG. - * RCC_APB1Periph_SPI2. - * RCC_APB1Periph_SPI3. - * RCC_APB1Periph_USART2. - * RCC_APB1Periph_USART3. - * RCC_APB1Periph_UART4 - * RCC_APB1Periph_UART5 - * RCC_APB1Periph_I2C1. - * RCC_APB1Periph_I2C2. - * RCC_APB1Periph_USB. - * RCC_APB1Periph_CAN1. - * RCC_APB1Periph_BKP. - * RCC_APB1Periph_PWR. - * RCC_APB1Periph_DAC. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->APB1PRSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1PRSTR &= ~RCC_APB1Periph; - } -} - -/********************************************************************* - * @fn RCC_BackupResetCmd - * - * @brief Forces or releases the Backup domain reset. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->BDCTLR |= (1 << 16); - } - else - { - RCC->BDCTLR &= ~(1 << 16); - } -} - -/********************************************************************* - * @fn RCC_ClockSecuritySystemCmd - * - * @brief Enables or disables the Clock Security System. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 19); - } - else - { - RCC->CTLR &= ~(1 << 19); - } -} - -/********************************************************************* - * @fn RCC_MCOConfig - * - * @brief Selects the clock source to output on MCO pin. - * - * @param RCC_MCO - specifies the clock source to output. - * RCC_MCO_NoClock - No clock selected. - * RCC_MCO_SYSCLK - System clock selected. - * RCC_MCO_HSI - HSI oscillator clock selected. - * RCC_MCO_HSE - HSE oscillator clock selected. - * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. - * RCC_MCO_PLL2CLK - PLL2 clock selected - * RCC_MCO_PLL3CLK_Div2 - PLL3 clock divided by 2 selected - * RCC_MCO_XT1 - External 3-25 MHz oscillator clock selected - * RCC_MCO_PLL3CLK - PLL3 clock selected - * - * @return none - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO; -} - -/********************************************************************* - * @fn RCC_GetFlagStatus - * - * @brief Checks whether the specified RCC flag is set or not. - * - * @param RCC_FLAG - specifies the flag to check. - * RCC_FLAG_HSIRDY - HSI oscillator clock ready. - * RCC_FLAG_HSERDY - HSE oscillator clock ready. - * RCC_FLAG_PLLRDY - PLL clock ready. - * RCC_FLAG_PLL2RDY - PLL2 clock ready. - * RCC_FLAG_PLL3RDY - PLL3 clock ready. - * RCC_FLAG_LSERDY - LSE oscillator clock ready. - * RCC_FLAG_LSIRDY - LSI oscillator clock ready. - * RCC_FLAG_PINRST - Pin reset. - * RCC_FLAG_PORRST - POR/PDR reset. - * RCC_FLAG_SFTRST - Software reset. - * RCC_FLAG_IWDGRST - Independent Watchdog reset. - * RCC_FLAG_WWDGRST - Window Watchdog reset. - * RCC_FLAG_LPWRRST - Low Power reset. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - - FlagStatus bitstatus = RESET; - tmp = RCC_FLAG >> 5; - - if(tmp == 1) - { - statusreg = RCC->CTLR; - } - else if(tmp == 2) - { - statusreg = RCC->BDCTLR; - } - else - { - statusreg = RCC->RSTSCKR; - } - - tmp = RCC_FLAG & FLAG_Mask; - - if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearFlag - * - * @brief Clears the RCC reset flags. - * Note- - * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @return none - */ -void RCC_ClearFlag(void) -{ - RCC->RSTSCKR |= RSTSCKR_RMVF_Set; -} - -/********************************************************************* - * @fn RCC_GetITStatus - * - * @brief Checks whether the specified RCC interrupt has occurred or not. - * - * @param RCC_IT - specifies the RCC interrupt source to check. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_PLL2RDY - PLL2 ready interrupt. - * RCC_IT_PLL3RDY - PLL3 ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * - * @return ITStatus - SET or RESET. - */ - -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - if((RCC->INTR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearITPendingBit - * - * @brief Clears the RCC's interrupt pending bits. - * - * @param RCC_IT - specifies the interrupt pending bit to clear. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_PLL2RDY - PLL2 ready interrupt. - * RCC_IT_PLL3RDY - PLL3 ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * - * @return none - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT; -} - -/********************************************************************* - * @fn RCC_PREDIV1Config - * - * @brief Configures the PREDIV1 division factor. - * - * @param RCC_PREDIV1_Source - specifies the PREDIV1 clock source. - * RCC_PREDIV1_Source_HSE - HSE selected as PREDIV1 clock - * RCC_PREDIV1_Source_PLL2 - PLL2 selected as PREDIV1 clock - * RCC_PREDIV1_Div - specifies the PREDIV1 clock division factor. - * This parameter can be RCC_PREDIV1_Divx where x[1,16] - * Note- - * - This function must be used only when the PLL is disabled. - * - * @return none - */ -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR2; - tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); - tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div; - RCC->CFGR2 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PREDIV2Config - * - * @brief Configures the PREDIV2 division factor. - * - * @param RCC_PREDIV2_Div - specifies the PREDIV2 clock division factor. - * This parameter can be RCC_PREDIV2_Divx where x:[1,16] - * Note- - * - This function must be used only when both PLL2 and PLL3 are disabled. - * - * @return none - */ -void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR2; - tmpreg &= ~CFGR2_PREDIV2; - tmpreg |= RCC_PREDIV2_Div; - RCC->CFGR2 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PLL2Config - * - * @brief Configures the PLL2 multiplication factor. - * - * @param RCC_PLL2Mul - specifies the PLL2 multiplication factor. - * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} - * Note- - * - This function must be used only when the PLL2 is disabled. - * - * @return none - */ -void RCC_PLL2Config(uint32_t RCC_PLL2Mul) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR2; - tmpreg &= ~CFGR2_PLL2MUL; - tmpreg |= RCC_PLL2Mul; - RCC->CFGR2 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PLL2Cmd - * - * @brief Enables or disables the PLL2. - * - * @param NewState - new state of the PLL2. This parameter can be - * ENABLE or DISABLE. - * Note- - * - The PLL2 can not be disabled if it is used indirectly as system clock - * (i.e. it is used as PLL clock entry that is used as System clock). - * - * @return none - */ -void RCC_PLL2Cmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 26); - } - else - { - RCC->CTLR &= ~(1 << 26); - } -} - -/********************************************************************* - * @fn RCC_PLL3Config - * - * @brief Configures the PLL3 multiplication factor. - * - * @param RCC_PLL3Mul - specifies the PLL2 multiplication factor. - * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} - * Note- - * - This function must be used only when the PLL3 is disabled. - * - * @return none - */ -void RCC_PLL3Config(uint32_t RCC_PLL3Mul) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR2; - tmpreg &= ~CFGR2_PLL3MUL; - tmpreg |= RCC_PLL3Mul; - RCC->CFGR2 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PLL3Cmd - * - * @brief Enables or disables the PLL3. - * - * @param NewState - new state of the PLL2. This parameter can be - * ENABLE or DISABLE. - * - * @return none - */ -void RCC_PLL3Cmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 28); - } - else - { - RCC->CTLR &= ~(1 << 28); - } -} - -/********************************************************************* - * @fn RCC_OTGFSCLKConfig - * - * @brief Configures the USB OTG FS clock (OTGFSCLK). - * - * @param RCC_OTGFSCLKSource - specifies the USB OTG FS clock source. - * RCC_OTGFSCLKSource_PLLCLK_Div1 - PLL clock divided by 1 - * selected as USB OTG FS clock source - * RCC_OTGFSCLKSource_PLLCLK_Div2 - PLL clock divided by 2 - * selected as USB OTG FS clock source - * RCC_OTGFSCLKSource_PLLCLK_Div3 - PLL clock divided by 3 - * selected as USB OTG FS clock source - * - * @return none - */ -void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) -{ - RCC->CFGR0 &= ~(3 << 22); - RCC->CFGR0 |= RCC_OTGFSCLKSource << 22; -} - -/********************************************************************* - * @fn RCC_I2S2CLKConfig - * - * @brief Configures the I2S2 clock source(I2S2CLK). - * - * @param RCC_I2S2CLKSource - specifies the I2S2 clock source. - * RCC_I2S2CLKSource_SYSCLK - system clock selected as I2S2 clock entry - * RCC_I2S2CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S2 clock entry - * Note- - * - This function must be called before enabling I2S2 APB clock. - * @return none - */ -void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) -{ - RCC->CFGR2 &= ~(1 << 17); - RCC->CFGR2 |= RCC_I2S2CLKSource << 17; -} - -/********************************************************************* - * @fn RCC_I2S3CLKConfig - * - * @brief Configures the I2S3 clock source(I2S2CLK). - * - * @param RCC_I2S3CLKSource - specifies the I2S3 clock source. - * RCC_I2S3CLKSource_SYSCLK - system clock selected as I2S3 clock entry - * RCC_I2S3CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S3 clock entry - * Note- - * - This function must be called before enabling I2S3 APB clock. - * @return none - */ -void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) -{ - RCC->CFGR2 &= ~(1 << 18); - RCC->CFGR2 |= RCC_I2S3CLKSource << 18; -} - -/********************************************************************* - * @fn RCC_AHBPeriphResetCmd - * - * @brief Forces or releases AHB peripheral reset. - * - * @param RCC_AHBPeriph - specifies the AHB peripheral to reset. - * RCC_AHBPeriph_OTG_FS - * RCC_AHBPeriph_ETH_MAC - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->AHBRSTR |= RCC_AHBPeriph; - } - else - { - RCC->AHBRSTR &= ~RCC_AHBPeriph; - } -} - -/********************************************************************* - * @fn RCC_ADCCLKADJcmd - * - * @brief Enable ADC clock duty cycle adjustment. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ADCCLKADJcmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->CFGR0 |= (1 << 31); - } - else - { - RCC->CFGR0 &= ~(1 << 31); - } -} - -/********************************************************************* - * @fn RCC_RNGCLKConfig - * - * @brief Configures the RNG clock source. - * - * @param RCC_RNGCLKSource - specifies the RNG clock source. - * RCC_RNGCLKSource_SYSCLK - system clock selected as RNG clock entry - * RCC_RNGCLKSource_PLL3_VCO - PLL3 VCO clock selected as RNG clock entry - * - * @return none - */ -void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource) -{ - RCC->CFGR2 &= ~(1 << 19); - RCC->CFGR2 |= RCC_RNGCLKSource << 19; -} - -/********************************************************************* - * @fn RCC_ETH1GCLKConfig - * - * @brief Configures the ETH1G clock source. - * - * @param RCC_RNGCLKSource - specifies the ETH1G clock source. - * RCC_ETH1GCLKSource_PLL2_VCO - system clock selected as ETH1G clock entry - * RCC_ETH1GCLKSource_PLL3_VCO - PLL3 VCO clock selected as ETH1G clock entry - * RCC_ETH1GCLKSource_PB1_IN - GPIO PB1 input clock selected as ETH1G clock entry - * - * @return none - */ -void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource) -{ - RCC->CFGR2 &= ~(3 << 20); - RCC->CFGR2 |= RCC_ETH1GCLKSource << 20; -} - -/********************************************************************* - * @fn RCC_ETH1G_125Mcmd - * - * @brief Enable ETH1G 125M. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ETH1G_125Mcmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->CFGR2 |= (1 << 22); - } - else - { - RCC->CFGR2 &= ~(1 << 22); - } -} - -/********************************************************************* - * @fn RCC_USBHSConfig - * - * @brief Configures the USBHS clock. - * - * @param RCC_USBHS - defines the USBHS clock divider. - * RCC_USBPLL_Div1 - USBHS clock = USBPLL. - * RCC_USBPLL_Div2 - USBHS clock = USBPLL/2. - * RCC_USBPLL_Div3 - USBHS clock = USBPLL/3. - * RCC_USBPLL_Div4 - USBHS clock = USBPLL/4. - * RCC_USBPLL_Div5 - USBHS clock = USBPLL/5. - * RCC_USBPLL_Div6 - USBHS clock = USBPLL/6. - * RCC_USBPLL_Div7 - USBHS clock = USBPLL/7. - * RCC_USBPLL_Div8 - USBHS clock = USBPLL/8. - * - * @return none - */ -void RCC_USBHSConfig(uint32_t RCC_USBHS) -{ - RCC->CFGR2 &= ~(7 << 24); - RCC->CFGR2 |= RCC_USBHS << 24; -} - -/********************************************************************* - * @fn RCC_USBHSPLLCLKConfig - * - * @brief Configures the USBHSPLL clock source. - * - * @param RCC_HSBHSPLLCLKSource - specifies the USBHSPLL clock source. - * RCC_HSBHSPLLCLKSource_HSE - HSE clock selected as USBHSPLL clock entry - * RCC_HSBHSPLLCLKSource_HSI - HSI clock selected as USBHSPLL clock entry - * - * @return none - */ -void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource) -{ - RCC->CFGR2 &= ~(1 << 27); - RCC->CFGR2 |= RCC_USBHSPLLCLKSource << 27; -} - -/********************************************************************* - * @fn RCC_USBHSPLLCKREFCLKConfig - * - * @brief Configures the USBHSPLL reference clock. - * - * @param RCC_USBHSPLLCKREFCLKSource - Select reference clock. - * RCC_USBHSPLLCKREFCLK_3M - reference clock 3Mhz. - * RCC_USBHSPLLCKREFCLK_4M - reference clock 4Mhz. - * RCC_USBHSPLLCKREFCLK_8M - reference clock 8Mhz. - * RCC_USBHSPLLCKREFCLK_5M - reference clock 5Mhz. - * - * @return none - */ -void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource) -{ - RCC->CFGR2 &= ~(3 << 28); - RCC->CFGR2 |= RCC_USBHSPLLCKREFCLKSource << 28; -} - -/********************************************************************* - * @fn RCC_USBHSPHYPLLALIVEcmd - * - * @brief Enable USBHS PHY control. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->CFGR2 |= (1 << 30); - } - else - { - RCC->CFGR2 &= ~(1 << 30); - } -} - -/********************************************************************* - * @fn RCC_USBCLK48MConfig - * - * @brief Configures the USB clock 48MHz source. - * - * @param RCC_USBCLK48MSource - specifies the USB clock 48MHz source. - * RCC_USBCLK48MCLKSource_PLLCLK - PLLCLK clock selected as USB clock 48MHz clock entry - * RCC_USBCLK48MCLKSource_USBPHY - USBPHY clock selected as USB clock 48MHz clock entry - * - * @return none - */ -void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource) -{ - RCC->CFGR2 &= ~(1 << 31); - RCC->CFGR2 |= RCC_USBCLK48MSource << 31; -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rcc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/28 +* Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_rcc.h" + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLL_Mask_1 ((uint32_t)0xFFC2FFFF) + +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* CFGR2 register bit mask */ +#define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) +#define CFGR2_PREDIV1 ((uint32_t)0x0000000F) +#define CFGR2_PREDIV2 ((uint32_t)0x000000F0) +#define CFGR2_PLL2MUL ((uint32_t)0x00000F00) +#define CFGR2_PLL3MUL ((uint32_t)0x0000F000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + +#ifdef CH32V30x_D8C + RCC->CFGR0 &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR0 &= (uint32_t)0xF0FF0000; +#endif + + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + +#ifdef CH32V30x_D8C + RCC->CTLR &= (uint32_t)0xEBFFFFFF; + RCC->INTR = 0x00FF0000; + RCC->CFGR2 = 0x00000000; +#else + RCC->INTR = 0x009F0000; +#endif +} + +/********************************************************************* + * @fn RCC_HSEConfig + * + * @brief Configures the External High Speed oscillator (HSE). + * + * @param RCC_HSE - + * RCC_HSE_OFF - HSE oscillator OFF. + * RCC_HSE_ON - HSE oscillator ON. + * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + RCC->CTLR &= CTLR_HSEON_Reset; + RCC->CTLR &= CTLR_HSEBYP_Reset; + + switch(RCC_HSE) + { + case RCC_HSE_ON: + RCC->CTLR |= CTLR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_WaitForHSEStartUp + * + * @brief Waits for HSE start-up. + * + * @return READY - HSE oscillator is stable and ready to use. + * NoREADY - HSE oscillator not yet ready. + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + + ErrorStatus status = NoREADY; + FlagStatus HSEStatus = RESET; + + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = READY; + } + else + { + status = NoREADY; + } + + return (status); +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 0); + } + else + { + RCC->CTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_PLLConfig + * + * @brief Configures the PLL clock source and multiplication factor. + * + * @param RCC_PLLSource - specifies the PLL entry clock source. + * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 + * selected as PLL clock entry. + * RCC_PLLSource_PREDIV1 - PREDIV1 clock selected as PLL clock + * entry. + * RCC_PLLMul - specifies the PLL multiplication factor. + * This parameter can be RCC_PLLMul_x where x:[2,16]. + * For CH32V307 - + * RCC_PLLMul_18_EXTEN + * RCC_PLLMul_3_EXTEN + * RCC_PLLMul_4_EXTEN + * RCC_PLLMul_5_EXTEN + * RCC_PLLMul_6_EXTEN + * RCC_PLLMul_7_EXTEN + * RCC_PLLMul_8_EXTEN + * RCC_PLLMul_9_EXTEN + * RCC_PLLMul_10_EXTEN + * RCC_PLLMul_11_EXTEN + * RCC_PLLMul_12_EXTEN + * RCC_PLLMul_13_EXTEN + * RCC_PLLMul_14_EXTEN + * RCC_PLLMul_6_5_EXTEN + * RCC_PLLMul_15_EXTEN + * RCC_PLLMul_16_EXTEN + * For other CH32V30x - + * RCC_PLLMul_2 + * RCC_PLLMul_3 + * RCC_PLLMul_4 + * RCC_PLLMul_5 + * RCC_PLLMul_6 + * RCC_PLLMul_7 + * RCC_PLLMul_8 + * RCC_PLLMul_9 + * RCC_PLLMul_10 + * RCC_PLLMul_11 + * RCC_PLLMul_12 + * RCC_PLLMul_13 + * RCC_PLLMul_14 + * RCC_PLLMul_15 + * RCC_PLLMul_16 + * RCC_PLLMul_18 + * + * @return none + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + + if(((*(uint32_t *)0x1FFFF70C) & (1 << 14)) != (1 << 14)) + { /* for other CH32V30x */ + tmpreg &= CFGR0_PLL_Mask; + } + else + { /* for CH32V307 */ + tmpreg &= CFGR0_PLL_Mask_1; + } + + tmpreg |= RCC_PLLSource | RCC_PLLMul; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLLCmd + * + * @brief Enables or disables the PLL. + * Note-The PLL can not be disabled if it is used as system clock. + * + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 24); + } + else + { + RCC->CTLR &= ~(1 << 24); + } +} + +/********************************************************************* + * @fn RCC_SYSCLKConfig + * + * @brief Configures the system clock (SYSCLK). + * + * @param RCC_SYSCLKSource - specifies the clock source used as system clock. + * RCC_SYSCLKSource_HSI - HSI selected as system clock. + * RCC_SYSCLKSource_HSE - HSE selected as system clock. + * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. + * + * @return none + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_SW_Mask; + tmpreg |= RCC_SYSCLKSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetSYSCLKSource + * + * @brief Returns the clock source used as system clock. + * + * @return 0x00 - HSI used as system clock. + * 0x04 - HSE used as system clock. + * 0x08 - PLL used as system clock. + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the AHB clock (HCLK). + * + * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. + * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. + * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. + * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. + * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. + * RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK1Config + * + * @brief Configures the Low Speed APB clock (PCLK1). + * + * @param RCC_HCLK - defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB1 clock = HCLK. + * RCC_HCLK_Div2 - APB1 clock = HCLK/2. + * RCC_HCLK_Div4 - APB1 clock = HCLK/4. + * RCC_HCLK_Div8 - APB1 clock = HCLK/8. + * RCC_HCLK_Div16 - APB1 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE1_Reset_Mask; + tmpreg |= RCC_HCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK2Config + * + * @brief Configures the High Speed APB clock (PCLK2). + * + * @param RCC_HCLK - defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB2 clock = HCLK. + * RCC_HCLK_Div2 - APB2 clock = HCLK/2. + * RCC_HCLK_Div4 - APB2 clock = HCLK/4. + * RCC_HCLK_Div8 - APB2 clock = HCLK/8. + * RCC_HCLK_Div16 - APB2 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE2_Reset_Mask; + tmpreg |= RCC_HCLK << 3; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_ITConfig + * + * @brief Enables or disables the specified RCC interrupts. + * + * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/********************************************************************* + * @fn RCC_ADCCLKConfig + * + * @brief Configures the ADC clock (ADCCLK). + * + * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. + * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. + * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. + * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. + * + * @return none + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_ADCPRE_Reset_Mask; + tmpreg |= RCC_PCLK2; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_LSEConfig + * + * @brief Configures the External Low Speed oscillator (LSE). + * + * @param RCC_LSE - specifies the new state of the LSE. + * RCC_LSE_OFF - LSE oscillator OFF. + * RCC_LSE_ON - LSE oscillator ON. + * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. + * + * @return none + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; + + switch(RCC_LSE) + { + case RCC_LSE_ON: + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_LSICmd + * + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * Note- + * LSI can not be disabled if the IWDG is running. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_LSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->RSTSCKR |= (1 << 0); + } + else + { + RCC->RSTSCKR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_RTCCLKConfig + * + * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * + * @param RCC_RTCCLKSource - specifies the RTC clock source. + * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. + * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. + * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. + * Note- + * Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * @return none + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + RCC->BDCTLR |= RCC_RTCCLKSource; +} + +/********************************************************************* + * @fn RCC_RTCCLKCmd + * + * @brief This function must be used only after the RTC clock was selected + * using the RCC_RTCCLKConfig function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1 << 15); + } + else + { + RCC->BDCTLR &= ~(1 << 15); + } +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + uint8_t Pll_6_5 = 0; + +#ifdef CH32V30x_D8C + uint8_t Pll2mull = 0; + +#endif + + tmp = RCC->CFGR0 & CFGR0_SWS_Mask; + + switch(tmp) + { + case 0x00: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + + case 0x04: + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: + pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; + pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; + + pllmull = (pllmull >> 18) + 2; + + if(((*(uint32_t *)0x1FFFF70C) & (1 << 14)) != (1 << 14)) + { /* for other CH32V30x */ + if(pllmull == 17) + pllmull = 18; + } + else + { /* for CH32V307 */ + if(pllmull == 2) + pllmull = 18; + if(pllmull == 15) + { + pllmull = 13; /* *6.5 */ + Pll_6_5 = 1; + } + if(pllmull == 16) + pllmull = 15; + if(pllmull == 17) + pllmull = 16; + } + + if(pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) + { + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE)*pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + } + else + { +#ifdef CH32V30x_D8 + if((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) + { + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; + } +#else + if(RCC->CFGR2 & (1<<16)){ /* PLL2 */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE/(((RCC->CFGR2 & 0xF0)>>4) + 1); /* PREDIV2 */ + + Pll2mull = (uint8_t)((RCC->CFGR2 & 0xF00)>>8); + + if(Pll2mull == 0) RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency * 5)>>1; + else if(Pll2mull == 1) RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency * 25)>>1; + else if(Pll2mull == 15) RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency * 20; + else RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency * (Pll2mull + 2); + + RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */ + } + else{/* HSE */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */ + } + + RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency * pllmull; + +#endif + } + + if(Pll_6_5 == 1) + RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency / 2); + + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/********************************************************************* + * @fn RCC_AHBPeriphClockCmd + * + * @brief Enables or disables the AHB peripheral clock. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. + * RCC_AHBPeriph_DMA1. + * RCC_AHBPeriph_DMA2. + * RCC_AHBPeriph_SRAM. + * RCC_AHBPeriph_CRC. + * RCC_AHBPeriph_FSMC + * RCC_AHBPeriph_RNG + * RCC_AHBPeriph_SDIO + * RCC_AHBPeriph_USBHS + * RCC_AHBPeriph_USBFS + * RCC_AHBPeriph_DVP + * RCC_AHBPeriph_ETH_MAC + * RCC_AHBPeriph_ETH_MAC_Tx + * RCC_AHBPeriph_ETH_MAC_Rx + * Note- + * SRAM clock can be disabled only during sleep mode. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->AHBPCENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCENR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphClockCmd + * + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_ADC2 + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_TIM8 + * RCC_APB2Periph_USART1. + * RCC_APB2Periph_TIM9 + * RCC_APB2Periph_TIM10 + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PCENR |= RCC_APB2Periph; + } + else + { + RCC->APB2PCENR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_TIM5 + * RCC_APB1Periph_TIM6 + * RCC_APB1Periph_TIM7 + * RCC_APB1Periph_UART6 + * RCC_APB1Periph_UART7 + * RCC_APB1Periph_UART8 + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_SPI3. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_UART4 + * RCC_APB1Periph_UART5 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * RCC_APB1Periph_DAC. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PCENR |= RCC_APB1Periph; + } + else + { + RCC->APB1PCENR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphResetCmd + * + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_ADC2 + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_TIM8 + * RCC_APB2Periph_USART1. + * RCC_APB2Periph_TIM9 + * RCC_APB2Periph_TIM10 + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PRSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2PRSTR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphResetCmd + * + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_TIM5 + * RCC_APB1Periph_TIM6 + * RCC_APB1Periph_TIM7 + * RCC_APB1Periph_UART6 + * RCC_APB1Periph_UART7 + * RCC_APB1Periph_UART8 + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_SPI3. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_UART4 + * RCC_APB1Periph_UART5 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * RCC_APB1Periph_DAC. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PRSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1PRSTR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_BackupResetCmd + * + * @brief Forces or releases the Backup domain reset. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1 << 16); + } + else + { + RCC->BDCTLR &= ~(1 << 16); + } +} + +/********************************************************************* + * @fn RCC_ClockSecuritySystemCmd + * + * @brief Enables or disables the Clock Security System. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 19); + } + else + { + RCC->CTLR &= ~(1 << 19); + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * RCC_MCO_HSE - HSE oscillator clock selected. + * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. + * RCC_MCO_PLL2CLK - PLL2 clock selected + * RCC_MCO_PLL3CLK_Div2 - PLL3 clock divided by 2 selected + * RCC_MCO_XT1 - External 3-25 MHz oscillator clock selected + * RCC_MCO_PLL3CLK - PLL3 clock selected + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_HSERDY - HSE oscillator clock ready. + * RCC_FLAG_PLLRDY - PLL clock ready. + * RCC_FLAG_PLL2RDY - PLL2 clock ready. + * RCC_FLAG_PLL3RDY - PLL3 clock ready. + * RCC_FLAG_LSERDY - LSE oscillator clock ready. + * RCC_FLAG_LSIRDY - LSI oscillator clock ready. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if(tmp == 1) + { + statusreg = RCC->CTLR; + } + else if(tmp == 2) + { + statusreg = RCC->BDCTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * Note- + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + +/********************************************************************* + * @fn RCC_GetITStatus + * + * @brief Checks whether the specified RCC interrupt has occurred or not. + * + * @param RCC_IT - specifies the RCC interrupt source to check. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_PLL2RDY - PLL2 ready interrupt. + * RCC_IT_PLL3RDY - PLL3 ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return ITStatus - SET or RESET. + */ + +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + if((RCC->INTR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearITPendingBit + * + * @brief Clears the RCC's interrupt pending bits. + * + * @param RCC_IT - specifies the interrupt pending bit to clear. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_PLL2RDY - PLL2 ready interrupt. + * RCC_IT_PLL3RDY - PLL3 ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return none + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT; +} + +/********************************************************************* + * @fn RCC_PREDIV1Config + * + * @brief Configures the PREDIV1 division factor. + * + * @param RCC_PREDIV1_Source - specifies the PREDIV1 clock source. + * RCC_PREDIV1_Source_HSE - HSE selected as PREDIV1 clock + * RCC_PREDIV1_Source_PLL2 - PLL2 selected as PREDIV1 clock + * RCC_PREDIV1_Div - specifies the PREDIV1 clock division factor. + * This parameter can be RCC_PREDIV1_Divx where x[1,16] + * Note- + * - This function must be used only when the PLL is disabled. + * + * @return none + */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); + tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PREDIV2Config + * + * @brief Configures the PREDIV2 division factor. + * + * @param RCC_PREDIV2_Div - specifies the PREDIV2 clock division factor. + * This parameter can be RCC_PREDIV2_Divx where x:[1,16] + * Note- + * - This function must be used only when both PLL2 and PLL3 are disabled. + * + * @return none + */ +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~CFGR2_PREDIV2; + tmpreg |= RCC_PREDIV2_Div; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLL2Config + * + * @brief Configures the PLL2 multiplication factor. + * + * @param RCC_PLL2Mul - specifies the PLL2 multiplication factor. + * This parameter can be RCC_PLL2Mul_x where x:{[4,16], 2.5, 12.5, 20} + * Note- + * - This function must be used only when the PLL2 is disabled. + * + * @return none + */ +void RCC_PLL2Config(uint32_t RCC_PLL2Mul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~CFGR2_PLL2MUL; + tmpreg |= RCC_PLL2Mul; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLL2Cmd + * + * @brief Enables or disables the PLL2. + * + * @param NewState - new state of the PLL2. This parameter can be + * ENABLE or DISABLE. + * Note- + * - The PLL2 can not be disabled if it is used indirectly as system clock + * (i.e. it is used as PLL clock entry that is used as System clock). + * + * @return none + */ +void RCC_PLL2Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 26); + } + else + { + RCC->CTLR &= ~(1 << 26); + } +} + +/********************************************************************* + * @fn RCC_PLL3Config + * + * @brief Configures the PLL3 multiplication factor. + * + * @param RCC_PLL3Mul - specifies the PLL3 multiplication factor. + * This parameter can be RCC_PLL3Mul_x where x:{[4,16], 2.5, 12.5, 20} + * Note- + * - This function must be used only when the PLL3 is disabled. + * + * @return none + */ +void RCC_PLL3Config(uint32_t RCC_PLL3Mul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~CFGR2_PLL3MUL; + tmpreg |= RCC_PLL3Mul; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLL3Cmd + * + * @brief Enables or disables the PLL3. + * + * @param NewState - new state of the PLL2. This parameter can be + * ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLL3Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 28); + } + else + { + RCC->CTLR &= ~(1 << 28); + } +} + +/********************************************************************* + * @fn RCC_USBFSCLKConfig + * + * @brief Configures the USB OTG FS clock (USBFSCLK). + * + * @param RCC_USBFSCLKSource - specifies the USB OTG FS clock source. + * RCC_USBFSCLKSource_PLLCLK_Div1 - PLL clock divided by 1 + * selected as USB OTG FS clock source + * RCC_USBFSCLKSource_PLLCLK_Div2 - PLL clock divided by 2 + * selected as USB OTG FS clock source + * RCC_USBFSCLKSource_PLLCLK_Div3 - PLL clock divided by 3 + * selected as USB OTG FS clock source + * + * @return none + */ +void RCC_USBFSCLKConfig(uint32_t RCC_USBFSCLKSource) +{ + RCC->CFGR0 &= ~(3 << 22); + RCC->CFGR0 |= RCC_USBFSCLKSource << 22; +} + +/********************************************************************* + * @fn RCC_I2S2CLKConfig + * + * @brief Configures the I2S2 clock source(I2S2CLK). + * + * @param RCC_I2S2CLKSource - specifies the I2S2 clock source. + * RCC_I2S2CLKSource_SYSCLK - system clock selected as I2S2 clock entry + * RCC_I2S2CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S2 clock entry + * Note- + * - This function must be called before enabling I2S2 APB clock. + * @return none + */ +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) +{ + RCC->CFGR2 &= ~(1 << 17); + RCC->CFGR2 |= RCC_I2S2CLKSource << 17; +} + +/********************************************************************* + * @fn RCC_I2S3CLKConfig + * + * @brief Configures the I2S3 clock source(I2S2CLK). + * + * @param RCC_I2S3CLKSource - specifies the I2S3 clock source. + * RCC_I2S3CLKSource_SYSCLK - system clock selected as I2S3 clock entry + * RCC_I2S3CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S3 clock entry + * Note- + * - This function must be called before enabling I2S3 APB clock. + * @return none + */ +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) +{ + RCC->CFGR2 &= ~(1 << 18); + RCC->CFGR2 |= RCC_I2S3CLKSource << 18; +} + +/********************************************************************* + * @fn RCC_AHBPeriphResetCmd + * + * @brief Forces or releases AHB peripheral reset. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to reset. + * RCC_AHBPeriph_USBFS + * RCC_AHBPeriph_ETH_MAC + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_ADCCLKADJcmd + * + * @brief Enable ADC clock duty cycle adjustment. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ADCCLKADJcmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->CFGR0 |= (1 << 31); + } + else + { + RCC->CFGR0 &= ~(1 << 31); + } +} + +/********************************************************************* + * @fn RCC_RNGCLKConfig + * + * @brief Configures the RNG clock source. + * + * @param RCC_RNGCLKSource - specifies the RNG clock source. + * RCC_RNGCLKSource_SYSCLK - system clock selected as RNG clock entry + * RCC_RNGCLKSource_PLL3_VCO - PLL3 VCO clock selected as RNG clock entry + * + * @return none + */ +void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource) +{ + RCC->CFGR2 &= ~(1 << 19); + RCC->CFGR2 |= RCC_RNGCLKSource << 19; +} + +/********************************************************************* + * @fn RCC_ETH1GCLKConfig + * + * @brief Configures the ETH1G clock source. + * + * @param RCC_RNGCLKSource - specifies the ETH1G clock source. + * RCC_ETH1GCLKSource_PLL2_VCO - system clock selected as ETH1G clock entry + * RCC_ETH1GCLKSource_PLL3_VCO - PLL3 VCO clock selected as ETH1G clock entry + * RCC_ETH1GCLKSource_PB1_IN - GPIO PB1 input clock selected as ETH1G clock entry + * + * @return none + */ +void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource) +{ + RCC->CFGR2 &= ~(3 << 20); + RCC->CFGR2 |= RCC_ETH1GCLKSource << 20; +} + +/********************************************************************* + * @fn RCC_ETH1G_125Mcmd + * + * @brief Enable ETH1G 125M. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ETH1G_125Mcmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->CFGR2 |= (1 << 22); + } + else + { + RCC->CFGR2 &= ~(1 << 22); + } +} + +/********************************************************************* + * @fn RCC_USBHSConfig + * + * @brief Configures the USBHS clock. + * + * @param RCC_USBHS - defines the USBHS clock divider. + * RCC_USBPLL_Div1 - USBHS clock = USBPLL. + * RCC_USBPLL_Div2 - USBHS clock = USBPLL/2. + * RCC_USBPLL_Div3 - USBHS clock = USBPLL/3. + * RCC_USBPLL_Div4 - USBHS clock = USBPLL/4. + * RCC_USBPLL_Div5 - USBHS clock = USBPLL/5. + * RCC_USBPLL_Div6 - USBHS clock = USBPLL/6. + * RCC_USBPLL_Div7 - USBHS clock = USBPLL/7. + * RCC_USBPLL_Div8 - USBHS clock = USBPLL/8. + * + * @return none + */ +void RCC_USBHSConfig(uint32_t RCC_USBHS) +{ + RCC->CFGR2 &= ~(7 << 24); + RCC->CFGR2 |= RCC_USBHS << 24; +} + +/********************************************************************* + * @fn RCC_USBHSPLLCLKConfig + * + * @brief Configures the USBHSPLL clock source. + * + * @param RCC_HSBHSPLLCLKSource - specifies the USBHSPLL clock source. + * RCC_HSBHSPLLCLKSource_HSE - HSE clock selected as USBHSPLL clock entry + * RCC_HSBHSPLLCLKSource_HSI - HSI clock selected as USBHSPLL clock entry + * + * @return none + */ +void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource) +{ + RCC->CFGR2 &= ~(1 << 27); + RCC->CFGR2 |= RCC_USBHSPLLCLKSource << 27; +} + +/********************************************************************* + * @fn RCC_USBHSPLLCKREFCLKConfig + * + * @brief Configures the USBHSPLL reference clock. + * + * @param RCC_USBHSPLLCKREFCLKSource - Select reference clock. + * RCC_USBHSPLLCKREFCLK_3M - reference clock 3Mhz. + * RCC_USBHSPLLCKREFCLK_4M - reference clock 4Mhz. + * RCC_USBHSPLLCKREFCLK_8M - reference clock 8Mhz. + * RCC_USBHSPLLCKREFCLK_5M - reference clock 5Mhz. + * + * @return none + */ +void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource) +{ + RCC->CFGR2 &= ~(3 << 28); + RCC->CFGR2 |= RCC_USBHSPLLCKREFCLKSource << 28; +} + +/********************************************************************* + * @fn RCC_USBHSPHYPLLALIVEcmd + * + * @brief Enable USBHS PHY control. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->CFGR2 |= (1 << 30); + } + else + { + RCC->CFGR2 &= ~(1 << 30); + } +} + +/********************************************************************* + * @fn RCC_USBCLK48MConfig + * + * @brief Configures the USB clock 48MHz source. + * + * @param RCC_USBCLK48MSource - specifies the USB clock 48MHz source. + * RCC_USBCLK48MCLKSource_PLLCLK - PLLCLK clock selected as USB clock 48MHz clock entry + * RCC_USBCLK48MCLKSource_USBPHY - USBPHY clock selected as USB clock 48MHz clock entry + * + * @return none + */ +void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource) +{ + RCC->CFGR2 &= ~(1 << 31); + RCC->CFGR2 |= RCC_USBCLK48MSource << 31; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_rng.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_rng.c index faea0ab..918e265 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_rng.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_rng.c @@ -1,154 +1,154 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_rng.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the RNG firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_rng.h" -#include "ch32v30x_rcc.h" - -/********************************************************************* - * @fn RNG_Cmd - * - * @brief Enables or disables the RNG peripheral. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RNG_Cmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RNG->CR |= RNG_CR_RNGEN; - } - else - { - RNG->CR &= ~RNG_CR_RNGEN; - } -} - -/********************************************************************* - * @fn RNG_GetRandomNumber - * - * @brief Returns a 32-bit random number. - * - * @return 32-bit random number. - */ -uint32_t RNG_GetRandomNumber(void) -{ - return RNG->DR; -} - -/********************************************************************* - * @fn RNG_ITConfig - * - * @brief Enables or disables the RNG interrupt. - * - * @param NewState - ENABLE or DISABLE. - * - * @return 32-bit random number. - */ -void RNG_ITConfig(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RNG->CR |= RNG_CR_IE; - } - else - { - RNG->CR &= ~RNG_CR_IE; - } -} - -/********************************************************************* - * @fn RNG_GetFlagStatus - * - * @brief Checks whether the specified RNG flag is set or not. - * - * @param RNG_FLAG - specifies the RNG flag to check. - * RNG_FLAG_DRDY - Data Ready flag. - * RNG_FLAG_CECS - Clock Error Current flag. - * RNG_FLAG_SECS - Seed Error Current flag. - * - * @return 32-bit random number. - */ -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((RNG->SR & RNG_FLAG) != (uint8_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RNG_ClearFlag - * - * @brief Clears the RNG flags. - * - * @param RNG_FLAG - specifies the flag to clear. - * RNG_FLAG_CECS - Clock Error Current flag. - * RNG_FLAG_SECS - Seed Error Current flag. - * - * @return 32-bit random number. - */ -void RNG_ClearFlag(uint8_t RNG_FLAG) -{ - RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); -} - -/********************************************************************* - * @fn RNG_GetFlagStatus - * - * @brief Checks whether the specified RNG interrupt has occurred or not. - * - * @param RNG_IT - specifies the RNG interrupt source to check. - * RNG_IT_CEI - Clock Error Interrupt. - * RNG_IT_SEI - Seed Error Interrupt. - * - * @return bitstatus:SET or RESET. - */ -ITStatus RNG_GetITStatus(uint8_t RNG_IT) -{ - ITStatus bitstatus = RESET; - - if((RNG->SR & RNG_IT) != (uint8_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RNG_ClearITPendingBit - * - * @brief Clears the RNG interrupt pending bit(s). - * - * @param RNG_IT - specifies the RNG interrupt pending bit(s) to clear. - * RNG_IT_CEI - Clock Error Interrupt. - * RNG_IT_SEI - Seed Error Interrupt. - * - * @return None - */ -void RNG_ClearITPendingBit(uint8_t RNG_IT) -{ - RNG->SR = (uint8_t)~RNG_IT; -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rng.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the RNG firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_rng.h" +#include "ch32v30x_rcc.h" + +/********************************************************************* + * @fn RNG_Cmd + * + * @brief Enables or disables the RNG peripheral. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RNG_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RNG->CR |= RNG_CR_RNGEN; + } + else + { + RNG->CR &= ~RNG_CR_RNGEN; + } +} + +/********************************************************************* + * @fn RNG_GetRandomNumber + * + * @brief Returns a 32-bit random number. + * + * @return 32-bit random number. + */ +uint32_t RNG_GetRandomNumber(void) +{ + return RNG->DR; +} + +/********************************************************************* + * @fn RNG_ITConfig + * + * @brief Enables or disables the RNG interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return 32-bit random number. + */ +void RNG_ITConfig(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RNG->CR |= RNG_CR_IE; + } + else + { + RNG->CR &= ~RNG_CR_IE; + } +} + +/********************************************************************* + * @fn RNG_GetFlagStatus + * + * @brief Checks whether the specified RNG flag is set or not. + * + * @param RNG_FLAG - specifies the RNG flag to check. + * RNG_FLAG_DRDY - Data Ready flag. + * RNG_FLAG_CECS - Clock Error Current flag. + * RNG_FLAG_SECS - Seed Error Current flag. + * + * @return 32-bit random number. + */ +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((RNG->SR & RNG_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RNG_ClearFlag + * + * @brief Clears the RNG flags. + * + * @param RNG_FLAG - specifies the flag to clear. + * RNG_FLAG_CECS - Clock Error Current flag. + * RNG_FLAG_SECS - Seed Error Current flag. + * + * @return 32-bit random number. + */ +void RNG_ClearFlag(uint8_t RNG_FLAG) +{ + RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); +} + +/********************************************************************* + * @fn RNG_GetFlagStatus + * + * @brief Checks whether the specified RNG interrupt has occurred or not. + * + * @param RNG_IT - specifies the RNG interrupt source to check. + * RNG_IT_CEI - Clock Error Interrupt. + * RNG_IT_SEI - Seed Error Interrupt. + * + * @return bitstatus:SET or RESET. + */ +ITStatus RNG_GetITStatus(uint8_t RNG_IT) +{ + ITStatus bitstatus = RESET; + + if((RNG->SR & RNG_IT) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RNG_ClearITPendingBit + * + * @brief Clears the RNG interrupt pending bit(s). + * + * @param RNG_IT - specifies the RNG interrupt pending bit(s) to clear. + * RNG_IT_CEI - Clock Error Interrupt. + * RNG_IT_SEI - Seed Error Interrupt. + * + * @return None + */ +void RNG_ClearITPendingBit(uint8_t RNG_IT) +{ + RNG->SR = (uint8_t)~RNG_IT; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_rtc.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_rtc.c index 7628bc1..c3f5de9 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_rtc.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_rtc.c @@ -1,279 +1,315 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_rtc.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the RTC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_rtc.h" - -/* RTC_Private_Defines */ -#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ -#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ - -/********************************************************************* - * @fn RTC_ITConfig - * - * @brief Enables or disables the specified RTC interrupts. - * - * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. - * RTC_IT_OW - Overflow interrupt - * RTC_IT_ALR - Alarm interrupt - * RTC_IT_SEC - Second interrupt - * - * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). - */ -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RTC->CTLRH |= RTC_IT; - } - else - { - RTC->CTLRH &= (uint16_t)~RTC_IT; - } -} - -/********************************************************************* - * @fn RTC_EnterConfigMode - * - * @brief Enters the RTC configuration mode. - * - * @return none - */ -void RTC_EnterConfigMode(void) -{ - RTC->CTLRL |= RTC_CTLRL_CNF; -} - -/********************************************************************* - * @fn RTC_ExitConfigMode - * - * @brief Exits from the RTC configuration mode. - * - * @return none - */ -void RTC_ExitConfigMode(void) -{ - RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); -} - -/********************************************************************* - * @fn RTC_GetCounter - * - * @brief Gets the RTC counter value - * - * @return RTC counter value - */ -uint32_t RTC_GetCounter(void) -{ - uint16_t high1 = 0, high2 = 0, low = 0; - - high1 = RTC->CNTH; - low = RTC->CNTL; - high2 = RTC->CNTH; - - if(high1 != high2) - { - return (((uint32_t)high2 << 16) | RTC->CNTL); - } - else - { - return (((uint32_t)high1 << 16) | low); - } -} - -/********************************************************************* - * @fn RTC_SetCounter - * - * @brief Sets the RTC counter value. - * - * @param CounterValue - RTC counter new value. - * - * @return RTC counter value - */ -void RTC_SetCounter(uint32_t CounterValue) -{ - RTC_EnterConfigMode(); - RTC->CNTH = CounterValue >> 16; - RTC->CNTL = (CounterValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/********************************************************************* - * @fn RTC_SetPrescaler - * - * @brief Sets the RTC prescaler value - * - * @param PrescalerValue - RTC prescaler new value - * - * @return none - */ -void RTC_SetPrescaler(uint32_t PrescalerValue) -{ - RTC_EnterConfigMode(); - RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; - RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/********************************************************************* - * @fn RTC_SetAlarm - * - * @brief Sets the RTC alarm value - * - * @param AlarmValue - RTC alarm new value - * - * @return none - */ -void RTC_SetAlarm(uint32_t AlarmValue) -{ - RTC_EnterConfigMode(); - RTC->ALRMH = AlarmValue >> 16; - RTC->ALRML = (AlarmValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/********************************************************************* - * @fn RTC_GetDivider - * - * @brief Gets the RTC divider value - * - * @return RTC Divider value - */ -uint32_t RTC_GetDivider(void) -{ - uint32_t tmp = 0x00; - tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; - tmp |= RTC->DIVL; - return tmp; -} - -/********************************************************************* - * @fn RTC_WaitForLastTask - * - * @brief Waits until last write operation on RTC registers has finished - * Note- - * This function must be called before any write to RTC registers. - * @return none - */ -void RTC_WaitForLastTask(void) -{ - while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) - { - } -} - -/********************************************************************* - * @fn RTC_WaitForSynchro - * - * @brief Waits until the RTC registers are synchronized with RTC APB clock - * Note- - * This function must be called before any read operation after an APB reset - * or an APB clock stop. - * - * @return none - */ -void RTC_WaitForSynchro(void) -{ - RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; - while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) - { - } -} - -/********************************************************************* - * @fn RTC_GetFlagStatus - * - * @brief Checks whether the specified RTC flag is set or not - * - * @param RTC_FLAG- specifies the flag to check - * RTC_FLAG_RTOFF - RTC Operation OFF flag - * RTC_FLAG_RSF - Registers Synchronized flag - * RTC_FLAG_OW - Overflow flag - * RTC_FLAG_ALR - Alarm flag - * RTC_FLAG_SEC - Second flag - * - * @return The new state of RTC_FLAG (SET or RESET) - */ -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn RTC_ClearFlag - * - * @brief Clears the RTC's pending flags - * - * @param RTC_FLAG - specifies the flag to clear - * RTC_FLAG_RSF - Registers Synchronized flag - * RTC_FLAG_OW - Overflow flag - * RTC_FLAG_ALR - Alarm flag - * RTC_FLAG_SEC - Second flag - * - * @return none - */ -void RTC_ClearFlag(uint16_t RTC_FLAG) -{ - RTC->CTLRL &= (uint16_t)~RTC_FLAG; -} - -/********************************************************************* - * @fn RTC_GetITStatus - * - * @brief Checks whether the specified RTC interrupt has occurred or not - * - * @param RTC_IT - specifies the RTC interrupts sources to check - * RTC_FLAG_OW - Overflow interrupt - * RTC_FLAG_ALR - Alarm interrupt - * RTC_FLAG_SEC - Second interrupt - * - * @return The new state of the RTC_IT (SET or RESET) - */ -ITStatus RTC_GetITStatus(uint16_t RTC_IT) -{ - ITStatus bitstatus = RESET; - - bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); - if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn RTC_ClearITPendingBit - * - * @brief Clears the RTC's interrupt pending bits - * - * @param RTC_IT - specifies the interrupt pending bit to clear - * RTC_FLAG_OW - Overflow interrupt - * RTC_FLAG_ALR - Alarm interrupt - * RTC_FLAG_SEC - Second interrupt - * - * @return none - */ -void RTC_ClearITPendingBit(uint16_t RTC_IT) -{ - RTC->CTLRL &= (uint16_t)~RTC_IT; -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rtc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the RTC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_rtc.h" + +/* RTC_Private_Defines */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ + +/********************************************************************* + * @fn RTC_ITConfig + * + * @brief Enables or disables the specified RTC interrupts. + * + * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. + * RTC_IT_OW - Overflow interrupt + * RTC_IT_ALR - Alarm interrupt + * RTC_IT_SEC - Second interrupt + * + * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RTC->CTLRH |= RTC_IT; + } + else + { + RTC->CTLRH &= (uint16_t)~RTC_IT; + } +} + +/********************************************************************* + * @fn RTC_EnterConfigMode + * + * @brief Enters the RTC configuration mode. + * + * @return none + */ +void RTC_EnterConfigMode(void) +{ + RTC->CTLRL |= RTC_CTLRL_CNF; +} + +/********************************************************************* + * @fn RTC_ExitConfigMode + * + * @brief Exits from the RTC configuration mode. + * + * @return none + */ +void RTC_ExitConfigMode(void) +{ + RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); +} + +/********************************************************************* + * @fn RTC_GetCounter + * + * @brief Gets the RTC counter value + * + * @return RTC counter value + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0; + uint16_t low1 = 0, low2 = 0; + + do{ + high1a = RTC->CNTH; + high1b = RTC->CNTH; + }while( high1a != high1b ); + + do{ + low1 = RTC->CNTL; + low2 = RTC->CNTL; + }while( low1 != low2 ); + + do{ + high2a = RTC->CNTH; + high2b = RTC->CNTH; + }while( high2a != high2b ); + + if(high1b != high2b) + { + do{ + low1 = RTC->CNTL; + low2 = RTC->CNTL; + }while( low1 != low2 ); + } + + return (((uint32_t)high2b << 16) | low2); +} + +/********************************************************************* + * @fn RTC_SetCounter + * + * @brief Sets the RTC counter value. + * + * @param CounterValue - RTC counter new value. + * + * @return RTC counter value + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + RTC->CNTH = CounterValue >> 16; + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetPrescaler + * + * @brief Sets the RTC prescaler value + * + * @param PrescalerValue - RTC prescaler new value + * + * @return none + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + RTC_EnterConfigMode(); + RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetAlarm + * + * @brief Sets the RTC alarm value + * + * @param AlarmValue - RTC alarm new value + * + * @return none + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + RTC->ALRMH = AlarmValue >> 16; + RTC->ALRML = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_GetDivider + * + * @brief Gets the RTC divider value + * + * @return RTC Divider value + */ +uint32_t RTC_GetDivider(void) +{ + uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0; + uint16_t low1 = 0, low2 = 0; + + do{ + high1a = RTC->DIVH; + high1b = RTC->DIVH; + }while( high1a != high1b ); + + do{ + low1 = RTC->DIVL; + low2 = RTC->DIVL; + }while( low1 != low2 ); + + do{ + high2a = RTC->DIVH; + high2b = RTC->DIVH; + }while( high2a != high2b ); + + if(high1b != high2b) + { + do{ + low1 = RTC->DIVL; + low2 = RTC->DIVL; + }while( low1 != low2 ); + } + + return ((((uint32_t)high2b & (uint32_t)0x000F) << 16) | low2); +} + +/********************************************************************* + * @fn RTC_WaitForLastTask + * + * @brief Waits until last write operation on RTC registers has finished + * Note- + * This function must be called before any write to RTC registers. + * @return none + */ +void RTC_WaitForLastTask(void) +{ + while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_WaitForSynchro + * + * @brief Waits until the RTC registers are synchronized with RTC APB clock + * Note- + * This function must be called before any read operation after an APB reset + * or an APB clock stop. + * + * @return none + */ +void RTC_WaitForSynchro(void) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; + while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_GetFlagStatus + * + * @brief Checks whether the specified RTC flag is set or not + * + * @param RTC_FLAG- specifies the flag to check + * RTC_FLAG_RTOFF - RTC Operation OFF flag + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return The new state of RTC_FLAG (SET or RESET) + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearFlag + * + * @brief Clears the RTC's pending flags + * + * @param RTC_FLAG - specifies the flag to clear + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return none + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG; +} + +/********************************************************************* + * @fn RTC_GetITStatus + * + * @brief Checks whether the specified RTC interrupt has occurred or not + * + * @param RTC_IT - specifies the RTC interrupts sources to check + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return The new state of the RTC_IT (SET or RESET) + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + + bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); + if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearITPendingBit + * + * @brief Clears the RTC's interrupt pending bits + * + * @param RTC_IT - specifies the interrupt pending bit to clear + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return none + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + RTC->CTLRL &= (uint16_t)~RTC_IT; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_sdio.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_sdio.c index 075a5f6..edfe15f 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_sdio.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_sdio.c @@ -1,672 +1,672 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_SDIO.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the SDIO firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_sdio.h" -#include "ch32v30x_rcc.h" - -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) - -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) - -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/********************************************************************* - * @fn SDIO_DeInit - * - * @brief Deinitializes the SDIO peripheral registers to their default - * reset values. - * - * @return RTC counter value - */ -void SDIO_DeInit(void) -{ - SDIO->POWER = 0x00000000; - SDIO->CLKCR = 0x00000000; - SDIO->ARG = 0x00000000; - SDIO->CMD = 0x00000000; - SDIO->DTIMER = 0x00000000; - SDIO->DLEN = 0x00000000; - SDIO->DCTRL = 0x00000000; - SDIO->ICR = 0x00C007FF; - SDIO->MASK = 0x00000000; -} - -/********************************************************************* - * @fn SDIO_Init - * - * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. - * - * @param SDIO_InitStruct - pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. - * - * @return None - */ -void SDIO_Init(SDIO_InitTypeDef *SDIO_InitStruct) -{ - uint32_t tmpreg = 0; - - tmpreg = SDIO->CLKCR; - tmpreg &= CLKCR_CLEAR_MASK; - tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | - SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | - SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); - - SDIO->CLKCR = tmpreg; -} - -/********************************************************************* - * @fn SDIO_StructInit - * - * @brief Fills each SDIO_InitStruct member with its default value. - * - * @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void SDIO_StructInit(SDIO_InitTypeDef *SDIO_InitStruct) -{ - SDIO_InitStruct->SDIO_ClockDiv = 0x00; - SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; -} - -/********************************************************************* - * @fn SDIO_ClockCmd - * - * @brief Enables or disables the SDIO Clock. - * - * @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void SDIO_ClockCmd(FunctionalState NewState) -{ - if(NewState) - SDIO->CLKCR |= (1 << 8); - else - SDIO->CLKCR &= ~(1 << 8); -} - -/********************************************************************* - * @fn SDIO_SetPowerState - * - * @brief Sets the power status of the controller. - * - * @param SDIO_PowerState - new state of the Power state. - * SDIO_PowerState_OFF - * SDIO_PowerState_ON - * - * @return none - */ -void SDIO_SetPowerState(uint32_t SDIO_PowerState) -{ - SDIO->POWER &= PWR_PWRCTRL_MASK; - SDIO->POWER |= SDIO_PowerState; -} - -/********************************************************************* - * @fn SDIO_GetPowerState - * - * @brief Gets the power status of the controller. - * - * @param CounterValue - RTC counter new value. - * - * @return power state - - * 0x00 - Power OFF - * 0x02 - Power UP - * 0x03 - Power ON - */ -uint32_t SDIO_GetPowerState(void) -{ - return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); -} - -/********************************************************************* - * @fn SDIO_ITConfig - * - * @brief Enables or disables the SDIO interrupts. - * - * @param DIO_IT - specifies the SDIO interrupt sources to be enabled or disabled. - * SDIO_IT_CCRCFAIL - * SDIO_IT_DCRCFAIL - * SDIO_IT_CTIMEOUT - * SDIO_IT_DTIMEOUT - * SDIO_IT_TXUNDERR - * SDIO_IT_RXOVERR - * SDIO_IT_CMDREND - * SDIO_IT_CMDSENT - * SDIO_IT_DATAEND - * SDIO_IT_STBITERR - * SDIO_IT_DBCKEND - * SDIO_IT_CMDACT - * SDIO_IT_TXACT - * SDIO_IT_RXACT - * SDIO_IT_TXFIFOHE - * SDIO_IT_RXFIFOHF - * SDIO_IT_TXFIFOF - * SDIO_IT_RXFIFOF - * SDIO_IT_TXFIFOE - * SDIO_IT_RXFIFOE - * SDIO_IT_TXDAVL - * SDIO_IT_RXDAVL - * SDIO_IT_SDIOIT - * SDIO_IT_CEATAEND - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SDIO->MASK |= SDIO_IT; - } - else - { - SDIO->MASK &= ~SDIO_IT; - } -} - -/********************************************************************* - * @fn SDIO_DMACmd - * - * @brief Enables or disables the SDIO DMA request. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void SDIO_DMACmd(FunctionalState NewState) -{ - if(NewState) - SDIO->DCTRL |= (1 << 3); - else - SDIO->DCTRL &= ~(1 << 3); -} - -/********************************************************************* - * @fn SDIO_SendCommand - * - * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. - * @param SDIO_CmdInitStruct - pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for - * ddthe SDIO command. - * - * @return none - */ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; - - tmpreg = SDIO->CMD; - tmpreg &= CMD_CLEAR_MASK; - tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; - - SDIO->CMD = tmpreg; -} - -/********************************************************************* - * @fn SDIO_CmdStructInit - * - * @brief Fills each SDIO_CmdInitStruct member with its default value. - * - * @param SDIO_CmdInitStruct - pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. - * - * @return none - */ -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -/********************************************************************* - * @fn SDIO_GetCommandResponse - * - * @brief Returns command index of last command for which response received. - * - * @return Returns the command index of the last command response received. - */ -uint8_t SDIO_GetCommandResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/********************************************************************* - * @fn SDIO_GetResponse - * - * @brief Returns response received from the card for the last command. - * - * @param SDIO_RESP - Specifies the SDIO response register. - * SDIO_RESP1 - Response Register 1 - * SDIO_RESP2 - Response Register 2 - * SDIO_RESP3 - Response Register 3 - * SDIO_RESP4 - Response Register 4 - * - * @return Returns the command index of the last command response received. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *)tmp); -} - -/********************************************************************* - * @fn SDIO_DataConfig - * - * @brief Initializes the SDIO data path according to the specified - * - * @param SDIO_DataInitStruct - pointer to a SDIO_DataInitTypeDef structure that - * contains the configuration information for the SDIO command. - * - * @return none - */ -void SDIO_DataConfig(SDIO_DataInitTypeDef *SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; - SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; - tmpreg = SDIO->DCTRL; - tmpreg &= DCTRL_CLEAR_MASK; - tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - - SDIO->DCTRL = tmpreg; -} - -/********************************************************************* - * @fn SDIO_DataStructInit - * - * @brief Fills each SDIO_DataInitStruct member with its default value. - * - * @param SDIO_DataInitStruct - pointer to an SDIO_DataInitTypeDef - * structure which will be initialized. - * - * @return RTC counter value - */ -void SDIO_DataStructInit(SDIO_DataInitTypeDef *SDIO_DataInitStruct) -{ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/********************************************************************* - * @fn SDIO_GetDataCounter - * - * @brief Returns number of remaining data bytes to be transferred. - * - * @return Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(void) -{ - return SDIO->DCOUNT; -} - -/********************************************************************* - * @fn SDIO_ReadData - * - * @brief Read one data word from Rx FIFO. - * - * @return Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/********************************************************************* - * @fn SDIO_WriteData - * - * @brief Write one data word to Tx FIFO. - * - * @param Data - 32-bit data word to write. - * - * @return RTC counter value - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/********************************************************************* - * @fn SDIO_GetFIFOCount - * - * @brief Returns the number of words left to be written to or read from FIFO. - * - * @return Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/********************************************************************* - * @fn SDIO_StartSDIOReadWait - * - * @brief Starts the SD I/O Read Wait operation. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void SDIO_StartSDIOReadWait(FunctionalState NewState) -{ - if(NewState) - SDIO->DCTRL |= (1 << 8); - else - SDIO->DCTRL &= ~(1 << 8); -} - -/********************************************************************* - * @fn SDIO_StopSDIOReadWait - * - * @brief Stops the SD I/O Read Wait operation. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void SDIO_StopSDIOReadWait(FunctionalState NewState) -{ - if(NewState) - SDIO->DCTRL |= (1 << 9); - else - SDIO->DCTRL &= ~(1 << 9); -} - -/********************************************************************* - * @fn SDIO_SetSDIOReadWaitMode - * - * @brief Sets one of the two options of inserting read wait interval. - * - * @param SDIO_ReadWaitMode - SD I/O Read Wait operation mode. - * SDIO_ReadWaitMode_CLK - Read Wait control by stopping SDIOCLK - * SDIO_ReadWaitMode_DATA2 - Read Wait control using SDIO_DATA2 - * - * @return none - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - if(SDIO_ReadWaitMode) - SDIO->DCTRL |= (1 << 10); - else - SDIO->DCTRL &= ~(1 << 10); -} - -/********************************************************************* - * @fn SDIO_SetSDIOOperation - * - * @brief Enables or disables the SD I/O Mode Operation. - * - * @param NewState: ENABLE or DISABLE. - * - * @return none - */ -void SDIO_SetSDIOOperation(FunctionalState NewState) -{ - if(NewState) - SDIO->DCTRL |= (1 << 11); - else - SDIO->DCTRL &= ~(1 << 11); -} - -/********************************************************************* - * @fn SDIO_SendSDIOSuspendCmd - * - * @brief Enables or disables the SD I/O Mode suspend command sending. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) -{ - if(NewState) - SDIO->CMD |= (1 << 11); - else - SDIO->CMD &= ~(1 << 11); -} - -/********************************************************************* - * @fn SDIO_CommandCompletionCmd - * - * @brief Enables or disables the command completion signal. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void SDIO_CommandCompletionCmd(FunctionalState NewState) -{ - if(NewState) - SDIO->CMD |= (1 << 12); - else - SDIO->CMD &= ~(1 << 12); -} - -/********************************************************************* - * @fn SDIO_CEATAITCmd - * - * @brief Enables or disables the CE-ATA interrupt. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void SDIO_CEATAITCmd(FunctionalState NewState) -{ - if(NewState) - SDIO->CMD |= (1 << 13); - else - SDIO->CMD &= ~(1 << 13); -} - -/********************************************************************* - * @fn SDIO_SendCEATACmd - * - * @brief Sends CE-ATA command (CMD61). - * - * @param NewState - ENABLE or DISABLE. - * - * @return RTC counter value - */ -void SDIO_SendCEATACmd(FunctionalState NewState) -{ - if(NewState) - SDIO->CMD |= (1 << 14); - else - SDIO->CMD &= ~(1 << 14); -} - -/********************************************************************* - * @fn SDIO_GetFlagStatus - * - * @brief Checks whether the specified SDIO flag is set or not. - * - * @param SDIO_FLAG - specifies the flag to check. - * SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed) - * SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed) - * SDIO_FLAG_CTIMEOUT - Command response timeout - * SDIO_FLAG_DTIMEOUT - Data timeout - * SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error - * SDIO_FLAG_RXOVERR - Received FIFO overrun error - * SDIO_FLAG_CMDREND - Command response received (CRC check passed) - * SDIO_FLAG_CMDSENT - Command sent (no response required) - * SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero) - * SDIO_FLAG_STBITERR - Start bit not detected on all data signals - * in wide bus mode. - * SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed) - * SDIO_FLAG_CMDACT - Command transfer in progress - * SDIO_FLAG_TXACT - Data transmit in progress - * SDIO_FLAG_RXACT - Data receive in progress - * SDIO_FLAG_TXFIFOHE - Transmit FIFO Half Empty - * SDIO_FLAG_RXFIFOHF - Receive FIFO Half Full - * SDIO_FLAG_TXFIFOF - Transmit FIFO full - * SDIO_FLAG_RXFIFOF - Receive FIFO full - * SDIO_FLAG_TXFIFOE - Transmit FIFO empty - * SDIO_FLAG_RXFIFOE - Receive FIFO empty - * SDIO_FLAG_TXDAVL - Data available in transmit FIFO - * SDIO_FLAG_RXDAVL - Data available in receive FIFO - * SDIO_FLAG_SDIOIT - SD I/O interrupt received - * SDIO_FLAG_CEATAEND - CE-ATA command completion signal received - * for CMD61 - * - * @return ITStatus - SET or RESET - */ -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn SDIO_ClearFlag - * - * @brief Clears the SDIO's pending flags. - * - * @param SDIO_FLAG - specifies the flag to clear. - * SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed) - * SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed) - * SDIO_FLAG_CTIMEOUT - Command response timeout - * SDIO_FLAG_DTIMEOUT - Data timeout - * SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error - * SDIO_FLAG_RXOVERR - Received FIFO overrun error - * SDIO_FLAG_CMDREND - Command response received (CRC check passed) - * SDIO_FLAG_CMDSENT - Command sent (no response required) - * SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero) - * SDIO_FLAG_STBITERR - Start bit not detected on all data signals - * in wide bus mode - * SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed) - * SDIO_FLAG_SDIOIT - SD I/O interrupt received - * SDIO_FLAG_CEATAEND - CE-ATA command completion signal received for CMD61 - * - * @return none - */ -void SDIO_ClearFlag(uint32_t SDIO_FLAG) -{ - SDIO->ICR = SDIO_FLAG; -} - -/********************************************************************* - * @fn SDIO_GetITStatus - * - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * - * @param SDIO_IT: specifies the SDIO interrupt source to check. - * SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt - * SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt - * SDIO_IT_CTIMEOUT - Command response timeout interrupt - * SDIO_IT_DTIMEOUT - Data timeout interrupt - * SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt - * SDIO_IT_RXOVERR - Received FIFO overrun error interrupt - * SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt - * SDIO_IT_CMDSENT - Command sent (no response required) interrupt - * SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt - * SDIO_IT_STBITERR - Start bit not detected on all data signals in wide - * bus mode interrupt - * SDIO_IT_DBCKEND - Data block sent/received (CRC check passed) interrupt - * SDIO_IT_CMDACT - Command transfer in progress interrupt - * SDIO_IT_TXACT - Data transmit in progress interrupt - * SDIO_IT_RXACT - Data receive in progress interrupt - * SDIO_IT_TXFIFOHE - Transmit FIFO Half Empty interrupt - * SDIO_IT_RXFIFOHF - Receive FIFO Half Full interrupt - * SDIO_IT_TXFIFOF - Transmit FIFO full interrupt - * SDIO_IT_RXFIFOF - Receive FIFO full interrupt - * SDIO_IT_TXFIFOE - Transmit FIFO empty interrupt - * SDIO_IT_RXFIFOE - Receive FIFO empty interrupt - * SDIO_IT_TXDAVL - Data available in transmit FIFO interrupt - * SDIO_IT_RXDAVL - Data available in receive FIFO interrupt - * SDIO_IT_SDIOIT - SD I/O interrupt received interrupt - * SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 interrupt - * - * @return ITStatus��SET or RESET - */ -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) -{ - ITStatus bitstatus = RESET; - - if((SDIO->STA & SDIO_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn SDIO_ClearITPendingBit - * - * @brief Clears the SDIO's interrupt pending bits. - * - * @param SDIO_IT - specifies the interrupt pending bit to clear. - * SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt - * SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt - * SDIO_IT_CTIMEOUT - Command response timeout interrupt - * SDIO_IT_DTIMEOUT - Data timeout interrupt - * SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt - * SDIO_IT_RXOVERR - Received FIFO overrun error interrupt - * SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt - * SDIO_IT_CMDSENT - Command sent (no response required) interrupt - * SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt - * SDIO_IT_STBITERR - Start bit not detected on all data signals in wide - * bus mode interrupt - * SDIO_IT_SDIOIT - SD I/O interrupt received interrupt - * SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 - * - * @return RTC counter value - */ -void SDIO_ClearITPendingBit(uint32_t SDIO_IT) -{ - SDIO->ICR = SDIO_IT; -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_SDIO.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the SDIO firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_sdio.h" +#include "ch32v30x_rcc.h" + +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/********************************************************************* + * @fn SDIO_DeInit + * + * @brief Deinitializes the SDIO peripheral registers to their default + * reset values. + * + * @return RTC counter value + */ +void SDIO_DeInit(void) +{ + SDIO->POWER = 0x00000000; + SDIO->CLKCR = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DLEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICR = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/********************************************************************* + * @fn SDIO_Init + * + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * + * @param SDIO_InitStruct - pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * + * @return None + */ +void SDIO_Init(SDIO_InitTypeDef *SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = SDIO->CLKCR; + tmpreg &= CLKCR_CLEAR_MASK; + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + SDIO->CLKCR = tmpreg; +} + +/********************************************************************* + * @fn SDIO_StructInit + * + * @brief Fills each SDIO_InitStruct member with its default value. + * + * @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SDIO_StructInit(SDIO_InitTypeDef *SDIO_InitStruct) +{ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/********************************************************************* + * @fn SDIO_ClockCmd + * + * @brief Enables or disables the SDIO Clock. + * + * @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CLKCR |= (1 << 8); + else + SDIO->CLKCR &= ~(1 << 8); +} + +/********************************************************************* + * @fn SDIO_SetPowerState + * + * @brief Sets the power status of the controller. + * + * @param SDIO_PowerState - new state of the Power state. + * SDIO_PowerState_OFF + * SDIO_PowerState_ON + * + * @return none + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + SDIO->POWER &= PWR_PWRCTRL_MASK; + SDIO->POWER |= SDIO_PowerState; +} + +/********************************************************************* + * @fn SDIO_GetPowerState + * + * @brief Gets the power status of the controller. + * + * @param CounterValue - RTC counter new value. + * + * @return power state - + * 0x00 - Power OFF + * 0x02 - Power UP + * 0x03 - Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/********************************************************************* + * @fn SDIO_ITConfig + * + * @brief Enables or disables the SDIO interrupts. + * + * @param DIO_IT - specifies the SDIO interrupt sources to be enabled or disabled. + * SDIO_IT_CCRCFAIL + * SDIO_IT_DCRCFAIL + * SDIO_IT_CTIMEOUT + * SDIO_IT_DTIMEOUT + * SDIO_IT_TXUNDERR + * SDIO_IT_RXOVERR + * SDIO_IT_CMDREND + * SDIO_IT_CMDSENT + * SDIO_IT_DATAEND + * SDIO_IT_STBITERR + * SDIO_IT_DBCKEND + * SDIO_IT_CMDACT + * SDIO_IT_TXACT + * SDIO_IT_RXACT + * SDIO_IT_TXFIFOHE + * SDIO_IT_RXFIFOHF + * SDIO_IT_TXFIFOF + * SDIO_IT_RXFIFOF + * SDIO_IT_TXFIFOE + * SDIO_IT_RXFIFOE + * SDIO_IT_TXDAVL + * SDIO_IT_RXDAVL + * SDIO_IT_SDIOIT + * SDIO_IT_CEATAEND + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SDIO->MASK |= SDIO_IT; + } + else + { + SDIO->MASK &= ~SDIO_IT; + } +} + +/********************************************************************* + * @fn SDIO_DMACmd + * + * @brief Enables or disables the SDIO DMA request. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 3); + else + SDIO->DCTRL &= ~(1 << 3); +} + +/********************************************************************* + * @fn SDIO_SendCommand + * + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct - pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for + * ddthe SDIO command. + * + * @return none + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + + tmpreg = SDIO->CMD; + tmpreg &= CMD_CLEAR_MASK; + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + SDIO->CMD = tmpreg; +} + +/********************************************************************* + * @fn SDIO_CmdStructInit + * + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * + * @param SDIO_CmdInitStruct - pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/********************************************************************* + * @fn SDIO_GetCommandResponse + * + * @brief Returns command index of last command for which response received. + * + * @return Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/********************************************************************* + * @fn SDIO_GetResponse + * + * @brief Returns response received from the card for the last command. + * + * @param SDIO_RESP - Specifies the SDIO response register. + * SDIO_RESP1 - Response Register 1 + * SDIO_RESP2 - Response Register 2 + * SDIO_RESP3 - Response Register 3 + * SDIO_RESP4 - Response Register 4 + * + * @return Returns the command index of the last command response received. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn SDIO_DataConfig + * + * @brief Initializes the SDIO data path according to the specified + * + * @param SDIO_DataInitStruct - pointer to a SDIO_DataInitTypeDef structure that + * contains the configuration information for the SDIO command. + * + * @return none + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef *SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + tmpreg = SDIO->DCTRL; + tmpreg &= DCTRL_CLEAR_MASK; + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + SDIO->DCTRL = tmpreg; +} + +/********************************************************************* + * @fn SDIO_DataStructInit + * + * @brief Fills each SDIO_DataInitStruct member with its default value. + * + * @param SDIO_DataInitStruct - pointer to an SDIO_DataInitTypeDef + * structure which will be initialized. + * + * @return RTC counter value + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef *SDIO_DataInitStruct) +{ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/********************************************************************* + * @fn SDIO_GetDataCounter + * + * @brief Returns number of remaining data bytes to be transferred. + * + * @return Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/********************************************************************* + * @fn SDIO_ReadData + * + * @brief Read one data word from Rx FIFO. + * + * @return Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/********************************************************************* + * @fn SDIO_WriteData + * + * @brief Write one data word to Tx FIFO. + * + * @param Data - 32-bit data word to write. + * + * @return RTC counter value + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/********************************************************************* + * @fn SDIO_GetFIFOCount + * + * @brief Returns the number of words left to be written to or read from FIFO. + * + * @return Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/********************************************************************* + * @fn SDIO_StartSDIOReadWait + * + * @brief Starts the SD I/O Read Wait operation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 8); + else + SDIO->DCTRL &= ~(1 << 8); +} + +/********************************************************************* + * @fn SDIO_StopSDIOReadWait + * + * @brief Stops the SD I/O Read Wait operation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 9); + else + SDIO->DCTRL &= ~(1 << 9); +} + +/********************************************************************* + * @fn SDIO_SetSDIOReadWaitMode + * + * @brief Sets one of the two options of inserting read wait interval. + * + * @param SDIO_ReadWaitMode - SD I/O Read Wait operation mode. + * SDIO_ReadWaitMode_CLK - Read Wait control by stopping SDIOCLK + * SDIO_ReadWaitMode_DATA2 - Read Wait control using SDIO_DATA2 + * + * @return none + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + if(SDIO_ReadWaitMode) + SDIO->DCTRL |= (1 << 10); + else + SDIO->DCTRL &= ~(1 << 10); +} + +/********************************************************************* + * @fn SDIO_SetSDIOOperation + * + * @brief Enables or disables the SD I/O Mode Operation. + * + * @param NewState: ENABLE or DISABLE. + * + * @return none + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 11); + else + SDIO->DCTRL &= ~(1 << 11); +} + +/********************************************************************* + * @fn SDIO_SendSDIOSuspendCmd + * + * @brief Enables or disables the SD I/O Mode suspend command sending. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 11); + else + SDIO->CMD &= ~(1 << 11); +} + +/********************************************************************* + * @fn SDIO_CommandCompletionCmd + * + * @brief Enables or disables the command completion signal. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 12); + else + SDIO->CMD &= ~(1 << 12); +} + +/********************************************************************* + * @fn SDIO_CEATAITCmd + * + * @brief Enables or disables the CE-ATA interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 13); + else + SDIO->CMD &= ~(1 << 13); +} + +/********************************************************************* + * @fn SDIO_SendCEATACmd + * + * @brief Sends CE-ATA command (CMD61). + * + * @param NewState - ENABLE or DISABLE. + * + * @return RTC counter value + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 14); + else + SDIO->CMD &= ~(1 << 14); +} + +/********************************************************************* + * @fn SDIO_GetFlagStatus + * + * @brief Checks whether the specified SDIO flag is set or not. + * + * @param SDIO_FLAG - specifies the flag to check. + * SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed) + * SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed) + * SDIO_FLAG_CTIMEOUT - Command response timeout + * SDIO_FLAG_DTIMEOUT - Data timeout + * SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error + * SDIO_FLAG_RXOVERR - Received FIFO overrun error + * SDIO_FLAG_CMDREND - Command response received (CRC check passed) + * SDIO_FLAG_CMDSENT - Command sent (no response required) + * SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero) + * SDIO_FLAG_STBITERR - Start bit not detected on all data signals + * in wide bus mode. + * SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed) + * SDIO_FLAG_CMDACT - Command transfer in progress + * SDIO_FLAG_TXACT - Data transmit in progress + * SDIO_FLAG_RXACT - Data receive in progress + * SDIO_FLAG_TXFIFOHE - Transmit FIFO Half Empty + * SDIO_FLAG_RXFIFOHF - Receive FIFO Half Full + * SDIO_FLAG_TXFIFOF - Transmit FIFO full + * SDIO_FLAG_RXFIFOF - Receive FIFO full + * SDIO_FLAG_TXFIFOE - Transmit FIFO empty + * SDIO_FLAG_RXFIFOE - Receive FIFO empty + * SDIO_FLAG_TXDAVL - Data available in transmit FIFO + * SDIO_FLAG_RXDAVL - Data available in receive FIFO + * SDIO_FLAG_SDIOIT - SD I/O interrupt received + * SDIO_FLAG_CEATAEND - CE-ATA command completion signal received + * for CMD61 + * + * @return ITStatus - SET or RESET + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn SDIO_ClearFlag + * + * @brief Clears the SDIO's pending flags. + * + * @param SDIO_FLAG - specifies the flag to clear. + * SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed) + * SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed) + * SDIO_FLAG_CTIMEOUT - Command response timeout + * SDIO_FLAG_DTIMEOUT - Data timeout + * SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error + * SDIO_FLAG_RXOVERR - Received FIFO overrun error + * SDIO_FLAG_CMDREND - Command response received (CRC check passed) + * SDIO_FLAG_CMDSENT - Command sent (no response required) + * SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero) + * SDIO_FLAG_STBITERR - Start bit not detected on all data signals + * in wide bus mode + * SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed) + * SDIO_FLAG_SDIOIT - SD I/O interrupt received + * SDIO_FLAG_CEATAEND - CE-ATA command completion signal received for CMD61 + * + * @return none + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + SDIO->ICR = SDIO_FLAG; +} + +/********************************************************************* + * @fn SDIO_GetITStatus + * + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt + * SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt + * SDIO_IT_CTIMEOUT - Command response timeout interrupt + * SDIO_IT_DTIMEOUT - Data timeout interrupt + * SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt + * SDIO_IT_RXOVERR - Received FIFO overrun error interrupt + * SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt + * SDIO_IT_CMDSENT - Command sent (no response required) interrupt + * SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt + * SDIO_IT_STBITERR - Start bit not detected on all data signals in wide + * bus mode interrupt + * SDIO_IT_DBCKEND - Data block sent/received (CRC check passed) interrupt + * SDIO_IT_CMDACT - Command transfer in progress interrupt + * SDIO_IT_TXACT - Data transmit in progress interrupt + * SDIO_IT_RXACT - Data receive in progress interrupt + * SDIO_IT_TXFIFOHE - Transmit FIFO Half Empty interrupt + * SDIO_IT_RXFIFOHF - Receive FIFO Half Full interrupt + * SDIO_IT_TXFIFOF - Transmit FIFO full interrupt + * SDIO_IT_RXFIFOF - Receive FIFO full interrupt + * SDIO_IT_TXFIFOE - Transmit FIFO empty interrupt + * SDIO_IT_RXFIFOE - Receive FIFO empty interrupt + * SDIO_IT_TXDAVL - Data available in transmit FIFO interrupt + * SDIO_IT_RXDAVL - Data available in receive FIFO interrupt + * SDIO_IT_SDIOIT - SD I/O interrupt received interrupt + * SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 interrupt + * + * @return ITStatus:SET or RESET + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + if((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn SDIO_ClearITPendingBit + * + * @brief Clears the SDIO's interrupt pending bits. + * + * @param SDIO_IT - specifies the interrupt pending bit to clear. + * SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt + * SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt + * SDIO_IT_CTIMEOUT - Command response timeout interrupt + * SDIO_IT_DTIMEOUT - Data timeout interrupt + * SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt + * SDIO_IT_RXOVERR - Received FIFO overrun error interrupt + * SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt + * SDIO_IT_CMDSENT - Command sent (no response required) interrupt + * SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt + * SDIO_IT_STBITERR - Start bit not detected on all data signals in wide + * bus mode interrupt + * SDIO_IT_SDIOIT - SD I/O interrupt received interrupt + * SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 + * + * @return RTC counter value + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + SDIO->ICR = SDIO_IT; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_spi.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_spi.c index 6b1fc6b..7736ca3 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_spi.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_spi.c @@ -1,668 +1,668 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_spi.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the SPI firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_spi.h" -#include "ch32v30x_rcc.h" - -/* SPI SPE mask */ -#define CTLR1_SPE_Set ((uint16_t)0x0040) -#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) - -/* I2S I2SE mask */ -#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) -#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) - -/* SPI CRCNext mask */ -#define CTLR1_CRCNext_Set ((uint16_t)0x1000) - -/* SPI CRCEN mask */ -#define CTLR1_CRCEN_Set ((uint16_t)0x2000) -#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) - -/* SPI SSOE mask */ -#define CTLR2_SSOE_Set ((uint16_t)0x0004) -#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) - -/* SPI registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) - -/* SPI or I2S mode selection masks */ -#define SPI_Mode_Select ((uint16_t)0xF7FF) -#define I2S_Mode_Select ((uint16_t)0x0800) - -/* I2S clock source selection masks */ -#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) -#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) -#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) -#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) - -/********************************************************************* - * @fn SPI_I2S_DeInit - * - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values (Affects also the I2Ss). - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * - * @return none - */ -void SPI_I2S_DeInit(SPI_TypeDef *SPIx) -{ - if(SPIx == SPI1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if(SPIx == SPI2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else - { - if(SPIx == SPI3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - } -} - -/********************************************************************* - * @fn SPI_Init - * - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * - * @return none - */ -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - tmpreg = SPIx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - - SPIx->CTLR1 = tmpreg; - SPIx->I2SCFGR &= SPI_Mode_Select; - SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/********************************************************************* - * @fn I2S_Init - * - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * (configured in I2S mode). - * I2S_InitStruct - pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * - * @return none - */ -void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0; - RCC_ClocksTypeDef RCC_Clocks; - uint32_t sourceclock = 0; - - SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; - SPIx->I2SPR = 0x0002; - tmpreg = SPIx->I2SCFGR; - - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - else - { - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - packetlength = 1; - } - else - { - packetlength = 2; - } - - if(((uint32_t)SPIx) == SPI2_BASE) - { - tmp = I2S2_CLOCK_SRC; - } - else - { - tmp = I2S3_CLOCK_SRC; - } - - RCC_GetClocksFreq(&RCC_Clocks); - - sourceclock = RCC_Clocks.SYSCLK_Frequency; - - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - tmp = tmp / 10; - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - i2sodd = (uint16_t)(i2sodd << 8); - } - - if((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - i2sdiv = 2; - i2sodd = 0; - } - - SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - SPIx->I2SCFGR = tmpreg; -} - -/********************************************************************* - * @fn SPI_StructInit - * - * @brief Fills each SPI_InitStruct member with its default value. - * - * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) -{ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/********************************************************************* - * @fn I2S_StructInit - * - * @brief Fills each I2S_InitStruct member with its default value. - * - * @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct) -{ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/********************************************************************* - * @fn SPI_Cmd - * - * @brief Enables or disables the specified SPI peripheral. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_SPE_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_SPE_Reset; - } -} - -/********************************************************************* - * @fn I2S_Cmd - * - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; - } - else - { - SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; - } -} - -/********************************************************************* - * @fn SPI_I2S_ITConfig - * - * @brief Enables or disables the specified SPI/I2S interrupts. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_IT - specifies the SPI/I2S interrupt source to be - * enabled or disabled. - * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. - * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. - * SPI_I2S_IT_ERR - Error interrupt mask. - * NewState: ENABLE or DISABLE. - * @return none - */ -void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0; - - itpos = SPI_I2S_IT >> 4; - itmask = (uint16_t)1 << (uint16_t)itpos; - - if(NewState != DISABLE) - { - SPIx->CTLR2 |= itmask; - } - else - { - SPIx->CTLR2 &= (uint16_t)~itmask; - } -} - -/********************************************************************* - * @fn SPI_I2S_DMACmd - * - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to - * be enabled or disabled. - * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. - * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= SPI_I2S_DMAReq; - } - else - { - SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/********************************************************************* - * @fn SPI_I2S_SendData - * - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * Data - Data to be transmitted. - * - * @return none - */ -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) -{ - SPIx->DATAR = Data; -} - -/********************************************************************* - * @fn SPI_I2S_ReceiveData - * - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * Data - Data to be transmitted. - * - * @return SPIx->DATAR - The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) -{ - return SPIx->DATAR; -} - -/********************************************************************* - * @fn SPI_NSSInternalSoftwareConfig - * - * @brief Configures internally by software the NSS pin for the selected SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_NSSInternalSoft - - * SPI_NSSInternalSoft_Set - Set NSS pin internally. - * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. - * - * @return none - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) -{ - if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; - } - else - { - SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/********************************************************************* - * @fn SPI_SSOutputCmd - * - * @brief Enables or disables the SS output for the selected SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * NewState - new state of the SPIx SS output. - * - * @return none - */ -void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= CTLR2_SSOE_Set; - } - else - { - SPIx->CTLR2 &= CTLR2_SSOE_Reset; - } -} - -/********************************************************************* - * @fn SPI_DataSizeConfig - * - * @brief Configures the data size for the selected SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_DataSize - specifies the SPI data size. - * SPI_DataSize_16b - Set data frame format to 16bit. - * SPI_DataSize_8b - Set data frame format to 8bit. - * - * @return none - */ -void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) -{ - SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; - SPIx->CTLR1 |= SPI_DataSize; -} - -/********************************************************************* - * @fn SPI_TransmitCRC - * - * @brief Transmit the SPIx CRC value. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * - * @return none - */ -void SPI_TransmitCRC(SPI_TypeDef *SPIx) -{ - SPIx->CTLR1 |= CTLR1_CRCNext_Set; -} - -/********************************************************************* - * @fn SPI_CalculateCRC - * - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * NewState - new state of the SPIx CRC value calculation. - * - * @return none - */ -void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_CRCEN_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_CRCEN_Reset; - } -} - -/********************************************************************* - * @fn SPI_GetCRC - * - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_CRC - specifies the CRC register to be read. - * SPI_CRC_Tx - Selects Tx CRC register. - * SPI_CRC_Rx - Selects Rx CRC register. - * - * @return crcreg: The selected CRC register value. - */ -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - - if(SPI_CRC != SPI_CRC_Rx) - { - crcreg = SPIx->TCRCR; - } - else - { - crcreg = SPIx->RCRCR; - } - - return crcreg; -} - -/********************************************************************* - * @fn SPI_GetCRCPolynomial - * - * @brief Returns the CRC Polynomial register value for the specified SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * - * @return SPIx->CRCR - The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) -{ - return SPIx->CRCR; -} - -/********************************************************************* - * @fn SPI_BiDirectionalLineConfig - * - * @brief Selects the data transfer direction in bi-directional mode - * for the specified SPI. - * - * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. - * SPI_Direction - specifies the data transfer direction in - * bi-directional mode. - * SPI_Direction_Tx - Selects Tx transmission direction. - * SPI_Direction_Rx - Selects Rx receive direction. - * - * @return none - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) -{ - if(SPI_Direction == SPI_Direction_Tx) - { - SPIx->CTLR1 |= SPI_Direction_Tx; - } - else - { - SPIx->CTLR1 &= SPI_Direction_Rx; - } -} - -/********************************************************************* - * @fn SPI_I2S_GetFlagStatus - * - * @brief Checks whether the specified SPI/I2S flag is set or not. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. - * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. - * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. - * SPI_I2S_FLAG_BSY - Busy flag. - * SPI_I2S_FLAG_OVR - Overrun flag. - * SPI_FLAG_MODF - Mode Fault flag. - * SPI_FLAG_CRCERR - CRC Error flag. - * I2S_FLAG_UDR - Underrun Error flag. - * I2S_FLAG_CHSIDE - Channel Side flag. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearFlag - * - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_FLAG - specifies the SPI flag to clear. - * SPI_FLAG_CRCERR - CRC Error flag. - * Note- - * - OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). - * - UDR (UnderRun error) flag is cleared by a read operation to - * SPI_STATR register (SPI_I2S_GetFlagStatus()). - * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). - * @return FlagStatus: SET or RESET. - */ -void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; -} - -/********************************************************************* - * @fn SPI_I2S_GetITStatus - * - * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * - 2 or 3 in I2S mode. - * SPI_I2S_IT - specifies the SPI/I2S interrupt source to check.. - * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. - * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. - * SPI_I2S_IT_OVR - Overrun interrupt. - * SPI_IT_MODF - Mode Fault interrupt. - * SPI_IT_CRCERR - CRC Error interrupt. - * I2S_IT_UDR - Underrun Error interrupt. - * - * @return FlagStatus: SET or RESET. - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - itmask = SPI_I2S_IT >> 4; - itmask = 0x01 << itmask; - enablestatus = (SPIx->CTLR2 & itmask); - - if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearITPendingBit - * - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * - * @param SPIx - where x can be - * - 1, 2 or 3 in SPI mode. - * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. - * SPI_IT_CRCERR - CRC Error interrupt. - * Note- - * - OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). - * - UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_STATR register (SPI_I2S_GetITStatus()). - * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable - * the SPI). - * @return none - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - SPIx->STATR = (uint16_t)~itpos; -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_spi.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the SPI firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_spi.h" +#include "ch32v30x_rcc.h" + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if(SPIx == SPI2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if(SPIx == SPI3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->I2SCFGR &= SPI_Mode_Select; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn I2S_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * (configured in I2S mode). + * I2S_InitStruct - pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * + * @return none + */ +void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + tmpreg = SPIx->I2SCFGR; + + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + else + { + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + packetlength = 1; + } + else + { + packetlength = 2; + } + + if(((uint32_t)SPIx) == SPI2_BASE) + { + tmp = I2S2_CLOCK_SRC; + } + else + { + tmp = I2S3_CLOCK_SRC; + } + + RCC_GetClocksFreq(&RCC_Clocks); + + sourceclock = RCC_Clocks.SYSCLK_Frequency; + + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + tmp = tmp / 10; + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + i2sodd = (uint16_t)(i2sodd << 8); + } + + if((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + i2sdiv = 2; + i2sodd = 0; + } + + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + SPIx->I2SCFGR = tmpreg; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn I2S_StructInit + * + * @brief Fills each I2S_InitStruct member with its default value. + * + * @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct) +{ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn I2S_Cmd + * + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI/I2S interrupts. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState: ENABLE or DISABLE. + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg: The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI/I2S flag is set or not. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * I2S_FLAG_UDR - Underrun Error flag. + * I2S_FLAG_CHSIDE - Channel Side flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * Note- + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). + * @return FlagStatus: SET or RESET. + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * I2S_IT_UDR - Underrun Error interrupt. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * Note- + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable + * the SPI). + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_tim.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_tim.c index 7ca216e..728c0cc 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_tim.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_tim.c @@ -1,2368 +1,2368 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_tim.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the TIM firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_tim.h" -#include "ch32v30x_rcc.h" - -/* TIM registers bit mask */ -#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) -#define CHCTLR_Offset ((uint16_t)0x0018) -#define CCER_CCE_Set ((uint16_t)0x0001) -#define CCER_CCNE_Set ((uint16_t)0x0004) - -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/********************************************************************* - * @fn TIM_DeInit - * - * @brief Deinitializes the TIMx peripheral registers to their default - * reset values. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * - * @return none - */ -void TIM_DeInit(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if(TIMx == TIM8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); - } - else if(TIMx == TIM9) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); - } - else if(TIMx == TIM10) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); - } - else if(TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if(TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if(TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if(TIMx == TIM5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); - } - else if(TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if(TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } -} - -/********************************************************************* - * @fn TIM_TimeBaseInit - * - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef - * structure. - * - * @return none - */ -void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - tmpcr1 = TIMx->CTLR1; - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || - (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) - { - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if((TIMx != TIM6) && (TIMx != TIM7)) - { - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CTLR1 = tmpcr1; - TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) - { - TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; -} - -/********************************************************************* - * @fn TIM_OC1Init - * - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); - - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2Init - * - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3Init - * - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4Init - * - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) - { - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ICInit - * - * @brief IInitializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_PWMIConfig - * - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external - * PWM signal. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - - if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_BDTRConfig - * - * @brief Configures the: Break feature, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable). - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/********************************************************************* - * @fn TIM_TimeBaseStructInit - * - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * - * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. - * - * @return none - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/********************************************************************* - * @fn TIM_OCStructInit - * - * @brief Fills each TIM_OCInitStruct member with its default value. - * - * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/********************************************************************* - * @fn TIM_ICStructInit - * - * @brief Fills each TIM_ICInitStruct member with its default value. - * - * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/********************************************************************* - * @fn TIM_BDTRStructInit - * - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * - * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/********************************************************************* - * @fn TIM_Cmd - * - * @brief Enables or disables the specified TIM peripheral. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_CEN; - } - else - { - TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); - } -} - -/********************************************************************* - * @fn TIM_CtrlPWMOutputs - * - * @brief Enables or disables the TIM peripheral Main Outputs. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->BDTR |= TIM_MOE; - } - else - { - TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); - } -} - -/********************************************************************* - * @fn TIM_ITConfig - * - * @brief Enables or disables the specified TIM interrupts. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->DMAINTENR |= TIM_IT; - } - else - { - TIMx->DMAINTENR &= (uint16_t)~TIM_IT; - } -} - -void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) -{ - TIMx->SWEVGR = TIM_EventSource; -} - -/********************************************************************* - * @fn TIM_DMAConfig - * - * @brief Configures the TIMx's DMA interface. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_DMABase: DMA Base address. - * TIM_DMABase_CR. - * TIM_DMABase_CR2. - * TIM_DMABase_SMCR. - * TIM_DMABase_DIER. - * TIM1_DMABase_SR. - * TIM_DMABase_EGR. - * TIM_DMABase_CCMR1. - * TIM_DMABase_CCMR2. - * TIM_DMABase_CCER. - * TIM_DMABase_CNT. - * TIM_DMABase_PSC. - * TIM_DMABase_CCR1. - * TIM_DMABase_CCR2. - * TIM_DMABase_CCR3. - * TIM_DMABase_CCR4. - * TIM_DMABase_BDTR. - * TIM_DMABase_DCR. - * TIM_DMABurstLength - DMA Burst length. - * TIM_DMABurstLength_1Transfer. - * TIM_DMABurstLength_18Transfers. - * - * @return none - */ -void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; -} - -/********************************************************************* - * @fn TIM_DMACmd - * - * @brief Enables or disables the TIMx's DMA Requests. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_DMASource - specifies the DMA Request sources. - * TIM_DMA_Update - TIM update Interrupt source. - * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. - * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. - * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. - * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. - * TIM_DMA_COM - TIM Commutation DMA source. - * TIM_DMA_Trigger - TIM Trigger DMA source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->DMAINTENR |= TIM_DMASource; - } - else - { - TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; - } -} - -/********************************************************************* - * @fn TIM_InternalClockConfig - * - * @brief Configures the TIMx internal Clock. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * - * @return none - */ -void TIM_InternalClockConfig(TIM_TypeDef *TIMx) -{ - TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); -} - -/********************************************************************* - * @fn TIM_ITRxExternalClockConfig - * - * @brief Configures the TIMx Internal Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_InputTriggerSource: Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * - * @return none - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_TIxExternalClockConfig - * - * @brief Configures the TIMx Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_TIxExternalCLKSource - Trigger source. - * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. - * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. - * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. - * TIM_ICPolarity - specifies the TIx Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_DMA_COM - TIM Commutation DMA source. - * TIM_DMA_Trigger - TIM Trigger DMA source. - * ICFilter - specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_ETRClockMode1Config - * - * @brief Configures the External clock Mode1. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_SlaveMode_External1; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_TS_ETRF; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_ETRClockMode2Config - * - * @brief Configures the External clock Mode2. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - TIMx->SMCFGR |= TIM_ECE; -} - -/********************************************************************* - * @fn TIM_ETRConfig - * - * @brief Configures the TIMx External Trigger (ETR). - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= SMCFGR_ETR_Mask; - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_PrescalerConfig - * - * @brief Configures the TIMx Prescaler. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * Prescaler - specifies the Prescaler Register value. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. - * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. - * - * @return none - */ -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - TIMx->PSC = Prescaler; - TIMx->SWEVGR = TIM_PSCReloadMode; -} - -/********************************************************************* - * @fn TIM_CounterModeConfig - * - * @brief Specifies the TIMx Counter Mode to be used. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_CounterMode - specifies the Counter Mode to be used. - * TIM_CounterMode_Up - TIM Up Counting Mode. - * TIM_CounterMode_Down - TIM Down Counting Mode. - * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. - * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. - * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. - * - * @return none - */ -void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - tmpcr1 = TIMx->CTLR1; - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= TIM_CounterMode; - TIMx->CTLR1 = tmpcr1; -} - -/********************************************************************* - * @fn TIM_SelectInputTrigger - * - * @brief Selects the Input Trigger source. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_InputTriggerSource - The Input Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * TIM_TS_TI1F_ED - TI1 Edge Detector. - * TIM_TS_TI1FP1 - Filtered Timer Input 1. - * TIM_TS_TI2FP2 - Filtered Timer Input 2. - * TIM_TS_ETRF - External Trigger input. - * - * @return none - */ -void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_InputTriggerSource; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_EncoderInterfaceConfig - * - * @brief Configures the TIMx Encoder Interface. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_EncoderMode - specifies the TIMx Encoder Mode. - * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending - * on TI2FP2 level. - * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending - * on TI1FP1 level. - * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and - * TI2FP2 edges depending. - * TIM_IC1Polarity - specifies the IC1 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TTIM_ICPolarity_Rising - IC Rising edge. - * TIM_IC2Polarity - specifies the IC2 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TIM_ICPolarity_Rising - IC Rising edge. - * - * @return none - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_EncoderMode; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); - tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; - tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - TIMx->SMCFGR = tmpsmcr; - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ForcedOC1Config - * - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC1REF. - * TIM_ForcedAction_InActive - Force inactive level on OC1REF. - * - * @return none - */ -void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); - tmpccmr1 |= TIM_ForcedAction; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC2Config - * - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC2REF. - * TIM_ForcedAction_InActive - Force inactive level on OC2REF. - * - * @return none - */ -void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC3Config - * - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC3REF. - * TIM_ForcedAction_InActive - Force inactive level on OC3REF. - * - * @return none - */ -void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); - tmpccmr2 |= TIM_ForcedAction; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ForcedOC4Config - * - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC4REF. - * TIM_ForcedAction_InActive - Force inactive level on OC4REF. - * - * @return none - */ -void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ARRPreloadConfig - * - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_ARPE; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); - } -} - -/********************************************************************* - * @fn TIM_SelectCOM - * - * @brief Selects the TIM peripheral Commutation event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCUS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); - } -} - -/********************************************************************* - * @fn TIM_SelectCCDMA - * - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCDS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); - } -} - -/********************************************************************* - * @fn TIM_CCPreloadControl - * - * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. - * reset values (Affects also the I2Ss). - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCPC; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); - } -} - -/********************************************************************* - * @fn TIM_OC1PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); - tmpccmr1 |= TIM_OCPreload; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC2PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC3PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); - tmpccmr2 |= TIM_OCPreload; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC4PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC1FastConfig - * - * @brief Configures the TIMx Output Compare 1 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); - tmpccmr1 |= TIM_OCFast; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC2FastConfig - * - * @brief Configures the TIMx Output Compare 2 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC3FastConfig - * - * @brief Configures the TIMx Output Compare 3 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); - tmpccmr2 |= TIM_OCFast; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC4FastConfig - * - * @brief Configures the TIMx Output Compare 4 Fast feature. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC1Ref - * - * @brief Clears or safeguards the OCREF1 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); - tmpccmr1 |= TIM_OCClear; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC2Ref - * - * @brief Clears or safeguards the OCREF2 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC3Ref - * - * @brief Clears or safeguards the OCREF3 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); - tmpccmr2 |= TIM_OCClear; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC4Ref - * - * @brief Clears or safeguards the OCREF4 signal on an external event. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC1PolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC1 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); - tmpccer |= TIM_OCPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC1NPolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); - tmpccer |= TIM_OCNPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2PolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC2 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2NPolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3PolarityConfig - * - * @brief Configures the TIMx Channel 3 polarity. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3NPolarityConfig - * - * @brief Configures the TIMx Channel 3N polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC2N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4PolarityConfig - * - * @brief Configures the TIMx Channel 4 polarity. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_CCxCmd - * - * @brief Enables or disables the TIM Capture Compare Channel x. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_CCx - specifies the TIM Channel CCxE bit new state. - * TIM_CCx_Enable. - * TIM_CCx_Disable. - * - * @return none - */ -void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - tmp = CCER_CCE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_CCxNCmd - * - * @brief Enables or disables the TIM Capture Compare Channel xN. - * - * @param TIMx - where x can be 1 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. - * TIM_CCxN_Enable. - * TIM_CCxN_Disable. - * - * @return none - */ -void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - tmp = CCER_CCNE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_SelectOCxM - * - * @brief Selects the TIM Output Compare Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_OCMode - specifies the TIM Output Compare Mode. - * TIM_OCMode_Timing. - * TIM_OCMode_Active. - * TIM_OCMode_Toggle. - * TIM_OCMode_PWM1. - * TIM_OCMode_PWM2. - * TIM_ForcedAction_Active. - * TIM_ForcedAction_InActive. - * - * @return none - */ -void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - tmp = (uint32_t)TIMx; - tmp += CHCTLR_Offset; - tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp1; - - if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel >> 1); - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); - *(__IO uint32_t *)tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); - *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/********************************************************************* - * @fn TIM_UpdateDisableConfig - * - * @brief Enables or Disables the TIMx Update event. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_UDIS; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); - } -} - -/********************************************************************* - * @fn TIM_UpdateRequestConfig - * - * @brief Configures the TIMx Update Request Interrupt source. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_UpdateSource - specifies the Update source. - * TIM_UpdateSource_Regular. - * TIM_UpdateSource_Global. - * - * @return none - */ -void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) -{ - if(TIM_UpdateSource != TIM_UpdateSource_Global) - { - TIMx->CTLR1 |= TIM_URS; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); - } -} - -/********************************************************************* - * @fn TIM_SelectHallSensor - * - * @brief Enables or disables the TIMx's Hall sensor interface. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_TI1S; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); - } -} - -/********************************************************************* - * @fn TIM_SelectOnePulseMode - * - * @brief Selects the TIMx's One Pulse Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OPMode - specifies the OPM Mode to be used. - * TIM_OPMode_Single. - * TIM_OPMode_Repetitive. - * - * @return none - */ -void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); - TIMx->CTLR1 |= TIM_OPMode; -} - -/********************************************************************* - * @fn TIM_SelectOutputTrigger - * - * @brief Selects the TIMx Trigger Output Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_TRGOSource - specifies the Trigger Output source. - * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is - * used as the trigger output (TRGO). - * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the - * trigger output (TRGO). - * TIM_TRGOSource_Update - The update event is selected as the - * trigger output (TRGO). - * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse - * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). - * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). - * - * @return none - */ -void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) -{ - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); - TIMx->CTLR2 |= TIM_TRGOSource; -} - -/********************************************************************* - * @fn TIM_SelectSlaveMode - * - * @brief Selects the TIMx Slave Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_SlaveMode - specifies the Timer Slave Mode. - * TIM_SlaveMode_Reset - Rising edge of the selected trigger - * signal (TRGI) re-initializes. - * TIM_SlaveMode_Gated - The counter clock is enabled when the - * trigger signal (TRGI) is high. - * TIM_SlaveMode_Trigger - The counter starts at a rising edge - * of the trigger TRGI. - * TIM_SlaveMode_External1 - Rising edges of the selected trigger - * (TRGI) clock the counter. - * - * @return none - */ -void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) -{ - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); - TIMx->SMCFGR |= TIM_SlaveMode; -} - -/********************************************************************* - * @fn TIM_SelectMasterSlaveMode - * - * @brief Sets or Resets the TIMx Master/Slave Mode. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. - * TIM_MasterSlaveMode_Enable - synchronization between the current - * timer and its slaves (through TRGO). - * TIM_MasterSlaveMode_Disable - No action. - * - * @return none - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) -{ - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); - TIMx->SMCFGR |= TIM_MasterSlaveMode; -} - -/********************************************************************* - * @fn TIM_SetCounter - * - * @brief Sets the TIMx Counter Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Counter - specifies the Counter register new value. - * - * @return none - */ -void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) -{ - TIMx->CNT = Counter; -} - -/********************************************************************* - * @fn TIM_SetAutoreload - * - * @brief Sets the TIMx Autoreload Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Autoreload - specifies the Autoreload register new value. - * - * @return none - */ -void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) -{ - TIMx->ATRLR = Autoreload; -} - -/********************************************************************* - * @fn TIM_SetCompare1 - * - * @brief Sets the TIMx Capture Compare1 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) -{ - TIMx->CH1CVR = Compare1; -} - -/********************************************************************* - * @fn TIM_SetCompare2 - * - * @brief Sets the TIMx Capture Compare2 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) -{ - TIMx->CH2CVR = Compare2; -} - -/********************************************************************* - * @fn TIM_SetCompare3 - * - * @brief Sets the TIMx Capture Compare3 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) -{ - TIMx->CH3CVR = Compare3; -} - -/********************************************************************* - * @fn TIM_SetCompare4 - * - * @brief Sets the TIMx Capture Compare4 Register value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) -{ - TIMx->CH4CVR = Compare4; -} - -/********************************************************************* - * @fn TIM_SetIC1Prescaler - * - * @brief Sets the TIMx Input Capture 1 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); - TIMx->CHCTLR1 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC2Prescaler - * - * @brief Sets the TIMx Input Capture 2 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); - TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetIC3Prescaler - * - * @brief Sets the TIMx Input Capture 3 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); - TIMx->CHCTLR2 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC4Prescaler - * - * @brief Sets the TIMx Input Capture 4 prescaler. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); - TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetClockDivision - * - * @brief Sets the TIMx Clock Division value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_CKD - specifies the clock division value. - * TIM_CKD_DIV1 - TDTS = Tck_tim. - * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. - * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. - * - * @return none - */ -void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); - TIMx->CTLR1 |= TIM_CKD; -} - -/********************************************************************* - * @fn TIM_GetCapture1 - * - * @brief Gets the TIMx Input Capture 1 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH1CVR - Capture Compare 1 Register value. - */ -uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) -{ - return TIMx->CH1CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture2 - * - * @brief Gets the TIMx Input Capture 2 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH2CVR - Capture Compare 2 Register value. - */ -uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) -{ - return TIMx->CH2CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture3 - * - * @brief Gets the TIMx Input Capture 3 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH3CVR - Capture Compare 3 Register value. - */ -uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) -{ - return TIMx->CH3CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture4 - * - * @brief Gets the TIMx Input Capture 4 value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CH4CVR - Capture Compare 4 Register value. - */ -uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) -{ - return TIMx->CH4CVR; -} - -/********************************************************************* - * @fn TIM_GetCounter - * - * @brief Gets the TIMx Counter value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->CNT - Counter Register value. - */ -uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) -{ - return TIMx->CNT; -} - -/********************************************************************* - * @fn TIM_GetPrescaler - * - * @brief Gets the TIMx Prescaler value. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * - * @return TIMx->PSC - Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) -{ - return TIMx->PSC; -} - -/********************************************************************* - * @fn TIM_GetFlagStatus - * - * @brief Checks whether the specified TIM flag is set or not. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return none - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - - if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearFlag - * - * @brief Clears the TIMx's pending flags. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return none - */ -void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - TIMx->INTFR = (uint16_t)~TIM_FLAG; -} - -/********************************************************************* - * @fn TIM_GetITStatus - * - * @brief Checks whether the TIM interrupt has occurred or not. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - - itstatus = TIMx->INTFR & TIM_IT; - - itenable = TIMx->DMAINTENR & TIM_IT; - if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearITPendingBit - * - * @brief Clears the TIMx's interrupt pending bits. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - TIMx->INTFR = (uint16_t)~TIM_IT; -} - -/********************************************************************* - * @fn TI1_Config - * - * @brief Configure the TI1 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || - (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI2_Config - * - * @brief Configure the TI2 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || - (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI3_Config - * - * @brief Configure the TI3 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || - (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI4_Config - * - * @brief Configure the TI4 as Input. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || - (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC4NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_tim.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file provides all the TIM firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_tim.h" +#include "ch32v30x_rcc.h" + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if(TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if(TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if(TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if(TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if(TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if(TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if(TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CTLR1 = tmpcr1; + TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1/8/9/10 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMABase: DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values (Affects also the I2Ss). + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 4 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) +{ + TIMx->CNT = Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) +{ + TIMx->ATRLR = Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) +{ + TIMx->CH1CVR = Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) +{ + TIMx->CH2CVR = Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) +{ + TIMx->CH3CVR = Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) +{ + TIMx->CH4CVR = Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture3 + * + * @brief Gets the TIMx Input Capture 3 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH3CVR - Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_usart.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_usart.c index 4ac7cf6..7127541 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_usart.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_usart.c @@ -1,830 +1,759 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_usart.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the USART firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_usart.h" -#include "ch32v30x_rcc.h" - -/* USART_Private_Defines */ -#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ -#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ - -#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ - -#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ -#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ -#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ -#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ - -#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ -#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ - -#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ -#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ -#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ - -#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ -#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ - -#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ -#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ - -#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ -#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ - -#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ -#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ - -#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ -#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ -#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ -#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ -#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ - -/* USART OverSampling-8 Mask */ -#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ -#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ - -/* USART One Bit Sampling Mask */ -#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ -#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ - -/********************************************************************* - * @fn USART_DeInit - * - * @brief Deinitializes the USARTx peripheral registers to their default - * reset values. - * - * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. - * - * @return none - */ -void USART_DeInit(USART_TypeDef *USARTx) -{ - if(USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if(USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if(USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if(USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else if(USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - else if(USARTx == UART6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, DISABLE); - } - else if(USARTx == UART7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); - } - else if(USARTx == UART8) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE); - } -} - -/********************************************************************* - * @fn USART_Init - * - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct. - * - * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. - * USART_InitStruct - pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified - * USART peripheral. - * - * @return none - */ -void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - uint32_t usartxbase = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - - if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - } - - usartxbase = (uint32_t)USARTx; - tmpreg = USARTx->CTLR2; - tmpreg &= CTLR2_STOP_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - USARTx->CTLR2 = (uint16_t)tmpreg; - tmpreg = USARTx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - USARTx->CTLR1 = (uint16_t)tmpreg; - - tmpreg = USARTx->CTLR3; - tmpreg &= CTLR3_CLEAR_Mask; - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - USARTx->CTLR3 = (uint16_t)tmpreg; - - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if(usartxbase == USART1_BASE) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) - { - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else - { - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - USARTx->BRR = (uint16_t)tmpreg; -} - -/********************************************************************* - * @fn USART_StructInit - * - * @brief Fills each USART_InitStruct member with its default value. - * - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void USART_StructInit(USART_InitTypeDef *USART_InitStruct) -{ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/********************************************************************* - * @fn USART_ClockInit - * - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * - * @return none - */ -void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - - tmpreg = USARTx->CTLR2; - tmpreg &= CTLR2_CLOCK_CLEAR_Mask; - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - USARTx->CTLR2 = (uint16_t)tmpreg; -} - -/********************************************************************* - * @fn USART_ClockStructInit - * - * @brief Fills each USART_ClockStructInit member with its default value. - * - * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * - * @return none - */ -void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/********************************************************************* - * @fn USART_Cmd - * - * @brief Enables or disables the specified USART peripheral. - * reset values (Affects also the I2Ss). - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_UE_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_UE_Reset; - } -} - -/********************************************************************* - * @fn USART_ITConfig - * - * @brief Enables or disables the specified USART interrupts. - * reset values (Affects also the I2Ss). - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_IT - specifies the USART interrupt sources to be enabled or disabled. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Transmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_PE - Parity Error interrupt. - * USART_IT_ERR - Error interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - - usartxbase = (uint32_t)USARTx; - usartreg = (((uint8_t)USART_IT) >> 0x05); - itpos = USART_IT & IT_Mask; - itmask = (((uint32_t)0x01) << itpos); - - if(usartreg == 0x01) - { - usartxbase += 0x0C; - } - else if(usartreg == 0x02) - { - usartxbase += 0x10; - } - else - { - usartxbase += 0x14; - } - - if(NewState != DISABLE) - { - *(__IO uint32_t *)usartxbase |= itmask; - } - else - { - *(__IO uint32_t *)usartxbase &= ~itmask; - } -} - -/********************************************************************* - * @fn USART_DMACmd - * - * @brief Enables or disables the USART DMA interface. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_DMAReq - specifies the DMA request. - * USART_DMAReq_Tx - USART DMA transmit request. - * USART_DMAReq_Rx - USART DMA receive request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= USART_DMAReq; - } - else - { - USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; - } -} - -/********************************************************************* - * @fn USART_SetAddress - * - * @brief Sets the address of the USART node. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_Address - Indicates the address of the USART node. - * - * @return none - */ -void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) -{ - USARTx->CTLR2 &= CTLR2_Address_Mask; - USARTx->CTLR2 |= USART_Address; -} - -/********************************************************************* - * @fn USART_WakeUpConfig - * - * @brief Selects the USART WakeUp method. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_WakeUp - specifies the USART wakeup method. - * USART_WakeUp_IdleLine - WakeUp by an idle line detection. - * USART_WakeUp_AddressMark - WakeUp by an address mark. - * - * @return none - */ -void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) -{ - USARTx->CTLR1 &= CTLR1_WAKE_Mask; - USARTx->CTLR1 |= USART_WakeUp; -} - -/********************************************************************* - * @fn USART_ReceiverWakeUpCmd - * - * @brief Determines if the USART is in mute mode or not. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_RWU_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_RWU_Reset; - } -} - -/********************************************************************* - * @fn USART_LINBreakDetectLengthConfig - * - * @brief Sets the USART LIN Break detection length. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_LINBreakDetectLength - specifies the LIN break detection length. - * USART_LINBreakDetectLength_10b - 10-bit break detection. - * USART_LINBreakDetectLength_11b - 11-bit break detection. - * - * @return none - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) -{ - USARTx->CTLR2 &= CTLR2_LBDL_Mask; - USARTx->CTLR2 |= USART_LINBreakDetectLength; -} - -/********************************************************************* - * @fn USART_LINCmd - * - * @brief Enables or disables the USART LIN mode. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR2 |= CTLR2_LINEN_Set; - } - else - { - USARTx->CTLR2 &= CTLR2_LINEN_Reset; - } -} - -/********************************************************************* - * @fn USART_SendData - * - * @brief Transmits single data through the USARTx peripheral. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * Data - the data to transmit. - * - * @return none - */ -void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) -{ - USARTx->DATAR = (Data & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_ReceiveData - * - * @brief Returns the most recent received data by the USARTx peripheral. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * - * @return The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef *USARTx) -{ - return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_SendBreak - * - * @brief Transmits break characters. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * - * @return none - */ -void USART_SendBreak(USART_TypeDef *USARTx) -{ - USARTx->CTLR1 |= CTLR1_SBK_Set; -} - -/********************************************************************* - * @fn USART_SetGuardTime - * - * @brief Sets the specified USART guard time. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_GuardTime - specifies the guard time. - * - * @return none - */ -void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) -{ - USARTx->GPR &= GPR_LSB_Mask; - USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/********************************************************************* - * @fn USART_SetPrescaler - * - * @brief Sets the system clock prescaler. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_Prescaler - specifies the prescaler clock. - * - * @return none - */ -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) -{ - USARTx->GPR &= GPR_MSB_Mask; - USARTx->GPR |= USART_Prescaler; -} - -/********************************************************************* - * @fn USART_SmartCardCmd - * - * @brief Enables or disables the USART Smart Card mode. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_SCEN_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_SCEN_Reset; - } -} - -/********************************************************************* - * @fn USART_SmartCardNACKCmd - * - * @brief Enables or disables NACK transmission. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_NACK_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_NACK_Reset; - } -} - -/********************************************************************* - * @fn USART_HalfDuplexCmd - * - * @brief Enables or disables the USART Half Duplex communication. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_HDSEL_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_HDSEL_Reset; - } -} - -/********************************************************************* - * @fn USART_OverSampling8Cmd - * - * @brief Enables or disables the USART's 8x oversampling mode. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * Note- - * This function has to be called before calling USART_Init() - * function in order to have correct baudrate Divider value. - * @return none - */ -void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_OVER8_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_OVER8_Reset; - } -} - -/********************************************************************* - * @fn USART_OneBitMethodCmd - * - * @brief Enables or disables the USART's one bit sampling method. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_ONEBITE_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_ONEBITE_Reset; - } -} - -/********************************************************************* - * @fn USART_IrDAConfig - * - * @brief Configures the USART's IrDA interface. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_IrDAMode - specifies the IrDA mode. - * USART_IrDAMode_LowPower. - * USART_IrDAMode_Normal. - * - * @return none - */ -void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) -{ - USARTx->CTLR3 &= CTLR3_IRLP_Mask; - USARTx->CTLR3 |= USART_IrDAMode; -} - -/********************************************************************* - * @fn USART_IrDACmd - * - * @brief Enables or disables the USART's IrDA interface. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_IREN_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_IREN_Reset; - } -} - -/********************************************************************* - * @fn USART_GetFlagStatus - * - * @brief Checks whether the specified USART flag is set or not. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_FLAG - specifies the flag to check. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TXE - Transmit data register empty flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * USART_FLAG_IDLE - Idle Line detection flag. - * USART_FLAG_ORE - OverRun Error flag. - * USART_FLAG_NE - Noise Error flag. - * USART_FLAG_FE - Framing Error flag. - * USART_FLAG_PE - Parity Error flag. - * - * @return bitstatus: SET or RESET - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearFlag - * - * @brief Clears the USARTx's pending flags. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_FLAG - specifies the flag to clear. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * Note- - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DATAR register (USART_ReceiveData()). - * - RXNE flag can be also cleared by a read to the USART_DATAR register - * (USART_ReceiveData()). - * - TC flag can be also cleared by software sequence: a read operation to - * USART_STATR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DATAR register (USART_SendData()). - * - TXE flag is cleared only by a write to the USART_DATAR register - * (USART_SendData()). - * @return none - */ -void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - - USARTx->STATR = (uint16_t)~USART_FLAG; -} - -/********************************************************************* - * @fn USART_GetITStatus - * - * @brief Checks whether the specified USART interrupt has occurred or not. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_IT - specifies the USART interrupt source to check. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Tansmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. - * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. - * USART_IT_NE - Noise Error interrupt. - * USART_IT_FE - Framing Error interrupt. - * USART_IT_PE - Parity Error interrupt. - * - * @return bitstatus: SET or RESET. - */ -ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - - usartreg = (((uint8_t)USART_IT) >> 0x05); - itmask = USART_IT & IT_Mask; - itmask = (uint32_t)0x01 << itmask; - - if(usartreg == 0x01) - { - itmask &= USARTx->CTLR1; - } - else if(usartreg == 0x02) - { - itmask &= USARTx->CTLR2; - } - else - { - itmask &= USARTx->CTLR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->STATR; - - if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearITPendingBit - * - * @brief Clears the USARTx's interrupt pending bits. - * - * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. - * USART_IT - specifies the interrupt pending bit to clear. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * Note- - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_STATR register - * (USART_GetITStatus()) followed by a read operation to USART_DATAR register - * (USART_ReceiveData()). - * - RXNE pending bit can be also cleared by a read to the USART_DATAR register - * (USART_ReceiveData()). - * - TC pending bit can be also cleared by software sequence: a read - * operation to USART_STATR register (USART_GetITStatus()) followed by a write - * operation to USART_DATAR register (USART_SendData()). - * - TXE pending bit is cleared only by a write to the USART_DATAR register - * (USART_SendData()). - * @return none - */ -void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->STATR = (uint16_t)~itmask; -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_usart.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file provides all the USART firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_usart.h" +#include "ch32v30x_rcc.h" + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if(USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if(USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if(USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else if(USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + else if(USARTx == UART6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, DISABLE); + } + else if(USARTx == UART7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); + } + else if(USARTx == UART8) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE); + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + tmpreg = (integerdivider / 100) << 4; + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return bitstatus: SET or RESET + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DATAR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_STATR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DATAR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return bitstatus: SET or RESET. + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_STATR register + * (USART_GetITStatus()) followed by a read operation to USART_DATAR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_STATR register (USART_GetITStatus()) followed by a write + * operation to USART_DATAR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_wwdg.c b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_wwdg.c index e027893..89d1702 100644 --- a/system/CH32V30x/SRC/Peripheral/src/ch32v30x_wwdg.c +++ b/system/CH32V30x/SRC/Peripheral/src/ch32v30x_wwdg.c @@ -1,141 +1,141 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_wwdg.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the WWDG firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_wwdg.h" -#include "ch32v30x_rcc.h" - -/* CTLR register bit mask */ -#define CTLR_WDGA_Set ((uint32_t)0x00000080) - -/* CFGR register bit mask */ -#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) -#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) -#define BIT_Mask ((uint8_t)0x7F) - -/********************************************************************* - * @fn WWDG_DeInit - * - * @brief Deinitializes the WWDG peripheral registers to their default reset values - * - * @return none - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/********************************************************************* - * @fn WWDG_SetPrescaler - * - * @brief Sets the WWDG Prescaler - * - * @param WWDG_Prescaler - specifies the WWDG Prescaler - * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 - * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 - * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 - * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 - * - * @return none - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; - tmpreg |= WWDG_Prescaler; - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_SetWindowValue - * - * @brief Sets the WWDG window value - * - * @param WindowValue - specifies the window value to be compared to the - * downcounter,which must be lower than 0x80 - * - * @return none - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - tmpreg = WWDG->CFGR & CFGR_W_Mask; - - tmpreg |= WindowValue & (uint32_t)BIT_Mask; - - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_EnableIT - * - * @brief Enables the WWDG Early Wakeup interrupt(EWI) - * - * @return none - */ -void WWDG_EnableIT(void) -{ - WWDG->CFGR |= (1 << 9); -} - -/********************************************************************* - * @fn WWDG_SetCounter - * - * @brief Sets the WWDG counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * - * @return none - */ -void WWDG_SetCounter(uint8_t Counter) -{ - WWDG->CTLR = Counter & BIT_Mask; -} - -/********************************************************************* - * @fn WWDG_Enable - * - * @brief Enables WWDG and load the counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * @return none - */ -void WWDG_Enable(uint8_t Counter) -{ - WWDG->CTLR = CTLR_WDGA_Set | Counter; -} - -/********************************************************************* - * @fn WWDG_GetFlagStatus - * - * @brief Checks whether the Early Wakeup interrupt flag is set or not - * - * @return The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - return (FlagStatus)(WWDG->STATR); -} - -/********************************************************************* - * @fn WWDG_ClearFlag - * - * @brief Clears Early Wakeup interrupt flag - * - * @return none - */ -void WWDG_ClearFlag(void) -{ - WWDG->STATR = (uint32_t)RESET; -} +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_wwdg.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the WWDG firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_wwdg.h" +#include "ch32v30x_rcc.h" + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/system/CH32V30x/SRC/Startup/startup_ch32v30x_D8.S b/system/CH32V30x/SRC/Startup/startup_ch32v30x_D8.S index 72b0209..76bf97c 100644 --- a/system/CH32V30x/SRC/Startup/startup_ch32v30x_D8.S +++ b/system/CH32V30x/SRC/Startup/startup_ch32v30x_D8.S @@ -1,8 +1,8 @@ /********************************** (C) COPYRIGHT ******************************* * File Name : startup_ch32v30x_D8.s * Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 +* Version : V1.0.1 +* Date : 2024/03/06 * Description : CH32V303x vector table for eclipse toolchain. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -15,19 +15,7 @@ .align 1 _start: j handle_reset - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00100073 + .section .vector,"ax",@progbits .align 1 _vector_base: @@ -97,7 +85,7 @@ _vector_base: .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word RNG_IRQHandler /* RNG */ - .word FSMC_IRQHandler /* FSMC */ + .word 0 .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ @@ -116,7 +104,7 @@ _vector_base: .word 0 .word 0 .word 0 - .word OTG_FS_IRQHandler /* OTGFS */ + .word USBFS_IRQHandler /* USBFS */ .word 0 .word 0 .word 0 @@ -139,7 +127,6 @@ _vector_base: .word DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ .option rvc; - .section .text.vector_handler, "ax", @progbits .weak NMI_Handler /* NMI */ .weak HardFault_Handler /* Hard Fault */ @@ -195,7 +182,6 @@ _vector_base: .weak TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ .weak TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .weak RNG_IRQHandler /* RNG */ - .weak FSMC_IRQHandler /* FSMC */ .weak SDIO_IRQHandler /* SDIO */ .weak TIM5_IRQHandler /* TIM5 */ .weak SPI3_IRQHandler /* SPI3 */ @@ -208,7 +194,7 @@ _vector_base: .weak DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ .weak DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ .weak DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ - .weak OTG_FS_IRQHandler /* OTGFS */ + .weak USBFS_IRQHandler /* USBFS */ .weak UART6_IRQHandler /* UART6 */ .weak UART7_IRQHandler /* UART7 */ .weak UART8_IRQHandler /* UART8 */ @@ -227,92 +213,92 @@ _vector_base: .weak DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */ .weak DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ -NMI_Handler: 1: j 1b -HardFault_Handler: 1: j 1b -Ecall_M_Mode_Handler: 1: j 1b -Ecall_U_Mode_Handler: 1: j 1b -Break_Point_Handler: 1: j 1b -SysTick_Handler: 1: j 1b -SW_Handler: 1: j 1b -WWDG_IRQHandler: 1: j 1b -PVD_IRQHandler: 1: j 1b -TAMPER_IRQHandler: 1: j 1b -RTC_IRQHandler: 1: j 1b -FLASH_IRQHandler: 1: j 1b -RCC_IRQHandler: 1: j 1b -EXTI0_IRQHandler: 1: j 1b -EXTI1_IRQHandler: 1: j 1b -EXTI2_IRQHandler: 1: j 1b -EXTI3_IRQHandler: 1: j 1b -EXTI4_IRQHandler: 1: j 1b -DMA1_Channel1_IRQHandler: 1: j 1b -DMA1_Channel2_IRQHandler: 1: j 1b -DMA1_Channel3_IRQHandler: 1: j 1b -DMA1_Channel4_IRQHandler: 1: j 1b -DMA1_Channel5_IRQHandler: 1: j 1b -DMA1_Channel6_IRQHandler: 1: j 1b -DMA1_Channel7_IRQHandler: 1: j 1b -ADC1_2_IRQHandler: 1: j 1b -USB_HP_CAN1_TX_IRQHandler: 1: j 1b -USB_LP_CAN1_RX0_IRQHandler: 1: j 1b -CAN1_RX1_IRQHandler: 1: j 1b -CAN1_SCE_IRQHandler: 1: j 1b -EXTI9_5_IRQHandler: 1: j 1b -TIM1_BRK_IRQHandler: 1: j 1b -TIM1_UP_IRQHandler: 1: j 1b -TIM1_TRG_COM_IRQHandler: 1: j 1b -TIM1_CC_IRQHandler: 1: j 1b -TIM2_IRQHandler: 1: j 1b -TIM3_IRQHandler: 1: j 1b -TIM4_IRQHandler: 1: j 1b -I2C1_EV_IRQHandler: 1: j 1b -I2C1_ER_IRQHandler: 1: j 1b -I2C2_EV_IRQHandler: 1: j 1b -I2C2_ER_IRQHandler: 1: j 1b -SPI1_IRQHandler: 1: j 1b -SPI2_IRQHandler: 1: j 1b -USART1_IRQHandler: 1: j 1b -USART2_IRQHandler: 1: j 1b -USART3_IRQHandler: 1: j 1b -EXTI15_10_IRQHandler: 1: j 1b -RTCAlarm_IRQHandler: 1: j 1b -TIM8_BRK_IRQHandler: 1: j 1b -TIM8_UP_IRQHandler: 1: j 1b -TIM8_TRG_COM_IRQHandler: 1: j 1b -TIM8_CC_IRQHandler: 1: j 1b -RNG_IRQHandler: 1: j 1b -FSMC_IRQHandler: 1: j 1b -SDIO_IRQHandler: 1: j 1b -TIM5_IRQHandler: 1: j 1b -SPI3_IRQHandler: 1: j 1b -UART4_IRQHandler: 1: j 1b -UART5_IRQHandler: 1: j 1b -TIM6_IRQHandler: 1: j 1b -TIM7_IRQHandler: 1: j 1b -DMA2_Channel1_IRQHandler: 1: j 1b -DMA2_Channel2_IRQHandler: 1: j 1b -DMA2_Channel3_IRQHandler: 1: j 1b -DMA2_Channel4_IRQHandler: 1: j 1b -DMA2_Channel5_IRQHandler: 1: j 1b -OTG_FS_IRQHandler: 1: j 1b -UART6_IRQHandler: 1: j 1b -UART7_IRQHandler: 1: j 1b -UART8_IRQHandler: 1: j 1b -TIM9_BRK_IRQHandler: 1: j 1b -TIM9_UP_IRQHandler: 1: j 1b -TIM9_TRG_COM_IRQHandler: 1: j 1b -TIM9_CC_IRQHandler: 1: j 1b -TIM10_BRK_IRQHandler: 1: j 1b -TIM10_UP_IRQHandler: 1: j 1b -TIM10_TRG_COM_IRQHandler: 1: j 1b -TIM10_CC_IRQHandler: 1: j 1b -DMA2_Channel6_IRQHandler: 1: j 1b -DMA2_Channel7_IRQHandler: 1: j 1b -DMA2_Channel8_IRQHandler: 1: j 1b -DMA2_Channel9_IRQHandler: 1: j 1b -DMA2_Channel10_IRQHandler: 1: j 1b -DMA2_Channel11_IRQHandler: 1: j 1b - +NMI_Handler: +HardFault_Handler: +Ecall_M_Mode_Handler: +Ecall_U_Mode_Handler: +Break_Point_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +TAMPER_IRQHandler: +RTC_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI0_IRQHandler: +EXTI1_IRQHandler: +EXTI2_IRQHandler: +EXTI3_IRQHandler: +EXTI4_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_2_IRQHandler: +USB_HP_CAN1_TX_IRQHandler: +USB_LP_CAN1_RX0_IRQHandler: +CAN1_RX1_IRQHandler: +CAN1_SCE_IRQHandler: +EXTI9_5_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +TIM3_IRQHandler: +TIM4_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +I2C2_EV_IRQHandler: +I2C2_ER_IRQHandler: +SPI1_IRQHandler: +SPI2_IRQHandler: +USART1_IRQHandler: +USART2_IRQHandler: +USART3_IRQHandler: +EXTI15_10_IRQHandler: +RTCAlarm_IRQHandler: +TIM8_BRK_IRQHandler: +TIM8_UP_IRQHandler: +TIM8_TRG_COM_IRQHandler: +TIM8_CC_IRQHandler: +RNG_IRQHandler: +SDIO_IRQHandler: +TIM5_IRQHandler: +SPI3_IRQHandler: +UART4_IRQHandler: +UART5_IRQHandler: +TIM6_IRQHandler: +TIM7_IRQHandler: +DMA2_Channel1_IRQHandler: +DMA2_Channel2_IRQHandler: +DMA2_Channel3_IRQHandler: +DMA2_Channel4_IRQHandler: +DMA2_Channel5_IRQHandler: +USBFS_IRQHandler: +UART6_IRQHandler: +UART7_IRQHandler: +UART8_IRQHandler: +TIM9_BRK_IRQHandler: +TIM9_UP_IRQHandler: +TIM9_TRG_COM_IRQHandler: +TIM9_CC_IRQHandler: +TIM10_BRK_IRQHandler: +TIM10_UP_IRQHandler: +TIM10_TRG_COM_IRQHandler: +TIM10_CC_IRQHandler: +DMA2_Channel6_IRQHandler: +DMA2_Channel7_IRQHandler: +DMA2_Channel8_IRQHandler: +DMA2_Channel9_IRQHandler: +DMA2_Channel10_IRQHandler: +DMA2_Channel11_IRQHandler: +1: + j 1b .section .text.handle_reset,"ax",@progbits .weak handle_reset @@ -325,7 +311,7 @@ handle_reset: 1: la sp, _eusrstack 2: - /* Load data section from flash to RAM */ +/* Load data section from flash to RAM */ la a0, _data_lma la a1, _data_vma la a2, _edata @@ -337,7 +323,7 @@ handle_reset: addi a1, a1, 4 bltu a1, a2, 1b 2: - /* Clear bss section */ +/* Clear bss section */ la a0, _sbss la a1, _ebss bgeu a0, a1, 2f @@ -346,25 +332,20 @@ handle_reset: addi a0, a0, 4 bltu a0, a1, 1b 2: +/* Configure pipelining and instruction prediction */ li t0, 0x1f csrw 0xbc0, t0 - - /* Enable nested and hardware stack */ +/* Enable interrupt nesting and hardware stack */ li t0, 0x0b csrw 0x804, t0 - - /* Enable floating point and interrupt */ +/* Enable floating point and global interrupt, configure privileged mode */ li t0, 0x6088 - csrs mstatus, t0 - + csrw mstatus, t0 +/* Configure the interrupt vector table recognition mode and entry address mode */ la t0, _vector_base ori t0, t0, 3 csrw mtvec, t0 - la a0, __libc_fini_array - call atexit - call __libc_init_array - jal SystemInit la t0, main csrw mepc, t0 diff --git a/system/CH32V30x/SRC/Startup/startup_ch32v30x_D8C.S b/system/CH32V30x/SRC/Startup/startup_ch32v30x_D8C.S index 2b526c2..f021c5b 100644 --- a/system/CH32V30x/SRC/Startup/startup_ch32v30x_D8C.S +++ b/system/CH32V30x/SRC/Startup/startup_ch32v30x_D8C.S @@ -1,8 +1,8 @@ /********************************** (C) COPYRIGHT ******************************* * File Name : startup_ch32v30x_D8C.s * Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 +* Version : V1.0.1 +* Date : 2024/03/06 * Description : CH32V307x-CH32V305x vector table for eclipse toolchain. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -15,19 +15,7 @@ .align 1 _start: j handle_reset - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00000013 - .word 0x00100073 + .section .vector,"ax",@progbits .align 1 _vector_base: @@ -97,7 +85,7 @@ _vector_base: .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word RNG_IRQHandler /* RNG */ - .word FSMC_IRQHandler /* FSMC */ + .word 0 .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ @@ -116,7 +104,7 @@ _vector_base: .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* OTGFS */ + .word USBFS_IRQHandler /* USBFS */ .word USBHSWakeup_IRQHandler /* USBHS Wakeup */ .word USBHS_IRQHandler /* USBHS */ .word DVP_IRQHandler /* DVP */ @@ -139,7 +127,6 @@ _vector_base: .word DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ .option rvc; - .section .text.vector_handler, "ax", @progbits .weak NMI_Handler /* NMI */ .weak HardFault_Handler /* Hard Fault */ @@ -196,7 +183,6 @@ _vector_base: .weak TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ .weak TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .weak RNG_IRQHandler /* RNG */ - .weak FSMC_IRQHandler /* FSMC */ .weak SDIO_IRQHandler /* SDIO */ .weak TIM5_IRQHandler /* TIM5 */ .weak SPI3_IRQHandler /* SPI3 */ @@ -215,7 +201,7 @@ _vector_base: .weak CAN2_RX0_IRQHandler /* CAN2 RX0 */ .weak CAN2_RX1_IRQHandler /* CAN2 RX1 */ .weak CAN2_SCE_IRQHandler /* CAN2 SCE */ - .weak OTG_FS_IRQHandler /* OTGFS */ + .weak USBFS_IRQHandler /* USBFS */ .weak USBHSWakeup_IRQHandler /* USBHS Wakeup */ .weak USBHS_IRQHandler /* USBHS */ .weak DVP_IRQHandler /* DVP */ @@ -237,102 +223,102 @@ _vector_base: .weak DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */ .weak DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ -NMI_Handler: 1: j 1b -HardFault_Handler: 1: j 1b -Ecall_M_Mode_Handler: 1: j 1b -Ecall_U_Mode_Handler: 1: j 1b -Break_Point_Handler: 1: j 1b -SysTick_Handler: 1: j 1b -SW_Handler: 1: j 1b -WWDG_IRQHandler: 1: j 1b -PVD_IRQHandler: 1: j 1b -TAMPER_IRQHandler: 1: j 1b -RTC_IRQHandler: 1: j 1b -FLASH_IRQHandler: 1: j 1b -RCC_IRQHandler: 1: j 1b -EXTI0_IRQHandler: 1: j 1b -EXTI1_IRQHandler: 1: j 1b -EXTI2_IRQHandler: 1: j 1b -EXTI3_IRQHandler: 1: j 1b -EXTI4_IRQHandler: 1: j 1b -DMA1_Channel1_IRQHandler: 1: j 1b -DMA1_Channel2_IRQHandler: 1: j 1b -DMA1_Channel3_IRQHandler: 1: j 1b -DMA1_Channel4_IRQHandler: 1: j 1b -DMA1_Channel5_IRQHandler: 1: j 1b -DMA1_Channel6_IRQHandler: 1: j 1b -DMA1_Channel7_IRQHandler: 1: j 1b -ADC1_2_IRQHandler: 1: j 1b -USB_HP_CAN1_TX_IRQHandler: 1: j 1b -USB_LP_CAN1_RX0_IRQHandler: 1: j 1b -CAN1_RX1_IRQHandler: 1: j 1b -CAN1_SCE_IRQHandler: 1: j 1b -EXTI9_5_IRQHandler: 1: j 1b -TIM1_BRK_IRQHandler: 1: j 1b -TIM1_UP_IRQHandler: 1: j 1b -TIM1_TRG_COM_IRQHandler: 1: j 1b -TIM1_CC_IRQHandler: 1: j 1b -TIM2_IRQHandler: 1: j 1b -TIM3_IRQHandler: 1: j 1b -TIM4_IRQHandler: 1: j 1b -I2C1_EV_IRQHandler: 1: j 1b -I2C1_ER_IRQHandler: 1: j 1b -I2C2_EV_IRQHandler: 1: j 1b -I2C2_ER_IRQHandler: 1: j 1b -SPI1_IRQHandler: 1: j 1b -SPI2_IRQHandler: 1: j 1b -USART1_IRQHandler: 1: j 1b -USART2_IRQHandler: 1: j 1b -USART3_IRQHandler: 1: j 1b -EXTI15_10_IRQHandler: 1: j 1b -RTCAlarm_IRQHandler: 1: j 1b -USBWakeUp_IRQHandler: 1: j 1b -TIM8_BRK_IRQHandler: 1: j 1b -TIM8_UP_IRQHandler: 1: j 1b -TIM8_TRG_COM_IRQHandler: 1: j 1b -TIM8_CC_IRQHandler: 1: j 1b -RNG_IRQHandler: 1: j 1b -FSMC_IRQHandler: 1: j 1b -SDIO_IRQHandler: 1: j 1b -TIM5_IRQHandler: 1: j 1b -SPI3_IRQHandler: 1: j 1b -UART4_IRQHandler: 1: j 1b -UART5_IRQHandler: 1: j 1b -TIM6_IRQHandler: 1: j 1b -TIM7_IRQHandler: 1: j 1b -DMA2_Channel1_IRQHandler: 1: j 1b -DMA2_Channel2_IRQHandler: 1: j 1b -DMA2_Channel3_IRQHandler: 1: j 1b -DMA2_Channel4_IRQHandler: 1: j 1b -DMA2_Channel5_IRQHandler: 1: j 1b -ETH_IRQHandler: 1: j 1b -ETH_WKUP_IRQHandler: 1: j 1b -CAN2_TX_IRQHandler: 1: j 1b -CAN2_RX0_IRQHandler: 1: j 1b -CAN2_RX1_IRQHandler: 1: j 1b -CAN2_SCE_IRQHandler: 1: j 1b -OTG_FS_IRQHandler: 1: j 1b -USBHSWakeup_IRQHandler: 1: j 1b -USBHS_IRQHandler: 1: j 1b -DVP_IRQHandler: 1: j 1b -UART6_IRQHandler: 1: j 1b -UART7_IRQHandler: 1: j 1b -UART8_IRQHandler: 1: j 1b -TIM9_BRK_IRQHandler: 1: j 1b -TIM9_UP_IRQHandler: 1: j 1b -TIM9_TRG_COM_IRQHandler: 1: j 1b -TIM9_CC_IRQHandler: 1: j 1b -TIM10_BRK_IRQHandler: 1: j 1b -TIM10_UP_IRQHandler: 1: j 1b -TIM10_TRG_COM_IRQHandler: 1: j 1b -TIM10_CC_IRQHandler: 1: j 1b -DMA2_Channel6_IRQHandler: 1: j 1b -DMA2_Channel7_IRQHandler: 1: j 1b -DMA2_Channel8_IRQHandler: 1: j 1b -DMA2_Channel9_IRQHandler: 1: j 1b -DMA2_Channel10_IRQHandler: 1: j 1b -DMA2_Channel11_IRQHandler: 1: j 1b - +NMI_Handler: +HardFault_Handler: +Ecall_M_Mode_Handler: +Ecall_U_Mode_Handler: +Break_Point_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +TAMPER_IRQHandler: +RTC_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI0_IRQHandler: +EXTI1_IRQHandler: +EXTI2_IRQHandler: +EXTI3_IRQHandler: +EXTI4_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_2_IRQHandler: +USB_HP_CAN1_TX_IRQHandler: +USB_LP_CAN1_RX0_IRQHandler: +CAN1_RX1_IRQHandler: +CAN1_SCE_IRQHandler: +EXTI9_5_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +TIM3_IRQHandler: +TIM4_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +I2C2_EV_IRQHandler: +I2C2_ER_IRQHandler: +SPI1_IRQHandler: +SPI2_IRQHandler: +USART1_IRQHandler: +USART2_IRQHandler: +USART3_IRQHandler: +EXTI15_10_IRQHandler: +RTCAlarm_IRQHandler: +USBWakeUp_IRQHandler: +TIM8_BRK_IRQHandler: +TIM8_UP_IRQHandler: +TIM8_TRG_COM_IRQHandler: +TIM8_CC_IRQHandler: +RNG_IRQHandler: +SDIO_IRQHandler: +TIM5_IRQHandler: +SPI3_IRQHandler: +UART4_IRQHandler: +UART5_IRQHandler: +TIM6_IRQHandler: +TIM7_IRQHandler: +DMA2_Channel1_IRQHandler: +DMA2_Channel2_IRQHandler: +DMA2_Channel3_IRQHandler: +DMA2_Channel4_IRQHandler: +DMA2_Channel5_IRQHandler: +ETH_IRQHandler: +ETH_WKUP_IRQHandler: +CAN2_TX_IRQHandler: +CAN2_RX0_IRQHandler: +CAN2_RX1_IRQHandler: +CAN2_SCE_IRQHandler: +USBFS_IRQHandler: +USBHSWakeup_IRQHandler: +USBHS_IRQHandler: +DVP_IRQHandler: +UART6_IRQHandler: +UART7_IRQHandler: +UART8_IRQHandler: +TIM9_BRK_IRQHandler: +TIM9_UP_IRQHandler: +TIM9_TRG_COM_IRQHandler: +TIM9_CC_IRQHandler: +TIM10_BRK_IRQHandler: +TIM10_UP_IRQHandler: +TIM10_TRG_COM_IRQHandler: +TIM10_CC_IRQHandler: +DMA2_Channel6_IRQHandler: +DMA2_Channel7_IRQHandler: +DMA2_Channel8_IRQHandler: +DMA2_Channel9_IRQHandler: +DMA2_Channel10_IRQHandler: +DMA2_Channel11_IRQHandler: +1: + j 1b .section .text.handle_reset,"ax",@progbits .weak handle_reset @@ -345,7 +331,7 @@ handle_reset: 1: la sp, _eusrstack 2: - /* Load data section from flash to RAM */ +/* Load data section from flash to RAM */ la a0, _data_lma la a1, _data_vma la a2, _edata @@ -357,7 +343,7 @@ handle_reset: addi a1, a1, 4 bltu a1, a2, 1b 2: - /* Clear bss section */ +/* Clear bss section */ la a0, _sbss la a1, _ebss bgeu a0, a1, 2f @@ -366,25 +352,20 @@ handle_reset: addi a0, a0, 4 bltu a0, a1, 1b 2: +/* Configure pipelining and instruction prediction */ li t0, 0x1f csrw 0xbc0, t0 - - /* Enable nested and hardware stack */ +/* Enable interrupt nesting and hardware stack */ li t0, 0x0b csrw 0x804, t0 - - /* Enable floating point and interrupt */ +/* Enable floating point and global interrupt, configure privileged mode */ li t0, 0x6088 - csrs mstatus, t0 - + csrw mstatus, t0 +/* Configure the interrupt vector table recognition mode and entry address mode */ la t0, _vector_base ori t0, t0, 3 csrw mtvec, t0 - la a0, __libc_fini_array - call atexit - call __libc_init_array - jal SystemInit la t0, main csrw mepc, t0 diff --git a/system/CH32V30x/USER/ch32v30x_conf.h b/system/CH32V30x/USER/ch32v30x_conf.h index bfd19b3..f8f2483 100644 --- a/system/CH32V30x/USER/ch32v30x_conf.h +++ b/system/CH32V30x/USER/ch32v30x_conf.h @@ -1,45 +1,45 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_conf.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : Library configuration file. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V30x_CONF_H -#define __CH32V30x_CONF_H - -#include "ch32v30x_adc.h" -#include "ch32v30x_bkp.h" -#include "ch32v30x_can.h" -#include "ch32v30x_crc.h" -#include "ch32v30x_dac.h" -#include "ch32v30x_dbgmcu.h" -#include "ch32v30x_dma.h" -#include "ch32v30x_exti.h" -#include "ch32v30x_flash.h" -#include "ch32v30x_fsmc.h" -#include "ch32v30x_gpio.h" -#include "ch32v30x_i2c.h" -#include "ch32v30x_iwdg.h" -#include "ch32v30x_pwr.h" -#include "ch32v30x_rcc.h" -#include "ch32v30x_rtc.h" -#include "ch32v30x_sdio.h" -#include "ch32v30x_spi.h" -#include "ch32v30x_tim.h" -#include "ch32v30x_usart.h" -#include "ch32v30x_wwdg.h" -#include "ch32v30x_it.h" -#include "ch32v30x_misc.h" - - -#endif /* __CH32V30x_CONF_H */ - - - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_conf.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : Library configuration file. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_CONF_H +#define __CH32V30x_CONF_H + +#include "ch32v30x_adc.h" +#include "ch32v30x_bkp.h" +#include "ch32v30x_can.h" +#include "ch32v30x_crc.h" +#include "ch32v30x_dac.h" +#include "ch32v30x_dbgmcu.h" +#include "ch32v30x_dma.h" +#include "ch32v30x_exti.h" +#include "ch32v30x_flash.h" +#include "ch32v30x_fsmc.h" +#include "ch32v30x_gpio.h" +#include "ch32v30x_i2c.h" +#include "ch32v30x_iwdg.h" +#include "ch32v30x_pwr.h" +#include "ch32v30x_rcc.h" +#include "ch32v30x_rtc.h" +#include "ch32v30x_sdio.h" +#include "ch32v30x_spi.h" +#include "ch32v30x_tim.h" +#include "ch32v30x_usart.h" +#include "ch32v30x_wwdg.h" +#include "ch32v30x_it.h" +#include "ch32v30x_misc.h" + + +#endif /* __CH32V30x_CONF_H */ + + + + + diff --git a/system/CH32V30x/USER/ch32v30x_it.c b/system/CH32V30x/USER/ch32v30x_it.c index e001e0f..262d5c6 100644 --- a/system/CH32V30x/USER/ch32v30x_it.c +++ b/system/CH32V30x/USER/ch32v30x_it.c @@ -1,42 +1,46 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_it.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : Main Interrupt Service Routines. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x_it.h" - -void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); - -/********************************************************************* - * @fn NMI_Handler - * - * @brief This function handles NMI exception. - * - * @return none - */ -void NMI_Handler(void) -{ -} - -/********************************************************************* - * @fn HardFault_Handler - * - * @brief This function handles Hard Fault exception. - * - * @return none - */ -void HardFault_Handler(void) -{ - while (1) - { - } -} - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_it.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : Main Interrupt Service Routines. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_it.h" + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ + while (1) + { + } +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + NVIC_SystemReset(); + while (1) + { + } +} + + diff --git a/system/CH32V30x/USER/system_ch32v30x.c b/system/CH32V30x/USER/system_ch32v30x.c index d3f36a2..4bd26c3 100644 --- a/system/CH32V30x/USER/system_ch32v30x.c +++ b/system/CH32V30x/USER/system_ch32v30x.c @@ -1,1014 +1,1036 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : system_ch32v30x.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : CH32V30x Device Peripheral Access Layer System Source File. -* For HSE = 8Mhz -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32v30x.h" - -/* -* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after -* reset the HSI is used as SYSCLK source). -* If none of the define below is enabled, the HSI is used as System clock source. -*/ -//#define SYSCLK_FREQ_HSE HSE_VALUE -//#define SYSCLK_FREQ_48MHz_HSE 48000000 -//#define SYSCLK_FREQ_56MHz_HSE 56000000 -//#define SYSCLK_FREQ_72MHz_HSE 72000000 -// #define SYSCLK_FREQ_96MHz_HSE 96000000 -//#define SYSCLK_FREQ_120MHz_HSE 120000000 -//#define SYSCLK_FREQ_144MHz_HSE 144000000 -//#define SYSCLK_FREQ_HSI HSI_VALUE -//#define SYSCLK_FREQ_48MHz_HSI 48000000 -//#define SYSCLK_FREQ_56MHz_HSI 56000000 -//#define SYSCLK_FREQ_72MHz_HSI 72000000 -//#define SYSCLK_FREQ_96MHz_HSI 96000000 -//#define SYSCLK_FREQ_120MHz_HSI 120000000 -//#define SYSCLK_FREQ_144MHz_HSI 144000000 - -/* Clock Definitions */ -#ifdef SYSCLK_FREQ_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_96MHz_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_120MHz_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_144MHz_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_96MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_120MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_144MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */ -#else -uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ - -#endif - -__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - - -/* system_private_function_proto_types */ -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE -static void SetSysClockToHSE( void ); -#elif defined SYSCLK_FREQ_48MHz_HSE -static void SetSysClockTo48_HSE( void ); -#elif defined SYSCLK_FREQ_56MHz_HSE -static void SetSysClockTo56_HSE( void ); -#elif defined SYSCLK_FREQ_72MHz_HSE -static void SetSysClockTo72_HSE( void ); -#elif defined SYSCLK_FREQ_96MHz_HSE -static void SetSysClockTo96_HSE( void ); -#elif defined SYSCLK_FREQ_120MHz_HSE -static void SetSysClockTo120_HSE( void ); -#elif defined SYSCLK_FREQ_144MHz_HSE -static void SetSysClockTo144_HSE( void ); -#elif defined SYSCLK_FREQ_48MHz_HSI -static void SetSysClockTo48_HSI( void ); -#elif defined SYSCLK_FREQ_56MHz_HSI -static void SetSysClockTo56_HSI( void ); -#elif defined SYSCLK_FREQ_72MHz_HSI -static void SetSysClockTo72_HSI( void ); -#elif defined SYSCLK_FREQ_96MHz_HSI -static void SetSysClockTo96_HSI( void ); -#elif defined SYSCLK_FREQ_120MHz_HSI -static void SetSysClockTo120_HSI( void ); -#elif defined SYSCLK_FREQ_144MHz_HSI -static void SetSysClockTo144_HSI( void ); - -#endif - - -/********************************************************************* - * @fn SystemInit - * - * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, - * the PLL and update the SystemCoreClock variable. - * - * @return none - */ -void SystemInit (void) -{ - RCC->CTLR |= (uint32_t)0x00000001; - -#ifdef CH32V30x_D8C - RCC->CFGR0 &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR0 &= (uint32_t)0xF0FF0000; -#endif - - RCC->CTLR &= (uint32_t)0xFEF6FFFF; - RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; - -#ifdef CH32V30x_D8C - RCC->CTLR &= (uint32_t)0xEBFFFFFF; - RCC->INTR = 0x00FF0000; - RCC->CFGR2 = 0x00000000; -#else - RCC->INTR = 0x009F0000; -#endif - SetSysClock(); -} - -/********************************************************************* - * @fn SystemCoreClockUpdate - * - * @brief Update SystemCoreClock variable according to Clock Register Values. - * - * @return none - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0; - - tmp = RCC->CFGR0 & RCC_SWS; - - switch (tmp) - { - case 0x00: - SystemCoreClock = HSI_VALUE; - break; - case 0x04: - SystemCoreClock = HSE_VALUE; - break; - case 0x08: - pllmull = RCC->CFGR0 & RCC_PLLMULL; - pllsource = RCC->CFGR0 & RCC_PLLSRC; - pllmull = ( pllmull >> 18) + 2; - -#ifdef CH32V30x_D8 - if(pllmull == 17) pllmull = 18; -#else - if(pllmull == 2) pllmull = 18; - if(pllmull == 15){ - pllmull = 13; /* *6.5 */ - Pll_6_5 = 1; - } - if(pllmull == 16) pllmull = 15; - if(pllmull == 17) pllmull = 16; -#endif - - if (pllsource == 0x00) - { - if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ - SystemCoreClock = (HSI_VALUE) * pllmull; - } - else{ - SystemCoreClock = (HSI_VALUE >>1) * pllmull; - } - } - else - { - if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) - { - SystemCoreClock = (HSE_VALUE >> 1) * pllmull; - } - else - { - SystemCoreClock = HSE_VALUE * pllmull; - } - } - - if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2); - - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - - tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; - SystemCoreClock >>= tmp; -} - -/********************************************************************* - * @fn SetSysClock - * - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_48MHz_HSE - SetSysClockTo48_HSE(); -#elif defined SYSCLK_FREQ_56MHz_HSE - SetSysClockTo56_HSE(); -#elif defined SYSCLK_FREQ_72MHz_HSE - SetSysClockTo72_HSE(); -#elif defined SYSCLK_FREQ_96MHz_HSE - SetSysClockTo96_HSE(); -#elif defined SYSCLK_FREQ_120MHz_HSE - SetSysClockTo120_HSE(); -#elif defined SYSCLK_FREQ_144MHz_HSE - SetSysClockTo144_HSE(); -#elif defined SYSCLK_FREQ_48MHz_HSI - SetSysClockTo48_HSI(); -#elif defined SYSCLK_FREQ_56MHz_HSI - SetSysClockTo56_HSI(); -#elif defined SYSCLK_FREQ_72MHz_HSI - SetSysClockTo72_HSI(); -#elif defined SYSCLK_FREQ_96MHz_HSI - SetSysClockTo96_HSI(); -#elif defined SYSCLK_FREQ_120MHz_HSI - SetSysClockTo120_HSI(); -#elif defined SYSCLK_FREQ_144MHz_HSI - SetSysClockTo144_HSI(); - -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - * source (default after reset) - */ -} - - -#ifdef SYSCLK_FREQ_HSE - -/********************************************************************* - * @fn SetSysClockToHSE - * - * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) - { - } - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_48MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo48_HSE - * - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo48_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_56MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo56_HSE - * - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo56_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_72MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo72_HSE - * - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo72_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | - RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - - -#elif defined SYSCLK_FREQ_96MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo96_HSE - * - * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo96_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | - RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - - -#elif defined SYSCLK_FREQ_120MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo120_HSE - * - * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo120_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | - RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - - -#elif defined SYSCLK_FREQ_144MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo144_HSE - * - * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo144_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | - RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_48MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo48_HSI - * - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo48_HSI(void) -{ - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - -#elif defined SYSCLK_FREQ_56MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo56_HSI - * - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo56_HSI(void) -{ - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - -#elif defined SYSCLK_FREQ_72MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo72_HSI - * - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo72_HSI(void) -{ - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - - -#elif defined SYSCLK_FREQ_96MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo96_HSI - * - * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo96_HSI(void) -{ - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - - -#elif defined SYSCLK_FREQ_120MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo120_HSI - * - * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo120_HSI(void) -{ - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - - -#elif defined SYSCLK_FREQ_144MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo144_HSI - * - * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo144_HSI(void) -{ - EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } -} - -#endif +/********************************** (C) COPYRIGHT ******************************* +* File Name : system_ch32v30x.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : CH32V30x Device Peripheral Access Layer System Source File. +* For HSE = 8Mhz +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x.h" + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ +//#define SYSCLK_FREQ_HSE HSE_VALUE +//#define SYSCLK_FREQ_48MHz_HSE 48000000 +//#define SYSCLK_FREQ_56MHz_HSE 56000000 +//#define SYSCLK_FREQ_72MHz_HSE 72000000 +// #define SYSCLK_FREQ_96MHz_HSE 96000000 +//#define SYSCLK_FREQ_120MHz_HSE 120000000 +//#define SYSCLK_FREQ_144MHz_HSE 144000000 +//#define SYSCLK_FREQ_HSI HSI_VALUE +//#define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_56MHz_HSI 56000000 +//#define SYSCLK_FREQ_72MHz_HSI 72000000 +//#define SYSCLK_FREQ_96MHz_HSI 96000000 +//#define SYSCLK_FREQ_120MHz_HSI 120000000 +//#define SYSCLK_FREQ_144MHz_HSI 144000000 + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */ +#else +uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ + +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE +static void SetSysClockToHSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSE +static void SetSysClockTo48_HSE( void ); +#elif defined SYSCLK_FREQ_56MHz_HSE +static void SetSysClockTo56_HSE( void ); +#elif defined SYSCLK_FREQ_72MHz_HSE +static void SetSysClockTo72_HSE( void ); +#elif defined SYSCLK_FREQ_96MHz_HSE +static void SetSysClockTo96_HSE( void ); +#elif defined SYSCLK_FREQ_120MHz_HSE +static void SetSysClockTo120_HSE( void ); +#elif defined SYSCLK_FREQ_144MHz_HSE +static void SetSysClockTo144_HSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSI +static void SetSysClockTo48_HSI( void ); +#elif defined SYSCLK_FREQ_56MHz_HSI +static void SetSysClockTo56_HSI( void ); +#elif defined SYSCLK_FREQ_72MHz_HSI +static void SetSysClockTo72_HSI( void ); +#elif defined SYSCLK_FREQ_96MHz_HSI +static void SetSysClockTo96_HSI( void ); +#elif defined SYSCLK_FREQ_120MHz_HSI +static void SetSysClockTo120_HSI( void ); +#elif defined SYSCLK_FREQ_144MHz_HSI +static void SetSysClockTo144_HSI( void ); + +#endif + + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + + RCC->CFGR0 &= (uint32_t)0xF0FF0000; + + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; + +#ifdef CH32V30x_D8C + RCC->CTLR &= (uint32_t)0xEBFFFFFF; + RCC->INTR = 0x00FF0000; + RCC->CFGR2 = 0x00000000; +#else + RCC->INTR = 0x009F0000; +#endif + SetSysClock(); +} + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + uint8_t Pll_6_5 = 0; + +#ifdef CH32V30x_D8C + uint8_t Pll2mull = 0; + +#endif + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + +#ifdef CH32V30x_D8 + if(pllmull == 17) pllmull = 18; +#else + if(pllmull == 2) pllmull = 18; + if(pllmull == 15){ + pllmull = 13; /* *6.5 */ + Pll_6_5 = 1; + } + if(pllmull == 16) pllmull = 15; + if(pllmull == 17) pllmull = 16; +#endif + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) SystemCoreClock = HSI_VALUE * pllmull; + else SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + +#ifdef CH32V30x_D8 + if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + +#else + if(RCC->CFGR2 & (1<<16)){ /* PLL2 */ + SystemCoreClock = HSE_VALUE/(((RCC->CFGR2 & 0xF0)>>4) + 1); /* PREDIV2 */ + + Pll2mull = (uint8_t)((RCC->CFGR2 & 0xF00)>>8); + + if(Pll2mull == 0) SystemCoreClock = (SystemCoreClock * 5)>>1; + else if(Pll2mull == 1) SystemCoreClock = (SystemCoreClock * 25)>>1; + else if(Pll2mull == 15) SystemCoreClock = SystemCoreClock * 20; + else SystemCoreClock = SystemCoreClock * (Pll2mull + 2); + + SystemCoreClock = SystemCoreClock/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */ + } + else{/* HSE */ + SystemCoreClock = HSE_VALUE/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */ + } + + SystemCoreClock = SystemCoreClock * pllmull; +#endif + } + + + if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2); + + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ + //GPIO_IPD_Unused(); +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo48_HSE(); +#elif defined SYSCLK_FREQ_56MHz_HSE + SetSysClockTo56_HSE(); +#elif defined SYSCLK_FREQ_72MHz_HSE + SetSysClockTo72_HSE(); +#elif defined SYSCLK_FREQ_96MHz_HSE + SetSysClockTo96_HSE(); +#elif defined SYSCLK_FREQ_120MHz_HSE + SetSysClockTo120_HSE(); +#elif defined SYSCLK_FREQ_144MHz_HSE + SetSysClockTo144_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); +#elif defined SYSCLK_FREQ_56MHz_HSI + SetSysClockTo56_HSI(); +#elif defined SYSCLK_FREQ_72MHz_HSI + SetSysClockTo72_HSI(); +#elif defined SYSCLK_FREQ_96MHz_HSI + SetSysClockTo96_HSI(); +#elif defined SYSCLK_FREQ_120MHz_HSI + SetSysClockTo120_HSI(); +#elif defined SYSCLK_FREQ_144MHz_HSI + SetSysClockTo144_HSI(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo48_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo56_HSE + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo72_HSE + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo96_HSE + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo120_HSE + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_144MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo144_HSE + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo56_HSI + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo72_HSI + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo96_HSI + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo120_HSI + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_144MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo144_HSI + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#endif diff --git a/system/CH32V30x/USER/system_ch32v30x.h b/system/CH32V30x/USER/system_ch32v30x.h index 056839b..8126393 100644 --- a/system/CH32V30x/USER/system_ch32v30x.h +++ b/system/CH32V30x/USER/system_ch32v30x.h @@ -1,32 +1,32 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : system_ch32v30x.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : CH32V30x Device Peripheral Access Layer System Header File. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __SYSTEM_CH32V30x_H -#define __SYSTEM_CH32V30x_H - -#ifdef __cplusplus - extern "C" { -#endif - -extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ - -/* System_Exported_Functions */ -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V30x_SYSTEM_H */ - - - +/********************************** (C) COPYRIGHT ******************************* +* File Name : system_ch32v30x.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : CH32V30x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_CH32V30x_H +#define __SYSTEM_CH32V30x_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V30x_SYSTEM_H */ + + + diff --git a/system/CH32VM00X/SRC/Core/core_riscv.c b/system/CH32VM00X/SRC/Core/core_riscv.c index 2aa1108..b61bf3d 100644 --- a/system/CH32VM00X/SRC/Core/core_riscv.c +++ b/system/CH32VM00X/SRC/Core/core_riscv.c @@ -1,276 +1,276 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : core_riscv.c - * Author : WCH - * Version : V1.0.1 - * Date : 2024/01/01 - * Description : RISC-V V2 Core Peripheral Access Layer Source File for CH32V00X - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -/* define compiler specific symbols */ -#if defined(__CC_ARM) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined(__ICCARM__) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined(__GNUC__) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined(__TASKING__) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/********************************************************************* - * @fn __get_MSTATUS - * - * @brief Return the Machine Status Register - * - * @return mstatus value - */ -uint32_t __get_MSTATUS(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mstatus": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MSTATUS - * - * @brief Set the Machine Status Register - * - * @param value - set mstatus value - * - * @return none - */ -void __set_MSTATUS(uint32_t value) -{ - __ASM volatile("csrw mstatus, %0" : : "r"(value)); -} - -/********************************************************************* - * @fn __get_MISA - * - * @brief Return the Machine ISA Register - * - * @return misa value - */ -uint32_t __get_MISA(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""misa" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MISA - * - * @brief Set the Machine ISA Register - * - * @param value - set misa value - * - * @return none - */ -void __set_MISA(uint32_t value) -{ - __ASM volatile("csrw misa, %0" : : "r"(value)); -} - -/********************************************************************* - * @fn __get_MTVEC - * - * @brief Return the Machine Trap-Vector Base-Address Register - * - * @return mtvec value - */ -uint32_t __get_MTVEC(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mtvec": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MTVEC - * - * @brief Set the Machine Trap-Vector Base-Address Register - * - * @param value - set mtvec value - * - * @return none - */ -void __set_MTVEC(uint32_t value) -{ - __ASM volatile("csrw mtvec, %0":: "r"(value)); -} - -/********************************************************************* - * @fn __get_MSCRATCH - * - * @brief Return the Machine Seratch Register - * - * @return mscratch value - */ -uint32_t __get_MSCRATCH(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mscratch" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MSCRATCH - * - * @brief Set the Machine Seratch Register - * - * @param value - set mscratch value - * - * @return none - */ -void __set_MSCRATCH(uint32_t value) -{ - __ASM volatile("csrw mscratch, %0" : : "r"(value)); -} - -/********************************************************************* - * @fn __get_MEPC - * - * @brief Return the Machine Exception Program Register - * - * @return mepc value - */ -uint32_t __get_MEPC(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mepc" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Exception Program Register - * - * @return mepc value - */ -void __set_MEPC(uint32_t value) -{ - __ASM volatile("csrw mepc, %0" : : "r"(value)); -} - -/********************************************************************* - * @fn __get_MCAUSE - * - * @brief Return the Machine Cause Register - * - * @return mcause value - */ -uint32_t __get_MCAUSE(void) -{ - uint32_t result; - - __ASM volatile("csrr %0," "mcause": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Cause Register - * - * @return mcause value - */ -void __set_MCAUSE(uint32_t value) -{ - __ASM volatile("csrw mcause, %0":: "r"(value)); -} - -/********************************************************************* - * @fn __get_MVENDORID - * - * @brief Return Vendor ID Register - * - * @return mvendorid value - */ -uint32_t __get_MVENDORID(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""mvendorid": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __get_MARCHID - * - * @brief Return Machine Architecture ID Register - * - * @return marchid value - */ -uint32_t __get_MARCHID(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""marchid": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __get_MIMPID - * - * @brief Return Machine Implementation ID Register - * - * @return mimpid value - */ -uint32_t __get_MIMPID(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""mimpid": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __get_MHARTID - * - * @brief Return Hart ID Register - * - * @return mhartid value - */ -uint32_t __get_MHARTID(void) -{ - uint32_t result; - - __ASM volatile("csrr %0,""mhartid": "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __get_SP - * - * @brief Return SP Register - * - * @return SP value - */ -uint32_t __get_SP(void) -{ - uint32_t result; - - __ASM volatile("mv %0,""sp": "=r"(result):); - return (result); -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.c + * Author : WCH + * Version : V1.0.1 + * Date : 2024/01/01 + * Description : RISC-V V2 Core Peripheral Access Layer Source File for CH32V00X + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined(__CC_ARM) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined(__ICCARM__) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined(__GNUC__) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined(__TASKING__) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mstatus": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile("csrw mstatus, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""misa" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile("csrw misa, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mtvec": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile("csrw mtvec, %0":: "r"(value)); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mscratch" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile("csrw mscratch, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mepc" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile("csrw mepc, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mcause": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile("csrw mcause, %0":: "r"(value)); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mvendorid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""marchid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mimpid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mhartid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile("mv %0,""sp": "=r"(result):); + return (result); +} diff --git a/system/CH32VM00X/SRC/Core/core_riscv.h b/system/CH32VM00X/SRC/Core/core_riscv.h index 631b628..2b4a9a7 100644 --- a/system/CH32VM00X/SRC/Core/core_riscv.h +++ b/system/CH32VM00X/SRC/Core/core_riscv.h @@ -1,401 +1,401 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : core_riscv.h - * Author : WCH - * Version : V1.0.1 - * Date : 2024/01/01 - * Description : RISC-V V2 Core Peripheral Access Layer Header File for CH32V00X - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CORE_RISCV_H__ -#define __CORE_RISCV_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* IO definitions */ -#ifdef __cplusplus - #define __I volatile /* defines 'read only' permissions */ -#else - #define __I volatile const /* defines 'read only' permissions */ -#endif -#define __O volatile /* defines 'write only' permissions */ -#define __IO volatile /* defines 'read / write' permissions */ - -/* Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef __I uint32_t vuc32; /* Read Only */ -typedef __I uint16_t vuc16; /* Read Only */ -typedef __I uint8_t vuc8; /* Read Only */ - -typedef const uint32_t uc32; /* Read Only */ -typedef const uint16_t uc16; /* Read Only */ -typedef const uint8_t uc8; /* Read Only */ - -typedef __I int32_t vsc32; /* Read Only */ -typedef __I int16_t vsc16; /* Read Only */ -typedef __I int8_t vsc8; /* Read Only */ - -typedef const int32_t sc32; /* Read Only */ -typedef const int16_t sc16; /* Read Only */ -typedef const int8_t sc8; /* Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -#define RV_STATIC_INLINE static inline - -/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ -typedef struct{ - __I uint32_t ISR[8]; - __I uint32_t IPR[8]; - __IO uint32_t ITHRESDR; - __IO uint32_t RESERVED; - __IO uint32_t CFGR; - __I uint32_t GISR; - __IO uint8_t VTFIDR[4]; - uint8_t RESERVED0[12]; - __IO uint32_t VTFADDR[4]; - uint8_t RESERVED1[0x90]; - __O uint32_t IENR[8]; - uint8_t RESERVED2[0x60]; - __O uint32_t IRER[8]; - uint8_t RESERVED3[0x60]; - __O uint32_t IPSR[8]; - uint8_t RESERVED4[0x60]; - __O uint32_t IPRR[8]; - uint8_t RESERVED5[0x60]; - __IO uint32_t IACTR[8]; - uint8_t RESERVED6[0xE0]; - __IO uint8_t IPRIOR[256]; - uint8_t RESERVED7[0x810]; - __IO uint32_t SCTLR; -}PFIC_Type; - -/* memory mapped structure for SysTick */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t SR; - __IO uint32_t CNT; - uint32_t RESERVED0; - __IO uint32_t CMP; - uint32_t RESERVED1; -}SysTick_Type; - - -#define PFIC ((PFIC_Type *) 0xE000E000 ) -#define NVIC PFIC -#define NVIC_KEY1 ((uint32_t)0xFA050000) -#define NVIC_KEY2 ((uint32_t)0xBCAF0000) -#define NVIC_KEY3 ((uint32_t)0xBEEF0000) - -#define SysTick ((SysTick_Type *) 0xE000F000) - - -/********************************************************************* - * @fn __enable_irq - * This function is only used for Machine mode. - * - * @brief Enable Global Interrupt - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() -{ - __asm volatile ("csrs mstatus, %0" : : "r" (0x88) ); -} - -/********************************************************************* - * @fn __disable_irq - * This function is only used for Machine mode. - * - * @brief Disable Global Interrupt - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() -{ - __asm volatile ("csrc mstatus, %0" : : "r" (0x88) ); -} - -/********************************************************************* - * @fn __NOP - * - * @brief nop - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() -{ - __asm volatile ("nop"); -} - -/********************************************************************* - * @fn NVIC_EnableIRQ - * - * @brief Enable Interrupt - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_DisableIRQ - * - * @brief Disable Interrupt - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_GetStatusIRQ - * - * @brief Get Interrupt Enable State - * - * @param IRQn - Interrupt Numbers - * - * @return 1 - Interrupt Pending Enable - * 0 - Interrupt Pending Disable - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_GetPendingIRQ - * - * @brief Get Interrupt Pending State - * - * @param IRQn - Interrupt Numbers - * - * @return 1 - Interrupt Pending Enable - * 0 - Interrupt Pending Disable - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_SetPendingIRQ - * - * @brief Set Interrupt Pending - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_ClearPendingIRQ - * - * @brief Clear Interrupt Pending - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_GetActive - * - * @brief Get Interrupt Active State - * - * @param IRQn - Interrupt Numbers - * - * @return 1 - Interrupt Active - * 0 - Interrupt No Active - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_SetPriority - * - * @brief Set Interrupt Priority - * - * @param IRQn - Interrupt Numbers - * interrupt nesting enable(CSR-0x804 bit1 = 1) - * priority - bit[7] - Preemption Priority - * bit[6] - Sub priority - * bit[5:0] - Reserve - * interrupt nesting disable(CSR-0x804 bit1 = 0) - * priority - bit[7:6] - Sub priority - * bit[5:0] - Reserve - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) -{ - NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; -} - -/********************************************************************* - * @fn __WFI - * - * @brief Wait for Interrupt - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) -{ - NVIC->SCTLR &= ~(1<<3); // wfi - asm volatile ("wfi"); -} - -/********************************************************************* - * @fn _SEV - * - * @brief Set Event - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) -{ - uint32_t t; - - t = NVIC->SCTLR; - NVIC->SCTLR |= (1<<3)|(1<<5); - NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); -} - -/********************************************************************* - * @fn _WFE - * - * @brief Wait for Events - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) -{ - NVIC->SCTLR |= (1<<3); - asm volatile ("wfi"); -} - -/********************************************************************* - * @fn __WFE - * - * @brief Wait for Events - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) -{ - _SEV(); - _WFE(); - _WFE(); -} - -/********************************************************************* - * @fn SetVTFIRQ - * - * @brief Set VTF Interrupt - * - * @param addr - VTF interrupt service function base address. - * IRQn - Interrupt Numbers - * num - VTF Interrupt Numbers - * NewState - DISABLE or ENABLE - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState) -{ - if(num > 1) return ; - - if (NewState != DISABLE) - { - NVIC->VTFIDR[num] = IRQn; - NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); - } - else - { - NVIC->VTFIDR[num] = IRQn; - NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); - } -} - -/********************************************************************* - * @fn NVIC_SystemReset - * - * @brief Initiate a system reset request - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) -{ - NVIC->CFGR = NVIC_KEY3|(1<<7); -} - - -/* Core_Exported_Functions */ -extern uint32_t __get_MSTATUS(void); -extern void __set_MSTATUS(uint32_t value); -extern uint32_t __get_MISA(void); -extern void __set_MISA(uint32_t value); -extern uint32_t __get_MTVEC(void); -extern void __set_MTVEC(uint32_t value); -extern uint32_t __get_MSCRATCH(void); -extern void __set_MSCRATCH(uint32_t value); -extern uint32_t __get_MEPC(void); -extern void __set_MEPC(uint32_t value); -extern uint32_t __get_MCAUSE(void); -extern void __set_MCAUSE(uint32_t value); -extern uint32_t __get_MVENDORID(void); -extern uint32_t __get_MARCHID(void); -extern uint32_t __get_MIMPID(void); -extern uint32_t __get_MHARTID(void); -extern uint32_t __get_SP(void); - -#ifdef __cplusplus -} -#endif - -#endif/* __CORE_RISCV_H__ */ - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.h + * Author : WCH + * Version : V1.0.1 + * Date : 2024/01/01 + * Description : RISC-V V2 Core Peripheral Access Layer Header File for CH32V00X + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint32_t CNT; + uint32_t RESERVED0; + __IO uint32_t CMP; + uint32_t RESERVED1; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000 ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + +#define SysTick ((SysTick_Type *) 0xE000F000) + + +/********************************************************************* + * @fn __enable_irq + * This function is only used for Machine mode. + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrs mstatus, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __disable_irq + * This function is only used for Machine mode. + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrc mstatus, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6] - Sub priority + * bit[5:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:6] - Sub priority + * bit[5:0] - Reserve + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + uint32_t t; + + t = NVIC->SCTLR; + NVIC->SCTLR |= (1<<3)|(1<<5); + NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + NVIC->SCTLR |= (1<<3); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param addr - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState) +{ + if(num > 1) return ; + + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + + +/* Core_Exported_Functions */ +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + +#ifdef __cplusplus +} +#endif + +#endif/* __CORE_RISCV_H__ */ + + + + + diff --git a/system/CH32VM00X/SRC/Debug/debug.c b/system/CH32VM00X/SRC/Debug/debug.c index 25317bd..2c76906 100644 --- a/system/CH32VM00X/SRC/Debug/debug.c +++ b/system/CH32VM00X/SRC/Debug/debug.c @@ -1,367 +1,368 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : debug.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for UART - * Printf , Delay functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -static uint8_t p_us = 0; -static uint16_t p_ms = 0; - -#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE00000F4) -#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE00000F8) - -/********************************************************************* - * @fn Delay_Init - * - * @brief Initializes Delay Funcation. - * - * @return none - */ -void Delay_Init(void) -{ - p_us = SystemCoreClock / 8000000; - p_ms = (uint16_t)p_us * 1000; -} - -/********************************************************************* - * @fn Delay_Us - * - * @brief Microsecond Delay Time. - * - * @param n - Microsecond number. - * - * @return None - */ -void Delay_Us(uint32_t n) -{ - uint32_t i; - - SysTick->SR &= ~(1 << 0); - i = (uint32_t)n * p_us; - - SysTick->CMP = i; - SysTick->CNT = 0; - SysTick->CTLR |=(1 << 0); - - while((SysTick->SR & (1 << 0)) != (1 << 0)); - SysTick->CTLR &= ~(1 << 0); -} - -/********************************************************************* - * @fn Delay_Ms - * - * @brief Millisecond Delay Time. - * - * @param n - Millisecond number. - * - * @return None - */ -void Delay_Ms(uint32_t n) -{ - uint32_t i; - - SysTick->SR &= ~(1 << 0); - i = (uint32_t)n * p_ms; - - SysTick->CMP = i; - SysTick->CNT = 0; - SysTick->CTLR |=(1 << 0); - - while((SysTick->SR & (1 << 0)) != (1 << 0)); - SysTick->CTLR &= ~(1 << 0); -} - -/********************************************************************* - * @fn USART_Printf_Init - * - * @brief Initializes the USARTx peripheral. - * - * @param baudrate - USART communication baud rate. - * - * @return None - */ -void USART_Printf_Init(uint32_t baudrate) -{ - GPIO_InitTypeDef GPIO_InitStructure; - USART_InitTypeDef USART_InitStructure; - -#if (DEBUG == DEBUG_UART1_NoRemap) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOD | RCC_PB2Periph_USART1, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOD, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART1_Remap1) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOD | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_PartialRemap1_USART1, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOD, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART1_Remap2) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOD | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_PartialRemap2_USART1, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOD, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART1_Remap3) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOC | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_PartialRemap3_USART1, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOC, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART1_Remap4) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOD | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_PartialRemap4_USART1, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOD, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART1_Remap5) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOB | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_PartialRemap5_USART1, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOB, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART1_Remap6) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOC | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_PartialRemap6_USART1, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOC, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART1_Remap7) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOB | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_PartialRemap7_USART1, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOB, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART1_Remap8) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_PartialRemap8_USART1, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART2_NoRemap) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_USART2, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART2_Remap1) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_USART2 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_PartialRemap1_USART2, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART2_Remap2) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_USART2 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_PartialRemap2_USART2, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART2_Remap3) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOD | RCC_PB2Periph_USART2 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_PartialRemap3_USART2, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOD, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART2_Remap4) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOB | RCC_PB2Periph_USART2 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_PartialRemap4_USART2, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOB, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART2_Remap5) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOC | RCC_PB2Periph_USART2 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_PartialRemap5_USART2, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOC, &GPIO_InitStructure); - -#elif (DEBUG == DEBUG_UART2_Remap6) - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_USART2 | RCC_PB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_FullRemap_USART2, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - -#endif - - USART_InitStructure.USART_BaudRate = baudrate; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_No; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Tx; - -#if (DEBUG == DEBUG_UART1_NoRemap)||(DEBUG == DEBUG_UART1_Remap1)||(DEBUG == DEBUG_UART1_Remap2)||(DEBUG == DEBUG_UART1_Remap3)||(DEBUG == DEBUG_UART1_Remap4) \ - ||(DEBUG == DEBUG_UART1_Remap5)||(DEBUG == DEBUG_UART1_Remap6)||(DEBUG == DEBUG_UART1_Remap7)||(DEBUG == DEBUG_UART1_Remap8) - USART_Init(USART1, &USART_InitStructure); - USART_Cmd(USART1, ENABLE); -#endif - -#if (DEBUG == DEBUG_UART2_NoRemap)||(DEBUG == DEBUG_UART2_Remap1)||(DEBUG == DEBUG_UART2_Remap2)||(DEBUG == DEBUG_UART2_Remap3) \ - ||(DEBUG == DEBUG_UART2_Remap4)||(DEBUG == DEBUG_UART2_Remap5)||(DEBUG == DEBUG_UART2_Remap6) - USART_Init(USART2, &USART_InitStructure); - USART_Cmd(USART2, ENABLE); -#endif -} - -/********************************************************************* - * @fn SDI_Printf_Enable - * - * @brief Initializes the SDI printf Function. - * - * @param None - * - * @return None - */ -void SDI_Printf_Enable(void) -{ - *(DEBUG_DATA0_ADDRESS) = 0; - Delay_Init(); - Delay_Ms(1); -} - -/********************************************************************* - * @fn _write - * - * @brief Support Printf Function - * - * @param *buf - UART send Data. - * size - Data length. - * - * @return size - Data length - */ -#if 0 -__attribute__((used)) -int _write(int fd, char *buf, int size) -{ - int i = 0; - int writeSize = size; -#if (SDI_PRINT == SDI_PR_OPEN) - do - { - - /** - * data0 data1 8 bytes - * data0 The lowest byte storage length, the maximum is 7 - * - */ - - while( (*(DEBUG_DATA0_ADDRESS) != 0u)) - { - - } - - if(writeSize>7) - { - *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); - *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); - - i += 7; - writeSize -= 7; - } - else - { - *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); - *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); - - writeSize = 0; - } - - } while (writeSize); - -#else - - for(i = 0; i < size; i++){ -#if (DEBUG == DEBUG_UART1_NoRemap)||(DEBUG == DEBUG_UART1_Remap1)||(DEBUG == DEBUG_UART1_Remap2)||(DEBUG == DEBUG_UART1_Remap3)||(DEBUG == DEBUG_UART1_Remap4) \ - ||(DEBUG == DEBUG_UART1_Remap5)||(DEBUG == DEBUG_UART1_Remap6)||(DEBUG == DEBUG_UART1_Remap7)||(DEBUG == DEBUG_UART1_Remap8) - while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); - USART_SendData(USART1, *buf++); -#elif (DEBUG == DEBUG_UART2_NoRemap)||(DEBUG == DEBUG_UART2_Remap1)||(DEBUG == DEBUG_UART2_Remap2)||(DEBUG == DEBUG_UART2_Remap3) \ - ||(DEBUG == DEBUG_UART2_Remap4)||(DEBUG == DEBUG_UART2_Remap5)||(DEBUG == DEBUG_UART2_Remap6) - while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); - USART_SendData(USART2, *buf++); -#endif - } - - -#endif - return writeSize; -} -#endif -/********************************************************************* - * @fn _sbrk - * - * @brief Change the spatial position of data segment. - * - * @return size: Data length - */ -__attribute__((used)) -void *_sbrk(ptrdiff_t incr) -{ - extern char _end[]; - extern char _heap_end[]; - static char *curbrk = _end; - - if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) - return NULL - 1; - - curbrk += incr; - return curbrk - incr; -} - -void _fini() {} -void _init() {} - +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +static uint8_t p_us = 0; +static uint16_t p_ms = 0; + +#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE00000F4) +#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE00000F8) + +/********************************************************************* + * @fn Delay_Init + * + * @brief Initializes Delay Funcation. + * + * @return none + */ +void Delay_Init(void) +{ + p_us = SystemCoreClock / 8000000; + p_ms = (uint16_t)p_us * 1000; +} + +/********************************************************************* + * @fn Delay_Us + * + * @brief Microsecond Delay Time. + * + * @param n - Microsecond number. + * + * @return None + */ +void Delay_Us(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_us; + + SysTick->CMP = i; + SysTick->CNT = 0; + SysTick->CTLR |=(1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn Delay_Ms + * + * @brief Millisecond Delay Time. + * + * @param n - Millisecond number. + * + * @return None + */ +void Delay_Ms(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_ms; + + SysTick->CMP = i; + SysTick->CNT = 0; + SysTick->CTLR |=(1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn USART_Printf_Init + * + * @brief Initializes the USARTx peripheral. + * + * @param baudrate - USART communication baud rate. + * + * @return None + */ +void USART_Printf_Init(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + +#if (DEBUG == DEBUG_UART1_NoRemap) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOD | RCC_PB2Periph_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap1) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOD | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap1_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap2) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOD | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap2_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap3) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOC | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap3_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOC, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap4) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOD | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap4_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap5) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOB | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap5_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap6) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOC | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap6_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOC, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap7) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOB | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap7_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap8) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_USART1 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap8_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART2_NoRemap) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_USART2, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART2_Remap1) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_USART2 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap1_USART2, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART2_Remap2) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_USART2 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap2_USART2, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART2_Remap3) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOD | RCC_PB2Periph_USART2 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap3_USART2, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART2_Remap4) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOB | RCC_PB2Periph_USART2 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap4_USART2, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART2_Remap5) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOC | RCC_PB2Periph_USART2 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap5_USART2, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOC, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART2_Remap6) + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA | RCC_PB2Periph_USART2 | RCC_PB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_FullRemap_USART2, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#endif + + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx; + +#if (DEBUG == DEBUG_UART1_NoRemap)||(DEBUG == DEBUG_UART1_Remap1)||(DEBUG == DEBUG_UART1_Remap2)||(DEBUG == DEBUG_UART1_Remap3)||(DEBUG == DEBUG_UART1_Remap4) \ + ||(DEBUG == DEBUG_UART1_Remap5)||(DEBUG == DEBUG_UART1_Remap6)||(DEBUG == DEBUG_UART1_Remap7)||(DEBUG == DEBUG_UART1_Remap8) + USART_Init(USART1, &USART_InitStructure); + USART_Cmd(USART1, ENABLE); +#endif + +#if (DEBUG == DEBUG_UART2_NoRemap)||(DEBUG == DEBUG_UART2_Remap1)||(DEBUG == DEBUG_UART2_Remap2)||(DEBUG == DEBUG_UART2_Remap3) \ + ||(DEBUG == DEBUG_UART2_Remap4)||(DEBUG == DEBUG_UART2_Remap5)||(DEBUG == DEBUG_UART2_Remap6) + USART_Init(USART2, &USART_InitStructure); + USART_Cmd(USART2, ENABLE); +#endif +} + +/********************************************************************* + * @fn SDI_Printf_Enable + * + * @brief Initializes the SDI printf Function. + * + * @param None + * + * @return None + */ +void SDI_Printf_Enable(void) +{ + *(DEBUG_DATA0_ADDRESS) = 0; + Delay_Init(); + Delay_Ms(1); +} + +/********************************************************************* + * @fn _write + * + * @brief Support Printf Function + * + * @param *buf - UART send Data. + * size - Data length. + * + * @return size - Data length + */ +#if 0 +__attribute__((used)) +int _write(int fd, char *buf, int size) +{ + int i = 0; + int writeSize = size; +#if (SDI_PRINT == SDI_PR_OPEN) + do + { + + /** + * data0 data1 8 bytes + * data0 The lowest byte storage length, the maximum is 7 + * + */ + + while( (*(DEBUG_DATA0_ADDRESS) != 0u)) + { + + } + + if(writeSize>7) + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + i += 7; + writeSize -= 7; + } + else + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + writeSize = 0; + } + + } while (writeSize); + +#else + + for(i = 0; i < size; i++){ +#if (DEBUG == DEBUG_UART1_NoRemap)||(DEBUG == DEBUG_UART1_Remap1)||(DEBUG == DEBUG_UART1_Remap2)||(DEBUG == DEBUG_UART1_Remap3)||(DEBUG == DEBUG_UART1_Remap4) \ + ||(DEBUG == DEBUG_UART1_Remap5)||(DEBUG == DEBUG_UART1_Remap6)||(DEBUG == DEBUG_UART1_Remap7)||(DEBUG == DEBUG_UART1_Remap8) + while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); + USART_SendData(USART1, *buf++); +#elif (DEBUG == DEBUG_UART2_NoRemap)||(DEBUG == DEBUG_UART2_Remap1)||(DEBUG == DEBUG_UART2_Remap2)||(DEBUG == DEBUG_UART2_Remap3) \ + ||(DEBUG == DEBUG_UART2_Remap4)||(DEBUG == DEBUG_UART2_Remap5)||(DEBUG == DEBUG_UART2_Remap6) + while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); + USART_SendData(USART2, *buf++); +#endif + } + + +#endif + return writeSize; +} +#endif + +/********************************************************************* + * @fn _sbrk + * + * @brief Change the spatial position of data segment. + * + * @return size: Data length + */ +__attribute__((used)) +void *_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} + +void _fini() {} +void _init() {} + diff --git a/system/CH32VM00X/SRC/Debug/debug.h b/system/CH32VM00X/SRC/Debug/debug.h index cf84a2d..32a81a0 100644 --- a/system/CH32VM00X/SRC/Debug/debug.h +++ b/system/CH32VM00X/SRC/Debug/debug.h @@ -1,67 +1,67 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : debug.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for UART - * Printf , Delay functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __DEBUG_H -#define __DEBUG_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include -#include - -/* UART Printf Definition */ -#define DEBUG_UART1_NoRemap 1 //Tx-PD5 -#define DEBUG_UART1_Remap1 2 //Tx-PD6 -#define DEBUG_UART1_Remap2 3 //Tx-PD0 -#define DEBUG_UART1_Remap3 4 //Tx-PC0 -#define DEBUG_UART1_Remap4 5 //Tx-PD1 -#define DEBUG_UART1_Remap5 6 //Tx-PB3 -#define DEBUG_UART1_Remap6 7 //Tx-PC5 -#define DEBUG_UART1_Remap7 8 //Tx-PB5 -#define DEBUG_UART1_Remap8 9 //Tx-PA0 - -/* USART2 print function only for V005,V006,V007,M007 series*/ -#if defined(CH32V005) || defined(CH32V006) || defined(CH32V007_M007) -#define DEBUG_UART2_NoRemap 10 //Tx-PA7 -#define DEBUG_UART2_Remap1 11 //Tx-PA4 -#define DEBUG_UART2_Remap2 12 //Tx-PA2 -#define DEBUG_UART2_Remap3 13 //Tx-PD2 -#define DEBUG_UART2_Remap4 14 //Tx-PB0 -#define DEBUG_UART2_Remap5 15 //Tx-PC4 -#define DEBUG_UART2_Remap6 16 //Tx-PA6 -#endif -/* DEBUG UATR Definition */ -#ifndef DEBUG -#define DEBUG DEBUG_UART1_NoRemap -#endif - -/* SDI Printf Definition */ -#define SDI_PR_CLOSE 0 -#define SDI_PR_OPEN 1 - -#ifndef SDI_PRINT -#define SDI_PRINT SDI_PR_CLOSE -#endif - -void Delay_Init(void); -void Delay_Us(uint32_t n); -void Delay_Ms(uint32_t n); -void USART_Printf_Init(uint32_t baudrate); -void SDI_Printf_Enable(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __DEBUG_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __DEBUG_H +#define __DEBUG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include +#include + +/* UART Printf Definition */ +#define DEBUG_UART1_NoRemap 1 //Tx-PD5 +#define DEBUG_UART1_Remap1 2 //Tx-PD6 +#define DEBUG_UART1_Remap2 3 //Tx-PD0 +#define DEBUG_UART1_Remap3 4 //Tx-PC0 +#define DEBUG_UART1_Remap4 5 //Tx-PD1 +#define DEBUG_UART1_Remap5 6 //Tx-PB3 +#define DEBUG_UART1_Remap6 7 //Tx-PC5 +#define DEBUG_UART1_Remap7 8 //Tx-PB5 +#define DEBUG_UART1_Remap8 9 //Tx-PA0 + +/* USART2 print function only for V005,V006,V007,M007 series*/ +#if defined(CH32V005) || defined(CH32V006) || defined(CH32V007_M007) +#define DEBUG_UART2_NoRemap 10 //Tx-PA7 +#define DEBUG_UART2_Remap1 11 //Tx-PA4 +#define DEBUG_UART2_Remap2 12 //Tx-PA2 +#define DEBUG_UART2_Remap3 13 //Tx-PD2 +#define DEBUG_UART2_Remap4 14 //Tx-PB0 +#define DEBUG_UART2_Remap5 15 //Tx-PC4 +#define DEBUG_UART2_Remap6 16 //Tx-PA6 +#endif +/* DEBUG UATR Definition */ +#ifndef DEBUG +#define DEBUG DEBUG_UART1_NoRemap +#endif + +/* SDI Printf Definition */ +#define SDI_PR_CLOSE 0 +#define SDI_PR_OPEN 1 + +#ifndef SDI_PRINT +#define SDI_PRINT SDI_PR_CLOSE +#endif + +void Delay_Init(void); +void Delay_Us(uint32_t n); +void Delay_Ms(uint32_t n); +void USART_Printf_Init(uint32_t baudrate); +void SDI_Printf_Enable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DEBUG_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X.h index 65d279b..1a21257 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X.h @@ -1,2532 +1,2534 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : CH32V00X Device Peripheral Access Layer Header File. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_H -#define __CH32V00X_H - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(CH32V002) && !defined(CH32V005) && !defined(CH32V006)&& !defined(CH32V007_M007) -//#define CH32V002 /* CH32V002*/ -//#define CH32V004 /* CH32V004 */ -//#define CH32V005 /* CH32V005 */ -#define CH32V006 /* CH32V006 */ -//#define CH32V007_M007 /* CH32V007 - CH32M007*/ -#endif - -#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ - -#define HSE_VALUE ((uint32_t)24000000) /* Value of the External oscillator in Hz */ - -/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x2000) /* Time out for HSE start up */ - -#define HSI_VALUE ((uint32_t)24000000) /* Value of the Internal oscillator in Hz */ - -/* CH32V00X Standard Peripheral Library version number */ -#define __CH32V00X_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ -#define __CH32V00X_STDPERIPH_VERSION_SUB (0x00) /* [7:0] sub version */ -#define __CH32V00X_STDPERIPH_VERSION ( (__CH32V00X_STDPERIPH_VERSION_MAIN << 8)\ - |(__CH32V00X_STDPERIPH_VERSION_SUB << 0)) - -/* Interrupt Number Definition, according to the selected device */ -typedef enum IRQn -{ - /****** RISC-V Processor Exceptions Numbers *******************************************************/ - NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = 3, /* 3 HardFault Interrupt */ - SysTicK_IRQn = 12, /* 12 System timer Interrupt */ - Software_IRQn = 14, /* 14 software Interrupt */ - - /****** RISC-V specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 16, /* Window WatchDog Interrupt */ - PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ - FLASH_IRQn = 18, /* FLASH global Interrupt */ - RCC_IRQn = 19, /* RCC global Interrupt */ - EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ - AWU_IRQn = 21, /* AWU global Interrupt */ - DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ - ADC_IRQn = 29, /* ADC global Interrupt */ - I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ - I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ - USART1_IRQn = 32, /* USART1 global Interrupt */ - SPI1_IRQn = 33, /* SPI1 global Interrupt */ - TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ - TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 38, /* TIM2 global Interrupt */ - -#if defined(CH32V005) || defined(CH32V006) || defined(CH32V007_M007) - USART2_IRQn = 39, /* USART2 global Interrupt */ - OPCM_IRQn = 40, /* OPCM global Interrupt */ -#endif -} IRQn_Type; - -#include -#include -#include - -/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSI_Value HSI_VALUE -#define HSE_Value HSE_VALUE -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT - -/* Analog to Digital Converter */ -typedef struct -{ - __IO uint32_t STATR; - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t SAMPTR1; - __IO uint32_t SAMPTR2; - __IO uint32_t IOFR1; - __IO uint32_t IOFR2; - __IO uint32_t IOFR3; - __IO uint32_t IOFR4; - __IO uint32_t WDHTR; - __IO uint32_t WDLTR; - __IO uint32_t RSQR1; - __IO uint32_t RSQR2; - __IO uint32_t RSQR3; - __IO uint32_t ISQR; - __IO uint32_t IDATAR1; - __IO uint32_t IDATAR2; - __IO uint32_t IDATAR3; - __IO uint32_t IDATAR4; - __IO uint32_t RDATAR; - __IO uint32_t CTLR3; - __IO uint32_t WDTR1; - __IO uint32_t WDTR2; -} ADC_TypeDef; - -/* DMA Controller */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t CNTR; - __IO uint32_t PADDR; - __IO uint32_t MADDR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t INTFR; - __IO uint32_t INTFCR; -} DMA_TypeDef; - -/* External Interrupt/Event Controller */ -typedef struct -{ - __IO uint32_t INTENR; - __IO uint32_t EVENR; - __IO uint32_t RTENR; - __IO uint32_t FTENR; - __IO uint32_t SWIEVR; - __IO uint32_t INTFR; -} EXTI_TypeDef; - -/* FLASH Registers */ -typedef struct -{ - __IO uint32_t ACTLR; - __IO uint32_t KEYR; - __IO uint32_t OBKEYR; - __IO uint32_t STATR; - __IO uint32_t CTLR; - __IO uint32_t ADDR; - uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WPR; - __IO uint32_t MODEKEYR; - __IO uint32_t BOOT_MODEKEYR; -} FLASH_TypeDef; - -/* Option Bytes Registers */ -typedef struct -{ - __IO uint16_t RDPR; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRPR0; - __IO uint16_t WRPR1; - __IO uint16_t WRPR2; - __IO uint16_t WRPR3; -} OB_TypeDef; - -/* General Purpose I/O */ -typedef struct -{ - __IO uint32_t CFGLR; - uint32_t RESERVED; - __IO uint32_t INDR; - __IO uint32_t OUTDR; - __IO uint32_t BSHR; - __IO uint32_t BCR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/* Alternate Function I/O */ -typedef struct -{ - uint32_t RESERVED0; - uint32_t RESERVED1; - __IO uint32_t EXTICR; - __IO uint32_t PCFR1; -} AFIO_TypeDef; - -/* Inter-Integrated Circuit Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t OADDR1; - uint16_t RESERVED2; - __IO uint16_t OADDR2; - uint16_t RESERVED3; - __IO uint16_t DATAR; - uint16_t RESERVED4; - __IO uint16_t STAR1; - uint16_t RESERVED5; - __IO uint16_t STAR2; - uint16_t RESERVED6; - __IO uint16_t CKCFGR; - uint16_t RESERVED7; -} I2C_TypeDef; - -/* Independent WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t PSCR; - __IO uint32_t RLDR; - __IO uint32_t STATR; -} IWDG_TypeDef; - -/* Power Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CSR; - __IO uint32_t AWUCSR; - __IO uint32_t AWUWR; - __IO uint32_t AWUPSC; -} PWR_TypeDef; - -/* Reset and Clock Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR0; - __IO uint32_t INTR; - __IO uint32_t PB2PRSTR; - __IO uint32_t PB1PRSTR; - __IO uint32_t HBPCENR; - __IO uint32_t PB2PCENR; - __IO uint32_t PB1PCENR; - uint32_t RESERVED0; - __IO uint32_t RSTSCKR; -} RCC_TypeDef; - -/* Serial Peripheral Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t STATR; - uint16_t RESERVED2; - __IO uint16_t DATAR; - uint16_t RESERVED3; - __IO uint16_t CRCR; - uint16_t RESERVED4; - __IO uint16_t RCRCR; - uint16_t RESERVED5; - __IO uint16_t TCRCR; - uint16_t RESERVED6; - uint32_t RESERVED7; - uint32_t RESERVED8; - __IO uint16_t HSCR; - uint16_t RESERVED9; -} SPI_TypeDef; - -/* TIM */ -typedef struct -{ - union - { - __IO uint16_t CTLR1; - __IO uint16_t TIM3_CTLR; - }; - uint16_t RESERVED0; - union - { - __IO uint16_t CTLR2; - __IO uint16_t TIM3_DMAINTENR; - }; - uint16_t RESERVED1; - union - { - __IO uint16_t SMCFGR; - __IO uint16_t TIM3_CNT; - }; - uint16_t RESERVED2; - union - { - __IO uint16_t DMAINTENR; - __IO uint16_t TIM3_ATRLR; - }; - uint16_t RESERVED3; - union - { - __IO uint16_t INTFR; - __IO uint16_t TIM3_CH1CVR; - }; - uint16_t RESERVED4; - union - { - __IO uint16_t SWEVGR; - __IO uint16_t TIM3_CH2CVR; - }; - uint16_t RESERVED5; - union - { - __IO uint16_t CHCTLR1; - __IO uint16_t TIM3_CH3CVR; - }; - uint16_t RESERVED6; - union - { - __IO uint16_t CHCTLR2; - __IO uint16_t TIM3_CH4CVR; - }; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ATRLR; - uint16_t RESERVED11; - __IO uint16_t RPTCR; - uint16_t RESERVED12; - __IO uint32_t CH1CVR; - __IO uint32_t CH2CVR; - __IO uint32_t CH3CVR; - __IO uint32_t CH4CVR; - union - { - __IO uint16_t BDTR; - __IO uint16_t TIM2_DTCR; - }; - uint16_t RESERVED13; - __IO uint16_t DMACFGR; - uint16_t RESERVED14; - __IO uint16_t DMAADR; - uint16_t RESERVED15; -} TIM_TypeDef; - -/* Universal Synchronous Asynchronous Receiver Transmitter */ -typedef struct -{ - __IO uint16_t STATR; - uint16_t RESERVED0; - __IO uint16_t DATAR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CTLR1; - uint16_t RESERVED3; - __IO uint16_t CTLR2; - uint16_t RESERVED4; - __IO uint16_t CTLR3; - uint16_t RESERVED5; - __IO uint16_t GPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/* Window WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR; - __IO uint32_t STATR; -} WWDG_TypeDef; - -/* Enhanced Registers */ -typedef struct -{ - __IO uint32_t EXTEN_CTR; -} EXTEN_TypeDef; - -/* OPA Registers */ -typedef struct -{ - __IO uint32_t CFGR1; - __IO uint32_t CTLR1; - __IO uint32_t CFGR2; - __IO uint32_t CTLR2; - __IO uint32_t OPAKEY; - __IO uint32_t CMPKEY; - __IO uint32_t POLLKEY; -} OPA_TypeDef; - -/* Peripheral memory map */ -#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ - -#define PB1PERIPH_BASE (PERIPH_BASE) -#define PB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define HBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (PB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (PB1PERIPH_BASE + 0x0800) -#define WWDG_BASE (PB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (PB1PERIPH_BASE + 0x3000) -#define USART2_BASE (PB1PERIPH_BASE + 0x4400) -#define I2C1_BASE (PB1PERIPH_BASE + 0x5400) -#define PWR_BASE (PB1PERIPH_BASE + 0x7000) - -#define AFIO_BASE (PB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (PB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (PB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (PB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (PB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (PB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (PB2PERIPH_BASE + 0x2400) -#define TIM1_BASE (PB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (PB2PERIPH_BASE + 0x3000) -#define USART1_BASE (PB2PERIPH_BASE + 0x3800) - -#define DMA1_BASE (HBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (HBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (HBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (HBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (HBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (HBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (HBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (HBPERIPH_BASE + 0x0080) -#define RCC_BASE (HBPERIPH_BASE + 0x1000) -#define FLASH_R_BASE (HBPERIPH_BASE + 0x2000) -#define EXTEN_BASE (HBPERIPH_BASE + 0x3800) -#define OPA_BASE (HBPERIPH_BASE + 0x4000) - -#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ - -/* Peripheral declaration */ -#define TIM2 ((TIM_TypeDef *)TIM2_BASE) -#define WWDG ((WWDG_TypeDef *)WWDG_BASE) -#define IWDG ((IWDG_TypeDef *)IWDG_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define PWR ((PWR_TypeDef *)PWR_BASE) -#define AFIO ((AFIO_TypeDef *)AFIO_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#define TIM1 ((TIM_TypeDef *)TIM1_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#define RCC ((RCC_TypeDef *)RCC_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#define OB ((OB_TypeDef *)OB_BASE) -#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) - -#define USART2 ((USART_TypeDef *)USART2_BASE) -#define OPA ((OPA_TypeDef *)OPA_BASE) -#define TIM3 ((TIM_TypeDef *)TIM3_BASE) -#define TKey1 ((ADC_TypeDef *)ADC1_BASE) - -/******************************************************************************/ -/* Peripheral Registers Bits Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* Analog to Digital Converter */ -/******************************************************************************/ - -/******************** Bit definition for ADC_STATR register ********************/ -#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ -#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ -#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ -#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ -#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ - -/******************* Bit definition for ADC_CTLR1 register ********************/ -#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ -#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ -#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ -#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ -#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ -#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ -#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ -#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ - -#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ -#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ - -#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ -#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ - -#define ADC_TKENABLE ((uint32_t)0x01000000) /* Analog watchdog enable on injected channels */ -#define ADC_TKITUNE ((uint32_t)0x02000000) /* Analog watchdog enable on injected channels */ -#define ADC_BUFEN ((uint32_t)0x04000000) /* Analog watchdog enable on injected channels */ - -/******************* Bit definition for ADC_CTLR2 register ********************/ -#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ -#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ -#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ -#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ -#define ADC_TGREGU ((uint32_t)0x00000010) /*External Trigger Events for Rule Channel Conversion*/ -#define ADC_TGINJE ((uint32_t)0x00000020) /*Injection of externally triggered events for channel conversions*/ - -#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ -#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ - -#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ - -#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ -#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ -#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ - -#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ -#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ -#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ - -/****************** Bit definition for ADC_SAMPTR1 register *******************/ -#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ - -/****************** Bit definition for ADC_SAMPTR2 register *******************/ -#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ - -#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ -#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ -#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ - -/****************** Bit definition for ADC_IOFR1 register *******************/ -#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_IOFR2 register *******************/ -#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_IOFR3 register *******************/ -#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_IOFR4 register *******************/ -#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_WDHTR register ********************/ -#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ - -/******************* Bit definition for ADC_WDLTR register ********************/ -#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ - -/******************* Bit definition for ADC_RSQR1 register *******************/ -#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ -#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ - -/******************* Bit definition for ADC_RSQR2 register *******************/ -#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_RSQR3 register *******************/ -#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_ISQR register *******************/ -#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ -#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ - -/******************* Bit definition for ADC_IDATAR1 register *******************/ -#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR2 register *******************/ -#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR3 register *******************/ -#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR4 register *******************/ -#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************** Bit definition for ADC_RDATAR register ********************/ -#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ - -/******************** Bit definition for ADC_CTLR3 register ********************/ -#define ADC_LP ((uint32_t)0x00000001) /* ADC Low Power Mode Selection */ -#define ADC_DUTYEN ((uint32_t)0x00000002) /* ADC clock duty cycle control */ -#define ADC_DRVEN ((uint32_t)0x00000004) /* Touchkey multi mask enable */ -#define ADC_AWD_SCAN ((uint32_t)0x00000008) /*Analog watchdog scan enable*/ -#define ADC_AWD0_RST_EN ((uint32_t)0x00000010) /*Analog watchdog 0 output reset enable*/ -#define ADC_AWD1_RST_EN ((uint32_t)0x00000020) /*Analog watchdog 1 output reset enable*/ -#define ADC_AWD2_RST_EN ((uint32_t)0x00000040) /*Analog watchdog 2 output reset enable*/ - -#define ADC_AWD0_RES ((uint32_t)0x00000100) /*Analog Watchdog 0 Comparison Result*/ -#define ADC_AWD1_RES ((uint32_t)0x00000200) /*Analog Watchdog 1 Comparison Result*/ -#define ADC_AWD2_RES ((uint32_t)0x00000400) /*Analog Watchdog 2 Comparison Result*/ - -#define ADC_DRV_OUTEN ((uint32_t)0x00FF0000) /*Touchkey multi mask enable for each channel*/ - -/******************** Bit definition for ADC_WDTR1 register ********************/ -#define ADC_WDTR1_LTR1 ((uint32_t)0x00000FFF) /*Analog Watchdog Low Threshold Setting Value*/ -#define ADC_WDTR1_HTR1 ((uint32_t)0x0FFF0000) /*Analog Watchdog High Threshold Setting Value*/ - -/******************** Bit definition for ADC_WDTR2 register ********************/ -#define ADC_WDTR2_LTR2 ((uint32_t)0x00000FFF) /*Analog Watchdog Low Threshold Setting Value*/ -#define ADC_WDTR2_HTR2 ((uint32_t)0x0FFF0000) /*Analog Watchdog High Threshold Setting Value*/ - -/******************************************************************************/ -/* DMA Controller */ -/******************************************************************************/ - -/******************* Bit definition for DMA_INTFR register ********************/ -#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ -#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ -#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ -#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ -#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ -#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ -#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ -#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ -#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ -#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ -#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ -#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ -#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ -#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ -#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ -#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ -#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ -#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ -#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ -#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ -#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ -#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ -#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ -#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ -#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ -#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ -#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ -#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_INTFCR register *******************/ -#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ -#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ -#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ -#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ -#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ -#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ -#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ -#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ -#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ -#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ -#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ -#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ -#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ -#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ -#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ -#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ -#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ -#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ -#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ -#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ -#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ -#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ -#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ -#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ -#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ -#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ -#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ -#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CFGR1 register *******************/ -#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ -#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ -#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR2 register *******************/ -#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR3 register *******************/ -#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG4 register *******************/ -#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/****************** Bit definition for DMA_CFG5 register *******************/ -#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/******************* Bit definition for DMA_CFG6 register *******************/ -#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG7 register *******************/ -#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/****************** Bit definition for DMA_CNTR1 register ******************/ -#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR2 register ******************/ -#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR3 register ******************/ -#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR4 register ******************/ -#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR5 register ******************/ -#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR6 register ******************/ -#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR7 register ******************/ -#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_PADDR1 register *******************/ -#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR2 register *******************/ -#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR3 register *******************/ -#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR4 register *******************/ -#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR5 register *******************/ -#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR6 register *******************/ -#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR7 register *******************/ -#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_MADDR1 register *******************/ -#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR2 register *******************/ -#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR3 register *******************/ -#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR4 register *******************/ -#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR5 register *******************/ -#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR6 register *******************/ -#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR7 register *******************/ -#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/******************************************************************************/ -/* External Interrupt/Event Controller */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_INTENR register *******************/ -#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ -#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ -#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ -#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ -#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ -#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ -#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ -#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ -#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ -#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ - -/******************* Bit definition for EXTI_EVENR register *******************/ -#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ -#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ -#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ -#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ -#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ -#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ -#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ -#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ -#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ -#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ - -/****************** Bit definition for EXTI_RTENR register *******************/ -#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ -#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ -#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ -#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ -#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ -#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ -#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ -#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ -#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ -#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ - -/****************** Bit definition for EXTI_FTENR register *******************/ -#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ -#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ -#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ -#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ -#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ -#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ -#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ -#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ -#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ -#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ - -/****************** Bit definition for EXTI_SWIEVR register ******************/ -#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ -#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ -#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ -#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ -#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ -#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ -#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ -#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ -#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ -#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ - -/******************* Bit definition for EXTI_INTFR register ********************/ -#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ -#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ -#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ -#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ -#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ -#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ -#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ -#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ -#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ -#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ - -/******************************************************************************/ -/* FLASH and Option Bytes Registers */ -/******************************************************************************/ - -/******************* Bit definition for FLASH_ACTLR register ******************/ -#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ -#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ - -/***************** Bit definition for FLASH_OBKEYR register ****************/ -#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ - -/****************** Bit definition for FLASH_STATR register *******************/ -#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ - -#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ -#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ -#define FLASH_STATR_FWAKE_FLAG ((uint8_t)0x40) /* Flag of wake */ -#define FLASH_STATR_TURBO ((uint8_t)0x80) /* The state of TURBO Enable */ -#define FLASH_STATR_BOOT_AVA ((uint16_t)0x1000) /* The state of Init Config */ -#define FLASH_STATR_BOOT_STATUS ((uint16_t)0x2000) /* The source of Execute Program */ -#define FLASH_STATR_BOOT_MODE ((uint16_t)0x4000) /* The switch of user section or boot section*/ -#define FLASH_STATR_BOOT_LOCK ((uint16_t)0x8000) /* Lock boot area*/ - -/******************* Bit definition for FLASH_CTLR register *******************/ -#define FLASH_CTLR_PER ((uint16_t)0x0002) /* Page Erase 1KByte*/ -#define FLASH_CTLR_MER ((uint16_t)0x0004) /* Mass Erase */ -#define FLASH_CTLR_OPTPG ((uint16_t)0x0010) /* Option Byte Programming */ -#define FLASH_CTLR_OPTER ((uint16_t)0x0020) /* Option Byte Erase */ -#define FLASH_CTLR_STRT ((uint16_t)0x0040) /* Start */ -#define FLASH_CTLR_LOCK ((uint16_t)0x0080) /* Lock */ -#define FLASH_CTLR_OPTWRE ((uint16_t)0x0200) /* Option Bytes Write Enable */ -#define FLASH_CTLR_ERRIE ((uint16_t)0x0400) /* Error Interrupt Enable */ -#define FLASH_CTLR_EOPIE ((uint16_t)0x1000) /* End of operation interrupt enable */ -#define FLASH_CTLR_FLOCK ((uint16_t)0x8000) /* Fast Lock */ -#define FLASH_CTLR_PAGE_PG ((uint16_t)0x00010000) /* Page Programming 256Byte */ -#define FLASH_CTLR_PAGE_ER ((uint16_t)0x00020000) /* Page Erase 256Byte */ -#define FLASH_CTLR_BUF_LOAD ((uint16_t)0x00040000) /* Buffer Load */ -#define FLASH_CTLR_BUF_RST ((uint16_t)0x00080000) /* Buffer Reset */ -#define FLASH_CTLR_BER32 ((uint32_t)0x00800000) /* Block Erase 32K */ - -/******************* Bit definition for FLASH_ADDR register *******************/ -#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ - -#define FLASH_OBR_USER ((uint16_t)0x00F4) /* User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ -#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ -#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */ -#define FLASH_OBR_STATR_MODE ((uint16_t)0x0080) /* RST_MODE */ - -#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) /* Data byte0 */ -#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) /* Data byte1 */ - -/****************** Bit definition for FLASH_WPR register ******************/ -#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ - -/****************** Bit definition for FLASH_MODEKEYR register ******************/ -#define FLASH_MODEKEYR_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open fast program /erase */ -#define FLASH_MODEKEYR_MODEKEYR1 ((uint32_t)0x45670123) -#define FLASH_MODEKEYR_MODEKEYR2 ((uint32_t)0xCDEF89AB) - -/****************** Bit definition for BOOT_MODEKEYP register ******************/ -#define BOOT_MODEKEYP_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open Boot section */ -#define BOOT_MODEKEYP_MODEKEYR1 ((uint32_t)0x45670123) -#define BOOT_MODEKEYP_MODEKEYR2 ((uint32_t)0xCDEF89AB) - -/****************** Bit definition for FLASH_RDPR register *******************/ -#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ -#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_WRPR0 register ******************/ -#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR1 register ******************/ -#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ - -/******************************************************************************/ -/* General Purpose and Alternate Function I/O */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CFGLR register *******************/ -#define GPIO_CFGLR_MODE ((uint32_t)0x11111111) /* Port x mode bits */ - -#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000001) /* MODE0 bits (Port x mode bits, pin 0) */ -#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000000) -#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000001) - -#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000010) /* MODE1 bits (Port x mode bits, pin 1) */ -#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000000) -#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000010) - -#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000100) /* MODE2 bits (Port x mode bits, pin 2) */ -#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000000) -#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000100) - -#define GPIO_CFGLR_MODE3 ((uint32_t)0x00001000) /* MODE3 bits (Port x mode bits, pin 3) */ -#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00000000) -#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00001000) - -#define GPIO_CFGLR_MODE4 ((uint32_t)0x00010000) /* MODE4 bits (Port x mode bits, pin 4) */ -#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00000000) -#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00010000) - -#define GPIO_CFGLR_MODE5 ((uint32_t)0x00100000) /* MODE5 bits (Port x mode bits, pin 5) */ -#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00000000) -#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00100000) - -#define GPIO_CFGLR_MODE6 ((uint32_t)0x01000000) /* MODE6 bits (Port x mode bits, pin 6) */ -#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) -#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x01000000) - -#define GPIO_CFGLR_MODE7 ((uint32_t)0x10000000) /* MODE7 bits (Port x mode bits, pin 7) */ -#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x00000000) -#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x10000000) - -#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_INDR register *******************/ -#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ -#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ -#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ -#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ -#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ -#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ -#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ -#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ - -/******************* Bit definition for GPIO_OUTDR register *******************/ -#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ -#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ -#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ -#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ -#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ -#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ -#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ -#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ - -/****************** Bit definition for GPIO_BSHR register *******************/ -#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ -#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ -#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ -#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ -#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ -#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ -#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ -#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ - -#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ -#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ -#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ -#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ -#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ -#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ -#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ -#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ - -/******************* Bit definition for GPIO_BCR register *******************/ -#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ -#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ -#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ -#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ -#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ -#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ -#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ -#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ -#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ -#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ -#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ -#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ -#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ -#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ -#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ - -#define GPIO_LCKK ((uint32_t)0x00000100) /* Lock key */ - -/****************** Bit definition for AFIO_PCFR1register *******************/ -#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000007) /* SPI1_RM [2:0] bits (SPI1_REMAP configuration) */ -#define AFIO_PCFR1_SPI1_REMAP_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define AFIO_PCFR1_SPI1_REMAP_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define AFIO_PCFR1_SPI1_REMAP_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000038) /* I2C1_RM [2:0] bits (I2C1_REMAP configuration) */ -#define AFIO_PCFR1_I2C1_REMAP_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define AFIO_PCFR1_I2C1_REMAP_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define AFIO_PCFR1_I2C1_REMAP_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x000003C0) /* USART1_RM [3:0] bits (USART1_REMAP configuration) */ -#define AFIO_PCFR1_USART1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define AFIO_PCFR1_USART1_REMAP_2 ((uint32_t)0x00000100) /* Bit 2 */ -#define AFIO_PCFR1_USART1_REMAP_3 ((uint32_t)0x00000200) /* Bit 3 */ - -#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x00003C00) /* TIM1_RM [3:0] bits (TIM1_REMAP configuration) */ -#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define AFIO_PCFR1_TIM1_REMAP_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define AFIO_PCFR1_TIM1_REMAP_3 ((uint32_t)0x00002000) /* Bit 3 */ - -#define AFIO_PCFR1_TIM1_1_REMAP ((uint32_t)0x00003000) /* TIM1 1 remapping (Timer 1 channel 1 selection) */ - -#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x0001C000) /* TIM2_RM [2:0] bits (TIM2_REMAP configuration) */ -#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00008000) /* Bit 1 */ -#define AFIO_PCFR1_TIM2_REMAP_2 ((uint32_t)0x00010000) /* Bit 2 */ - -#define AFIO_PCFR1_PA1PA2_REMAP ((uint32_t)0x00020000) /* Port A0/Port A1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCFR1_ADC_ETRGINJ_REMAP ((uint32_t)0x00040000) /* Remap bit for ADC externally triggered injection conversion */ -#define AFIO_PCFR1_ADC_ETRGREG_REMAP ((uint32_t)0x00080000) /* Remap bits for ADC externally triggered rule conversion */ - -#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00700000) /* USART2_RM [2:0] bits (USART2_REMAP configuration) */ -#define AFIO_PCFR1_USART2_REMAP_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define AFIO_PCFR1_USART2_REMAP_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define AFIO_PCFR1_USART2_REMAP_2 ((uint32_t)0x00400000) /* Bit 2 */ - -#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x0003) /* EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x000C) /* EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0030) /* EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0x00C0) /* EXTI 3 configuration */ -#define AFIO_EXTICR1_EXTI4 ((uint16_t)0x0300) /* EXTI 4 configuration */ -#define AFIO_EXTICR1_EXTI5 ((uint16_t)0x0C00) /* EXTI 5 configuration */ -#define AFIO_EXTICR1_EXTI6 ((uint16_t)0x3000) /* EXTI 6 configuration */ -#define AFIO_EXTICR1_EXTI7 ((uint16_t)0xC000) /* EXTI 7 configuration */ - -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ - -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0004) /* PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0008) /* PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x000C) /* PD[1] pin */ - -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0010) /* PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0020) /* PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0030) /* PD[2] pin */ - -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x0040) /* PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x0080) /* PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x00C0) /* PD[3] pin */ - -#define AFIO_EXTICR1_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ -#define AFIO_EXTICR1_EXTI4_PB ((uint16_t)0x0100) /* PB[4] pin */ -#define AFIO_EXTICR1_EXTI4_PC ((uint16_t)0x0200) /* PC[4] pin */ -#define AFIO_EXTICR1_EXTI4_PD ((uint16_t)0x0300) /* PD[4] pin */ - -#define AFIO_EXTICR1_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ -#define AFIO_EXTICR1_EXTI5_PB ((uint16_t)0x0400) /* PB[5] pin */ -#define AFIO_EXTICR1_EXTI5_PC ((uint16_t)0x0800) /* PC[5] pin */ -#define AFIO_EXTICR1_EXTI5_PD ((uint16_t)0x0C00) /* PD[5] pin */ - -#define AFIO_EXTICR1_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ -#define AFIO_EXTICR1_EXTI6_PB ((uint16_t)0x1000) /* PB[6] pin */ -#define AFIO_EXTICR1_EXTI6_PC ((uint16_t)0x2000) /* PC[6] pin */ -#define AFIO_EXTICR1_EXTI6_PD ((uint16_t)0x3000) /* PD[6] pin */ - -#define AFIO_EXTICR1_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ -#define AFIO_EXTICR1_EXTI7_PB ((uint16_t)0x4000) /* PB[7] pin */ -#define AFIO_EXTICR1_EXTI7_PC ((uint16_t)0x8000) /* PC[7] pin */ -#define AFIO_EXTICR1_EXTI7_PD ((uint16_t)0xC000) /* PD[7] pin */ - -/******************************************************************************/ -/* Independent WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_CTLR register ********************/ -#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PSCR register ********************/ -#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ -#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ -#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ -#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ - -/******************* Bit definition for IWDG_RLDR register *******************/ -#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ - -/******************* Bit definition for IWDG_STATR register ********************/ -#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ -#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ - -/******************************************************************************/ -/* Inter-integrated Circuit Interface */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CTLR1 register ********************/ -#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ - -#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ -#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ -#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ -#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ -#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ -#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ -#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ -#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ - -#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ - -/******************* Bit definition for I2C_CTLR2 register ********************/ -#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ - -#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ -#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ -#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ -#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ -#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ - -/******************* Bit definition for I2C_OADDR1 register *******************/ -#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ -#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ - -#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ -#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ -#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ -#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ -#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ - -#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OADDR2 register *******************/ -#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ -#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ - -/******************** Bit definition for I2C_DATAR register ********************/ -#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ - -/******************* Bit definition for I2C_STAR1 register ********************/ -#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ -#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ -#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ -#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ -#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ -#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ -#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ -#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ -#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ -#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ -#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ -#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ - -/******************* Bit definition for I2C_STAR2 register ********************/ -#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ -#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ -#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ -#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ - -#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ -#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ - -/******************* Bit definition for I2C_CKCFGR register ********************/ -#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ -#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ - -/******************************************************************************/ -/* Power Control */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CTLR register ********************/ -#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ - -#define PWR_CTLR_LDO_MODE ((uint16_t)0x000C) /* LDO_MODE[1:0] bits (Voltage regulator working mode selection) */ -#define PWR_CTLR_LDO_MODE_0 ((uint16_t)0x0004) /* Bit 0 */ -#define PWR_CTLR_LDO_MODE_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define PWR_CTLR_LDO_MODE_NORMAL ((uint16_t)0x0008) /* LDO normal mode*/ -#define PWR_CTLR_LDO_MODE_ENERGYSAVE ((uint16_t)0x000C) /* LDO energy saving mode */ -#define PWR_CTLR_LDO_MODE_LOWPOWER ((uint16_t)0x0004) /* LDO low power mode*/ - -#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ - -#define PWR_CTLR_PLS ((uint16_t)0x0060) /* PLS[1:0] bits (PVD Level Selection) */ -#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ - -#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) /* PVD level 0 */ -#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) /* PVD level 1 */ -#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) /* PVD level 2 */ -#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) /* PVD level 3 */ - -#define PWR_CTLR_FLASH_LP_REG ((uint16_t)0x0200) /* Configure FLASH to enter low-power mode */ - -#define PWR_CTLR_FLASH_LP ((uint16_t)0x0C00) /* FLASH_LP[1:0] bits (Flash Status Selection) */ -#define PWR_CTLR_FLASH_LP_0 ((uint16_t)0x0000) /* free time */ -#define PWR_CTLR_FLASH_LP_1 ((uint16_t)0x0400) /* sleep state */ - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ - -/******************* Bit definition for PWR_AWUCSR register ********************/ -#define PWR_AWUEN ((uint16_t)0x0002) - -/******************* Bit definition for PWR_AWUWR register ********************/ -#define PWR_AWUWR ((uint16_t)0x003F) /* PWR_AWUWR[5:0] bits*/ -#define PWR_AWUWR_0 ((uint16_t)0x0001) /* Bit 0 */ -#define PWR_AWUWR_1 ((uint16_t)0x0002) /* Bit 1 */ -#define PWR_AWUWR_2 ((uint16_t)0x0004) /* Bit 2 */ -#define PWR_AWUWR_3 ((uint16_t)0x0008) /* Bit 3 */ -#define PWR_AWUWR_4 ((uint16_t)0x0010) /* Bit 4 */ -#define PWR_AWUWR_5 ((uint16_t)0x0020) /* Bit 5 */ - -/******************* Bit definition for PWR_AWUPSC register ********************/ -#define PWR_AWUPSC ((uint16_t)0x000F) /* PWR_AWUPSC[3:0]*/ -#define PWR_AWUPSC_0 ((uint16_t)0x0001) /* Bit 0 */ -#define PWR_AWUPSC_1 ((uint16_t)0x0002) /* Bit 1 */ -#define PWR_AWUPSC_2 ((uint16_t)0x0004) /* Bit 2 */ -#define PWR_AWUPSC_3 ((uint16_t)0x0008) /* Bit 3 */ - -/******************************************************************************/ -/* Reset and Clock Control */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CTLR register ********************/ -#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ -#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ -#define RCC_HSILP ((uint32_t)0x00000004) /* HSI Low Power Mode Enabled */ -#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ -#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ -#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ -#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ -#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ -#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ -#define RCC_HSE_LP ((uint32_t)0x00100000) /* Internal High Speed clock enable */ -#define RCC_SYSCM_EN ((uint32_t)0x00200000) /* Internal High Speed clock enable */ - -#define RCC_HSE_SI ((uint32_t)0x00C00000) /* HSE_SI[1:0] bits (HSE current supply adjustment bit) */ -#define RCC_HSE_SI_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define RCC_HSE_SI_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ -#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ - -/******************* Bit definition for RCC_CFGR0 register *******************/ -#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ -#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ -#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ -#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ - -#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ -#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ -#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ - -#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (HB prescaler) */ -#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ -#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ - -#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ -#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ -#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ -#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ -#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ -#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ -#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ -#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ -#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ -#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ -#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ -#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ -#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ - -#define RCC_ADCPRE ((uint32_t)0x0000F800) /* ADCPRE[4:0] bits (ADC prescaler) */ -#define RCC_ADCPRE_0 ((uint32_t)0x00000800) /* Bit 0 */ -#define RCC_ADCPRE_1 ((uint32_t)0x00001000) /* Bit 1 */ -#define RCC_ADCPRE_2 ((uint32_t)0x00002000) /* Bit 2 */ -#define RCC_ADCPRE_3 ((uint32_t)0x00004000) /* Bit 3 */ -#define RCC_ADCPRE_4 ((uint32_t)0x00008000) /* Bit 4 */ - -#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ -#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ -#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ -#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ -#define RCC_ADCPRE_DIV12 ((uint32_t)0x0000A000) /* PCLK2 divided by 12 */ -#define RCC_ADCPRE_DIV16 ((uint32_t)0x0000E000) /* PCLK2 divided by 16 */ -#define RCC_ADCPRE_DIV24 ((uint32_t)0x0000A800) /* PCLK2 divided by 24 */ -#define RCC_ADCPRE_DIV32 ((uint32_t)0x0000E800) /* PCLK2 divided by 32 */ -#define RCC_ADCPRE_DIV48 ((uint32_t)0x0000B000) /* PCLK2 divided by 48 */ -#define RCC_ADCPRE_DIV64 ((uint32_t)0x0000F000) /* PCLK2 divided by 64 */ -#define RCC_ADCPRE_DIV96 ((uint32_t)0x0000B800) /* PCLK2 divided by 96 */ -#define RCC_ADCPRE_DIV128 ((uint32_t)0x0000F800) /* PCLK2 divided by 128 */ - -#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ - -#define RCC_PLLSRC_HSI_Mul2 ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */ -#define RCC_PLLSRC_HSE_Mul2 ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */ - -#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ -#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ -#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ -#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ - -#define RCC_ADC_CLK_ADJ ((uint32_t)0x10000000) /* ADC clock duty cycle adjustment */ -#define RCC_ADC_CLK_MODE ((uint32_t)0x80000000) /* ADC Clock Mode */ - -/******************* Bit definition for RCC_INTR register ********************/ -#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ - -#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ -#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ -#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ -#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ -#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ -#define RCC_SYSCLK_FAILIE ((uint32_t)0x00000200) /* system clock fail Interrupt Enable */ -#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ -#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ -#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ -#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ - -#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ -#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ -#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ -#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ - -/***************** Bit definition for RCC_PB2PRSTR register *****************/ -#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ -#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ -#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ -#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ -#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ -#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ - -#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ -#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ -#define RCC_USART2RST ((uint32_t)0x00002000) /* USART2 reset */ -#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ - -/***************** Bit definition for RCC_PB1PRSTR register *****************/ -#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ -#define RCC_TIM3RST ((uint32_t)0x00000004) /* Timer 3 reset */ -#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ -#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ - -#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ - -/****************** Bit definition for RCC_HBPCENR register ******************/ -#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ -#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ - -/****************** Bit definition for RCC_PB2PCENR register *****************/ -#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ -#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ -#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ -#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ -#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ -#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ - -#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ -#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ -#define RCC_USART2EN ((uint32_t)0x00002000) /* USART2 clock enable */ -#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ - -/***************** Bit definition for RCC_PB1PCENR register ******************/ -#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ -#define RCC_TIM3EN ((uint32_t)0x00000004) /* Timer 3 clock enable */ -#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ - -#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ - -#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ - -/******************* Bit definition for RCC_RSTSCKR register ********************/ -#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ -#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ -#define RCC_SYSCLK_FAILIF ((uint32_t)0x00000100) /* System clock failure interrupt flag */ -#define RCC_ADCRSTF ((uint32_t)0x00800000) /* ADC Reset Flag */ -#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ -#define RCC_OPCMRSTF ((uint32_t)0x02000000) /* OPA_CMP reset flag */ -#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ -#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ -#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ -#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ -#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ - -/******************************************************************************/ -/* Serial Peripheral Interface */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CTLR1 register ********************/ -#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ -#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ -#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ - -#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ -#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ -#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ -#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ - -#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ -#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /*Data frame format control bits*/ -#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ -#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ -#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ -#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ -#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ -#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ -#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ -#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CTLR2 register ********************/ -#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ -#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ -#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ -#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ -#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ -#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_STATR register ********************/ -#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ -#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ - -#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ -#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ -#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ -#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ - -/******************** Bit definition for SPI_DATAR register ********************/ -#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ - -/******************* Bit definition for SPI_CRCR register ******************/ -#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ - -/****************** Bit definition for SPI_RCRCR register ******************/ -#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ - -/****************** Bit definition for SPI_TCRCR register ******************/ -#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ - -/****************** Bit definition for SPI_HSCR register ******************/ -#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) /* Enable high-speed read mode */ - -/******************************************************************************/ -/* TIM */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CTLR1 register ********************/ -#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ -#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ -#define TIM_URS ((uint16_t)0x0004) /* Update request source */ -#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ -#define TIM_DIR ((uint16_t)0x0010) /* Direction */ - -#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ - -#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ - -#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ -#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_CAPOV ((uint16_t)0x4000) /*Capture Value Mode Configuration*/ -#define TIM_CAPLVL ((uint16_t)0x8000) /*Capture level indication enable in double-edge capture mode*/ - -/******************* Bit definition for TIM_CTLR2 register ********************/ -#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ -#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ -#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ - -#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ -#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ -#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ -#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ -#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ -#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ -#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ -#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ -#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIM_SMCFGR register *******************/ -#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ - -#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ -#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ - -#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ -#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ - -#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ -#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ - -/******************* Bit definition for TIM_DMAINTENR register *******************/ -#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ -#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ -#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ -#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ -#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ -#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ -#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ -#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ -#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ -#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ -#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ -#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ -#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ -#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ -#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ - -/******************** Bit definition for TIM_INTFR register ********************/ -#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ -#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ -#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ -#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ -#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ -#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ -#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ -#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ -#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ -#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ -#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ -#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIM_SWEVGR register ********************/ -#define TIM_UG ((uint8_t)0x01) /* Update Generation */ -#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ -#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ -#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ -#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ -#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ -#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ -#define TIM_BG ((uint8_t)0x80) /* Break Generation */ - -/****************** Bit definition for TIM_CHCTLR1 register *******************/ -#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ -#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ - -#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ - -#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ -#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ - -#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ - -#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/****************** Bit definition for TIM_CHCTLR2 register *******************/ -#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ -#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ - -#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ - -#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ -#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ - -#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ - -#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ -#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ -#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ -#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ -#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ -#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ -#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ -#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ -#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ -#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ -#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ -#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ -#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ -#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ - -/******************* Bit definition for TIM_ATRLR register ********************/ -#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ - -/******************* Bit definition for TIM_RPTCR register ********************/ -#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ - -/******************* Bit definition for TIM_CH1CVR register *******************/ -#define TIM_CCR1 ((uint32_t)0x0000FFFF) /* Capture/Compare 1 Value */ -#define TIM_LEVEL1 ((uint32_t)0x00010000) - -/******************* Bit definition for TIM_CH2CVR register *******************/ -#define TIM_CCR2 ((uint32_t)0x0000FFFF) /* Capture/Compare 2 Value */ -#define TIM_LEVEL2 ((uint32_t)0x00010000) - -/******************* Bit definition for TIM_CH3CVR register *******************/ -#define TIM_CCR3 ((uint32_t)0x0000FFFF) /* Capture/Compare 3 Value */ -#define TIM_LEVEL3 ((uint32_t)0x00010000) - -/******************* Bit definition for TIM_CH4CVR register *******************/ -#define TIM_CCR4 ((uint32_t)0x0000FFFF) /* Capture/Compare 4 Value */ -#define TIM_LEVEL4 ((uint32_t)0x00010000) - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_DTG ((uint16_t)0x00FF) /* DTG[7:0] bits (Dead-Time Generator set-up) */ -#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ -#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ -#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ -#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ - -#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ -#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ -#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ -#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ -#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ -#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ -#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ - -/******************* Bit definition for TIM_DTCR register *******************/ -#define TIM_OC1N_EN ((uint16_t)0x0001) /* Complementary channel 1 output enable*/ -#define TIM_OC2N_EN ((uint16_t)0x0002) /* Complementary channel 2 output enable*/ -#define TIM_DT1_P ((uint16_t)0x0004) /* Channel 1 output polarity setting*/ -#define TIM_DT1N_P ((uint16_t)0x0008) /* Channel 1 complementary channel output polarity setting*/ -#define TIM_DT2_P ((uint16_t)0x0010) /* Channel 2 output polarity setting*/ -#define TIM_DT2N_P ((uint16_t)0x0020) /* Channel 2 complementary channel output polarity setting*/ - -#define TIM_DT1 ((uint16_t)0x0F00) /* TIM_DT1[3:0] (Channel 1 dead time setting)*/ -#define TIM_DT1_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_DT1_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_DT1_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_DT1_3 ((uint16_t)0x0800) /* Bit 3 */ - -#define TIM_DT2 ((uint16_t)0xF000) /* TIM_DT2[3:0] (Channel 2 dead time setting)*/ -#define TIM_DT2_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_DT2_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_DT2_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_DT2_3 ((uint16_t)0x8000) /* Bit 3 */ - -/******************* Bit definition for TIM_DMACFGR register ********************/ -#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ -#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ - -#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ -#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ - -/******************* Bit definition for TIM_DMAADR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ - -/******************************************************************************/ -/* Streamlined Timer */ -/******************************************************************************/ - -/****************** Bit definition for SLTM_CTLR register ********************/ -#define SLTM_CEN ((uint16_t)0x0001) /* Counter enable */ -#define SLTM_UDIS ((uint16_t)0x0002) /* Update disable */ - -#define SLTM_DIR ((uint16_t)0x0010) /* Direction */ - -#define SLTM_CMS ((uint16_t)0x0060) /*CMS[1:0] bits (Count Mode Selection) */ -#define SLTM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define SLTM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ - -#define SLTM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ - -#define SLTM_SMS ((uint16_t)0x0700) /*SMS[2:0] bits (Slave Mode Selection) */ -#define SLTM_SMS_0 ((uint16_t)0x0100) /* Bit 0 */ -#define SLTM_SMS_1 ((uint16_t)0x0100) /* Bit 1 */ -#define SLTM_SMS_2 ((uint16_t)0x0100) /* Bit 2 */ - -/**************** Bit definition for SLTM_DMAINTENR register ****************/ -#define SLTM_OC1PE ((uint16_t)0x0001) /* Compare Register 1 Preload Enable*/ -#define SLTM_OC2PE ((uint16_t)0x0002) /* Compare Register 2 Preload Enable*/ -#define SLTM_OC3PE ((uint16_t)0x0004) /* Compare Register 3 Preload Enable*/ -#define SLTM_OC4PE ((uint16_t)0x0008) /* Compare Register 4 Preload Enable*/ - -#define SLTM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ -#define SLTM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ - -/****************** Bit definition for SLTM_CNT register ********************/ -#define SLTM_CNT ((uint16_t)0xFFFF) /* Counter Value */ - -/***************** Bit definition for SLTM_ATRLR register *******************/ -#define SLTM_ATRLR ((uint16_t)0xFFFF) /* actual auto-reload Value */ - -/**************** Bit definition for SLTM_CH1CVR register *******************/ -#define SLTM_CH1CVR ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ - -/**************** Bit definition for SLTM_CH2CVR register *******************/ -#define SLTM_CH2CVR ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ - -/**************** Bit definition for SLTM_CH3CVR register *******************/ -#define SLTM_CH3CVR ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ - -/**************** Bit definition for SLTM_CH4CVR register *******************/ -#define SLTM_CH4CVR ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ - -/******************************************************************************/ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/******************************************************************************/ - -/******************* Bit definition for USART_STATR register *******************/ -#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ -#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ -#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ -#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ -#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ -#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ -#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ -#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ -#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ -#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ - -/******************* Bit definition for USART_DATAR register *******************/ -#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ - -/****************** Bit definition for USART_CTLR1 register *******************/ -#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ -#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ -#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ -#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ -#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ -#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ -#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ -#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ -#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ -#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ -#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ -#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ -#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ -#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ - -/****************** Bit definition for USART_CTLR2 register *******************/ -#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ -#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ -#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ - -#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ -#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ -#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ - -/****************** Bit definition for USART_CTLR3 register *******************/ -#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ -#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ -#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ -#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ - -#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ -#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ -#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ -#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ -#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ - -/****************** Bit definition for USART_GPR register ******************/ -#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ -#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ -#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ -#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ -#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ -#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ -#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ -#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ -#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ - -/******************************************************************************/ -/* Window WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CTLR register ********************/ -#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ -#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ -#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ -#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ -#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ -#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ -#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ - -#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ - -/******************* Bit definition for WWDG_CFGR register *******************/ -#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ -#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ -#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ -#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ -#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ -#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ -#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ -#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ - -#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ -#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ - -#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_STATR register ********************/ -#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ - -/******************************************************************************/ -/* OPA and CMP */ -/******************************************************************************/ - -/****************** Bit definition for OPA_CFGR1 register ********************/ -#define OPA_CFGR1_POLL_EN ((uint32_t)0x00000001) /* OPA1 positive polling enable*/ - -#define OPA_CFGR1_POLL1_NUM ((uint32_t)0x0000000C) /* POLL1_MUM[1:0] bits (Configure the number of positive ends polled by OPA1)*/ -#define OPA_CFGR1_POLL1_NUM_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define OPA_CFGR1_POLL1_NUM_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define OPA_CFGR1_RST_EN1 ((uint32_t)0x00000010) /*OPA Reset Enable*/ - -#define OPA_CFGR1_SETUP_CFG ((uint32_t)0x00000060) /* SETUP_CFG[1:0] bits(OPA Establishment Time Configuration)*/ -#define OPA_CFGR1_SETUP_CFG_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define OPA_CFGR1_SETUP_CFG_1 ((uint32_t)0x00000040) /* Bit 1 */ - -#define OPA_CFGR1_AUTO_ADC_CFG ((uint32_t)0x00000080) /* OPA Auto Polling*/ - -#define OPA_CFGR1_IE_OUT1 ((uint32_t)0x00000100) /* OPA Interrupt Enable*/ -#define OPA_CFGR1_NMI_EN ((uint32_t)0x00000400) /* OPA Connection NMI Interrupt Enable*/ - -#define OPA_CFGR1_IF_OUT_POLL_CH1 ((uint32_t)0x00001000) /* Polling channel 1 outputs a high level interrupt flag*/ -#define OPA_CFGR1_IF_OUT_POLL_CH2 ((uint32_t)0x00002000) /* Polling channel 2 outputs a high level interrupt flag*/ -#define OPA_CFGR1_IF_OUT_POLL_CH3 ((uint32_t)0x00004000) /* Polling channel 3 outputs a high level interrupt flag*/ - -#define OPA_CFGR1_POLL_CH1 ((uint32_t)0x00030000) /*POLL_CH1[1:0] bits (OPA Channel 1 Polling Order)*/ -#define OPA_CFGR1_POLL_CH1_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define OPA_CFGR1_POLL_CH1_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define OPA_CFGR1_POLL_CH2 ((uint32_t)0x000C0000) /*POLL_CH2[1:0] bits (OPA Channel 2 Polling Order)*/ -#define OPA_CFGR1_POLL_CH2_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define OPA_CFGR1_POLL_CH2_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define OPA_CFGR1_POLL_CH3 ((uint32_t)0x00300000) /*POLL_CH3[1:0] bits (OPA Channel 3 Polling Order)*/ -#define OPA_CFGR1_POLL_CH3_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define OPA_CFGR1_POLL_CH3_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define OPA_CFGR1_POLL_SWSTRT ((uint32_t)0x01000000) /* Start OPA polling */ - -#define OPA_CFGR1_POLL_SEL ((uint32_t)0x0E000000) /*POLL_SEL[2:0] bits (OPA Polling Trigger Event Selection)*/ -#define OPA_CFGR1_POLL_SEL_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define OPA_CFGR1_POLL_SEL_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define OPA_CFGR1_POLL_SEL_2 ((uint32_t)0x08000000) /* Bit 2 */ - -#define OPA_CFGR1_POLL_LOCK ((uint32_t)0x80000000) /* POLL LOCK */ - -/****************** Bit definition for OPA_CTLR1 register ********************/ -#define OPA_CTLR1_OPA_EN1 ((uint32_t)0x00000001) /* OPA1 enable*/ - -#define OPA_CTLR1_MODE1 ((uint32_t)0x00000006) /* MODE[1:0] bits(OPA1 output channel selection)*/ -#define OPA_CTLR1_MODE1_0 ((uint32_t)0x00000002) /* Bit 0 */ -#define OPA_CTLR1_MODE1_1 ((uint32_t)0x00000004) /* Bit 1 */ - -#define OPA_CTLR1_PSEL1 ((uint32_t)0x00000030) /* PSEL1[1:0] bits(OPA1 positive input channel selection)*/ -#define OPA_CTLR1_PSEL1_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define OPA_CTLR1_PSEL1_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define OPA_CTLR1_NSEL1 ((uint32_t)0x00000700) /* NSEL1[2:0] bits(OPA1 negative input channel)*/ -#define OPA_CTLR1_NSEL1_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define OPA_CTLR1_NSEL1_1 ((uint32_t)0x00000200) /* Bit 1 */ -#define OPA_CTLR1_NSEL1_2 ((uint32_t)0x00000400) /* Bit 2 */ - -#define OPA_CTLR1_FB_EN1 ((uint32_t)0x00000800) /* OPA1 internal feedback resistor enable*/ -#define OPA_CTLR1_PGADIF ((uint32_t)0x00001000) /* PGA differential input configuration*/ -#define OPA_CTLR1_VBEN ((uint32_t)0x00010000) /* PGA mode, positive reference voltage enable*/ -#define OPA_CTLR1_VBSEL ((uint32_t)0x00020000) /* PGA mode, positive reference voltage selection*/ - -#define OPA_CTLR1_VBCMPSEL ((uint32_t)0x000C0000) /* VBCMPSEL[1:0] bits(Given the reference voltage at the negative end of CMP2)*/ -#define OPA_CTLR1_VBCMPSEL_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define OPA_CTLR1_VBCMPSEL_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define OPA_CTLR1_OPA_HS1 ((uint32_t)0x00100000) /* OPA1 high speed mode enable*/ -#define OPA_CTLR1_OPA_LOCK ((uint32_t)0x80000000) /* OPA LOCK*/ - -/****************** Bit definition for OPA_CFGR2 register ********************/ -#define OPA_CFGR2_POLL_EN1 ((uint32_t)0x00000001) /* CMP1 Positive Polling Enable*/ - -#define OPA_CFGR2_POLL_NUM ((uint32_t)0x0000000C) /* POLL1_NUM[1:0] bits (Number of positive ends polled by CMP1)*/ -#define OPA_CFGR2_POLL_NUM_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define OPA_CFGR2_POLL_NUM_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define OPA_CFGR2_RST_EN1 ((uint32_t)0x00000010) /* CMP1 reset system enable*/ -#define OPA_CFGR2_RST_EN2 ((uint32_t)0x00000020) /* CMP2 reset system enable*/ - -#define OPA_CFGR2_IE_OUT1 ((uint32_t)0x00000100) /* CMP1 interrupt enable*/ -#define OPA_CFGR2_IE_CNT ((uint32_t)0x00000200) /* CMP1 end-of-polling-interval interrupt enable*/ - -#define OPA_CFGR2_IF_OUT_POLL_CH1 ((uint32_t)0x00001000) /* CMP1 polled to channel 1 output for high level interrupt flag*/ -#define OPA_CFGR2_IF_OUT_POLL_CH2 ((uint32_t)0x00002000) /* CMP1 polled to channel 2 output for high level interrupt flag*/ -#define OPA_CFGR2_IF_OUT_POLL_CH3 ((uint32_t)0x00004000) /* CMP1 polled to channel 3 output for high level interrupt flag*/ - -#define OPA_CFGR2_IF_CNT ((uint32_t)0x00008000) /* CMP1 polling interval end interrupt flag*/ - -#define OPA_CFGR2_POLL_VLU ((uint32_t)0x01FF0000) /* CMP1 Positive Polling Interval*/ - -#define OPA_CFGR2_POLL_CH1 ((uint32_t)0x06000000) /* POLL_CH1[1:0] bits (CMP1 Polling Sequence Configuration)*/ -#define OPA_CFGR2_POLL_CH1_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define OPA_CFGR2_POLL_CH1_1 ((uint32_t)0x04000000) /* Bit 1 */ - -#define OPA_CFGR2_POLL_CH2 ((uint32_t)0x18000000) /* POLL_CH2[1:0] bits (CMP1 Polling Sequence Configuration)*/ -#define OPA_CFGR2_POLL_CH2_0 ((uint32_t)0x08000000) /* Bit 0 */ -#define OPA_CFGR2_POLL_CH2_1 ((uint32_t)0x10000000) /* Bit 1 */ - -#define OPA_CFGR2_POLL_CH3 ((uint32_t)0x60000000) /* POLL_CH3[1:0] bits (CMP1 Polling Sequence Configuration)*/ -#define OPA_CFGR2_POLL_CH3_0 ((uint32_t)0x20000000) /* Bit 0 */ -#define OPA_CFGR2_POLL_CH3_1 ((uint32_t)0x40000000) /* Bit 1 */ - -/****************** Bit definition for OPA_CTLR2 register ********************/ -#define OPA_CTLR2_CMP_EN1 ((uint32_t)0x00000001) /* CMP1 Enable*/ - -#define OPA_CTLR2_MODE1 ((uint32_t)0x00000006) /* MODE1[1:0] bits (CMP1 output mode selection)*/ -#define OPA_CTLR2_MODE1_0 ((uint32_t)0x00000002) /* Bit 0 */ -#define OPA_CTLR2_MODE1_1 ((uint32_t)0x00000004) /* Bit 1 */ - -#define OPA_CTLR2_NSEL1 ((uint32_t)0x00000018) /* NSEL1[1:0] bits (CMP1 negative input channel selection)*/ -#define OPA_CTLR2_NSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define OPA_CTLR2_NSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ - -#define OPA_CTLR2_PSEL1 ((uint32_t)0x00000060) /* PSEL1[1:0] bits (CMP1 positive input channel selection)*/ -#define OPA_CTLR2_PSEL1_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define OPA_CTLR2_PSEL1_1 ((uint32_t)0x00000040) /* Bit 1 */ - -#define OPA_CTLR2_HYEN1 ((uint32_t)0x00000080) /* CMP1 hysteresis comparator switch */ -#define OPA_CTLR2_RMID1 ((uint32_t)0x00000100) /* CMP1 Positive Input Channel Virtual Center Point Enable*/ -#define OPA_CTLR2_CMP_EN2 ((uint32_t)0x00010000) /* CMP2 Enable*/ - -#define OPA_CTLR2_FILT_EN ((uint32_t)0x01000000) /* CMP digital filter enable*/ -#define OPA_CTLR2_FILT_SEL ((uint32_t)0x02000000) /* CMP output digital filter length selection*/ - -#define OPA_CTLR2_BKIN_CFG ((uint32_t)0x0C000000) /* BKIN_CFG[1:0] bits (TIM1 Brake Source Configuration)*/ -#define OPA_CTLR2_BKIN_CFG_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define OPA_CTLR2_BKIN_CFG_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define OPA_CTLR2_CMP_LOCK ((uint32_t)0x80000000) /* CMP LOCK */ - -/****************** Bit definition for OPA_KEY register ********************/ -#define OPA_KEY ((uint32_t)0xFFFFFFFF) /* OPA Unlock Key Register*/ - -/****************** Bit definition for CMP_KEY register ********************/ -#define CMP_KEY ((uint32_t)0xFFFFFFFF) /* CMP Unlock Key Register*/ - -/****************** Bit definition for POLL_KEY register ********************/ -#define POLL_KEY ((uint32_t)0xFFFFFFFF) /* POLL Upper Lock Key Register*/ - -/******************************************************************************/ -/* ENHANCED FUNNCTION */ -/******************************************************************************/ - -/**************************** Enhanced register *****************************/ -#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 6 */ -#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ - -#define EXTEN_TIM2_DMA_REMAP ((uint32_t)0x00010000) /* DMA multiplexing of TIM2*/ - -#include - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00X_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/07 + * Description : CH32V00X Device Peripheral Access Layer Header File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_H +#define __CH32V00X_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(CH32V002) && !defined(CH32V004) && !defined(CH32V005) && !defined(CH32V006)&& !defined(CH32V007_M007) +//#define CH32V002 /* CH32V002*/ +//#define CH32V004 /* CH32V004 */ +//#define CH32V005 /* CH32V005 */ +//#define CH32V006 /* CH32V006 */ +//#define CH32V007_M007 /* CH32V007 - CH32M007*/ +#endif + +#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#ifndef HSE_VALUE +#define HSE_VALUE ((uint32_t)24000000) /* Value of the External oscillator in Hz */ +#endif + +/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x2000) /* Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)24000000) /* Value of the Internal oscillator in Hz */ + +/* CH32V00X Standard Peripheral Library version number */ +#define __CH32V00X_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ +#define __CH32V00X_STDPERIPH_VERSION_SUB (0x02) /* [7:0] sub version */ +#define __CH32V00X_STDPERIPH_VERSION ( (__CH32V00X_STDPERIPH_VERSION_MAIN << 8)\ + |(__CH32V00X_STDPERIPH_VERSION_SUB << 0)) + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = 3, /* 3 HardFault Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + FLASH_IRQn = 18, /* FLASH global Interrupt */ + RCC_IRQn = 19, /* RCC global Interrupt */ + EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ + AWU_IRQn = 21, /* AWU global Interrupt */ + DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 29, /* ADC global Interrupt */ + I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ + USART1_IRQn = 32, /* USART1 global Interrupt */ + SPI1_IRQn = 33, /* SPI1 global Interrupt */ + TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 38, /* TIM2 global Interrupt */ + +#if defined(CH32V005) || defined(CH32V006) || defined(CH32V007_M007) + USART2_IRQn = 39, /* USART2 global Interrupt */ + OPCM_IRQn = 40, /* OPCM global Interrupt */ +#endif +} IRQn_Type; + +#define SysTicK_IRQn SysTick_IRQn + +#include +#include +#include + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + __IO uint32_t CTLR3; + __IO uint32_t WDTR1; + __IO uint32_t WDTR2; +} ADC_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; + __IO uint32_t BOOT_MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + uint32_t RESERVED; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + uint32_t RESERVED0; + uint32_t RESERVED1; + __IO uint32_t EXTICR; + __IO uint32_t PCFR1; +} AFIO_TypeDef; + +/* Inter-Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; + __IO uint32_t AWUCSR; + __IO uint32_t AWUWR; + __IO uint32_t AWUPSC; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t PB2PRSTR; + __IO uint32_t PB1PRSTR; + __IO uint32_t HBPCENR; + __IO uint32_t PB2PCENR; + __IO uint32_t PB1PCENR; + uint32_t RESERVED0; + __IO uint32_t RSTSCKR; +} RCC_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + union + { + __IO uint16_t CTLR1; + __IO uint16_t TIM3_CTLR; + }; + uint16_t RESERVED0; + union + { + __IO uint16_t CTLR2; + __IO uint16_t TIM3_DMAINTENR; + }; + uint16_t RESERVED1; + union + { + __IO uint16_t SMCFGR; + __IO uint16_t TIM3_CNT; + }; + uint16_t RESERVED2; + union + { + __IO uint16_t DMAINTENR; + __IO uint16_t TIM3_ATRLR; + }; + uint16_t RESERVED3; + union + { + __IO uint16_t INTFR; + __IO uint16_t TIM3_CH1CVR; + }; + uint16_t RESERVED4; + union + { + __IO uint16_t SWEVGR; + __IO uint16_t TIM3_CH2CVR; + }; + uint16_t RESERVED5; + union + { + __IO uint16_t CHCTLR1; + __IO uint16_t TIM3_CH3CVR; + }; + uint16_t RESERVED6; + union + { + __IO uint16_t CHCTLR2; + __IO uint16_t TIM3_CH4CVR; + }; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint32_t CH1CVR; + __IO uint32_t CH2CVR; + __IO uint32_t CH3CVR; + __IO uint32_t CH4CVR; + union + { + __IO uint16_t BDTR; + __IO uint16_t TIM2_DTCR; + }; + uint16_t RESERVED13; + __IO uint16_t DMACFGR; + uint16_t RESERVED14; + __IO uint16_t DMAADR; + uint16_t RESERVED15; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* OPA Registers */ +typedef struct +{ + __IO uint32_t CFGR1; + __IO uint32_t CTLR1; + __IO uint32_t CFGR2; + __IO uint32_t CTLR2; + __IO uint32_t OPAKEY; + __IO uint32_t CMPKEY; + __IO uint32_t POLLKEY; +} OPA_TypeDef; + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define PB1PERIPH_BASE (PERIPH_BASE) +#define PB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define HBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (PB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (PB1PERIPH_BASE + 0x0800) +#define WWDG_BASE (PB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (PB1PERIPH_BASE + 0x3000) +#define USART2_BASE (PB1PERIPH_BASE + 0x4400) +#define I2C1_BASE (PB1PERIPH_BASE + 0x5400) +#define PWR_BASE (PB1PERIPH_BASE + 0x7000) + +#define AFIO_BASE (PB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (PB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (PB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (PB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (PB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (PB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (PB2PERIPH_BASE + 0x2400) +#define TIM1_BASE (PB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (PB2PERIPH_BASE + 0x3000) +#define USART1_BASE (PB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (HBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (HBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (HBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (HBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (HBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (HBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (HBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (HBPERIPH_BASE + 0x0080) +#define RCC_BASE (HBPERIPH_BASE + 0x1000) +#define FLASH_R_BASE (HBPERIPH_BASE + 0x2000) +#define EXTEN_BASE (HBPERIPH_BASE + 0x3800) +#define OPA_BASE (HBPERIPH_BASE + 0x4000) + +#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) + +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define OPA ((OPA_TypeDef *)OPA_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TKey1 ((ADC_TypeDef *)ADC1_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +#define ADC_TKENABLE ((uint32_t)0x01000000) /* Analog watchdog enable on injected channels */ +#define ADC_TKITUNE ((uint32_t)0x02000000) /* Analog watchdog enable on injected channels */ +#define ADC_BUFEN ((uint32_t)0x04000000) /* Analog watchdog enable on injected channels */ + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_TGREGU ((uint32_t)0x00000010) /*External Trigger Events for Rule Channel Conversion*/ +#define ADC_TGINJE ((uint32_t)0x00000020) /*Injection of externally triggered events for channel conversions*/ + +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ + +/******************** Bit definition for ADC_CTLR3 register ********************/ +#define ADC_LP ((uint32_t)0x00000001) /* ADC Low Power Mode Selection */ +#define ADC_DUTYEN ((uint32_t)0x00000002) /* ADC clock duty cycle control */ +#define ADC_DRVEN ((uint32_t)0x00000004) /* Touchkey multi mask enable */ +#define ADC_AWD_SCAN ((uint32_t)0x00000008) /*Analog watchdog scan enable*/ +#define ADC_AWD0_RST_EN ((uint32_t)0x00000010) /*Analog watchdog 0 output reset enable*/ +#define ADC_AWD1_RST_EN ((uint32_t)0x00000020) /*Analog watchdog 1 output reset enable*/ +#define ADC_AWD2_RST_EN ((uint32_t)0x00000040) /*Analog watchdog 2 output reset enable*/ + +#define ADC_AWD0_RES ((uint32_t)0x00000100) /*Analog Watchdog 0 Comparison Result*/ +#define ADC_AWD1_RES ((uint32_t)0x00000200) /*Analog Watchdog 1 Comparison Result*/ +#define ADC_AWD2_RES ((uint32_t)0x00000400) /*Analog Watchdog 2 Comparison Result*/ + +#define ADC_DRV_OUTEN ((uint32_t)0x00FF0000) /*Touchkey multi mask enable for each channel*/ + +/******************** Bit definition for ADC_WDTR1 register ********************/ +#define ADC_WDTR1_LTR1 ((uint32_t)0x00000FFF) /*Analog Watchdog Low Threshold Setting Value*/ +#define ADC_WDTR1_HTR1 ((uint32_t)0x0FFF0000) /*Analog Watchdog High Threshold Setting Value*/ + +/******************** Bit definition for ADC_WDTR2 register ********************/ +#define ADC_WDTR2_LTR2 ((uint32_t)0x00000FFF) /*Analog Watchdog Low Threshold Setting Value*/ +#define ADC_WDTR2_HTR2 ((uint32_t)0x0FFF0000) /*Analog Watchdog High Threshold Setting Value*/ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ + +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_FWAKE_FLAG ((uint8_t)0x40) /* Flag of wake */ +#define FLASH_STATR_TURBO ((uint8_t)0x80) /* The state of TURBO Enable */ +#define FLASH_STATR_BOOT_AVA ((uint16_t)0x1000) /* The state of Init Config */ +#define FLASH_STATR_BOOT_STATUS ((uint16_t)0x2000) /* The source of Execute Program */ +#define FLASH_STATR_BOOT_MODE ((uint16_t)0x4000) /* The switch of user section or boot section*/ +#define FLASH_STATR_BOOT_LOCK ((uint16_t)0x8000) /* Lock boot area*/ + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PER ((uint16_t)0x0002) /* Page Erase 1KByte*/ +#define FLASH_CTLR_MER ((uint16_t)0x0004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG ((uint16_t)0x0010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint16_t)0x0020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint16_t)0x0040) /* Start */ +#define FLASH_CTLR_LOCK ((uint16_t)0x0080) /* Lock */ +#define FLASH_CTLR_OPTWRE ((uint16_t)0x0200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint16_t)0x0400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint16_t)0x1000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FLOCK ((uint16_t)0x8000) /* Fast Lock */ +#define FLASH_CTLR_PAGE_PG ((uint16_t)0x00010000) /* Page Programming 256Byte */ +#define FLASH_CTLR_PAGE_ER ((uint16_t)0x00020000) /* Page Erase 256Byte */ +#define FLASH_CTLR_BUF_LOAD ((uint16_t)0x00040000) /* Buffer Load */ +#define FLASH_CTLR_BUF_RST ((uint16_t)0x00080000) /* Buffer Reset */ +#define FLASH_CTLR_BER32 ((uint32_t)0x00800000) /* Block Erase 32K */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x00F4) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */ +#define FLASH_OBR_STATR_MODE ((uint16_t)0x0080) /* RST_MODE */ + +#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) /* Data byte0 */ +#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) /* Data byte1 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_MODEKEYR register ******************/ +#define FLASH_MODEKEYR_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open fast program /erase */ +#define FLASH_MODEKEYR_MODEKEYR1 ((uint32_t)0x45670123) +#define FLASH_MODEKEYR_MODEKEYR2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for BOOT_MODEKEYP register ******************/ +#define BOOT_MODEKEYP_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open Boot section */ +#define BOOT_MODEKEYP_MODEKEYR1 ((uint32_t)0x45670123) +#define BOOT_MODEKEYP_MODEKEYR2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x11111111) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000001) /* MODE0 bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000000) +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000001) + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000010) /* MODE1 bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000000) +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000010) + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000100) /* MODE2 bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000000) +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000100) + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00001000) /* MODE3 bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00000000) +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00001000) + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00010000) /* MODE4 bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00000000) +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00010000) + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00100000) /* MODE5 bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00000000) +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00100000) + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x01000000) /* MODE6 bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x01000000) + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x10000000) /* MODE7 bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x00000000) +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x10000000) + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ + +#define GPIO_LCKK ((uint32_t)0x00000100) /* Lock key */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000007) /* SPI1_RM [2:0] bits (SPI1_REMAP configuration) */ +#define AFIO_PCFR1_SPI1_REMAP_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define AFIO_PCFR1_SPI1_REMAP_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define AFIO_PCFR1_SPI1_REMAP_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000038) /* I2C1_RM [2:0] bits (I2C1_REMAP configuration) */ +#define AFIO_PCFR1_I2C1_REMAP_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define AFIO_PCFR1_I2C1_REMAP_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define AFIO_PCFR1_I2C1_REMAP_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x000003C0) /* USART1_RM [3:0] bits (USART1_REMAP configuration) */ +#define AFIO_PCFR1_USART1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define AFIO_PCFR1_USART1_REMAP_2 ((uint32_t)0x00000100) /* Bit 2 */ +#define AFIO_PCFR1_USART1_REMAP_3 ((uint32_t)0x00000200) /* Bit 3 */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x00003C00) /* TIM1_RM [3:0] bits (TIM1_REMAP configuration) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define AFIO_PCFR1_TIM1_REMAP_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define AFIO_PCFR1_TIM1_REMAP_3 ((uint32_t)0x00002000) /* Bit 3 */ + +#define AFIO_PCFR1_TIM1_1_REMAP ((uint32_t)0x00003000) /* TIM1 1 remapping (Timer 1 channel 1 selection) */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x0001C000) /* TIM2_RM [2:0] bits (TIM2_REMAP configuration) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00008000) /* Bit 1 */ +#define AFIO_PCFR1_TIM2_REMAP_2 ((uint32_t)0x00010000) /* Bit 2 */ + +#define AFIO_PCFR1_PA1PA2_REMAP ((uint32_t)0x00020000) /* Port A0/Port A1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_ADC_ETRGINJ_REMAP ((uint32_t)0x00040000) /* Remap bit for ADC externally triggered injection conversion */ +#define AFIO_PCFR1_ADC_ETRGREG_REMAP ((uint32_t)0x00080000) /* Remap bits for ADC externally triggered rule conversion */ + +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00700000) /* USART2_RM [2:0] bits (USART2_REMAP configuration) */ +#define AFIO_PCFR1_USART2_REMAP_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define AFIO_PCFR1_USART2_REMAP_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define AFIO_PCFR1_USART2_REMAP_2 ((uint32_t)0x00400000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x0003) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x000C) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0030) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0x00C0) /* EXTI 3 configuration */ +#define AFIO_EXTICR1_EXTI4 ((uint16_t)0x0300) /* EXTI 4 configuration */ +#define AFIO_EXTICR1_EXTI5 ((uint16_t)0x0C00) /* EXTI 5 configuration */ +#define AFIO_EXTICR1_EXTI6 ((uint16_t)0x3000) /* EXTI 6 configuration */ +#define AFIO_EXTICR1_EXTI7 ((uint16_t)0xC000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0004) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0008) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x000C) /* PD[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0010) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0020) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0030) /* PD[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x0040) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x0080) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x00C0) /* PD[3] pin */ + +#define AFIO_EXTICR1_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR1_EXTI4_PB ((uint16_t)0x0100) /* PB[4] pin */ +#define AFIO_EXTICR1_EXTI4_PC ((uint16_t)0x0200) /* PC[4] pin */ +#define AFIO_EXTICR1_EXTI4_PD ((uint16_t)0x0300) /* PD[4] pin */ + +#define AFIO_EXTICR1_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR1_EXTI5_PB ((uint16_t)0x0400) /* PB[5] pin */ +#define AFIO_EXTICR1_EXTI5_PC ((uint16_t)0x0800) /* PC[5] pin */ +#define AFIO_EXTICR1_EXTI5_PD ((uint16_t)0x0C00) /* PD[5] pin */ + +#define AFIO_EXTICR1_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR1_EXTI6_PB ((uint16_t)0x1000) /* PB[6] pin */ +#define AFIO_EXTICR1_EXTI6_PC ((uint16_t)0x2000) /* PC[6] pin */ +#define AFIO_EXTICR1_EXTI6_PD ((uint16_t)0x3000) /* PD[6] pin */ + +#define AFIO_EXTICR1_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR1_EXTI7_PB ((uint16_t)0x4000) /* PB[7] pin */ +#define AFIO_EXTICR1_EXTI7_PC ((uint16_t)0x8000) /* PC[7] pin */ +#define AFIO_EXTICR1_EXTI7_PD ((uint16_t)0xC000) /* PD[7] pin */ + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ + +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ + +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ + +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ + +#define PWR_CTLR_LDO_MODE ((uint16_t)0x000C) /* LDO_MODE[1:0] bits (Voltage regulator working mode selection) */ +#define PWR_CTLR_LDO_MODE_0 ((uint16_t)0x0004) /* Bit 0 */ +#define PWR_CTLR_LDO_MODE_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define PWR_CTLR_LDO_MODE_NORMAL ((uint16_t)0x0008) /* LDO normal mode*/ +#define PWR_CTLR_LDO_MODE_ENERGYSAVE ((uint16_t)0x000C) /* LDO energy saving mode */ +#define PWR_CTLR_LDO_MODE_LOWPOWER ((uint16_t)0x0004) /* LDO low power mode*/ + +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x0060) /* PLS[1:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) /* PVD level 0 */ +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) /* PVD level 1 */ +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) /* PVD level 2 */ +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) /* PVD level 3 */ + +#define PWR_CTLR_FLASH_LP_REG ((uint16_t)0x0200) /* Configure FLASH to enter low-power mode */ + +#define PWR_CTLR_FLASH_LP ((uint16_t)0x0C00) /* FLASH_LP[1:0] bits (Flash Status Selection) */ +#define PWR_CTLR_FLASH_LP_0 ((uint16_t)0x0000) /* free time */ +#define PWR_CTLR_FLASH_LP_1 ((uint16_t)0x0400) /* sleep state */ + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ + +/******************* Bit definition for PWR_AWUCSR register ********************/ +#define PWR_AWUEN ((uint16_t)0x0002) + +/******************* Bit definition for PWR_AWUWR register ********************/ +#define PWR_AWUWR ((uint16_t)0x003F) /* PWR_AWUWR[5:0] bits*/ +#define PWR_AWUWR_0 ((uint16_t)0x0001) /* Bit 0 */ +#define PWR_AWUWR_1 ((uint16_t)0x0002) /* Bit 1 */ +#define PWR_AWUWR_2 ((uint16_t)0x0004) /* Bit 2 */ +#define PWR_AWUWR_3 ((uint16_t)0x0008) /* Bit 3 */ +#define PWR_AWUWR_4 ((uint16_t)0x0010) /* Bit 4 */ +#define PWR_AWUWR_5 ((uint16_t)0x0020) /* Bit 5 */ + +/******************* Bit definition for PWR_AWUPSC register ********************/ +#define PWR_AWUPSC ((uint16_t)0x000F) /* PWR_AWUPSC[3:0]*/ +#define PWR_AWUPSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define PWR_AWUPSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define PWR_AWUPSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define PWR_AWUPSC_3 ((uint16_t)0x0008) /* Bit 3 */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSILP ((uint32_t)0x00000004) /* HSI Low Power Mode Enabled */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_HSE_LP ((uint32_t)0x00100000) /* Internal High Speed clock enable */ +#define RCC_SYSCM_EN ((uint32_t)0x00200000) /* Internal High Speed clock enable */ + +#define RCC_HSE_SI ((uint32_t)0x00C00000) /* HSE_SI[1:0] bits (HSE current supply adjustment bit) */ +#define RCC_HSE_SI_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define RCC_HSE_SI_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (HB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ +#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ +#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ + +#define RCC_ADCPRE ((uint32_t)0x0000F800) /* ADCPRE[4:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_ADCPRE_2 ((uint32_t)0x00002000) /* Bit 2 */ +#define RCC_ADCPRE_3 ((uint32_t)0x00004000) /* Bit 3 */ +#define RCC_ADCPRE_4 ((uint32_t)0x00008000) /* Bit 4 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ +#define RCC_ADCPRE_DIV12 ((uint32_t)0x0000A000) /* PCLK2 divided by 12 */ +#define RCC_ADCPRE_DIV16 ((uint32_t)0x0000E000) /* PCLK2 divided by 16 */ +#define RCC_ADCPRE_DIV24 ((uint32_t)0x0000A800) /* PCLK2 divided by 24 */ +#define RCC_ADCPRE_DIV32 ((uint32_t)0x0000E800) /* PCLK2 divided by 32 */ +#define RCC_ADCPRE_DIV48 ((uint32_t)0x0000B000) /* PCLK2 divided by 48 */ +#define RCC_ADCPRE_DIV64 ((uint32_t)0x0000F000) /* PCLK2 divided by 64 */ +#define RCC_ADCPRE_DIV96 ((uint32_t)0x0000B800) /* PCLK2 divided by 96 */ +#define RCC_ADCPRE_DIV128 ((uint32_t)0x0000F800) /* PCLK2 divided by 128 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLSRC_HSI_Mul2 ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE_Mul2 ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +#define RCC_ADC_CLK_ADJ ((uint32_t)0x10000000) /* ADC clock duty cycle adjustment */ +#define RCC_ADC_CLK_MODE ((uint32_t)0x80000000) /* ADC Clock Mode */ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ + +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_SYSCLK_FAILIE ((uint32_t)0x00000200) /* system clock fail Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ + +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_PB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ + +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART2RST ((uint32_t)0x00002000) /* USART2 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +/***************** Bit definition for RCC_PB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000004) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ + +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + +/****************** Bit definition for RCC_HBPCENR register ******************/ +#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ + +/****************** Bit definition for RCC_PB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ + +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART2EN ((uint32_t)0x00002000) /* USART2 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_PB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000004) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ + +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ + +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_SYSCLK_FAILIF ((uint32_t)0x00000100) /* System clock failure interrupt flag */ +#define RCC_ADCRSTF ((uint32_t)0x00800000) /* ADC Reset Flag */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_OPCMRSTF ((uint32_t)0x02000000) /* OPA_CMP reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /*Data frame format control bits*/ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ + +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register ******************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) /* Enable high-speed read mode */ + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_CAPOV ((uint16_t)0x4000) /*Capture Value Mode Configuration*/ +#define TIM_CAPLVL ((uint16_t)0x8000) /*Capture level indication enable in double-edge capture mode*/ + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint32_t)0x0000FFFF) /* Capture/Compare 1 Value */ +#define TIM_LEVEL1 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint32_t)0x0000FFFF) /* Capture/Compare 2 Value */ +#define TIM_LEVEL2 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint32_t)0x0000FFFF) /* Capture/Compare 3 Value */ +#define TIM_LEVEL3 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint32_t)0x0000FFFF) /* Capture/Compare 4 Value */ +#define TIM_LEVEL4 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[7:0] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DTCR register *******************/ +#define TIM_OC1N_EN ((uint16_t)0x0001) /* Complementary channel 1 output enable*/ +#define TIM_OC2N_EN ((uint16_t)0x0002) /* Complementary channel 2 output enable*/ +#define TIM_DT1_P ((uint16_t)0x0004) /* Channel 1 output polarity setting*/ +#define TIM_DT1N_P ((uint16_t)0x0008) /* Channel 1 complementary channel output polarity setting*/ +#define TIM_DT2_P ((uint16_t)0x0010) /* Channel 2 output polarity setting*/ +#define TIM_DT2N_P ((uint16_t)0x0020) /* Channel 2 complementary channel output polarity setting*/ + +#define TIM_DT1 ((uint16_t)0x0F00) /* TIM_DT1[3:0] (Channel 1 dead time setting)*/ +#define TIM_DT1_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DT1_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DT1_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DT1_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_DT2 ((uint16_t)0xF000) /* TIM_DT2[3:0] (Channel 2 dead time setting)*/ +#define TIM_DT2_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_DT2_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_DT2_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_DT2_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Streamlined Timer */ +/******************************************************************************/ + +/****************** Bit definition for SLTM_CTLR register ********************/ +#define SLTM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define SLTM_UDIS ((uint16_t)0x0002) /* Update disable */ + +#define SLTM_DIR ((uint16_t)0x0010) /* Direction */ + +#define SLTM_CMS ((uint16_t)0x0060) /*CMS[1:0] bits (Count Mode Selection) */ +#define SLTM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define SLTM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define SLTM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define SLTM_SMS ((uint16_t)0x0700) /*SMS[2:0] bits (Slave Mode Selection) */ +#define SLTM_SMS_0 ((uint16_t)0x0100) /* Bit 0 */ +#define SLTM_SMS_1 ((uint16_t)0x0100) /* Bit 1 */ +#define SLTM_SMS_2 ((uint16_t)0x0100) /* Bit 2 */ + +/**************** Bit definition for SLTM_DMAINTENR register ****************/ +#define SLTM_OC1PE ((uint16_t)0x0001) /* Compare Register 1 Preload Enable*/ +#define SLTM_OC2PE ((uint16_t)0x0002) /* Compare Register 2 Preload Enable*/ +#define SLTM_OC3PE ((uint16_t)0x0004) /* Compare Register 3 Preload Enable*/ +#define SLTM_OC4PE ((uint16_t)0x0008) /* Compare Register 4 Preload Enable*/ + +#define SLTM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define SLTM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ + +/****************** Bit definition for SLTM_CNT register ********************/ +#define SLTM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/***************** Bit definition for SLTM_ATRLR register *******************/ +#define SLTM_ATRLR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/**************** Bit definition for SLTM_CH1CVR register *******************/ +#define SLTM_CH1CVR ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/**************** Bit definition for SLTM_CH2CVR register *******************/ +#define SLTM_CH2CVR ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/**************** Bit definition for SLTM_CH3CVR register *******************/ +#define SLTM_CH3CVR ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/**************** Bit definition for SLTM_CH4CVR register *******************/ +#define SLTM_CH4CVR ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ + +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* OPA and CMP */ +/******************************************************************************/ + +/****************** Bit definition for OPA_CFGR1 register ********************/ +#define OPA_CFGR1_POLL_EN ((uint32_t)0x00000001) /* OPA1 positive polling enable*/ + +#define OPA_CFGR1_POLL1_NUM ((uint32_t)0x0000000C) /* POLL1_MUM[1:0] bits (Configure the number of positive ends polled by OPA1)*/ +#define OPA_CFGR1_POLL1_NUM_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define OPA_CFGR1_POLL1_NUM_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define OPA_CFGR1_RST_EN1 ((uint32_t)0x00000010) /*OPA Reset Enable*/ + +#define OPA_CFGR1_SETUP_CFG ((uint32_t)0x00000060) /* SETUP_CFG[1:0] bits(OPA Establishment Time Configuration)*/ +#define OPA_CFGR1_SETUP_CFG_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define OPA_CFGR1_SETUP_CFG_1 ((uint32_t)0x00000040) /* Bit 1 */ + +#define OPA_CFGR1_AUTO_ADC_CFG ((uint32_t)0x00000080) /* OPA Auto Polling*/ + +#define OPA_CFGR1_IE_OUT1 ((uint32_t)0x00000100) /* OPA Interrupt Enable*/ +#define OPA_CFGR1_NMI_EN ((uint32_t)0x00000400) /* OPA Connection NMI Interrupt Enable*/ + +#define OPA_CFGR1_IF_OUT_POLL_CH1 ((uint32_t)0x00001000) /* Polling channel 1 outputs a high level interrupt flag*/ +#define OPA_CFGR1_IF_OUT_POLL_CH2 ((uint32_t)0x00002000) /* Polling channel 2 outputs a high level interrupt flag*/ +#define OPA_CFGR1_IF_OUT_POLL_CH3 ((uint32_t)0x00004000) /* Polling channel 3 outputs a high level interrupt flag*/ + +#define OPA_CFGR1_POLL_CH1 ((uint32_t)0x00030000) /*POLL_CH1[1:0] bits (OPA Channel 1 Polling Order)*/ +#define OPA_CFGR1_POLL_CH1_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define OPA_CFGR1_POLL_CH1_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define OPA_CFGR1_POLL_CH2 ((uint32_t)0x000C0000) /*POLL_CH2[1:0] bits (OPA Channel 2 Polling Order)*/ +#define OPA_CFGR1_POLL_CH2_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define OPA_CFGR1_POLL_CH2_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define OPA_CFGR1_POLL_CH3 ((uint32_t)0x00300000) /*POLL_CH3[1:0] bits (OPA Channel 3 Polling Order)*/ +#define OPA_CFGR1_POLL_CH3_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define OPA_CFGR1_POLL_CH3_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define OPA_CFGR1_POLL_SWSTRT ((uint32_t)0x01000000) /* Start OPA polling */ + +#define OPA_CFGR1_POLL_SEL ((uint32_t)0x0E000000) /*POLL_SEL[2:0] bits (OPA Polling Trigger Event Selection)*/ +#define OPA_CFGR1_POLL_SEL_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define OPA_CFGR1_POLL_SEL_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define OPA_CFGR1_POLL_SEL_2 ((uint32_t)0x08000000) /* Bit 2 */ + +#define OPA_CFGR1_POLL_LOCK ((uint32_t)0x80000000) /* POLL LOCK */ + +/****************** Bit definition for OPA_CTLR1 register ********************/ +#define OPA_CTLR1_OPA_EN1 ((uint32_t)0x00000001) /* OPA1 enable*/ + +#define OPA_CTLR1_MODE1 ((uint32_t)0x00000006) /* MODE[1:0] bits(OPA1 output channel selection)*/ +#define OPA_CTLR1_MODE1_0 ((uint32_t)0x00000002) /* Bit 0 */ +#define OPA_CTLR1_MODE1_1 ((uint32_t)0x00000004) /* Bit 1 */ + +#define OPA_CTLR1_PSEL1 ((uint32_t)0x00000030) /* PSEL1[1:0] bits(OPA1 positive input channel selection)*/ +#define OPA_CTLR1_PSEL1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define OPA_CTLR1_PSEL1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define OPA_CTLR1_NSEL1 ((uint32_t)0x00000700) /* NSEL1[2:0] bits(OPA1 negative input channel)*/ +#define OPA_CTLR1_NSEL1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define OPA_CTLR1_NSEL1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define OPA_CTLR1_NSEL1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define OPA_CTLR1_FB_EN1 ((uint32_t)0x00000800) /* OPA1 internal feedback resistor enable*/ +#define OPA_CTLR1_PGADIF ((uint32_t)0x00001000) /* PGA differential input configuration*/ +#define OPA_CTLR1_VBEN ((uint32_t)0x00010000) /* PGA mode, positive reference voltage enable*/ +#define OPA_CTLR1_VBSEL ((uint32_t)0x00020000) /* PGA mode, positive reference voltage selection*/ + +#define OPA_CTLR1_VBCMPSEL ((uint32_t)0x000C0000) /* VBCMPSEL[1:0] bits(Given the reference voltage at the negative end of CMP2)*/ +#define OPA_CTLR1_VBCMPSEL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define OPA_CTLR1_VBCMPSEL_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define OPA_CTLR1_OPA_HS1 ((uint32_t)0x00100000) /* OPA1 high speed mode enable*/ +#define OPA_CTLR1_OPA_LOCK ((uint32_t)0x80000000) /* OPA LOCK*/ + +/****************** Bit definition for OPA_CFGR2 register ********************/ +#define OPA_CFGR2_POLL_EN1 ((uint32_t)0x00000001) /* CMP1 Positive Polling Enable*/ + +#define OPA_CFGR2_POLL_NUM ((uint32_t)0x0000000C) /* POLL1_NUM[1:0] bits (Number of positive ends polled by CMP1)*/ +#define OPA_CFGR2_POLL_NUM_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define OPA_CFGR2_POLL_NUM_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define OPA_CFGR2_RST_EN1 ((uint32_t)0x00000010) /* CMP1 reset system enable*/ +#define OPA_CFGR2_RST_EN2 ((uint32_t)0x00000020) /* CMP2 reset system enable*/ + +#define OPA_CFGR2_IE_OUT1 ((uint32_t)0x00000100) /* CMP1 interrupt enable*/ +#define OPA_CFGR2_IE_CNT ((uint32_t)0x00000200) /* CMP1 end-of-polling-interval interrupt enable*/ + +#define OPA_CFGR2_IF_OUT_POLL_CH1 ((uint32_t)0x00001000) /* CMP1 polled to channel 1 output for high level interrupt flag*/ +#define OPA_CFGR2_IF_OUT_POLL_CH2 ((uint32_t)0x00002000) /* CMP1 polled to channel 2 output for high level interrupt flag*/ +#define OPA_CFGR2_IF_OUT_POLL_CH3 ((uint32_t)0x00004000) /* CMP1 polled to channel 3 output for high level interrupt flag*/ + +#define OPA_CFGR2_IF_CNT ((uint32_t)0x00008000) /* CMP1 polling interval end interrupt flag*/ + +#define OPA_CFGR2_POLL_VLU ((uint32_t)0x01FF0000) /* CMP1 Positive Polling Interval*/ + +#define OPA_CFGR2_POLL_CH1 ((uint32_t)0x06000000) /* POLL_CH1[1:0] bits (CMP1 Polling Sequence Configuration)*/ +#define OPA_CFGR2_POLL_CH1_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define OPA_CFGR2_POLL_CH1_1 ((uint32_t)0x04000000) /* Bit 1 */ + +#define OPA_CFGR2_POLL_CH2 ((uint32_t)0x18000000) /* POLL_CH2[1:0] bits (CMP1 Polling Sequence Configuration)*/ +#define OPA_CFGR2_POLL_CH2_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define OPA_CFGR2_POLL_CH2_1 ((uint32_t)0x10000000) /* Bit 1 */ + +#define OPA_CFGR2_POLL_CH3 ((uint32_t)0x60000000) /* POLL_CH3[1:0] bits (CMP1 Polling Sequence Configuration)*/ +#define OPA_CFGR2_POLL_CH3_0 ((uint32_t)0x20000000) /* Bit 0 */ +#define OPA_CFGR2_POLL_CH3_1 ((uint32_t)0x40000000) /* Bit 1 */ + +/****************** Bit definition for OPA_CTLR2 register ********************/ +#define OPA_CTLR2_CMP_EN1 ((uint32_t)0x00000001) /* CMP1 Enable*/ + +#define OPA_CTLR2_MODE1 ((uint32_t)0x00000006) /* MODE1[1:0] bits (CMP1 output mode selection)*/ +#define OPA_CTLR2_MODE1_0 ((uint32_t)0x00000002) /* Bit 0 */ +#define OPA_CTLR2_MODE1_1 ((uint32_t)0x00000004) /* Bit 1 */ + +#define OPA_CTLR2_NSEL1 ((uint32_t)0x00000018) /* NSEL1[1:0] bits (CMP1 negative input channel selection)*/ +#define OPA_CTLR2_NSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define OPA_CTLR2_NSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ + +#define OPA_CTLR2_PSEL1 ((uint32_t)0x00000060) /* PSEL1[1:0] bits (CMP1 positive input channel selection)*/ +#define OPA_CTLR2_PSEL1_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define OPA_CTLR2_PSEL1_1 ((uint32_t)0x00000040) /* Bit 1 */ + +#define OPA_CTLR2_HYEN1 ((uint32_t)0x00000080) /* CMP1 hysteresis comparator switch */ +#define OPA_CTLR2_RMID1 ((uint32_t)0x00000100) /* CMP1 Positive Input Channel Virtual Center Point Enable*/ +#define OPA_CTLR2_CMP_EN2 ((uint32_t)0x00010000) /* CMP2 Enable*/ + +#define OPA_CTLR2_FILT_EN ((uint32_t)0x01000000) /* CMP digital filter enable*/ +#define OPA_CTLR2_FILT_SEL ((uint32_t)0x02000000) /* CMP output digital filter length selection*/ + +#define OPA_CTLR2_BKIN_CFG ((uint32_t)0x0C000000) /* BKIN_CFG[1:0] bits (TIM1 Brake Source Configuration)*/ +#define OPA_CTLR2_BKIN_CFG_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define OPA_CTLR2_BKIN_CFG_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define OPA_CTLR2_CMP_LOCK ((uint32_t)0x80000000) /* CMP LOCK */ + +/****************** Bit definition for OPA_KEY register ********************/ +#define OPA_KEY ((uint32_t)0xFFFFFFFF) /* OPA Unlock Key Register*/ + +/****************** Bit definition for CMP_KEY register ********************/ +#define CMP_KEY ((uint32_t)0xFFFFFFFF) /* CMP Unlock Key Register*/ + +/****************** Bit definition for POLL_KEY register ********************/ +#define POLL_KEY ((uint32_t)0xFFFFFFFF) /* POLL Upper Lock Key Register*/ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 6 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + +#define EXTEN_TIM2_DMA_REMAP ((uint32_t)0x00010000) /* DMA multiplexing of TIM2*/ + +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00X_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_adc.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_adc.h index 1b7f9b0..bb04d11 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_adc.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_adc.h @@ -1,212 +1,208 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_adc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the - * ADC firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_ADC_H -#define __CH32V00X_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* ADC Init structure definition */ -typedef struct -{ - uint32_t ADC_Mode; /* Configures the ADC to operate in independent or - dual mode. - This parameter can be a value of @ref ADC_mode */ - - FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in - Scan (multichannels) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ -} ADC_InitTypeDef; - -/* ADC_mode */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) - -/* ADC_external_trigger_sources_for_regular_channels_conversion */ -#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) -#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) -#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigConv_Ext_PD3_PC2_OPA ((uint32_t)0x000C0000) -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) - -/* ADC_data_align */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) - -/* ADC_channels */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) - -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8) -#define ADC_Channel_OPA ((uint8_t)ADC_Channel_9) -#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_10) - -/* ADC_sampling_time */ -#define ADC_SampleTime_CyclesMode0 ((uint8_t)0x00) -#define ADC_SampleTime_CyclesMode1 ((uint8_t)0x01) -#define ADC_SampleTime_CyclesMode2 ((uint8_t)0x02) -#define ADC_SampleTime_CyclesMode3 ((uint8_t)0x03) -#define ADC_SampleTime_CyclesMode4 ((uint8_t)0x04) -#define ADC_SampleTime_CyclesMode5 ((uint8_t)0x05) -#define ADC_SampleTime_CyclesMode6 ((uint8_t)0x06) -#define ADC_SampleTime_CyclesMode7 ((uint8_t)0x07) - -/* ADC_external_trigger_sources_for_injected_channels_conversion */ -#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) -#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) -#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) -#define ADC_ExternalTrigInjecConv_T3_CC1 ((uint32_t)0x00004000) -#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00005000) -#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2_OPA ((uint32_t)0x00006000) -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) - -/* ADC_injected_channel_selection */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) - -/* ADC_analog_watchdog_selection */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -/* ADC_interrupts_definition */ -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) - -/* ADC_flags_definition */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) - -/* ADC_TKey_Current_definition */ -#define ADC_TKey_Current_mode0 ((uint32_t)0x00000000) -#define ADC_TKey_Current_mode1 ((uint32_t)0x02000000) - -/* ADC_RegularExTrigConv_definition */ -#define ADC_RegularExTrigConv_PD3_PC2 ((uint32_t)0x00000000) -#define ADC_RegularExTrigConv_OPA ((uint32_t)0x00000010) - -/* ADC_InjectedExTrigConv_definition */ -#define ADC_InjectedExTrigConv_PD1_PA2 ((uint32_t)0x00000000) -#define ADC_InjectedExTrigConv_OPA ((uint32_t)0x00000020) - -/* ADC_Sample_mode_definition */ -#define ADC_Sample_Over_1M_Mode ((uint32_t)0x00000000) -#define ADC_Sample_NoOver_1M_Mode ((uint32_t)0x00000001) - -/* ADC_analog_watchdog_flags_definition */ -#define ADC_AnalogWatchdog_0_FLAG ((uint32_t)0x00000100) -#define ADC_AnalogWatchdog_1_FLAG ((uint32_t)0x00000200) -#define ADC_AnalogWatchdog_2_FLAG ((uint32_t)0x00000400) - -/* ADC_analog_watchdog_reset_enable_selection */ -#define ADC_AnalogWatchdog_0_RST_EN ((uint32_t)0x00000010) -#define ADC_AnalogWatchdog_1_RST_EN ((uint32_t)0x00000020) -#define ADC_AnalogWatchdog_2_RST_EN ((uint32_t)0x00000040) - - -void ADC_DeInit(ADC_TypeDef *ADCx); -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); -void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); -void ADC_ResetCalibration(ADC_TypeDef *ADCx); -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); -void ADC_StartCalibration(ADC_TypeDef *ADCx); -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); -void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); -void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); -void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); -void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); -void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_TKeyCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_Tkey_CurrentConfig(ADC_TypeDef *ADCx, uint32_t TKey_CurrentMode); -void ADC_RegularExTrigConvConfig(ADC_TypeDef *ADCx, uint32_t RegularExTrigConv); -void ADC_InjectedExTrigConvConfig(ADC_TypeDef *ADCx, uint32_t InjectedExTrigConv); -void ADC_TKey_ChannelxMulShieldCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState); -void ADC_TKey_MulShieldCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_Sample_ModeConfig(ADC_TypeDef *ADCx, uint32_t ADC_Sample_Mode); -void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -FlagStatus ADC_GetAnalogWatchdogFlagStatus(ADC_TypeDef *ADCx, uint32_t AnalogWatchdog_FLAG); -void ADC_ClearAnalogWatchdogFlag(ADC_TypeDef *ADCx, uint32_t AnalogWatchdog_FLAG); -void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog_x, FunctionalState NewState); -void ADC_AnalogWatchdogScanCmd(ADC_TypeDef *ADCx, FunctionalState NewState); - - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V00X_ADC_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_adc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/06 + * Description : This file contains all the functions prototypes for the + * ADC firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_ADC_H +#define __CH32V00X_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +} ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_PD3_PC2_OPA ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) + +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8) +#define ADC_Channel_OPA ((uint8_t)ADC_Channel_9) +#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_10) + +/* ADC_sampling_time */ +#define ADC_SampleTime_CyclesMode0 ((uint8_t)0x00) +#define ADC_SampleTime_CyclesMode1 ((uint8_t)0x01) +#define ADC_SampleTime_CyclesMode2 ((uint8_t)0x02) +#define ADC_SampleTime_CyclesMode3 ((uint8_t)0x03) +#define ADC_SampleTime_CyclesMode4 ((uint8_t)0x04) +#define ADC_SampleTime_CyclesMode5 ((uint8_t)0x05) +#define ADC_SampleTime_CyclesMode6 ((uint8_t)0x06) +#define ADC_SampleTime_CyclesMode7 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC1 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2_OPA ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +/* ADC_TKey_Current_definition */ +#define ADC_TKey_Current_mode0 ((uint32_t)0x00000000) +#define ADC_TKey_Current_mode1 ((uint32_t)0x02000000) + +/* ADC_RegularExTrigConv_definition */ +#define ADC_RegularExTrigConv_PD3_PC2 ((uint32_t)0x00000000) +#define ADC_RegularExTrigConv_OPA ((uint32_t)0x00000010) + +/* ADC_InjectedExTrigConv_definition */ +#define ADC_InjectedExTrigConv_PD1_PA2 ((uint32_t)0x00000000) +#define ADC_InjectedExTrigConv_OPA ((uint32_t)0x00000020) + +/* ADC_Sample_mode_definition */ +#define ADC_Sample_Over_1M_Mode ((uint32_t)0x00000000) +#define ADC_Sample_NoOver_1M_Mode ((uint32_t)0x00000001) + +/* ADC_analog_watchdog_flags_definition */ +#define ADC_AnalogWatchdog_0_FLAG ((uint32_t)0x00000100) +#define ADC_AnalogWatchdog_1_FLAG ((uint32_t)0x00000200) +#define ADC_AnalogWatchdog_2_FLAG ((uint32_t)0x00000400) + +/* ADC_analog_watchdog_reset_enable_selection */ +#define ADC_AnalogWatchdog_0_RST_EN ((uint32_t)0x00000010) +#define ADC_AnalogWatchdog_1_RST_EN ((uint32_t)0x00000020) +#define ADC_AnalogWatchdog_2_RST_EN ((uint32_t)0x00000040) + + +void ADC_DeInit(ADC_TypeDef *ADCx); +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_TKeyCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_Tkey_CurrentConfig(ADC_TypeDef *ADCx, uint32_t TKey_CurrentMode); +void ADC_RegularExTrigConvConfig(ADC_TypeDef *ADCx, uint32_t RegularExTrigConv); +void ADC_InjectedExTrigConvConfig(ADC_TypeDef *ADCx, uint32_t InjectedExTrigConv); +void ADC_TKey_ChannelxMulShieldCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState); +void ADC_TKey_MulShieldCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_Sample_ModeConfig(ADC_TypeDef *ADCx, uint32_t ADC_Sample_Mode); +void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetAnalogWatchdogFlagStatus(ADC_TypeDef *ADCx, uint32_t AnalogWatchdog_FLAG); +void ADC_ClearAnalogWatchdogFlag(ADC_TypeDef *ADCx, uint32_t AnalogWatchdog_FLAG); +void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog_x, FunctionalState NewState); +void ADC_AnalogWatchdogScanCmd(ADC_TypeDef *ADCx, FunctionalState NewState); + + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00X_ADC_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_dbgmcu.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_dbgmcu.h index 328869a..dd29f23 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_dbgmcu.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_dbgmcu.h @@ -1,41 +1,41 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_dbgmcu.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the - * DBGMCU firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_DBGMCU_H -#define __CH32V00X_DBGMCU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* CFGR0 Register */ -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) -#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) -#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) - -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -uint32_t __get_DEBUG_CR(void); -void __set_DEBUG_CR(uint32_t value); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -uint32_t DBGMCU_GetCHIPID( void ); -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00X_DBGMCU_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_dbgmcu.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file contains all the functions prototypes for the + * DBGMCU firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_DBGMCU_H +#define __CH32V00X_DBGMCU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* CFGR0 Register */ +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +uint32_t __get_DEBUG_CR(void); +void __set_DEBUG_CR(uint32_t value); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +uint32_t DBGMCU_GetCHIPID( void ); +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00X_DBGMCU_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_dma.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_dma.h index d5037f7..c03eb43 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_dma.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_dma.h @@ -1,177 +1,177 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_dma.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the - * DMA firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_DMA_H -#define __CH32V00X_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* DMA Init structure definition */ -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode. - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -} DMA_InitTypeDef; - -/* DMA_data_transfer_direction */ -#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) - -/* DMA_peripheral_incremented_mode */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) - -/* DMA_memory_incremented_mode */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) - -/* DMA_peripheral_data_size */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) - -/* DMA_memory_data_size */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) - -/* DMA_circular_normal_mode */ -#define DMA_Mode_Circular ((uint32_t)0x00000020) -#define DMA_Mode_Normal ((uint32_t)0x00000000) - -/* DMA_priority_level */ -#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) -#define DMA_Priority_High ((uint32_t)0x00002000) -#define DMA_Priority_Medium ((uint32_t)0x00001000) -#define DMA_Priority_Low ((uint32_t)0x00000000) - -/* DMA_memory_to_memory */ -#define DMA_M2M_Enable ((uint32_t)0x00004000) -#define DMA_M2M_Disable ((uint32_t)0x00000000) - -/* DMA_interrupts_definition */ -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) - -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) - -/* DMA_flags_definition */ -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) - - -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); -void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); -void DMA_ClearFlag(uint32_t DMAy_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMAy_IT); -void DMA_ClearITPendingBit(uint32_t DMAy_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V00X_DMA_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_dma.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file contains all the functions prototypes for the + * DMA firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_DMA_H +#define __CH32V00X_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + + +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00X_DMA_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_exti.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_exti.h index 07c9cf0..d1193a5 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_exti.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_exti.h @@ -1,78 +1,78 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_exti.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the - * EXTI firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_EXTI_H -#define __CH32V00X_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* EXTI mode enumeration */ -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -} EXTIMode_TypeDef; - -/* EXTI Trigger enumeration */ -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -} EXTITrigger_TypeDef; - -/* EXTI Init Structure definition */ -typedef struct -{ - uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -} EXTI_InitTypeDef; - -/* EXTI_Lines */ -#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */ -#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/ - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00X_EXTI_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_exti.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/08/02 + * Description : This file contains all the functions prototypes for the + * EXTI firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_EXTI_H +#define __CH32V00X_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitTypeDef; + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00X_EXTI_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_flash.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_flash.h index 8bdeb91..4be29f7 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_flash.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_flash.h @@ -1,146 +1,147 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_flash.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the FLASH - * firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_FLASH_H -#define __CH32V00X_FLASH_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* FLASH Status */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT, - FLASH_RDP, - FLASH_OP_RANGE_ERROR = 0xFD, - FLASH_ALIGN_ERROR = 0xFE, - FLASH_ADR_RANGE_ERROR = 0xFF, -} FLASH_Status; - -/* Flash_Latency */ -#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ - -/* Values to be used with CH32V00X devices (1page = 256Byte) */ -#define FLASH_WRProt_Pages0to7 ((uint32_t)0x00000001) /* Write protection of page 0 to 7 */ -#define FLASH_WRProt_Pages8to15 ((uint32_t)0x00000002) /* Write protection of page 8 to 15 */ -#define FLASH_WRProt_Pages16to23 ((uint32_t)0x00000004) /* Write protection of page 16 to 23 */ -#define FLASH_WRProt_Pages24to31 ((uint32_t)0x00000008) /* Write protection of page 24 to 31 */ -#define FLASH_WRProt_Pages32to39 ((uint32_t)0x00000010) /* Write protection of page 32 to 39 */ -#define FLASH_WRProt_Pages40to47 ((uint32_t)0x00000020) /* Write protection of page 40 to 47 */ -#define FLASH_WRProt_Pages48to55 ((uint32_t)0x00000040) /* Write protection of page 48 to 55 */ -#define FLASH_WRProt_Pages56to63 ((uint32_t)0x00000080) /* Write protection of page 56 to 63 */ -#define FLASH_WRProt_Pages64to71 ((uint32_t)0x00000100) /* Write protection of page 64 to 71 */ -#define FLASH_WRProt_Pages72to79 ((uint32_t)0x00000200) /* Write protection of page 72 to 79 */ -#define FLASH_WRProt_Pages80to87 ((uint32_t)0x00000400) /* Write protection of page 80 to 87 */ -#define FLASH_WRProt_Pages88to95 ((uint32_t)0x00000800) /* Write protection of page 88 to 95 */ -#define FLASH_WRProt_Pages96to103 ((uint32_t)0x00001000) /* Write protection of page 96 to 103 */ -#define FLASH_WRProt_Pages104to111 ((uint32_t)0x00002000) /* Write protection of page 104 to 111 */ -#define FLASH_WRProt_Pages112to119 ((uint32_t)0x00004000) /* Write protection of page 112 to 119 */ -#define FLASH_WRProt_Pages120to127 ((uint32_t)0x00008000) /* Write protection of page 120 to 127 */ -#define FLASH_WRProt_Pages128to135 ((uint32_t)0x00010000) /* Write protection of page 128 to 135 */ -#define FLASH_WRProt_Pages136to143 ((uint32_t)0x00020000) /* Write protection of page 136 to 143 */ -#define FLASH_WRProt_Pages144to151 ((uint32_t)0x00040000) /* Write protection of page 144 to 151 */ -#define FLASH_WRProt_Pages152to159 ((uint32_t)0x00080000) /* Write protection of page 152 to 159 */ -#define FLASH_WRProt_Pages160to167 ((uint32_t)0x00100000) /* Write protection of page 160 to 167 */ -#define FLASH_WRProt_Pages168to175 ((uint32_t)0x00200000) /* Write protection of page 168 to 175 */ -#define FLASH_WRProt_Pages176to183 ((uint32_t)0x00400000) /* Write protection of page 176 to 183 */ -#define FLASH_WRProt_Pages184to191 ((uint32_t)0x00800000) /* Write protection of page 184 to 191 */ -#define FLASH_WRProt_Pages192to199 ((uint32_t)0x01000000) /* Write protection of page 192 to 199 */ -#define FLASH_WRProt_Pages200to207 ((uint32_t)0x02000000) /* Write protection of page 200 to 207 */ -#define FLASH_WRProt_Pages208to215 ((uint32_t)0x04000000) /* Write protection of page 208 to 215 */ -#define FLASH_WRProt_Pages216to223 ((uint32_t)0x08000000) /* Write protection of page 216 to 223 */ -#define FLASH_WRProt_Pages224to231 ((uint32_t)0x10000000) /* Write protection of page 224 to 231 */ -#define FLASH_WRProt_Pages232to239 ((uint32_t)0x20000000) /* Write protection of page 232 to 239 */ -#define FLASH_WRProt_Pages240to247 ((uint32_t)0x40000000) /* Write protection of page 240 to 247 */ - -#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ - -/* Option_Bytes_IWatchdog */ -#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ -#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ - -/* Option_Bytes_nRST_STDBY */ -#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ - -/* Option_Bytes_RST_ENandDT */ -#define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable */ -#define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable and Ignore delay time 12ms */ -#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable and Ignore delay time 1ms */ -#define OB_RST_EN_DT128us ((uint16_t)0x0000) /* Reset IO enable and Ignore delay time 128us */ - -/* Option_Bytes_Power_ON_Start_Mode */ -#define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* Boot start after power on */ -#define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* User start after power on */ - -/* FLASH_Interrupts */ -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ -#define FLASH_IT_FWAKE ((uint32_t)0x00002000) /* FLASH Wake Up Interrupt source */ - -/* FLASH_Flags */ -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ -#define FLASH_FLAG_FWAKE ((uint32_t)0x00000040) /* FLASH Wake Up flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ - -/* System_Reset_Start_Mode */ -#define Start_Mode_USER ((uint32_t)0x00000000) -#define Start_Mode_BOOT ((uint32_t)0x00004000) - - -/*Functions used for all CH32V00X devices*/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); -FLASH_Status FLASH_EnableReadOutProtection(void); -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STDBY, uint16_t OB_RST, uint16_t OB_PowerON_Start_Mode); -uint32_t FLASH_GetUserOptionByte(void); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); -void FLASH_Unlock_Fast(void); -void FLASH_Lock_Fast(void); -void FLASH_BufReset(void); -void FLASH_BufLoad(uint32_t Address, uint32_t Data0); -void FLASH_ErasePage_Fast(uint32_t Page_Address); -void FLASH_ProgramPage_Fast(uint32_t Page_Address); -void SystemReset_StartMode(uint32_t Mode); -FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); -FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00X_FLASH_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_flash.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/04 + * Description : This file contains all the functions prototypes for the FLASH + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_FLASH_H +#define __CH32V00X_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_RDP, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ + +/* Values to be used with CH32V00X devices (1page = 256Byte) */ +#define FLASH_WRProt_Pages0to7 ((uint32_t)0x00000001) /* Write protection of page 0 to 7 */ +#define FLASH_WRProt_Pages8to15 ((uint32_t)0x00000002) /* Write protection of page 8 to 15 */ +#define FLASH_WRProt_Pages16to23 ((uint32_t)0x00000004) /* Write protection of page 16 to 23 */ +#define FLASH_WRProt_Pages24to31 ((uint32_t)0x00000008) /* Write protection of page 24 to 31 */ +#define FLASH_WRProt_Pages32to39 ((uint32_t)0x00000010) /* Write protection of page 32 to 39 */ +#define FLASH_WRProt_Pages40to47 ((uint32_t)0x00000020) /* Write protection of page 40 to 47 */ +#define FLASH_WRProt_Pages48to55 ((uint32_t)0x00000040) /* Write protection of page 48 to 55 */ +#define FLASH_WRProt_Pages56to63 ((uint32_t)0x00000080) /* Write protection of page 56 to 63 */ +#define FLASH_WRProt_Pages64to71 ((uint32_t)0x00000100) /* Write protection of page 64 to 71 */ +#define FLASH_WRProt_Pages72to79 ((uint32_t)0x00000200) /* Write protection of page 72 to 79 */ +#define FLASH_WRProt_Pages80to87 ((uint32_t)0x00000400) /* Write protection of page 80 to 87 */ +#define FLASH_WRProt_Pages88to95 ((uint32_t)0x00000800) /* Write protection of page 88 to 95 */ +#define FLASH_WRProt_Pages96to103 ((uint32_t)0x00001000) /* Write protection of page 96 to 103 */ +#define FLASH_WRProt_Pages104to111 ((uint32_t)0x00002000) /* Write protection of page 104 to 111 */ +#define FLASH_WRProt_Pages112to119 ((uint32_t)0x00004000) /* Write protection of page 112 to 119 */ +#define FLASH_WRProt_Pages120to127 ((uint32_t)0x00008000) /* Write protection of page 120 to 127 */ +#define FLASH_WRProt_Pages128to135 ((uint32_t)0x00010000) /* Write protection of page 128 to 135 */ +#define FLASH_WRProt_Pages136to143 ((uint32_t)0x00020000) /* Write protection of page 136 to 143 */ +#define FLASH_WRProt_Pages144to151 ((uint32_t)0x00040000) /* Write protection of page 144 to 151 */ +#define FLASH_WRProt_Pages152to159 ((uint32_t)0x00080000) /* Write protection of page 152 to 159 */ +#define FLASH_WRProt_Pages160to167 ((uint32_t)0x00100000) /* Write protection of page 160 to 167 */ +#define FLASH_WRProt_Pages168to175 ((uint32_t)0x00200000) /* Write protection of page 168 to 175 */ +#define FLASH_WRProt_Pages176to183 ((uint32_t)0x00400000) /* Write protection of page 176 to 183 */ +#define FLASH_WRProt_Pages184to191 ((uint32_t)0x00800000) /* Write protection of page 184 to 191 */ +#define FLASH_WRProt_Pages192to199 ((uint32_t)0x01000000) /* Write protection of page 192 to 199 */ +#define FLASH_WRProt_Pages200to207 ((uint32_t)0x02000000) /* Write protection of page 200 to 207 */ +#define FLASH_WRProt_Pages208to215 ((uint32_t)0x04000000) /* Write protection of page 208 to 215 */ +#define FLASH_WRProt_Pages216to223 ((uint32_t)0x08000000) /* Write protection of page 216 to 223 */ +#define FLASH_WRProt_Pages224to231 ((uint32_t)0x10000000) /* Write protection of page 224 to 231 */ +#define FLASH_WRProt_Pages232to239 ((uint32_t)0x20000000) /* Write protection of page 232 to 239 */ +#define FLASH_WRProt_Pages240to247 ((uint32_t)0x40000000) /* Write protection of page 240 to 247 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* Option_Bytes_RST_ENandDT */ +#define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable */ +#define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable and Ignore delay time 12ms */ +#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable and Ignore delay time 1ms */ +#define OB_RST_EN_DT128us ((uint16_t)0x0000) /* Reset IO enable and Ignore delay time 128us */ + +/* Option_Bytes_Power_ON_Start_Mode */ +#define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* Boot start after power on */ +#define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* User start after power on */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_FWAKE ((uint32_t)0x00002000) /* FLASH Wake Up Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_FWAKE ((uint32_t)0x00000040) /* FLASH Wake Up flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/* System_Reset_Start_Mode */ +#define Start_Mode_USER ((uint32_t)0x00000000) +#define Start_Mode_BOOT ((uint32_t)0x00004000) + + +/*Functions used for all CH32V00X devices*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_EnableReadOutProtection(void); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STDBY, uint16_t OB_RST, uint16_t OB_PowerON_Start_Mode); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_BufReset(void); +void FLASH_BufLoad(uint32_t Address, uint32_t Data0); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address); +void SystemReset_StartMode(uint32_t Mode); +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00X_FLASH_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_gpio.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_gpio.h index 0666f99..e5754d0 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_gpio.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_gpio.h @@ -1,159 +1,159 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_gpio.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the - * GPIO firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_GPIO_H -#define __CH32V00X_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* Output Maximum frequency selection */ -typedef enum -{ - GPIO_Speed_30MHz = 1, -} GPIOSpeed_TypeDef; - -/* Configuration Mode enumeration */ -typedef enum -{ - GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 -} GPIOMode_TypeDef; - -/* GPIO Init structure definition */ -typedef struct -{ - uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -} GPIO_InitTypeDef; - -/* Bit_SET and Bit_RESET enumeration */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -} BitAction; - -/* GPIO_pins_define */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_All ((uint16_t)0x00FF) /* All pins selected */ - -/* GPIO_Remap_define */ -#define GPIO_PartialRemap1_SPI1 ((uint32_t)0x08100001) /* SPI1 Partial Alternate Function mapping */ -#define GPIO_PartialRemap2_SPI1 ((uint32_t)0x08100002) /* SPI1 Partia2 Alternate Function mapping */ -#define GPIO_PartialRemap3_SPI1 ((uint32_t)0x08100003) /* SPI1 Partia3 Alternate Function mapping */ -#define GPIO_PartialRemap4_SPI1 ((uint32_t)0x08100004) /* SPI1 Partia4 Alternate Function mapping */ -#define GPIO_PartialRemap5_SPI1 ((uint32_t)0x08100005) /* SPI1 Partia5 Alternate Function mapping */ -#define GPIO_FullRemap_SPI1 ((uint32_t)0x08100006) /* SPI1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_I2C1 ((uint32_t)0x08130008) /* I2C1 Partia1 Alternate Function mapping */ -#define GPIO_PartialRemap2_I2C1 ((uint32_t)0x08130010) /* I2C1 Partia2 Alternate Function mapping */ -#define GPIO_PartialRemap3_I2C1 ((uint32_t)0x08130018) /* I2C1 Partia3 Alternate Function mapping */ -#define GPIO_FullRemap_I2C1 ((uint32_t)0x08130020) /* I2C1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_USART1 ((uint32_t)0x00160040) /* USART1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_USART1 ((uint32_t)0x00160080) /* USART1 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_USART1 ((uint32_t)0x001600C0) /* USART1 Partial3 Alternate Function mapping */ -#define GPIO_PartialRemap4_USART1 ((uint32_t)0x00160100) /* USART1 Partial4 Alternate Function mapping */ -#define GPIO_PartialRemap5_USART1 ((uint32_t)0x00160140) /* USART1 Partial5 Alternate Function mapping */ -#define GPIO_PartialRemap6_USART1 ((uint32_t)0x00160180) /* USART1 Partial6 Alternate Function mapping */ -#define GPIO_PartialRemap7_USART1 ((uint32_t)0x001601C0) /* USART1 Partial7 Alternate Function mapping */ -#define GPIO_PartialRemap8_USART1 ((uint32_t)0x00160200) /* USART1 Partial8 Alternate Function mapping */ -#define GPIO_FullRemap_USART1 ((uint32_t)0x00160240) /* USART1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x001A0400) /* TIM1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x001A0800) /* TIM1 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_TIM1 ((uint32_t)0x001A0C00) /* TIM1 Partial3 Alternate Function mapping */ -#define GPIO_PartialRemap4_TIM1 ((uint32_t)0x001A1000) /* TIM1 Partial4 Alternate Function mapping */ -#define GPIO_PartialRemap5_TIM1 ((uint32_t)0x001A1400) /* TIM1 Partial5 Alternate Function mapping */ -#define GPIO_PartialRemap6_TIM1 ((uint32_t)0x001A1800) /* TIM1 Partial6 Alternate Function mapping */ -#define GPIO_PartialRemap7_TIM1 ((uint32_t)0x001A1C00) /* TIM1 Partial7 Alternate Function mapping */ -#define GPIO_PartialRemap8_TIM1 ((uint32_t)0x001A2000) /* TIM1 Partial8 Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x001A2400) /* TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x084E0001) /* TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x084E0002) /* TIM2 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_TIM2 ((uint32_t)0x084E0003) /* TIM2 Partial3 Alternate Function mapping */ -#define GPIO_PartialRemap4_TIM2 ((uint32_t)0x084E0004) /* TIM2 Partial4 Alternate Function mapping */ -#define GPIO_PartialRemap5_TIM2 ((uint32_t)0x084E0005) /* TIM2 Partial5 Alternate Function mapping */ -#define GPIO_PartialRemap6_TIM2 ((uint32_t)0x084E0006) /* TIM2 Partial6 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x084E0007) /* TIM2 Full Alternate Function mapping */ -#define GPIO_Remap_PA1_2 ((uint32_t)0x00200002) /* PA1 and PA2 Alternate Function mapping */ -#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200004) /* ADC1 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200008) /* ADC1 External Trigger Regular Conversion remapping */ -#define GPIO_PartialRemap1_USART2 ((uint32_t)0x08240010) /* USART2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_USART2 ((uint32_t)0x08240020) /* USART2 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_USART2 ((uint32_t)0x08240030) /* USART2 Partial3 Alternate Function mapping */ -#define GPIO_PartialRemap4_USART2 ((uint32_t)0x08240040) /* USART2 Partial4 Alternate Function mapping */ -#define GPIO_PartialRemap5_USART2 ((uint32_t)0x08240050) /* USART2 Partial5 Alternate Function mapping */ -#define GPIO_FullRemap_USART2 ((uint32_t)0x08240060) /* USART2 Full Alternate Function mapping */ -#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */ -#define GPIO_Remap_SDI_Disable ((uint32_t)0x08300400) /* SDI Disabled */ - -/* GPIO_Port_Sources */ -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOB ((uint8_t)0x01) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) -#define GPIO_PortSourceGPIOD ((uint8_t)0x03) - -/* GPIO_Pin_sources */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) - -void GPIO_DeInit(GPIO_TypeDef *GPIOx); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_EventOutputCmd(FunctionalState NewState); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_IPD_Unused(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00X_GPIO_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_gpio.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file contains all the functions prototypes for the + * GPIO firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_GPIO_H +#define __CH32V00X_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_30MHz = 1, +} GPIOSpeed_TypeDef; + +/* Configuration Mode enumeration */ +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +} GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_All ((uint16_t)0x00FF) /* All pins selected */ + +/* GPIO_Remap_define */ +#define GPIO_PartialRemap1_SPI1 ((uint32_t)0x08100001) /* SPI1 Partial Alternate Function mapping */ +#define GPIO_PartialRemap2_SPI1 ((uint32_t)0x08100002) /* SPI1 Partia2 Alternate Function mapping */ +#define GPIO_PartialRemap3_SPI1 ((uint32_t)0x08100003) /* SPI1 Partia3 Alternate Function mapping */ +#define GPIO_PartialRemap4_SPI1 ((uint32_t)0x08100004) /* SPI1 Partia4 Alternate Function mapping */ +#define GPIO_PartialRemap5_SPI1 ((uint32_t)0x08100005) /* SPI1 Partia5 Alternate Function mapping */ +#define GPIO_FullRemap_SPI1 ((uint32_t)0x08100006) /* SPI1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_I2C1 ((uint32_t)0x08130008) /* I2C1 Partia1 Alternate Function mapping */ +#define GPIO_PartialRemap2_I2C1 ((uint32_t)0x08130010) /* I2C1 Partia2 Alternate Function mapping */ +#define GPIO_PartialRemap3_I2C1 ((uint32_t)0x08130018) /* I2C1 Partia3 Alternate Function mapping */ +#define GPIO_FullRemap4_I2C1 ((uint32_t)0x08130020) /* I2C1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART1 ((uint32_t)0x00160040) /* USART1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART1 ((uint32_t)0x00160080) /* USART1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART1 ((uint32_t)0x001600C0) /* USART1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_USART1 ((uint32_t)0x00160100) /* USART1 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_USART1 ((uint32_t)0x00160140) /* USART1 Partial5 Alternate Function mapping */ +#define GPIO_PartialRemap6_USART1 ((uint32_t)0x00160180) /* USART1 Partial6 Alternate Function mapping */ +#define GPIO_PartialRemap7_USART1 ((uint32_t)0x001601C0) /* USART1 Partial7 Alternate Function mapping */ +#define GPIO_PartialRemap8_USART1 ((uint32_t)0x00160200) /* USART1 Partial8 Alternate Function mapping */ +#define GPIO_FullRemap_USART1 ((uint32_t)0x00160240) /* USART1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x001A0400) /* TIM1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x001A0800) /* TIM1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM1 ((uint32_t)0x001A0C00) /* TIM1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM1 ((uint32_t)0x001A1000) /* TIM1 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM1 ((uint32_t)0x001A1400) /* TIM1 Partial5 Alternate Function mapping */ +#define GPIO_PartialRemap6_TIM1 ((uint32_t)0x001A1800) /* TIM1 Partial6 Alternate Function mapping */ +#define GPIO_PartialRemap7_TIM1 ((uint32_t)0x001A1C00) /* TIM1 Partial7 Alternate Function mapping */ +#define GPIO_PartialRemap8_TIM1 ((uint32_t)0x001A2000) /* TIM1 Partial8 Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001A2400) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x084E0001) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x084E0002) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM2 ((uint32_t)0x084E0003) /* TIM2 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM2 ((uint32_t)0x084E0004) /* TIM2 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM2 ((uint32_t)0x084E0005) /* TIM2 Partial5 Alternate Function mapping */ +#define GPIO_PartialRemap6_TIM2 ((uint32_t)0x084E0006) /* TIM2 Partial6 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x084E0007) /* TIM2 Full Alternate Function mapping */ +#define GPIO_Remap_PA1_2 ((uint32_t)0x00200002) /* PA1 and PA2 Alternate Function mapping */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200004) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200008) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_PartialRemap1_USART2 ((uint32_t)0x08240010) /* USART2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART2 ((uint32_t)0x08240020) /* USART2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART2 ((uint32_t)0x08240030) /* USART2 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_USART2 ((uint32_t)0x08240040) /* USART2 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_USART2 ((uint32_t)0x08240050) /* USART2 Partial5 Alternate Function mapping */ +#define GPIO_FullRemap_USART2 ((uint32_t)0x08240060) /* USART2 Full Alternate Function mapping */ +#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */ +#define GPIO_Remap_SDI_Disable ((uint32_t)0x08300400) /* SDI Disabled */ + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) + +void GPIO_DeInit(GPIO_TypeDef *GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_IPD_Unused(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00X_GPIO_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_i2c.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_i2c.h index b74557c..14e8f18 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_i2c.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_i2c.h @@ -1,415 +1,415 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_i2c.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the - * I2C firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_I2C_H -#define __CH32V00X_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* I2C Init structure definition */ -typedef struct -{ - uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /* Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /* Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /* Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -} I2C_InitTypeDef; - -/* I2C_mode */ -#define I2C_Mode_I2C ((uint16_t)0x0000) - -/* I2C_duty_cycle_in_fast_mode */ -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ - -/* I2C_acknowledgement */ -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) - -/* I2C_transfer_direction */ -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) - -/* I2C_acknowledged_address */ -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) - -/* I2C_registers */ -#define I2C_Register_CTLR1 ((uint8_t)0x00) -#define I2C_Register_CTLR2 ((uint8_t)0x04) -#define I2C_Register_OADDR1 ((uint8_t)0x08) -#define I2C_Register_OADDR2 ((uint8_t)0x0C) -#define I2C_Register_DATAR ((uint8_t)0x10) -#define I2C_Register_STAR1 ((uint8_t)0x14) -#define I2C_Register_STAR2 ((uint8_t)0x18) -#define I2C_Register_CKCFGR ((uint8_t)0x1C) - -/* I2C_PEC_position */ -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) - -/* I2C_NACK_position */ -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) - -/* I2C_interrupts_definition */ -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) - -/* I2C_interrupts_definition */ -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -/* STAR2 register flags */ -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/* STAR1 register flags */ -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -/****************I2C Master Events (Events grouped in order of communication)********************/ - -/******************************************************************************************************************** - * @brief Start communicate - * - * After master use I2C_GenerateSTART() function sending the START condition,the master - * has to wait for event 5(the Start condition has been correctly - * released on the I2C bus ). - * - */ -/* EVT5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/******************************************************************************************************************** - * @brief Address Acknowledge - * - * When start condition correctly released on the bus(check EVT5), the - * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate - * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will be set: - * - * - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (after generating the START - * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. - * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent - * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part - * of the 10-bit address (LSB) . Then master should wait for event 6. - * - * - */ - -/* EVT6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* EVT9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/******************************************************************************************************************** - * @brief Communication events - * - * If START condition has generated and slave address - * been acknowledged. then the master has to check one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EVT7 then use - * I2C_ReceiveData() function to read the data received from the slave . - * - * 2) Master Transmitter mode: The master use I2C_SendData() function to send data - * then to wait on event EVT8 or EVT8_2. - * These two events are similar: - * - EVT8 means that the data has been written in the data register and is - * being shifted out. - * - EVT8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EVT8 is sufficient for the application. - * Using EVT8_2 will leads to a slower communication speed but will more reliable . - * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission - * - * - * Note: - * In case the user software does not guarantee that this event EVT7 is managed before - * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. - * - * - */ - -/* Master Receive mode */ -/* EVT7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master Transmitter mode*/ -/* EVT8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* EVT8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - -/******************I2C Slave Events (Events grouped in order of communication)******************/ - -/******************************************************************************************************************** - * @brief Start Communicate events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a start condition of master device generate on the bus. - * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. - * - * - * - * a) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * b) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * c) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* EVT1 */ -/* a) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* b) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* c) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/******************************************************************************************************************** - * @brief Communication events - * - * Wait on one of these events when EVT1 has already been checked : - * - * - Slave Receiver mode: - * - EVT2--The device is expecting to receive a data byte . - * - EVT4--The device is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EVT3--When a byte has been transmitted by the slave and the Master is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee - * the EVT3 is managed before the current byte end of transfer The second one can optionally - * be used. - * - EVT3_2--When the master sends a NACK to tell slave device that data transmission - * shall end . The slave device has to stop sending - * data bytes and wait a Stop condition from bus. - * - * Note: - * If the user software does not guarantee that the event 2 is - * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time . - * In this case the communication will be slower. - * - */ - -/* Slave Receiver mode*/ -/* EVT2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* EVT4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave Transmitter mode -----------------------*/ -/* EVT3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* EVT3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - - -void I2C_DeInit(I2C_TypeDef *I2Cx); -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); -void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); -void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); -void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); -void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); - - -/***************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * profit the application requirements and constraints: - * - * - * a) First way: - * Using I2C_CheckEvent() function: - * It compares the status registers (STARR1 and STAR2) content to a given event - * (can be the combination of more flags). - * If the current status registers includes the given flags will return SUCCESS. - * and if the current status registers miss flags will returns ERROR. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (CH32V03RM). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs besides to the monitored error, - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * in corrupted state. it is suggeted to use error interrupts to monitor the error - * events and handle them in IRQ handler. - * - * - * Note: - * The following functions are recommended for error management: : - * - I2C_ITConfig() main function of configure and enable the error interrupts. - * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions - * to determine which error occurred. - * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() - * \ I2C_GenerateStop() will be use to clear the error flag and source, - * and return to correct communication status. - * - * - * b) Second way: - * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. - * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). - * - When to use: - * - * - This function is suitable for the same applications above but it - * don't have the limitations of I2C_GetFlagStatus() function . - * The returned value could be compared to events already defined in the - * library (CH32V00X_i2c.h) or to custom values defined by user. - * - This function can be used to monitor the status of multiple flags simultaneously. - * - Contrary to the I2C_CheckEvent () function, this function can choose the time to - * accept the event according to the user's needs (when all event flags are set and - * no other flags are set, or only when the required flags are set) - * - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * c) Third way: - * Using the function I2C_GetFlagStatus() get the status of - * one single flag . - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed . - * - * - Limitations: - * - Call this function to access the status register. Some flag bits may be cleared. - * - Function may need to be called twice or more in order to monitor one single event. - */ - - - -/********************************************************* - * - * a) Basic state monitoring(First way) - ******************************************************** - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/********************************************************* - * - * b) Advanced state monitoring(Second way:) - ******************************************************** - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/********************************************************* - * - * c) Flag-based state monitoring(Third way) - ********************************************************* - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - -void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V00X_I2C_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_i2c.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file contains all the functions prototypes for the + * I2C firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_I2C_H +#define __CH32V00X_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* STAR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* STAR1 register flags */ +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode -----------------------*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef *I2Cx); +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); + + +/***************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * profit the application requirements and constraints: + * + * + * a) First way: + * Using I2C_CheckEvent() function: + * It compares the status registers (STARR1 and STAR2) content to a given event + * (can be the combination of more flags). + * If the current status registers includes the given flags will return SUCCESS. + * and if the current status registers miss flags will returns ERROR. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (CH32V03RM). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs besides to the monitored error, + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * in corrupted state. it is suggeted to use error interrupts to monitor the error + * events and handle them in IRQ handler. + * + * + * Note: + * The following functions are recommended for error management: : + * - I2C_ITConfig() main function of configure and enable the error interrupts. + * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions + * to determine which error occurred. + * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() + * \ I2C_GenerateStop() will be use to clear the error flag and source, + * and return to correct communication status. + * + * + * b) Second way: + * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. + * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). + * - When to use: + * + * - This function is suitable for the same applications above but it + * don't have the limitations of I2C_GetFlagStatus() function . + * The returned value could be compared to events already defined in the + * library (CH32V00X_i2c.h) or to custom values defined by user. + * - This function can be used to monitor the status of multiple flags simultaneously. + * - Contrary to the I2C_CheckEvent () function, this function can choose the time to + * accept the event according to the user's needs (when all event flags are set and + * no other flags are set, or only when the required flags are set) + * + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * c) Third way: + * Using the function I2C_GetFlagStatus() get the status of + * one single flag . + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed . + * + * - Limitations: + * - Call this function to access the status register. Some flag bits may be cleared. + * - Function may need to be called twice or more in order to monitor one single event. + */ + + + +/********************************************************* + * + * a) Basic state monitoring(First way) + ******************************************************** + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/********************************************************* + * + * b) Advanced state monitoring(Second way:) + ******************************************************** + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/********************************************************* + * + * c) Flag-based state monitoring(Third way) + ********************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00X_I2C_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_iwdg.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_iwdg.h index f3fb3fd..654c831 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_iwdg.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_iwdg.h @@ -1,50 +1,50 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_iwdg.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the - * IWDG firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_IWDG_H -#define __CH32V00X_IWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* IWDG_WriteAccess */ -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) - -/* IWDG_prescaler */ -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) - -/* IWDG_Flag */ -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) - -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_Enable(void); -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00X_IWDG_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_iwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file contains all the functions prototypes for the + * IWDG firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_IWDG_H +#define __CH32V00X_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00X_IWDG_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_misc.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_misc.h index 3e2f287..594a4a4 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_misc.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_misc.h @@ -1,74 +1,74 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_misc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the - * miscellaneous firmware library functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_MISC_H -#define __CH32V00X_MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include - -/* CSR_INTSYSCR_INEST_definition */ -#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ -#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ - -/* Check the configuration of CSR(0x804) in the startup file(.S) - * interrupt nesting enable(CSR-0x804 bit1 = 1) - * priority - bit[7] - Preemption Priority - * bit[6] - Sub priority - * bit[5:0] - Reserve - * interrupt nesting disable(CSR-0x804 bit1 = 0) - * priority - bit[7:6] - Sub priority - * bit[5:0] - Reserve - */ - -#ifndef INTSYSCR_INEST -#define INTSYSCR_INEST INTSYSCR_INEST_EN -#endif - -/* NVIC Init Structure definition - * interrupt nesting enable(CSR-0x804 bit1 = 1) - * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. - * NVIC_IRQChannelSubPriority - range from 0 to 1. - * - * interrupt nesting disable(CSR-0x804 bit1 = 0) - * NVIC_IRQChannelPreemptionPriority - range is 0. - * NVIC_IRQChannelSubPriority - range from 0 to 3. - * - */ -typedef struct -{ - uint8_t NVIC_IRQChannel; - uint8_t NVIC_IRQChannelPreemptionPriority; - uint8_t NVIC_IRQChannelSubPriority; - FunctionalState NVIC_IRQChannelCmd; -} NVIC_InitTypeDef; - -/* Preemption_Priority_Group */ -#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) -#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ -#else -#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ -#endif - - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); - -#ifdef __cplusplus -} -#endif - -#endif - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_misc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file contains all the functions prototypes for the + * miscellaneous firmware library functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_MISC_H +#define __CH32V00X_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include + +/* CSR_INTSYSCR_INEST_definition */ +#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ + +/* Check the configuration of CSR(0x804) in the startup file(.S) + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6] - Sub priority + * bit[5:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:6] - Sub priority + * bit[5:0] - Reserve + */ + +#ifndef INTSYSCR_INEST +#define INTSYSCR_INEST INTSYSCR_INEST_EN +#endif + +/* NVIC Init Structure definition + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 1. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Preemption_Priority_Group */ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#else +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ +#endif + + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_opa.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_opa.h index 64a0f5a..ab2e152 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_opa.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_opa.h @@ -1,373 +1,373 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_opa.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the - * OPA firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_OPA_H -#define __CH32V00X_OPA_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32v00X.h" - -/* OPA_PSEL_POLL_enumeration */ -typedef enum -{ - CHP_OPA_POLL_OFF = 0, - CHP_OPA_POLL_ON, -} OPA_PSEL_POLL_TypeDef; - -/* OPA_PSEL_POLL_NUM_enumeration */ -typedef enum -{ - CHP_POLL_NUM_1 = 0, - CHP_POLL_NUM_2, - CHP_POLL_NUM_3 -} OPA_PSEL_POLL_NUM_TypeDef; - -/* OPA_RST_EN_enumeration */ -typedef enum -{ - RST_OPA_OFF = 0, - RST_OPA_ON, -} OPA_RST_EN_TypeDef; - -/* OPA_SETUP_CFG_enumeration */ -typedef enum -{ - OPA_SETUP_CFG_0 = 0, - OPA_SETUP_CFG_1, - OPA_SETUP_CFG_2 = 3, -} OPA_SETUP_CFG_TypeDef; - -/* OPA_POLL_AUTO_enumeration */ -typedef enum -{ - OPA_POLL_AUTO_OFF = 0, - OPA_POLL_AUTO_ON, -} OPA_POLL_AUTO_TypeDef; - -/* OPA_OUT_IE_enumeration */ -typedef enum -{ - OUT_IE_OFF= 0, - OUT_IE_ON, -} OPA_OUT_IE_TypeDef; - -/* OPA_NMI_IE_enumeration */ -typedef enum -{ - NMI_IE_OFF = 0, - NMI_IE_ON, -} OPA_NMI_IE_TypeDef; - -/* OPA_POLL_CH1_definition */ -typedef enum -{ - OPA_POLL_CH1_PA2 = 0, - OPA_POLL_CH1_PD7, - OPA_POLL_CH1_PD3, - OPA_POLL_CH1_PD1 -} OPA_POLL_CH1_TypeDef; - -/* OPA_POLL_CH2_definition */ -typedef enum -{ - OPA_POLL_CH2_PA2 = 0, - OPA_POLL_CH2_PD7, - OPA_POLL_CH2_PD3, - OPA_POLL_CH2_PD1 -} OPA_POLL_CH2_TypeDef; - -/* OPA_POLL_CH3_definition */ -typedef enum -{ - OPA_POLL_CH3_PA2 = 0, - OPA_POLL_CH3_PD7, - OPA_POLL_CH3_PD3, - OPA_POLL_CH3_PD1 -} OPA_POLL_CH3_TypeDef; - -/* OPA_POLL_SEL_enumeration */ -typedef enum -{ - OPA_POLL_SEL_SOFT = 0, - OPA_POLL_SEL_TIM1_CH4, - OPA_POLL_SEL_TIM2_CH4, - OPA_POLL_SEL_TIM3_CH1, - OPA_POLL_SEL_TIM3_CH2 -} OPA_POLL_SEL_TypeDef; - -/* OPA_out_channel_enumeration */ -typedef enum -{ - OUT_IO_OUT0 = 0, - OUT_IO_OUT1, - OUT_CMP2_ONLY = 3 -} OPA_Mode_TypeDef; - -/* OPA_PSEL_enumeration */ -typedef enum -{ - CHP0 = 0, - CHP1, - CHP2, - CHP3, -} OPA_PSEL_TypeDef; - -/* OPA_NSEL_enumeration */ -typedef enum -{ - CHN0 = 0, - CHN1, - CHN_PGA_4xIN = 3, - CHN_PGA_8xIN, - CHN_PGA_16xIN, - CHN_PGA_32xIN, - CHN_OFF, -} OPA_NSEL_TypeDef; - -/* OPA_FB_enumeration */ -typedef enum -{ - FB_OFF = 0, - FB_ON -} OPA_FB_TypeDef; - -/* OPA_PGADIF_enumeration */ -typedef enum -{ - PGADIF_OFF = 0, - PGADIF_ON -} OPA_PGADIF_TypeDef; - -/* OPA_PGA_VBEN_enumeration */ -typedef enum -{ - PGA_VBEN_OFF = 0, - PGA_VBEN_ON, -} OPA_PGA_VBEN_TypeDef; - -/* OPA_PGA_VBSEL_enumeration */ -typedef enum -{ - PGA_VBSEL_VDD_DIV2 = 0, - PGA_VBSEL_VDD_DIV4, -} OPA_PGA_VBSEL_TypeDef; - -/* OPA_VBCMPSEL_enumeration */ -typedef enum -{ - VBCMPSEL_Mode_0 = 0, - VBCMPSEL_Mode_1, - VBCMPSEL_Mode_2, - VBCMPSEL_OFF -} OPA_VBCMPSEL_TypeDef; - -/* OPA_HIGH_SPEED_enumeration */ -typedef enum -{ - HS_OFF = 0, - HS_ON -} OPA_HIGH_SPEED_TypeDef; - -/* OPA Init Structure definition */ -typedef struct -{ - OPA_PSEL_POLL_TypeDef PSEL_POLL;/* Specifies the positive channel poll of OPA */ - OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of OPA poll */ - OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */ - OPA_SETUP_CFG_TypeDef SETUP_CFG;/* Specifies the ADC conversion interval for the OPA */ - OPA_POLL_AUTO_TypeDef POLL_AT; /* specifies auto Poll of OPA */ - OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */ - OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NMI interrupt of OPA */ - OPA_POLL_CH1_TypeDef POLL_CH1; /* Specifies the poll channel 1 of OPA */ - OPA_POLL_CH2_TypeDef POLL_CH2; /* Specifies the poll channel 2 of OPA */ - OPA_POLL_CH3_TypeDef POLL_CH3; /* Specifies the poll channel 3 of OPA */ - OPA_POLL_SEL_TypeDef POLL_SEL; /* specifies Poll Trigger Event of OPA */ - OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ - OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ - OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ - OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ - OPA_PGADIF_TypeDef PGADIF; /* OPA with NSEL1 for use as a PGA */ - OPA_PGA_VBEN_TypeDef PGA_VBEN; /* Enable PGA mode positive reference voltage */ - OPA_PGA_VBSEL_TypeDef PGA_VBSEL;/* Specifies the positive reference voltage for PGA mode */ - OPA_VBCMPSEL_TypeDef VBCMPSEL; /* Specifies the CMP2 negative reference voltage */ - OPA_HIGH_SPEED_TypeDef OPA_HS; /* specifies high speed mode enable of OPA */ -} OPA_InitTypeDef; - -/* CMP_member_enumeration */ -typedef enum -{ - CMP1 = 0, - CMP2 -} CMP_Num_TypeDef; - -/* CMP_PSEL_POLL_enumeration */ -typedef enum -{ - CHP_CMP1_POLL_OFF = 0, - CHP_CMP1_POLL_ON, -} CMP_PSEL_POLL_TypeDef; - -/* OPA_PSEL_POLL_NUM_enumeration */ -typedef enum -{ - CMP_POLL_NUM_1 = 0, - CMP_POLL_NUM_2, - CMP_POLL_NUM_3 -} CMP_PSEL_POLL_NUM_TypeDef; - -/* CMP_OUT_IE_enumeration */ -typedef enum -{ - CMP_OUT_IE_OFF= 0, - CMP_OUT_IE_ON -} CMP_OUT_IE_TypeDef; - -/* CMP_CNT_IE_enumeration */ -typedef enum -{ - CMP_CNT_IE_OFF = 0, - CMP_CNT_IE_ON, -} CMP_CNT_IE_TypeDef; - -/* CMP_POLL_CH1_definition */ -typedef enum -{ - CMP_POLL_CH1_PC5 = 0, - CMP_POLL_CH1_PB3, - CMP_POLL_CH1_PD2 -} CMP_POLL_CH1_TypeDef; - -/* CMP_POLL_CH2_definition */ -typedef enum -{ - CMP_POLL_CH2_PC5 = 0, - CMP_POLL_CH2_PB3, - CMP_POLL_CH2_PD2 -} CMP_POLL_CH2_TypeDef; - -/* CMP_POLL_CH3_definition */ -typedef enum -{ - CMP_POLL_CH3_PC5 = 0, - CMP_POLL_CH3_PB3, - CMP_POLL_CH3_PD2 -} CMP_POLL_CH3_TypeDef; - -/* CMP_out_mode_enumeration */ -typedef enum -{ - OUT_IO0 = 0, - OUT_IO_TIM1_CH4, - OUT_IO_TIM2_CH4 -} CMP_OutMode_TypeDef; - -/* CMP_NSEL_enumeration */ -typedef enum -{ - CMP_CHN0 = 0, - CMP_CHN1, - CMP_CHN2 -} CMP_NSEL_TypeDef; - -/* CMP_PSEL_enumeration */ -typedef enum -{ - CMP_CHP0 = 0, - CMP_CHP1, - CMP_CHP2 -} CMP_PSEL_TypeDef; - -/* CMP_HYEN_enumeration */ -typedef enum -{ - CMP_HYEN_OFF = 0, - CMP_HYEN_ON, -} CMP_HYEN_TypeDef; - -/* CMP_RMID_enumeration */ -typedef enum -{ - CMP_RMID_OFF = 0, - CMP_RMID_ON -} CMP_RMID_TypeDef; - -/* CMP1 Init Structure definition */ -typedef struct -{ - uint16_t CMP_POLL_Interval; /* CMP polling interval = (CMP_POLL_Interval+1)*1us - This parameter must range from 0 to 0x1FF.*/ - CMP_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of CMP */ - CMP_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the poll members of CMP */ - CMP_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of CMP */ - CMP_CNT_IE_TypeDef CNT_IE; /* Specifies the interrupt at the end of the CMP1 polling interval */ - CMP_POLL_CH1_TypeDef POLL_CH1; /* Specifies the poll channel 1 of CMP */ - CMP_POLL_CH2_TypeDef POLL_CH2; /* Specifies the poll channel 2 of CMP */ - CMP_POLL_CH3_TypeDef POLL_CH3; /* Specifies the poll channel 3 of CMP */ - CMP_OutMode_TypeDef CMP_Out_Mode; /* Specifies the out mode of CMP */ - CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ - CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ - CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */ - CMP_RMID_TypeDef RMID; /* Specifies the virtual center point of the CMP1 positive input channel */ -} CMP1_InitTypeDef; - -/* CMP_FILT_Length_definition */ -#define CMP_FILT_Len_0 ((uint32_t)0x00000000) -#define CMP_FILT_Len_1 ((uint32_t)0x02000000) - -/* TIM1_brake_source_definition */ -#define TIM1_Brake_Source_IO ((uint32_t)0x00000000) -#define TIM1_Brake_Source_CMP1 ((uint32_t)0x04000000) -#define TIM1_Brake_Source_CMP2 ((uint32_t)0x08000000) -#define TIM1_Brake_Source_OPA ((uint32_t)0x0C000000) - -/* CMP_OUT_POLL_FLAG */ -#define CMP_FLAG_OUT_POLL_CH_1 ((uint32_t)0x00001000) -#define CMP_FLAG_OUT_POLL_CH_2 ((uint32_t)0x00002000) -#define CMP_FLAG_OUT_POLL_CH_3 ((uint32_t)0x00004000) -#define CMP_FLAG_POLL_END ((uint32_t)0x00008000) - -/* OPA_OUT_POLL_FLAG */ -#define OPA_FLAG_OUT_POLL_CH_1 ((uint32_t)0x00001000) -#define OPA_FLAG_OUT_POLL_CH_2 ((uint32_t)0x00002000) -#define OPA_FLAG_OUT_POLL_CH_3 ((uint32_t)0x00004000) - - -void OPA_Unlock(void); -void OPA_Lock(void); -void OPA_CMP_POLL_Lock(void); -void OPA_CMP_Unlock(void); -void OPA_CMP_Lock(void); -void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); -void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); -void OPA_CMP1_Init(CMP1_InitTypeDef *CMP_InitStruct); -void OPA_CMP1_StructInit(CMP1_InitTypeDef *CMP_InitStruct); -void OPA_Cmd(FunctionalState NewState); -void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); -void OPA_SystemReset_Cmd(FunctionalState NewState); -void OPA_CMP_SystemReset_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); -void OPA_CMP_FILT_Cmd(FunctionalState NewState); -void OPA_CMP_FILT_LEN_Config(uint32_t FILT_Len); -void OPA_CMP_TIM1_BKINConfig(uint32_t Brake_Source); -FlagStatus OPA_GetFlagStatus(uint32_t OPA_FLAG); -FlagStatus OPA_CMP_GetFlagStatus(uint32_t CMP_FLAG); -void OPA_ClearFlag(uint32_t OPA_FLAG); -void OPA_CMP_ClearFlag(uint32_t CMP_FLAG); -void OPA_SoftwareStartPollCmd(FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_opa.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file contains all the functions prototypes for the + * OPA firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_OPA_H +#define __CH32V00X_OPA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v00X.h" + +/* OPA_PSEL_POLL_enumeration */ +typedef enum +{ + CHP_OPA_POLL_OFF = 0, + CHP_OPA_POLL_ON, +} OPA_PSEL_POLL_TypeDef; + +/* OPA_PSEL_POLL_NUM_enumeration */ +typedef enum +{ + CHP_POLL_NUM_1 = 0, + CHP_POLL_NUM_2, + CHP_POLL_NUM_3 +} OPA_PSEL_POLL_NUM_TypeDef; + +/* OPA_RST_EN_enumeration */ +typedef enum +{ + RST_OPA_OFF = 0, + RST_OPA_ON, +} OPA_RST_EN_TypeDef; + +/* OPA_SETUP_CFG_enumeration */ +typedef enum +{ + OPA_SETUP_CFG_0 = 0, + OPA_SETUP_CFG_1, + OPA_SETUP_CFG_2 = 3, +} OPA_SETUP_CFG_TypeDef; + +/* OPA_POLL_AUTO_enumeration */ +typedef enum +{ + OPA_POLL_AUTO_OFF = 0, + OPA_POLL_AUTO_ON, +} OPA_POLL_AUTO_TypeDef; + +/* OPA_OUT_IE_enumeration */ +typedef enum +{ + OUT_IE_OFF= 0, + OUT_IE_ON, +} OPA_OUT_IE_TypeDef; + +/* OPA_NMI_IE_enumeration */ +typedef enum +{ + NMI_IE_OFF = 0, + NMI_IE_ON, +} OPA_NMI_IE_TypeDef; + +/* OPA_POLL_CH1_definition */ +typedef enum +{ + OPA_POLL_CH1_PA2 = 0, + OPA_POLL_CH1_PD7, + OPA_POLL_CH1_PD3, + OPA_POLL_CH1_PD1 +} OPA_POLL_CH1_TypeDef; + +/* OPA_POLL_CH2_definition */ +typedef enum +{ + OPA_POLL_CH2_PA2 = 0, + OPA_POLL_CH2_PD7, + OPA_POLL_CH2_PD3, + OPA_POLL_CH2_PD1 +} OPA_POLL_CH2_TypeDef; + +/* OPA_POLL_CH3_definition */ +typedef enum +{ + OPA_POLL_CH3_PA2 = 0, + OPA_POLL_CH3_PD7, + OPA_POLL_CH3_PD3, + OPA_POLL_CH3_PD1 +} OPA_POLL_CH3_TypeDef; + +/* OPA_POLL_SEL_enumeration */ +typedef enum +{ + OPA_POLL_SEL_SOFT = 0, + OPA_POLL_SEL_TIM1_CH4, + OPA_POLL_SEL_TIM2_CH4, + OPA_POLL_SEL_TIM3_CH1, + OPA_POLL_SEL_TIM3_CH2 +} OPA_POLL_SEL_TypeDef; + +/* OPA_out_channel_enumeration */ +typedef enum +{ + OUT_IO_OUT0 = 0, + OUT_IO_OUT1, + OUT_CMP2_ONLY = 3 +} OPA_Mode_TypeDef; + +/* OPA_PSEL_enumeration */ +typedef enum +{ + CHP0 = 0, + CHP1, + CHP2, + CHP3, +} OPA_PSEL_TypeDef; + +/* OPA_NSEL_enumeration */ +typedef enum +{ + CHN0 = 0, + CHN1, + CHN_PGA_4xIN = 3, + CHN_PGA_8xIN, + CHN_PGA_16xIN, + CHN_PGA_32xIN, + CHN_OFF, +} OPA_NSEL_TypeDef; + +/* OPA_FB_enumeration */ +typedef enum +{ + FB_OFF = 0, + FB_ON +} OPA_FB_TypeDef; + +/* OPA_PGADIF_enumeration */ +typedef enum +{ + PGADIF_OFF = 0, + PGADIF_ON +} OPA_PGADIF_TypeDef; + +/* OPA_PGA_VBEN_enumeration */ +typedef enum +{ + PGA_VBEN_OFF = 0, + PGA_VBEN_ON, +} OPA_PGA_VBEN_TypeDef; + +/* OPA_PGA_VBSEL_enumeration */ +typedef enum +{ + PGA_VBSEL_VDD_DIV2 = 0, + PGA_VBSEL_VDD_DIV4, +} OPA_PGA_VBSEL_TypeDef; + +/* OPA_VBCMPSEL_enumeration */ +typedef enum +{ + VBCMPSEL_Mode_0 = 0, + VBCMPSEL_Mode_1, + VBCMPSEL_Mode_2, + VBCMPSEL_OFF +} OPA_VBCMPSEL_TypeDef; + +/* OPA_HIGH_SPEED_enumeration */ +typedef enum +{ + HS_OFF = 0, + HS_ON +} OPA_HIGH_SPEED_TypeDef; + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_PSEL_POLL_TypeDef PSEL_POLL;/* Specifies the positive channel poll of OPA */ + OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of OPA poll */ + OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */ + OPA_SETUP_CFG_TypeDef SETUP_CFG;/* Specifies the ADC conversion interval for the OPA */ + OPA_POLL_AUTO_TypeDef POLL_AT; /* specifies auto Poll of OPA */ + OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */ + OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NMI interrupt of OPA */ + OPA_POLL_CH1_TypeDef POLL_CH1; /* Specifies the poll channel 1 of OPA */ + OPA_POLL_CH2_TypeDef POLL_CH2; /* Specifies the poll channel 2 of OPA */ + OPA_POLL_CH3_TypeDef POLL_CH3; /* Specifies the poll channel 3 of OPA */ + OPA_POLL_SEL_TypeDef POLL_SEL; /* specifies Poll Trigger Event of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ + OPA_PGADIF_TypeDef PGADIF; /* OPA with NSEL1 for use as a PGA */ + OPA_PGA_VBEN_TypeDef PGA_VBEN; /* Enable PGA mode positive reference voltage */ + OPA_PGA_VBSEL_TypeDef PGA_VBSEL;/* Specifies the positive reference voltage for PGA mode */ + OPA_VBCMPSEL_TypeDef VBCMPSEL; /* Specifies the CMP2 negative reference voltage */ + OPA_HIGH_SPEED_TypeDef OPA_HS; /* specifies high speed mode enable of OPA */ +} OPA_InitTypeDef; + +/* CMP_member_enumeration */ +typedef enum +{ + CMP1 = 0, + CMP2 +} CMP_Num_TypeDef; + +/* CMP_PSEL_POLL_enumeration */ +typedef enum +{ + CHP_CMP1_POLL_OFF = 0, + CHP_CMP1_POLL_ON, +} CMP_PSEL_POLL_TypeDef; + +/* OPA_PSEL_POLL_NUM_enumeration */ +typedef enum +{ + CMP_POLL_NUM_1 = 0, + CMP_POLL_NUM_2, + CMP_POLL_NUM_3 +} CMP_PSEL_POLL_NUM_TypeDef; + +/* CMP_OUT_IE_enumeration */ +typedef enum +{ + CMP_OUT_IE_OFF= 0, + CMP_OUT_IE_ON +} CMP_OUT_IE_TypeDef; + +/* CMP_CNT_IE_enumeration */ +typedef enum +{ + CMP_CNT_IE_OFF = 0, + CMP_CNT_IE_ON, +} CMP_CNT_IE_TypeDef; + +/* CMP_POLL_CH1_definition */ +typedef enum +{ + CMP_POLL_CH1_PC5 = 0, + CMP_POLL_CH1_PB3, + CMP_POLL_CH1_PD2 +} CMP_POLL_CH1_TypeDef; + +/* CMP_POLL_CH2_definition */ +typedef enum +{ + CMP_POLL_CH2_PC5 = 0, + CMP_POLL_CH2_PB3, + CMP_POLL_CH2_PD2 +} CMP_POLL_CH2_TypeDef; + +/* CMP_POLL_CH3_definition */ +typedef enum +{ + CMP_POLL_CH3_PC5 = 0, + CMP_POLL_CH3_PB3, + CMP_POLL_CH3_PD2 +} CMP_POLL_CH3_TypeDef; + +/* CMP_out_mode_enumeration */ +typedef enum +{ + OUT_IO0 = 0, + OUT_IO_TIM1_CH4, + OUT_IO_TIM2_CH4 +} CMP_OutMode_TypeDef; + +/* CMP_NSEL_enumeration */ +typedef enum +{ + CMP_CHN0 = 0, + CMP_CHN1, + CMP_CHN2 +} CMP_NSEL_TypeDef; + +/* CMP_PSEL_enumeration */ +typedef enum +{ + CMP_CHP0 = 0, + CMP_CHP1, + CMP_CHP2 +} CMP_PSEL_TypeDef; + +/* CMP_HYEN_enumeration */ +typedef enum +{ + CMP_HYEN_OFF = 0, + CMP_HYEN_ON, +} CMP_HYEN_TypeDef; + +/* CMP_RMID_enumeration */ +typedef enum +{ + CMP_RMID_OFF = 0, + CMP_RMID_ON +} CMP_RMID_TypeDef; + +/* CMP1 Init Structure definition */ +typedef struct +{ + uint16_t CMP_POLL_Interval; /* CMP polling interval = (CMP_POLL_Interval+1)*1us + This parameter must range from 0 to 0x1FF.*/ + CMP_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of CMP */ + CMP_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the poll members of CMP */ + CMP_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of CMP */ + CMP_CNT_IE_TypeDef CNT_IE; /* Specifies the interrupt at the end of the CMP1 polling interval */ + CMP_POLL_CH1_TypeDef POLL_CH1; /* Specifies the poll channel 1 of CMP */ + CMP_POLL_CH2_TypeDef POLL_CH2; /* Specifies the poll channel 2 of CMP */ + CMP_POLL_CH3_TypeDef POLL_CH3; /* Specifies the poll channel 3 of CMP */ + CMP_OutMode_TypeDef CMP_Out_Mode; /* Specifies the out mode of CMP */ + CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ + CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ + CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */ + CMP_RMID_TypeDef RMID; /* Specifies the virtual center point of the CMP1 positive input channel */ +} CMP1_InitTypeDef; + +/* CMP_FILT_Length_definition */ +#define CMP_FILT_Len_0 ((uint32_t)0x00000000) +#define CMP_FILT_Len_1 ((uint32_t)0x02000000) + +/* TIM1_brake_source_definition */ +#define TIM1_Brake_Source_IO ((uint32_t)0x00000000) +#define TIM1_Brake_Source_CMP1 ((uint32_t)0x04000000) +#define TIM1_Brake_Source_CMP2 ((uint32_t)0x08000000) +#define TIM1_Brake_Source_OPA ((uint32_t)0x0C000000) + +/* CMP_OUT_POLL_FLAG */ +#define CMP_FLAG_OUT_POLL_CH_1 ((uint32_t)0x00001000) +#define CMP_FLAG_OUT_POLL_CH_2 ((uint32_t)0x00002000) +#define CMP_FLAG_OUT_POLL_CH_3 ((uint32_t)0x00004000) +#define CMP_FLAG_POLL_END ((uint32_t)0x00008000) + +/* OPA_OUT_POLL_FLAG */ +#define OPA_FLAG_OUT_POLL_CH_1 ((uint32_t)0x00001000) +#define OPA_FLAG_OUT_POLL_CH_2 ((uint32_t)0x00002000) +#define OPA_FLAG_OUT_POLL_CH_3 ((uint32_t)0x00004000) + + +void OPA_Unlock(void); +void OPA_Lock(void); +void OPA_CMP_POLL_Lock(void); +void OPA_CMP_Unlock(void); +void OPA_CMP_Lock(void); +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); +void OPA_CMP1_Init(CMP1_InitTypeDef *CMP_InitStruct); +void OPA_CMP1_StructInit(CMP1_InitTypeDef *CMP_InitStruct); +void OPA_Cmd(FunctionalState NewState); +void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); +void OPA_SystemReset_Cmd(FunctionalState NewState); +void OPA_CMP_SystemReset_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); +void OPA_CMP_FILT_Cmd(FunctionalState NewState); +void OPA_CMP_FILT_LEN_Config(uint32_t FILT_Len); +void OPA_CMP_TIM1_BKINConfig(uint32_t Brake_Source); +FlagStatus OPA_GetFlagStatus(uint32_t OPA_FLAG); +FlagStatus OPA_CMP_GetFlagStatus(uint32_t CMP_FLAG); +void OPA_ClearFlag(uint32_t OPA_FLAG); +void OPA_CMP_ClearFlag(uint32_t CMP_FLAG); +void OPA_SoftwareStartPollCmd(FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_pwr.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_pwr.h index 2db9443..51209ab 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_pwr.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_pwr.h @@ -1,66 +1,66 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_pwr.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the PWR - * firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_PWR_H -#define __CH32V00X_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* PVD_detection_level */ -#define PWR_PVDLevel_0 ((uint32_t)0x00000000) -#define PWR_PVDLevel_1 ((uint32_t)0x00000020) -#define PWR_PVDLevel_2 ((uint32_t)0x00000040) -#define PWR_PVDLevel_3 ((uint32_t)0x00000060) - -/* PWR_AWU_Prescaler */ -#define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000) -#define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002) -#define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003) -#define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004) -#define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005) -#define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006) -#define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007) -#define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008) -#define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009) -#define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A) -#define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B) -#define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C) -#define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D) -#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E) -#define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F) - -/* STOP_mode_entry */ -#define PWR_STANDBYEntry_WFI ((uint8_t)0x01) -#define PWR_STANDBYEntry_WFE ((uint8_t)0x02) - -/* PWR_Flag */ -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) - -void PWR_DeInit(void); -void PWR_PVDCmd(FunctionalState NewState); -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_AutoWakeUpCmd(FunctionalState NewState); -void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler); -void PWR_AWU_SetWindowValue(uint8_t WindowValue); -void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_FLASH_LP_Cmd(FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00X_PWR_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_pwr.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/07 + * Description : This file contains all the functions prototypes for the PWR + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_PWR_H +#define __CH32V00X_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* PVD_detection_level */ +#define PWR_PVDLevel_0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_3 ((uint32_t)0x00000060) + +/* PWR_AWU_Prescaler */ +#define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000) +#define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002) +#define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003) +#define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004) +#define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005) +#define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006) +#define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007) +#define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008) +#define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009) +#define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A) +#define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B) +#define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C) +#define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D) +#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E) +#define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F) + +/* STOP_mode_entry */ +#define PWR_STANDBYEntry_WFI ((uint8_t)0x01) +#define PWR_STANDBYEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + +void PWR_DeInit(void); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_AutoWakeUpCmd(FunctionalState NewState); +void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler); +void PWR_AWU_SetWindowValue(uint8_t WindowValue); +void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_FLASH_LP_Cmd(FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00X_PWR_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_rcc.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_rcc.h index a34ecab..c843163 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_rcc.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_rcc.h @@ -1,177 +1,177 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_rcc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the RCC firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_RCC_H -#define __CH32V00X_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* RCC_Exported_Types */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ - uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ -} RCC_ClocksTypeDef; - -/* HSE_configuration */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00010000) -#define RCC_HSE_Bypass ((uint32_t)0x00040000) - -/* PLL_entry_clock_source */ -#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000) -#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00010000) - -/* System_clock_source */ -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) - -/* HB_clock_source */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) -#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) -#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) -#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) -#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) -#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) - -/* RCC_Interrupt_source */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) -#define RCC_IT_SYSCLK_FAIL ((uint8_t)0x02) - -/* ADC_clock_source */ -#define RCC_PCLK2_Div1 ((uint32_t)0x80000000) -#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) -#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) -#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) -#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) -#define RCC_PCLK2_Div12 ((uint32_t)0x0000A000) -#define RCC_PCLK2_Div16 ((uint32_t)0x0000E000) -#define RCC_PCLK2_Div24 ((uint32_t)0x0000A800) -#define RCC_PCLK2_Div32 ((uint32_t)0x0000E800) -#define RCC_PCLK2_Div48 ((uint32_t)0x0000B000) -#define RCC_PCLK2_Div64 ((uint32_t)0x0000F000) -#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800) -#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800) - -/* HB_peripheral */ -#define RCC_HBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_HBPeriph_SRAM ((uint32_t)0x00000004) - -/* PB2_peripheral */ -#define RCC_PB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_PB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_PB2Periph_GPIOB ((uint32_t)0x00000008) -#define RCC_PB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_PB2Periph_GPIOD ((uint32_t)0x00000020) -#define RCC_PB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_PB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_PB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_PB2Periph_USART2 ((uint32_t)0x00002000) -#define RCC_PB2Periph_USART1 ((uint32_t)0x00004000) - -/* PB1_peripheral */ -#define RCC_PB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_PB1Periph_TIM3 ((uint32_t)0x00000004) -#define RCC_PB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_PB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_PB1Periph_PWR ((uint32_t)0x10000000) - -/* Clock_source_to_output_on_MCO_pin */ -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) -#define RCC_MCO_HSE ((uint8_t)0x06) -#define RCC_MCO_PLLCLK ((uint8_t)0x07) - -/* RCC_Flag */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_SYSCFAL ((uint8_t)0x68) -#define RCC_FLAG_ADCRST ((uint8_t)0x77) -#define RCC_FLAG_OPCMRST ((uint8_t)0x79) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) - -/* SysTick_clock_source */ -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) - -/* RCC_HSE_Current_Level */ -#define RCC_HSE_C_Level0 ((uint32_t)0x00000000) -#define RCC_HSE_C_Level1 ((uint32_t)0x00400000) -#define RCC_HSE_C_Level2 ((uint32_t)0x00800000) -#define RCC_HSE_C_Level3 ((uint32_t)0x00C00000) - -/* ADC_clock_H_Level_Duty_Cycle */ -#define RCC_ADC_H_Level_Mode0 ((uint32_t)0x00000000) -#define RCC_ADC_H_Level_Mode1 ((uint32_t)0x10000000) - - -void RCC_DeInit(void); -void RCC_HSEConfig(uint32_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); -void RCC_LSICmd(FunctionalState NewState); -void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); -void RCC_HBPeriphClockCmd(uint32_t RCC_HBPeriph, FunctionalState NewState); -void RCC_PB2PeriphClockCmd(uint32_t RCC_PB2Periph, FunctionalState NewState); -void RCC_PB1PeriphClockCmd(uint32_t RCC_PB1Periph, FunctionalState NewState); -void RCC_PB2PeriphResetCmd(uint32_t RCC_PB2Periph, FunctionalState NewState); -void RCC_PB1PeriphResetCmd(uint32_t RCC_PB1Periph, FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCO); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); -void RCC_ClockMonitorCmd(FunctionalState NewState); -void RCC_HSE_LP_Cmd(FunctionalState NewState); -void RCC_HSI_LP_Cmd(FunctionalState NewState); -void RCC_HSECurrentConfig(uint32_t RCC_HSECurrent); -void RCC_ADCCLKDutyCycleConfig(uint32_t RCC_DutyCycle); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00X_RCC_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_rcc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file provides all the RCC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_RCC_H +#define __CH32V00X_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ +} RCC_ClocksTypeDef; + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00010000) + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* HB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) +#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) +#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) +#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) +#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) +#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) +#define RCC_IT_SYSCLK_FAIL ((uint8_t)0x02) + +/* ADC_clock_source */ +#define RCC_PCLK2_Div1 ((uint32_t)0x80000000) +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define RCC_PCLK2_Div12 ((uint32_t)0x0000A000) +#define RCC_PCLK2_Div16 ((uint32_t)0x0000E000) +#define RCC_PCLK2_Div24 ((uint32_t)0x0000A800) +#define RCC_PCLK2_Div32 ((uint32_t)0x0000E800) +#define RCC_PCLK2_Div48 ((uint32_t)0x0000B000) +#define RCC_PCLK2_Div64 ((uint32_t)0x0000F000) +#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800) +#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800) + +/* HB_peripheral */ +#define RCC_HBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_HBPeriph_SRAM ((uint32_t)0x00000004) + +/* PB2_peripheral */ +#define RCC_PB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_PB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_PB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_PB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_PB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_PB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_PB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_PB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_PB2Periph_USART2 ((uint32_t)0x00002000) +#define RCC_PB2Periph_USART1 ((uint32_t)0x00004000) + +/* PB1_peripheral */ +#define RCC_PB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_PB1Periph_TIM3 ((uint32_t)0x00000004) +#define RCC_PB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_PB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_PB1Periph_PWR ((uint32_t)0x10000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK ((uint8_t)0x07) + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_SYSCFAL ((uint8_t)0x68) +#define RCC_FLAG_ADCRST ((uint8_t)0x77) +#define RCC_FLAG_OPCMRST ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +/* RCC_HSE_Current_Level */ +#define RCC_HSE_C_Level0 ((uint32_t)0x00000000) +#define RCC_HSE_C_Level1 ((uint32_t)0x00400000) +#define RCC_HSE_C_Level2 ((uint32_t)0x00800000) +#define RCC_HSE_C_Level3 ((uint32_t)0x00C00000) + +/* ADC_clock_H_Level_Duty_Cycle */ +#define RCC_ADC_H_Level_Mode0 ((uint32_t)0x00000000) +#define RCC_ADC_H_Level_Mode1 ((uint32_t)0x10000000) + + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSICmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); +void RCC_HBPeriphClockCmd(uint32_t RCC_HBPeriph, FunctionalState NewState); +void RCC_PB2PeriphClockCmd(uint32_t RCC_PB2Periph, FunctionalState NewState); +void RCC_PB1PeriphClockCmd(uint32_t RCC_PB1Periph, FunctionalState NewState); +void RCC_PB2PeriphResetCmd(uint32_t RCC_PB2Periph, FunctionalState NewState); +void RCC_PB1PeriphResetCmd(uint32_t RCC_PB1Periph, FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); +void RCC_ClockMonitorCmd(FunctionalState NewState); +void RCC_HSE_LP_Cmd(FunctionalState NewState); +void RCC_HSI_LP_Cmd(FunctionalState NewState); +void RCC_HSECurrentConfig(uint32_t RCC_HSECurrent); +void RCC_ADCCLKDutyCycleConfig(uint32_t RCC_DutyCycle); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00X_RCC_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_spi.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_spi.h index 07cc7be..84f2e1f 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_spi.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_spi.h @@ -1,153 +1,154 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_spi.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the - * SPI firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_SPI_H -#define __CH32V00X_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* SPI Init structure definition */ -typedef struct -{ - uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /* Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /* Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /* Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB bit. */ - - uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ -} SPI_InitTypeDef; - -/* SPI_data_direction */ -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) - -/* SPI_mode */ -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) - -/* SPI_data_size */ -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) - -/* SPI_Clock_Polarity */ -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) - -/* SPI_Clock_Phase */ -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) - -/* SPI_Slave_Select_management */ -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) - -/* SPI_BaudRate_Prescaler */ -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) - -/* SPI_MSB_LSB transmission */ -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) - -/* SPI_I2S_DMA_transfer_requests */ -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) - -/* SPI_NSS_internal_software_management */ -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) - -/* SPI_CRC_Transmit_Receive */ -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) - -/* SPI_direction_transmit_receive */ -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) - -/* SPI_I2S_interrupts_definition */ -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) - -/* SPI_I2S_flags_definition */ -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) - -void SPI_I2S_DeInit(SPI_TypeDef *SPIx); -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); -void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); -void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); -void SPI_TransmitCRC(SPI_TypeDef *SPIx); -void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); -void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); -void SPI_HS_RX_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V00X_SPI_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_spi.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/05 + * Description : This file contains all the functions prototypes for the + * SPI firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_SPI_H +#define __CH32V00X_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity + When using SPI slave mode to send data, the CPOL bit should be set to 1 */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB bit. */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +} SPI_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002)//When using SPI slave mode to send data, the CPOL bit should be set to 1. + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + +void SPI_I2S_DeInit(SPI_TypeDef *SPIx); +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef *SPIx); +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); +void SPI_HS_RX_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00X_SPI_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_tim.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_tim.h index 67b17a4..1f6eb0a 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_tim.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_tim.h @@ -1,529 +1,529 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_tim.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the - * TIM firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_TIM_H -#define __CH32V00X_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* TIM Time Base Init structure definition */ -typedef struct -{ - uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF. - @note This parameter is valid for TIM1 and TIM2. */ - - uint16_t TIM_CounterMode; /* Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode. - @note This parameter is valid for TIM1 ,TIM2 and TIM3. */ - - uint16_t TIM_Period; /* Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. - @note This parameter is valid for TIM1 ,TIM2 and TIM3. */ - - uint16_t TIM_ClockDivision; /* Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD - @note This parameter is valid for TIM1 and TIM2. */ - - uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1. */ -} TIM_TimeBaseInitTypeDef; - -/* TIM Output Compare Init structure definition */ -typedef struct -{ - uint16_t TIM_OCMode; /* Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes - @note This parameter is valid for TIM1 and TIM2. */ - - uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state - @note This parameter is valid for TIM1 and TIM2. */ - - uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_state - @note This parameter is valid only for TIM1 and TIM2. */ - - uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF - @note This parameter is valid for TIM1 and TIM2. */ - - uint16_t TIM_OCPolarity; /* Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid for TIM1 and TIM2. */ - - uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1. */ - - uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1. */ -} TIM_OCInitTypeDef; - -/* TIM Input Capture Init structure definition */ -typedef struct -{ - uint16_t TIM_Channel; /* Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel - @note This parameter is valid for TIM1 and TIM2. */ - - uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity - @note This parameter is valid for TIM1 and TIM2. */ - - uint16_t TIM_ICSelection; /* Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection - @note This parameter is valid for TIM1 and TIM2. */ - - uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler - @note This parameter is valid for TIM1 and TIM2. */ - - uint16_t TIM_ICFilter; /* Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF - @note This parameter is valid for TIM1 and TIM2. */ -} TIM_ICInitTypeDef; - -/* BDTR structure definition */ -typedef struct -{ - uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state - @note This parameter is valid only for TIM1. */ - - uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. - This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state - @note This parameter is valid only for TIM1. */ - - uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. - This parameter can be a value of @ref Lock_level - @note This parameter is valid only for TIM1. */ - - uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF - @note This parameter is valid for TIM1. */ - - uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref Break_Input_enable_disable - @note This parameter is valid only for TIM1. */ - - uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref Break_Polarity - @note This parameter is valid only for TIM1. */ - - uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset - @note This parameter is valid only for TIM1. */ -} TIM_BDTRInitTypeDef; - -/* TIM_Output_Compare_and_PWM_modes */ -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) - -/* TIM_One_Pulse_Mode */ -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) - -/* TIM_Channel */ -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -/* TIM_Clock_Division_CKD */ -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) - -/* TIM_Counter_Mode */ -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) - -/* TIM_Output_Compare_Polarity */ -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) - -/* TIM_Output_Compare_N_Polarity */ -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) - -/* TIM_Output_Compare_state */ -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) - -/* TIM_Output_Compare_N_state */ -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) - -/* TIM_Capture_Compare_state */ -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) - -/* TIM_Capture_Compare_N_state */ -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) - -/* Break_Input_enable_disable */ -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) - -/* Break_Polarity */ -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) - -/* TIM_AOE_Bit_Set_Reset */ -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) - -/* Lock_level */ -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) - -/* OSSI_Off_State_Selection_for_Idle_mode_state */ -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) - -/* OSSR_Off_State_Selection_for_Run_mode_state */ -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Idle_State */ -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Output_Compare_N_Idle_State */ -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Input_Capture_Polarity */ -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) - -/* TIM_Input_Capture_Selection */ -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ - -/* TIM_Input_Capture_Prescaler */ -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ - -/* TIM_interrupt_sources */ -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) - -/* TIM_DMA_Base_address */ -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) - -/* TIM_DMA_Burst_Length */ -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) - -/* TIM_DMA_sources */ -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) - -/* TIM_External_Trigger_Prescaler */ -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) - -/* TIM_Internal_Trigger_Selection */ -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) - -/* TIM_TIx_External_Clock_Source */ -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/* TIM_External_Trigger_Polarity */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) - -/* TIM_Prescaler_Reload_Mode */ -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) - -/* TIM_Forced_Action */ -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) - -/* TIM_Encoder_Mode */ -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) - -/* TIM_Event_Source */ -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) - -/* TIM_Update_Source */ -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ - or the setting of UG bit, or an update generation \ - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ - -/* TIM_Output_Compare_Preload_State */ -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Fast_State */ -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Clear_State */ -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) - -/* TIM_Trigger_Output_Source */ -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) - -/* TIM_Slave_Mode */ -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) - -/* TIM_Master_Slave_Mode */ -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) - -/* TIM_Flags */ -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) - -/* TIM_Legacy */ -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers - -void TIM_DeInit(TIM_TypeDef *TIMx); -void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); -void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); -void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_InternalClockConfig(TIM_TypeDef *TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); -void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); -void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); -void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); -void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); -void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); -void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); -void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); -void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); -void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); -void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); -void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); -void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); -uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); -uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); -void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_DeadTimeConfig(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint8_t DeadTime); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V00X_TIM_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_tim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_TIM_H +#define __CH32V00X_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF. + @note This parameter is valid for TIM1 and TIM2. */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode. + @note This parameter is valid for TIM1 ,TIM2 and TIM3. */ + + uint16_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. + @note This parameter is valid for TIM1 ,TIM2 and TIM3. */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD + @note This parameter is valid for TIM1 and TIM2. */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes + @note This parameter is valid for TIM1 and TIM2. */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state + @note This parameter is valid for TIM1 and TIM2. */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM2. */ + + uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF + @note This parameter is valid for TIM1 and TIM2. */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid for TIM1 and TIM2. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel + @note This parameter is valid for TIM1 and TIM2. */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity + @note This parameter is valid for TIM1 and TIM2. */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection + @note This parameter is valid for TIM1 and TIM2. */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler + @note This parameter is valid for TIM1 and TIM2. */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF + @note This parameter is valid for TIM1 and TIM2. */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF + @note This parameter is valid for TIM1. */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset + @note This parameter is valid only for TIM1. */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef *TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_DeadTimeConfig(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint8_t DeadTime); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00X_TIM_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_usart.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_usart.h index 090eedb..6943b4b 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_usart.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_usart.h @@ -1,147 +1,147 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_usart.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the - * USART firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_USART_H -#define __CH32V00X_USART_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* USART Init Structure definition */ -typedef struct -{ - uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /* Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/* USART_Word_Length */ -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -/* USART_Stop_Bits */ -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) - -/* USART_Parity */ -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) - -/* USART_Mode */ -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) - -/* USART_Hardware_Flow_Control */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) - -/* USART_Interrupt_definition */ -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) - -#define USART_IT_ORE USART_IT_ORE_ER - -/* USART_DMA_Requests */ -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) - -/* USART_WakeUp_methods */ -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) - -/* USART_LIN_Break_Detection_Length */ -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) - -/* USART_IrDA_Low_Power */ -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) - -/* USART_Flags */ -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) - -void USART_DeInit(USART_TypeDef *USARTx); -void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); -void USART_StructInit(USART_InitTypeDef *USART_InitStruct); -void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); -void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); -void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef *USARTx); -void USART_SendBreak(USART_TypeDef *USARTx); -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); -void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00X_USART_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_usart.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file contains all the functions prototypes for the + * USART firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_USART_H +#define __CH32V00X_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +void USART_DeInit(USART_TypeDef *USARTx); +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); +void USART_StructInit(USART_InitTypeDef *USART_InitStruct); +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef *USARTx); +void USART_SendBreak(USART_TypeDef *USARTx); +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00X_USART_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_wwdg.h b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_wwdg.h index 20be0e2..d9e952c 100644 --- a/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_wwdg.h +++ b/system/CH32VM00X/SRC/Peripheral/inc/ch32v00X_wwdg.h @@ -1,41 +1,41 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_wwdg.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file contains all the functions prototypes for the WWDG - * firmware library. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#ifndef __CH32V00X_WWDG_H -#define __CH32V00X_WWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* WWDG_Prescaler */ -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) - -void WWDG_DeInit(void); -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); -void WWDG_Enable(uint8_t Counter); -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __CH32V00X_WWDG_H */ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_wwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file contains all the functions prototypes for the WWDG + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_WWDG_H +#define __CH32V00X_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00X_WWDG_H */ diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_adc.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_adc.c index dc0e185..1def0d9 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_adc.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_adc.c @@ -1,1367 +1,1283 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_adc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the ADC firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* ADC DISCNUM mask */ -#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) -#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) - -/* ADC JAUTO mask */ -#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) -#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) - -/* ADC AWDCH mask */ -#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) - -/* CTLR1 register Mask */ -#define CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) - -/* ADC ADON mask */ -#define CTLR2_ADON_Set ((uint32_t)0x00000001) -#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CTLR2_DMA_Set ((uint32_t)0x00000100) -#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) - -/* ADC RSTCAL mask */ -#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) - -/* ADC CAL mask */ -#define CTLR2_CAL_Set ((uint32_t)0x00000004) - -/* ADC SWSTART mask */ -#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) - -/* ADC EXTTRIG mask */ -#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) - -/* ADC JEXTSEL mask */ -#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTART mask */ -#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) - -/* CTLR2 register Mask */ -#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) - -/* ADC SQx mask */ -#define RSQR3_SQ_Set ((uint32_t)0x0000001F) -#define RSQR2_SQ_Set ((uint32_t)0x0000001F) -#define RSQR1_SQ_Set ((uint32_t)0x0000001F) - -/* RSQR1 register Mask */ -#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define ISQR_JSQ_Set ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define ISQR_JL_Set ((uint32_t)0x00300000) -#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) -#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) - -/* ADC IDATARx registers offset */ -#define IDATAR_Offset ((uint8_t)0x28) - -/********************************************************************* - * @fn ADC_DeInit - * - * @brief Deinitializes the ADCx peripheral registers to their default - * reset values. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return none - */ -void ADC_DeInit(ADC_TypeDef *ADCx) -{ - RCC_PB2PeriphResetCmd(RCC_PB2Periph_ADC1, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_ADC1, DISABLE); -} - -/********************************************************************* - * @fn ADC_Init - * - * @brief Initializes the ADCx peripheral according to the specified - * parameters in the ADC_InitStruct. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); - ADCx->CTLR1 = tmpreg1; - - tmpreg1 = ADCx->CTLR2; - tmpreg1 &= CTLR2_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - ADCx->CTLR2 = tmpreg1; - - tmpreg1 = ADCx->RSQR1; - tmpreg1 &= RSQR1_CLEAR_Mask; - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); - tmpreg1 |= (uint32_t)tmpreg2 << 20; - ADCx->RSQR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_StructInit - * - * @brief Fills each ADC_InitStruct member with its default value. - * - * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) -{ - ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO; - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStruct->ADC_NbrOfChannel = 1; -} - -/********************************************************************* - * @fn ADC_Cmd - * - * @brief Enables or disables the specified ADC peripheral. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_ADON_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_ADON_Reset; - } -} - -/********************************************************************* - * @fn ADC_DMACmd - * - * @brief Enables or disables the specified ADC DMA request. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_DMA_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_DMA_Reset; - } -} - -/********************************************************************* - * @fn ADC_ITConfig - * - * @brief Enables or disables the specified ADC interrupts. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)ADC_IT; - - if(NewState != DISABLE) - { - ADCx->CTLR1 |= itmask; - } - else - { - ADCx->CTLR1 &= (~(uint32_t)itmask); - } -} - -/********************************************************************* - * @fn ADC_ResetCalibration - * - * @brief Resets the selected ADC calibration registers. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return none - */ -void ADC_ResetCalibration(ADC_TypeDef *ADCx) -{ - ADCx->CTLR2 |= CTLR2_RSTCAL_Set; -} - -/********************************************************************* - * @fn ADC_GetResetCalibrationStatus - * - * @brief Gets the selected ADC reset calibration registers status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_StartCalibration - * - * @brief Starts the selected ADC calibration process. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return None - */ -void ADC_StartCalibration(ADC_TypeDef *ADCx) -{ - ADCx->CTLR2 |= CTLR2_CAL_Set; -} - -/********************************************************************* - * @fn ADC_GetCalibrationStatus - * - * @brief Gets the selected ADC calibration status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_SoftwareStartConvCmd - * - * @brief Enables or disables the selected ADC software start conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartConvStatus - * - * @brief Gets the selected ADC Software start conversion Status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_DiscModeChannelCountConfig - * - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * Number - specifies the discontinuous mode regular channel - * count value(1-8). - * - * @return None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_DISCNUM_Reset; - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - ADCx->CTLR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_DiscModeCmd - * - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_DISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_DISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_RegularChannelConfig - * - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_Vrefint - ADC Channel8 selected. - * ADC_Channel_OPA - ADC Channel9 selected. - * ADC_Channel_Vcalint - ADC Channel10 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_CyclesMode0 - Sample time equal to 3.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 3.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode1 - Sample time equal to 7.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 7.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode2 - Sample time equal to 11.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 13.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode3 - Sample time equal to 19.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 28.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode4 - Sample time equal to 35.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 41.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode5 - Sample time equal to 55.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 55.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode6 - Sample time equal to 71.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 71.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode7 - Sample time equal to 239.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 239.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * - * @return None - */ -void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - if(Rank < 7) - { - tmpreg1 = ADCx->RSQR3; - tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - tmpreg1 |= tmpreg2; - ADCx->RSQR3 = tmpreg1; - } - else if(Rank < 13) - { - tmpreg1 = ADCx->RSQR2; - tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - tmpreg1 |= tmpreg2; - ADCx->RSQR2 = tmpreg1; - } - else - { - tmpreg1 = ADCx->RSQR1; - tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - tmpreg1 |= tmpreg2; - ADCx->RSQR1 = tmpreg1; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigConvCmd - * - * @brief Enables or disables the ADCx conversion through external trigger. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetConversionValue - * - * @brief Returns the last ADCx conversion result data for regular channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return ADCx->RDATAR - The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) -{ - return (uint16_t)ADCx->RDATAR; -} - -/********************************************************************* - * @fn ADC_AutoInjectedConvCmd - * - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JAUTO_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JAUTO_Reset; - } -} - -/********************************************************************* - * @fn ADC_InjectedDiscModeCmd - * - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JDISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvConfig - * - * @brief Configures the ADCx external trigger for injected channels conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start - * injected conversion. - * ADC_ExternalTrigInjecConv_T1_CC3 - Timer1 capture compare3 selected. - * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. - * ADC_ExternalTrigInjecConv_T2_CC3 - Timer2 capture compare3 selected. - * ADC_ExternalTrigInjecConv_T2_CC4 - Timer2 capture compare4 selected. - * ADC_ExternalTrigInjecConv_T3_CC1 - Timer3 capture compare1 selected. - * ADC_ExternalTrigInjecConv_T4_CC2 - Timer3 capture compare2 selected. - * ADC_ExternalTrigInjecConv_Ext_PD1_PA2_OPA - PD1 or PA2 or OPA selected. - * line 15 event selected. - * ADC_ExternalTrigInjecConv_None: Injected conversion started - * by software and not by external trigger. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR2; - tmpreg &= CTLR2_JEXTSEL_Reset; - tmpreg |= ADC_ExternalTrigInjecConv; - ADCx->CTLR2 = tmpreg; -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvCmd - * - * @brief Enables or disables the ADCx injected channels conversion through - * external trigger. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_SoftwareStartInjectedConvCmd - * - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartInjectedConvCmdStatus - * - * @brief Gets the selected ADC Software start injected conversion Status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_InjectedChannelConfig - * - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_Vrefint - ADC Channel8 selected. - * ADC_Channel_OPA - ADC Channel9 selected. - * ADC_Channel_Vcalint - ADC Channel10 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_CyclesMode0 - Sample time equal to 3.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 3.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode1 - Sample time equal to 7.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 7.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode2 - Sample time equal to 11.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 13.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode3 - Sample time equal to 19.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 28.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode4 - Sample time equal to 35.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 41.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode5 - Sample time equal to 55.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 55.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode6 - Sample time equal to 71.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 71.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * ADC_SampleTime_CyclesMode7 - Sample time equal to 239.5 cycles(CTLR3 bit[0]-ADC_LP=0). - * - Sample time equal to 239.5 cycles(CTLR3 bit[0]-ADC_LP=1). - * - * @return None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - tmpreg1 = ADCx->ISQR; - tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; - tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 |= tmpreg2; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_InjectedSequencerLengthConfig - * - * @brief Configures the sequencer length for injected channels. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * Length - The sequencer length. - * This parameter must be a number between 1 to 4. - * - * @return None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->ISQR; - tmpreg1 &= ISQR_JL_Reset; - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_SetInjectedOffset - * - * @brief Set the injected channels conversion value offset. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InjectedChannel: the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * Offset - the offset value for the selected ADC injected channel. - * This parameter must be a 10bit value. - * - * @return None - */ -void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - *(__IO uint32_t *)tmp = (uint32_t)Offset; -} - -/********************************************************************* - * @fn ADC_GetInjectedConversionValue - * - * @brief Returns the ADC injected channel conversion result. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InjectedChannel - the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * - * @return tmp - The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + IDATAR_Offset; - - return (uint16_t)(*(__IO uint32_t *)tmp); -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogCmd - * - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_AnalogWatchdog - the ADC analog watchdog configuration. - * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a - * single regular channel. - * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a - * single injected channel. - * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog - * on a single regular or injected channel. - * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all - * regular channel. - * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all - * injected channel. - * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on - * all regular and injected channels. - * ADC_AnalogWatchdog_None - No channel guarded by the analog - * watchdog. - * - * @return none - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDMode_Reset; - tmpreg |= ADC_AnalogWatchdog; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogThresholdsConfig - * - * @brief Configures the high and low thresholds of the analog watchdog. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * HighThreshold - the ADC analog watchdog High threshold value. - * This parameter must be a 10bit value. - * LowThreshold - the ADC analog watchdog Low threshold value. - * This parameter must be a 10bit value. - * - * @return none - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - ADCx->WDHTR = HighThreshold; - ADCx->WDLTR = LowThreshold; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdog1ThresholdsConfig - * - * @brief Configures the high and low thresholds of the analog watchdog1. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * HighThreshold - the ADC analog watchdog1 High threshold value. - * This parameter must be a 12bit value. - * LowThreshold - the ADC analog watchdog1 Low threshold value. - * This parameter must be a 12bit value. - * - * @return none - */ -void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - ADCx->WDTR1 = (uint32_t)HighThreshold<<16; - ADCx->WDTR1 |= (uint32_t)LowThreshold; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdog2ThresholdsConfig - * - * @brief Configures the high and low thresholds of the analog watchdog2. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * HighThreshold - the ADC analog watchdog2 High threshold value. - * This parameter must be a 12bit value. - * LowThreshold - the ADC analog watchdog2 Low threshold value. - * This parameter must be a 12bit value. - * - * @return none - */ -void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - ADCx->WDTR2 = (uint32_t)HighThreshold<<16; - ADCx->WDTR2 |= (uint32_t)LowThreshold; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogSingleChannelConfig - * - * @brief Configures the analog watchdog guarded single channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_Vrefint - ADC Channel8 selected. - * ADC_Channel_OPA - ADC Channel9 selected. - * ADC_Channel_Vcalint - ADC Channel10 selected. - * - * @return None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDCH_Reset; - tmpreg |= ADC_Channel; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_GetFlagStatus - * - * @brief Checks whether the specified ADC flag is set or not. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to check. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearFlag - * - * @brief Clears the ADCx's pending flags. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to clear. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return none - */ -void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - ADCx->STATR = ~(uint32_t)ADC_FLAG; -} - -/********************************************************************* - * @fn ADC_GetITStatus - * - * @brief Checks whether the specified ADC interrupt has occurred or not. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt source to check. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return ITStatus: SET or RESET. - */ -ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - itmask = ADC_IT >> 8; - enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); - - if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearITPendingBit - * - * @brief Clears the ADCx's interrupt pending bits. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt pending bit to clear. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return none - */ -void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)(ADC_IT >> 8); - ADCx->STATR = ~(uint32_t)itmask; -} - -/********************************************************************* - * @fn ADC_BufferCmd - * - * @brief Enables or disables the ADCx buffer. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= (1 << 26); - } - else - { - ADCx->CTLR1 &= ~(1 << 26); - } -} - -/********************************************************************* - * @fn ADC_TKeyCmd - * - * @brief Enables or disables the TKey. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_TKeyCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= (1 << 24); - } - else - { - ADCx->CTLR1 &= ~(1 << 24); - } -} - -/********************************************************************* - * @fn ADC_Tkey_CurrentConfig - * - * @brief Configures TKey current. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * TKey_Current - Tkey current. - * ADC_TKey_Current_mode0 - TKey Current mode0(35uA). - * ADC_TKey_Current_mode1 - TKey Current mode1(17.5uA). - * - * @return none - */ -void ADC_Tkey_CurrentConfig(ADC_TypeDef *ADCx, uint32_t TKey_CurrentMode) -{ - ADCx->CTLR1 &= ~ADC_TKITUNE; - ADCx->CTLR1 |= TKey_CurrentMode; -} - -/********************************************************************* - * @fn ADC_RegularExTrigConvConfig - * - * @brief Configures ADC Regular external trigger conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * RegularExTrigConv - ADC Regular external trigger conversion. - * ADC_RegularExTrigConv_PD3_PC2 - ADC Regular external trigger - * conversion is PD3 or PC2. - * ADC_RegularExTrigConv_OPA - ADC Regular external trigger - * conversion is OPA. - * - * @return none - */ -void ADC_RegularExTrigConvConfig(ADC_TypeDef *ADCx, uint32_t RegularExTrigConv) -{ - ADCx->CTLR2 &= ~ADC_RegularExTrigConv_OPA; - ADCx->CTLR2 |= RegularExTrigConv; -} - -/********************************************************************* - * @fn ADC_InjectedExTrigConvConfig - * - * @brief Configures ADC Injected external trigger conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * RegularExTrigConv - ADC Injected external trigger conversion. - * ADC_InjectedExTrigConv_PD1_PA2 - ADC Injected external trigger - * conversion is PD1 or PA2. - * ADC_InjectedExTrigConv_OPA - ADC Injected external trigger - * conversion is OPA. - * - * @return none - */ -void ADC_InjectedExTrigConvConfig(ADC_TypeDef *ADCx, uint32_t InjectedExTrigConv) -{ - ADCx->CTLR2 &= ~ADC_InjectedExTrigConv_OPA; - ADCx->CTLR2 |= InjectedExTrigConv; -} - -/********************************************************************* - * @fn ADC_TKey_ChannelxMulShieldCmd - * - * @brief Enables or disables TKey Multiplex shielding of the selected ADC channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_Vrefint - ADC Channel8 selected. - * ADC_Channel_OPA - ADC Channel9 selected. - * ADC_Channel_Vcalint - ADC Channel10 selected. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_TKey_ChannelxMulShieldCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR3 |= ((1<<16)<< ADC_Channel); - } - else - { - ADCx->CTLR3 &= ~((1<<16)<< ADC_Channel); - } -} - -/********************************************************************* - * @fn ADC_TKey_MulShieldCmd - * - * @brief Enables or disables the TKey Multiplex shielding. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_TKey_MulShieldCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR3 |= (1 << 2); - } - else - { - ADCx->CTLR3 &= ~(1 << 2); - } -} - -/********************************************************************* - * @fn ADC_Sample_ModeConfig - * - * @brief Configures the ADC Sample Mode. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Sample_Mode - Sample Mode. - * ADC_Sample_NoOver_1M_Mode - sampling rate no over 1M(<=1M) mode. - * ADC_Sample_Over_1M_Mode - sampling rate over 1M(>1M) mode. - * - * @return none - */ -void ADC_Sample_ModeConfig(ADC_TypeDef *ADCx, uint32_t ADC_Sample_Mode) -{ - ADCx->CTLR3 &= ~ADC_Sample_NoOver_1M_Mode; - ADCx->CTLR3 |= ADC_Sample_Mode; -} - -/********************************************************************* - * @fn ADC_DutyDelayCmd - * - * @brief Enables or disables the Duty delay. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR3 |= (1 << 1); - } - else - { - ADCx->CTLR3 &= ~(1 << 1); - } -} - -/********************************************************************* - * @fn ADC_GetAnalogWatchdogFlagStatus - * - * @brief Checks whether the specified ADC Analog Watchdog flag is set or not. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * AnalogWatchdog_FLAG - specifies the Analog watchdog flag to check. - * ADC_AnalogWatchdog_0_FLAG - Analog watchdog 0 flag. - * ADC_AnalogWatchdog_1_FLAG - Analog watchdog 1 flag. - * ADC_AnalogWatchdog_2_FLAG - Analog watchdog 2 flag. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetAnalogWatchdogFlagStatus(ADC_TypeDef *ADCx, uint32_t AnalogWatchdog_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR3 & AnalogWatchdog_FLAG) != (uint8_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearAnalogWatchdogFlag - * - * @brief Clears the ADCx's pending Analog Watchdog flags. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * AnalogWatchdog_FLAG - specifies the Analog watchdog flag to check. - * ADC_AnalogWatchdog_0_FLAG - Analog watchdog 0 flag. - * ADC_AnalogWatchdog_1_FLAG - Analog watchdog 1 flag. - * ADC_AnalogWatchdog_2_FLAG - Analog watchdog 2 flag. - * - * @return none - */ -void ADC_ClearAnalogWatchdogFlag(ADC_TypeDef *ADCx, uint32_t AnalogWatchdog_FLAG) -{ - ADCx->CTLR3 &= ~(uint32_t)AnalogWatchdog_FLAG; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogResetCmd - * - * @brief Enables or disables the analog watchdog reset - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_AnalogWatchdog_x - Analog watchdog X. - * ADC_AnalogWatchdog_0_RST_EN. - * ADC_AnalogWatchdog_1_RST_EN. - * ADC_AnalogWatchdog_2_RST_EN. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog_x, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR3 |= ADC_AnalogWatchdog_x; - } - else - { - ADCx->CTLR3 &= ~ADC_AnalogWatchdog_x; - } -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogScanCmd - * - * @brief Enable ADC clock duty cycle adjustment. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_AnalogWatchdogScanCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR3 |= (1<<3); - } - else - { - ADCx->CTLR3 &= ~(1<<3); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_adc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/06 + * Description : This file provides all the ADC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + RCC_PB2PeriphResetCmd(RCC_PB2Periph_ADC1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_ADC1, DISABLE); +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_Vrefint - ADC Channel8 selected. + * ADC_Channel_OPA - ADC Channel9 selected. + * ADC_Channel_Vcalint - ADC Channel10 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_CyclesMode0 - Sample time equal to 3.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 3.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode1 - Sample time equal to 7.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 7.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode2 - Sample time equal to 11.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 13.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode3 - Sample time equal to 19.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 28.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode4 - Sample time equal to 35.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 41.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode5 - Sample time equal to 55.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 55.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode6 - Sample time equal to 71.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 71.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode7 - Sample time equal to 239.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 239.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_CC3 - Timer1 capture compare3 selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_CC3 - Timer2 capture compare3 selected. + * ADC_ExternalTrigInjecConv_T2_CC4 - Timer2 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T3_CC1 - Timer3 capture compare1 selected. + * ADC_ExternalTrigInjecConv_T4_CC2 - Timer3 capture compare2 selected. + * ADC_ExternalTrigInjecConv_Ext_PD1_PA2_OPA - PD1 or PA2 or OPA selected. + * line 15 event selected. + * ADC_ExternalTrigInjecConv_None: Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_Vrefint - ADC Channel8 selected. + * ADC_Channel_OPA - ADC Channel9 selected. + * ADC_Channel_Vcalint - ADC Channel10 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_CyclesMode0 - Sample time equal to 3.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 3.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode1 - Sample time equal to 7.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 7.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode2 - Sample time equal to 11.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 13.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode3 - Sample time equal to 19.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 28.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode4 - Sample time equal to 35.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 41.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode5 - Sample time equal to 55.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 55.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode6 - Sample time equal to 71.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 71.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * ADC_SampleTime_CyclesMode7 - Sample time equal to 239.5 cycles(CTLR3 bit[0]-ADC_LP=0). + * - Sample time equal to 239.5 cycles(CTLR3 bit[0]-ADC_LP=1). + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 10bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 10bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 10bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdog1ThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog1. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog1 High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog1 Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDTR1 = (uint32_t)HighThreshold<<16; + ADCx->WDTR1 |= (uint32_t)LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdog2ThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog2. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog2 High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog2 Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDTR2 = (uint32_t)HighThreshold<<16; + ADCx->WDTR2 |= (uint32_t)LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_Vrefint - ADC Channel8 selected. + * ADC_Channel_OPA - ADC Channel9 selected. + * ADC_Channel_Vcalint - ADC Channel10 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return ITStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn ADC_BufferCmd + * + * @brief Enables or disables the ADCx buffer. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= (1 << 26); + } + else + { + ADCx->CTLR1 &= ~(1 << 26); + } +} + +/********************************************************************* + * @fn ADC_TKeyCmd + * + * @brief Enables or disables the TKey. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TKeyCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= (1 << 24); + } + else + { + ADCx->CTLR1 &= ~(1 << 24); + } +} + +/********************************************************************* + * @fn ADC_Tkey_CurrentConfig + * + * @brief Configures TKey current. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * TKey_Current - Tkey current. + * ADC_TKey_Current_mode0 - TKey Current mode0(35uA). + * ADC_TKey_Current_mode1 - TKey Current mode1(17.5uA). + * + * @return none + */ +void ADC_Tkey_CurrentConfig(ADC_TypeDef *ADCx, uint32_t TKey_CurrentMode) +{ + ADCx->CTLR1 &= ~ADC_TKITUNE; + ADCx->CTLR1 |= TKey_CurrentMode; +} + +/********************************************************************* + * @fn ADC_RegularExTrigConvConfig + * + * @brief Configures ADC Regular external trigger conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * RegularExTrigConv - ADC Regular external trigger conversion. + * ADC_RegularExTrigConv_PD3_PC2 - ADC Regular external trigger + * conversion is PD3 or PC2. + * ADC_RegularExTrigConv_OPA - ADC Regular external trigger + * conversion is OPA. + * + * @return none + */ +void ADC_RegularExTrigConvConfig(ADC_TypeDef *ADCx, uint32_t RegularExTrigConv) +{ + ADCx->CTLR2 &= ~ADC_RegularExTrigConv_OPA; + ADCx->CTLR2 |= RegularExTrigConv; +} + +/********************************************************************* + * @fn ADC_InjectedExTrigConvConfig + * + * @brief Configures ADC Injected external trigger conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * RegularExTrigConv - ADC Injected external trigger conversion. + * ADC_InjectedExTrigConv_PD1_PA2 - ADC Injected external trigger + * conversion is PD1 or PA2. + * ADC_InjectedExTrigConv_OPA - ADC Injected external trigger + * conversion is OPA. + * + * @return none + */ +void ADC_InjectedExTrigConvConfig(ADC_TypeDef *ADCx, uint32_t InjectedExTrigConv) +{ + ADCx->CTLR2 &= ~ADC_InjectedExTrigConv_OPA; + ADCx->CTLR2 |= InjectedExTrigConv; +} + +/********************************************************************* + * @fn ADC_TKey_ChannelxMulShieldCmd + * + * @brief Enables or disables TKey Multiplex shielding of the selected ADC channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_Vrefint - ADC Channel8 selected. + * ADC_Channel_OPA - ADC Channel9 selected. + * ADC_Channel_Vcalint - ADC Channel10 selected. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TKey_ChannelxMulShieldCmd(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR3 |= ((1<<16)<< ADC_Channel); + } + else + { + ADCx->CTLR3 &= ~((1<<16)<< ADC_Channel); + } +} + +/********************************************************************* + * @fn ADC_TKey_MulShieldCmd + * + * @brief Enables or disables the TKey Multiplex shielding. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TKey_MulShieldCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR3 |= (1 << 2); + } + else + { + ADCx->CTLR3 &= ~(1 << 2); + } +} + +/********************************************************************* + * @fn ADC_Sample_ModeConfig + * + * @brief Configures the ADC Sample Mode. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Sample_Mode - Sample Mode. + * ADC_Sample_NoOver_1M_Mode - sampling rate no over 1M(<=1M) mode. + * ADC_Sample_Over_1M_Mode - sampling rate over 1M(>1M) mode. + * + * @return none + */ +void ADC_Sample_ModeConfig(ADC_TypeDef *ADCx, uint32_t ADC_Sample_Mode) +{ + ADCx->CTLR3 &= ~ADC_Sample_NoOver_1M_Mode; + ADCx->CTLR3 |= ADC_Sample_Mode; +} + +/********************************************************************* + * @fn ADC_DutyDelayCmd + * + * @brief Enables or disables the Duty delay. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DutyDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR3 |= (1 << 1); + } + else + { + ADCx->CTLR3 &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn ADC_GetAnalogWatchdogFlagStatus + * + * @brief Checks whether the specified ADC Analog Watchdog flag is set or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * AnalogWatchdog_FLAG - specifies the Analog watchdog flag to check. + * ADC_AnalogWatchdog_0_FLAG - Analog watchdog 0 flag. + * ADC_AnalogWatchdog_1_FLAG - Analog watchdog 1 flag. + * ADC_AnalogWatchdog_2_FLAG - Analog watchdog 2 flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetAnalogWatchdogFlagStatus(ADC_TypeDef *ADCx, uint32_t AnalogWatchdog_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR3 & AnalogWatchdog_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearAnalogWatchdogFlag + * + * @brief Clears the ADCx's pending Analog Watchdog flags. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * AnalogWatchdog_FLAG - specifies the Analog watchdog flag to check. + * ADC_AnalogWatchdog_0_FLAG - Analog watchdog 0 flag. + * ADC_AnalogWatchdog_1_FLAG - Analog watchdog 1 flag. + * ADC_AnalogWatchdog_2_FLAG - Analog watchdog 2 flag. + * + * @return none + */ +void ADC_ClearAnalogWatchdogFlag(ADC_TypeDef *ADCx, uint32_t AnalogWatchdog_FLAG) +{ + ADCx->CTLR3 &= ~(uint32_t)AnalogWatchdog_FLAG; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogResetCmd + * + * @brief Enables or disables the analog watchdog reset + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_AnalogWatchdog_x - Analog watchdog X. + * ADC_AnalogWatchdog_0_RST_EN. + * ADC_AnalogWatchdog_1_RST_EN. + * ADC_AnalogWatchdog_2_RST_EN. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog_x, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR3 |= ADC_AnalogWatchdog_x; + } + else + { + ADCx->CTLR3 &= ~ADC_AnalogWatchdog_x; + } +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogScanCmd + * + * @brief Enable ADC clock duty cycle adjustment. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_AnalogWatchdogScanCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR3 |= (1<<3); + } + else + { + ADCx->CTLR3 &= ~(1<<3); + } +} diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_dbgmcu.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_dbgmcu.c index 53b563f..19982cc 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_dbgmcu.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_dbgmcu.c @@ -1,137 +1,137 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_dbgmcu.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the DBGMCU firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - - -#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) - -/********************************************************************* - * @fn DBGMCU_GetREVID - * - * @brief Returns the device revision identifier. - * - * @return Revision identifier. - */ -uint32_t DBGMCU_GetREVID(void) -{ - return ((*(uint32_t *)0x1FFFF704) >> 16); -} - -/********************************************************************* - * @fn DBGMCU_GetDEVID - * - * @brief Returns the device identifier. - * - * @return Device identifier. - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); -} - -/********************************************************************* - * @fn __get_DEBUG_CR - * - * @brief Return the DEBUGE Control Register - * - * @return DEBUGE Control value - */ -uint32_t __get_DEBUG_CR(void) -{ - uint32_t result; - - __asm volatile("csrr %0,""0x7C0" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_DEBUG_CR - * - * @brief Set the DEBUGE Control Register - * - * @param value - set DEBUGE Control value - * - * @return none - */ -void __set_DEBUG_CR(uint32_t value) -{ - __asm volatile("csrw 0x7C0, %0" : : "r"(value)); -} - - -/********************************************************************* - * @fn DBGMCU_Config - * - * @brief Configures the specified peripheral and low power mode behavior - * when the MCU under Debug mode. - * - * @param DBGMCU_Periph - specifies the peripheral and low power mode. - * DBGMCU_SLEEP - Keep debugger connection during SLEEP mode - * DBGMCU_STANDBY - Keep debugger connection during STANDBY mode - * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted - * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted - * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted - * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted - * DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - uint32_t val; - - if(NewState != DISABLE) - { - __set_DEBUG_CR(DBGMCU_Periph); - } - else - { - val = __get_DEBUG_CR(); - val &= ~(uint32_t)DBGMCU_Periph; - __set_DEBUG_CR(val); - } -} -/********************************************************************* - * @fn DBGMCU_GetCHIPID - * - * @brief Returns the CHIP identifier. - * - * @return Device identifier. - * ChipID List- - * CH32V006K8U6-0x006006x0 - * CH32V006E8R6-0x006106x0 - * CH32V006F8U6-0x006206x0 - * CH32V006F8P6-0x006306x0 - * - * CH32M007G8R6-0x007008x0 - * CH32V007E8R6-0x007106x0 - * CH32V007F8U6-0x007206x0 - * - * CH32V005E6R6-0x005006x0 - * CH32V005F6U6-0x005106x0 - * CH32V005F6P6-0x005206x0 - * CH32V005D6U6-0x005306x0 - * - * CH32V002F4P6-0x002006x0 - * CH32V002F4U6-0x002106x0 - * CH32V002A4M6-0x002206x0 - * CH32V002D4U6-0x002306x0 - * CH32V002J4M6-0x002406x0 - * - * CH32V004F6P1-0x004006x0 - * CH32V004F6U1-0x00410600 - */ -uint32_t DBGMCU_GetCHIPID( void ) -{ - return( *( uint32_t * )0x1FFFF704 ); -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_dbgmcu.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/07 + * Description : This file provides all the DBGMCU firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + + +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) >> 16); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); +} + +/********************************************************************* + * @fn __get_DEBUG_CR + * + * @brief Return the DEBUGE Control Register + * + * @return DEBUGE Control value + */ +uint32_t __get_DEBUG_CR(void) +{ + uint32_t result; + + __asm volatile("csrr %0,""0x7C0" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_DEBUG_CR + * + * @brief Set the DEBUGE Control Register + * + * @param value - set DEBUGE Control value + * + * @return none + */ +void __set_DEBUG_CR(uint32_t value) +{ + __asm volatile("csrw 0x7C0, %0" : : "r"(value)); +} + + +/********************************************************************* + * @fn DBGMCU_Config + * + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * + * @param DBGMCU_Periph - specifies the peripheral and low power mode. + * DBGMCU_SLEEP - Keep debugger connection during SLEEP mode + * DBGMCU_STANDBY - Keep debugger connection during STANDBY mode + * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted + * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted + * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted + * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted + * DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + uint32_t val; + + if(NewState != DISABLE) + { + __set_DEBUG_CR(DBGMCU_Periph); + } + else + { + val = __get_DEBUG_CR(); + val &= ~(uint32_t)DBGMCU_Periph; + __set_DEBUG_CR(val); + } +} +/********************************************************************* + * @fn DBGMCU_GetCHIPID + * + * @brief Returns the CHIP identifier. + * + * @return Device identifier. + * ChipID List- + * CH32V006K8U6-0x006006x0 + * CH32V006E8R6-0x006106x0 + * CH32V006F8U6-0x006206x0 + * CH32V006F8P6-0x006306x0 + * + * CH32M007G8R6-0x007008x0 + * CH32V007E8R6-0x007106x0 + * CH32V007K8U6-0x007206x0 + * + * CH32V005E6R6-0x005006x0 + * CH32V005F6U6-0x005106x0 + * CH32V005F6P6-0x005206x0 + * CH32V005D6U6-0x005306x0 + * + * CH32V002F4P6-0x002006x0 + * CH32V002F4U6-0x002106x0 + * CH32V002A4M6-0x002206x0 + * CH32V002D4U6-0x002306x0 + * CH32V002J4M6-0x002406x0 + * + * CH32V004F6P1-0x004006x0 + * CH32V004F6U1-0x00410600 + */ +uint32_t DBGMCU_GetCHIPID( void ) +{ + return( *( uint32_t * )0x1FFFF704 ); +} diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_dma.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_dma.c index b8dc726..b6c75e5 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_dma.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_dma.c @@ -1,411 +1,411 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_dma.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the DMA firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) -#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) -#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) -#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) -#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) -#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) -#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) - -/* DMA registers Masks */ -#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) - -/********************************************************************* - * @fn DMA_DeInit - * - * @brief Deinitializes the DMAy Channelx registers to their default - * reset values. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * - * @return none - */ -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) -{ - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - DMAy_Channelx->CFGR = 0; - DMAy_Channelx->CNTR = 0; - DMAy_Channelx->PADDR = 0; - DMAy_Channelx->MADDR = 0; - if(DMAy_Channelx == DMA1_Channel1) - { - DMA1->INTFCR |= DMA1_Channel1_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel2) - { - DMA1->INTFCR |= DMA1_Channel2_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel3) - { - DMA1->INTFCR |= DMA1_Channel3_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel4) - { - DMA1->INTFCR |= DMA1_Channel4_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel5) - { - DMA1->INTFCR |= DMA1_Channel5_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel6) - { - DMA1->INTFCR |= DMA1_Channel6_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel7) - { - DMA1->INTFCR |= DMA1_Channel7_IT_Mask; - } -} - -/********************************************************************* - * @fn DMA_Init - * - * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - tmpreg = DMAy_Channelx->CFGR; - tmpreg &= CFGR_CLEAR_Mask; - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - DMAy_Channelx->CFGR = tmpreg; - DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; - DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; - DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/********************************************************************* - * @fn DMA_StructInit - * - * @brief Fills each DMA_InitStruct member with its default value. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) -{ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - DMA_InitStruct->DMA_BufferSize = 0; - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/********************************************************************* - * @fn DMA_Cmd - * - * @brief Enables or disables the specified DMAy Channelx. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_CFGR1_EN; - } - else - { - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - } -} - -/********************************************************************* - * @fn DMA_ITConfig - * - * @brief Enables or disables the specified DMAy Channelx interrupts. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * DMA_IT - specifies the DMA interrupts sources to be enabled - * or disabled. - * DMA_IT_TC - Transfer complete interrupt mask - * DMA_IT_HT - Half transfer interrupt mask - * DMA_IT_TE - Transfer error interrupt mask - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_IT; - } - else - { - DMAy_Channelx->CFGR &= ~DMA_IT; - } -} - -/********************************************************************* - * @fn DMA_SetCurrDataCounter - * - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * DataNumber - The number of data units in the current DMAy Channelx - * transfer. - * - * @return none - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) -{ - DMAy_Channelx->CNTR = DataNumber; -} - -/********************************************************************* - * @fn DMA_GetCurrDataCounter - * - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 7 for DMA1 to select the DMA Channel. - * - * @return DataNumber - The number of remaining data units in the current - * DMAy Channelx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) -{ - return ((uint16_t)(DMAy_Channelx->CNTR)); -} - -/********************************************************************* - * @fn DMA_GetFlagStatus - * - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * - * @return The new state of DMAy_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - tmpreg = DMA1->INTFR; - - if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearFlag - * - * @brief Clears the DMAy Channelx's pending flags. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * - * @return none - */ -void DMA_ClearFlag(uint32_t DMAy_FLAG) -{ - DMA1->INTFCR = DMAy_FLAG; -} - -/********************************************************************* - * @fn DMA_GetITStatus - * - * @brief Checks whether the specified DMAy Channelx interrupt has - * occurred or not. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * - * @return The new state of DMAy_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMAy_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - tmpreg = DMA1->INTFR; - - if((tmpreg & DMAy_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearITPendingBit - * - * @brief Clears the DMAy Channelx's interrupt pending bits. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * - * @return none - */ -void DMA_ClearITPendingBit(uint32_t DMAy_IT) -{ - DMA1->INTFCR = DMAy_IT; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_dma.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file provides all the DMA firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + DMA1->INTFCR = DMAy_FLAG; +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + DMA1->INTFCR = DMAy_IT; +} diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_exti.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_exti.c index a386bc6..d677ea0 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_exti.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_exti.c @@ -1,182 +1,182 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_exti.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the EXTI firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -/* No interrupt selected */ -#define EXTI_LINENONE ((uint32_t)0x00000) - -/********************************************************************* - * @fn EXTI_DeInit - * - * @brief Deinitializes the EXTI peripheral registers to their default - * reset values. - * - * @return none. - */ -void EXTI_DeInit(void) -{ - EXTI->INTENR = 0x00000000; - EXTI->EVENR = 0x00000000; - EXTI->RTENR = 0x00000000; - EXTI->FTENR = 0x00000000; - EXTI->INTFR = 0x000FFFFF; -} - -/********************************************************************* - * @fn EXTI_Init - * - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) -{ - uint32_t tmp = 0; - - tmp = (uint32_t)EXTI_BASE; - if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; - if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/********************************************************************* - * @fn EXTI_StructInit - * - * @brief Fills each EXTI_InitStruct member with its reset value. - * - * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/********************************************************************* - * @fn EXTI_GenerateSWInterrupt - * - * @brief Generates a Software interrupt. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none. - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - EXTI->SWIEVR |= EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetFlagStatus - * - * @brief Checks whether the specified EXTI line flag is set or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearFlag - * - * @brief Clears the EXTI's line pending flags. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetITStatus - * - * @brief Checks whether the specified EXTI line is asserted or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = EXTI->INTENR & EXTI_Line; - if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearITPendingBit - * - * @brief Clears the EXTI's line pending bits. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_exti.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file provides all the EXTI firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x000FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_flash.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_flash.c index 4b30a50..8ca9124 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_flash.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_flash.c @@ -1,1065 +1,1067 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_flash.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the FLASH firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -/* Flash Access Control Register bits */ -#define ACR_LATENCY_Mask ((uint32_t)0xFFFFFFFC) - -/* Flash Control Register bits */ -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) -#define CR_FLOCK_Set ((uint32_t)0x00008000) -#define CR_PAGE_PG ((uint32_t)0x00010000) -#define CR_PAGE_ER ((uint32_t)0x00020000) -#define CR_PAGE_ER_Reset ((uint32_t)0xFFFDFFFF) -#define CR_BUF_LOAD ((uint32_t)0x00040000) -#define CR_BUF_RST ((uint32_t)0x00080000) -#define CR_BER32 ((uint32_t)0x00800000) - -/* FLASH Status Register bits */ -#define SR_BSY ((uint32_t)0x00000001) -#define SR_WRPRTERR ((uint32_t)0x00000010) -#define SR_EOP ((uint32_t)0x00000020) - -/* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) - -/* FLASH Keys */ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) - -/* Delay definition */ -#define EraseTimeout ((uint32_t)0x000B0000) -#define ProgramTimeout ((uint32_t)0x00002000) - -/* Flash Program Valid Address */ -#define ValidAddrStart (FLASH_BASE) - -#if defined(CH32V002) -#define ValidAddrEnd (FLASH_BASE + 0x4000) - -#elif defined(CH32V004) || defined(CH32V005) -#define ValidAddrEnd (FLASH_BASE + 0x8000) - -#elif defined(CH32V006) || defined(CH32V007_M007) -#define ValidAddrEnd (FLASH_BASE + 0xF800) - -#endif - -/* FLASH Size */ -#define Size_256B 0x100 -#define Size_1KB 0x400 -#define Size_32KB 0x8000 - -/******************************************************************************** - * @fn FLASH_SetLatency - * - * @brief Sets the code latency value. - * - * @param FLASH_Latency - specifies the FLASH Latency value. - * FLASH_Latency_0 - FLASH Zero Latency cycle - * FLASH_Latency_1 - FLASH One Latency cycle - * FLASH_Latency_2 - FLASH Two Latency cycles - * - * @return None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - tmpreg = FLASH->ACTLR; - tmpreg &= ACR_LATENCY_Mask; - tmpreg |= FLASH_Latency; - FLASH->ACTLR = tmpreg; -} - -/******************************************************************************** - * @fn FLASH_Unlock - * - * @brief Unlocks the FLASH Program Erase Controller. - * - * @return None - */ -void FLASH_Unlock(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -/******************************************************************************** - * @fn FLASH_Lock - * - * @brief Locks the FLASH Program Erase Controller. - * - * @return None - */ -void FLASH_Lock(void) -{ - FLASH->CTLR |= CR_LOCK_Set; -} - -/******************************************************************************** - * @fn FLASH_ErasePage - * - * @brief Erases a specified FLASH page(1KB). - * - * @param Page_Address - The page address to be erased. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - FLASH->CTLR |= CR_PER_Set; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_PER_Reset; - } - - return status; -} - -/******************************************************************************** - * @fn FLASH_EraseAllPages - * - * @brief Erases all FLASH pages. - * - * @return FLASH Status - The returned value can be:FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - FLASH->CTLR |= CR_MER_Set; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_MER_Reset; - } - - return status; -} - -/******************************************************************************** - * @fn FLASH_EraseOptionBytes - * - * @brief Erases the FLASH option bytes. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseOptionBytes(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH_Unlock(); - - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_OPTER_Reset; - - FLASH_Lock(); - } - return status; -} - -/********************************************************************* - * @fn FLASH_OptionBytePR - * - * @brief Programs option bytes. - * - * @param pbuf - data. - * - * @return none - */ -void FLASH_OptionBytePR(u32* pbuf) -{ - uint8_t i; - - FLASH_EraseOptionBytes(); - FLASH_Unlock_Fast(); - FLASH_BufReset(); - - for(i=0; i<4; i++) - { - FLASH_BufLoad((OB_BASE + 4*i), *pbuf++); - } - - FLASH_ProgramPage_Fast(OB_BASE); - FLASH_Lock_Fast(); -} - -/********************************************************************* - * @fn FLASH_EnableWriteProtection - * - * @brief Write protects the desired sectors - * - * @param FLASH_Pages - specifies the address of the pages to be write protected. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. - */ -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) -{ - uint8_t WRP0_Data = 0xFF, WRP1_Data = 0xFF, WRP2_Data = 0xFF, WRP3_Data = 0xFF; - uint32_t buf[4]; - uint8_t i; - FLASH_Status status = FLASH_COMPLETE; - - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - status = FLASH_RDP; - } - else{ - FLASH_Pages = (uint32_t)(~FLASH_Pages); - WRP0_Data = (uint8_t)(FLASH_Pages & WRP0_Mask); - WRP1_Data = (uint8_t)((FLASH_Pages & WRP1_Mask) >> 8); - WRP2_Data = (uint8_t)((FLASH_Pages & WRP2_Mask) >> 16); - WRP3_Data = (uint8_t)((FLASH_Pages & WRP3_Mask) >> 24); - - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - for(i=0; i<4; i++){ - buf[i] = *(uint32_t*)(OB_BASE + 4*i); - } - - buf[2] = ((uint32_t)(((uint32_t)(WRP0_Data) & 0x00FF) + (((uint32_t)(~WRP0_Data) & 0x00FF) << 8) \ - + (((uint32_t)(WRP1_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP1_Data) & 0x00FF) << 24))); - buf[3] = ((uint32_t)(((uint32_t)(WRP2_Data) & 0x00FF) + (((uint32_t)(~WRP2_Data) & 0x00FF) << 8) \ - + (((uint32_t)(WRP3_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP3_Data) & 0x00FF) << 24))); - - FLASH_OptionBytePR(buf); - } - } - - return status; -} - -/********************************************************************* - * @fn FLASH_EnableReadOutProtection - * - * @brief Enables the read out protection. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT or FLASH_RDP. - */ -FLASH_Status FLASH_EnableReadOutProtection(void) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t buf[4]; - uint8_t i; - - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - status = FLASH_RDP; - } - else{ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - for(i=0; i<4; i++){ - buf[i] = *(uint32_t*)(OB_BASE + 4*i); - } - - buf[0] = 0x000000FF + (buf[0] & 0xFFFF0000); - FLASH_OptionBytePR(buf); - } - } - - return status; -} - -/********************************************************************* - * @fn FLASH_UserOptionByteConfig - * - * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / - * RST_STDBY / OB_PowerON_Start_Mode. - * - * @param OB_IWDG - Selects the IWDG mode - * OB_IWDG_SW - Software IWDG selected - * OB_IWDG_HW - Hardware IWDG selected - * OB_STDBY - Reset event when entering Standby mode. - * OB_STDBY_NoRST - No reset generated when entering in STANDBY. - * OB_STDBY_RST - Reset generated when entering in STANDBY. - * OB_RST - Selects the reset IO mode and Ignore delay time. - * OB_RST_NoEN - Reset IO disable. - * OB_RST_EN_DT12ms - Reset IO enable and Ignore delay time 12ms. - * OB_RST_EN_DT1ms - Reset IO enable and Ignore delay time 1ms. - * OB_RST_EN_DT128us - Reset IO enable and Ignore delay time 128us. - * OB_PowerON_Start_Mode - Selects start mode after power on. - * OB_PowerON_Start_Mode_BOOT - Boot start after power on. - * OB_PowerON_Start_Mode_USER - User start after power on. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT or FLASH_RDP. - */ -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STDBY, uint16_t OB_RST, uint16_t OB_PowerON_Start_Mode) -{ - FLASH_Status status = FLASH_COMPLETE; - uint8_t UserByte; - uint32_t buf[4]; - uint8_t i; - - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - status = FLASH_RDP; - } - else{ - UserByte = OB_IWDG | (uint16_t)(OB_STDBY | (uint16_t)(OB_RST | (uint16_t)(OB_PowerON_Start_Mode | 0xC2))); - - for(i=0; i<4; i++){ - buf[i] = *(uint32_t*)(OB_BASE + 4*i); - } - buf[0] = ((uint32_t)((((uint32_t)(UserByte) & 0x00FF) << 16) + (((uint32_t)(~UserByte) & 0x00FF) << 24))) + 0x00005AA5; - - FLASH_OptionBytePR(buf); - } - - return status; -} - -/********************************************************************* - * @fn FLASH_GetUserOptionByte - * - * @brief Returns the FLASH User Option Bytes values. - * - * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STDBY(Bit2) - * , RST_MODE(Bit[3:4]) and START_MODE(Bit5). - */ -uint32_t FLASH_GetUserOptionByte(void) -{ - return (uint32_t)(FLASH->OBR >> 2); -} - -/********************************************************************* - * @fn FLASH_GetWriteProtectionOptionByte - * - * @brief Returns the FLASH Write Protection Option Bytes Register value. - * - * @return The FLASH Write Protection Option Bytes Register value. - */ -uint32_t FLASH_GetWriteProtectionOptionByte(void) -{ - return (uint32_t)(FLASH->WPR); -} - -/********************************************************************* - * @fn FLASH_GetReadOutProtectionStatus - * - * @brief Checks whether the FLASH Read Out Protection Status is set or not. - * - * @return FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetReadOutProtectionStatus(void) -{ - FlagStatus readoutstatus = RESET; - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - readoutstatus = SET; - } - else - { - readoutstatus = RESET; - } - return readoutstatus; -} - -/********************************************************************* - * @fn FLASH_ITConfig - * - * @brief Enables or disables the specified FLASH interrupts. - * - * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. - * FLASH_IT_ERROR - FLASH Error Interrupt. - * FLASH_IT_EOP - FLASH end of operation Interrupt. - * FLASH_IT_FWAKE - FLASH Wake Up Interrupt. - * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). - * - * @return FLASH Prefetch Buffer Status (SET or RESET). - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - FLASH->CTLR |= FLASH_IT; - } - else - { - FLASH->CTLR &= ~(uint32_t)FLASH_IT; - } -} - -/********************************************************************* - * @fn FLASH_GetFlagStatus - * - * @brief Checks whether the specified FLASH flag is set or not. - * - * @param FLASH_FLAG - specifies the FLASH flag to check. - * FLASH_FLAG_BSY - FLASH Busy flag - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * FLASH_FLAG_FWAKE - FLASH Wake Up flag - * FLASH_FLAG_OPTERR - FLASH Option Byte error flag - * - * @return The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - return bitstatus; -} - -/********************************************************************* - * @fn FLASH_ClearFlag - * - * @brief Clears the FLASH's pending flags. - * - * @param FLASH_FLAG - specifies the FLASH flags to clear. - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * FLASH_FLAG_FWAKE - FLASH Wake Up flag - * - * @return none - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - if(FLASH_FLAG == FLASH_FLAG_FWAKE) - { - FLASH->STATR &= ~FLASH_FLAG; - } - else - { - FLASH->STATR = FLASH_FLAG; - } -} - -/********************************************************************* - * @fn FLASH_GetStatus - * - * @brief Returns the FLASH Status. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_GetBank1Status - * - * @brief Returns the FLASH Bank1 Status. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetBank1Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_WaitForLastOperation - * - * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_WaitForLastBank1Operation - * - * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_Unlock_Fast - * - * @brief Unlocks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Unlock_Fast(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - - /* Fast program mode unlock */ - FLASH->MODEKEYR = FLASH_KEY1; - FLASH->MODEKEYR = FLASH_KEY2; -} - -/********************************************************************* - * @fn FLASH_Lock_Fast - * - * @brief Locks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Lock_Fast(void) -{ - FLASH->CTLR |= CR_FLOCK_Set; -} - -/********************************************************************* - * @fn FLASH_BufReset - * - * @brief Flash Buffer reset. - * - * @return none - */ -void FLASH_BufReset(void) -{ - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - FLASH->CTLR |= CR_PAGE_PG; - FLASH->CTLR |= CR_BUF_RST; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; -} - -/********************************************************************* - * @fn FLASH_BufLoad - * - * @brief Flash Buffer load(4Byte). - * - * @param Address - specifies the address to be programmed. - * Data0 - specifies the data0 to be programmed. - * - * @return none - */ -void FLASH_BufLoad(uint32_t Address, uint32_t Data0) -{ - if(((Address >= ValidAddrStart) && (Address < ValidAddrEnd)) || (Address == OB_BASE)) - { - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - FLASH->CTLR |= CR_PAGE_PG; - *(__IO uint32_t *)(Address) = Data0; - FLASH->CTLR |= CR_BUF_LOAD; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; - } -} - -/********************************************************************* - * @fn FLASH_ErasePage_Fast - * - * @brief Erases a specified FLASH page (1page = 256Byte). - * - * @param Page_Address - The page address to be erased. - * - * @return none - */ -void FLASH_ErasePage_Fast(uint32_t Page_Address) -{ - if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) - { - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - FLASH->CTLR |= CR_PAGE_ER; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_ER; - } -} - -/********************************************************************* - * @fn FLASH_EraseBlock_32K_Fast - * - * @brief Erases a specified FLASH Block (1Block = 32KByte). - * - * @param Block_Address - The block address to be erased. - * - * @return none - */ -void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) -{ - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - Block_Address &= 0xFFFF8000; - - FLASH->CTLR |= CR_BER32; - FLASH->ADDR = Block_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_BER32; -} - -/********************************************************************* - * @fn FLASH_ProgramPage_Fast - * - * @brief Program a specified FLASH page (1page = 256Byte). - * - * @param Page_Address - The page address to be programed. - * - * @return none - */ -void FLASH_ProgramPage_Fast(uint32_t Page_Address) -{ - if(((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) || (Page_Address == OB_BASE)) - { - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - FLASH->CTLR |= CR_PAGE_PG; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; - } -} - -/********************************************************************* - * @fn SystemReset_StartMode - * - * @brief Start mode after system reset. - * - * @param Mode - Start mode. - * Start_Mode_USER - USER start after system reset - * Start_Mode_BOOT - Boot start after system reset - * - * @return none - */ -void SystemReset_StartMode(uint32_t Mode) -{ - FLASH_Unlock(); - - FLASH->BOOT_MODEKEYR = FLASH_KEY1; - FLASH->BOOT_MODEKEYR = FLASH_KEY2; - - FLASH->STATR &= ~(1<<14); - if(Mode == Start_Mode_BOOT){ - FLASH->STATR |= (1<<14); - } - - FLASH_Lock(); -} - -/********************************************************************* - * @fn ROM_ERASE - * - * @brief Select erases a specified FLASH . - * - * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). - * Cnt - Erases count. - * Erase_Size - Erases size select.The returned value can be: - * Size_32KB, Size_1KB, Size_256B. - * - * @return none. - */ -static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) -{ - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - do{ - if(Erase_Size == Size_32KB) - { - FLASH->CTLR |= CR_BER32; - } - else if(Erase_Size == Size_1KB) - { - FLASH->CTLR |= CR_PER_Set; - } - else if(Erase_Size == Size_256B) - { - FLASH->CTLR |= CR_PAGE_ER; - } - - FLASH->ADDR = StartAddr; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - - if(Erase_Size == Size_32KB) - { - FLASH->CTLR &= ~CR_BER32; - StartAddr += Size_32KB; - } - else if(Erase_Size == Size_1KB) - { - FLASH->CTLR &= ~CR_PER_Set; - StartAddr += Size_1KB; - } - else if(Erase_Size == Size_256B) - { - FLASH->CTLR &= ~CR_PAGE_ER; - StartAddr += Size_256B; - } - }while(--Cnt); -} - -/********************************************************************* - * @fn FLASH_ROM_ERASE - * - * @brief Erases a specified FLASH . - * - * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). - * Length - Erases Flash start Length(Length%256 == 0). - * - * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, - * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ROM_ERASE( uint32_t StartAddr, uint32_t Length ) -{ - uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; - - FLASH_Status status = FLASH_COMPLETE; - - if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) - { - return FLASH_ADR_RANGE_ERROR; - } - - if((StartAddr + Length) > ValidAddrEnd) - { - return FLASH_OP_RANGE_ERROR; - } - - if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) - { - return FLASH_ALIGN_ERROR; - } - - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - - /* Fast program mode unlock */ - FLASH->MODEKEYR = FLASH_KEY1; - FLASH->MODEKEYR = FLASH_KEY2; - - Addr0 = StartAddr; - - if(Length >= Size_32KB) - { - Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); - Addr1 = StartAddr + Length0; - Length1 = Length - Length0; - } - else if(Length >= Size_1KB) - { - Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); - Addr1 = StartAddr + Length0; - Length1 = Length - Length0; - } - else if(Length >= Size_256B) - { - Length0 = Length; - } - - /* Erase 32KB */ - if(Length0 >= Size_32KB)//front - { - Length = Length0; - if(Addr0 & (Size_32KB - 1)) - { - Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); - } - else - { - Length0 = 0; - } - - ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB); - } - - if(Length1 >= Size_32KB)//back - { - StartAddr = Addr1; - Length = Length1; - - if((Addr1 + Length1) & (Size_32KB - 1)) - { - Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1))); - Length1 = (StartAddr + Length1) & (Size_32KB - 1); - } - else - { - Length1 = 0; - } - - ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB); - } - - /* Erase 1KB */ - if(Length0 >= Size_1KB) //front - { - Length = Length0; - if(Addr0 & (Size_1KB - 1)) - { - Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); - } - else - { - Length0 = 0; - } - - ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB); - } - - if(Length1 >= Size_1KB) //back - { - StartAddr = Addr1; - Length = Length1; - - if((Addr1 + Length1) & (Size_1KB - 1)) - { - Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1))); - Length1 = (StartAddr + Length1) & (Size_1KB - 1); - } - else - { - Length1 = 0; - } - - ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB); - } - - /* Erase 256B */ - if(Length0)//front - { - ROM_ERASE(Addr0, (Length0 >> 8), Size_256B); - } - - if(Length1)//back - { - ROM_ERASE(Addr1, (Length1 >> 8), Size_256B); - } - - FLASH->CTLR |= CR_FLOCK_Set; - FLASH->CTLR |= CR_LOCK_Set; - - return status; -} - -/********************************************************************* - * @fn FLASH_ROM_WRITE - * - * @brief Writes a specified FLASH . - * - * @param StartAddr - Writes Flash start address(StartAddr%256 == 0). - * Length - Writes Flash start Length(Length%256 == 0). - * pbuf - Writes Flash value buffer. - * - * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, - * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ROM_WRITE( uint32_t StartAddr, uint32_t *pbuf, uint32_t Length ) -{ - uint32_t i, adr; - uint8_t size; - - FLASH_Status status = FLASH_COMPLETE; - - if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) - { - return FLASH_ADR_RANGE_ERROR; - } - - if((StartAddr + Length) > ValidAddrEnd) - { - return FLASH_OP_RANGE_ERROR; - } - - if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) - { - return FLASH_ALIGN_ERROR; - } - adr = StartAddr; - i = Length >> 8; - - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - - /* Fast program mode unlock */ - FLASH->MODEKEYR = FLASH_KEY1; - FLASH->MODEKEYR = FLASH_KEY2; - - FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); - - do{ - FLASH->CTLR |= CR_PAGE_PG; - FLASH->CTLR |= CR_BUF_RST; - while(FLASH->STATR & SR_BSY) - ; - size = 64; - while(size) - { - *(uint32_t *)StartAddr = *(uint32_t *)pbuf; - FLASH->CTLR |= CR_BUF_LOAD; - while(FLASH->STATR & SR_BSY) - ; - StartAddr += 4; - pbuf += 1; - size -= 1; - } - - FLASH->ADDR = adr; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; - adr += 256; - }while(--i); - - FLASH->CTLR |= CR_FLOCK_Set; - FLASH->CTLR |= CR_LOCK_Set; - - return status; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_flash.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/07/26 + * Description : This file provides all the FLASH firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0xFFFFFFFC) + +/* Flash Control Register bits */ +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FLOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_PAGE_ER_Reset ((uint32_t)0xFFFDFFFF) +#define CR_BUF_LOAD ((uint32_t)0x00040000) +#define CR_BUF_RST ((uint32_t)0x00080000) +#define CR_BER32 ((uint32_t)0x00800000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) + +#if defined(CH32V002) +#define ValidAddrEnd (FLASH_BASE + 0x4000) + +#elif defined(CH32V004) || defined(CH32V005) +#define ValidAddrEnd (FLASH_BASE + 0x8000) + +#elif defined(CH32V006) || defined(CH32V007_M007) +#define ValidAddrEnd (FLASH_BASE + 0xF800) + +#endif + +/* FLASH Size */ +#define Size_256B 0x100 +#define Size_1KB 0x400 +#define Size_32KB 0x8000 + +/******************************************************************************** + * @fn FLASH_SetLatency + * + * @brief Sets the code latency value. + * + * @param FLASH_Latency - specifies the FLASH Latency value. + * FLASH_Latency_0 - FLASH Zero Latency cycle + * FLASH_Latency_1 - FLASH One Latency cycle + * FLASH_Latency_2 - FLASH Two Latency cycles + * + * @return None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + tmpreg = FLASH->ACTLR; + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + FLASH->ACTLR = tmpreg; +} + +/******************************************************************************** + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/******************************************************************************** + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/******************************************************************************** + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page(1KB). + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - The returned value can be:FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH_Unlock(); + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_OPTER_Reset; + + FLASH_Lock(); + } + return status; +} + +/********************************************************************* + * @fn FLASH_OptionBytePR + * + * @brief Programs option bytes. + * + * @param pbuf - data. + * + * @return none + */ +void FLASH_OptionBytePR(u32* pbuf) +{ + uint8_t i; + + FLASH_EraseOptionBytes(); + FLASH_Unlock_Fast(); + FLASH_BufReset(); + + for(i=0; i<4; i++) + { + FLASH_BufLoad((OB_BASE + 4*i), *pbuf++); + } + + FLASH_ProgramPage_Fast(OB_BASE); + FLASH_Lock_Fast(); +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Pages - specifies the address of the pages to be write protected. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint8_t WRP0_Data = 0xFF, WRP1_Data = 0xFF, WRP2_Data = 0xFF, WRP3_Data = 0xFF; + uint32_t buf[4]; + uint8_t i; + FLASH_Status status = FLASH_COMPLETE; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint8_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint8_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint8_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint8_t)((FLASH_Pages & WRP3_Mask) >> 24); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + + buf[2] = ((uint32_t)(((uint32_t)(WRP0_Data) & 0x00FF) + (((uint32_t)(~WRP0_Data) & 0x00FF) << 8) \ + + (((uint32_t)(WRP1_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP1_Data) & 0x00FF) << 24))); + buf[3] = ((uint32_t)(((uint32_t)(WRP2_Data) & 0x00FF) + (((uint32_t)(~WRP2_Data) & 0x00FF) << 8) \ + + (((uint32_t)(WRP3_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP3_Data) & 0x00FF) << 24))); + + FLASH_OptionBytePR(buf); + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EnableReadOutProtection + * + * @brief Enables the read out protection. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_EnableReadOutProtection(void) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t buf[4]; + uint8_t i; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + + buf[0] = 0x000000FF + (buf[0] & 0xFFFF0000); + FLASH_OptionBytePR(buf); + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / + * RST_STDBY / OB_PowerON_Start_Mode. + * + * @param OB_IWDG - Selects the IWDG mode + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY. + * OB_STDBY_RST - Reset generated when entering in STANDBY. + * OB_RST - Selects the reset IO mode and Ignore delay time. + * OB_RST_NoEN - Reset IO disable. + * OB_RST_EN_DT12ms - Reset IO enable and Ignore delay time 12ms. + * OB_RST_EN_DT1ms - Reset IO enable and Ignore delay time 1ms. + * OB_RST_EN_DT128us - Reset IO enable and Ignore delay time 128us. + * OB_PowerON_Start_Mode - Selects start mode after power on. + * OB_PowerON_Start_Mode_BOOT - Boot start after power on. + * OB_PowerON_Start_Mode_USER - User start after power on. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STDBY, uint16_t OB_RST, uint16_t OB_PowerON_Start_Mode) +{ + FLASH_Status status = FLASH_COMPLETE; + uint8_t UserByte; + uint32_t buf[4]; + uint8_t i; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + UserByte = OB_IWDG | (uint16_t)(OB_STDBY | (uint16_t)(OB_RST | (uint16_t)(OB_PowerON_Start_Mode | 0xC2))); + + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + buf[0] = ((uint32_t)((((uint32_t)(UserByte) & 0x00FF) << 16) + (((uint32_t)(~UserByte) & 0x00FF) << 24))) + 0x00005AA5; + + FLASH_OptionBytePR(buf); + } + + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STDBY(Bit2) + * , RST_MODE(Bit[3:4]) and START_MODE(Bit5). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt. + * FLASH_IT_EOP - FLASH end of operation Interrupt. + * FLASH_IT_FWAKE - FLASH Wake Up Interrupt. + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_FWAKE - FLASH Wake Up flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_FWAKE - FLASH Wake Up flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + if(FLASH_FLAG == FLASH_FLAG_FWAKE) + { + FLASH->STATR &= ~FLASH_FLAG; + } + else + { + FLASH->STATR = FLASH_FLAG; + } +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_FLOCK_Set; +} + +/********************************************************************* + * @fn FLASH_BufReset + * + * @brief Flash Buffer reset. + * + * @return none + */ +void FLASH_BufReset(void) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_BufLoad + * + * @brief Flash Buffer load(4Byte). + * + * @param Address - specifies the address to be programmed. + * Data0 - specifies the data0 to be programmed. + * + * @return none + */ +void FLASH_BufLoad(uint32_t Address, uint32_t Data0) +{ + if(((Address >= ValidAddrStart) && (Address < ValidAddrEnd)) || ((Address >= OB_BASE) && (Address < OB_BASE+0x100))) + { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + *(__IO uint32_t *)(Address) = Data0; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + } +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) + { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_ER; + } +} + +/********************************************************************* + * @fn FLASH_EraseBlock_32K_Fast + * + * @brief Erases a specified FLASH Block (1Block = 32KByte). + * + * @param Block_Address - The block address to be erased. + * This function is only capable of erasing addresses + * in the range of 0x08000000~0x08008000. + * + * @return none + */ +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + Block_Address &= 0xFFFF8000; + + FLASH->CTLR |= CR_BER32; + FLASH->ADDR = Block_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_BER32; +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address) +{ + if(((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) || (Page_Address == OB_BASE)) + { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + } +} + +/********************************************************************* + * @fn SystemReset_StartMode + * + * @brief Start mode after system reset. + * + * @param Mode - Start mode. + * Start_Mode_USER - USER start after system reset + * Start_Mode_BOOT - Boot start after system reset + * + * @return none + */ +void SystemReset_StartMode(uint32_t Mode) +{ + FLASH_Unlock(); + + FLASH->BOOT_MODEKEYR = FLASH_KEY1; + FLASH->BOOT_MODEKEYR = FLASH_KEY2; + + FLASH->STATR &= ~(1<<14); + if(Mode == Start_Mode_BOOT){ + FLASH->STATR |= (1<<14); + } + + FLASH_Lock(); +} + +/********************************************************************* + * @fn ROM_ERASE + * + * @brief Select erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Cnt - Erases count. + * Erase_Size - Erases size select.The returned value can be: + * Size_32KB, Size_1KB, Size_256B. + * + * @return none. + */ +static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + do{ + if(Erase_Size == Size_32KB) + { + FLASH->CTLR |= CR_BER32; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR |= CR_PER_Set; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR |= CR_PAGE_ER; + } + + FLASH->ADDR = StartAddr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + + if(Erase_Size == Size_32KB) + { + FLASH->CTLR &= ~CR_BER32; + StartAddr += Size_32KB; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR &= ~CR_PER_Set; + StartAddr += Size_1KB; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR &= ~CR_PAGE_ER; + StartAddr += Size_256B; + } + }while(--Cnt); +} + +/********************************************************************* + * @fn FLASH_ROM_ERASE + * + * @brief Erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Length - Erases Flash start Length(Length%256 == 0). + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_ERASE( uint32_t StartAddr, uint32_t Length ) +{ + uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + Addr0 = StartAddr; + + if(Length >= Size_32KB) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_1KB) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_256B) + { + Length0 = Length; + } + + /* Erase 32KB */ + if(Length0 >= Size_32KB)//front + { + Length = Length0; + if(Addr0 & (Size_32KB - 1)) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB); + } + + if(Length1 >= Size_32KB)//back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_32KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1))); + Length1 = (StartAddr + Length1) & (Size_32KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB); + } + + /* Erase 1KB */ + if(Length0 >= Size_1KB) //front + { + Length = Length0; + if(Addr0 & (Size_1KB - 1)) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB); + } + + if(Length1 >= Size_1KB) //back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_1KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1))); + Length1 = (StartAddr + Length1) & (Size_1KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB); + } + + /* Erase 256B */ + if(Length0)//front + { + ROM_ERASE(Addr0, (Length0 >> 8), Size_256B); + } + + if(Length1)//back + { + ROM_ERASE(Addr1, (Length1 >> 8), Size_256B); + } + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + +/********************************************************************* + * @fn FLASH_ROM_WRITE + * + * @brief Writes a specified FLASH . + * + * @param StartAddr - Writes Flash start address(StartAddr%256 == 0). + * Length - Writes Flash start Length(Length%256 == 0). + * pbuf - Writes Flash value buffer. + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_WRITE( uint32_t StartAddr, uint32_t *pbuf, uint32_t Length ) +{ + uint32_t i, adr; + uint8_t size; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + adr = StartAddr; + i = Length >> 8; + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + do{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + size = 64; + while(size) + { + *(uint32_t *)StartAddr = *(uint32_t *)pbuf; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + StartAddr += 4; + pbuf += 1; + size -= 1; + } + + FLASH->ADDR = adr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + adr += 256; + }while(--i); + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_gpio.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_gpio.c index 3b71966..4a87c24 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_gpio.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_gpio.c @@ -1,740 +1,729 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_gpio.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the GPIO firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* MASK */ -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) -#define DBGAFR_TIM2RP_MASK ((uint32_t)0x00400000) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) - -/********************************************************************* - * @fn GPIO_DeInit - * - * @brief Deinitializes the GPIOx peripheral registers to their default - * reset values. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * - * @return none - */ -void GPIO_DeInit(GPIO_TypeDef *GPIOx) -{ - if(GPIOx == GPIOA) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOA, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOA, DISABLE); - } - else if(GPIOx == GPIOB) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOB, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOB, DISABLE); - } - else if(GPIOx == GPIOC) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOC, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOC, DISABLE); - } - else if(GPIOx == GPIOD) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOD, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOD, DISABLE); - } -} - -/********************************************************************* - * @fn GPIO_AFIODeInit - * - * @brief Deinitializes the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * - * @return none - */ -void GPIO_AFIODeInit(void) -{ - RCC_PB2PeriphResetCmd(RCC_PB2Periph_AFIO, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_AFIO, DISABLE); -} - -/********************************************************************* - * @fn GPIO_Init - * - * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. - * - * @return none - */ -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - - if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - { - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } - - if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) - { - tmpreg = GPIOx->CFGLR; - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << pinpos); - } - else - { - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CFGLR = tmpreg; - } -} - -/********************************************************************* - * @fn GPIO_StructInit - * - * @brief Fills each GPIO_InitStruct member with its default - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) -{ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_30MHz; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/********************************************************************* - * @fn GPIO_ReadInputDataBit - * - * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. - * - * @param GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..7). - * - * @return The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadInputData - * - * @brief Reads the specified GPIO input data port. - * - * @param GPIOx: where x can be (A..D) to select the GPIO peripheral. - * - * @return The input port pin value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) -{ - return ((uint16_t)GPIOx->INDR); -} - -/********************************************************************* - * @fn GPIO_ReadOutputDataBit - * - * @brief Reads the specified output data port bit. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..7). - * - * @return none - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadOutputData - * - * @brief Reads the specified GPIO output data port. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * - * @return GPIO output port pin value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) -{ - return ((uint16_t)GPIOx->OUTDR); -} - -/********************************************************************* - * @fn GPIO_SetBits - * - * @brief Sets the selected data port bits. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). - * - * @return none - */ -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BSHR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_ResetBits - * - * @brief Clears the selected data port bits. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). - * - * @return none - */ -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BCR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_WriteBit - * - * @brief Sets or clears the selected data port bit. - * - * @param GPIO_Pin - specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..7). - * BitVal - specifies the value to be written to the selected bit. - * Bit_RESET - to clear the port pin. - * Bit_SET - to set the port pin. - * - * @return none - */ -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - if(BitVal != Bit_RESET) - { - GPIOx->BSHR = GPIO_Pin; - } - else - { - GPIOx->BCR = GPIO_Pin; - } -} - -/********************************************************************* - * @fn GPIO_Write - * - * @brief Writes data to the specified GPIO data port. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * PortVal - specifies the value to be written to the port output data register. - * - * @return none - */ -void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) -{ - GPIOx->OUTDR = PortVal; -} - -/********************************************************************* - * @fn GPIO_PinLockConfig - * - * @brief Locks GPIO Pins configuration registers. - * - * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). - * - * @return none - */ -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - - tmp |= GPIO_Pin; - GPIOx->LCKR = tmp; - GPIOx->LCKR = GPIO_Pin; - GPIOx->LCKR = tmp; - tmp = GPIOx->LCKR; - tmp = GPIOx->LCKR; -} - -/********************************************************************* - * @fn GPIO_PinRemapConfig - * - * @brief Changes the mapping of the specified pin. - * - * @param GPIO_Remap - selects the pin to remap. - * GPIO_PartialRemap1_SPI1 - SPI1 Partial Alternate Function mapping - * GPIO_PartialRemap2_SPI1 - SPI1 Partia2 Alternate Function mapping - * GPIO_PartialRemap3_SPI1 - SPI1 Partia3 Alternate Function mapping - * GPIO_PartialRemap4_SPI1 - SPI1 Partia4 Alternate Function mapping - * GPIO_PartialRemap5_SPI1 - SPI1 Partia5 Alternate Function mapping - * GPIO_FullRemap_SPI1 - SPI1 Full Alternate Function mapping - * GPIO_PartialRemap1_I2C1 - I2C1 Partia1 Alternate Function mapping - * GPIO_PartialRemap2_I2C1 - I2C1 Partia2 Alternate Function mapping - * GPIO_PartialRemap3_I2C1 - I2C1 Partia3 Alternate Function mapping - * GPIO_FullRemap4_I2C1 - I2C1 Full Alternate Function mapping - * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping - * GPIO_PartialRemap3_USART1 - USART1 Partial3 Alternate Function mapping - * GPIO_PartialRemap4_USART1 - USART1 Partial4 Alternate Function mapping - * GPIO_PartialRemap5_USART1 - USART1 Partial5 Alternate Function mapping - * GPIO_PartialRemap6_USART1 - USART1 Partial6 Alternate Function mapping - * GPIO_PartialRemap7_USART1 - USART1 Partial7 Alternate Function mapping - * GPIO_PartialRemap8_USART1 - USART1 Partial8 Alternate Function mapping - * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping - * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping - * GPIO_PartialRemap3_TIM1 - TIM1 Partial3 Alternate Function mapping - * GPIO_PartialRemap4_TIM1 - TIM1 Partial4 Alternate Function mapping - * GPIO_PartialRemap5_TIM1 - TIM1 Partial5 Alternate Function mapping - * GPIO_PartialRemap6_TIM1 - TIM1 Partial6 Alternate Function mapping - * GPIO_PartialRemap7_TIM1 - TIM1 Partial7 Alternate Function mapping - * GPIO_PartialRemap8_TIM1 - TIM1 Partial8 Alternate Function mapping - * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping - * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping - * GPIO_PartialRemap3_TIM2 - TIM2 Partial3 Alternate Function mapping - * GPIO_PartialRemap4_TIM2 - TIM2 Partial4 Alternate Function mapping - * GPIO_PartialRemap5_TIM2 - TIM2 Partial5 Alternate Function mapping - * GPIO_PartialRemap6_TIM2 - TIM2 Partial6 Alternate Function mapping - * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping - * GPIO_Remap_PA1_2 - PA1 and PA2 Alternate Function mapping - * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion mapping - * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion mapping - * GPIO_PartialRemap1_USART2 - USART2 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_USART2 - USART2 Partial2 Alternate Function mapping - * GPIO_PartialRemap3_USART2 - USART2 Partial3 Alternate Function mapping - * GPIO_PartialRemap4_USART2 - USART2 Partial4 Alternate Function mapping - * GPIO_PartialRemap5_USART2 - USART2 Partial5 Alternate Function mapping - * GPIO_FullRemap_USART2 - USART2 Full Alternate Function mapping - * GPIO_Remap_LSI_CAL - LSI calibration Alternate Function mapping - * GPIO_Remap_SDI_Disable - SDI Disabled - * NewState - ENABLE or DISABLE. - * - * @return none - */ - -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) -{ - uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; - - tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - tmp = GPIO_Remap & LSB_MASK; - tmpreg = AFIO->PCFR1; - - /* Clear bit */ - if((GPIO_Remap & 0x08000000) == 0x08000000) /* 3bit */ - { - if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] SDI */ - { - tmpreg &= DBGAFR_SDI_MASK; - AFIO->PCFR1 &= DBGAFR_SDI_MASK; - } - else if((GPIO_Remap & DBGAFR_TIM2RP_MASK) == DBGAFR_TIM2RP_MASK) /* [16:14] 3bit */ - { - tmp1 = ((uint32_t)0x07) << tmpmask; - tmpreg &= ~tmp1; - - if(NewState != DISABLE) - { - tmpreg |= (tmp << tmpmask); - } - - AFIO->PCFR1 = tmpreg; - return; - } - else if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == DBGAFR_LOCATION_MASK) /* [31:16] 3bit */ - { - tmp1 = ((uint32_t)0x07) << (tmpmask + 0x10); - tmpreg &= ~tmp1; - } - else /* [15:0] 3bit */ - { - tmp1 = ((uint32_t)0x07) << tmpmask; - tmpreg &= ~tmp1; - } - } - else - { - if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 4bit */ - { - tmp1 = ((uint32_t)0x0F) << tmpmask; - tmpreg &= ~tmp1; - } - else /* [31:0] 1bit */ - { - tmpreg &= ~(tmp << (((GPIO_Remap & 0x00FFFFFF ) >> 0x15) * 0x10)); - } - } - - /* Set bit */ - if(NewState != DISABLE) - { - tmpreg |= (tmp << (((GPIO_Remap & 0x00FFFFFF )>> 0x15) * 0x10)); - } - - AFIO->PCFR1 = tmpreg; -} - -/********************************************************************* - * @fn GPIO_EXTILineConfig - * - * @brief Selects the GPIO pin used as EXTI Line. - * - * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). - * GPIO_PinSource - specifies the EXTI line to be configured. - * This parameter can be GPIO_PinSourcex where x can be (0..7). - * - * @return none - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmp = 0x00; - - tmp = ((uint32_t)(3<<(GPIO_PinSource<<1))); - AFIO->EXTICR &= ~tmp; - AFIO->EXTICR |= ((uint32_t)(GPIO_PortSource<<(GPIO_PinSource<<1))); -} - -/********************************************************************* - * @fn GPIO_IPD_Unused - * - * @brief Configure unused GPIO as input pull-down. - * - * @param none - * - * @return none - */ -void GPIO_IPD_Unused(void) -{ - GPIO_InitTypeDef GPIO_InitStructure = {0}; - uint32_t chip = 0; - RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA |RCC_PB2Periph_GPIOB | RCC_PB2Periph_GPIOC | RCC_PB2Periph_GPIOD, ENABLE); - chip = *( uint32_t * )0x1FFFF704 & (~0x000000F0); - switch(chip) - { - case 0x00630600: //CH32V006F8P6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ - |GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - break; - } - case 0x00620600: //CH32V006F8U6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ - |GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - break; - } - case 0x00610600: //CH32V006E8R6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOC, &GPIO_InitStructure); - break; - } - case 0x00600600: //CH32V006K8U6 - { - break; - } - - case 0x00720600: //CH32V007F8U6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_4\ - |GPIO_Pin_5|GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ - |GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOC, &GPIO_InitStructure); - break; - } - case 0x00710600: //CH32V007E8R6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOC, &GPIO_InitStructure); - break; - } - case 0x00700800: //CH32M007G8R6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2|GPIO_Pin_3\ - |GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ - |GPIO_Pin_4|GPIO_Pin_5|GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOD, &GPIO_InitStructure); - break; - } - - case 0x00530600: //CH32V005D6U6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_3; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3|GPIO_Pin_5; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOD, &GPIO_InitStructure); - break; - } - case 0x00520600: //CH32V005F6P6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_3; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - break; - } - case 0x00510600: //CH32V005F6U6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_3; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - break; - } - case 0x00500600: //CH32V005E6R6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOC, &GPIO_InitStructure); - break; - } - - case 0x00240600: //CH32V002J4M6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_4\ - |GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ - |GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2|GPIO_Pin_3\ - |GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOD, &GPIO_InitStructure); - break; - } - - case 0x00230600: //CH32V002D4U6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_4\ - |GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_5; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOD, &GPIO_InitStructure); - break; - } - case 0x00220600: //CH32V002A4M6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_4\ - |GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2|GPIO_Pin_3; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOD, &GPIO_InitStructure); - break; - } - case 0x00210600: //CH32V002F4U6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_4\ - |GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - break; - } - case 0x00200600: //CH32V002F4P6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_4\ - |GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - break; - } - case 0x00400600: //CH32V004F6P1 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ - |GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - break; - } - case 0x00410600: //CH32V004F6U1 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ - |GPIO_Pin_6|GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ - |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - break; - } - - default: - { - break; - } - - } - -} - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_gpio.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/07 + * Description : This file provides all the GPIO firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* MASK */ +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) +#define DBGAFR_TIM2RP_MASK ((uint32_t)0x00400000) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOA, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOB, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOC, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOD, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_GPIOD, DISABLE); + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_PB2PeriphResetCmd(RCC_PB2Periph_AFIO, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..7). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx: where x can be (A..D) to select the GPIO peripheral. + * + * @return The input port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->INDR); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..7). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->OUTDR); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BSHR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..7). + * BitVal - specifies the value to be written to the selected bit. + * Bit_RESET - to clear the port pin. + * Bit_SET - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = GPIO_Pin; + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_PartialRemap1_SPI1 - SPI1 Partial Alternate Function mapping + * GPIO_PartialRemap2_SPI1 - SPI1 Partia2 Alternate Function mapping + * GPIO_PartialRemap3_SPI1 - SPI1 Partia3 Alternate Function mapping + * GPIO_PartialRemap4_SPI1 - SPI1 Partia4 Alternate Function mapping + * GPIO_PartialRemap5_SPI1 - SPI1 Partia5 Alternate Function mapping + * GPIO_FullRemap_SPI1 - SPI1 Full Alternate Function mapping + * GPIO_PartialRemap1_I2C1 - I2C1 Partia1 Alternate Function mapping + * GPIO_PartialRemap2_I2C1 - I2C1 Partia2 Alternate Function mapping + * GPIO_PartialRemap3_I2C1 - I2C1 Partia3 Alternate Function mapping + * GPIO_FullRemap4_I2C1 - I2C1 Full Alternate Function mapping + * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_USART1 - USART1 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_USART1 - USART1 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_USART1 - USART1 Partial5 Alternate Function mapping + * GPIO_PartialRemap6_USART1 - USART1 Partial6 Alternate Function mapping + * GPIO_PartialRemap7_USART1 - USART1 Partial7 Alternate Function mapping + * GPIO_PartialRemap8_USART1 - USART1 Partial8 Alternate Function mapping + * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_TIM1 - TIM1 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_TIM1 - TIM1 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_TIM1 - TIM1 Partial5 Alternate Function mapping + * GPIO_PartialRemap6_TIM1 - TIM1 Partial6 Alternate Function mapping + * GPIO_PartialRemap7_TIM1 - TIM1 Partial7 Alternate Function mapping + * GPIO_PartialRemap8_TIM1 - TIM1 Partial8 Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_TIM2 - TIM2 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_TIM2 - TIM2 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_TIM2 - TIM2 Partial5 Alternate Function mapping + * GPIO_PartialRemap6_TIM2 - TIM2 Partial6 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_Remap_PA1_2 - PA1 and PA2 Alternate Function mapping + * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion mapping + * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion mapping + * GPIO_PartialRemap1_USART2 - USART2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART2 - USART2 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_USART2 - USART2 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_USART2 - USART2 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_USART2 - USART2 Partial5 Alternate Function mapping + * GPIO_FullRemap_USART2 - USART2 Full Alternate Function mapping + * GPIO_Remap_LSI_CAL - LSI calibration Alternate Function mapping + * GPIO_Remap_SDI_Disable - SDI Disabled + * NewState - ENABLE or DISABLE. + * + * @return none + */ + +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + tmpreg = AFIO->PCFR1; + + /* Clear bit */ + if((GPIO_Remap & 0x08000000) == 0x08000000) /* 3bit */ + { + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] SDI */ + { + tmpreg &= DBGAFR_SDI_MASK; + AFIO->PCFR1 &= DBGAFR_SDI_MASK; + } + else if((GPIO_Remap & DBGAFR_TIM2RP_MASK) == DBGAFR_TIM2RP_MASK) /* [16:14] 3bit */ + { + tmp1 = ((uint32_t)0x07) << tmpmask; + tmpreg &= ~tmp1; + + if(NewState != DISABLE) + { + tmpreg |= (tmp << tmpmask); + } + + AFIO->PCFR1 = tmpreg; + return; + } + else if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == DBGAFR_LOCATION_MASK) /* [31:16] 3bit */ + { + tmp1 = ((uint32_t)0x07) << (tmpmask + 0x10); + tmpreg &= ~tmp1; + } + else /* [15:0] 3bit */ + { + tmp1 = ((uint32_t)0x07) << tmpmask; + tmpreg &= ~tmp1; + } + } + else + { + if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 4bit */ + { + tmp1 = ((uint32_t)0x0F) << tmpmask; + tmpreg &= ~tmp1; + } + else /* [31:0] 1bit */ + { + tmpreg &= ~(tmp << (((GPIO_Remap & 0x00FFFFFF ) >> 0x15) * 0x10)); + } + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg |= (tmp << (((GPIO_Remap & 0x00FFFFFF )>> 0x15) * 0x10)); + } + + AFIO->PCFR1 = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..7). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)(3<<(GPIO_PinSource<<1))); + AFIO->EXTICR &= ~tmp; + AFIO->EXTICR |= ((uint32_t)(GPIO_PortSource<<(GPIO_PinSource<<1))); +} + +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-down. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + RCC_PB2PeriphClockCmd(RCC_PB2Periph_GPIOA |RCC_PB2Periph_GPIOB | RCC_PB2Periph_GPIOC | RCC_PB2Periph_GPIOD, ENABLE); + chip = *( uint32_t * )0x1FFFF704 & (~0x000000F0); + switch(chip) + { + case 0x00630600: //CH32V006F8P6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + break; + } + case 0x00620600: //CH32V006F8U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + break; + } + case 0x00610600: //CH32V006E8R6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x00600600: //CH32V006K8U6 + { + break; + } + + case 0x00720600: //CH32V007K8U6 + { + break; + } + case 0x00710600: //CH32V007E8R6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x00700800: //CH32M007G8R6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_4|GPIO_Pin_5|GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + + case 0x00530600: //CH32V005D6U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_3; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3|GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x00520600: //CH32V005F6P6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_3; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + break; + } + case 0x00510600: //CH32V005F6U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_3; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + break; + } + case 0x00500600: //CH32V005E6R6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + + case 0x00240600: //CH32V002J4M6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + + case 0x00230600: //CH32V002D4U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x00220600: //CH32V002A4M6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2|GPIO_Pin_3; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + case 0x00210600: //CH32V002F4U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + break; + } + case 0x00200600: //CH32V002F4P6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + break; + } + case 0x00400600: //CH32V004F6P1 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + break; + } + case 0x00410600: //CH32V004F6U1 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + break; + } + + default: + { + break; + } + + } + +} + diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_i2c.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_i2c.c index b6d1c06..f9d12dc 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_i2c.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_i2c.c @@ -1,973 +1,973 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_i2c.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the I2C firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* I2C SPE mask */ -#define CTLR1_PE_Set ((uint16_t)0x0001) -#define CTLR1_PE_Reset ((uint16_t)0xFFFE) - -/* I2C START mask */ -#define CTLR1_START_Set ((uint16_t)0x0100) -#define CTLR1_START_Reset ((uint16_t)0xFEFF) - -/* I2C STOP mask */ -#define CTLR1_STOP_Set ((uint16_t)0x0200) -#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) - -/* I2C ACK mask */ -#define CTLR1_ACK_Set ((uint16_t)0x0400) -#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) - -/* I2C ENGC mask */ -#define CTLR1_ENGC_Set ((uint16_t)0x0040) -#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) - -/* I2C SWRST mask */ -#define CTLR1_SWRST_Set ((uint16_t)0x8000) -#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) - -/* I2C PEC mask */ -#define CTLR1_PEC_Set ((uint16_t)0x1000) -#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) - -/* I2C ENPEC mask */ -#define CTLR1_ENPEC_Set ((uint16_t)0x0020) -#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) - -/* I2C ENARP mask */ -#define CTLR1_ENARP_Set ((uint16_t)0x0010) -#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) - -/* I2C NOSTRETCH mask */ -#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) -#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) - -/* I2C registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) - -/* I2C DMAEN mask */ -#define CTLR2_DMAEN_Set ((uint16_t)0x0800) -#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) - -/* I2C LAST mask */ -#define CTLR2_LAST_Set ((uint16_t)0x1000) -#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) - -/* I2C FREQ mask */ -#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) - -/* I2C ADD0 mask */ -#define OADDR1_ADD0_Set ((uint16_t)0x0001) -#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) - -/* I2C ENDUAL mask */ -#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) -#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) - -/* I2C ADD2 mask */ -#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) - -/* I2C F/S mask */ -#define CKCFGR_FS_Set ((uint16_t)0x8000) - -/* I2C CCR mask */ -#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) - -/* I2C FLAG mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) - -/* I2C Interrupt Enable mask */ -#define ITEN_Mask ((uint32_t)0x07000000) - -/********************************************************************* - * @fn I2C_DeInit - * - * @brief Deinitializes the I2Cx peripheral registers to their default - * reset values. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * - * @return none - */ -void I2C_DeInit(I2C_TypeDef *I2Cx) -{ - if(I2Cx == I2C1) - { - RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C1, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C1, DISABLE); - } -} - -/********************************************************************* - * @fn I2C_Init - * - * @brief Initializes the I2Cx peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified I2C peripheral. - * - * @return none - */ -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) -{ - uint16_t tmpreg = 0, freqrange = 0; - uint16_t result = 0x04; - uint32_t pclk1 = 8000000; - - RCC_ClocksTypeDef rcc_clocks; - - tmpreg = I2Cx->CTLR2; - tmpreg &= CTLR2_FREQ_Reset; - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - I2Cx->CTLR2 = tmpreg; - - I2Cx->CTLR1 &= CTLR1_PE_Reset; - tmpreg = 0; - - if(I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - - if(result < 0x04) - { - result = 0x04; - } - - tmpreg |= result; - } - else - { - if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - result |= I2C_DutyCycle_16_9; - } - - if((result & CKCFGR_CCR_Set) == 0) - { - result |= (uint16_t)0x0001; - } - - tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); - } - - I2Cx->CKCFGR = tmpreg; - I2Cx->CTLR1 |= CTLR1_PE_Set; - - tmpreg = I2Cx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - I2Cx->CTLR1 = tmpreg; - - I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/********************************************************************* - * @fn I2C_StructInit - * - * @brief Fills each I2C_InitStruct member with its default value. - * - * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) -{ - I2C_InitStruct->I2C_ClockSpeed = 5000; - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStruct->I2C_OwnAddress1 = 0; - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/********************************************************************* - * @fn I2C_Cmd - * - * @brief Enables or disables the specified I2C peripheral. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PE_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PE_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMACmd - * - * @brief Enables or disables the specified I2C DMA requests. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_DMAEN_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMALastTransferCmd - * - * @brief Specifies if the next DMA transfer will be the last one. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_LAST_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_LAST_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTART - * - * @brief Generates I2Cx communication START condition. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_START_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_START_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTOP - * - * @brief Generates I2Cx communication STOP condition. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_STOP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_STOP_Reset; - } -} - -/********************************************************************* - * @fn I2C_AcknowledgeConfig - * - * @brief Enables or disables the specified I2C acknowledge feature. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ACK_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ACK_Reset; - } -} - -/********************************************************************* - * @fn I2C_OwnAddress2Config - * - * @brief Configures the specified I2C own address2. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * Address - specifies the 7bit I2C own address2. - * - * @return none - */ -void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - tmpreg = I2Cx->OADDR2; - tmpreg &= OADDR2_ADD2_Reset; - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - I2Cx->OADDR2 = tmpreg; -} - -/********************************************************************* - * @fn I2C_DualAddressCmd - * - * @brief Enables or disables the specified I2C dual addressing mode. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; - } - else - { - I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; - } -} - -/********************************************************************* - * @fn I2C_GeneralCallCmd - * - * @brief Enables or disables the specified I2C general call feature. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENGC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENGC_Reset; - } -} - -/********************************************************************* - * @fn I2C_ITConfig - * - * @brief Enables or disables the specified I2C interrupts. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. - * I2C_IT_BUF - Buffer interrupt mask. - * I2C_IT_EVT - Event interrupt mask. - * I2C_IT_ERR - Error interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= I2C_IT; - } - else - { - I2Cx->CTLR2 &= (uint16_t)~I2C_IT; - } -} - -/********************************************************************* - * @fn I2C_SendData - * - * @brief Sends a data byte through the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * Data - Byte to be transmitted. - * - * @return none - */ -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) -{ - I2Cx->DATAR = Data; -} - -/********************************************************************* - * @fn I2C_ReceiveData - * - * @brief Returns the most recent received data by the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * - * @return The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) -{ - return (uint8_t)I2Cx->DATAR; -} - -/********************************************************************* - * @fn I2C_Send7bitAddress - * - * @brief Transmits the address byte to select the slave device. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * Address - specifies the slave address which will be transmitted. - * I2C_Direction - specifies whether the I2C device will be a - * Transmitter or a Receiver. - * I2C_Direction_Transmitter - Transmitter mode. - * I2C_Direction_Receiver - Receiver mode. - * - * @return none - */ -void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - if(I2C_Direction != I2C_Direction_Transmitter) - { - Address |= OADDR1_ADD0_Set; - } - else - { - Address &= OADDR1_ADD0_Reset; - } - - I2Cx->DATAR = Address; -} - -/********************************************************************* - * @fn I2C_ReadRegister - * - * @brief Reads the specified I2C register and returns its value. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_Register - specifies the register to read. - * I2C_Register_CTLR1. - * I2C_Register_CTLR2. - * I2C_Register_OADDR1. - * I2C_Register_OADDR2. - * I2C_Register_DATAR. - * I2C_Register_STAR1. - * I2C_Register_STAR2. - * I2C_Register_CKCFGR. - * - * @return none - */ -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)I2Cx; - tmp += I2C_Register; - - return (*(__IO uint16_t *)tmp); -} - -/********************************************************************* - * @fn I2C_SoftwareResetCmd - * - * @brief Enables or disables the specified I2C software reset. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_SWRST_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_SWRST_Reset; - } -} - -/********************************************************************* - * @fn I2C_NACKPositionConfig - * - * @brief Selects the specified I2C NACK position in master receiver mode. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_NACKPosition - specifies the NACK position. - * I2C_NACKPosition_Next - indicates that the next byte will be - * the last received byte. - * I2C_NACKPosition_Current - indicates that current byte is the - * last received byte. - * Note- - * This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * @return none - */ -void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) -{ - if(I2C_NACKPosition == I2C_NACKPosition_Next) - { - I2Cx->CTLR1 |= I2C_NACKPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_NACKPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_TransmitPEC - * - * @brief Enables or disables the specified I2C PEC transfer. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_PECPositionConfig - * - * @brief Selects the specified I2C PEC position. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_PECPosition - specifies the PEC position. - * I2C_PECPosition_Next - indicates that the next byte is PEC. - * I2C_PECPosition_Current - indicates that current byte is PEC. - * - * @return none - */ -void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) -{ - if(I2C_PECPosition == I2C_PECPosition_Next) - { - I2Cx->CTLR1 |= I2C_PECPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_PECPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_CalculatePEC - * - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * - * @param I2Cx- where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENPEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_GetPEC - * - * @brief Returns the PEC value for the specified I2C. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * - * @return The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) -{ - return ((I2Cx->STAR2) >> 8); -} - -/********************************************************************* - * @fn I2C_ARPCmd - * - * @brief Enables or disables the specified I2C ARP. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return The PEC value. - */ -void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENARP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENARP_Reset; - } -} - -/********************************************************************* - * @fn I2C_StretchClockCmd - * - * @brief Enables or disables the specified I2C Clock stretching. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState == DISABLE) - { - I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; - } -} - -/********************************************************************* - * @fn I2C_FastModeDutyCycleConfig - * - * @brief Selects the specified I2C fast mode duty cycle. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_DutyCycle - specifies the fast mode duty cycle. - * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. - * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. - * - * @return none - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) -{ - if(I2C_DutyCycle != I2C_DutyCycle_16_9) - { - I2Cx->CKCFGR &= I2C_DutyCycle_2; - } - else - { - I2Cx->CKCFGR |= I2C_DutyCycle_16_9; - } -} - -/********************************************************************* - * @fn I2C_CheckEvent - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx- where x can be 1 to select the I2C peripheral. - * I2C_EVENT: specifies the event to be checked. - * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. - * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. - * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. - * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. - * I2C_EVENT_MASTER_MODE_SELECT - EVT5. - * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. - * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. - * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. - * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. - * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. - * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. - * - * @return ErrorStatus - READY or NoREADY. - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = NoREADY; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - - lastevent = (flag1 | flag2) & FLAG_Mask; - - if((lastevent & I2C_EVENT) == I2C_EVENT) - { - status = READY; - } - else - { - status = NoREADY; - } - - return status; -} - -/********************************************************************* - * @fn I2C_GetLastEvent - * - * @brief Returns the last I2Cx Event. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * - * @return none - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - lastevent = (flag1 | flag2) & FLAG_Mask; - - return lastevent; -} - -/********************************************************************* - * @fn I2C_GetFlagStatus - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to check. - * I2C_FLAG_DUALF - Dual flag (Slave mode). - * I2C_FLAG_GENCALL - General call header flag (Slave mode). - * I2C_FLAG_TRA - Transmitter/Receiver flag. - * I2C_FLAG_BUSY - Bus busy flag. - * I2C_FLAG_MSL - Master/Slave flag. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * I2C_FLAG_TXE - Data register empty flag (Transmitter). - * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. - * I2C_FLAG_STOPF - Stop detection flag (Slave mode). - * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). - * I2C_FLAG_BTF - Byte transfer finished flag. - * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDA". - * I2C_FLAG_SB - Start bit flag (Master mode). - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - i2cxbase = (uint32_t)I2Cx; - i2creg = I2C_FLAG >> 28; - I2C_FLAG &= FLAG_Mask; - - if(i2creg != 0) - { - i2cxbase += 0x14; - } - else - { - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearFlag - * - * @brief Clears the I2Cx's pending flags. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to clear. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * Note- - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DATAR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DATAR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SATR2 register ((void)(I2Cx->STAR2)). - * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR - * register (I2C_SendData()). - * @return none - */ -void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - - flagpos = I2C_FLAG & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} - -/********************************************************************* - * @fn I2C_GetITStatus - * - * @brief Checks whether the specified I2C interrupt has occurred or not. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * II2C_IT - specifies the interrupt source to check. - * I2C_IT_PECERR - PEC error in reception flag. - * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). - * I2C_IT_AF - Acknowledge failure flag. - * I2C_IT_ARLO - Arbitration lost flag (Master mode). - * I2C_IT_BERR - Bus error flag. - * I2C_IT_TXE - Data register empty flag (Transmitter). - * I2C_IT_RXNE - Data register not empty (Receiver) flag. - * I2C_IT_STOPF - Stop detection flag (Slave mode). - * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). - * I2C_IT_BTF - Byte transfer finished flag. - * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched - * flag (Slave mode)"ENDAD". - * I2C_IT_SB - Start bit flag (Master mode). - * - * @return none - */ -ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); - I2C_IT &= FLAG_Mask; - - if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearITPendingBit - * - * @brief Clears the I2Cx interrupt pending bits. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_IT - specifies the interrupt pending bit to clear. - * I2C_IT_PECERR - PEC error in reception interrupt. - * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). - * I2C_IT_AF - Acknowledge failure interrupt. - * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). - * I2C_IT_BERR - Bus error interrupt. - * Note- - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DATAR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DATAR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_STAR2 register ((void)(I2Cx->STAR2)). - * - SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DATAR register (I2C_SendData()). - * - * @return none - */ -void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - - flagpos = I2C_IT & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} - - - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_i2c.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file provides all the I2C firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C1, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_I2C1, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * Note- + * This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. + * I2C_EVENT_MASTER_MODE_SELECT - EVT5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. + * + * @return ErrorStatus - READY or NoREADY. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = NoREADY; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = READY; + } + else + { + status = NoREADY; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SATR2 register ((void)(I2Cx->STAR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR + * register (I2C_SendData()). + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_STAR2 register ((void)(I2Cx->STAR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DATAR register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + + + + + + + diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_iwdg.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_iwdg.c index dc90b22..d7244b0 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_iwdg.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_iwdg.c @@ -1,126 +1,126 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_iwdg.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the IWDG firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -/* CTLR register bit mask */ -#define CTLR_KEY_Reload ((uint16_t)0xAAAA) -#define CTLR_KEY_Enable ((uint16_t)0xCCCC) - -/********************************************************************* - * @fn IWDG_WriteAccessCmd - * - * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. - * - * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR - * and IWDG_RLDR registers. - * - * @return none - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - IWDG->CTLR = IWDG_WriteAccess; -} - -/********************************************************************* - * @fn IWDG_SetPrescaler - * - * @brief Sets IWDG Prescaler value. - * - * @param IWDG_Prescaler - specifies the IWDG Prescaler value. - * IWDG_Prescaler_4 - IWDG prescaler set to 4. - * IWDG_Prescaler_8 - IWDG prescaler set to 8. - * IWDG_Prescaler_16 - IWDG prescaler set to 16. - * IWDG_Prescaler_32 - IWDG prescaler set to 32. - * IWDG_Prescaler_64 - IWDG prescaler set to 64. - * IWDG_Prescaler_128 - IWDG prescaler set to 128. - * IWDG_Prescaler_256 - IWDG prescaler set to 256. - * - * @return none - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - IWDG->PSCR = IWDG_Prescaler; -} - -/********************************************************************* - * @fn IWDG_SetReload - * - * @brief Sets IWDG Reload value. - * - * @param Reload - specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * - * @return none - */ -void IWDG_SetReload(uint16_t Reload) -{ - IWDG->RLDR = Reload; -} - -/********************************************************************* - * @fn IWDG_ReloadCounter - * - * @brief Reloads IWDG counter with value defined in the reload register. - * - * @return none - */ -void IWDG_ReloadCounter(void) -{ - IWDG->CTLR = CTLR_KEY_Reload; -} - -/********************************************************************* - * @fn IWDG_Enable - * - * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). - * - * @return none - */ -void IWDG_Enable(void) -{ - IWDG->CTLR = CTLR_KEY_Enable; - while((RCC->RSTSCKR & 0x2) == RESET); -} - -/********************************************************************* - * @fn IWDG_GetFlagStatus - * - * @brief Checks whether the specified IWDG flag is set or not. - * - * @param IWDG_FLAG - specifies the flag to check. - * IWDG_FLAG_PVU - Prescaler Value Update on going. - * IWDG_FLAG_RVU - Reload Value Update on going. - * - * @return none - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_iwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file provides all the IWDG firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; + while((RCC->RSTSCKR & 0x2) == RESET); +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + + diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_misc.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_misc.c index e7ed670..eaaec50 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_misc.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_misc.c @@ -1,81 +1,81 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_misc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the miscellaneous firmware functions . - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -__IO uint32_t NVIC_Priority_Group = 0; - -/********************************************************************* - * @fn NVIC_PriorityGroupConfig - * - * @brief Configures the priority grouping - pre-emption priority and subpriority. - * - * @param NVIC_PriorityGroup - specifies the priority grouping bits length. - * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority - * 2 bits for subpriority - * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority - * 1 bits for subpriority - * - * @return none - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - NVIC_Priority_Group = NVIC_PriorityGroup; -} - -/********************************************************************* - * @fn NVIC_Init - * - * @brief Initializes the NVIC peripheral according to the specified parameters in - * the NVIC_InitStruct. - * - * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the - * configuration information for the specified NVIC peripheral. - * interrupt nesting enable(CSR-0x804 bit1 = 1) - * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. - * NVIC_IRQChannelSubPriority - range from 0 to 1. - * - * interrupt nesting disable(CSR-0x804 bit1 = 0) - * NVIC_IRQChannelPreemptionPriority - range is 0. - * NVIC_IRQChannelSubPriority - range from 0 to 3. - * - * @return none - */ -void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) -{ -#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) - if(NVIC_Priority_Group == NVIC_PriorityGroup_0) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6); - } -#else - if(NVIC_Priority_Group == NVIC_PriorityGroup_1) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6)); - } - else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6)); - } - } -#endif - - if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } - else - { - NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_misc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file provides all the miscellaneous firmware functions . + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 2 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 1 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 1. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6); + } +#else + if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6)); + } + else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6)); + } + } +#endif + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_opa.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_opa.c index 7cafdde..9630bef 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_opa.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_opa.c @@ -1,469 +1,469 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_opa.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the OPA firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - - -/* FLASH Keys */ -#define OPA_KEY1 ((uint32_t)0x45670123) -#define OPA_KEY2 ((uint32_t)0xCDEF89AB) - -/* TIM1 Brake Source mask definition */ -#define TIM1_Brake_Source_Config_MASK ((uint32_t)0xF3FFFFFF) - -/******************************************************************************** - * @fn OPA_Unlock - * - * @brief Unlocks the OPA Controller. - * - * @return None - */ -void OPA_Unlock(void) -{ - OPA->OPAKEY = OPA_KEY1; - OPA->OPAKEY = OPA_KEY2; -} - -/******************************************************************************** - * @fn OPA_Lock - * - * @brief Locks the OPA Controller. - * - * @return None - */ -void OPA_Lock(void) -{ - OPA->CTLR1 |= (1<<31); -} - -/******************************************************************************** - * @fn OPA_CMP_POLL_Lock - * - * @brief Locks the OPA and CMP POLL Controller. - * - * @return None - */ -void OPA_CMP_POLL_Lock(void) -{ - OPA->POLLKEY = OPA_KEY1; - OPA->POLLKEY = OPA_KEY2; -} - -/******************************************************************************** - * @fn OPA_CMP_Unlock - * - * @brief Unlocks the CMP Controller. - * - * @return None - */ -void OPA_CMP_Unlock(void) -{ - OPA->CMPKEY = OPA_KEY1; - OPA->CMPKEY = OPA_KEY2; -} - -/******************************************************************************** - * @fn OPA_CMP_Lock - * - * @brief Locks the CMP Controller. - * - * @return None - */ -void OPA_CMP_Lock(void) -{ - OPA->CTLR2 |= (1<<31); -} - -/********************************************************************* - * @fn OPA_Init - * - * @brief Initializes the OPA peripheral according to the specified - * parameters in the OPA_InitStruct. - * - * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure - * - * @return none - */ -void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) -{ - uint32_t tmp0 = 0, tmp1 = 0; - - tmp0 = OPA->CFGR1; - tmp1 = OPA->CTLR1; - - tmp0 &= 0xF1C0FA02; - tmp1 &= 0xFFE0E0C9; - - tmp0 |= (OPA_InitStruct->PSEL_POLL) | (OPA_InitStruct->POLL_NUM << 2) - | (OPA_InitStruct->RST_EN << 4) | (OPA_InitStruct->SETUP_CFG <<5) - | (OPA_InitStruct->POLL_AT <<7) | (OPA_InitStruct->OUT_IE << 8) - | (OPA_InitStruct->NMI_IE << 10) | (OPA_InitStruct->POLL_CH1 << 16) - | (OPA_InitStruct->POLL_CH2 << 18) | (OPA_InitStruct->POLL_CH3 << 20) - | (OPA_InitStruct->POLL_SEL << 25); - tmp1 |= (OPA_InitStruct->Mode << 1) | (OPA_InitStruct->PSEL << 4) - | (OPA_InitStruct->NSEL << 8) | (OPA_InitStruct->FB << 11) - | (OPA_InitStruct->PGADIF << 12) | (OPA_InitStruct->PGA_VBEN << 16) - | (OPA_InitStruct->PGA_VBSEL << 17) |(OPA_InitStruct->VBCMPSEL << 18) - | (OPA_InitStruct->OPA_HS << 20); - - OPA->CFGR1 = tmp0; - OPA->CTLR1 = tmp1; -} - -/********************************************************************* - * @fn OPA_StructInit - * - * @brief Fills each OPA_StructInit member with its reset value. - * - * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure - * - * @return none - */ -void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) -{ - OPA_InitStruct->PSEL_POLL = CHP_OPA_POLL_OFF; - OPA_InitStruct->POLL_NUM = CHP_POLL_NUM_1; - OPA_InitStruct->RST_EN = RST_OPA_OFF; - OPA_InitStruct->SETUP_CFG = OPA_SETUP_CFG_0; - OPA_InitStruct->POLL_AT = OPA_POLL_AUTO_OFF; - OPA_InitStruct->OUT_IE = OUT_IE_OFF; - OPA_InitStruct->NMI_IE = NMI_IE_OFF; - OPA_InitStruct->POLL_CH1 = OPA_POLL_CH1_PA2; - OPA_InitStruct->POLL_CH2 = OPA_POLL_CH1_PA2; - OPA_InitStruct->POLL_CH3 = OPA_POLL_CH1_PA2; - OPA_InitStruct->POLL_SEL = OPA_POLL_SEL_SOFT; - OPA_InitStruct->Mode = OUT_IO_OUT0; - OPA_InitStruct->PSEL = OUT_CMP2_ONLY; - OPA_InitStruct->NSEL = CHN_OFF; - OPA_InitStruct->FB = FB_OFF; - OPA_InitStruct->PGADIF = PGADIF_OFF; - OPA_InitStruct->PGA_VBEN = PGA_VBEN_OFF; - OPA_InitStruct->PGA_VBSEL = PGA_VBSEL_VDD_DIV2; - OPA_InitStruct->VBCMPSEL = VBCMPSEL_OFF; - OPA_InitStruct->OPA_HS = HS_OFF; -} - -/********************************************************************* - * @fn OPA_CMP1_Init - * - * @brief Initializes the CMP1 peripheral according to the specified - * parameters in the CMP1_InitTypeDef. - * - * @param CMP1_InitStruct - pointer to a CMP1_InitTypeDef structure - * - * @return none - */ -void OPA_CMP1_Init(CMP1_InitTypeDef *CMP_InitStruct) -{ - uint32_t tmp0 = 0; - uint32_t tmp1 = 0; - - tmp0 = OPA->CFGR2; - tmp1 = OPA->CTLR2; - - tmp0 &= 0x8000FCF2; - tmp1 &= 0xFFFFFE01; - - tmp0 |= (CMP_InitStruct->PSEL_POLL) | (CMP_InitStruct->POLL_NUM << 2) - | (CMP_InitStruct->OUT_IE << 8) | (CMP_InitStruct->CNT_IE << 9) - | (CMP_InitStruct->CMP_POLL_Interval << 16) | (CMP_InitStruct->POLL_CH1 << 25) - | (CMP_InitStruct->POLL_CH2 << 27) | (CMP_InitStruct->POLL_CH3 << 29); - - tmp1 |= (CMP_InitStruct->CMP_Out_Mode << 1) | (CMP_InitStruct->NSEL << 3) - | (CMP_InitStruct->PSEL <<5) | (CMP_InitStruct->HYEN <<7) - |(CMP_InitStruct->RMID << 8); - - OPA->CFGR2 = tmp0; - OPA->CTLR2 = tmp1; -} - -/********************************************************************* - * @fn OPA_CMP1_StructInit - * - * @brief Fills each OPA_CMP1_StructInit member with its reset value. - * - * @param CMP1_StructInit - pointer to a OPA_CMP1_StructInit structure - * - * @return none - */ -void OPA_CMP1_StructInit(CMP1_InitTypeDef *CMP_InitStruct) -{ - CMP_InitStruct->CMP_POLL_Interval = 0; - CMP_InitStruct->PSEL_POLL = CHP_CMP1_POLL_OFF; - CMP_InitStruct->POLL_NUM = CMP_POLL_NUM_1; - CMP_InitStruct->OUT_IE = CMP_OUT_IE_OFF; - CMP_InitStruct->CNT_IE = CMP_CNT_IE_OFF; - CMP_InitStruct->POLL_CH1 = CMP_POLL_CH1_PC5; - CMP_InitStruct->POLL_CH2 = CMP_POLL_CH2_PC5; - CMP_InitStruct->POLL_CH3 = CMP_POLL_CH3_PC5; - CMP_InitStruct->CMP_Out_Mode = OUT_IO0; - CMP_InitStruct->NSEL = CMP_CHN0; - CMP_InitStruct->PSEL = CMP_CHP0; - CMP_InitStruct->HYEN = CMP_HYEN_OFF; - CMP_InitStruct->RMID = CMP_RMID_OFF; -} - -/********************************************************************* - * @fn OPA_Cmd - * - * @brief Enables or disables the specified OPA peripheral. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void OPA_Cmd(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - OPA->CTLR1 |= (uint32_t)(1 << 0); - } - else - { - OPA->CTLR1 &= ~(uint32_t)(1 << 0); - } -} - -/********************************************************************* - * @fn OPA_CMP_Cmd - * - * @brief Enables or disables the specified CMP peripheral. - * - * @param CMP_NUM - Select CMP - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - OPA->CTLR2 |= (uint32_t)(1 << (CMP_NUM <<4)); - } - else - { - OPA->CTLR2 &= ~(uint32_t)(1 << (CMP_NUM <<4)); - } -} - -/********************************************************************* - * @fn OPA_SystemReset_Cmd - * - * @brief Enables or disables system reset the specified OPA peripheral. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void OPA_SystemReset_Cmd(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - OPA->CFGR1 |= (uint32_t)(1 << 4); - } - else - { - OPA->CFGR1 &= ~(uint32_t)(1 << 4); - } -} - -/********************************************************************* - * @fn OPA_CMP_SystemReset_Cmd - * - * @brief Enables or disables system reset the specified CMP peripheral. - * - * @param CMP_NUM - Select CMP - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void OPA_CMP_SystemReset_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - OPA->CFGR2 |= (uint32_t)(1 << (CMP_NUM + 4)); - } - else - { - OPA->CFGR2 &= ~(uint32_t)(1 << (CMP_NUM + 4)); - } -} - -/********************************************************************* - * @fn OPA_CMP_FILT_Cmd - * - * @brief Enables or disables digital filtering the specified CMP peripheral. - * - * @param CMP_NUM - Select CMP - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void OPA_CMP_FILT_Cmd(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - OPA->CTLR2 |= (uint32_t)(1 << 24); - } - else - { - OPA->CTLR2 &= ~(uint32_t)(1 << 24); - } -} - -/********************************************************************* - * @fn OPA_CMP_FILT_LEN_Config - * - * @brief Configures the length of digital filtering for the CMP. - * - * @param FILT_Len - The length of digital filtering. - * CMP_FILT_Len_0 - digital filtering(0.33us). - * CMP_FILT_Len_1 - digital filtering(0.5us). - * - * @return none - */ -void OPA_CMP_FILT_LEN_Config(uint32_t FILT_Len) -{ - OPA->CTLR2 &= ~CMP_FILT_Len_1; - OPA->CTLR2 |= FILT_Len; -} - -/********************************************************************* - * @fn OPA_CMP_TIM1_BKINConfig - * - * @brief Specifies the TIM1 Brake source. - * - * @param Brake_Source - specifies the brake source to clear. - * TIM1_Brake_Source_IO - choose GPIO to be the TIM1 brake source - * TIM1_Brake_Source_CMP1 - choose CMP1 to be the TIM1 brake source - * TIM1_Brake_Source_CMP2 - choose CMP2 to be the TIM1 brake source - * TIM1_Brake_Source_OPA - choose OPA to be the TIM1 brake source - * - * @return none - */ -void OPA_CMP_TIM1_BKINConfig(uint32_t Brake_Source) -{ - OPA->CTLR2 &= TIM1_Brake_Source_Config_MASK; - OPA->CTLR2 |= Brake_Source; -} - -/********************************************************************* - * @fn OPA_GetFlagStatus - * - * @brief Checks whether the OPA flag is set or not. - * - * @param OPA_FLAG - specifies the OPA flag to check. - * OPA_FLAG_OUT_POLL_CH_1 - the poll channel 1 of OPA - * OPA_FLAG_OUT_POLL_CH_2 - the poll channel 2 of OPA - * OPA_FLAG_OUT_POLL_CH_3 - the poll channel 3 of OPA - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus OPA_GetFlagStatus(uint32_t OPA_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((OPA->CFGR1 & OPA_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn OPA_CMP_GetFlagStatus - * - * @brief Checks whether the CMP flag is set or not. - * - * @param CMP_FLAG - specifies the CMP flag to check. - * CMP_FLAG_OUT_POLL_CH_1 - the poll channel 1 of CMP - * CMP_FLAG_OUT_POLL_CH_2 - the poll channel 2 of CMP - * CMP_FLAG_OUT_POLL_CH_3 - the poll channel 3 of CMP - * CMP_FLAG_POLL_END - poll channel end of CMP - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus OPA_CMP_GetFlagStatus(uint32_t CMP_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((OPA->CFGR2 & CMP_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn OPA_ClearFlag - * - * @brief Clears the OPA flag. - * - * @param OPA_FLAG - specifies the OPA flag to clear. - * OPA_FLAG_OUT_POLL_CH_1 - the poll channel 1 of OPA - * OPA_FLAG_OUT_POLL_CH_2 - the poll channel 2 of OPA - * OPA_FLAG_OUT_POLL_CH_3 - the poll channel 3 of OPA - * - * @return none - */ -void OPA_ClearFlag(uint32_t OPA_FLAG) -{ - OPA->CFGR1 &= (uint32_t)~OPA_FLAG; -} - -/********************************************************************* - * @fn OPA_CMP_ClearFlag - * - * @brief Clears the CMP flag. - * - * @param CMP_FLAG - specifies the CMP flag to clear. - * CMP_FLAG_OUT_POLL_CH_1 - the poll channel 1 of CMP - * CMP_FLAG_OUT_POLL_CH_2 - the poll channel 2 of CMP - * CMP_FLAG_OUT_POLL_CH_3 - the poll channel 3 of CMP - * CMP_FLAG_POLL_END - poll channel end of CMP - * - * @return none - */ -void OPA_CMP_ClearFlag(uint32_t CMP_FLAG) -{ - OPA->CFGR2 &= (uint32_t)~CMP_FLAG; -} - -/********************************************************************* - * @fn OPA_SoftwareStartPollCmd - * - * @brief Enables or disables the selected OPA software start POLL. - * - * @param NewState - ENABLE or DISABLE. - * - * @return None - */ -void OPA_SoftwareStartPollCmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - OPA->CFGR1 |= (1<<24); - } - else - { - OPA->CFGR1 &= ~(1<<24); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_opa.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file provides all the OPA firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + + +/* FLASH Keys */ +#define OPA_KEY1 ((uint32_t)0x45670123) +#define OPA_KEY2 ((uint32_t)0xCDEF89AB) + +/* TIM1 Brake Source mask definition */ +#define TIM1_Brake_Source_Config_MASK ((uint32_t)0xF3FFFFFF) + +/******************************************************************************** + * @fn OPA_Unlock + * + * @brief Unlocks the OPA Controller. + * + * @return None + */ +void OPA_Unlock(void) +{ + OPA->OPAKEY = OPA_KEY1; + OPA->OPAKEY = OPA_KEY2; +} + +/******************************************************************************** + * @fn OPA_Lock + * + * @brief Locks the OPA Controller. + * + * @return None + */ +void OPA_Lock(void) +{ + OPA->CTLR1 |= (1<<31); +} + +/******************************************************************************** + * @fn OPA_CMP_POLL_Lock + * + * @brief Locks the OPA and CMP POLL Controller. + * + * @return None + */ +void OPA_CMP_POLL_Lock(void) +{ + OPA->POLLKEY = OPA_KEY1; + OPA->POLLKEY = OPA_KEY2; +} + +/******************************************************************************** + * @fn OPA_CMP_Unlock + * + * @brief Unlocks the CMP Controller. + * + * @return None + */ +void OPA_CMP_Unlock(void) +{ + OPA->CMPKEY = OPA_KEY1; + OPA->CMPKEY = OPA_KEY2; +} + +/******************************************************************************** + * @fn OPA_CMP_Lock + * + * @brief Locks the CMP Controller. + * + * @return None + */ +void OPA_CMP_Lock(void) +{ + OPA->CTLR2 |= (1<<31); +} + +/********************************************************************* + * @fn OPA_Init + * + * @brief Initializes the OPA peripheral according to the specified + * parameters in the OPA_InitStruct. + * + * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) +{ + uint32_t tmp0 = 0, tmp1 = 0; + + tmp0 = OPA->CFGR1; + tmp1 = OPA->CTLR1; + + tmp0 &= 0xF1C0FA02; + tmp1 &= 0xFFE0E0C9; + + tmp0 |= (OPA_InitStruct->PSEL_POLL) | (OPA_InitStruct->POLL_NUM << 2) + | (OPA_InitStruct->RST_EN << 4) | (OPA_InitStruct->SETUP_CFG <<5) + | (OPA_InitStruct->POLL_AT <<7) | (OPA_InitStruct->OUT_IE << 8) + | (OPA_InitStruct->NMI_IE << 10) | (OPA_InitStruct->POLL_CH1 << 16) + | (OPA_InitStruct->POLL_CH2 << 18) | (OPA_InitStruct->POLL_CH3 << 20) + | (OPA_InitStruct->POLL_SEL << 25); + tmp1 |= (OPA_InitStruct->Mode << 1) | (OPA_InitStruct->PSEL << 4) + | (OPA_InitStruct->NSEL << 8) | (OPA_InitStruct->FB << 11) + | (OPA_InitStruct->PGADIF << 12) | (OPA_InitStruct->PGA_VBEN << 16) + | (OPA_InitStruct->PGA_VBSEL << 17) |(OPA_InitStruct->VBCMPSEL << 18) + | (OPA_InitStruct->OPA_HS << 20); + + OPA->CFGR1 = tmp0; + OPA->CTLR1 = tmp1; +} + +/********************************************************************* + * @fn OPA_StructInit + * + * @brief Fills each OPA_StructInit member with its reset value. + * + * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) +{ + OPA_InitStruct->PSEL_POLL = CHP_OPA_POLL_OFF; + OPA_InitStruct->POLL_NUM = CHP_POLL_NUM_1; + OPA_InitStruct->RST_EN = RST_OPA_OFF; + OPA_InitStruct->SETUP_CFG = OPA_SETUP_CFG_0; + OPA_InitStruct->POLL_AT = OPA_POLL_AUTO_OFF; + OPA_InitStruct->OUT_IE = OUT_IE_OFF; + OPA_InitStruct->NMI_IE = NMI_IE_OFF; + OPA_InitStruct->POLL_CH1 = OPA_POLL_CH1_PA2; + OPA_InitStruct->POLL_CH2 = OPA_POLL_CH1_PA2; + OPA_InitStruct->POLL_CH3 = OPA_POLL_CH1_PA2; + OPA_InitStruct->POLL_SEL = OPA_POLL_SEL_SOFT; + OPA_InitStruct->Mode = OUT_IO_OUT0; + OPA_InitStruct->PSEL = OUT_CMP2_ONLY; + OPA_InitStruct->NSEL = CHN_OFF; + OPA_InitStruct->FB = FB_OFF; + OPA_InitStruct->PGADIF = PGADIF_OFF; + OPA_InitStruct->PGA_VBEN = PGA_VBEN_OFF; + OPA_InitStruct->PGA_VBSEL = PGA_VBSEL_VDD_DIV2; + OPA_InitStruct->VBCMPSEL = VBCMPSEL_OFF; + OPA_InitStruct->OPA_HS = HS_OFF; +} + +/********************************************************************* + * @fn OPA_CMP1_Init + * + * @brief Initializes the CMP1 peripheral according to the specified + * parameters in the CMP1_InitTypeDef. + * + * @param CMP1_InitStruct - pointer to a CMP1_InitTypeDef structure + * + * @return none + */ +void OPA_CMP1_Init(CMP1_InitTypeDef *CMP_InitStruct) +{ + uint32_t tmp0 = 0; + uint32_t tmp1 = 0; + + tmp0 = OPA->CFGR2; + tmp1 = OPA->CTLR2; + + tmp0 &= 0x8000FCF2; + tmp1 &= 0xFFFFFE01; + + tmp0 |= (CMP_InitStruct->PSEL_POLL) | (CMP_InitStruct->POLL_NUM << 2) + | (CMP_InitStruct->OUT_IE << 8) | (CMP_InitStruct->CNT_IE << 9) + | (CMP_InitStruct->CMP_POLL_Interval << 16) | (CMP_InitStruct->POLL_CH1 << 25) + | (CMP_InitStruct->POLL_CH2 << 27) | (CMP_InitStruct->POLL_CH3 << 29); + + tmp1 |= (CMP_InitStruct->CMP_Out_Mode << 1) | (CMP_InitStruct->NSEL << 3) + | (CMP_InitStruct->PSEL <<5) | (CMP_InitStruct->HYEN <<7) + |(CMP_InitStruct->RMID << 8); + + OPA->CFGR2 = tmp0; + OPA->CTLR2 = tmp1; +} + +/********************************************************************* + * @fn OPA_CMP1_StructInit + * + * @brief Fills each OPA_CMP1_StructInit member with its reset value. + * + * @param CMP1_StructInit - pointer to a OPA_CMP1_StructInit structure + * + * @return none + */ +void OPA_CMP1_StructInit(CMP1_InitTypeDef *CMP_InitStruct) +{ + CMP_InitStruct->CMP_POLL_Interval = 0; + CMP_InitStruct->PSEL_POLL = CHP_CMP1_POLL_OFF; + CMP_InitStruct->POLL_NUM = CMP_POLL_NUM_1; + CMP_InitStruct->OUT_IE = CMP_OUT_IE_OFF; + CMP_InitStruct->CNT_IE = CMP_CNT_IE_OFF; + CMP_InitStruct->POLL_CH1 = CMP_POLL_CH1_PC5; + CMP_InitStruct->POLL_CH2 = CMP_POLL_CH2_PC5; + CMP_InitStruct->POLL_CH3 = CMP_POLL_CH3_PC5; + CMP_InitStruct->CMP_Out_Mode = OUT_IO0; + CMP_InitStruct->NSEL = CMP_CHN0; + CMP_InitStruct->PSEL = CMP_CHP0; + CMP_InitStruct->HYEN = CMP_HYEN_OFF; + CMP_InitStruct->RMID = CMP_RMID_OFF; +} + +/********************************************************************* + * @fn OPA_Cmd + * + * @brief Enables or disables the specified OPA peripheral. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_Cmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CTLR1 |= (uint32_t)(1 << 0); + } + else + { + OPA->CTLR1 &= ~(uint32_t)(1 << 0); + } +} + +/********************************************************************* + * @fn OPA_CMP_Cmd + * + * @brief Enables or disables the specified CMP peripheral. + * + * @param CMP_NUM - Select CMP + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CTLR2 |= (uint32_t)(1 << (CMP_NUM <<4)); + } + else + { + OPA->CTLR2 &= ~(uint32_t)(1 << (CMP_NUM <<4)); + } +} + +/********************************************************************* + * @fn OPA_SystemReset_Cmd + * + * @brief Enables or disables system reset the specified OPA peripheral. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_SystemReset_Cmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CFGR1 |= (uint32_t)(1 << 4); + } + else + { + OPA->CFGR1 &= ~(uint32_t)(1 << 4); + } +} + +/********************************************************************* + * @fn OPA_CMP_SystemReset_Cmd + * + * @brief Enables or disables system reset the specified CMP peripheral. + * + * @param CMP_NUM - Select CMP + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_CMP_SystemReset_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CFGR2 |= (uint32_t)(1 << (CMP_NUM + 4)); + } + else + { + OPA->CFGR2 &= ~(uint32_t)(1 << (CMP_NUM + 4)); + } +} + +/********************************************************************* + * @fn OPA_CMP_FILT_Cmd + * + * @brief Enables or disables digital filtering the specified CMP peripheral. + * + * @param CMP_NUM - Select CMP + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_CMP_FILT_Cmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CTLR2 |= (uint32_t)(1 << 24); + } + else + { + OPA->CTLR2 &= ~(uint32_t)(1 << 24); + } +} + +/********************************************************************* + * @fn OPA_CMP_FILT_LEN_Config + * + * @brief Configures the length of digital filtering for the CMP. + * + * @param FILT_Len - The length of digital filtering. + * CMP_FILT_Len_0 - digital filtering(0.33us). + * CMP_FILT_Len_1 - digital filtering(0.5us). + * + * @return none + */ +void OPA_CMP_FILT_LEN_Config(uint32_t FILT_Len) +{ + OPA->CTLR2 &= ~CMP_FILT_Len_1; + OPA->CTLR2 |= FILT_Len; +} + +/********************************************************************* + * @fn OPA_CMP_TIM1_BKINConfig + * + * @brief Specifies the TIM1 Brake source. + * + * @param Brake_Source - specifies the brake source to clear. + * TIM1_Brake_Source_IO - choose GPIO to be the TIM1 brake source + * TIM1_Brake_Source_CMP1 - choose CMP1 to be the TIM1 brake source + * TIM1_Brake_Source_CMP2 - choose CMP2 to be the TIM1 brake source + * TIM1_Brake_Source_OPA - choose OPA to be the TIM1 brake source + * + * @return none + */ +void OPA_CMP_TIM1_BKINConfig(uint32_t Brake_Source) +{ + OPA->CTLR2 &= TIM1_Brake_Source_Config_MASK; + OPA->CTLR2 |= Brake_Source; +} + +/********************************************************************* + * @fn OPA_GetFlagStatus + * + * @brief Checks whether the OPA flag is set or not. + * + * @param OPA_FLAG - specifies the OPA flag to check. + * OPA_FLAG_OUT_POLL_CH_1 - the poll channel 1 of OPA + * OPA_FLAG_OUT_POLL_CH_2 - the poll channel 2 of OPA + * OPA_FLAG_OUT_POLL_CH_3 - the poll channel 3 of OPA + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus OPA_GetFlagStatus(uint32_t OPA_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((OPA->CFGR1 & OPA_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn OPA_CMP_GetFlagStatus + * + * @brief Checks whether the CMP flag is set or not. + * + * @param CMP_FLAG - specifies the CMP flag to check. + * CMP_FLAG_OUT_POLL_CH_1 - the poll channel 1 of CMP + * CMP_FLAG_OUT_POLL_CH_2 - the poll channel 2 of CMP + * CMP_FLAG_OUT_POLL_CH_3 - the poll channel 3 of CMP + * CMP_FLAG_POLL_END - poll channel end of CMP + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus OPA_CMP_GetFlagStatus(uint32_t CMP_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((OPA->CFGR2 & CMP_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn OPA_ClearFlag + * + * @brief Clears the OPA flag. + * + * @param OPA_FLAG - specifies the OPA flag to clear. + * OPA_FLAG_OUT_POLL_CH_1 - the poll channel 1 of OPA + * OPA_FLAG_OUT_POLL_CH_2 - the poll channel 2 of OPA + * OPA_FLAG_OUT_POLL_CH_3 - the poll channel 3 of OPA + * + * @return none + */ +void OPA_ClearFlag(uint32_t OPA_FLAG) +{ + OPA->CFGR1 &= (uint32_t)~OPA_FLAG; +} + +/********************************************************************* + * @fn OPA_CMP_ClearFlag + * + * @brief Clears the CMP flag. + * + * @param CMP_FLAG - specifies the CMP flag to clear. + * CMP_FLAG_OUT_POLL_CH_1 - the poll channel 1 of CMP + * CMP_FLAG_OUT_POLL_CH_2 - the poll channel 2 of CMP + * CMP_FLAG_OUT_POLL_CH_3 - the poll channel 3 of CMP + * CMP_FLAG_POLL_END - poll channel end of CMP + * + * @return none + */ +void OPA_CMP_ClearFlag(uint32_t CMP_FLAG) +{ + OPA->CFGR2 &= (uint32_t)~CMP_FLAG; +} + +/********************************************************************* + * @fn OPA_SoftwareStartPollCmd + * + * @brief Enables or disables the selected OPA software start POLL. + * + * @param NewState - ENABLE or DISABLE. + * + * @return None + */ +void OPA_SoftwareStartPollCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + OPA->CFGR1 |= (1<<24); + } + else + { + OPA->CFGR1 &= ~(1<<24); + } +} diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_pwr.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_pwr.c index 73c89cc..f70e457 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_pwr.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_pwr.c @@ -1,227 +1,227 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_pwr.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the PWR firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* PWR registers bit mask */ -/* CTLR register bit mask */ -#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) -#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) -#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) -#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) - -/********************************************************************* - * @fn PWR_DeInit - * - * @brief Deinitializes the PWR peripheral registers to their default - * reset values. - * - * @return none - */ -void PWR_DeInit(void) -{ - RCC_PB1PeriphResetCmd(RCC_PB1Periph_PWR, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_PWR, DISABLE); -} - -/********************************************************************* - * @fn PWR_PVDCmd - * - * @brief Enables or disables the Power Voltage Detector(PVD). - * - * @param NewState - new state of the PVD(ENABLE or DISABLE). - * - * @return none - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (1 << 4); - } - else - { - PWR->CTLR &= ~(1 << 4); - } -} - -/********************************************************************* - * @fn PWR_PVDLevelConfig - * - * @brief Configures the voltage threshold detected by the Power Voltage - * Detector(PVD). - * - * @param PWR_PVDLevel - specifies the PVD detection level - * PWR_PVDLevel_0 - PVD detection level set to mode 0. - * PWR_PVDLevel_1 - PVD detection level set to mode 1. - * PWR_PVDLevel_2 - PVD detection level set to mode 2. - * PWR_PVDLevel_3 - PVD detection level set to mode 3. - * - * @return none - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_PLS_MASK; - tmpreg |= PWR_PVDLevel; - PWR->CTLR = tmpreg; -} - -/********************************************************************* - * @fn PWR_AutoWakeUpCmd - * - * @brief Enables or disables the Auto WakeUp functionality. - * - * @param NewState - new state of the Auto WakeUp functionality - * (ENABLE or DISABLE). - * - * @return none - */ -void PWR_AutoWakeUpCmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->AWUCSR |= (1 << 1); - } - else - { - PWR->AWUCSR &= ~(1 << 1); - } -} - -/********************************************************************* - * @fn PWR_AWU_SetPrescaler - * - * @brief Sets the Auto Wake up Prescaler - * - * @param AWU_Prescaler - specifies the Auto Wake up Prescaler - * PWR_AWU_Prescaler_1 - AWU counter clock = LSI/1 - * PWR_AWU_Prescaler_2 - AWU counter clock = LSI/2 - * PWR_AWU_Prescaler_4 - AWU counter clock = LSI/4 - * PWR_AWU_Prescaler_8 - AWU counter clock = LSI/8 - * PWR_AWU_Prescaler_16 - AWU counter clock = LSI/16 - * PWR_AWU_Prescaler_32 - AWU counter clock = LSI/32 - * PWR_AWU_Prescaler_64 - AWU counter clock = LSI/64 - * PWR_AWU_Prescaler_128 - AWU counter clock = LSI/128 - * PWR_AWU_Prescaler_256 - AWU counter clock = LSI/256 - * PWR_AWU_Prescaler_512 - AWU counter clock = LSI/512 - * PWR_AWU_Prescaler_1024 - AWU counter clock = LSI/1024 - * PWR_AWU_Prescaler_2048 - AWU counter clock = LSI/2048 - * PWR_AWU_Prescaler_4096 - AWU counter clock = LSI/4096 - * PWR_AWU_Prescaler_10240 - AWU counter clock = LSI/10240 - * PWR_AWU_Prescaler_61440 - AWU counter clock = LSI/61440 - * - * @return none - */ -void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->AWUPSC & AWUPSC_MASK; - tmpreg |= AWU_Prescaler; - PWR->AWUPSC = tmpreg; -} - -/********************************************************************* - * @fn PWR_AWU_SetWindowValue - * - * @brief Sets the WWDG window value - * - * @param WindowValue - specifies the window value to be compared to the - * downcounter,which must be lower than 0x3F - * - * @return none - */ -void PWR_AWU_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - tmpreg = PWR->AWUWR & AWUWR_MASK; - tmpreg |= WindowValue; - PWR->AWUWR = tmpreg; -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode - * - * @brief Enters STANDBY mode. - * - * @param PWR_STANDBYEntry - specifies if STANDBY mode in entered with WFI or WFE instruction. - * PWR_STANDBYEntry_WFI - enter STANDBY mode with WFI instruction - * PWR_STANDBYEntry_WFE - enter STANDBY mode with WFE instruction - * - * @return none - */ -void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry) -{ - PWR->CTLR &= CTLR_DS_MASK; - PWR->CTLR |= PWR_CTLR_PDDS; - - NVIC->SCTLR |= (1 << 2); - - if(PWR_STANDBYEntry == PWR_STANDBYEntry_WFI) - { - __WFI(); - } - else - { - __WFE(); - } - - NVIC->SCTLR &= ~(1 << 2); -} - -/********************************************************************* - * @fn PWR_GetFlagStatus - * - * @brief Checks whether the specified PWR flag is set or not. - * - * @param PWR_FLAG - specifies the flag to check. - * PWR_FLAG_PVDO - PVD Output - * - * @return The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn PWR_FLASH_LP_Cmd - * - * @brief Enables or disables the FLASH enter low power mode 0. - * - * @param NewState - new state of the FLASH enter low power mode 0. - * (ENABLE or DISABLE). - * - * @return none - */ -void PWR_FLASH_LP_Cmd(FunctionalState NewState) -{ - if(NewState) - { - PWR->CTLR |= (7 << 9); - } - else - { - PWR->CTLR &= ~(1 << 9); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_pwr.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file provides all the PWR firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) +#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) +#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_PB1PeriphResetCmd(RCC_PB1Periph_PWR, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_PVDCmd + * + * @brief Enables or disables the Power Voltage Detector(PVD). + * + * @param NewState - new state of the PVD(ENABLE or DISABLE). + * + * @return none + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 4); + } + else + { + PWR->CTLR &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_0 - PVD detection level set to mode 0. + * PWR_PVDLevel_1 - PVD detection level set to mode 1. + * PWR_PVDLevel_2 - PVD detection level set to mode 2. + * PWR_PVDLevel_3 - PVD detection level set to mode 3. + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_AutoWakeUpCmd + * + * @brief Enables or disables the Auto WakeUp functionality. + * + * @param NewState - new state of the Auto WakeUp functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_AutoWakeUpCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->AWUCSR |= (1 << 1); + } + else + { + PWR->AWUCSR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn PWR_AWU_SetPrescaler + * + * @brief Sets the Auto Wake up Prescaler + * + * @param AWU_Prescaler - specifies the Auto Wake up Prescaler + * PWR_AWU_Prescaler_1 - AWU counter clock = LSI/1 + * PWR_AWU_Prescaler_2 - AWU counter clock = LSI/2 + * PWR_AWU_Prescaler_4 - AWU counter clock = LSI/4 + * PWR_AWU_Prescaler_8 - AWU counter clock = LSI/8 + * PWR_AWU_Prescaler_16 - AWU counter clock = LSI/16 + * PWR_AWU_Prescaler_32 - AWU counter clock = LSI/32 + * PWR_AWU_Prescaler_64 - AWU counter clock = LSI/64 + * PWR_AWU_Prescaler_128 - AWU counter clock = LSI/128 + * PWR_AWU_Prescaler_256 - AWU counter clock = LSI/256 + * PWR_AWU_Prescaler_512 - AWU counter clock = LSI/512 + * PWR_AWU_Prescaler_1024 - AWU counter clock = LSI/1024 + * PWR_AWU_Prescaler_2048 - AWU counter clock = LSI/2048 + * PWR_AWU_Prescaler_4096 - AWU counter clock = LSI/4096 + * PWR_AWU_Prescaler_10240 - AWU counter clock = LSI/10240 + * PWR_AWU_Prescaler_61440 - AWU counter clock = LSI/61440 + * + * @return none + */ +void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->AWUPSC & AWUPSC_MASK; + tmpreg |= AWU_Prescaler; + PWR->AWUPSC = tmpreg; +} + +/********************************************************************* + * @fn PWR_AWU_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x3F + * + * @return none + */ +void PWR_AWU_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + tmpreg = PWR->AWUWR & AWUWR_MASK; + tmpreg |= WindowValue; + PWR->AWUWR = tmpreg; +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @param PWR_STANDBYEntry - specifies if STANDBY mode in entered with WFI or WFE instruction. + * PWR_STANDBYEntry_WFI - enter STANDBY mode with WFI instruction + * PWR_STANDBYEntry_WFE - enter STANDBY mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry) +{ + PWR->CTLR &= CTLR_DS_MASK; + PWR->CTLR |= PWR_CTLR_PDDS; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STANDBYEntry == PWR_STANDBYEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_PVDO - PVD Output + * + * @return The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn PWR_FLASH_LP_Cmd + * + * @brief Enables or disables the FLASH enter low power mode 0. + * + * @param NewState - new state of the FLASH enter low power mode 0. + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_FLASH_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (7 << 9); + } + else + { + PWR->CTLR &= ~(1 << 9); + } +} diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_rcc.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_rcc.c index 33487ff..8c9c66b 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_rcc.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_rcc.c @@ -1,880 +1,880 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_rcc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the RCC firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include - -/* RCC registers bit mask */ - -/* CTLR register bit mask */ -#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) -#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CTLR_HSEON_Set ((uint32_t)0x00010000) -#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -#define CFGR0_PLL_Mask ((uint32_t)0xFFFEFFFF) -#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0x7FFF07FF) -#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800) - -/* RSTSCKR register bit mask */ -#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -/* INTR register byte 2 (Bits[15:8]) base address */ -#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* INTR register byte 3 (Bits[23:16]) base address */ -#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CFGR0 register byte 4 (Bits[31:24]) base address */ -#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) - -static __I uint8_t PBHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; -static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128}; - -/********************************************************************* - * @fn RCC_DeInit - * - * @brief Resets the RCC clock configuration to the default reset state. - * - * @return none - */ -void RCC_DeInit(void) -{ - uint32_t tmp = 0; - - /* Flash 2 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; - RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0x68FF0000; - - tmp = RCC->CTLR; - tmp &= (uint32_t)0xFE16FFFB; - tmp |= (uint32_t)(1<<22)|(1<<20); - RCC->CTLR = tmp; - - RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFFFEFFFF; - RCC->INTR = 0x009D0000; -} - -/********************************************************************* - * @fn RCC_HSEConfig - * - * @brief Configures the External High Speed oscillator (HSE). - * - * @param RCC_HSE - - * RCC_HSE_OFF - HSE oscillator OFF. - * RCC_HSE_ON - HSE oscillator ON. - * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. - * Note- - * HSE can not be stopped if it is used directly or through the PLL as system clock. - * - * @return none - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - RCC->CTLR &= CTLR_HSEON_Reset; - RCC->CTLR &= CTLR_HSEBYP_Reset; - - switch(RCC_HSE) - { - case RCC_HSE_ON: - RCC->CTLR |= CTLR_HSEON_Set; - break; - - case RCC_HSE_Bypass: - RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn RCC_WaitForHSEStartUp - * - * @brief Waits for HSE start-up. - * - * @return READY - HSE oscillator is stable and ready to use. - * NoREADY - HSE oscillator not yet ready. - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - - ErrorStatus status = NoREADY; - FlagStatus HSEStatus = RESET; - - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = READY; - } - else - { - status = NoREADY; - } - - return (status); -} - -/********************************************************************* - * @fn RCC_AdjustHSICalibrationValue - * - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * - * @param HSICalibrationValue - specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * - * @return none - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CTLR; - tmpreg &= CTLR_HSITRIM_Mask; - tmpreg |= (uint32_t)HSICalibrationValue << 3; - RCC->CTLR = tmpreg; -} - -/********************************************************************* - * @fn RCC_HSICmd - * - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_HSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 0); - } - else - { - RCC->CTLR &= ~(1 << 0); - } -} - -/********************************************************************* - * @fn RCC_PLLConfig - * - * @brief Configures the PLL clock source and multiplication factor. - * - * @param RCC_PLLSource - specifies the PLL entry clock source. - * RCC_PLLSource_HSI_MUL2 - HSI oscillator clock*2 - * selected as PLL clock entry. - * RCC_PLLSource_HSE_MUL2 - HSE oscillator clock*2 - * selected as PLL clock entry. - * - * @return none - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_PLL_Mask; - tmpreg |= RCC_PLLSource; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PLLCmd - * - * @brief Enables or disables the PLL. - * Note-The PLL can not be disabled if it is used as system clock. - * - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 24); - } - else - { - RCC->CTLR &= ~(1 << 24); - } -} - -/********************************************************************* - * @fn RCC_SYSCLKConfig - * - * @brief Configures the system clock (SYSCLK). - * - * @param RCC_SYSCLKSource - specifies the clock source used as system clock. - * RCC_SYSCLKSource_HSI - HSI selected as system clock. - * RCC_SYSCLKSource_HSE - HSE selected as system clock. - * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. - * - * @return none - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_SW_Mask; - tmpreg |= RCC_SYSCLKSource; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_GetSYSCLKSource - * - * @brief Returns the clock source used as system clock. - * - * @return 0x00 - HSI used as system clock. - * 0x04 - HSE used as system clock. - * 0x08 - PLL used as system clock. - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); -} - -/********************************************************************* - * @fn RCC_HCLKConfig - * - * @brief Configures the HB clock (HCLK). - * - * @param RCC_SYSCLK - defines the HB clock divider. This clock is derived from - * the system clock (SYSCLK). - * RCC_SYSCLK_Div1 - HB clock = SYSCLK. - * RCC_SYSCLK_Div2 - HB clock = SYSCLK/2. - * RCC_SYSCLK_Div3 - HB clock = SYSCLK/3. - * RCC_SYSCLK_Div4 - HB clock = SYSCLK/4. - * RCC_SYSCLK_Div5 - HB clock = SYSCLK/5. - * RCC_SYSCLK_Div6 - HB clock = SYSCLK/6. - * RCC_SYSCLK_Div7 - HB clock = SYSCLK/7. - * RCC_SYSCLK_Div8 - HB clock = SYSCLK/8. - * RCC_SYSCLK_Div16 - HB clock = SYSCLK/16. - * RCC_SYSCLK_Div32 - HB clock = SYSCLK/32. - * RCC_SYSCLK_Div64 - HB clock = SYSCLK/64. - * RCC_SYSCLK_Div128 - HB clock = SYSCLK/128. - * RCC_SYSCLK_Div256 - HB clock = SYSCLK/256. - * - * @return none - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_HPRE_Reset_Mask; - tmpreg |= RCC_SYSCLK; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_ITConfig - * - * @brief Enables or disables the specified RCC interrupts. - * - * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_SYSCLK_FAIL - System clock fail interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/********************************************************************* - * @fn RCC_ADCCLKConfig - * - * @brief Configures the ADC clock (ADCCLK). - * - * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from - * the PB2 clock (PCLK2). - * RCC_PCLK2_Div1 - ADC clock = PCLK2/1. - * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. - * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. - * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. - * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. - * RCC_PCLK2_Div12 - ADC clock = PCLK2/12. - * RCC_PCLK2_Div16 - ADC clock = PCLK2/16. - * RCC_PCLK2_Div24 - ADC clock = PCLK2/24. - * RCC_PCLK2_Div32 - ADC clock = PCLK2/32. - * RCC_PCLK2_Div48 - ADC clock = PCLK2/48. - * RCC_PCLK2_Div64 - ADC clock = PCLK2/64. - * RCC_PCLK2_Div96 - ADC clock = PCLK2/96. - * RCC_PCLK2_Div128 - ADC clock = PCLK2/128. - * - * @return none - */ -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_ADCPRE_Reset_Mask; - tmpreg |= RCC_PCLK2; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_LSICmd - * - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * Note- - * LSI can not be disabled if the IWDG is running. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_LSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->RSTSCKR |= (1 << 0); - } - else - { - RCC->RSTSCKR &= ~(1 << 0); - } -} - -/********************************************************************* - * @fn RCC_GetClocksFreq - * - * @brief The result of this function could be not correct when using - * fractional value for HSE crystal. - * - * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @return none - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks) -{ - uint32_t tmp = 0, pllsource = 0, presc = 0; - - tmp = RCC->CFGR0 & CFGR0_SWS_Mask; - - switch(tmp) - { - case 0x00: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - - case 0x04: - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - - case 0x08: - pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; - - if(pllsource == 0x00) - { - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE * 2; - } - else - { - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * 2; - } - break; - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - - tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = PBHBPrescTable[tmp]; - - if(((RCC->CFGR0 & CFGR0_HPRE_Set_Mask) >> 4) < 8) - { - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency / presc; - } - else - { - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - } - - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency; - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency; - tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; - tmp = tmp >> 11; - tmp = ((tmp & 0x18) >> 3) | ((tmp & 0x7) << 2); - - if((tmp & 0x13) >= 4) - { - tmp -= 12; - } - else - { - tmp &= 0x03; - } - - if(RCC->CFGR0 & RCC_ADC_CLK_MODE) - { - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency; - } - else - { - presc = ADCPrescTable[tmp]; - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; - } -} - -/********************************************************************* - * @fn RCC_HBPeriphClockCmd - * - * @brief Enables or disables the HB peripheral clock. - * - * @param RCC_HBPeriph - specifies the HB peripheral to gates its clock. - * RCC_HBPeriph_DMA1. - * RCC_HBPeriph_SRAM. - * Note- - * SRAM clock can be disabled only during sleep mode. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void RCC_HBPeriphClockCmd(uint32_t RCC_HBPeriph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->HBPCENR |= RCC_HBPeriph; - } - else - { - RCC->HBPCENR &= ~RCC_HBPeriph; - } -} - -/********************************************************************* - * @fn RCC_PB2PeriphClockCmd - * - * @brief Enables or disables the High Speed PB (PB2) peripheral clock. - * - * @param RCC_PB2Periph - specifies the PB2 peripheral to gates its clock. - * RCC_PB2Periph_AFIO. - * RCC_PB2Periph_GPIOA. - * RCC_PB2Periph_GPIOB. - * RCC_PB2Periph_GPIOC. - * RCC_PB2Periph_GPIOD. - * RCC_PB2Periph_ADC1. - * RCC_PB2Periph_TIM1. - * RCC_PB2Periph_SPI1. - * RCC_PB2Periph_USART2. - * RCC_PB2Periph_USART1. - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_PB2PeriphClockCmd(uint32_t RCC_PB2Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->PB2PCENR |= RCC_PB2Periph; - } - else - { - RCC->PB2PCENR &= ~RCC_PB2Periph; - } -} - -/********************************************************************* - * @fn RCC_PB1PeriphClockCmd - * - * @brief Enables or disables the Low Speed PB (PB1) peripheral clock. - * - * @param RCC_PB1Periph - specifies the PB1 peripheral to gates its clock. - * RCC_PB1Periph_TIM2. - * RCC_PB1Periph_TIM3. - * RCC_PB1Periph_WWDG. - * RCC_PB1Periph_I2C1. - * RCC_PB1Periph_PWR. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_PB1PeriphClockCmd(uint32_t RCC_PB1Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->PB1PCENR |= RCC_PB1Periph; - } - else - { - RCC->PB1PCENR &= ~RCC_PB1Periph; - } -} - -/********************************************************************* - * @fn RCC_PB2PeriphResetCmd - * - * @brief Forces or releases High Speed PB (PB2) peripheral reset. - * - * @param RCC_PB2Periph - specifies the PB2 peripheral to reset. - * RCC_PB2Periph_AFIO. - * RCC_PB2Periph_GPIOA. - * RCC_PB2Periph_GPIOB. - * RCC_PB2Periph_GPIOC. - * RCC_PB2Periph_GPIOD. - * RCC_PB2Periph_ADC1. - * RCC_PB2Periph_TIM1. - * RCC_PB2Periph_SPI1. - * RCC_PB2Periph_USART2. - * RCC_PB2Periph_USART1. - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_PB2PeriphResetCmd(uint32_t RCC_PB2Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->PB2PRSTR |= RCC_PB2Periph; - } - else - { - RCC->PB2PRSTR &= ~RCC_PB2Periph; - } -} - -/********************************************************************* - * @fn RCC_PB1PeriphResetCmd - * - * @brief Forces or releases Low Speed PB (PB1) peripheral reset. - * - * @param RCC_PB1Periph - specifies the PB1 peripheral to reset. - * RCC_PB1Periph_TIM2. - * RCC_PB1Periph_TIM3. - * RCC_PB1Periph_WWDG. - * RCC_PB1Periph_I2C1. - * RCC_PB1Periph_PWR. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_PB1PeriphResetCmd(uint32_t RCC_PB1Periph, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - RCC->PB1PRSTR |= RCC_PB1Periph; - } - else - { - RCC->PB1PRSTR &= ~RCC_PB1Periph; - } -} - -/********************************************************************* - * @fn RCC_ClockSecuritySystemCmd - * - * @brief Enables or disables the Clock Security System. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1 << 19); - } - else - { - RCC->CTLR &= ~(1 << 19); - } -} - -/********************************************************************* - * @fn RCC_MCOConfig - * - * @brief Selects the clock source to output on MCO pin. - * - * @param RCC_MCO - specifies the clock source to output. - * RCC_MCO_NoClock - No clock selected. - * RCC_MCO_SYSCLK - System clock selected. - * RCC_MCO_HSI - HSI oscillator clock selected. - * RCC_MCO_HSE - HSE oscillator clock selected. - * RCC_MCO_PLLCLK - PLL clock selected. - * - * @return none - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO; -} - -/********************************************************************* - * @fn RCC_GetFlagStatus - * - * @brief Checks whether the specified RCC flag is set or not. - * - * @param RCC_FLAG - specifies the flag to check. - * RCC_FLAG_HSIRDY - HSI oscillator clock ready. - * RCC_FLAG_HSERDY - HSE oscillator clock ready. - * RCC_FLAG_PLLRDY - PLL clock ready. - * RCC_FLAG_LSIRDY - LSI oscillator clock ready. - * RCC_FLAG_SYSCFAL - System clock fail flag. - * RCC_FLAG_ADCRST - ADC reset. - * RCC_FLAG_OPCMRST - OPA and CMP reset. - * RCC_FLAG_PINRST - Pin reset. - * RCC_FLAG_PORRST - POR/PDR reset. - * RCC_FLAG_SFTRST - Software reset. - * RCC_FLAG_IWDGRST - Independent Watchdog reset. - * RCC_FLAG_WWDGRST - Window Watchdog reset. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - - FlagStatus bitstatus = RESET; - tmp = RCC_FLAG >> 5; - - if(tmp == 1) - { - statusreg = RCC->CTLR; - } - else - { - statusreg = RCC->RSTSCKR; - } - - tmp = RCC_FLAG & FLAG_Mask; - - if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearFlag - * - * @brief Clears the RCC reset flags. - * Note- - * The reset flags are: RCC_FLAG_ADCRST, RCC_FLAG_OPCMRST, RCC_FLAG_PINRST, - * RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. - * - * @return none - */ -void RCC_ClearFlag(void) -{ - RCC->RSTSCKR |= RSTSCKR_RMVF_Set; -} - -/********************************************************************* - * @fn RCC_GetITStatus - * - * @brief Checks whether the specified RCC interrupt has occurred or not. - * - * @param RCC_IT - specifies the RCC interrupt source to check. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * RCC_IT_SYSCLK_FAIL - System clock fail interrupt. - * - * @return ITStatus - SET or RESET. - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - uint16_t tmp; - tmp = (uint16_t)RCC_IT; - - if(RCC_IT == RCC_IT_SYSCLK_FAIL) - { - tmp = (1<<8); - } - - if((RCC->INTR & tmp) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearITPendingBit - * - * @brief Clears the RCC's interrupt pending bits. - * - * @param RCC_IT - specifies the interrupt pending bit to clear. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * RCC_IT_SYSCLK_FAIL - System clock fail interrupt. - * - * @return none - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - if(RCC_IT == RCC_IT_SYSCLK_FAIL) - { - RCC->RSTSCKR &= ~RCC_SYSCLK_FAILIF; - return; - } - - *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT; -} - -/********************************************************************* - * @fn RCC_ClockMonitorCmd - * - * @brief Enables or disables the system clock monitor function. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ClockMonitorCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= RCC_SYSCM_EN; - } - else - { - RCC->CTLR &= ~RCC_SYSCM_EN; - } -} - -/********************************************************************* - * @fn RCC_HSE_LP_Cmd - * - * @brief Enables or disables low power mode of the External High Speed - * oscillator (HSE). - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_HSE_LP_Cmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= RCC_HSE_LP; - } - else - { - RCC->CTLR &= ~RCC_HSE_LP; - } -} - -/********************************************************************* - * @fn RCC_HSI_LP_Cmd - * - * @brief Enables or disables low power mode of the Internal High Speed - * oscillator (HSI) . - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_HSI_LP_Cmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= RCC_HSILP; - } - else - { - RCC->CTLR &= ~RCC_HSILP; - } -} - -/********************************************************************* - * @fn RCC_HSECurrentConfig - * - * @brief Configures the HSE Current level. - * - * @param RCC_HSECurrent - the HSE Current level. - * RCC_HSE_C_Level0 - HSE Current is level 0. - * RCC_HSE_C_Level1 - HSE Current is level 1. - * RCC_HSE_C_Level2 - HSE Current is level 2. - * RCC_HSE_C_Level3 - HSE Current is level 3. - * - * @return none - */ -void RCC_HSECurrentConfig(uint32_t RCC_HSECurrent) -{ - RCC->CTLR &= ~RCC_HSE_SI; - RCC->CTLR |= RCC_HSECurrent; -} - -/********************************************************************* - * @fn RCC_ADCCLKDutyCycleConfig - * - * @brief Configures the ADC clock high level duty cycle. - * - * @param RCC_DutyCycle - high level duty cycle. - * RCC_ADC_H_Level_Mode0 - ADC clock high-level duty cycle is mode 0. - * RCC_ADC_H_Level_Mode1 - ADC clock high-level duty cycle is mode 1. - * - * @return none - */ -void RCC_ADCCLKDutyCycleConfig(uint32_t RCC_DutyCycle) -{ - RCC->CFGR0 &= ~RCC_ADC_CLK_ADJ; - RCC->CFGR0 |= RCC_DutyCycle; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_rcc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/04 + * Description : This file provides all the RCC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFFEFFFF) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0x7FFF07FF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +static __I uint8_t PBHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; +static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * + * @return none + */ +void RCC_DeInit(void) +{ + uint32_t tmp = 0; + + /* Flash 2 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0x68FF0000; + + tmp = RCC->CTLR; + tmp &= (uint32_t)0xFED6FFFB; + tmp |= (uint32_t)(1<<20); + RCC->CTLR = tmp; + + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFFFEFFFF; + RCC->INTR = 0x009D0000; +} + +/********************************************************************* + * @fn RCC_HSEConfig + * + * @brief Configures the External High Speed oscillator (HSE). + * + * @param RCC_HSE - + * RCC_HSE_OFF - HSE oscillator OFF. + * RCC_HSE_ON - HSE oscillator ON. + * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * + * @return none + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + RCC->CTLR &= CTLR_HSEON_Reset; + RCC->CTLR &= CTLR_HSEBYP_Reset; + + switch(RCC_HSE) + { + case RCC_HSE_ON: + RCC->CTLR |= CTLR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_WaitForHSEStartUp + * + * @brief Waits for HSE start-up. + * + * @return READY - HSE oscillator is stable and ready to use. + * NoREADY - HSE oscillator not yet ready. + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + + ErrorStatus status = NoREADY; + FlagStatus HSEStatus = RESET; + + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = READY; + } + else + { + status = NoREADY; + } + + return (status); +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 0); + } + else + { + RCC->CTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_PLLConfig + * + * @brief Configures the PLL clock source and multiplication factor. + * + * @param RCC_PLLSource - specifies the PLL entry clock source. + * RCC_PLLSource_HSI_MUL2 - HSI oscillator clock*2 + * selected as PLL clock entry. + * RCC_PLLSource_HSE_MUL2 - HSE oscillator clock*2 + * selected as PLL clock entry. + * + * @return none + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PLL_Mask; + tmpreg |= RCC_PLLSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLLCmd + * + * @brief Enables or disables the PLL. + * Note-The PLL can not be disabled if it is used as system clock. + * + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 24); + } + else + { + RCC->CTLR &= ~(1 << 24); + } +} + +/********************************************************************* + * @fn RCC_SYSCLKConfig + * + * @brief Configures the system clock (SYSCLK). + * + * @param RCC_SYSCLKSource - specifies the clock source used as system clock. + * RCC_SYSCLKSource_HSI - HSI selected as system clock. + * RCC_SYSCLKSource_HSE - HSE selected as system clock. + * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. + * + * @return none + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_SW_Mask; + tmpreg |= RCC_SYSCLKSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetSYSCLKSource + * + * @brief Returns the clock source used as system clock. + * + * @return 0x00 - HSI used as system clock. + * 0x04 - HSE used as system clock. + * 0x08 - PLL used as system clock. + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the HB clock (HCLK). + * + * @param RCC_SYSCLK - defines the HB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - HB clock = SYSCLK. + * RCC_SYSCLK_Div2 - HB clock = SYSCLK/2. + * RCC_SYSCLK_Div3 - HB clock = SYSCLK/3. + * RCC_SYSCLK_Div4 - HB clock = SYSCLK/4. + * RCC_SYSCLK_Div5 - HB clock = SYSCLK/5. + * RCC_SYSCLK_Div6 - HB clock = SYSCLK/6. + * RCC_SYSCLK_Div7 - HB clock = SYSCLK/7. + * RCC_SYSCLK_Div8 - HB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - HB clock = SYSCLK/16. + * RCC_SYSCLK_Div32 - HB clock = SYSCLK/32. + * RCC_SYSCLK_Div64 - HB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - HB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - HB clock = SYSCLK/256. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_ITConfig + * + * @brief Enables or disables the specified RCC interrupts. + * + * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_SYSCLK_FAIL - System clock fail interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/********************************************************************* + * @fn RCC_ADCCLKConfig + * + * @brief Configures the ADC clock (ADCCLK). + * + * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from + * the PB2 clock (PCLK2). + * RCC_PCLK2_Div1 - ADC clock = PCLK2/1. + * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. + * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. + * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. + * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. + * RCC_PCLK2_Div12 - ADC clock = PCLK2/12. + * RCC_PCLK2_Div16 - ADC clock = PCLK2/16. + * RCC_PCLK2_Div24 - ADC clock = PCLK2/24. + * RCC_PCLK2_Div32 - ADC clock = PCLK2/32. + * RCC_PCLK2_Div48 - ADC clock = PCLK2/48. + * RCC_PCLK2_Div64 - ADC clock = PCLK2/64. + * RCC_PCLK2_Div96 - ADC clock = PCLK2/96. + * RCC_PCLK2_Div128 - ADC clock = PCLK2/128. + * + * @return none + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_ADCPRE_Reset_Mask; + tmpreg |= RCC_PCLK2; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_LSICmd + * + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * Note- + * LSI can not be disabled if the IWDG is running. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_LSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->RSTSCKR |= (1 << 0); + } + else + { + RCC->RSTSCKR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks) +{ + uint32_t tmp = 0, pllsource = 0, presc = 0; + + tmp = RCC->CFGR0 & CFGR0_SWS_Mask; + + switch(tmp) + { + case 0x00: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + + case 0x04: + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: + pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; + + if(pllsource == 0x00) + { + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE * 2; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * 2; + } + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = PBHBPrescTable[tmp]; + + if(((RCC->CFGR0 & CFGR0_HPRE_Set_Mask) >> 4) < 8) + { + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency / presc; + } + else + { + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + } + + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency; + tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; + tmp = tmp >> 11; + tmp = ((tmp & 0x18) >> 3) | ((tmp & 0x7) << 2); + + if((tmp & 0x13) >= 4) + { + tmp -= 12; + } + else + { + tmp &= 0x03; + } + + if(RCC->CFGR0 & RCC_ADC_CLK_MODE) + { + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency; + } + else + { + presc = ADCPrescTable[tmp]; + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; + } +} + +/********************************************************************* + * @fn RCC_HBPeriphClockCmd + * + * @brief Enables or disables the HB peripheral clock. + * + * @param RCC_HBPeriph - specifies the HB peripheral to gates its clock. + * RCC_HBPeriph_DMA1. + * RCC_HBPeriph_SRAM. + * Note- + * SRAM clock can be disabled only during sleep mode. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_HBPeriphClockCmd(uint32_t RCC_HBPeriph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->HBPCENR |= RCC_HBPeriph; + } + else + { + RCC->HBPCENR &= ~RCC_HBPeriph; + } +} + +/********************************************************************* + * @fn RCC_PB2PeriphClockCmd + * + * @brief Enables or disables the High Speed PB (PB2) peripheral clock. + * + * @param RCC_PB2Periph - specifies the PB2 peripheral to gates its clock. + * RCC_PB2Periph_AFIO. + * RCC_PB2Periph_GPIOA. + * RCC_PB2Periph_GPIOB. + * RCC_PB2Periph_GPIOC. + * RCC_PB2Periph_GPIOD. + * RCC_PB2Periph_ADC1. + * RCC_PB2Periph_TIM1. + * RCC_PB2Periph_SPI1. + * RCC_PB2Periph_USART2. + * RCC_PB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_PB2PeriphClockCmd(uint32_t RCC_PB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->PB2PCENR |= RCC_PB2Periph; + } + else + { + RCC->PB2PCENR &= ~RCC_PB2Periph; + } +} + +/********************************************************************* + * @fn RCC_PB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed PB (PB1) peripheral clock. + * + * @param RCC_PB1Periph - specifies the PB1 peripheral to gates its clock. + * RCC_PB1Periph_TIM2. + * RCC_PB1Periph_TIM3. + * RCC_PB1Periph_WWDG. + * RCC_PB1Periph_I2C1. + * RCC_PB1Periph_PWR. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PB1PeriphClockCmd(uint32_t RCC_PB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->PB1PCENR |= RCC_PB1Periph; + } + else + { + RCC->PB1PCENR &= ~RCC_PB1Periph; + } +} + +/********************************************************************* + * @fn RCC_PB2PeriphResetCmd + * + * @brief Forces or releases High Speed PB (PB2) peripheral reset. + * + * @param RCC_PB2Periph - specifies the PB2 peripheral to reset. + * RCC_PB2Periph_AFIO. + * RCC_PB2Periph_GPIOA. + * RCC_PB2Periph_GPIOB. + * RCC_PB2Periph_GPIOC. + * RCC_PB2Periph_GPIOD. + * RCC_PB2Periph_ADC1. + * RCC_PB2Periph_TIM1. + * RCC_PB2Periph_SPI1. + * RCC_PB2Periph_USART2. + * RCC_PB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_PB2PeriphResetCmd(uint32_t RCC_PB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->PB2PRSTR |= RCC_PB2Periph; + } + else + { + RCC->PB2PRSTR &= ~RCC_PB2Periph; + } +} + +/********************************************************************* + * @fn RCC_PB1PeriphResetCmd + * + * @brief Forces or releases Low Speed PB (PB1) peripheral reset. + * + * @param RCC_PB1Periph - specifies the PB1 peripheral to reset. + * RCC_PB1Periph_TIM2. + * RCC_PB1Periph_TIM3. + * RCC_PB1Periph_WWDG. + * RCC_PB1Periph_I2C1. + * RCC_PB1Periph_PWR. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PB1PeriphResetCmd(uint32_t RCC_PB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->PB1PRSTR |= RCC_PB1Periph; + } + else + { + RCC->PB1PRSTR &= ~RCC_PB1Periph; + } +} + +/********************************************************************* + * @fn RCC_ClockSecuritySystemCmd + * + * @brief Enables or disables the Clock Security System. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 19); + } + else + { + RCC->CTLR &= ~(1 << 19); + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * RCC_MCO_HSE - HSE oscillator clock selected. + * RCC_MCO_PLLCLK - PLL clock selected. + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_HSERDY - HSE oscillator clock ready. + * RCC_FLAG_PLLRDY - PLL clock ready. + * RCC_FLAG_LSIRDY - LSI oscillator clock ready. + * RCC_FLAG_SYSCFAL - System clock fail flag. + * RCC_FLAG_ADCRST - ADC reset. + * RCC_FLAG_OPCMRST - OPA and CMP reset. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if(tmp == 1) + { + statusreg = RCC->CTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * Note- + * The reset flags are: RCC_FLAG_ADCRST, RCC_FLAG_OPCMRST, RCC_FLAG_PINRST, + * RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. + * + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + +/********************************************************************* + * @fn RCC_GetITStatus + * + * @brief Checks whether the specified RCC interrupt has occurred or not. + * + * @param RCC_IT - specifies the RCC interrupt source to check. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * RCC_IT_SYSCLK_FAIL - System clock fail interrupt. + * + * @return ITStatus - SET or RESET. + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + uint16_t tmp; + tmp = (uint16_t)RCC_IT; + + if(RCC_IT == RCC_IT_SYSCLK_FAIL) + { + tmp = (1<<8); + } + + if((RCC->INTR & tmp) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearITPendingBit + * + * @brief Clears the RCC's interrupt pending bits. + * + * @param RCC_IT - specifies the interrupt pending bit to clear. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * RCC_IT_SYSCLK_FAIL - System clock fail interrupt. + * + * @return none + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + if(RCC_IT == RCC_IT_SYSCLK_FAIL) + { + RCC->RSTSCKR &= ~RCC_SYSCLK_FAILIF; + return; + } + + *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT; +} + +/********************************************************************* + * @fn RCC_ClockMonitorCmd + * + * @brief Enables or disables the system clock monitor function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ClockMonitorCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= RCC_SYSCM_EN; + } + else + { + RCC->CTLR &= ~RCC_SYSCM_EN; + } +} + +/********************************************************************* + * @fn RCC_HSE_LP_Cmd + * + * @brief Enables or disables low power mode of the External High Speed + * oscillator (HSE). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSE_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= RCC_HSE_LP; + } + else + { + RCC->CTLR &= ~RCC_HSE_LP; + } +} + +/********************************************************************* + * @fn RCC_HSI_LP_Cmd + * + * @brief Enables or disables low power mode of the Internal High Speed + * oscillator (HSI) . + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSI_LP_Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= RCC_HSILP; + } + else + { + RCC->CTLR &= ~RCC_HSILP; + } +} + +/********************************************************************* + * @fn RCC_HSECurrentConfig + * + * @brief Configures the HSE Current level. + * + * @param RCC_HSECurrent - the HSE Current level. + * RCC_HSE_C_Level0 - HSE Current is level 0. + * RCC_HSE_C_Level1 - HSE Current is level 1. + * RCC_HSE_C_Level2 - HSE Current is level 2. + * RCC_HSE_C_Level3 - HSE Current is level 3. + * + * @return none + */ +void RCC_HSECurrentConfig(uint32_t RCC_HSECurrent) +{ + RCC->CTLR &= ~RCC_HSE_SI; + RCC->CTLR |= RCC_HSECurrent; +} + +/********************************************************************* + * @fn RCC_ADCCLKDutyCycleConfig + * + * @brief Configures the ADC clock high level duty cycle. + * + * @param RCC_DutyCycle - high level duty cycle. + * RCC_ADC_H_Level_Mode0 - ADC clock high-level duty cycle is mode 0. + * RCC_ADC_H_Level_Mode1 - ADC clock high-level duty cycle is mode 1. + * + * @return none + */ +void RCC_ADCCLKDutyCycleConfig(uint32_t RCC_DutyCycle) +{ + RCC->CFGR0 &= ~RCC_ADC_CLK_ADJ; + RCC->CFGR0 |= RCC_DutyCycle; +} diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_spi.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_spi.c index b713e37..8a9e35e 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_spi.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_spi.c @@ -1,530 +1,531 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_spi.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the SPI firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* SPI SPE mask */ -#define CTLR1_SPE_Set ((uint16_t)0x0040) -#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) - -/* SPI CRCNext mask */ -#define CTLR1_CRCNext_Set ((uint16_t)0x1000) - -/* SPI CRCEN mask */ -#define CTLR1_CRCEN_Set ((uint16_t)0x2000) -#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) - -/* SPI SSOE mask */ -#define CTLR2_SSOE_Set ((uint16_t)0x0004) -#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) - -/* SPI registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) - - -/********************************************************************* - * @fn SPI_I2S_DeInit - * - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values. - * @param SPIx - where x can be 1 to select the SPI peripheral. - * - * @return none - */ -void SPI_I2S_DeInit(SPI_TypeDef *SPIx) -{ - if(SPIx == SPI1) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_SPI1, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_SPI1, DISABLE); - } -} - -/********************************************************************* - * @fn SPI_Init - * - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * - * @return none - */ -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - tmpreg = SPIx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - - SPIx->CTLR1 = tmpreg; - SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/********************************************************************* - * @fn SPI_StructInit - * - * @brief Fills each SPI_InitStruct member with its default value. - * - * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) -{ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/********************************************************************* - * @fn SPI_Cmd - * - * @brief Enables or disables the specified SPI peripheral. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_SPE_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_SPE_Reset; - } -} - -/********************************************************************* - * @fn SPI_I2S_ITConfig - * - * @brief Enables or disables the specified SPI interrupts. - * - * @param SPIx - where x can be 1 in SPI mode. - * SPI_I2S_IT - specifies the SPI interrupt source to be - * enabled or disabled. - * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. - * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. - * SPI_I2S_IT_ERR - Error interrupt mask. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0; - - itpos = SPI_I2S_IT >> 4; - itmask = (uint16_t)1 << (uint16_t)itpos; - - if(NewState != DISABLE) - { - SPIx->CTLR2 |= itmask; - } - else - { - SPIx->CTLR2 &= (uint16_t)~itmask; - } -} - -/********************************************************************* - * @fn SPI_I2S_DMACmd - * - * @brief Enables or disables the SPIx DMA interface. - * - * @param SPIx - where x can be 1 in SPI mode. - * SPI_I2S_DMAReq - specifies the SPI DMA transfer request to - * be enabled or disabled. - * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. - * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= SPI_I2S_DMAReq; - } - else - { - SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/********************************************************************* - * @fn SPI_I2S_SendData - * - * @brief Transmits a Data through the SPIx peripheral. - * - * @param SPIx - where x can be 1 in SPI mode. - * Data - Data to be transmitted. - * - * @return none - */ -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) -{ - SPIx->DATAR = Data; -} - -/********************************************************************* - * @fn SPI_I2S_ReceiveData - * - * @brief Returns the most recent received data by the SPIx peripheral. - * - * @param SPIx - where x can be 1 in SPI mode. - * Data - Data to be transmitted. - * - * @return SPIx->DATAR - The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) -{ - return SPIx->DATAR; -} - -/********************************************************************* - * @fn SPI_NSSInternalSoftwareConfig - * - * @brief Configures internally by software the NSS pin for the selected SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_NSSInternalSoft - - * SPI_NSSInternalSoft_Set - Set NSS pin internally. - * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. - * - * @return none - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) -{ - if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; - } - else - { - SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/********************************************************************* - * @fn SPI_SSOutputCmd - * - * @brief Enables or disables the SS output for the selected SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * NewState - new state of the SPIx SS output. - * - * @return none - */ -void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= CTLR2_SSOE_Set; - } - else - { - SPIx->CTLR2 &= CTLR2_SSOE_Reset; - } -} - -/********************************************************************* - * @fn SPI_DataSizeConfig - * - * @brief Configures the data size for the selected SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_DataSize - specifies the SPI data size. - * SPI_DataSize_16b - Set data frame format to 16bit. - * SPI_DataSize_8b - Set data frame format to 8bit. - * - * @return none - */ -void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) -{ - SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; - SPIx->CTLR1 |= SPI_DataSize; -} - -/********************************************************************* - * @fn SPI_TransmitCRC - * - * @brief Transmit the SPIx CRC value. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * - * @return none - */ -void SPI_TransmitCRC(SPI_TypeDef *SPIx) -{ - SPIx->CTLR1 |= CTLR1_CRCNext_Set; -} - -/********************************************************************* - * @fn SPI_CalculateCRC - * - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * NewState - new state of the SPIx CRC value calculation. - * - * @return none - */ -void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_CRCEN_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_CRCEN_Reset; - } -} - -/********************************************************************* - * @fn SPI_GetCRC - * - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_CRC - specifies the CRC register to be read. - * SPI_CRC_Tx - Selects Tx CRC register. - * SPI_CRC_Rx - Selects Rx CRC register. - * - * @return crcreg: The selected CRC register value. - */ -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - - if(SPI_CRC != SPI_CRC_Rx) - { - crcreg = SPIx->TCRCR; - } - else - { - crcreg = SPIx->RCRCR; - } - - return crcreg; -} - -/********************************************************************* - * @fn SPI_GetCRCPolynomial - * - * @brief Returns the CRC Polynomial register value for the specified SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * - * @return SPIx->CRCR - The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) -{ - return SPIx->CRCR; -} - -/********************************************************************* - * @fn SPI_BiDirectionalLineConfig - * - * @brief Selects the data transfer direction in bi-directional mode - * for the specified SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_Direction - specifies the data transfer direction in - * bi-directional mode. - * SPI_Direction_Tx - Selects Tx transmission direction. - * SPI_Direction_Rx - Selects Rx receive direction. - * - * @return none - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) -{ - if(SPI_Direction == SPI_Direction_Tx) - { - SPIx->CTLR1 |= SPI_Direction_Tx; - } - else - { - SPIx->CTLR1 &= SPI_Direction_Rx; - } -} - -/********************************************************************* - * @fn SPI_HS_RX_Cmd - * - * @brief Enables or disables high speed read mode the specified SPI peripheral. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_HS_RX_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->HSCR |= SPI_HSCR_HSRXEN; - } - else - { - SPIx->HSCR &= ~SPI_HSCR_HSRXEN; - } -} - -/********************************************************************* - * @fn SPI_I2S_GetFlagStatus - * - * @brief Checks whether the specified SPI flag is set or not. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. - * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. - * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. - * SPI_I2S_FLAG_BSY - Busy flag. - * SPI_I2S_FLAG_OVR - Overrun flag. - * SPI_FLAG_MODF - Mode Fault flag. - * SPI_FLAG_CRCERR - CRC Error flag. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearFlag - * - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_FLAG - specifies the SPI flag to clear. - * SPI_FLAG_CRCERR - CRC Error flag. - * Note- - * - OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). - * - UDR (UnderRun error) flag is cleared by a read operation to - * SPI_STATR register (SPI_I2S_GetFlagStatus()). - * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). - * @return FlagStatus: SET or RESET. - */ -void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; -} - -/********************************************************************* - * @fn SPI_I2S_GetITStatus - * - * @brief Checks whether the specified SPI interrupt has occurred or not. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_IT - specifies the SPI interrupt source to check.. - * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. - * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. - * SPI_I2S_IT_OVR - Overrun interrupt. - * SPI_IT_MODF - Mode Fault interrupt. - * SPI_IT_CRCERR - CRC Error interrupt. - * - * @return FlagStatus: SET or RESET. - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - itmask = SPI_I2S_IT >> 4; - itmask = 0x01 << itmask; - enablestatus = (SPIx->CTLR2 & itmask); - - if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearITPendingBit - * - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. - * SPI_IT_CRCERR - CRC Error interrupt. - * Note- - * - OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). - * - UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_STATR register (SPI_I2S_GetITStatus()). - * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable - * the SPI). - * @return none - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - SPIx->STATR = (uint16_t)~itpos; -} - - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_spi.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/05 + * Description : This file provides all the SPI firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) + + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values. + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_SPI1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_SPI1, DISABLE); + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * When using SPI slave mode to send data, the CPOL bit should be set to 1. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI interrupts. + * + * @param SPIx - where x can be 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIx DMA interface. + * + * @param SPIx - where x can be 1 in SPI mode. + * SPI_I2S_DMAReq - specifies the SPI DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx peripheral. + * + * @param SPIx - where x can be 1 in SPI mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx peripheral. + * + * @param SPIx - where x can be 1 in SPI mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg: The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_HS_RX_Cmd + * + * @brief Enables or disables high speed read mode the specified SPI peripheral. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_HS_RX_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->HSCR |= SPI_HSCR_HSRXEN; + } + else + { + SPIx->HSCR &= ~SPI_HSCR_HSRXEN; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI flag is set or not. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * Note- + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). + * @return FlagStatus: SET or RESET. + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * Note- + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable + * the SPI). + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} + + + + + + diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_tim.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_tim.c index 445e1ee..a81a24c 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_tim.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_tim.c @@ -1,2601 +1,2601 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_tim.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the TIM firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* TIM registers bit mask */ -#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) -#define CHCTLR_Offset ((uint16_t)0x0018) -#define CCER_CCE_Set ((uint16_t)0x0001) -#define CCER_CCNE_Set ((uint16_t)0x0004) - -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/********************************************************************* - * @fn TIM_DeInit - * - * @brief Deinitializes the TIMx peripheral registers to their default - * reset values. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * - * @return none - */ -void TIM_DeInit(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM1) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_TIM1, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_TIM1, DISABLE); - } - else if(TIMx == TIM2) - { - RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM2, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM2, DISABLE); - } - else if(TIMx == TIM3) - { - RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM3, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM3, DISABLE); - } -} - -/********************************************************************* - * @fn TIM_TimeBaseInit - * - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef - * structure. - * - * @return none - */ -void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpcr1 = TIMx->CTLR1; - - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - - TIMx->CTLR1 = tmpcr1; - TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if(TIMx == TIM1) - { - TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; - } - else if(TIMx == TIM3) - { - tmpcr1 = TIMx->TIM3_CTLR; - - tmpcr1 &= (uint16_t)(~((uint16_t)(SLTM_DIR | SLTM_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - - TIMx->TIM3_CTLR = tmpcr1; - TIMx->TIM3_ATRLR = TIM_TimeBaseInitStruct->TIM_Period; - } -} - -/********************************************************************* - * @fn TIM_OC1Init - * - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if(TIMx == TIM1) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); - - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - else if(TIMx == TIM2) - { - TIM2->TIM2_DTCR &= 0xFFF2; - TIM2->TIM2_DTCR |= (TIM_OCInitStruct->TIM_OutputNState >> 2) \ - | (TIM_OCInitStruct->TIM_OCPolarity << 1) \ - | (TIM_OCInitStruct->TIM_OCNPolarity); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2Init - * - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if(TIMx == TIM1) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - else if(TIMx == TIM2) - { - TIM2->TIM2_DTCR &= 0xFFCD; - - TIM2->TIM2_DTCR |= (TIM_OCInitStruct->TIM_OutputNState >> 1) \ - | (TIM_OCInitStruct->TIM_OCPolarity << 3) \ - | (TIM_OCInitStruct->TIM_OCNPolarity << 2); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3Init - * - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if(TIMx == TIM1) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4Init - * - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if(TIMx == TIM1) - { - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ICInit - * - * @brief IInitializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_PWMIConfig - * - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external - * PWM signal. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - - if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_BDTRConfig - * - * @brief Configures the: Break feature, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable). - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/********************************************************************* - * @fn TIM_TimeBaseStructInit - * - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * - * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. - * - * @return none - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/********************************************************************* - * @fn TIM_OCStructInit - * - * @brief Fills each TIM_OCInitStruct member with its default value. - * - * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/********************************************************************* - * @fn TIM_ICStructInit - * - * @brief Fills each TIM_ICInitStruct member with its default value. - * - * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/********************************************************************* - * @fn TIM_BDTRStructInit - * - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * - * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/********************************************************************* - * @fn TIM_Cmd - * - * @brief Enables or disables the specified TIM peripheral. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->CTLR1 |= TIM_CEN; - } - else if(TIMx == TIM3) - { - TIMx->TIM3_CTLR |= SLTM_CEN; - } - } - else - { - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); - } - else if(TIMx == TIM3) - { - TIMx->TIM3_CTLR &= (uint16_t)(~((uint16_t)SLTM_CEN)); - } - } -} - -/********************************************************************* - * @fn TIM_CtrlPWMOutputs - * - * @brief Enables or disables the TIM peripheral Main Outputs. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->BDTR |= TIM_MOE; - } - else - { - TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); - } -} - -/********************************************************************* - * @fn TIM_ITConfig - * - * @brief Enables or disables the specified TIM interrupts. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->DMAINTENR |= TIM_IT; - } - else - { - TIMx->DMAINTENR &= (uint16_t)~TIM_IT; - } -} - -/********************************************************************* - * @fn TIM_GenerateEvent - * - * @brief Configures the TIMx event to be generate by software. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) -{ - TIMx->SWEVGR = TIM_EventSource; -} - -/********************************************************************* - * @fn TIM_DMAConfig - * - * @brief Configures the TIMx's DMA interface. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_DMABase: DMA Base address. - * TIM_DMABase_CR. - * TIM_DMABase_CR2. - * TIM_DMABase_SMCR. - * TIM_DMABase_DIER. - * TIM1_DMABase_SR. - * TIM_DMABase_EGR. - * TIM_DMABase_CCMR1. - * TIM_DMABase_CCMR2. - * TIM_DMABase_CCER. - * TIM_DMABase_CNT. - * TIM_DMABase_PSC. - * TIM_DMABase_CCR1. - * TIM_DMABase_CCR2. - * TIM_DMABase_CCR3. - * TIM_DMABase_CCR4. - * TIM_DMABase_BDTR. - * TIM_DMABase_DCR. - * TIM_DMABurstLength - DMA Burst length. - * TIM_DMABurstLength_1Transfer. - * TIM_DMABurstLength_18Transfers. - * - * @return none - */ -void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; -} - -/********************************************************************* - * @fn TIM_DMACmd - * - * @brief Enables or disables the TIMx's DMA Requests. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_DMASource - specifies the DMA Request sources. - * TIM_DMA_Update - TIM update Interrupt source.(for TIM1 TIM2) - * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source.(for TIM1 TIM2) - * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source.(for TIM1 TIM2) - * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source.(for TIM1 TIM2 TIM3) - * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source.(for TIM1 TIM2 TIM3) - * TIM_DMA_COM - TIM Commutation DMA source.(for TIM1 TIM2) - * TIM_DMA_Trigger - TIM Trigger DMA source.(for TIM1 TIM2) - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->DMAINTENR |= TIM_DMASource; - } - else if(TIMx == TIM3) - { - TIMx->TIM3_DMAINTENR |= TIM_DMASource; - } - } - else - { - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; - } - else if(TIMx == TIM3) - { - TIMx->TIM3_DMAINTENR &= (uint16_t)~TIM_DMASource;; - } - - } -} - -/********************************************************************* - * @fn TIM_InternalClockConfig - * - * @brief Configures the TIMx internal Clock. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * - * @return none - */ -void TIM_InternalClockConfig(TIM_TypeDef *TIMx) -{ - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); - } - else if(TIMx == TIM3) - { - TIMx->TIM3_CTLR &= (uint16_t)(~((uint16_t)SLTM_SMS)); - } -} - -/********************************************************************* - * @fn TIM_ITRxExternalClockConfig - * - * @brief Configures the TIMx Internal Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_InputTriggerSource: Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * - * @return none - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_TIxExternalClockConfig - * - * @brief Configures the TIMx Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_TIxExternalCLKSource - Trigger source. - * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. - * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. - * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. - * TIM_ICPolarity - specifies the TIx Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_DMA_COM - TIM Commutation DMA source. - * TIM_DMA_Trigger - TIM Trigger DMA source. - * ICFilter - specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_ETRClockMode1Config - * - * @brief Configures the External clock Mode1. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_SlaveMode_External1; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_TS_ETRF; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_ETRClockMode2Config - * - * @brief Configures the External clock Mode2. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - TIMx->SMCFGR |= TIM_ECE; -} - -/********************************************************************* - * @fn TIM_ETRConfig - * - * @brief Configures the TIMx External Trigger (ETR). - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= SMCFGR_ETR_Mask; - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_PrescalerConfig - * - * @brief Configures the TIMx Prescaler. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * Prescaler - specifies the Prescaler Register value. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. - * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. - * - * @return none - */ -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - TIMx->PSC = Prescaler; - TIMx->SWEVGR = TIM_PSCReloadMode; -} - -/********************************************************************* - * @fn TIM_CounterModeConfig - * - * @brief Specifies the TIMx Counter Mode to be used. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_CounterMode - specifies the Counter Mode to be used. - * TIM_CounterMode_Up - TIM Up Counting Mode. - * TIM_CounterMode_Down - TIM Down Counting Mode. - * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. - * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. - * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. - * - * @return none - */ -void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpcr1 = TIMx->CTLR1; - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= TIM_CounterMode; - TIMx->CTLR1 = tmpcr1; - } - else if(TIMx == TIM3) - { - tmpcr1 = TIMx->TIM3_CTLR; - tmpcr1 &= (uint16_t)(~((uint16_t)(SLTM_DIR | SLTM_CMS))); - tmpcr1 |= TIM_CounterMode; - TIMx->TIM3_CTLR = tmpcr1; - } -} - -/********************************************************************* - * @fn TIM_SelectInputTrigger - * - * @brief Selects the Input Trigger source. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_InputTriggerSource - The Input Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * TIM_TS_TI1F_ED - TI1 Edge Detector. - * TIM_TS_TI1FP1 - Filtered Timer Input 1. - * TIM_TS_TI2FP2 - Filtered Timer Input 2. - * TIM_TS_ETRF - External Trigger input. - * - * @return none - */ -void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_InputTriggerSource; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_EncoderInterfaceConfig - * - * @brief Configures the TIMx Encoder Interface. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_EncoderMode - specifies the TIMx Encoder Mode. - * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending - * on TI2FP2 level. - * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending - * on TI1FP1 level. - * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and - * TI2FP2 edges depending. - * TIM_IC1Polarity - specifies the IC1 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TTIM_ICPolarity_Rising - IC Rising edge. - * TIM_IC2Polarity - specifies the IC2 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TIM_ICPolarity_Rising - IC Rising edge. - * - * @return none - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_EncoderMode; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); - tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; - tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - TIMx->SMCFGR = tmpsmcr; - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ForcedOC1Config - * - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC1REF. - * TIM_ForcedAction_InActive - Force inactive level on OC1REF. - * - * @return none - */ -void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); - tmpccmr1 |= TIM_ForcedAction; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC2Config - * - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC2REF. - * TIM_ForcedAction_InActive - Force inactive level on OC2REF. - * - * @return none - */ -void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC3Config - * - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC3REF. - * TIM_ForcedAction_InActive - Force inactive level on OC3REF. - * - * @return none - */ -void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); - tmpccmr2 |= TIM_ForcedAction; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ForcedOC4Config - * - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC4REF. - * TIM_ForcedAction_InActive - Force inactive level on OC4REF. - * - * @return none - */ -void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ARRPreloadConfig - * - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->CTLR1 |= TIM_ARPE; - } - else if(TIMx == TIM3) - { - TIMx->TIM3_CTLR |= SLTM_ARPE; - } - } - else - { - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); - } - else if(TIMx == TIM3) - { - TIMx->TIM3_CTLR &= (uint16_t) ~((uint16_t)SLTM_ARPE); - } - } -} - -/********************************************************************* - * @fn TIM_SelectCOM - * - * @brief Selects the TIM peripheral Commutation event. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCUS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); - } -} - -/********************************************************************* - * @fn TIM_SelectCCDMA - * - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCDS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); - } -} - -/********************************************************************* - * @fn TIM_CCPreloadControl - * - * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. - * reset values . - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCPC; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); - } -} - -/********************************************************************* - * @fn TIM_OC1PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); - tmpccmr1 |= TIM_OCPreload; - TIMx->CHCTLR1 = tmpccmr1; - } - else if(TIMx == TIM3) - { - tmpccmr1 = TIMx->TIM3_DMAINTENR; - tmpccmr1 &= (uint16_t) ~((uint16_t)SLTM_OC1PE); - tmpccmr1 |= (TIM_OCPreload >> 3); - TIMx->TIM3_DMAINTENR = tmpccmr1; - } -} - -/********************************************************************* - * @fn TIM_OC2PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR1 = tmpccmr1; - } - else if(TIMx == TIM3) - { - tmpccmr1 = TIMx->TIM3_DMAINTENR; - tmpccmr1 &= (uint16_t) ~((uint16_t)SLTM_OC2PE); - tmpccmr1 |= (TIM_OCPreload >> 2); - TIMx->TIM3_DMAINTENR = tmpccmr1; - } -} - -/********************************************************************* - * @fn TIM_OC3PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); - tmpccmr2 |= TIM_OCPreload; - TIMx->CHCTLR2 = tmpccmr2; - } - else if(TIMx == TIM3) - { - tmpccmr2 = TIMx->TIM3_DMAINTENR; - tmpccmr2 &= (uint16_t) ~((uint16_t)SLTM_OC3PE); - tmpccmr2 |= (TIM_OCPreload >> 1); - TIMx->TIM3_DMAINTENR = tmpccmr2; - } -} - -/********************************************************************* - * @fn TIM_OC4PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR2 = tmpccmr2; - } - else if(TIMx == TIM3) - { - tmpccmr2 = TIMx->TIM3_DMAINTENR; - tmpccmr2 &= (uint16_t) ~((uint16_t)SLTM_OC4PE); - tmpccmr2 |= TIM_OCPreload; - TIMx->TIM3_DMAINTENR = tmpccmr2; - } -} - -/********************************************************************* - * @fn TIM_OC1FastConfig - * - * @brief Configures the TIMx Output Compare 1 Fast feature. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); - tmpccmr1 |= TIM_OCFast; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC2FastConfig - * - * @brief Configures the TIMx Output Compare 2 Fast feature. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC3FastConfig - * - * @brief Configures the TIMx Output Compare 3 Fast feature. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); - tmpccmr2 |= TIM_OCFast; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC4FastConfig - * - * @brief Configures the TIMx Output Compare 4 Fast feature. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC1Ref - * - * @brief Clears or safeguards the OCREF1 signal on an external event. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); - tmpccmr1 |= TIM_OCClear; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC2Ref - * - * @brief Clears or safeguards the OCREF2 signal on an external event. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC3Ref - * - * @brief Clears or safeguards the OCREF3 signal on an external event. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); - tmpccmr2 |= TIM_OCClear; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC4Ref - * - * @brief Clears or safeguards the OCREF4 signal on an external event. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC1PolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC1 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); - tmpccer |= TIM_OCPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC1NPolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); - tmpccer |= TIM_OCNPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2PolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC2 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2NPolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3PolarityConfig - * - * @brief Configures the TIMx Channel 3 polarity. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3NPolarityConfig - * - * @brief Configures the TIMx Channel 3N polarity. - * - * @param TIMx - where x can be 1 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC2N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4PolarityConfig - * - * @brief Configures the TIMx Channel 2 polarity. - * - * @param TIMx - where x can be 1 to 4 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_CCxCmd - * - * @brief Enables or disables the TIM Capture Compare Channel x. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_CCx - specifies the TIM Channel CCxE bit new state. - * TIM_CCx_Enable. - * TIM_CCx_Disable. - * - * @return none - */ -void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - tmp = CCER_CCE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_CCxNCmd - * - * @brief Enables or disables the TIM Capture Compare Channel xN. - * - * @param TIMx - where x can be 1 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. - * TIM_CCxN_Enable. - * TIM_CCxN_Disable. - * - * @return none - */ -void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - tmp = CCER_CCNE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_SelectOCxM - * - * @brief Selects the TIM Output Compare Mode. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_OCMode - specifies the TIM Output Compare Mode. - * TIM_OCMode_Timing. - * TIM_OCMode_Active. - * TIM_OCMode_Toggle. - * TIM_OCMode_PWM1. - * TIM_OCMode_PWM2. - * TIM_ForcedAction_Active. - * TIM_ForcedAction_InActive. - * - * @return none - */ -void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - tmp = (uint32_t)TIMx; - tmp += CHCTLR_Offset; - tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp1; - - if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel >> 1); - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); - *(__IO uint32_t *)tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); - *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/********************************************************************* - * @fn TIM_UpdateDisableConfig - * - * @brief Enables or Disables the TIMx Update event. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->CTLR1 |= TIM_UDIS; - } - else if(TIMx == TIM3) - { - TIMx->TIM3_CTLR |= SLTM_UDIS; - } - } - else - { - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); - } - else if(TIMx == TIM3) - { - TIMx->TIM3_CTLR &= (uint16_t) ~((uint16_t)SLTM_UDIS); - } - } -} - -/********************************************************************* - * @fn TIM_UpdateRequestConfig - * - * @brief Configures the TIMx Update Request Interrupt source. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_UpdateSource - specifies the Update source. - * TIM_UpdateSource_Regular. - * TIM_UpdateSource_Global. - * - * @return none - */ -void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) -{ - if(TIM_UpdateSource != TIM_UpdateSource_Global) - { - TIMx->CTLR1 |= TIM_URS; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); - } -} - -/********************************************************************* - * @fn TIM_SelectHallSensor - * - * @brief Enables or disables the TIMx's Hall sensor interface. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_TI1S; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); - } -} - -/********************************************************************* - * @fn TIM_SelectOnePulseMode - * - * @brief Selects the TIMx's One Pulse Mode. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_OPMode - specifies the OPM Mode to be used. - * TIM_OPMode_Single. - * TIM_OPMode_Repetitive. - * - * @return none - */ -void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); - TIMx->CTLR1 |= TIM_OPMode; -} - -/********************************************************************* - * @fn TIM_SelectOutputTrigger - * - * @brief Selects the TIMx Trigger Output Mode. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_TRGOSource - specifies the Trigger Output source. - * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is - * used as the trigger output (TRGO). - * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the - * trigger output (TRGO). - * TIM_TRGOSource_Update - The update event is selected as the - * trigger output (TRGO). - * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse - * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). - * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). - * - * @return none - */ -void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) -{ - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); - TIMx->CTLR2 |= TIM_TRGOSource; -} - -/********************************************************************* - * @fn TIM_SelectSlaveMode - * - * @brief Selects the TIMx Slave Mode. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_SlaveMode - specifies the Timer Slave Mode. - * TIM_SlaveMode_Reset - Rising edge of the selected trigger - * signal (TRGI) re-initializes. - * TIM_SlaveMode_Gated - The counter clock is enabled when the - * trigger signal (TRGI) is high. - * TIM_SlaveMode_Trigger - The counter starts at a rising edge - * of the trigger TRGI. - * TIM_SlaveMode_External1 - Rising edges of the selected trigger - * (TRGI) clock the counter. - * - * @return none - */ -void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) -{ - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); - TIMx->SMCFGR |= TIM_SlaveMode; - } - else if(TIMx == TIM3) - { - TIMx->TIM3_CTLR &= (uint16_t) ~((uint16_t)SLTM_SMS); - TIMx->TIM3_CTLR |= (TIM_SlaveMode << 8); - } -} - -/********************************************************************* - * @fn TIM_SelectMasterSlaveMode - * - * @brief Sets or Resets the TIMx Master/Slave Mode. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. - * TIM_MasterSlaveMode_Enable - synchronization between the current - * timer and its slaves (through TRGO). - * TIM_MasterSlaveMode_Disable - No action. - * - * @return none - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) -{ - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); - TIMx->SMCFGR |= TIM_MasterSlaveMode; -} - -/********************************************************************* - * @fn TIM_SetCounter - * - * @brief Sets the TIMx Counter Register value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * Counter - specifies the Counter register new value. - * - * @return none - */ -void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) -{ - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->CNT = Counter; - } - else if(TIMx == TIM3) - { - TIMx->TIM3_CNT = Counter; - } -} - -/********************************************************************* - * @fn TIM_SetAutoreload - * - * @brief Sets the TIMx Autoreload Register value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * Autoreload - specifies the Autoreload register new value. - * - * @return none - */ -void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) -{ - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->ATRLR = Autoreload; - } - else if(TIMx == TIM3) - { - TIMx->TIM3_ATRLR = Autoreload; - } -} - -/********************************************************************* - * @fn TIM_SetCompare1 - * - * @brief Sets the TIMx Capture Compare1 Register value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) -{ - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->CH1CVR = Compare1; - } - else if(TIMx == TIM3) - { - TIMx->TIM3_CH1CVR = Compare1; - } -} - -/********************************************************************* - * @fn TIM_SetCompare2 - * - * @brief Sets the TIMx Capture Compare2 Register value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) -{ - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->CH2CVR = Compare2; - } - else if(TIMx == TIM3) - { - TIMx->TIM3_CH2CVR = Compare2; - } -} - -/********************************************************************* - * @fn TIM_SetCompare3 - * - * @brief Sets the TIMx Capture Compare3 Register value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) -{ - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->CH3CVR = Compare3; - } - else if(TIMx == TIM3) - { - TIMx->TIM3_CH3CVR = Compare3; - } -} - -/********************************************************************* - * @fn TIM_SetCompare4 - * - * @brief Sets the TIMx Capture Compare4 Register value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) -{ - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->CH4CVR = Compare4; - } - else if(TIMx == TIM3) - { - TIMx->TIM3_CH4CVR = Compare4; - } -} - -/********************************************************************* - * @fn TIM_SetIC1Prescaler - * - * @brief Sets the TIMx Input Capture 1 prescaler. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); - TIMx->CHCTLR1 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC2Prescaler - * - * @brief Sets the TIMx Input Capture 2 prescaler. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); - TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetIC3Prescaler - * - * @brief Sets the TIMx Input Capture 3 prescaler. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); - TIMx->CHCTLR2 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC4Prescaler - * - * @brief Sets the TIMx Input Capture 4 prescaler. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); - TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetClockDivision - * - * @brief Sets the TIMx Clock Division value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_CKD - specifies the clock division value. - * TIM_CKD_DIV1 - TDTS = Tck_tim. - * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. - * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. - * - * @return none - */ -void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); - TIMx->CTLR1 |= TIM_CKD; -} - -/********************************************************************* - * @fn TIM_GetCapture1 - * - * @brief Gets the TIMx Input Capture 1 value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * - * @return TIMx->CH1CVR - Capture Compare 1 Register value. - */ -uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) -{ - if((TIMx == TIM1) || (TIMx == TIM2)) - { - return TIMx->CH1CVR; - } - else if(TIMx == TIM3) - { - return TIMx->TIM3_CH1CVR; - } - return 0; -} - -/********************************************************************* - * @fn TIM_GetCapture2 - * - * @brief Gets the TIMx Input Capture 2 value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * - * @return TIMx->CH2CVR - Capture Compare 2 Register value. - */ -uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) -{ - if((TIMx == TIM1) || (TIMx == TIM2)) - { - return TIMx->CH2CVR; - } - else if(TIMx == TIM3) - { - return TIMx->TIM3_CH2CVR; - } - return 0; -} - -/********************************************************************* - * @fn TIM_GetCapture3 - * - * @brief Gets the TIMx Input Capture 3 value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * - * @return TIMx->CH3CVR - Capture Compare 3 Register value. - */ -uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) -{ - if((TIMx == TIM1) || (TIMx == TIM2)) - { - return TIMx->CH3CVR; - } - else if(TIMx == TIM3) - { - return TIMx->TIM3_CH3CVR; - } - return 0; -} - -/********************************************************************* - * @fn TIM_GetCapture4 - * - * @brief Gets the TIMx Input Capture 4 value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * - * @return TIMx->CH4CVR - Capture Compare 4 Register value. - */ -uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) -{ - if((TIMx == TIM1) || (TIMx == TIM2)) - { - return TIMx->CH4CVR; - } - else if(TIMx == TIM3) - { - return TIMx->TIM3_CH4CVR; - } - return 0; -} - -/********************************************************************* - * @fn TIM_GetCounter - * - * @brief Gets the TIMx Counter value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * - * @return TIMx->CNT - Counter Register value. - */ -uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) -{ - if((TIMx == TIM1) || (TIMx == TIM2)) - { - return TIMx->CNT; - } - else if(TIMx == TIM3) - { - return TIMx->TIM3_CNT; - } - return 0; -} - -/********************************************************************* - * @fn TIM_GetPrescaler - * - * @brief Gets the TIMx Prescaler value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * - * @return TIMx->PSC - Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) -{ - return TIMx->PSC; -} - -/********************************************************************* - * @fn TIM_GetFlagStatus - * - * @brief Checks whether the specified TIM flag is set or not. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return SET or RESET. - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - - if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearFlag - * - * @brief Clears the TIMx's pending flags. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return none - */ -void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - TIMx->INTFR = (uint16_t)~TIM_FLAG; -} - -/********************************************************************* - * @fn TIM_GetITStatus - * - * @brief Checks whether the TIM interrupt has occurred or not. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - - itstatus = TIMx->INTFR & TIM_IT; - - itenable = TIMx->DMAINTENR & TIM_IT; - if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearITPendingBit - * - * @brief Clears the TIMx's interrupt pending bits. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - TIMx->INTFR = (uint16_t)~TIM_IT; -} - -/********************************************************************* - * @fn TI1_Config - * - * @brief Configure the TI1 as Input. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); - - TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI2_Config - * - * @brief Configure the TI2 as Input. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 2 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 2 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 2 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); - - TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI3_Config - * - * @brief Configure the TI3 as Input. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 3 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 3 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 3 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); - - TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI4_Config - * - * @brief Configure the TI4 as Input. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 4 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 4 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 4 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); - - TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_IndicateCaptureLevelCmd - * - * @brief Enables or disables the TIMx capture level indication. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState) - { - TIMx->CTLR1 |= (1<<15); - } - else{ - TIMx->CTLR1 &= ~(1<<15); - } -} - -/********************************************************************* - * @fn TIM_DeadTimeConfig - * - * @brief Configures the TIM2 complementary output dead time. - * - * @param TIMx - where x can be 2 to select the TIM peripheral. - * DeadTime - This parameter can be a number between 0x00 and 0xFF. - * TIM_Channel - TIM2 out channel. - * TIM_Channel_1 - TIM output Channel 1. - * TIM_Channel_2 - TIM output Channel 2. - * - * @return none - */ -void TIM_DeadTimeConfig(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint8_t DeadTime) -{ - if(TIMx == TIM2) - { - TIM2->TIM2_DTCR &= ~((0xF << (TIM_Channel + 8))); - TIM2->TIM2_DTCR |= ((uint16_t)DeadTime) << (TIM_Channel + 8); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_tim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file provides all the TIM firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_TIM1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM2, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM2, DISABLE); + } + else if(TIMx == TIM3) + { + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM3, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_TIM3, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpcr1 = TIMx->CTLR1; + + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + + TIMx->CTLR1 = tmpcr1; + TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if(TIMx == TIM1) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; + } + else if(TIMx == TIM3) + { + tmpcr1 = TIMx->TIM3_CTLR; + + tmpcr1 &= (uint16_t)(~((uint16_t)(SLTM_DIR | SLTM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + + TIMx->TIM3_CTLR = tmpcr1; + TIMx->TIM3_ATRLR = TIM_TimeBaseInitStruct->TIM_Period; + } +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + else if(TIMx == TIM2) + { + TIM2->TIM2_DTCR &= 0xFFF2; + TIM2->TIM2_DTCR |= (TIM_OCInitStruct->TIM_OutputNState >> 2) \ + | (TIM_OCInitStruct->TIM_OCPolarity << 1) \ + | (TIM_OCInitStruct->TIM_OCNPolarity); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + else if(TIMx == TIM2) + { + TIM2->TIM2_DTCR &= 0xFFCD; + + TIM2->TIM2_DTCR |= (TIM_OCInitStruct->TIM_OutputNState >> 1) \ + | (TIM_OCInitStruct->TIM_OCPolarity << 3) \ + | (TIM_OCInitStruct->TIM_OCNPolarity << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if(TIMx == TIM1) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->CTLR1 |= TIM_CEN; + } + else if(TIMx == TIM3) + { + TIMx->TIM3_CTLR |= SLTM_CEN; + } + } + else + { + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } + else if(TIMx == TIM3) + { + TIMx->TIM3_CTLR &= (uint16_t)(~((uint16_t)SLTM_CEN)); + } + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +/********************************************************************* + * @fn TIM_GenerateEvent + * + * @brief Configures the TIMx event to be generate by software. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_DMABase: DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source.(for TIM1 TIM2) + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source.(for TIM1 TIM2) + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source.(for TIM1 TIM2) + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source.(for TIM1 TIM2 TIM3) + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source.(for TIM1 TIM2 TIM3) + * TIM_DMA_COM - TIM Commutation DMA source.(for TIM1 TIM2) + * TIM_DMA_Trigger - TIM Trigger DMA source.(for TIM1 TIM2) + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else if(TIMx == TIM3) + { + TIMx->TIM3_DMAINTENR |= TIM_DMASource; + } + } + else + { + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } + else if(TIMx == TIM3) + { + TIMx->TIM3_DMAINTENR &= (uint16_t)~TIM_DMASource;; + } + + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); + } + else if(TIMx == TIM3) + { + TIMx->TIM3_CTLR &= (uint16_t)(~((uint16_t)SLTM_SMS)); + } +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; + } + else if(TIMx == TIM3) + { + tmpcr1 = TIMx->TIM3_CTLR; + tmpcr1 &= (uint16_t)(~((uint16_t)(SLTM_DIR | SLTM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->TIM3_CTLR = tmpcr1; + } +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else if(TIMx == TIM3) + { + TIMx->TIM3_CTLR |= SLTM_ARPE; + } + } + else + { + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } + else if(TIMx == TIM3) + { + TIMx->TIM3_CTLR &= (uint16_t) ~((uint16_t)SLTM_ARPE); + } + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values . + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; + } + else if(TIMx == TIM3) + { + tmpccmr1 = TIMx->TIM3_DMAINTENR; + tmpccmr1 &= (uint16_t) ~((uint16_t)SLTM_OC1PE); + tmpccmr1 |= (TIM_OCPreload >> 3); + TIMx->TIM3_DMAINTENR = tmpccmr1; + } +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; + } + else if(TIMx == TIM3) + { + tmpccmr1 = TIMx->TIM3_DMAINTENR; + tmpccmr1 &= (uint16_t) ~((uint16_t)SLTM_OC2PE); + tmpccmr1 |= (TIM_OCPreload >> 2); + TIMx->TIM3_DMAINTENR = tmpccmr1; + } +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; + } + else if(TIMx == TIM3) + { + tmpccmr2 = TIMx->TIM3_DMAINTENR; + tmpccmr2 &= (uint16_t) ~((uint16_t)SLTM_OC3PE); + tmpccmr2 |= (TIM_OCPreload >> 1); + TIMx->TIM3_DMAINTENR = tmpccmr2; + } +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; + } + else if(TIMx == TIM3) + { + tmpccmr2 = TIMx->TIM3_DMAINTENR; + tmpccmr2 &= (uint16_t) ~((uint16_t)SLTM_OC4PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->TIM3_DMAINTENR = tmpccmr2; + } +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 2 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else if(TIMx == TIM3) + { + TIMx->TIM3_CTLR |= SLTM_UDIS; + } + } + else + { + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } + else if(TIMx == TIM3) + { + TIMx->TIM3_CTLR &= (uint16_t) ~((uint16_t)SLTM_UDIS); + } + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; + } + else if(TIMx == TIM3) + { + TIMx->TIM3_CTLR &= (uint16_t) ~((uint16_t)SLTM_SMS); + TIMx->TIM3_CTLR |= (TIM_SlaveMode << 8); + } +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) +{ + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->CNT = Counter; + } + else if(TIMx == TIM3) + { + TIMx->TIM3_CNT = Counter; + } +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) +{ + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->ATRLR = Autoreload; + } + else if(TIMx == TIM3) + { + TIMx->TIM3_ATRLR = Autoreload; + } +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) +{ + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->CH1CVR = Compare1; + } + else if(TIMx == TIM3) + { + TIMx->TIM3_CH1CVR = Compare1; + } +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) +{ + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->CH2CVR = Compare2; + } + else if(TIMx == TIM3) + { + TIMx->TIM3_CH2CVR = Compare2; + } +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) +{ + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->CH3CVR = Compare3; + } + else if(TIMx == TIM3) + { + TIMx->TIM3_CH3CVR = Compare3; + } +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) +{ + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->CH4CVR = Compare4; + } + else if(TIMx == TIM3) + { + TIMx->TIM3_CH4CVR = Compare4; + } +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + if((TIMx == TIM1) || (TIMx == TIM2)) + { + return TIMx->CH1CVR; + } + else if(TIMx == TIM3) + { + return TIMx->TIM3_CH1CVR; + } + return 0; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + if((TIMx == TIM1) || (TIMx == TIM2)) + { + return TIMx->CH2CVR; + } + else if(TIMx == TIM3) + { + return TIMx->TIM3_CH2CVR; + } + return 0; +} + +/********************************************************************* + * @fn TIM_GetCapture3 + * + * @brief Gets the TIMx Input Capture 3 value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * + * @return TIMx->CH3CVR - Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + if((TIMx == TIM1) || (TIMx == TIM2)) + { + return TIMx->CH3CVR; + } + else if(TIMx == TIM3) + { + return TIMx->TIM3_CH3CVR; + } + return 0; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + if((TIMx == TIM1) || (TIMx == TIM2)) + { + return TIMx->CH4CVR; + } + else if(TIMx == TIM3) + { + return TIMx->TIM3_CH4CVR; + } + return 0; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + if((TIMx == TIM1) || (TIMx == TIM2)) + { + return TIMx->CNT; + } + else if(TIMx == TIM3) + { + return TIMx->TIM3_CNT; + } + return 0; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return SET or RESET. + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 2 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 2 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 2 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 3 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 3 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 3 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 4 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 4 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 4 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_IndicateCaptureLevelCmd + * + * @brief Enables or disables the TIMx capture level indication. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState) + { + TIMx->CTLR1 |= (1<<15); + } + else{ + TIMx->CTLR1 &= ~(1<<15); + } +} + +/********************************************************************* + * @fn TIM_DeadTimeConfig + * + * @brief Configures the TIM2 complementary output dead time. + * + * @param TIMx - where x can be 2 to select the TIM peripheral. + * DeadTime - This parameter can be a number between 0x00 and 0xFF. + * TIM_Channel - TIM2 out channel. + * TIM_Channel_1 - TIM output Channel 1. + * TIM_Channel_2 - TIM output Channel 2. + * + * @return none + */ +void TIM_DeadTimeConfig(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint8_t DeadTime) +{ + if(TIMx == TIM2) + { + TIM2->TIM2_DTCR &= ~((0xF << (TIM_Channel + 8))); + TIM2->TIM2_DTCR |= ((uint16_t)DeadTime) << (TIM_Channel + 8); + } +} diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_usart.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_usart.c index 38e5602..c0e5e65 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_usart.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_usart.c @@ -1,625 +1,625 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_usart.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the USART firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* USART_Private_Defines */ -#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ -#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ - -#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ - -#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ -#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ -#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ -#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ - -#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ -#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ - -#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ -#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ -#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ - -#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ -#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ - -#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ -#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ - -#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ -#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ -#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ -#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ - -/********************************************************************* - * @fn USART_DeInit - * - * @brief Deinitializes the USARTx peripheral registers to their default - * reset values. - * - * @param USARTx - where x can be 1 or 2 to select the UART peripheral. - * - * @return none - */ -void USART_DeInit(USART_TypeDef *USARTx) -{ - if(USARTx == USART1) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART1, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART1, DISABLE); - } - if(USARTx == USART2) - { - RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART2, ENABLE); - RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART2, DISABLE); - } -} - -/********************************************************************* - * @fn USART_Init - * - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct. - * - * @param USARTx - where x can be 1 or 2 to select the UART peripheral. - * USART_InitStruct - pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified - * USART peripheral. - * - * @return none - */ -void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - uint32_t usartxbase = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - - if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - } - - usartxbase = (uint32_t)USARTx; - tmpreg = USARTx->CTLR2; - tmpreg &= CTLR2_STOP_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - USARTx->CTLR2 = (uint16_t)tmpreg; - tmpreg = USARTx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - USARTx->CTLR1 = (uint16_t)tmpreg; - - tmpreg = USARTx->CTLR3; - tmpreg &= CTLR3_CLEAR_Mask; - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - USARTx->CTLR3 = (uint16_t)tmpreg; - - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if(usartxbase == USART1_BASE) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - - tmpreg = (integerdivider / 100) << 4; - - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - - USARTx->BRR = (uint16_t)tmpreg; -} - -/********************************************************************* - * @fn USART_StructInit - * - * @brief Fills each USART_InitStruct member with its default value. - * - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void USART_StructInit(USART_InitTypeDef *USART_InitStruct) -{ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/********************************************************************* - * @fn USART_Cmd - * - * @brief Enables or disables the specified USART peripheral. - * reset values . - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_UE_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_UE_Reset; - } -} - -/********************************************************************* - * @fn USART_ITConfig - * - * @brief Enables or disables the specified USART interrupts. - * reset values . - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * USART_IT - specifies the USART interrupt sources to be enabled or disabled. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Transmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_PE - Parity Error interrupt. - * USART_IT_ERR - Error interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - - usartxbase = (uint32_t)USARTx; - usartreg = (((uint8_t)USART_IT) >> 0x05); - itpos = USART_IT & IT_Mask; - itmask = (((uint32_t)0x01) << itpos); - - if(usartreg == 0x01) - { - usartxbase += 0x0C; - } - else if(usartreg == 0x02) - { - usartxbase += 0x10; - } - else - { - usartxbase += 0x14; - } - - if(NewState != DISABLE) - { - *(__IO uint32_t *)usartxbase |= itmask; - } - else - { - *(__IO uint32_t *)usartxbase &= ~itmask; - } -} - -/********************************************************************* - * @fn USART_DMACmd - * - * @brief Enables or disables the USART DMA interface. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * USART_DMAReq - specifies the DMA request. - * USART_DMAReq_Tx - USART DMA transmit request. - * USART_DMAReq_Rx - USART DMA receive request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= USART_DMAReq; - } - else - { - USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; - } -} - -/********************************************************************* - * @fn USART_SetAddress - * - * @brief Sets the address of the USART node. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * USART_Address - Indicates the address of the USART node. - * - * @return none - */ -void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) -{ - USARTx->CTLR2 &= CTLR2_Address_Mask; - USARTx->CTLR2 |= USART_Address; -} - -/********************************************************************* - * @fn USART_WakeUpConfig - * - * @brief Selects the USART WakeUp method. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * USART_WakeUp - specifies the USART wakeup method. - * USART_WakeUp_IdleLine - WakeUp by an idle line detection. - * USART_WakeUp_AddressMark - WakeUp by an address mark. - * - * @return none - */ -void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) -{ - USARTx->CTLR1 &= CTLR1_WAKE_Mask; - USARTx->CTLR1 |= USART_WakeUp; -} - -/********************************************************************* - * @fn USART_ReceiverWakeUpCmd - * - * @brief Determines if the USART is in mute mode or not. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_RWU_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_RWU_Reset; - } -} - -/********************************************************************* - * @fn USART_LINBreakDetectLengthConfig - * - * @brief Sets the USART LIN Break detection length. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * USART_LINBreakDetectLength - specifies the LIN break detection length. - * USART_LINBreakDetectLength_10b - 10-bit break detection. - * USART_LINBreakDetectLength_11b - 11-bit break detection. - * - * @return none - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) -{ - USARTx->CTLR2 &= CTLR2_LBDL_Mask; - USARTx->CTLR2 |= USART_LINBreakDetectLength; -} - -/********************************************************************* - * @fn USART_LINCmd - * - * @brief Enables or disables the USART LIN mode. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR2 |= CTLR2_LINEN_Set; - } - else - { - USARTx->CTLR2 &= CTLR2_LINEN_Reset; - } -} - -/********************************************************************* - * @fn USART_SendData - * - * @brief Transmits single data through the USARTx peripheral. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * Data - the data to transmit. - * - * @return none - */ -void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) -{ - USARTx->DATAR = (Data & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_ReceiveData - * - * @brief Returns the most recent received data by the USARTx peripheral. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * - * @return The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef *USARTx) -{ - return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_SendBreak - * - * @brief Transmits break characters. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * - * @return none - */ -void USART_SendBreak(USART_TypeDef *USARTx) -{ - USARTx->CTLR1 |= CTLR1_SBK_Set; -} - -/********************************************************************* - * @fn USART_SetPrescaler - * - * @brief Sets the system clock prescaler. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * USART_Prescaler - specifies the prescaler clock. - * - * @return none - */ -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) -{ - USARTx->GPR &= GPR_MSB_Mask; - USARTx->GPR |= USART_Prescaler; -} - -/********************************************************************* - * @fn USART_HalfDuplexCmd - * - * @brief Enables or disables the USART Half Duplex communication. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_HDSEL_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_HDSEL_Reset; - } -} - -/********************************************************************* - * @fn USART_IrDAConfig - * - * @brief Configures the USART's IrDA interface. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * USART_IrDAMode - specifies the IrDA mode. - * USART_IrDAMode_LowPower. - * USART_IrDAMode_Normal. - * - * @return none - */ -void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) -{ - USARTx->CTLR3 &= CTLR3_IRLP_Mask; - USARTx->CTLR3 |= USART_IrDAMode; -} - -/********************************************************************* - * @fn USART_IrDACmd - * - * @brief Enables or disables the USART's IrDA interface. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_IREN_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_IREN_Reset; - } -} - -/********************************************************************* - * @fn USART_GetFlagStatus - * - * @brief Checks whether the specified USART flag is set or not. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * USART_FLAG - specifies the flag to check. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TXE - Transmit data register empty flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * USART_FLAG_IDLE - Idle Line detection flag. - * USART_FLAG_ORE - OverRun Error flag. - * USART_FLAG_NE - Noise Error flag. - * USART_FLAG_FE - Framing Error flag. - * USART_FLAG_PE - Parity Error flag. - * - * @return bitstatus: SET or RESET - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearFlag - * - * @brief Clears the USARTx's pending flags. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * USART_FLAG - specifies the flag to clear. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * Note- - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DATAR register (USART_ReceiveData()). - * - RXNE flag can be also cleared by a read to the USART_DATAR register - * (USART_ReceiveData()). - * - TC flag can be also cleared by software sequence: a read operation to - * USART_STATR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DATAR register (USART_SendData()). - * - TXE flag is cleared only by a write to the USART_DATAR register - * (USART_SendData()). - * - * @return none - */ -void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - USARTx->STATR = (uint16_t)~USART_FLAG; -} - -/********************************************************************* - * @fn USART_GetITStatus - * - * @brief Checks whether the specified USART interrupt has occurred or not. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * USART_IT - specifies the USART interrupt source to check. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Transmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. - * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. - * USART_IT_NE - Noise Error interrupt. - * USART_IT_FE - Framing Error interrupt. - * USART_IT_PE - Parity Error interrupt. - * - * @return bitstatus: SET or RESET. - */ -ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - - usartreg = (((uint8_t)USART_IT) >> 0x05); - itmask = USART_IT & IT_Mask; - itmask = (uint32_t)0x01 << itmask; - - if(usartreg == 0x01) - { - itmask &= USARTx->CTLR1; - } - else if(usartreg == 0x02) - { - itmask &= USARTx->CTLR2; - } - else - { - itmask &= USARTx->CTLR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->STATR; - - if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearITPendingBit - * - * @brief Clears the USARTx's interrupt pending bits. - * - * @param USARTx - where x can be 1 or 2 to select the USART peripheral. - * USART_IT - specifies the interrupt pending bit to clear. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * Note- - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_STATR register - * (USART_GetITStatus()) followed by a read operation to USART_DATAR register - * (USART_ReceiveData()). - * - RXNE pending bit can be also cleared by a read to the USART_DATAR register - * (USART_ReceiveData()). - * - TC pending bit can be also cleared by software sequence: a read - * operation to USART_STATR register (USART_GetITStatus()) followed by a write - * operation to USART_DATAR register (USART_SendData()). - * - TXE pending bit is cleared only by a write to the USART_DATAR register - * (USART_SendData()). - * - * @return none - */ -void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->STATR = (uint16_t)~itmask; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_usart.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file provides all the USART firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1 or 2 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART1, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART1, DISABLE); + } + if(USARTx == USART2) + { + RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART2, ENABLE); + RCC_PB2PeriphResetCmd(RCC_PB2Periph_USART2, DISABLE); + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1 or 2 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + + tmpreg = (integerdivider / 100) << 4; + + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * reset values . + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values . + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return bitstatus: SET or RESET + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DATAR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_STATR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DATAR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return bitstatus: SET or RESET. + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1 or 2 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_STATR register + * (USART_GetITStatus()) followed by a read operation to USART_DATAR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_STATR register (USART_GetITStatus()) followed by a write + * operation to USART_DATAR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_wwdg.c b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_wwdg.c index c18ec52..6341a0a 100644 --- a/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_wwdg.c +++ b/system/CH32VM00X/SRC/Peripheral/src/ch32v00X_wwdg.c @@ -1,141 +1,141 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_wwdg.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : This file provides all the WWDG firmware functions. - ********************************************************************************* - * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * Attention: This software (modified or not) and binary are used for - * microcontroller manufactured by Nanjing Qinheng Microelectronics. - *******************************************************************************/ -#include -#include - -/* CTLR register bit mask */ -#define CTLR_WDGA_Set ((uint32_t)0x00000080) - -/* CFGR register bit mask */ -#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) -#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) -#define BIT_Mask ((uint8_t)0x7F) - -/********************************************************************* - * @fn WWDG_DeInit - * - * @brief Deinitializes the WWDG peripheral registers to their default reset values - * - * @return none - */ -void WWDG_DeInit(void) -{ - RCC_PB1PeriphResetCmd(RCC_PB1Periph_WWDG, ENABLE); - RCC_PB1PeriphResetCmd(RCC_PB1Periph_WWDG, DISABLE); -} - -/********************************************************************* - * @fn WWDG_SetPrescaler - * - * @brief Sets the WWDG Prescaler - * - * @param WWDG_Prescaler - specifies the WWDG Prescaler - * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 - * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 - * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 - * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 - * - * @return none - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; - tmpreg |= WWDG_Prescaler; - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_SetWindowValue - * - * @brief Sets the WWDG window value - * - * @param WindowValue - specifies the window value to be compared to the - * downcounter,which must be lower than 0x80 - * - * @return none - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - tmpreg = WWDG->CFGR & CFGR_W_Mask; - - tmpreg |= WindowValue & (uint32_t)BIT_Mask; - - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_EnableIT - * - * @brief Enables the WWDG Early Wakeup interrupt(EWI) - * - * @return none - */ -void WWDG_EnableIT(void) -{ - WWDG->CFGR |= (1 << 9); -} - -/********************************************************************* - * @fn WWDG_SetCounter - * - * @brief Sets the WWDG counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * - * @return none - */ -void WWDG_SetCounter(uint8_t Counter) -{ - WWDG->CTLR = Counter & BIT_Mask; -} - -/********************************************************************* - * @fn WWDG_Enable - * - * @brief Enables WWDG and load the counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * @return none - */ -void WWDG_Enable(uint8_t Counter) -{ - WWDG->CTLR = CTLR_WDGA_Set | Counter; -} - -/********************************************************************* - * @fn WWDG_GetFlagStatus - * - * @brief Checks whether the Early Wakeup interrupt flag is set or not - * - * @return The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - return (FlagStatus)(WWDG->STATR); -} - -/********************************************************************* - * @fn WWDG_ClearFlag - * - * @brief Clears Early Wakeup interrupt flag - * - * @return none - */ -void WWDG_ClearFlag(void) -{ - WWDG->STATR = (uint32_t)RESET; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_wwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : This file provides all the WWDG firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_PB1PeriphResetCmd(RCC_PB1Periph_WWDG, ENABLE); + RCC_PB1PeriphResetCmd(RCC_PB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/system/CH32VM00X/SRC/Startup/startup_ch32v00X.S b/system/CH32VM00X/SRC/Startup/startup_ch32v00X.S index 4c18741..8be8d21 100644 --- a/system/CH32VM00X/SRC/Startup/startup_ch32v00X.S +++ b/system/CH32VM00X/SRC/Startup/startup_ch32v00X.S @@ -2,7 +2,7 @@ ;* File Name : startup_ch32v00X.s ;* Author : WCH ;* Version : V1.0.1 -;* Date : 2024/01/01 +;* Date : 2024/08/02 ;* Description : ch32v002-ch32v004-ch32v005-ch32v006-ch32v007-ch32m007 vector table for eclipse toolchain. ;********************************************************************************* ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -165,10 +165,6 @@ handle_reset: ori t0, t0, 3 csrw mtvec, t0 - la a0, __libc_fini_array - call atexit - call __libc_init_array - jal SystemInit la t0, main csrw mepc, t0 diff --git a/system/CH32VM00X/USER/ch32v00X_conf.h b/system/CH32VM00X/USER/ch32v00X_conf.h index 5968e3a..75f1fab 100644 --- a/system/CH32VM00X/USER/ch32v00X_conf.h +++ b/system/CH32VM00X/USER/ch32v00X_conf.h @@ -1,40 +1,40 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_conf.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : Library configuration file. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32V00X_CONF_H -#define __CH32V00X_CONF_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - - -#endif /* __CH32V00X_CONF_H */ - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : Library configuration file. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V00X_CONF_H +#define __CH32V00X_CONF_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + + +#endif /* __CH32V00X_CONF_H */ + + + + + diff --git a/system/CH32VM00X/USER/ch32v00X_it.c b/system/CH32VM00X/USER/ch32v00X_it.c index 91f92f3..af11897 100644 --- a/system/CH32VM00X/USER/ch32v00X_it.c +++ b/system/CH32VM00X/USER/ch32v00X_it.c @@ -1,45 +1,46 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v00X_it.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : Main Interrupt Service Routines. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include - -void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); - -/********************************************************************* - * @fn NMI_Handler - * - * @brief This function handles NMI exception. - * - * @return none - */ -void NMI_Handler(void) -{ - while (1) - { - } -} - -/********************************************************************* - * @fn HardFault_Handler - * - * @brief This function handles Hard Fault exception. - * - * @return none - */ -void HardFault_Handler(void) -{ - while (1) - { - } -} - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00X_it.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/04 + * Description : Main Interrupt Service Routines. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ + while (1) + { + } +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + NVIC_SystemReset(); + while (1) + { + } +} + + diff --git a/system/CH32VM00X/USER/system_ch32v00X.c b/system/CH32VM00X/USER/system_ch32v00X.c index 6169b77..acefa15 100644 --- a/system/CH32VM00X/USER/system_ch32v00X.c +++ b/system/CH32VM00X/USER/system_ch32v00X.c @@ -1,441 +1,456 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : system_ch32v00X.c - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : CH32V00X Device Peripheral Access Layer System Source File. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include - -/* -* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after -* reset the HSI is used as SYSCLK source). -* If none of the define below is enabled, the HSI is used as System clock source. -*/ - -//#define SYSCLK_FREQ_8MHz_HSI 8000000 -//#define SYSCLK_FREQ_24MHz_HSI HSI_VALUE -//#define SYSCLK_FREQ_48MHz_HSI 48000000 -//#define SYSCLK_FREQ_8MHz_HSE 8000000 -//#define SYSCLK_FREQ_24MHz_HSE HSE_VALUE -//#define SYSCLK_FREQ_48MHz_HSE 48000000 - -/* Clock Definitions */ -#ifdef SYSCLK_FREQ_8MHz_HSI - uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz_HSI - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz_HSI - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_8MHz_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ -#else - uint32_t SystemCoreClock = HSI_VALUE; -#endif - -__I uint8_t HBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; - - -/* system_private_function_proto_types */ -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_8MHz_HSI - static void SetSysClockTo_8MHz_HSI(void); -#elif defined SYSCLK_FREQ_24MHz_HSI - static void SetSysClockTo_24MHz_HSI(void); -#elif defined SYSCLK_FREQ_48MHz_HSI - static void SetSysClockTo_48MHz_HSI(void); -#elif defined SYSCLK_FREQ_8MHz_HSE - static void SetSysClockTo_8MHz_HSE(void); -#elif defined SYSCLK_FREQ_24MHz_HSE - static void SetSysClockTo_24MHz_HSE(void); -#elif defined SYSCLK_FREQ_48MHz_HSE - static void SetSysClockTo_48MHz_HSE(void); -#endif - - -/********************************************************************* - * @fn SystemInit - * - * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, - * the PLL and update the SystemCoreClock variable. - * - * @return none - */ -void SystemInit (void) -{ - uint32_t tmp = 0; - - /* Flash 2 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; - RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0x68FF0000; - - tmp = RCC->CTLR; - tmp &= (uint32_t)0xFE16FFFB; - tmp |= (uint32_t)(1<<22)|(1<<20); - RCC->CTLR = tmp; - - RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFFFEFFFF; - RCC->INTR = 0x009D0000; - - SetSysClock(); -} - - -/********************************************************************* - * @fn SystemCoreClockUpdate - * - * @brief Update SystemCoreClock variable according to Clock Register Values. - * - * @return none - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllsource = 0; - - tmp = RCC->CFGR0 & RCC_SWS; - - switch (tmp) - { - case 0x00: - SystemCoreClock = HSI_VALUE; - break; - case 0x04: - SystemCoreClock = HSE_VALUE; - break; - case 0x08: - pllsource = RCC->CFGR0 & RCC_PLLSRC; - if (pllsource == 0x00) - { - SystemCoreClock = HSI_VALUE * 2; - } - else - { - SystemCoreClock = HSE_VALUE * 2; - } - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - - tmp = HBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; - - if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8) - { - SystemCoreClock /= tmp; - } - else - { - SystemCoreClock >>= tmp; - } -} - - -/********************************************************************* - * @fn SetSysClock - * - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClock(void) -{ -RCC->PB2PCENR |= RCC_PB2Periph_GPIOD; -GPIOD->CFGLR&=(~0xF0); -GPIOD->CFGLR|=0x80; -GPIOD->BSHR =0x2; -GPIO_IPD_Unused(); -#ifdef SYSCLK_FREQ_8MHz_HSI - SetSysClockTo_8MHz_HSI(); -#elif defined SYSCLK_FREQ_24MHZ_HSI - SetSysClockTo_24MHZ_HSI(); -#elif defined SYSCLK_FREQ_48MHZ_HSI - SetSysClockTo_48MHZ_HSI(); -#elif defined SYSCLK_FREQ_8MHz_HSE - SetSysClockTo_8MHz_HSE(); -#elif defined SYSCLK_FREQ_24MHz_HSE - SetSysClockTo_24MHz_HSE(); -#elif defined SYSCLK_FREQ_48MHz_HSE - SetSysClockTo_48MHz_HSE(); -#endif - - /* If none of the define above is enabled, the HSI is used as System clock. - * source (default after reset) - */ -} - - -#ifdef SYSCLK_FREQ_8MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo_8MHz_HSI - * - * @brief Sets HSI as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo_8MHz_HSI(void) -{ - /* HCLK = SYSCLK = PB1 */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; - - /* Flash 0 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_0; -} - -#elif defined SYSCLK_FREQ_24MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo_24MHZ_HSI - * - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo_24MHz_HSI(void) -{ - /* HCLK = SYSCLK = PB1 */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - - /* Flash 1 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; -} - - -#elif defined SYSCLK_FREQ_48MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo_48MHZ_HSI - * - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo_48MHz_HSI(void) -{ - /* HCLK = SYSCLK = PB1 */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - - /* PLL configuration: PLLCLK = HSI * 2 = 48 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Mul2); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - /* Flash 2 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; -} - -#elif defined SYSCLK_FREQ_8MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo_8MHz_HSE - * - * @brief Sets System clock frequency to 8MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo_8MHz_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Close PA1-PA2 GPIO function */ - RCC->PB2PCENR |= RCC_AFIOEN; - AFIO->PCFR1 |= (1<<17); - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK = PB1 */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; - - /* Select HSE as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) - { - } - /* Flash 0 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_0; - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_24MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo_24MHz_HSE - * - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo_24MHz_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Close PA1-PA2 GPIO function */ - RCC->PB2PCENR |= RCC_AFIOEN; - AFIO->PCFR1 |= (1<<17); - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK = PB1 */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) - { - } - /* Flash 1 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_48MHz_HSE - -/********************************************************************* - * @fn SetSysClockTo_48MHz_HSE - * - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo_48MHz_HSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Close PA1-PA2 GPIO function */ - RCC->PB2PCENR |= RCC_AFIOEN; - AFIO->PCFR1 |= (1<<17); - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK = PB1 */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - - /* PLL configuration: PLLCLK = HSE * 2 = 48 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC)); - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE_Mul2); - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - /* Flash 2 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} -#endif - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v00X.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/11/04 + * Description : CH32V00X Device Peripheral Access Layer System Source File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ + +//#define SYSCLK_FREQ_8MHz_HSI 8000000 +//#define SYSCLK_FREQ_24MHz_HSI HSI_VALUE +// #define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_8MHz_HSE 8000000 +//#define SYSCLK_FREQ_24MHz_HSE HSE_VALUE +//#define SYSCLK_FREQ_48MHz_HSE 48000000 + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_8MHz_HSI + uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz_HSI + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSI + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_8MHz_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#else + uint32_t SystemCoreClock = HSI_VALUE; +#endif + +__I uint8_t HBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_8MHz_HSI + static void SetSysClockTo_8MHz_HSI(void); +#elif defined SYSCLK_FREQ_24MHz_HSI + static void SetSysClockTo_24MHz_HSI(void); +#elif defined SYSCLK_FREQ_48MHz_HSI + static void SetSysClockTo_48MHz_HSI(void); +#elif defined SYSCLK_FREQ_8MHz_HSE + static void SetSysClockTo_8MHz_HSE(void); +#elif defined SYSCLK_FREQ_24MHz_HSE + static void SetSysClockTo_24MHz_HSE(void); +#elif defined SYSCLK_FREQ_48MHz_HSE + static void SetSysClockTo_48MHz_HSE(void); +#endif + + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + uint32_t tmp = 0; + + /* Flash 2 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0x68FF0000; + + tmp = RCC->CTLR; + tmp &= (uint32_t)0xFED6FFFB; + tmp |= (uint32_t)(1<<20); + RCC->CTLR = tmp; + + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFFFEFFFF; + RCC->INTR = 0x009D0000; + + SetSysClock(); +} + + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllsource = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllsource = RCC->CFGR0 & RCC_PLLSRC; + if (pllsource == 0x00) + { + SystemCoreClock = HSI_VALUE * 2; + } + else + { + SystemCoreClock = HSE_VALUE * 2; + } + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = HBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + + if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8) + { + SystemCoreClock /= tmp; + } + else + { + SystemCoreClock >>= tmp; + } +} + + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ +RCC->PB2PCENR |= RCC_PB2Periph_GPIOD; +GPIOD->CFGLR&=(~0xF0); +GPIOD->CFGLR|=0x80; +GPIOD->BSHR =0x2; +GPIO_IPD_Unused(); +#ifdef SYSCLK_FREQ_8MHz_HSI + SetSysClockTo_8MHz_HSI(); +#elif defined SYSCLK_FREQ_24MHz_HSI + SetSysClockTo_24MHz_HSI(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo_48MHz_HSI(); +#elif defined SYSCLK_FREQ_8MHz_HSE + SetSysClockTo_8MHz_HSE(); +#elif defined SYSCLK_FREQ_24MHz_HSE + SetSysClockTo_24MHz_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo_48MHz_HSE(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock. + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_8MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo_8MHz_HSI + * + * @brief Sets HSI as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_8MHz_HSI(void) +{ + /* HCLK = SYSCLK = PB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; + + /* Flash 0 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_0; +} + +#elif defined SYSCLK_FREQ_24MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo_24MHz_HSI + * + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_24MHz_HSI(void) +{ + /* HCLK = SYSCLK = PB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; +} + + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo_48MHz_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_48MHz_HSI(void) +{ + /* HCLK = SYSCLK = PB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + + /* PLL configuration: PLLCLK = HSI * 2 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Mul2); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + /* Flash 2 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; +} + +#elif defined SYSCLK_FREQ_8MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo_8MHz_HSE + * + * @brief Sets System clock frequency to 8MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_8MHz_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Close PA1-PA2 GPIO function */ + RCC->PB2PCENR |= RCC_AFIOEN; + AFIO->PCFR1 |= (1<<17); + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK = PB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + /* Flash 0 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_0; + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + /* Open PA1-PA2 GPIO function */ + AFIO->PCFR1 &= ~(1<<17); + RCC->PB2PCENR &= ~RCC_AFIOEN; + + RCC->CTLR &= ((uint32_t)~RCC_HSEON); + } +} + +#elif defined SYSCLK_FREQ_24MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo_24MHz_HSE + * + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_24MHz_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Close PA1-PA2 GPIO function */ + RCC->PB2PCENR |= RCC_AFIOEN; + AFIO->PCFR1 |= (1<<17); + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK = PB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + /* Open PA1-PA2 GPIO function */ + AFIO->PCFR1 &= ~(1<<17); + RCC->PB2PCENR &= ~RCC_AFIOEN; + + RCC->CTLR &= ((uint32_t)~RCC_HSEON); + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo_48MHz_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_48MHz_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Close PA1-PA2 GPIO function */ + RCC->PB2PCENR |= RCC_AFIOEN; + AFIO->PCFR1 |= (1<<17); + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK = PB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + + /* PLL configuration: PLLCLK = HSE * 2 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE_Mul2); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + /* Flash 2 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_2; + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + /* Open PA1-PA2 GPIO function */ + AFIO->PCFR1 &= ~(1<<17); + RCC->PB2PCENR &= ~RCC_AFIOEN; + + RCC->CTLR &= ((uint32_t)~RCC_HSEON); + } +} +#endif + + + + diff --git a/system/CH32VM00X/USER/system_ch32v00X.h b/system/CH32VM00X/USER/system_ch32v00X.h index f98af4f..ef41ef0 100644 --- a/system/CH32VM00X/USER/system_ch32v00X.h +++ b/system/CH32VM00X/USER/system_ch32v00X.h @@ -1,32 +1,32 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : system_ch32v00X.h - * Author : WCH - * Version : V1.0.0 - * Date : 2024/01/01 - * Description : CH32V00X Device Peripheral Access Layer System Header File. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __SYSTEM_CH32V00X_H -#define __SYSTEM_CH32V00X_H - -#ifdef __cplusplus - extern "C" { -#endif - -extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ - -/* System_Exported_Functions */ -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V00X_SYSTEM_H */ - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v00X.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/01 + * Description : CH32V00X Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_CH32V00X_H +#define __SYSTEM_CH32V00X_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00X_SYSTEM_H */ + + + diff --git a/system/CH32X035/SRC/Core/core_riscv.c b/system/CH32X035/SRC/Core/core_riscv.c index 46395d2..7d1e06d 100644 --- a/system/CH32X035/SRC/Core/core_riscv.c +++ b/system/CH32X035/SRC/Core/core_riscv.c @@ -1,307 +1,307 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : core_riscv.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : RISC-V Core Peripheral Access Layer Source File -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - - -/********************************************************************* - * @fn __get_MSTATUS - * - * @brief Return the Machine Status Register - * - * @return mstatus value - */ -uint32_t __get_MSTATUS(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MSTATUS - * - * @brief Set the Machine Status Register - * - * @param value - set mstatus value - * - * @return none - */ -void __set_MSTATUS(uint32_t value) -{ - __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MISA - * - * @brief Return the Machine ISA Register - * - * @return misa value - */ -uint32_t __get_MISA(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MISA - * - * @brief Set the Machine ISA Register - * - * @param value - set misa value - * - * @return none - */ -void __set_MISA(uint32_t value) -{ - __ASM volatile ("csrw misa, %0" : : "r" (value) ); -} - - -/********************************************************************* - * @fn __get_MTVEC - * - * @brief Return the Machine Trap-Vector Base-Address Register - * - * @return mtvec value - */ -uint32_t __get_MTVEC(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MTVEC - * - * @brief Set the Machine Trap-Vector Base-Address Register - * - * @param value - set mtvec value - * - * @return none - */ -void __set_MTVEC(uint32_t value) -{ - __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MSCRATCH - * - * @brief Return the Machine Seratch Register - * - * @return mscratch value - */ -uint32_t __get_MSCRATCH(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MSCRATCH - * - * @brief Set the Machine Seratch Register - * - * @param value - set mscratch value - * - * @return none - */ -void __set_MSCRATCH(uint32_t value) -{ - __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MEPC - * - * @brief Return the Machine Exception Program Register - * - * @return mepc value - */ -uint32_t __get_MEPC(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Exception Program Register - * - * @return mepc value - */ -void __set_MEPC(uint32_t value) -{ - __ASM volatile ("csrw mepc, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MCAUSE - * - * @brief Return the Machine Cause Register - * - * @return mcause value - */ -uint32_t __get_MCAUSE(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Cause Register - * - * @return mcause value - */ -void __set_MCAUSE(uint32_t value) -{ - __ASM volatile ("csrw mcause, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MTVAL - * - * @brief Return the Machine Trap Value Register - * - * @return mtval value - */ -uint32_t __get_MTVAL(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MTVAL - * - * @brief Set the Machine Trap Value Register - * - * @return mtval value - */ -void __set_MTVAL(uint32_t value) -{ - __ASM volatile ("csrw mtval, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MVENDORID - * - * @brief Return Vendor ID Register - * - * @return mvendorid value - */ -uint32_t __get_MVENDORID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_MARCHID - * - * @brief Return Machine Architecture ID Register - * - * @return marchid value - */ -uint32_t __get_MARCHID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_MIMPID - * - * @brief Return Machine Implementation ID Register - * - * @return mimpid value - */ -uint32_t __get_MIMPID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_MHARTID - * - * @brief Return Hart ID Register - * - * @return mhartid value - */ -uint32_t __get_MHARTID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_SP - * - * @brief Return SP Register - * - * @return SP value - */ -uint32_t __get_SP(void) -{ - uint32_t result; - - __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); - return (result); -} - +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.c + * Author : WCH + * Version : V1.0.1 + * Date : 2023/11/11 + * Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32X035 +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /* asm keyword for ARM Compiler */ + #define __INLINE __inline /* inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /* asm keyword for IAR Compiler */ + #define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /* asm keyword for GNU Compiler */ + #define __INLINE inline /* inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /* asm keyword for TASKING Compiler */ + #define __INLINE inline /* inline keyword for TASKING Compiler */ + +#endif + + + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile ("csrw misa, %0" : : "r" (value) ); +} + + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile ("csrw mepc, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile ("csrw mcause, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile ("csrw mtval, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); + return (result); +} + diff --git a/system/CH32X035/SRC/Core/core_riscv.h b/system/CH32X035/SRC/Core/core_riscv.h index d519740..4172102 100644 --- a/system/CH32X035/SRC/Core/core_riscv.h +++ b/system/CH32X035/SRC/Core/core_riscv.h @@ -1,569 +1,585 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : core_riscv.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : RISC-V Core Peripheral Access Layer Header File for CH32X035 -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CORE_RISCV_H__ -#define __CORE_RISCV_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* IO definitions */ -#ifdef __cplusplus - #define __I volatile /* defines 'read only' permissions */ -#else - #define __I volatile const /* defines 'read only' permissions */ -#endif -#define __O volatile /* defines 'write only' permissions */ -#define __IO volatile /* defines 'read / write' permissions */ - -/* Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef __I uint64_t vuc64; /* Read Only */ -typedef __I uint32_t vuc32; /* Read Only */ -typedef __I uint16_t vuc16; /* Read Only */ -typedef __I uint8_t vuc8; /* Read Only */ - -typedef const uint64_t uc64; /* Read Only */ -typedef const uint32_t uc32; /* Read Only */ -typedef const uint16_t uc16; /* Read Only */ -typedef const uint8_t uc8; /* Read Only */ - -typedef __I int64_t vsc64; /* Read Only */ -typedef __I int32_t vsc32; /* Read Only */ -typedef __I int16_t vsc16; /* Read Only */ -typedef __I int8_t vsc8; /* Read Only */ - -typedef const int64_t sc64; /* Read Only */ -typedef const int32_t sc32; /* Read Only */ -typedef const int16_t sc16; /* Read Only */ -typedef const int8_t sc8; /* Read Only */ - -typedef __IO uint64_t vu64; -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef uint64_t u64; -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef __IO int64_t vs64; -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef int64_t s64; -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -#define RV_STATIC_INLINE static inline - -/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ -typedef struct{ - __I uint32_t ISR[8]; - __I uint32_t IPR[8]; - __IO uint32_t ITHRESDR; - __IO uint32_t RESERVED; - __IO uint32_t CFGR; - __I uint32_t GISR; - __IO uint8_t VTFIDR[4]; - uint8_t RESERVED0[12]; - __IO uint32_t VTFADDR[4]; - uint8_t RESERVED1[0x90]; - __O uint32_t IENR[8]; - uint8_t RESERVED2[0x60]; - __O uint32_t IRER[8]; - uint8_t RESERVED3[0x60]; - __O uint32_t IPSR[8]; - uint8_t RESERVED4[0x60]; - __O uint32_t IPRR[8]; - uint8_t RESERVED5[0x60]; - __IO uint32_t IACTR[8]; - uint8_t RESERVED6[0xE0]; - __IO uint8_t IPRIOR[256]; - uint8_t RESERVED7[0x810]; - __IO uint32_t SCTLR; -}PFIC_Type; - -/* memory mapped structure for SysTick */ -typedef struct -{ - __IO u32 CTLR; - __IO u32 SR; - __IO u64 CNT; - __IO u64 CMP; -}SysTick_Type; - - -#define PFIC ((PFIC_Type *) 0xE000E000 ) -#define NVIC PFIC -#define NVIC_KEY1 ((uint32_t)0xFA050000) -#define NVIC_KEY2 ((uint32_t)0xBCAF0000) -#define NVIC_KEY3 ((uint32_t)0xBEEF0000) -#define SysTick ((SysTick_Type *) 0xE000F000) - - -/********************************************************************* - * @fn __enable_irq - * - * @brief Enable Global Interrupt - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() -{ - __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) ); -} - -/********************************************************************* - * @fn __disable_irq - * - * @brief Disable Global Interrupt - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() -{ - __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) ); -} - -/********************************************************************* - * @fn __NOP - * - * @brief nop - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() -{ - __asm volatile ("nop"); -} - -/********************************************************************* - * @fn NVIC_EnableIRQ - * - * @brief Enable Interrupt - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_DisableIRQ - * - * @brief Disable Interrupt - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_GetStatusIRQ - * - * @brief Get Interrupt Enable State - * - * @param IRQn - Interrupt Numbers - * - * @return 1 - Interrupt Pending Enable - * 0 - Interrupt Pending Disable - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_GetPendingIRQ - * - * @brief Get Interrupt Pending State - * - * @param IRQn - Interrupt Numbers - * - * @return 1 - Interrupt Pending Enable - * 0 - Interrupt Pending Disable - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_SetPendingIRQ - * - * @brief Set Interrupt Pending - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_ClearPendingIRQ - * - * @brief Clear Interrupt Pending - * - * @param IRQn - Interrupt Numbers - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - -/********************************************************************* - * @fn NVIC_GetActive - * - * @brief Get Interrupt Active State - * - * @param IRQn - Interrupt Numbers - * - * @return 1 - Interrupt Active - * 0 - Interrupt No Active - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - -/********************************************************************* - * @fn NVIC_SetPriority - * - * @brief Set Interrupt Priority - * - * @param IRQn - Interrupt Numbers - * priority: bit7 - pre-emption priority - * bit6-bit5 - subpriority - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) -{ - NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; -} - -/********************************************************************* - * @fn __WFI - * - * @brief Wait for Interrupt - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) -{ - NVIC->SCTLR &= ~(1<<3); // wfi - asm volatile ("wfi"); -} - -/********************************************************************* - * @fn _SEV - * - * @brief Set Event - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) -{ - uint32_t t; - - t = NVIC->SCTLR; - NVIC->SCTLR |= (1<<3)|(1<<5); - NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); -} - -/********************************************************************* - * @fn _WFE - * - * @brief Wait for Events - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) -{ - NVIC->SCTLR |= (1<<3); - asm volatile ("wfi"); -} - -/********************************************************************* - * @fn __WFE - * - * @brief Wait for Events - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) -{ - _SEV(); - _WFE(); - _WFE(); -} - -/********************************************************************* - * @fn SetVTFIRQ - * - * @brief Set VTF Interrupt - * - * @param addr - VTF interrupt service function base address. - * IRQn - Interrupt Numbers - * num - VTF Interrupt Numbers - * NewState - DISABLE or ENABLE - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ - if(num > 3) return ; - - if (NewState != DISABLE) - { - NVIC->VTFIDR[num] = IRQn; - NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); - } - else{ - NVIC->VTFIDR[num] = IRQn; - NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); - } -} - -/********************************************************************* - * @fn NVIC_SystemReset - * - * @brief Initiate a system reset request - * - * @return none - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) -{ - NVIC->CFGR = NVIC_KEY3|(1<<7); -} - -/********************************************************************* - * @fn __AMOADD_W - * - * @brief Atomic Add with 32bit value - * Atomically ADD 32bit value with value in memory using amoadd.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be ADDed - * - * @return return memory value + add value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amoadd.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOAND_W - * - * @brief Atomic And with 32bit value - * Atomically AND 32bit value with value in memory using amoand.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be ANDed - * - * @return return memory value & and value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amoand.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOMAX_W - * - * @brief Atomic signed MAX with 32bit value - * @details Atomically signed max compare 32bit value with value in memory using amomax.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared - * - * @return the bigger value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amomax.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOMAXU_W - * - * @brief Atomic unsigned MAX with 32bit value - * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared - * - * @return return the bigger value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) -{ - uint32_t result; - - __asm volatile ("amomaxu.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOMIN_W - * - * @brief Atomic signed MIN with 32bit value - * Atomically signed min compare 32bit value with value in memory using amomin.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared - * - * @return the smaller value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amomin.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOMINU_W - * - * @brief Atomic unsigned MIN with 32bit value - * Atomically unsigned min compare 32bit value with value in memory using amominu.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be compared - * - * @return the smaller value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) -{ - uint32_t result; - - __asm volatile ("amominu.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOOR_W - * - * @brief Atomic OR with 32bit value - * @details Atomically OR 32bit value with value in memory using amoor.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be ORed - * - * @return return memory value | and value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amoor.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/********************************************************************* - * @fn __AMOSWAP_W - * - * @brief Atomically swap new 32bit value into memory using amoswap.d. - * addr - Address pointer to data, address need to be 4byte aligned - * newval - New value to be stored into the address - * - * @return return the original value in memory - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) -{ - uint32_t result; - - __asm volatile ("amoswap.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); - return result; -} - -/********************************************************************* - * @fn __AMOXOR_W - * - * @brief Atomic XOR with 32bit value - * @details Atomically XOR 32bit value with value in memory using amoxor.d. - * addr - Address pointer to data, address need to be 4byte aligned - * value - value to be XORed - * - * @return return memory value ^ and value - */ -__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) -{ - int32_t result; - - __asm volatile ("amoxor.w %0, %2, %1" : \ - "=r"(result), "+A"(*addr) : "r"(value) : "memory"); - return *addr; -} - -/* Core_Exported_Functions */ -extern uint32_t __get_MSTATUS(void); -extern void __set_MSTATUS(uint32_t value); -extern uint32_t __get_MISA(void); -extern void __set_MISA(uint32_t value); -extern uint32_t __get_MTVEC(void); -extern void __set_MTVEC(uint32_t value); -extern uint32_t __get_MSCRATCH(void); -extern void __set_MSCRATCH(uint32_t value); -extern uint32_t __get_MEPC(void); -extern void __set_MEPC(uint32_t value); -extern uint32_t __get_MCAUSE(void); -extern void __set_MCAUSE(uint32_t value); -extern uint32_t __get_MTVAL(void); -extern void __set_MTVAL(uint32_t value); -extern uint32_t __get_MVENDORID(void); -extern uint32_t __get_MARCHID(void); -extern uint32_t __get_MIMPID(void); -extern uint32_t __get_MHARTID(void); -extern uint32_t __get_SP(void); - -#ifdef __cplusplus -} -#endif - -#endif - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.h + * Author : WCH + * Version : V1.0.1 + * Date : 2023/12/26 + * Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32X035 +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint64_t vuc64; /* Read Only */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint64_t uc64; /* Read Only */ +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int64_t vsc64; /* Read Only */ +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int64_t sc64; /* Read Only */ +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint64_t vu64; +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int64_t vs64; +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int64_t s64; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + __IO uint64_t CMP; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000 ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) +#define SysTick ((SysTick_Type *) 0xE000F000) + + +/********************************************************************* + * @fn __enable_irq + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrs 0x800, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __disable_irq + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrc 0x800, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + uint32_t t; + + t = NVIC->SCTLR; + NVIC->SCTLR |= (1<<3)|(1<<5); + NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + NVIC->SCTLR |= (1<<3); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param addr - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState) +{ + if(num > 3) return ; + + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + +/********************************************************************* + * @fn __AMOADD_W + * + * @brief Atomic Add with 32bit value + * Atomically ADD 32bit value with value in memory using amoadd.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ADDed + * + * @return return memory value + add value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoadd.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOAND_W + * + * @brief Atomic And with 32bit value + * Atomically AND 32bit value with value in memory using amoand.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ANDed + * + * @return return memory value & and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoand.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAX_W + * + * @brief Atomic signed MAX with 32bit value + * Atomically signed max compare 32bit value with value in memory using amomax.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomax.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAXU_W + * + * @brief Atomic unsigned MAX with 32bit value + * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amomaxu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMIN_W + * + * @brief Atomic signed MIN with 32bit value + * Atomically signed min compare 32bit value with value in memory using amomin.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomin.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMINU_W + * + * @brief Atomic unsigned MIN with 32bit value + * Atomically unsigned min compare 32bit value with value in memory using amominu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amominu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOOR_W + * + * @brief Atomic OR with 32bit value + * Atomically OR 32bit value with value in memory using amoor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ORed + * + * @return return memory value | and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOSWAP_W + * + * @brief Atomically swap new 32bit value into memory using amoswap.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * newval - New value to be stored into the address + * + * @return return the original value in memory + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) +{ + uint32_t result; + + __asm volatile ("amoswap.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); + return result; +} + +/********************************************************************* + * @fn __AMOXOR_W + * + * @brief Atomic XOR with 32bit value + * Atomically XOR 32bit value with value in memory using amoxor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be XORed + * + * @return return memory value ^ and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoxor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/* Core_Exported_Functions */ +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MTVAL(void); +extern void __set_MTVAL(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/system/CH32X035/SRC/Debug/debug.c b/system/CH32X035/SRC/Debug/debug.c index a223d15..52adcca 100644 --- a/system/CH32X035/SRC/Debug/debug.c +++ b/system/CH32X035/SRC/Debug/debug.c @@ -14,6 +14,10 @@ static uint8_t p_us = 0; static uint16_t p_ms = 0; + +#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE0000380) +#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE0000384) + /********************************************************************* * @fn Delay_Init * @@ -139,6 +143,22 @@ void USART_Printf_Init(uint32_t baudrate) #endif } +/********************************************************************* + * @fn SDI_Printf_Enable + * + * @brief Initializes the SDI printf Function. + * + * @param None + * + * @return None + */ +void SDI_Printf_Enable(void) +{ + *(DEBUG_DATA0_ADDRESS) = 0; + Delay_Init(); + Delay_Ms(1); +} + /********************************************************************* * @fn _write * @@ -153,8 +173,45 @@ void USART_Printf_Init(uint32_t baudrate) __attribute__((used)) int _write(int fd, char *buf, int size) { - int i; + int i = 0; + +#if (SDI_PRINT == SDI_PR_OPEN) + int writeSize = size; + do + { + + /** + * data0 data1 ��8���ֽ� + * data0���λ���ֽڴ�ų��ȣ����Ϊ 7 + * + */ + + while( (*(DEBUG_DATA0_ADDRESS) != 0u)) + { + + } + + if(writeSize>7) + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + i += 7; + writeSize -= 7; + } + else + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + writeSize = 0; + } + + } while (writeSize); + + +#else for(i = 0; i < size; i++){ #if(DEBUG == DEBUG_UART1) while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); @@ -167,7 +224,7 @@ int _write(int fd, char *buf, int size) USART_SendData(USART3, *buf++); #endif } - +#endif return size; } #endif @@ -192,5 +249,6 @@ void *_sbrk(ptrdiff_t incr) curbrk += incr; return curbrk - incr; } + void _fini() {} -void _init() {} \ No newline at end of file +void _init() {} diff --git a/system/CH32X035/SRC/Debug/debug.h b/system/CH32X035/SRC/Debug/debug.h index e1abcb0..e2b6062 100644 --- a/system/CH32X035/SRC/Debug/debug.h +++ b/system/CH32X035/SRC/Debug/debug.h @@ -1,48 +1,57 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : debug.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for UART - * Printf , Delay functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __DEBUG_H -#define __DEBUG_H - -#include "stdio.h" -#include "ch32x035.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* UART Printf Definition */ -#define DEBUG_UART1 1 -#define DEBUG_UART2 2 -#define DEBUG_UART3 3 - -/* DEBUG UATR Definition */ -#ifndef DEBUG -#define DEBUG DEBUG_UART1 -#endif - -void Delay_Init(void); -void Delay_Us(uint32_t n); -void Delay_Ms(uint32_t n); -void USART_Printf_Init(uint32_t baudrate); - -#if(DEBUG) - #define PRINT(format, ...) printf(format, ##__VA_ARGS__) -#else - #define PRINT(X...) -#endif - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __DEBUG_H +#define __DEBUG_H + +#include "stdio.h" +#include "ch32x035.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* UART Printf Definition */ +#define DEBUG_UART1 1 +#define DEBUG_UART2 2 +#define DEBUG_UART3 3 + +/* DEBUG UATR Definition */ +#ifndef DEBUG +#define DEBUG DEBUG_UART1 +#endif + +/* SDI Printf Definition */ +#define SDI_PR_CLOSE 0 +#define SDI_PR_OPEN 1 + +#ifndef SDI_PRINT +#define SDI_PRINT SDI_PR_CLOSE +#endif + +void Delay_Init(void); +void Delay_Us(uint32_t n); +void Delay_Ms(uint32_t n); +void USART_Printf_Init(uint32_t baudrate); +void SDI_Printf_Enable(void); + +#if(DEBUG) + #define PRINT(format, ...) printf(format, ##__VA_ARGS__) +#else + #define PRINT(X...) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/PIOC_SFR.h b/system/CH32X035/SRC/Peripheral/inc/PIOC_SFR.h new file mode 100644 index 0000000..0d4cc4f --- /dev/null +++ b/system/CH32X035/SRC/Peripheral/inc/PIOC_SFR.h @@ -0,0 +1,266 @@ +/* Define for PIOC */ +/* Website: http://wch.cn */ +/* Email: tech@wch.cn */ +/* Author: W.ch 2022.08 */ +/* V1.0 SpecialFunctionRegister */ + +// __PIOC_SFR_H__ + +#ifndef __PIOC_SFR_H__ +#define __PIOC_SFR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +// Register Bit Attribute / Bit Access Type +// RO: Read Only (internal change) +// RW: Read / Write +// Attribute: master/PIOC + +/* Register name rule: + R32_* for 32 bits register (UINT32,ULONG) + R16_* for 16 bits register (UINT16,USHORT) + R8_* for 8 bits register (UINT8,UCHAR) + RB_* for bit or bit mask of 8 bit register */ + +/* ********************************************************************************************************************* */ + +#define PIOC_SRAM_BASE (SRAM_BASE+0x4000) // PIOC code RAM base address + +#define PIOC_SFR_BASE PIOC_BASE // PIOC SFR base address + +#define R32_PIOC_SFR (*((volatile unsigned long *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC SFR + +#define R8_INDIR_ADDR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC indirect address + +#define R8_TMR0_COUNT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x05))) // RO/RW, PIOC timer count + +#define R8_TMR0_CTRL (*((volatile unsigned char *)(PIOC_SFR_BASE+0x06))) // RO/RW, PIOC timer control and GP bit +#define RB_EN_LEVEL1 0x80 // RO/RW, enable IO1 level change to wakeup & action interrupt flag +#define RB_EN_LEVEL0 0x40 // RO/RW, enable IO0 level change to wakeup & action interrupt flag +#define RB_GP_BIT_Y 0x20 // RO/RW, general-purpose bit 1, reset by power on, no effect if system reset or RB_MST_RESET reset +#define RB_GP_BIT_X 0x10 // RO/RW, general-purpose bit 0, reset by power on, no effect if system reset or RB_MST_RESET reset +#define RB_TMR0_MODE 0x08 // RO/RW, timer mode: 0-timer, 1-PWM +#define RB_TMR0_FREQ2 0x04 // RO/RW, timer clock frequency selection 2 +#define RB_TMR0_FREQ1 0x02 // RO/RW, timer clock frequency selection 1 +#define RB_TMR0_FREQ0 0x01 // RO/RW, timer clock frequency selection 0 + +#define R8_TMR0_INIT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x07))) // RO/RW, PIOC timer initial value + + +#define R32_PORT_CFG (*((volatile unsigned long *)(PIOC_SFR_BASE+0x08))) // RO/RW, port status and config + +#define R8_BIT_CYCLE (*((volatile unsigned char *)(PIOC_SFR_BASE+0x08))) // RO/RW, encode bit cycle +#define RB_BIT_TX_O0 0x80 // RO/RW, bit data for IO0 port encode output +#define RB_BIT_CYCLE 0x7F // RO/RW, IO0 port bit data cycle -1 + +#define R8_INDIR_ADDR2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x09))) // RO/RW, PIOC indirect address 2 + +#define R8_PORT_DIR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0A))) // RO/RW, IO port direction and mode +//#define RB_PORT_MOD3 0x80 // RO/RW, IO port mode 3 +//#define RB_PORT_MOD2 0x40 // RO/RW, IO port mode 2 +//#define RB_PORT_MOD1 0x20 // RO/RW, IO port mode 1 +//#define RB_PORT_MOD0 0x10 // RO/RW, IO port mode 0 +//#define RB_PORT_PU1 0x08 // RO/RW, IO1 port pullup enable +//#define RB_PORT_PU0 0x04 // RO/RW, IO0 port pullup enable +#define RB_PORT_DIR1 0x02 // RO/RW, IO1 port direction +#define RB_PORT_DIR0 0x01 // RO/RW, IO0 port direction + +#define R8_PORT_IO (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0B))) // RO/RW, IO port input and output +#define RB_PORT_IN_XOR 0x80 // RO/RO, IO0 XOR IO1 port input +#define RB_BIT_RX_I0 0x40 // RO/RO, decoced bit data for IO0 port received +#define RB_PORT_IN1 0x20 // RO/RO, IO1 port input +#define RB_PORT_IN0 0x10 // RO/RO, IO0 port input +#define RB_PORT_XOR1 0x08 // RO/RO, IO1 port output XOR input +#define RB_PORT_XOR0 0x04 // RO/RO, IO0 port output XOR input +#define RB_PORT_OUT1 0x02 // RO/RW, IO1 port output +#define RB_PORT_OUT0 0x01 // RO/RW, IO0 port output + + +#define R32_DATA_CTRL (*((volatile unsigned long *)(PIOC_SFR_BASE+0x1C))) // RW/RW, data control + +#define R8_SYS_CFG (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1C))) // RW/RW, port config +#define RB_INT_REQ 0x80 // RO/RW, PIOC interrupt request action, set 1/0 by PIOC, clear 0 by master write R8_CTRL_RD (no effect) +#define RB_DATA_SW_MR 0x40 // RO/RO, R8_CTRL_RD wait for read status, set 1 by PIOC write R8_CTRL_RD, clear 0 by master read R8_CTRL_RD +#define RB_DATA_MW_SR 0x20 // RO/RO, R8_CTRL_WR wait for read status, set 1 by master write R8_CTRL_WR, clear 0 by PIOC read R8_CTRL_WR +#define RB_MST_CFG_B4 0x10 // RW/RO, config inform bit, default 0 +#define RB_MST_IO_EN1 0x08 // RW/RO, IO1 switch enable, default 0 +#define RB_MST_IO_EN0 0x04 // RW/RO, IO0 switch enable, default 0 +#define RB_MST_RESET 0x02 // RW/RO, force PIOC reset, high action, default 0 +#define RB_MST_CLK_GATE 0x01 // RW/RO, PIOC global clock enable, high action, default 0 + +#define R8_CTRL_RD (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1D))) // RO/RW, data for master read only and PIOC write only + +#define R8_CTRL_WR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1E))) // RW/RO, data for master write only and PIOC read only + +#define R8_DATA_EXCH (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1F))) // RW/RW, data exchange + + +#define R32_DATA_REG0_3 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0~3 +#define R8_DATA_REG0 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0 +#define R8_DATA_REG1 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x21))) // RW/RW, data buffer 1 +#define R8_DATA_REG2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x22))) // RW/RW, data buffer 2 +#define R8_DATA_REG3 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x23))) // RW/RW, data buffer 3 + +#define R32_DATA_REG4_7 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4~7 +#define R8_DATA_REG4 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4 +#define R8_DATA_REG5 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x25))) // RW/RW, data buffer 5 +#define R8_DATA_REG6 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x26))) // RW/RW, data buffer 6 +#define R8_DATA_REG7 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x27))) // RW/RW, data buffer 7 + +#define R32_DATA_REG8_11 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8~11 +#define R8_DATA_REG8 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8 +#define R8_DATA_REG9 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x29))) // RW/RW, data buffer 9 +#define R8_DATA_REG10 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2A))) // RW/RW, data buffer 10 +#define R8_DATA_REG11 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2B))) // RW/RW, data buffer 11 + +#define R32_DATA_REG12_15 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12~15 +#define R8_DATA_REG12 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12 +#define R8_DATA_REG13 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2D))) // RW/RW, data buffer 13 +#define R8_DATA_REG14 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2E))) // RW/RW, data buffer 14 +#define R8_DATA_REG15 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2F))) // RW/RW, data buffer 15 + +#define R32_DATA_REG16_19 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16~19 +#define R8_DATA_REG16 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16 +#define R8_DATA_REG17 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x31))) // RW/RW, data buffer 17 +#define R8_DATA_REG18 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x32))) // RW/RW, data buffer 18 +#define R8_DATA_REG19 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x33))) // RW/RW, data buffer 19 + +#define R32_DATA_REG20_23 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20~23 +#define R8_DATA_REG20 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20 +#define R8_DATA_REG21 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x35))) // RW/RW, data buffer 21 +#define R8_DATA_REG22 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x36))) // RW/RW, data buffer 22 +#define R8_DATA_REG23 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x37))) // RW/RW, data buffer 23 + +#define R32_DATA_REG24_27 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24~27 +#define R8_DATA_REG24 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24 +#define R8_DATA_REG25 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x39))) // RW/RW, data buffer 25 +#define R8_DATA_REG26 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3A))) // RW/RW, data buffer 26 +#define R8_DATA_REG27 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3B))) // RW/RW, data buffer 27 + +#define R32_DATA_REG28_31 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28~31 +#define R8_DATA_REG28 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28 +#define R8_DATA_REG29 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3D))) // RW/RW, data buffer 29 +#define R8_DATA_REG30 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3E))) // RW/RW, data buffer 30 +#define R8_DATA_REG31 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3F))) // RW/RW, data buffer 31 + +/* ******************************************************************************************************* */ + +/* PIOC Registers */ +typedef struct +{ + uint32_t RESERVED00; + union { + __IO uint32_t D32_PIOC_SFR ; // RO/RW, PIOC SFR + struct { + __IO uint8_t D8_INDIR_ADDR; // RO/RW, PIOC indirect address + __IO uint8_t D8_TMR0_COUNT; // RO/RW, PIOC timer count + __IO uint8_t D8_TMR0_CTRL; // RO/RW, PIOC timer control and GP bit + __IO uint8_t D8_TMR0_INIT; // RO/RW, PIOC timer initial value + } ; + } ; + union { + __IO uint32_t D32_PORT_CFG ; // RO/RW, port status and config + struct { + __IO uint8_t D8_BIT_CYCLE; // RO/RW, encode bit cycle + __IO uint8_t D8_INDIR_ADDR2; // RO/RW, PIOC indirect address 2 + __IO uint8_t D8_PORT_DIR; // RO/RW, IO port direction and mode + __IO uint8_t D8_PORT_IO; // RO/RW, IO port input and output + } ; + } ; + uint32_t RESERVED0C; + uint32_t RESERVED10; + uint32_t RESERVED14; + uint32_t RESERVED18; + union { + __IO uint32_t D32_DATA_CTRL ; // RW/RW, data control + struct { + __IO uint8_t D8_SYS_CFG; // RW/RW, port config + __IO uint8_t D8_CTRL_RD; // RO/RW, data for master read only and PIOC write only + __IO uint8_t D8_CTRL_WR; // RW/RO, data for master write only and PIOC read only + __IO uint8_t D8_DATA_EXCH; // RW/RW, data exchange + } ; + } ; + union { + __IO uint32_t D32_DATA_REG0_3 ; // RW/RW, data buffer 0~3 + struct { + __IO uint8_t D8_DATA_REG0; // RW/RW, data buffer 0 + __IO uint8_t D8_DATA_REG1; // RW/RW, data buffer 1 + __IO uint8_t D8_DATA_REG2; // RW/RW, data buffer 2 + __IO uint8_t D8_DATA_REG3; // RW/RW, data buffer 3 + } ; + __IO uint16_t D16_DATA_REG0_1 ; // RW/RW, data buffer 0~1 + } ; + union { + __IO uint32_t D32_DATA_REG4_7 ; // RW/RW, data buffer 4~7 + struct { + __IO uint8_t D8_DATA_REG4; // RW/RW, data buffer 4 + __IO uint8_t D8_DATA_REG5; // RW/RW, data buffer 5 + __IO uint8_t D8_DATA_REG6; // RW/RW, data buffer 6 + __IO uint8_t D8_DATA_REG7; // RW/RW, data buffer 7 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG8_11 ; // RW/RW, data buffer 8~11 + struct { + __IO uint8_t D8_DATA_REG8; // RW/RW, data buffer 8 + __IO uint8_t D8_DATA_REG9; // RW/RW, data buffer 9 + __IO uint8_t D8_DATA_REG10; // RW/RW, data buffer 10 + __IO uint8_t D8_DATA_REG11; // RW/RW, data buffer 11 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG12_15 ; // RW/RW, data buffer 12~15 + struct { + __IO uint8_t D8_DATA_REG12; // RW/RW, data buffer 12 + __IO uint8_t D8_DATA_REG13; // RW/RW, data buffer 13 + __IO uint8_t D8_DATA_REG14; // RW/RW, data buffer 14 + __IO uint8_t D8_DATA_REG15; // RW/RW, data buffer 15 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG16_19 ; // RW/RW, data buffer 16~19 + struct { + __IO uint8_t D8_DATA_REG16; // RW/RW, data buffer 16 + __IO uint8_t D8_DATA_REG17; // RW/RW, data buffer 17 + __IO uint8_t D8_DATA_REG18; // RW/RW, data buffer 18 + __IO uint8_t D8_DATA_REG19; // RW/RW, data buffer 19 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG20_23 ; // RW/RW, data buffer 20~23 + struct { + __IO uint8_t D8_DATA_REG20; // RW/RW, data buffer 20 + __IO uint8_t D8_DATA_REG21; // RW/RW, data buffer 21 + __IO uint8_t D8_DATA_REG22; // RW/RW, data buffer 22 + __IO uint8_t D8_DATA_REG23; // RW/RW, data buffer 23 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG24_27 ; // RW/RW, data buffer 24~27 + struct { + __IO uint8_t D8_DATA_REG24; // RW/RW, data buffer 24 + __IO uint8_t D8_DATA_REG25; // RW/RW, data buffer 25 + __IO uint8_t D8_DATA_REG26; // RW/RW, data buffer 26 + __IO uint8_t D8_DATA_REG27; // RW/RW, data buffer 27 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG28_31 ; // RW/RW, data buffer 28~31 + struct { + __IO uint8_t D8_DATA_REG28; // RW/RW, data buffer 28 + __IO uint8_t D8_DATA_REG29; // RW/RW, data buffer 29 + __IO uint8_t D8_DATA_REG30; // RW/RW, data buffer 30 + __IO uint8_t D8_DATA_REG31; // RW/RW, data buffer 31 + } ; + } ; +} PIOC_TypeDef; + +#define PIOC ((PIOC_TypeDef *)PIOC_BASE) + +#ifdef __cplusplus +} +#endif + +#endif // __PIOC_SFR_H__ diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035.h index a5c889a..bf9eef6 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035.h @@ -1,2779 +1,3042 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : CH32X035 Device Peripheral Access Layer Header File. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_H -#define __CH32X035_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ - -#define HSI_VALUE ((uint32_t)48000000) /* Value of the Internal oscillator in Hz */ - -/* Standard Peripheral Library version number */ -#define __STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ -#define __STDPERIPH_VERSION_SUB (0x00) /* [7:0] sub version */ -#define __STDPERIPH_VERSION ((__STDPERIPH_VERSION_MAIN << 8)\ - |(__STDPERIPH_VERSION_SUB << 0)) - - -/* Interrupt Number Definition, according to the selected device */ -typedef enum IRQn -{ - /****** RISC-V Processor Exceptions Numbers *******************************************************/ - NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ - EXC_IRQn = 3, /* 3 Exception Interrupt */ - Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ - Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ - Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ - SysTicK_IRQn = 12, /* 12 System timer Interrupt */ - Software_IRQn = 14, /* 14 software Interrupt */ - - /****** RISC-V specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 16, /* Window WatchDog Interrupt */ - PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ - FLASH_IRQn = 18, /* FLASH global Interrupt */ - EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ - AWU_IRQn = 21, /* AWU global Interrupt */ - DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 29, /* ADC1 global Interrupt */ - I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ - I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ - USART1_IRQn = 32, /* USART1 global Interrupt */ - SPI1_IRQn = 33, /* SPI1 global Interrupt */ - TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ - TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ - TIM2_UP_IRQn = 38, /* TIM2 Update Interrupt */ - USART2_IRQn = 39, /* USART2 global Interrupt */ - EXTI15_8_IRQn = 40, /* External Line[15:8] Interrupts */ - EXTI25_16_IRQn = 41, /* External Line[25:16] Interrupts */ - USART3_IRQn = 42, /* USART3 global Interrupt */ - USART4_IRQn = 43, /* USART4 global Interrupt */ - DMA1_Channel8_IRQn = 44, /* DMA1 Channel 8 global Interrupt */ - USBFS_IRQn = 45, /* USBFS Host/Device global Interrupt */ - USBFSWakeUp_IRQn = 46, /* USBFS Host/Device WakeUp Interrupt */ - PIOC_IRQn = 47, /* PIOC global Interrupt */ - OPA_IRQn = 48, /* OPA global Interrupt */ - USBPD_IRQn = 49, /* USBPD global Interrupt */ - USBPDWakeUp_IRQn = 50, /* USBPD WakeUp Interrupt */ - TIM2_CC_IRQn = 51, /* TIM2 Capture Compare Interrupt */ - TIM2_TRG_COM_IRQn = 52, /* TIM2 Trigger and Commutation Interrupt */ - TIM2_BRK_IRQn = 53, /* TIM2 Break Interrupt */ - TIM3_IRQn = 54, /* TIM3 global Interrupt */ -} IRQn_Type; - -#define HardFault_IRQn EXC_IRQn - -#include -#include "core_riscv.h" -#include "system_ch32x035.h" - -/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSI_Value HSI_VALUE - -/* Analog to Digital Converter */ -typedef struct -{ - __IO uint32_t STATR; - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t SAMPTR1; - __IO uint32_t SAMPTR2; - __IO uint32_t IOFR1; - __IO uint32_t IOFR2; - __IO uint32_t IOFR3; - __IO uint32_t IOFR4; - __IO uint32_t WDHTR; - __IO uint32_t WDLTR; - __IO uint32_t RSQR1; - __IO uint32_t RSQR2; - __IO uint32_t RSQR3; - __IO uint32_t ISQR; - __IO uint32_t IDATAR1; - __IO uint32_t IDATAR2; - __IO uint32_t IDATAR3; - __IO uint32_t IDATAR4; - __IO uint32_t RDATAR; - __IO uint32_t CTLR3; - __IO uint32_t WDTR1; - __IO uint32_t WDTR2; - __IO uint32_t WDTR3; -} ADC_TypeDef; - -/* DMA Channel Controller */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t CNTR; - __IO uint32_t PADDR; - __IO uint32_t MADDR; -} DMA_Channel_TypeDef; - -/* DMA Controller */ -typedef struct -{ - __IO uint32_t INTFR; - __IO uint32_t INTFCR; -} DMA_TypeDef; - -/* External Interrupt/Event Controller */ -typedef struct -{ - __IO uint32_t INTENR; - __IO uint32_t EVENR; - __IO uint32_t RTENR; - __IO uint32_t FTENR; - __IO uint32_t SWIEVR; - __IO uint32_t INTFR; -} EXTI_TypeDef; - -/* FLASH Registers */ -typedef struct -{ - __IO uint32_t ACTLR; - __IO uint32_t KEYR; - __IO uint32_t OBKEYR; - __IO uint32_t STATR; - __IO uint32_t CTLR; - __IO uint32_t ADDR; - uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WPR; - __IO uint32_t MODEKEYR; - __IO uint32_t BOOT_MODEKEYR; -} FLASH_TypeDef; - -/* Option Bytes Registers */ -typedef struct -{ - __IO uint16_t RDPR; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRPR0; - __IO uint16_t WRPR1; - __IO uint16_t WRPR2; - __IO uint16_t WRPR3; -} OB_TypeDef; - -/* General Purpose I/O */ -typedef struct -{ - __IO uint32_t CFGLR; - __IO uint32_t CFGHR; - __IO uint32_t INDR; - __IO uint32_t OUTDR; - __IO uint32_t BSHR; - __IO uint32_t BCR; - __IO uint32_t LCKR; - __IO uint32_t CFGXR; - __IO uint32_t BSXR; -} GPIO_TypeDef; - -/* Alternate Function I/O */ -typedef struct -{ - uint32_t RESERVED0; - __IO uint32_t PCFR1; - __IO uint32_t EXTICR[2]; - uint32_t RESERVED1; - uint32_t RESERVED2; - __IO uint32_t CTLR; -} AFIO_TypeDef; - -/* Inter Integrated Circuit Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t OADDR1; - uint16_t RESERVED2; - __IO uint16_t OADDR2; - uint16_t RESERVED3; - __IO uint16_t DATAR; - uint16_t RESERVED4; - __IO uint16_t STAR1; - uint16_t RESERVED5; - __IO uint16_t STAR2; - uint16_t RESERVED6; - __IO uint16_t CKCFGR; - uint16_t RESERVED7; -} I2C_TypeDef; - -/* Independent WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t PSCR; - __IO uint32_t RLDR; - __IO uint32_t STATR; -} IWDG_TypeDef; - -/* Power Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/* Reset and Clock Control */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR0; - __IO uint32_t RESERVED0; - __IO uint32_t APB2PRSTR; - __IO uint32_t APB1PRSTR; - __IO uint32_t AHBPCENR; - __IO uint32_t APB2PCENR; - __IO uint32_t APB1PCENR; - __IO uint32_t RESERVED1; - __IO uint32_t RSTSCKR; - __IO uint32_t AHBRSTR; -} RCC_TypeDef; - -/* Serial Peripheral Interface */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t STATR; - uint16_t RESERVED2; - __IO uint16_t DATAR; - uint16_t RESERVED3; - __IO uint16_t CRCR; - uint16_t RESERVED4; - __IO uint16_t RCRCR; - uint16_t RESERVED5; - __IO uint16_t TCRCR; - uint16_t RESERVED6; - uint32_t RESERVED7; - uint32_t RESERVED8; - __IO uint16_t HSCR; - uint16_t RESERVED9; -} SPI_TypeDef; - -/* TIM */ -typedef struct -{ - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t SMCFGR; - uint16_t RESERVED2; - __IO uint16_t DMAINTENR; - uint16_t RESERVED3; - __IO uint16_t INTFR; - uint16_t RESERVED4; - __IO uint16_t SWEVGR; - uint16_t RESERVED5; - __IO uint16_t CHCTLR1; - uint16_t RESERVED6; - __IO uint16_t CHCTLR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ATRLR; - uint16_t RESERVED11; - __IO uint16_t RPTCR; - uint16_t RESERVED12; - __IO uint16_t CH1CVR; - uint16_t RESERVED13; - __IO uint16_t CH2CVR; - uint16_t RESERVED14; - __IO uint16_t CH3CVR; - uint16_t RESERVED15; - __IO uint16_t CH4CVR; - uint16_t RESERVED16; - __IO uint16_t BDTR; - uint16_t RESERVED17; - __IO uint16_t DMACFGR; - uint16_t RESERVED18; - __IO uint16_t DMAADR; - uint16_t RESERVED19; - __IO uint16_t SPEC; - uint16_t RESERVED20; -} TIM_TypeDef; - -/* Universal Synchronous Asynchronous Receiver Transmitter */ -typedef struct -{ - __IO uint16_t STATR; - uint16_t RESERVED0; - __IO uint16_t DATAR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CTLR1; - uint16_t RESERVED3; - __IO uint16_t CTLR2; - uint16_t RESERVED4; - __IO uint16_t CTLR3; - uint16_t RESERVED5; - __IO uint16_t GPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/* Window WatchDog */ -typedef struct -{ - __IO uint32_t CTLR; - __IO uint32_t CFGR; - __IO uint32_t STATR; -} WWDG_TypeDef; - -/* OPA Registers */ -typedef struct -{ - __IO uint16_t CFGR1; - __IO uint16_t CFGR2; - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t OPAKEY; - __IO uint32_t CMPKEY; - __IO uint32_t POLLKEY; -} OPA_TypeDef; - -/* AWU Registers */ -typedef struct -{ - __IO uint32_t CSR; - __IO uint32_t WR; - __IO uint32_t PSC; -} AWU_TypeDef; - -/* PD Registers */ - -typedef struct -{ - union - { - __IO uint32_t USBPD_CONFIG; - struct - { - __IO uint16_t CONFIG; - __IO uint16_t BMC_CLK_CNT; - }; - }; - union - { - __IO uint32_t USBPD_CONTROL; - struct - { - union - { - __IO uint16_t R16_CONTROL; - struct - { - __IO uint8_t CONTROL; - __IO uint8_t TX_SEL; - }; - }; - __IO uint16_t BMC_TX_SZ; - }; - }; - union - { - __IO uint32_t USBPD_STATUS; - struct - { - union - { - __IO uint16_t R16_STATUS; - struct - { - __IO uint8_t DATA_BUF; - __IO uint8_t STATUS; - }; - }; - __IO uint16_t BMC_BYTE_CNT; - }; - }; - union - { - __IO uint32_t USBPD_PORT; - struct - { - __IO uint16_t PORT_CC1; - __IO uint16_t PORT_CC2; - }; - }; - union - { - __IO uint32_t USBPD_DMA; - struct - { - __IO uint16_t DMA; - __IO uint16_t RESERVED; - }; - }; -} USBPD_TypeDef; - -/* USBFS Registers */ -typedef struct -{ - __IO uint8_t BASE_CTRL; - __IO uint8_t UDEV_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_ADDR; - uint8_t RESERVED0; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint32_t RX_LEN; - __IO uint8_t UEP4_1_MOD; - __IO uint8_t UEP2_3_MOD; - __IO uint8_t UEP567_MOD; - uint8_t RESERVED1; - __IO uint32_t UEP0_DMA; - __IO uint32_t UEP1_DMA; - __IO uint32_t UEP2_DMA; - __IO uint32_t UEP3_DMA; - union{ - __IO uint32_t UEP0_CTRL; - struct{ - __IO uint16_t UEP0_TX_LEN; - __IO uint16_t UEP0_CTRL_H; - }; - }; - union{ - __IO uint32_t UEP1_CTRL; - struct{ - __IO uint16_t UEP1_TX_LEN; - __IO uint16_t UEP1_CTRL_H; - }; - }; - union{ - __IO uint32_t UEP2_CTRL; - struct{ - __IO uint16_t UEP2_TX_LEN; - __IO uint16_t UEP2_CTRL_H; - }; - }; - union{ - __IO uint32_t UEP3_CTRL; - struct{ - __IO uint16_t UEP3_TX_LEN; - __IO uint16_t UEP3_CTRL_H; - }; - }; - union{ - __IO uint32_t UEP4_CTRL; - struct{ - __IO uint16_t UEP4_TX_LEN; - __IO uint16_t UEP4_CTRL_H; - }; - }; - uint32_t RESERVED2; - uint32_t RESERVED3; - uint32_t RESERVED4; - uint32_t RESERVED5; - uint32_t RESERVED6; - uint32_t RESERVED7; - uint32_t RESERVED8; - uint32_t RESERVED9; - __IO uint32_t UEP5_DMA; - __IO uint32_t UEP6_DMA; - __IO uint32_t UEP7_DMA; - uint32_t RESERVED10; - union{ - __IO uint32_t UEP5_CTRL; - struct{ - __IO uint16_t UEP5_TX_LEN; - __IO uint16_t UEP5_CTRL_H; - }; - }; - union{ - __IO uint32_t UEP6_CTRL; - struct{ - __IO uint16_t UEP6_TX_LEN; - __IO uint16_t UEP6_CTRL_H; - }; - }; - union{ - __IO uint32_t UEP7_CTRL; - struct{ - __IO uint16_t UEP7_TX_LEN; - __IO uint16_t UEP7_CTRL_H; - }; - }; - __IO uint32_t UEPX_MOD; -} USBFSD_TypeDef; - -typedef struct -{ - __IO uint8_t BASE_CTRL; - __IO uint8_t HOST_CTRL; - __IO uint8_t INT_EN; - __IO uint8_t DEV_ADDR; - uint8_t RESERVED0; - __IO uint8_t MIS_ST; - __IO uint8_t INT_FG; - __IO uint8_t INT_ST; - __IO uint16_t RX_LEN; - uint16_t RESERVED1; - uint8_t RESERVED2; - __IO uint8_t HOST_EP_MOD; - uint16_t RESERVED3; - uint32_t RESERVED4; - uint32_t RESERVED5; - __IO uint16_t HOST_RX_DMA; - uint16_t RESERVED6; - __IO uint16_t HOST_TX_DMA; - uint16_t RESERVED7; - uint32_t RESERVED8; - uint16_t RESERVED9; - __IO uint8_t HOST_SETUP; - uint8_t RESERVED10; - __IO uint8_t HOST_EP_PID; - uint8_t RESERVED11; - __IO uint8_t HOST_RX_CTRL; - uint8_t RESERVED12; - __IO uint8_t HOST_TX_LEN; - uint8_t RESERVED13; - __IO uint8_t HOST_TX_CTRL; - uint8_t RESERVED14; -} USBFSH_TypeDef; - -/* Peripheral memory map */ -#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ - -#define APB1PERIPH_BASE (PERIPH_BASE) -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define USART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA1_Channel8_BASE (AHBPERIPH_BASE + 0x0094) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) -#define USBFS_BASE (AHBPERIPH_BASE + 0x3400) -#define OPA_BASE (AHBPERIPH_BASE + 0x6000) -#define AWU_BASE (AHBPERIPH_BASE + 0x6400) -#define PIOC_BASE (AHBPERIPH_BASE + 0x6C00) -#define USBPD_BASE (AHBPERIPH_BASE + 0x7000) - -#define OB_BASE ((uint32_t)0x1FFFF800) - -/* Peripheral declaration */ -#define TIM2 ((TIM_TypeDef *)TIM2_BASE) -#define TIM3 ((TIM_TypeDef *)TIM3_BASE) -#define WWDG ((WWDG_TypeDef *)WWDG_BASE) -#define IWDG ((IWDG_TypeDef *)IWDG_BASE) -#define USART2 ((USART_TypeDef *)USART2_BASE) -#define USART3 ((USART_TypeDef *)USART3_BASE) -#define USART4 ((USART_TypeDef *)USART4_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define PWR ((PWR_TypeDef *)PWR_BASE) - -#define AFIO ((AFIO_TypeDef *)AFIO_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#define TKey1 ((ADC_TypeDef *)ADC1_BASE) -#define TIM1 ((TIM_TypeDef *)TIM1_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) - -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE) -#define RCC ((RCC_TypeDef *)RCC_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE) -#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE) -#define OPA ((OPA_TypeDef *)OPA_BASE) -#define AWU ((AWU_TypeDef *)AWU_BASE) -#define USBPD ((USBPD_TypeDef *)USBPD_BASE) - -#define OB ((OB_TypeDef *)OB_BASE) - - -/******************************************************************************/ -/* Peripheral Registers Bits Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* Analog to Digital Converter */ -/******************************************************************************/ - -/******************** Bit definition for ADC_STATR register ********************/ -#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ -#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ -#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ -#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ -#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ - -/******************* Bit definition for ADC_CTLR1 register ********************/ -#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ -#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ -#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ -#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ -#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ -#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ -#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ -#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ - -#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ -#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ -#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ - -#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ -#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ -#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ - -#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ -#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ - -/******************* Bit definition for ADC_CTLR2 register ********************/ -#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ -#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ -#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ -#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ -#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ -#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ - -#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ - -#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ -#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ -#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ - -#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ -#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ -#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ -#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ - -/****************** Bit definition for ADC_SAMPTR1 register *******************/ -#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ - -/****************** Bit definition for ADC_SAMPTR2 register *******************/ -#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ - -#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ -#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ -#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ - -#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ -#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ - -#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ -#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ -#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ - -#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ -#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ - -#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ - -#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ -#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ - -#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ -#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ -#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ - -#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ -#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ -#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ - -/****************** Bit definition for ADC_IOFR1 register *******************/ -#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_IOFR2 register *******************/ -#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_IOFR3 register *******************/ -#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_IOFR4 register *******************/ -#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_WDHTR register ********************/ -#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ - -/******************* Bit definition for ADC_WDLTR register ********************/ -#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ - -/******************* Bit definition for ADC_RSQR1 register *******************/ -#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ -#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ - -/******************* Bit definition for ADC_RSQR2 register *******************/ -#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_RSQR3 register *******************/ -#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ -#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ -#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ -#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ - -#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ -#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ -#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ -#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ -#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ - -/******************* Bit definition for ADC_ISQR register *******************/ -#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ -#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ -#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ -#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ - -#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ -#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ -#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ -#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ -#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ - -#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ -#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ -#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ -#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ - -#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ -#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ -#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ -#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ -#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ - -#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ -#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ - -/******************* Bit definition for ADC_IDATAR1 register *******************/ -#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR2 register *******************/ -#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR3 register *******************/ -#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************* Bit definition for ADC_IDATAR4 register *******************/ -#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ - -/******************** Bit definition for ADC_RDATAR register ********************/ -#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ -#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ - -/******************************************************************************/ -/* DMA Controller */ -/******************************************************************************/ - -/******************* Bit definition for DMA_INTFR register ********************/ -#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ -#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ -#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ -#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ -#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ -#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ -#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ -#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ -#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ -#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ -#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ -#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ -#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ -#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ -#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ -#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ -#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ -#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ -#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ -#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ -#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ -#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ -#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ -#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ -#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ -#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ -#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ -#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ -#define DMA_GIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt flag */ -#define DMA_TCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete flag */ -#define DMA_HTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer flag */ -#define DMA_TEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error flag */ - -/******************* Bit definition for DMA_INTFCR register *******************/ -#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ -#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ -#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ -#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ -#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ -#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ -#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ -#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ -#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ -#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ -#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ -#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ -#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ -#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ -#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ -#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ -#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ -#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ -#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ -#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ -#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ -#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ -#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ -#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ -#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ -#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ -#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ -#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ -#define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */ -#define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */ -#define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */ -#define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */ - -/******************* Bit definition for DMA_CFGR1 register *******************/ -#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ -#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ -#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR2 register *******************/ -#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFGR3 register *******************/ -#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG4 register *******************/ -#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/****************** Bit definition for DMA_CFG5 register *******************/ -#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/******************* Bit definition for DMA_CFG6 register *******************/ -#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ - -/******************* Bit definition for DMA_CFG7 register *******************/ -#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/******************* Bit definition for DMA_CFG8 register *******************/ -#define DMA_CFG8_EN ((uint16_t)0x0001) /* Channel enable */ -#define DMA_CFG8_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CFG8_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CFG8_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ -#define DMA_CFG8_DIR ((uint16_t)0x0010) /* Data transfer direction */ -#define DMA_CFG8_CIRC ((uint16_t)0x0020) /* Circular mode */ -#define DMA_CFG8_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ -#define DMA_CFG8_MINC ((uint16_t)0x0080) /* Memory increment mode */ - -#define DMA_CFG8_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CFG8_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ -#define DMA_CFG8_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define DMA_CFG8_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CFG8_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ -#define DMA_CFG8_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define DMA_CFG8_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CFG8_PL_0 ((uint16_t)0x1000) /* Bit 0 */ -#define DMA_CFG8_PL_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define DMA_CFG8_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ - -/****************** Bit definition for DMA_CNTR1 register ******************/ -#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR2 register ******************/ -#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR3 register ******************/ -#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR4 register ******************/ -#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR5 register ******************/ -#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR6 register ******************/ -#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR7 register ******************/ -#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_CNTR8 register ******************/ -#define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ - -/****************** Bit definition for DMA_PADDR1 register *******************/ -#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR2 register *******************/ -#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR3 register *******************/ -#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR4 register *******************/ -#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR5 register *******************/ -#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR6 register *******************/ -#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR7 register *******************/ -#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_PADDR8 register *******************/ -#define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ - -/****************** Bit definition for DMA_MADDR1 register *******************/ -#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR2 register *******************/ -#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR3 register *******************/ -#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR4 register *******************/ -#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR5 register *******************/ -#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR6 register *******************/ -#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR7 register *******************/ -#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/****************** Bit definition for DMA_MADDR8 register *******************/ -#define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ - -/******************************************************************************/ -/* External Interrupt/Event Controller */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_INTENR register *******************/ -#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ -#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ -#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ -#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ -#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ -#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ -#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ -#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ -#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ -#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ -#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ -#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ -#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ -#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ -#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ -#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ -#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ -#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ -#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ -#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ -#define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */ -#define EXTI_INTENR_MR21 ((uint32_t)0x00200000) /* Interrupt Mask on line 21 */ -#define EXTI_INTENR_MR22 ((uint32_t)0x00400000) /* Interrupt Mask on line 22 */ -#define EXTI_INTENR_MR23 ((uint32_t)0x00800000) /* Interrupt Mask on line 23 */ -#define EXTI_INTENR_MR24 ((uint32_t)0x01000000) /* Interrupt Mask on line 24 */ -#define EXTI_INTENR_MR25 ((uint32_t)0x02000000) /* Interrupt Mask on line 25 */ -#define EXTI_INTENR_MR26 ((uint32_t)0x04000000) /* Interrupt Mask on line 26 */ -#define EXTI_INTENR_MR27 ((uint32_t)0x08000000) /* Interrupt Mask on line 27 */ -#define EXTI_INTENR_MR28 ((uint32_t)0x10000000) /* Interrupt Mask on line 28 */ -#define EXTI_INTENR_MR29 ((uint32_t)0x20000000) /* Interrupt Mask on line 29 */ - -/******************* Bit definition for EXTI_EVENR register *******************/ -#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ -#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ -#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ -#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ -#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ -#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ -#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ -#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ -#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ -#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ -#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ -#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ -#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ -#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ -#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ -#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ -#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ -#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ -#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ -#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ -#define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */ -#define EXTI_EVENR_MR21 ((uint32_t)0x00200000) /* Event Mask on line 21 */ -#define EXTI_EVENR_MR22 ((uint32_t)0x00400000) /* Event Mask on line 22 */ -#define EXTI_EVENR_MR23 ((uint32_t)0x00800000) /* Event Mask on line 23 */ -#define EXTI_EVENR_MR24 ((uint32_t)0x01000000) /* Event Mask on line 24 */ -#define EXTI_EVENR_MR25 ((uint32_t)0x02000000) /* Event Mask on line 25 */ -#define EXTI_EVENR_MR26 ((uint32_t)0x04000000) /* Event Mask on line 26 */ -#define EXTI_EVENR_MR27 ((uint32_t)0x08000000) /* Event Mask on line 27 */ -#define EXTI_EVENR_MR28 ((uint32_t)0x10000000) /* Event Mask on line 28 */ -#define EXTI_EVENR_MR29 ((uint32_t)0x20000000) /* Event Mask on line 29 */ - -/****************** Bit definition for EXTI_RTENR register *******************/ -#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ -#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ -#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ -#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ -#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ -#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ -#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ -#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ -#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ -#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ -#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ -#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ -#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ -#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ -#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ -#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ -#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ -#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ -#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ -#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ -#define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */ -#define EXTI_RTENR_TR21 ((uint32_t)0x00200000) /* Rising trigger event configuration bit of line 21 */ -#define EXTI_RTENR_TR22 ((uint32_t)0x00400000) /* Rising trigger event configuration bit of line 22 */ -#define EXTI_RTENR_TR23 ((uint32_t)0x00800000) /* Rising trigger event configuration bit of line 23 */ -#define EXTI_RTENR_TR24 ((uint32_t)0x01000000) /* Rising trigger event configuration bit of line 24 */ -#define EXTI_RTENR_TR25 ((uint32_t)0x02000000) /* Rising trigger event configuration bit of line 25 */ -#define EXTI_RTENR_TR26 ((uint32_t)0x04000000) /* Rising trigger event configuration bit of line 26 */ -#define EXTI_RTENR_TR27 ((uint32_t)0x08000000) /* Rising trigger event configuration bit of line 27 */ -#define EXTI_RTENR_TR28 ((uint32_t)0x10000000) /* Rising trigger event configuration bit of line 28 */ -#define EXTI_RTENR_TR29 ((uint32_t)0x20000000) /* Rising trigger event configuration bit of line 29 */ - -/****************** Bit definition for EXTI_FTENR register *******************/ -#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ -#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ -#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ -#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ -#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ -#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ -#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ -#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ -#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ -#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ -#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ -#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ -#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ -#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ -#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ -#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ -#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ -#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ -#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ -#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ -#define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */ -#define EXTI_FTENR_TR21 ((uint32_t)0x00200000) /* Falling trigger event configuration bit of line 21 */ -#define EXTI_FTENR_TR22 ((uint32_t)0x00400000) /* Falling trigger event configuration bit of line 22 */ -#define EXTI_FTENR_TR23 ((uint32_t)0x00800000) /* Falling trigger event configuration bit of line 23 */ -#define EXTI_FTENR_TR24 ((uint32_t)0x01000000) /* Falling trigger event configuration bit of line 24 */ -#define EXTI_FTENR_TR25 ((uint32_t)0x02000000) /* Falling trigger event configuration bit of line 25 */ -#define EXTI_FTENR_TR26 ((uint32_t)0x04000000) /* Falling trigger event configuration bit of line 26 */ -#define EXTI_FTENR_TR27 ((uint32_t)0x08000000) /* Falling trigger event configuration bit of line 27 */ -#define EXTI_FTENR_TR28 ((uint32_t)0x10000000) /* Falling trigger event configuration bit of line 28 */ -#define EXTI_FTENR_TR29 ((uint32_t)0x20000000) /* Falling trigger event configuration bit of line 29 */ - -/****************** Bit definition for EXTI_SWIEVR register ******************/ -#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ -#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ -#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ -#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ -#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ -#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ -#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ -#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ -#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ -#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ -#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ -#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ -#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ -#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ -#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ -#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ -#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ -#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ -#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ -#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ -#define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */ -#define EXTI_SWIEVR_SWIEVR21 ((uint32_t)0x00200000) /* Software Interrupt on line 21 */ -#define EXTI_SWIEVR_SWIEVR22 ((uint32_t)0x00400000) /* Software Interrupt on line 22 */ -#define EXTI_SWIEVR_SWIEVR23 ((uint32_t)0x00800000) /* Software Interrupt on line 23 */ -#define EXTI_SWIEVR_SWIEVR24 ((uint32_t)0x01000000) /* Software Interrupt on line 24 */ -#define EXTI_SWIEVR_SWIEVR25 ((uint32_t)0x02000000) /* Software Interrupt on line 25 */ -#define EXTI_SWIEVR_SWIEVR26 ((uint32_t)0x04000000) /* Software Interrupt on line 26 */ -#define EXTI_SWIEVR_SWIEVR27 ((uint32_t)0x08000000) /* Software Interrupt on line 27 */ -#define EXTI_SWIEVR_SWIEVR28 ((uint32_t)0x10000000) /* Software Interrupt on line 28 */ -#define EXTI_SWIEVR_SWIEVR29 ((uint32_t)0x20000000) /* Software Interrupt on line 29 */ - -/******************* Bit definition for EXTI_INTFR register ********************/ -#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ -#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ -#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ -#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ -#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ -#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ -#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ -#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ -#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ -#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ -#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ -#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ -#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ -#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ -#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ -#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ -#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ -#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ -#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ -#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ -#define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */ -#define EXTI_INTF_INTF21 ((uint32_t)0x00200000) /* Pending bit for line 21 */ -#define EXTI_INTF_INTF22 ((uint32_t)0x00400000) /* Pending bit for line 22 */ -#define EXTI_INTF_INTF23 ((uint32_t)0x00800000) /* Pending bit for line 23 */ -#define EXTI_INTF_INTF24 ((uint32_t)0x01000000) /* Pending bit for line 24 */ -#define EXTI_INTF_INTF25 ((uint32_t)0x02000000) /* Pending bit for line 25 */ -#define EXTI_INTF_INTF26 ((uint32_t)0x04000000) /* Pending bit for line 26 */ -#define EXTI_INTF_INTF27 ((uint32_t)0x08000000) /* Pending bit for line 27 */ -#define EXTI_INTF_INTF28 ((uint32_t)0x10000000) /* Pending bit for line 28 */ -#define EXTI_INTF_INTF29 ((uint32_t)0x20000000) /* Pending bit for line 29 */ - -/******************************************************************************/ -/* FLASH and Option Bytes Registers */ -/******************************************************************************/ - -/******************* Bit definition for FLASH_ACTLR register ******************/ -#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ -#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ -#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ - -/***************** Bit definition for FLASH_OBKEYR register ****************/ -#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ - -/****************** Bit definition for FLASH_STATR register *******************/ -#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ -#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ -#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ -#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ - -/******************* Bit definition for FLASH_CTLR register *******************/ -#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */ -#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */ -#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ -#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ -#define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ -#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ -#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ -#define FLASH_CTLR_OPTWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ -#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ -#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ -#define FLASH_CTLR_FAST_LOCK ((uint32_t)0x00008000) /* Fast Lock */ -#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */ -#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */ -#define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */ -#define FLASH_CTLR_PAGE_BER64 ((uint32_t)0x00080000) /* Block Erase 64K */ -#define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */ - -/******************* Bit definition for FLASH_ADDR register *******************/ -#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ - -#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ -#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ -#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /* BFB2 */ - -/****************** Bit definition for FLASH_WPR register ******************/ -#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ - -/****************** Bit definition for FLASH_RDPR register *******************/ -#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ -#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ - -/****************** Bit definition for FLASH_WRPR0 register ******************/ -#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR1 register ******************/ -#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR2 register ******************/ -#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRPR3 register ******************/ -#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ - -/******************************************************************************/ -/* General Purpose and Alternate Function I/O */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CFGLR register *******************/ -#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_CFGHR register *******************/ -#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ - -#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ -#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ - -#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ -#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ -#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ -#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ - -#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ -#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ -#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ - -#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ -#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ -#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ -#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ - -#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ -#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ - -/******************* Bit definition for GPIO_INDR register *******************/ -#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ -#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ -#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ -#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ -#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ -#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ -#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ -#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ -#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ -#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ -#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ -#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ -#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ -#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ -#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ -#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ - -/******************* Bit definition for GPIO_OUTDR register *******************/ -#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ -#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ -#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ -#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ -#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ -#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ -#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ -#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ -#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ -#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ -#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ -#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ -#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ -#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ -#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ -#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSHR register *******************/ -#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ -#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ -#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ -#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ -#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ -#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ -#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ -#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ -#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ -#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ -#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ -#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ -#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ -#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ -#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ -#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ - -#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ -#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ -#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ -#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ -#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ -#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ -#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ -#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ -#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ -#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ -#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ -#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ -#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ -#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ -#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ -#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BCR register *******************/ -#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ -#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ -#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ -#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ -#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ -#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ -#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ -#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ -#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ -#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ -#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ -#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ -#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ -#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ -#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ -#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ -#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ -#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ -#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ -#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ -#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ -#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ -#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ -#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ -#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ -#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ -#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ -#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ -#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ -#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ -#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ -#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ - -/****************** Bit definition for AFIO_PCFR1register *******************/ -#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ -#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ -#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ -#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ - -#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ - -#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ -#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ - -#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ -#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ - -#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ -#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ - -#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ - -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ - -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ - -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ - -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ - -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ - -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ - -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ - -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ - -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ - -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ - -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ - -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ - -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ - -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ - -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ - -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ - -/******************************************************************************/ -/* Independent WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_CTLR register ********************/ -#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PSCR register ********************/ -#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ -#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ -#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ -#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ - -/******************* Bit definition for IWDG_RLDR register *******************/ -#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ - -/******************* Bit definition for IWDG_STATR register ********************/ -#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ -#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ - -/******************************************************************************/ -/* Inter-integrated Circuit Interface */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CTLR1 register ********************/ -#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ -#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ -#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ -#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ -#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ -#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ -#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ -#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ -#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ -#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ -#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ -#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ -#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ -#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ - -/******************* Bit definition for I2C_CTLR2 register ********************/ -#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ - -#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ -#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ -#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ -#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ -#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ - -/******************* Bit definition for I2C_OADDR1 register *******************/ -#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ -#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ - -#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ -#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ -#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ -#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ -#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ -#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ -#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ -#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ -#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ -#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ - -#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OADDR2 register *******************/ -#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ -#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ - -/******************** Bit definition for I2C_DATAR register ********************/ -#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ - -/******************* Bit definition for I2C_STAR1 register ********************/ -#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ -#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ -#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ -#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ -#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ -#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ -#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ -#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ -#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ -#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ -#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ -#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ -#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ -#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ - -/******************* Bit definition for I2C_STAR2 register ********************/ -#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ -#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ -#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ -#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ -#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ -#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ -#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ -#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ - -/******************* Bit definition for I2C_CKCFGR register ********************/ -#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ -#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ - -/******************************************************************************/ -/* Power Control */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CTLR register ********************/ -#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ -#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ - -#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ -#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ - -#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ - -/******************************************************************************/ -/* Reset and Clock Control */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CTLR register ********************/ -#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ -#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ -#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ -#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ - -/******************* Bit definition for RCC_CFGR0 register *******************/ -#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ -#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ -#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ -#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ -#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ - -#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ -#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ -#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ -#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ -#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ -#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ -#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ -#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ -#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ -#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ -#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ -#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ -#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ - -#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ -#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ -#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ -#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ - -#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ -#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ -#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ - -/***************** Bit definition for RCC_APB2PRSTR register *****************/ -#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ -#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ -#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ -#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ -#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ -#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ -#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ -#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ - -/***************** Bit definition for RCC_APB1PRSTR register *****************/ -#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ -#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ -#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ -#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ -#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ -#define RCC_USART4RST ((uint32_t)0x00080000) /* USART 4 reset */ -#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ -#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ - -/****************** Bit definition for RCC_AHBPCENR register ******************/ -#define RCC_DMA1EN ((uint32_t)0x00000001) /* DMA1 clock enable */ -#define RCC_SRAMEN ((uint32_t)0x00000004) /* SRAM interface clock enable */ -#define RCC_USBFS ((uint32_t)0x00001000) /* USBFS clock enable */ -#define RCC_USBPD ((uint32_t)0x00020000) /* USBPD clock enable */ - -/****************** Bit definition for RCC_APB2PCENR register *****************/ -#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ -#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ -#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ -#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ -#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ -#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ -#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ -#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ - -/***************** Bit definition for RCC_APB1PCENR register ******************/ -#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ -#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ -#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ -#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ -#define RCC_USART3EN ((uint32_t)0x00040000) /* USART 3 clock enable */ -#define RCC_USART4EN ((uint32_t)0x00080000) /* USART 4 clock enable */ -#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ -#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ - -/******************* Bit definition for RCC_RSTSCKR register ********************/ -#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ -#define RCC_OPARSTF ((uint32_t)0x02000000) /* OPA reset flag */ -#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ -#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ -#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ -#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ -#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ -#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ - -/******************************************************************************/ -/* Serial Peripheral Interface */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CTLR1 register ********************/ -#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ -#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ -#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ - -#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ -#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ -#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ -#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ - -#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ -#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ -#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ -#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ -#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ -#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ -#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ -#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ -#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ -#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CTLR2 register ********************/ -#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ -#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ -#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ -#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ -#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ -#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_STATR register ********************/ -#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ -#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ -#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ -#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ -#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ -#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ -#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ -#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ - -/******************** Bit definition for SPI_DATAR register ********************/ -#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ - -/******************* Bit definition for SPI_CRCR register ******************/ -#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ - -/****************** Bit definition for SPI_RCRCR register ******************/ -#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ - -/****************** Bit definition for SPI_TCRCR register ******************/ -#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ - -/****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ - -#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ -#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ - -/****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ -#define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ - -/******************************************************************************/ -/* TIM */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CTLR1 register ********************/ -#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ -#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ -#define TIM_URS ((uint16_t)0x0004) /* Update request source */ -#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ -#define TIM_DIR ((uint16_t)0x0010) /* Direction */ - -#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ -#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ - -#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ - -#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ -#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ - -/******************* Bit definition for TIM_CTLR2 register ********************/ -#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ -#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ -#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ - -#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ -#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ -#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ -#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ -#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ -#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ -#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ -#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ -#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIM_SMCFGR register *******************/ -#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ - -#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ -#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ - -#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ -#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ - -#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ -#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ - -/******************* Bit definition for TIM_DMAINTENR register *******************/ -#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ -#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ -#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ -#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ -#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ -#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ -#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ -#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ -#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ -#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ -#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ -#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ -#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ -#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ -#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ - -/******************** Bit definition for TIM_INTFR register ********************/ -#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ -#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ -#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ -#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ -#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ -#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ -#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ -#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ -#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ -#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ -#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ -#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIM_SWEVGR register ********************/ -#define TIM_UG ((uint8_t)0x01) /* Update Generation */ -#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ -#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ -#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ -#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ -#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ -#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ -#define TIM_BG ((uint8_t)0x80) /* Break Generation */ - -/****************** Bit definition for TIM_CHCTLR1 register *******************/ -#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ -#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ - -#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ - -#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ -#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ - -#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ - -#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/****************** Bit definition for TIM_CHCTLR2 register *******************/ -#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ - -#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ -#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ - -#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ - -#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ - -#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ -#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ - -#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ - -#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ - -#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ -#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ - -#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ -#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ -#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ -#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ - -#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ -#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ - -#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ -#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ -#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ -#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ -#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ -#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ -#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ -#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ -#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ -#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ -#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ -#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ -#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ -#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ -#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ -#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ -#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ -#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ - -/******************* Bit definition for TIM_ATRLR register ********************/ -#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ - -/******************* Bit definition for TIM_RPTCR register ********************/ -#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ - -/******************* Bit definition for TIM_CH1CVR register *******************/ -#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ - -/******************* Bit definition for TIM_CH2CVR register *******************/ -#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ - -/******************* Bit definition for TIM_CH3CVR register *******************/ -#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ - -/******************* Bit definition for TIM_CH4CVR register *******************/ -#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ -#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ -#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ -#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ - -#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ -#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ - -#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ -#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ -#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ -#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ -#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ -#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ - -/******************* Bit definition for TIM_DMACFGR register ********************/ -#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ -#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ -#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ -#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ -#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ -#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ - -#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ -#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ -#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ -#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ -#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ - -/******************* Bit definition for TIM_DMAADR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ - -/******************************************************************************/ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/******************************************************************************/ - -/******************* Bit definition for USART_STATR register *******************/ -#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ -#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ -#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ -#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ -#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ -#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ -#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ -#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ -#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ -#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ - -/******************* Bit definition for USART_DATAR register *******************/ -#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ - -/****************** Bit definition for USART_CTLR1 register *******************/ -#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ -#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ -#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ -#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ -#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ -#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ -#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ -#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ -#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ -#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ -#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ -#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ -#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ -#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ -#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ - -/****************** Bit definition for USART_CTLR2 register *******************/ -#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ -#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ -#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ -#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ -#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ -#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ -#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ - -#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ -#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ -#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ - -#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ - -/****************** Bit definition for USART_CTLR3 register *******************/ -#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ -#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ -#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ -#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ -#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ -#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ -#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ -#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ -#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ -#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ -#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ -#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ - -/****************** Bit definition for USART_GPR register ******************/ -#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ -#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ -#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ -#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ -#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ -#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ -#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ -#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ -#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ - -#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ - -/******************************************************************************/ -/* Window WATCHDOG */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CTLR register ********************/ -#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ -#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ -#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ -#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ -#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ -#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ -#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ - -#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ - -/******************* Bit definition for WWDG_CFGR register *******************/ -#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ -#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ -#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ -#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ -#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ -#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ -#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ -#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ - -#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ -#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ - -#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_STATR register ********************/ -#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ - - -#include "ch32x035_conf.h" - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035.h + * Author : WCH + * Version : V1.0.1 + * Date : 2024/10/28 + * Description : CH32X035 Device Peripheral Access Layer Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_H +#define __CH32X035_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#define HSI_VALUE ((uint32_t)48000000) /* Value of the Internal oscillator in Hz */ + +/* Standard Peripheral Library version number */ +#define __STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ +#define __STDPERIPH_VERSION_SUB (0x08) /* [7:0] sub version */ +#define __STDPERIPH_VERSION ((__STDPERIPH_VERSION_MAIN << 8)\ + |(__STDPERIPH_VERSION_SUB << 0)) + + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + FLASH_IRQn = 18, /* FLASH global Interrupt */ + EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ + AWU_IRQn = 21, /* AWU global Interrupt */ + DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 29, /* ADC1 global Interrupt */ + I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ + USART1_IRQn = 32, /* USART1 global Interrupt */ + SPI1_IRQn = 33, /* SPI1 global Interrupt */ + TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ + TIM2_UP_IRQn = 38, /* TIM2 Update Interrupt */ + USART2_IRQn = 39, /* USART2 global Interrupt */ + EXTI15_8_IRQn = 40, /* External Line[15:8] Interrupts */ + EXTI25_16_IRQn = 41, /* External Line[25:16] Interrupts */ + USART3_IRQn = 42, /* USART3 global Interrupt */ + USART4_IRQn = 43, /* USART4 global Interrupt */ + DMA1_Channel8_IRQn = 44, /* DMA1 Channel 8 global Interrupt */ + USBFS_IRQn = 45, /* USBFS Host/Device global Interrupt */ + USBFSWakeUp_IRQn = 46, /* USBFS Host/Device WakeUp Interrupt */ + PIOC_IRQn = 47, /* PIOC global Interrupt */ + OPA_IRQn = 48, /* OPA global Interrupt */ + USBPD_IRQn = 49, /* USBPD global Interrupt */ + USBPDWakeUp_IRQn = 50, /* USBPD WakeUp Interrupt */ + TIM2_CC_IRQn = 51, /* TIM2 Capture Compare Interrupt */ + TIM2_TRG_COM_IRQn = 52, /* TIM2 Trigger and Commutation Interrupt */ + TIM2_BRK_IRQn = 53, /* TIM2 Break Interrupt */ + TIM3_IRQn = 54, /* TIM3 global Interrupt */ +} IRQn_Type; + +#define HardFault_IRQn EXC_IRQn +#define SysTicK_IRQn SysTick_IRQn + +#include +#include "core_riscv.h" +#include "system_ch32x035.h" + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + __IO uint32_t CTLR3; + __IO uint32_t WDTR1; + __IO uint32_t WDTR2; + __IO uint32_t WDTR3; +} ADC_TypeDef; + +/* DMA Channel Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; + __IO uint32_t BOOT_MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; + __IO uint32_t CFGXR; + __IO uint32_t BSXR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[2]; + uint32_t RESERVED1; + uint32_t RESERVED2; + __IO uint32_t CTLR; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t RESERVED0; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t RESERVED1; + __IO uint32_t RSTSCKR; + __IO uint32_t AHBRSTR; +} RCC_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + union + { + __IO uint32_t CH1CVR_R32; + struct + { + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + }; + }; + union + { + __IO uint32_t CH2CVR__R32; + struct + { + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + }; + }; + union + { + __IO uint32_t CH3CVR__R32; + struct + { + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + }; + }; + union + { + __IO uint32_t CH4CVR__R32; + struct + { + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + }; + }; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DMACFGR; + uint16_t RESERVED18; + __IO uint16_t DMAADR; + uint16_t RESERVED19; + __IO uint16_t SPEC; + uint16_t RESERVED20; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* OPA Registers */ +typedef struct +{ + __IO uint16_t CFGR1; + __IO uint16_t CFGR2; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t OPAKEY; + __IO uint32_t CMPKEY; + __IO uint32_t POLLKEY; +} OPA_TypeDef; + +/* AWU Registers */ +typedef struct +{ + __IO uint32_t CSR; + __IO uint32_t WR; + __IO uint32_t PSC; +} AWU_TypeDef; + +/* PD Registers */ + +typedef struct +{ + union + { + __IO uint32_t USBPD_CONFIG; + struct + { + __IO uint16_t CONFIG; + __IO uint16_t BMC_CLK_CNT; + }; + }; + union + { + __IO uint32_t USBPD_CONTROL; + struct + { + union + { + __IO uint16_t R16_CONTROL; + struct + { + __IO uint8_t CONTROL; + __IO uint8_t TX_SEL; + }; + }; + __IO uint16_t BMC_TX_SZ; + }; + }; + union + { + __IO uint32_t USBPD_STATUS; + struct + { + union + { + __IO uint16_t R16_STATUS; + struct + { + __IO uint8_t DATA_BUF; + __IO uint8_t STATUS; + }; + }; + __IO uint16_t BMC_BYTE_CNT; + }; + }; + union + { + __IO uint32_t USBPD_PORT; + struct + { + __IO uint16_t PORT_CC1; + __IO uint16_t PORT_CC2; + }; + }; + union + { + __IO uint32_t USBPD_DMA; + struct + { + __IO uint16_t DMA; + __IO uint16_t RESERVED; + }; + }; +} USBPD_TypeDef; + +/* USBFS Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + uint8_t RESERVED0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint32_t RX_LEN; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP567_MOD; + uint8_t RESERVED1; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + union{ + __IO uint32_t UEP0_CTRL; + struct{ + __IO uint16_t UEP0_TX_LEN; + __IO uint16_t UEP0_CTRL_H; + }; + }; + union{ + __IO uint32_t UEP1_CTRL; + struct{ + __IO uint16_t UEP1_TX_LEN; + __IO uint16_t UEP1_CTRL_H; + }; + }; + union{ + __IO uint32_t UEP2_CTRL; + struct{ + __IO uint16_t UEP2_TX_LEN; + __IO uint16_t UEP2_CTRL_H; + }; + }; + union{ + __IO uint32_t UEP3_CTRL; + struct{ + __IO uint16_t UEP3_TX_LEN; + __IO uint16_t UEP3_CTRL_H; + }; + }; + union{ + __IO uint32_t UEP4_CTRL; + struct{ + __IO uint16_t UEP4_TX_LEN; + __IO uint16_t UEP4_CTRL_H; + }; + }; + uint32_t RESERVED2; + uint32_t RESERVED3; + uint32_t RESERVED4; + uint32_t RESERVED5; + uint32_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + uint32_t RESERVED9; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + uint32_t RESERVED10; + union{ + __IO uint32_t UEP5_CTRL; + struct{ + __IO uint16_t UEP5_TX_LEN; + __IO uint16_t UEP5_CTRL_H; + }; + }; + union{ + __IO uint32_t UEP6_CTRL; + struct{ + __IO uint16_t UEP6_TX_LEN; + __IO uint16_t UEP6_CTRL_H; + }; + }; + union{ + __IO uint32_t UEP7_CTRL; + struct{ + __IO uint16_t UEP7_TX_LEN; + __IO uint16_t UEP7_CTRL_H; + }; + }; + __IO uint32_t UEPX_MOD; +} USBFSD_TypeDef; + +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + uint8_t RESERVED0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + uint16_t RESERVED1; + uint8_t RESERVED2; + __IO uint8_t HOST_EP_MOD; + uint16_t RESERVED3; + uint32_t RESERVED4; + uint32_t RESERVED5; + __IO uint16_t HOST_RX_DMA; + uint16_t RESERVED6; + __IO uint16_t HOST_TX_DMA; + uint16_t RESERVED7; + uint32_t RESERVED8; + uint16_t RESERVED9; + __IO uint8_t HOST_SETUP; + uint8_t RESERVED10; + __IO uint8_t HOST_EP_PID; + uint8_t RESERVED11; + __IO uint8_t HOST_RX_CTRL; + uint8_t RESERVED12; + __IO uint8_t HOST_TX_LEN; + uint8_t RESERVED13; + __IO uint8_t HOST_TX_CTRL; + uint8_t RESERVED14; +} USBFSH_TypeDef; + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define USART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA1_Channel8_BASE (AHBPERIPH_BASE + 0x0094) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) +#define USBFS_BASE (AHBPERIPH_BASE + 0x3400) +#define OPA_BASE (AHBPERIPH_BASE + 0x6000) +#define AWU_BASE (AHBPERIPH_BASE + 0x6400) +#define PIOC_BASE (AHBPERIPH_BASE + 0x6C00) +#define USBPD_BASE (AHBPERIPH_BASE + 0x7000) + +#define OB_BASE ((uint32_t)0x1FFFF800) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define USART4 ((USART_TypeDef *)USART4_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) + +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define TKey1 ((ADC_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) + +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE) +#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE) +#define OPA ((OPA_TypeDef *)OPA_BASE) +#define AWU ((AWU_TypeDef *)AWU_BASE) +#define USBPD ((USBPD_TypeDef *)USBPD_BASE) + +#define OB ((OB_TypeDef *)OB_BASE) + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000000F) /* AWDCH[3:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ +#define ADC_TKENABLE ((uint32_t)0x01000000) /* TKEN mode enable */ + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ + +/******************** Bit definition for ADC_CTLR3 register ********************/ +#define ADC_CTLR3_CLK_DIV ((uint32_t)0x0000000F) /* CLK_DIVL[3:0] bits */ +#define ADC_CTLR3_CLK_DIV_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_CTLR3_CLK_DIV_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_CTLR3_CLK_DIV_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_CTLR3_CLK_DIV_3 ((uint32_t)0x00000008) /* Bit 3 */ + +#define ADC_CTLR3_AWD_SCAN ((uint32_t)0x00000200) /* Analog watchdog Scan enable */ +#define ADC_CTLR3_AWD0_RST_EN ((uint32_t)0x00001000) /* Watchdog0 Reset Enable */ +#define ADC_CTLR3_AWD1_RST_EN ((uint32_t)0x00002000) /* Watchdog1 Reset Enable */ +#define ADC_CTLR3_AWD2_RST_EN ((uint32_t)0x00004000) /* Watchdog2 Reset Enable */ +#define ADC_CTLR3_AWD3_RST_EN ((uint32_t)0x00008000) /* Watchdog3 Reset Enable */ + +/******************** Bit definition for ADC_WDTR1 register ********************/ +#define ADC_WDTR1_LTR1 ((uint32_t)0x00000FFF) /* Analog watchdog1 low threshold */ +#define ADC_WDTR1_HTR1 ((uint32_t)0x0FFF0000) /* Analog watchdog1 high threshold */ + +/******************** Bit definition for ADC_WDTR2 register ********************/ +#define ADC_WDTR2_LTR2 ((uint32_t)0x00000FFF) /* Analog watchdog2 low threshold */ +#define ADC_WDTR2_HTR2 ((uint32_t)0x0FFF0000) /* Analog watchdog2 high threshold */ + +/******************** Bit definition for ADC_WDTR3 register ********************/ +#define ADC_WDTR3_LTR3 ((uint32_t)0x00000FFF) /* Analog watchdog3 low threshold */ +#define ADC_WDTR3_HTR3 ((uint32_t)0x0FFF0000) /* Analog watchdog3 high threshold */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ +#define DMA_GIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ +#define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */ +#define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */ +#define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */ +#define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG8 register *******************/ +#define DMA_CFG8_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG8_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG8_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG8_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG8_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG8_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG8_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG8_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG8_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG8_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG8_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG8_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG8_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG8_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG8_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG8_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG8_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG8_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR8 register ******************/ +#define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR8 register *******************/ +#define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR8 register *******************/ +#define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ +#define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */ +#define EXTI_INTENR_MR21 ((uint32_t)0x00200000) /* Interrupt Mask on line 21 */ +#define EXTI_INTENR_MR22 ((uint32_t)0x00400000) /* Interrupt Mask on line 22 */ +#define EXTI_INTENR_MR23 ((uint32_t)0x00800000) /* Interrupt Mask on line 23 */ +#define EXTI_INTENR_MR24 ((uint32_t)0x01000000) /* Interrupt Mask on line 24 */ +#define EXTI_INTENR_MR25 ((uint32_t)0x02000000) /* Interrupt Mask on line 25 */ +#define EXTI_INTENR_MR26 ((uint32_t)0x04000000) /* Interrupt Mask on line 26 */ +#define EXTI_INTENR_MR27 ((uint32_t)0x08000000) /* Interrupt Mask on line 27 */ +#define EXTI_INTENR_MR28 ((uint32_t)0x10000000) /* Interrupt Mask on line 28 */ +#define EXTI_INTENR_MR29 ((uint32_t)0x20000000) /* Interrupt Mask on line 29 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ +#define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */ +#define EXTI_EVENR_MR21 ((uint32_t)0x00200000) /* Event Mask on line 21 */ +#define EXTI_EVENR_MR22 ((uint32_t)0x00400000) /* Event Mask on line 22 */ +#define EXTI_EVENR_MR23 ((uint32_t)0x00800000) /* Event Mask on line 23 */ +#define EXTI_EVENR_MR24 ((uint32_t)0x01000000) /* Event Mask on line 24 */ +#define EXTI_EVENR_MR25 ((uint32_t)0x02000000) /* Event Mask on line 25 */ +#define EXTI_EVENR_MR26 ((uint32_t)0x04000000) /* Event Mask on line 26 */ +#define EXTI_EVENR_MR27 ((uint32_t)0x08000000) /* Event Mask on line 27 */ +#define EXTI_EVENR_MR28 ((uint32_t)0x10000000) /* Event Mask on line 28 */ +#define EXTI_EVENR_MR29 ((uint32_t)0x20000000) /* Event Mask on line 29 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ +#define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */ +#define EXTI_RTENR_TR21 ((uint32_t)0x00200000) /* Rising trigger event configuration bit of line 21 */ +#define EXTI_RTENR_TR22 ((uint32_t)0x00400000) /* Rising trigger event configuration bit of line 22 */ +#define EXTI_RTENR_TR23 ((uint32_t)0x00800000) /* Rising trigger event configuration bit of line 23 */ +#define EXTI_RTENR_TR24 ((uint32_t)0x01000000) /* Rising trigger event configuration bit of line 24 */ +#define EXTI_RTENR_TR25 ((uint32_t)0x02000000) /* Rising trigger event configuration bit of line 25 */ +#define EXTI_RTENR_TR26 ((uint32_t)0x04000000) /* Rising trigger event configuration bit of line 26 */ +#define EXTI_RTENR_TR27 ((uint32_t)0x08000000) /* Rising trigger event configuration bit of line 27 */ +#define EXTI_RTENR_TR28 ((uint32_t)0x10000000) /* Rising trigger event configuration bit of line 28 */ +#define EXTI_RTENR_TR29 ((uint32_t)0x20000000) /* Rising trigger event configuration bit of line 29 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ +#define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */ +#define EXTI_FTENR_TR21 ((uint32_t)0x00200000) /* Falling trigger event configuration bit of line 21 */ +#define EXTI_FTENR_TR22 ((uint32_t)0x00400000) /* Falling trigger event configuration bit of line 22 */ +#define EXTI_FTENR_TR23 ((uint32_t)0x00800000) /* Falling trigger event configuration bit of line 23 */ +#define EXTI_FTENR_TR24 ((uint32_t)0x01000000) /* Falling trigger event configuration bit of line 24 */ +#define EXTI_FTENR_TR25 ((uint32_t)0x02000000) /* Falling trigger event configuration bit of line 25 */ +#define EXTI_FTENR_TR26 ((uint32_t)0x04000000) /* Falling trigger event configuration bit of line 26 */ +#define EXTI_FTENR_TR27 ((uint32_t)0x08000000) /* Falling trigger event configuration bit of line 27 */ +#define EXTI_FTENR_TR28 ((uint32_t)0x10000000) /* Falling trigger event configuration bit of line 28 */ +#define EXTI_FTENR_TR29 ((uint32_t)0x20000000) /* Falling trigger event configuration bit of line 29 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ +#define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */ +#define EXTI_SWIEVR_SWIEVR21 ((uint32_t)0x00200000) /* Software Interrupt on line 21 */ +#define EXTI_SWIEVR_SWIEVR22 ((uint32_t)0x00400000) /* Software Interrupt on line 22 */ +#define EXTI_SWIEVR_SWIEVR23 ((uint32_t)0x00800000) /* Software Interrupt on line 23 */ +#define EXTI_SWIEVR_SWIEVR24 ((uint32_t)0x01000000) /* Software Interrupt on line 24 */ +#define EXTI_SWIEVR_SWIEVR25 ((uint32_t)0x02000000) /* Software Interrupt on line 25 */ +#define EXTI_SWIEVR_SWIEVR26 ((uint32_t)0x04000000) /* Software Interrupt on line 26 */ +#define EXTI_SWIEVR_SWIEVR27 ((uint32_t)0x08000000) /* Software Interrupt on line 27 */ +#define EXTI_SWIEVR_SWIEVR28 ((uint32_t)0x10000000) /* Software Interrupt on line 28 */ +#define EXTI_SWIEVR_SWIEVR29 ((uint32_t)0x20000000) /* Software Interrupt on line 29 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ +#define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */ +#define EXTI_INTF_INTF21 ((uint32_t)0x00200000) /* Pending bit for line 21 */ +#define EXTI_INTF_INTF22 ((uint32_t)0x00400000) /* Pending bit for line 22 */ +#define EXTI_INTF_INTF23 ((uint32_t)0x00800000) /* Pending bit for line 23 */ +#define EXTI_INTF_INTF24 ((uint32_t)0x01000000) /* Pending bit for line 24 */ +#define EXTI_INTF_INTF25 ((uint32_t)0x02000000) /* Pending bit for line 25 */ +#define EXTI_INTF_INTF26 ((uint32_t)0x04000000) /* Pending bit for line 26 */ +#define EXTI_INTF_INTF27 ((uint32_t)0x08000000) /* Pending bit for line 27 */ +#define EXTI_INTF_INTF28 ((uint32_t)0x10000000) /* Pending bit for line 28 */ +#define EXTI_INTF_INTF29 ((uint32_t)0x20000000) /* Pending bit for line 29 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ + +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_FWAKE_FLAG ((uint8_t)0x40) /* Flag of wake */ +#define FLASH_STATR_TURBO ((uint8_t)0x80) /* The state of TURBO Enable */ +#define FLASH_STATR_BOOT_AVA ((uint16_t)0x1000) /* The state of Init Config */ +#define FLASH_STATR_BOOT_STATUS ((uint16_t)0x2000) /* The source of Execute Program */ +#define FLASH_STATR_BOOT_MODE ((uint16_t)0x4000) /* The switch of user section or boot section*/ +#define FLASH_STATR_BOOT_LOCK ((uint16_t)0x8000) /* Lock boot area*/ + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */ +#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ +#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ +#define FLASH_CTLR_OBWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FWAKEIE ((uint32_t)0x00002000) /* Wake inter Enable */ +#define FLASH_CTLR_FLOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_FTPG ((uint32_t)0x00010000) /* Fast Program */ +#define FLASH_CTLR_FTER ((uint32_t)0x00020000) /* Fast Erase */ +#define FLASH_CTLR_BUFLOAD ((uint32_t)0x00040000) /* BUF Load */ +#define FLASH_CTLR_BUFRST ((uint32_t)0x00080000) /* BUF Reset */ +#define FLASH_CTLR_BER32 ((uint32_t)0x00800000) /* Block Erase 32K */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x007C) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_CFGRSTT ((uint16_t)0x0060) /* Config Reset delay time */ + +#define FLASH_OBR_FIX_11 ((uint16_t)0x0300) /* fix 11 */ +#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) /* Data byte0 */ +#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) /* Data byte1 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_MODEKEYR register ******************/ +#define FLASH_MODEKEYR_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open fast program /erase */ +#define FLASH_MODEKEYR_MODEKEYR1 ((uint32_t)0x45670123) +#define FLASH_MODEKEYR_MODEKEYR2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for BOOT_MODEKEYP register ******************/ +#define BOOT_MODEKEYP_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open Boot section */ +#define BOOT_MODEKEYP_MODEKEYR1 ((uint32_t)0x45670123) +#define BOOT_MODEKEYP_MODEKEYR2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ +#define GPIO_INDR_IDR16 ((uint32_t)0x10000) /* Port input data, bit 16 */ +#define GPIO_INDR_IDR17 ((uint32_t)0x20000) /* Port input data, bit 17 */ +#define GPIO_INDR_IDR18 ((uint32_t)0x40000) /* Port input data, bit 18 */ +#define GPIO_INDR_IDR19 ((uint32_t)0x80000) /* Port input data, bit 19 */ +#define GPIO_INDR_IDR20 ((uint32_t)0x100000) /* Port input data, bit 20 */ +#define GPIO_INDR_IDR21 ((uint32_t)0x200000) /* Port input data, bit 21 */ +#define GPIO_INDR_IDR22 ((uint32_t)0x400000) /* Port input data, bit 22 */ +#define GPIO_INDR_IDR23 ((uint32_t)0x800000) /* Port input data, bit 23 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ +#define GPIO_OUTDR_ODR16 ((uint32_t)0x10000) /* Port output data, bit 16 */ +#define GPIO_OUTDR_ODR17 ((uint32_t)0x20000) /* Port output data, bit 17 */ +#define GPIO_OUTDR_ODR18 ((uint32_t)0x40000) /* Port output data, bit 18 */ +#define GPIO_OUTDR_ODR19 ((uint32_t)0x80000) /* Port output data, bit 19 */ +#define GPIO_OUTDR_ODR20 ((uint32_t)0x100000) /* Port output data, bit 20 */ +#define GPIO_OUTDR_ODR21 ((uint32_t)0x200000) /* Port output data, bit 21 */ +#define GPIO_OUTDR_ODR22 ((uint32_t)0x400000) /* Port output data, bit 22 */ +#define GPIO_OUTDR_ODR23 ((uint32_t)0x800000) /* Port output data, bit 23 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ +#define GPIO_BCR_BR16 ((uint32_t)0x10000) /* Port x Reset bit 16 */ +#define GPIO_BCR_BR17 ((uint32_t)0x20000) /* Port x Reset bit 17 */ +#define GPIO_BCR_BR18 ((uint32_t)0x40000) /* Port x Reset bit 18 */ +#define GPIO_BCR_BR19 ((uint32_t)0x80000) /* Port x Reset bit 19 */ +#define GPIO_BCR_BR20 ((uint32_t)0x100000) /* Port x Reset bit 20 */ +#define GPIO_BCR_BR21 ((uint32_t)0x200000) /* Port x Reset bit 21 */ +#define GPIO_BCR_BR22 ((uint32_t)0x400000) /* Port x Reset bit 22 */ +#define GPIO_BCR_BR23 ((uint32_t)0x800000) /* Port x Reset bit 23 */ + + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCK16 ((uint32_t)0x00010000) /* Port x Lock bit 16 */ +#define GPIO_LCK17 ((uint32_t)0x00020000) /* Port x Lock bit 17 */ +#define GPIO_LCK18 ((uint32_t)0x00040000) /* Port x Lock bit 18 */ +#define GPIO_LCK19 ((uint32_t)0x00080000) /* Port x Lock bit 19 */ +#define GPIO_LCK20 ((uint32_t)0x00100000) /* Port x Lock bit 20 */ +#define GPIO_LCK21 ((uint32_t)0x00200000) /* Port x Lock bit 21 */ +#define GPIO_LCK22 ((uint32_t)0x00400000) /* Port x Lock bit 22 */ +#define GPIO_LCK23 ((uint32_t)0x00800000) /* Port x Lock bit 23 */ + +#define GPIO_LCKK ((uint32_t)0x01000000) /* Lock key */ + +/******************* Bit definition for GPIO_CFGXR register *******************/ +#define GPIO_CFGXR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGXR_MODE16 ((uint32_t)0x00000003) /* MODE16[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGXR_MODE16_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGXR_MODE16_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGXR_MODE17 ((uint32_t)0x00000030) /* MODE17[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGXR_MODE17_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGXR_MODE17_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGXR_MODE18 ((uint32_t)0x00000300) /* MODE18[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGXR_MODE18_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGXR_MODE18_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGXR_MODE19 ((uint32_t)0x00003000) /* MODE19[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGXR_MODE19_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGXR_MODE19_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE20 ((uint32_t)0x00030000) /* MODE20[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGXR_MODE20_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGXR_MODE20_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE21 ((uint32_t)0x00300000) /* MODE21[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGXR_MODE21_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGXR_MODE21_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE22 ((uint32_t)0x03000000) /* MODE22[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGXR_MODE22_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGXR_MODE22_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE23 ((uint32_t)0x30000000) /* MODE23[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGXR_MODE23_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGXR_MODE23_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGXR_CNF16 ((uint32_t)0x0000000C) /* CNF16[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGXR_CNF16_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGXR_CNF16_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGXR_CNF17 ((uint32_t)0x000000C0) /* CNF17[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGXR_CNF17_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGXR_CNF17_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGXR_CNF18 ((uint32_t)0x00000C00) /* CNF18[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGXR_CNF18_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGXR_CNF18_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGXR_CNF19 ((uint32_t)0x0000C000) /* CNF19[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGXR_CNF19_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGXR_CNF19_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF20 ((uint32_t)0x000C0000) /* CNF20[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGXR_CNF20_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGXR_CNF20_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF21 ((uint32_t)0x00C00000) /* CNF21[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGXR_CNF21_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGXR_CNF21_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF22 ((uint32_t)0x0C000000) /* CNF22[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGXR_CNF22_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGXR_CNF22_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF23 ((uint32_t)0xC0000000) /* CNF23[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGXR_CNF23_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGXR_CNF23_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/****************** Bit definition for GPIO_BSXR register *******************/ +#define GPIO_BSXR_BS16 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSXR_BS17 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSXR_BS18 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSXR_BS19 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSXR_BS20 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSXR_BS21 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSXR_BS22 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSXR_BS23 ((uint32_t)0x00000080) /* Port x Set bit 7 */ + +#define GPIO_BSXR_BR16 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSXR_BR17 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSXR_BR18 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSXR_BR19 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSXR_BR20 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSXR_BR21 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSXR_BR22 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSXR_BR23 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000003) /* SPI1_REMAP[1:0] bits (SPI1 remapping) */ +#define AFIO_PCFR1_SPI1_REMAP_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define AFIO_PCFR1_SPI1_REMAP_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x0000001C) /* I2C1_REMAP[4:2] bits (I2C1 remapping) */ +#define AFIO_PCFR1_I2C1_REMAP_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define AFIO_PCFR1_I2C1_REMAP_1 ((uint32_t)0x00000008) /* Bit 1 */ +#define AFIO_PCFR1_I2C1_REMAP_2 ((uint32_t)0x00000010) /* Bit 2 */ + +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000060) /* USART1_REMAP[6:5] bits (USART1 remapping) */ +#define AFIO_PCFR1_USART1_REMAP_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00000040) /* Bit 1 */ + +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000380) /* USART2_REMAP[9:7] bits (USART2 remapping) */ +#define AFIO_PCFR1_USART2_REMAP_0 ((uint32_t)0x00000080) /* Bit 0 */ +#define AFIO_PCFR1_USART2_REMAP_1 ((uint32_t)0x00000100) /* Bit 1 */ +#define AFIO_PCFR1_USART2_REMAP_2 ((uint32_t)0x00000200) /* Bit 2 */ + +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000C00) /* USART3_REMAP[11:10] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define AFIO_PCFR1_USART4_REMAP ((uint32_t)0x00007000) /* USART4_REMAP[14:12] bits (USART4 remapping) */ +#define AFIO_PCFR1_USART4_REMAP_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define AFIO_PCFR1_USART4_REMAP_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define AFIO_PCFR1_USART4_REMAP_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x00038000) /* TIM1_REMAP[17:15] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define AFIO_PCFR1_TIM1_REMAP_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x001C0000) /* TIM2_REMAP[20:18] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define AFIO_PCFR1_TIM2_REMAP_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00600000) /* TIM3_REMAP[22:21] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00400000) /* Bit 1 */ + +#define AFIO_PCFR1_PIOC_REMAP ((uint32_t)0x00800000) /* PIOC[23] bits (PIOC remapping) */ + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x00000003) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x0000000C) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000030) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x000000C0) /* EXTI 3 configuration */ +#define AFIO_EXTICR1_EXTI4 ((uint32_t)0x00000300) /* EXTI 4 configuration */ +#define AFIO_EXTICR1_EXTI5 ((uint32_t)0x00000C00) /* EXTI 5 configuration */ +#define AFIO_EXTICR1_EXTI6 ((uint32_t)0x00003000) /* EXTI 6 configuration */ +#define AFIO_EXTICR1_EXTI7 ((uint32_t)0x0000C000) /* EXTI 7 configuration */ +#define AFIO_EXTICR1_EXTI8 ((uint32_t)0x00030000) /* EXTI 8 configuration */ +#define AFIO_EXTICR1_EXTI9 ((uint32_t)0x000C0000) /* EXTI 9 configuration */ +#define AFIO_EXTICR1_EXTI10 ((uint32_t)0x00300000) /* EXTI 10 configuration */ +#define AFIO_EXTICR1_EXTI11 ((uint32_t)0x00C00000) /* EXTI 11 configuration */ +#define AFIO_EXTICR1_EXTI12 ((uint32_t)0x03000000) /* EXTI 12 configuration */ +#define AFIO_EXTICR1_EXTI13 ((uint32_t)0x0C000000) /* EXTI 13 configuration */ +#define AFIO_EXTICR1_EXTI14 ((uint32_t)0x30000000) /* EXTI 14 configuration */ +#define AFIO_EXTICR1_EXTI15 ((uint32_t)0xC0000000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /* PC[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000004) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000008) /* PC[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000010) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000020) /* PC[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00000040) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00000080) /* PC[3] pin */ + +#define AFIO_EXTICR1_EXTI4_PA ((uint32_t)0x00000000) /* PA[4] pin */ +#define AFIO_EXTICR1_EXTI4_PB ((uint32_t)0x00000100) /* PB[4] pin */ +#define AFIO_EXTICR1_EXTI4_PC ((uint32_t)0x00000200) /* PC[4] pin */ + +#define AFIO_EXTICR1_EXTI5_PA ((uint32_t)0x00000000) /* PA[5] pin */ +#define AFIO_EXTICR1_EXTI5_PB ((uint32_t)0x00000400) /* PB[5] pin */ +#define AFIO_EXTICR1_EXTI5_PC ((uint32_t)0x00000800) /* PC[5] pin */ + +#define AFIO_EXTICR1_EXTI6_PA ((uint32_t)0x00000000) /* PA[6] pin */ +#define AFIO_EXTICR1_EXTI6_PB ((uint32_t)0x00001000) /* PB[6] pin */ +#define AFIO_EXTICR1_EXTI6_PC ((uint32_t)0x00002000) /* PC[6] pin */ + +#define AFIO_EXTICR1_EXTI7_PA ((uint32_t)0x00000000) /* PA[7] pin */ +#define AFIO_EXTICR1_EXTI7_PB ((uint32_t)0x00004000) /* PB[7] pin */ +#define AFIO_EXTICR1_EXTI7_PC ((uint32_t)0x00008000) /* PC[7] pin */ + +#define AFIO_EXTICR1_EXTI8_PA ((uint32_t)0x00000000) /* PA[8] pin */ +#define AFIO_EXTICR1_EXTI8_PB ((uint32_t)0x00010000) /* PB[8] pin */ +#define AFIO_EXTICR1_EXTI8_PC ((uint32_t)0x00020000) /* PC[8] pin */ + +#define AFIO_EXTICR1_EXTI9_PA ((uint32_t)0x00000000) /* PA[9] pin */ +#define AFIO_EXTICR1_EXTI9_PB ((uint32_t)0x00040000) /* PB[9] pin */ +#define AFIO_EXTICR1_EXTI9_PC ((uint32_t)0x00080000) /* PC[9] pin */ + +#define AFIO_EXTICR1_EXTI10_PA ((uint32_t)0x00000000) /* PA[10] pin */ +#define AFIO_EXTICR1_EXTI10_PB ((uint32_t)0x00100000) /* PB[10] pin */ +#define AFIO_EXTICR1_EXTI10_PC ((uint32_t)0x00200000) /* PC[10] pin */ + +#define AFIO_EXTICR1_EXTI11_PA ((uint32_t)0x00000000) /* PA[11] pin */ +#define AFIO_EXTICR1_EXTI11_PB ((uint32_t)0x00400000) /* PB[11] pin */ +#define AFIO_EXTICR1_EXTI11_PC ((uint32_t)0x00800000) /* PC[11] pin */ + +#define AFIO_EXTICR1_EXTI12_PA ((uint32_t)0x00000000) /* PA[12] pin */ +#define AFIO_EXTICR1_EXTI12_PB ((uint32_t)0x01000000) /* PB[12] pin */ +#define AFIO_EXTICR1_EXTI12_PC ((uint32_t)0x02000000) /* PC[12] pin */ + +#define AFIO_EXTICR1_EXTI13_PA ((uint32_t)0x00000000) /* PA[13] pin */ +#define AFIO_EXTICR1_EXTI13_PB ((uint32_t)0x04000000) /* PB[13] pin */ +#define AFIO_EXTICR1_EXTI13_PC ((uint32_t)0x08000000) /* PC[13] pin */ + +#define AFIO_EXTICR1_EXTI14_PA ((uint32_t)0x00000000) /* PA[14] pin */ +#define AFIO_EXTICR1_EXTI14_PB ((uint32_t)0x10000000) /* PB[14] pin */ +#define AFIO_EXTICR1_EXTI14_PC ((uint32_t)0x20000000) /* PC[14] pin */ + +#define AFIO_EXTICR1_EXTI15_PA ((uint32_t)0x00000000) /* PA[15] pin */ +#define AFIO_EXTICR1_EXTI15_PB ((uint32_t)0x40000000) /* PB[15] pin */ +#define AFIO_EXTICR1_EXTI15_PC ((uint32_t)0x80000000) /* PC[15] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI16 ((uint32_t)0x00000003) /* EXTI 16 configuration */ +#define AFIO_EXTICR2_EXTI17 ((uint32_t)0x0000000C) /* EXTI 17 configuration */ +#define AFIO_EXTICR2_EXTI18 ((uint32_t)0x00000030) /* EXTI 18 configuration */ +#define AFIO_EXTICR2_EXTI19 ((uint32_t)0x000000C0) /* EXTI 19 configuration */ +#define AFIO_EXTICR2_EXTI20 ((uint32_t)0x00000300) /* EXTI 20 configuration */ +#define AFIO_EXTICR2_EXTI21 ((uint32_t)0x00000C00) /* EXTI 21 configuration */ +#define AFIO_EXTICR2_EXTI22 ((uint32_t)0x00003000) /* EXTI 22 configuration */ +#define AFIO_EXTICR2_EXTI23 ((uint32_t)0x0000C000) /* EXTI 23 configuration */ + +#define AFIO_EXTICR2_EXTI16_PA ((uint32_t)0x00000000) /* PA[16] pin */ +#define AFIO_EXTICR2_EXTI16_PB ((uint32_t)0x00000001) /* PB[16] pin */ +#define AFIO_EXTICR2_EXTI16_PC ((uint32_t)0x00000002) /* PC[16] pin */ + +#define AFIO_EXTICR2_EXTI17_PA ((uint32_t)0x00000000) /* PA[17] pin */ +#define AFIO_EXTICR2_EXTI17_PB ((uint32_t)0x00000004) /* PB[17] pin */ +#define AFIO_EXTICR2_EXTI17_PC ((uint32_t)0x00000008) /* PC[17] pin */ + +#define AFIO_EXTICR2_EXTI18_PA ((uint32_t)0x00000000) /* PA[18] pin */ +#define AFIO_EXTICR2_EXTI18_PB ((uint32_t)0x00000010) /* PB[18] pin */ +#define AFIO_EXTICR2_EXTI18_PC ((uint32_t)0x00000020) /* PC[18] pin */ + +#define AFIO_EXTICR2_EXTI19_PA ((uint32_t)0x00000000) /* PA[19] pin */ +#define AFIO_EXTICR2_EXTI19_PB ((uint32_t)0x00000040) /* PB[19] pin */ +#define AFIO_EXTICR2_EXTI19_PC ((uint32_t)0x00000080) /* PC[19] pin */ + +#define AFIO_EXTICR2_EXTI20_PA ((uint32_t)0x00000000) /* PA[20] pin */ +#define AFIO_EXTICR2_EXTI20_PB ((uint32_t)0x00000100) /* PB[20] pin */ +#define AFIO_EXTICR2_EXTI20_PC ((uint32_t)0x00000200) /* PC[20] pin */ + +#define AFIO_EXTICR2_EXTI21_PA ((uint32_t)0x00000000) /* PA[21] pin */ +#define AFIO_EXTICR2_EXTI21_PB ((uint32_t)0x00000400) /* PB[21] pin */ +#define AFIO_EXTICR2_EXTI21_PC ((uint32_t)0x00000800) /* PC[21] pin */ + +#define AFIO_EXTICR2_EXTI22_PA ((uint32_t)0x00000000) /* PA[22] pin */ +#define AFIO_EXTICR2_EXTI22_PB ((uint32_t)0x00001000) /* PB[22] pin */ +#define AFIO_EXTICR2_EXTI22_PC ((uint32_t)0x00002000) /* PC[22] pin */ + +#define AFIO_EXTICR2_EXTI23_PA ((uint32_t)0x00000000) /* PA[23] pin */ +#define AFIO_EXTICR2_EXTI23_PB ((uint32_t)0x00004000) /* PB[23] pin */ +#define AFIO_EXTICR2_EXTI23_PC ((uint32_t)0x00008000) /* PC[23] pin */ + +/******************* Bit definition for AFIO_CTLR register ********************/ +#define AFIO_CTLR_UDM_PUE ((uint32_t)0x00000003) /* PC16/UDM Pin pull-up Mode*/ +#define AFIO_CTLR_UDM_PUE_0 ((uint32_t)0x00000001) /* bit[0] */ +#define AFIO_CTLR_UDM_PUE_1 ((uint32_t)0x00000002) /* bit[1] */ + +#define AFIO_CTLR_UDP_PUE ((uint32_t)0x0000000C) /* PC17/UDP Pin pull-up Mode*/ +#define AFIO_CTLR_UDP_PUE_0 ((uint32_t)0x00000004) /* bit[2] */ +#define AFIO_CTLR_UDP_PUE_1 ((uint32_t)0x00000008) /* bit[3] */ + +#define AFIO_CTLR_USB_PHY_V33 ((uint32_t)0x00000040) /* USB transceiver PHY output and pull-up limiter configuration */ +#define AFIO_CTLR_USB_IOEN ((uint32_t)0x00000080) /* USB Remap pin enable */ +#define AFIO_CTLR_USBPD_PHY_V33 ((uint32_t)0x00000100) /* USBPD transceiver PHY output and pull-up limiter configuration */ +#define AFIO_CTLR_USBPD_IN_HVT ((uint32_t)0x00000200) /* PD pin PC14/PC15 high threshold input mode */ +#define AFIO_CTLR_UDP_BC_VSRC ((uint32_t)0x00010000) /* PC17/UDP pin BC protocol source voltage enable */ +#define AFIO_CTLR_UDM_BC_VSRC ((uint32_t)0x00020000) /* PC16/UDM pin BC protocol source voltage enable */ +#define AFIO_CTLR_UDP_BC_CMPO ((uint32_t)0x00040000) /* PC17/UDP pin BC protocol comparator status */ +#define AFIO_CTLR_UDM_BC_CMPO ((uint32_t)0x00080000) /* PC16/UDM pin BC protocol comparator status */ +#define AFIO_CTLR_PA3_FILT_EN ((uint32_t)0x01000000) /* Controls the input filtering of the PA3 pin */ +#define AFIO_CTLR_PA4_FILT_EN ((uint32_t)0x02000000) /* Controls the input filtering of the PA4 pin */ +#define AFIO_CTLR_PB5_FILT_EN ((uint32_t)0x04000000) /* Controls the input filtering of the PB5 pin */ +#define AFIO_CTLR_PB6_FILT_EN ((uint32_t)0x08000000) /* Controls the input filtering of the PB6 pin */ + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ + +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ + +#define PWR_CTLR_PLS ((uint16_t)0x0060) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) /* PVD level 0 */ +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) /* PVD level 1 */ +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) /* PVD level 2 */ +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) /* PVD level 3 */ + +#define PWR_CTLR_LP_REG ((uint16_t)0x0200) /* Software configure flash into lower energy mode */ +#define PWR_CTLR_LP ((uint16_t)0x0C00) /* Software configure flash Status */ +#define PWR_CTLR_LP_0 ((uint16_t)0x0400) +#define PWR_CTLR_LP_1 ((uint16_t)0x0800) + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_Flash_ack ((uint16_t)0x0200) /* Flash Status */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ +#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ +#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_USART4RST ((uint32_t)0x00080000) /* USART 4 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint32_t)0x00000001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint32_t)0x00000004) /* SRAM interface clock enable */ +#define RCC_USBFS ((uint32_t)0x00001000) /* USBFS clock enable */ +#define RCC_USBPD ((uint32_t)0x00020000) /* USBPD clock enable */ + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_USART3EN ((uint32_t)0x00040000) /* USART 3 clock enable */ +#define RCC_USART4EN ((uint32_t)0x00080000) /* USART 4 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_OPARSTF ((uint32_t)0x02000000) /* OPA reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************* Bit definition for RCC_AHBRSTR register ********************/ +#define RCC_USBFSRST ((uint32_t)0x00001000) /* USBFS reset */ +#define RCC_PIOCRST ((uint32_t)0x00002000) /* PIOC RST */ +#define RCC_USBPDRST ((uint32_t)0x00020000) /* USBPD reset */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ +#define SPI_CTLR2_ODEN ((uint16_t)0x8000) /* SPI OD output Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register *****************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) /* Read Enable under SPI High speed mode */ + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_CMP_BK ((uint16_t)0x1000) /* voltage comparator break enable, TIM1 only */ +#define TIM_CAPOV ((uint16_t)0x4000) /* Cfg mode of capture value */ +#define TIM_CAPLVL ((uint16_t)0x8000) + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ +#define TIM_LEVEL1 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ +#define TIM_LEVEL2 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ +#define TIM_LEVEL3 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ +#define TIM_LEVEL4 ((uint32_t)0x00010000) + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************* Bit definition for TIM_SPEC register *******************/ +#define TIM_SPEC_PWM_EN_1_2 ((uint16_t)0x0001) /* Channel 1 and Channel 2 alternate */ +#define TIM_SPEC_PWM_EN_3_4 ((uint16_t)0x0002) /* Channel 3 and Channel 4 alternate */ +#define TIM_SPEC_PWM_OC1 ((uint16_t)0x0010) /* Channel 1 invalid level under alternate mode */ +#define TIM_SPEC_PWM_OC2 ((uint16_t)0x0020) /* Channel 2 invalid level under alternate mode */ +#define TIM_SPEC_PWM_OC3 ((uint16_t)0x0040) /* Channel 3 invalid level under alternate mode */ +#define TIM_SPEC_PWM_OC4 ((uint16_t)0x0080) /* Channel 4 invalid level under alternate mode */ +#define TIM_SPEC_TOGGLE ((uint16_t)0x8000) /* valid channel indicator */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* OPA and CMP */ +/******************************************************************************/ + +/******************* Bit definition for OPA_CFGR1 register ********************/ +#define OPA_CFGR1_POLL_EN1 ((uint16_t)0x0001) +#define OPA_CFGR1_POLL_EN2 ((uint16_t)0x0002) +#define OPA_CFGR1_BKIN_EN1 ((uint16_t)0x0004) +#define OPA_CFGR1_BKIN_EN2 ((uint16_t)0x0008) +#define OPA_CFGR1_RST_EN1 ((uint16_t)0x0010) +#define OPA_CFGR1_RST_EN2 ((uint16_t)0x0020) +#define OPA_CFGR1_BKIN_SEL ((uint16_t)0x0040) +#define OPA_CFGR1_POLL_LOCK ((uint16_t)0x0080) +#define OPA_CFGR1_IE_OUT1 ((uint16_t)0x0100) +#define OPA_CFGR1_IE_OUT2 ((uint16_t)0x0200) +#define OPA_CFGR1_IE_CNT ((uint16_t)0x0400) +#define OPA_CFGR1_NMI_EN ((uint16_t)0x0800) +#define OPA_CFGR1_IF_OUT1 ((uint16_t)0x1000) +#define OPA_CFGR1_IF_OUT2 ((uint16_t)0x2000) +#define OPA_CFGR1_IF_CNT ((uint16_t)0x4000) + +/******************* Bit definition for OPA_CFGR2 register ********************/ +#define OPA_CFGR2_POLL_VLU ((uint16_t)0x01FF) +#define OPA_CFGR2_POLL1_NUM ((uint16_t)0x0600) +#define OPA_CFGR2_POLL2_NUM ((uint16_t)0x1800) + +/******************* Bit definition for OPA_CTLR1 register ********************/ +#define OPA_CTLR1_EN1 ((uint32_t)0x00000001) +#define OPA_CTLR1_MODE1 ((uint32_t)0x00000002) + +#define OPA_CTLR1_PSEL1 ((uint32_t)0x00000018) + +#define OPA_CTLR1_FB_EN1 ((uint32_t)0x00000020) +#define OPA_CTLR1_NSEL1 ((uint32_t)0x000001C0) + +#define OPA_CTLR1_EN2 ((uint32_t)0x00010000) +#define OPA_CTLR1_MODE2 ((uint32_t)0x00020000) + +#define OPA_CTLR1_PSEL2 ((uint32_t)0x00180000) + +#define OPA_CTLR1_FB_EN2 ((uint32_t)0x00200000) +#define OPA_CTLR1_NSEL2 ((uint32_t)0x01C00000) + +#define OPA_CTLR1_OPA_LOCK ((uint32_t)0x80000000) + +/******************* Bit definition for OPA_CTLR2 register ********************/ +#define OPA_CTLR2_EN1 ((uint32_t)0x00000001) +#define OPA_CTLR2_MODE1 ((uint32_t)0x00000002) +#define OPA_CTLR2_NSEL1 ((uint32_t)0x00000004) +#define OPA_CTLR2_PSEL1 ((uint32_t)0x00000008) + +#define OPA_CTLR2_EN2 ((uint32_t)0x00000020) +#define OPA_CTLR2_MODE2 ((uint32_t)0x00000040) +#define OPA_CTLR2_NSEL2 ((uint32_t)0x00000080) +#define OPA_CTLR2_PSEL2 ((uint32_t)0x00000100) + +#define OPA_CTLR2_EN3 ((uint32_t)0x00000400) +#define OPA_CTLR2_MODE3 ((uint32_t)0x00000800) +#define OPA_CTLR2_NSEL3 ((uint32_t)0x00001000) +#define OPA_CTLR2_PSEL3 ((uint32_t)0x00002000) + +#define OPA_CTLR2_CMP_LOCK ((uint32_t)0x00002000) + +/******************* Bit definition for OPA_KEY register ********************/ +#define OPA_KEY ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for CMP_KEY register ********************/ +#define CMP_KEY ((uint32_t)0xFFFFFFFF) + +/******************* Bit definition for POLL_KEY register ********************/ +#define POLL_KEY ((uint32_t)0xFFFFFFFF) + +#include "ch32x035_conf.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_adc.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_adc.h index d3be07b..c438ae7 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_adc.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_adc.h @@ -1,210 +1,210 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_adc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the - * ADC firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_ADC_H -#define __CH32X035_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* ADC Init structure definition */ -typedef struct -{ - uint32_t ADC_Mode; /* Configures the ADC to operate in independent or - dual mode. - This parameter can be a value of @ref ADC_mode */ - - FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in - Scan (multichannels) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ - - uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. - This parameter can be a value of @ref ADC_OutputBuffer */ - - uint32_t ADC_Pga; /* Specifies the PGA gain multiple. - This parameter can be a value of @ref ADC_Pga */ -} ADC_InitTypeDef; - -/* ADC_mode */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) - -/* ADC_external_trigger_sources_for_regular_channels_conversion */ -#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) -#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) -#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x000C0000) -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) - -/* ADC_data_align */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) - -/* ADC_channels */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) - -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_15) - -/* ADC_sampling_time */ -#define ADC_SampleTime_4Cycles ((uint8_t)0x00) -#define ADC_SampleTime_5Cycles ((uint8_t)0x01) -#define ADC_SampleTime_6Cycles ((uint8_t)0x02) -#define ADC_SampleTime_7Cycles ((uint8_t)0x03) -#define ADC_SampleTime_8Cycles ((uint8_t)0x04) -#define ADC_SampleTime_9Cycles ((uint8_t)0x05) -#define ADC_SampleTime_10Cycles ((uint8_t)0x06) -#define ADC_SampleTime_11Cycles ((uint8_t)0x07) - -/* ADC_external_trigger_sources_for_injected_channels_conversion */ -#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) -#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) -#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) -#define ADC_ExternalTrigInjecConv_T2_CC2 ((uint32_t)0x00004000) -#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00005000) -#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x00006000) -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) - -/* ADC_injected_channel_selection */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) - -/* ADC_analog_watchdog_selection */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -/* ADC_interrupts_definition */ -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) - -/* ADC_flags_definition */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) - -/* ADC_analog_watchdog_reset_enable_selection */ -#define ADC_AnalogWatchdog_0_RST_EN ((uint32_t)0x00001000) -#define ADC_AnalogWatchdog_1_RST_EN ((uint32_t)0x00002000) -#define ADC_AnalogWatchdog_2_RST_EN ((uint32_t)0x00004000) -#define ADC_AnalogWatchdog_3_RST_EN ((uint32_t)0x00008000) - -/* ADC_analog_watchdog_reset_flags_definition */ -#define ADC_AnalogWatchdogResetFLAG_0 ((uint32_t)0x00010000) -#define ADC_AnalogWatchdogResetFLAG_1 ((uint32_t)0x00020000) -#define ADC_AnalogWatchdogResetFLAG_2 ((uint32_t)0x00040000) -#define ADC_AnalogWatchdogResetFLAG_3 ((uint32_t)0x00080000) - -/* ADC_clock */ -#define ADC_CLK_Div4 ((uint32_t)0x00000013) -#define ADC_CLK_Div5 ((uint32_t)0x00000014) -#define ADC_CLK_Div6 ((uint32_t)0x00000025) -#define ADC_CLK_Div7 ((uint32_t)0x00000026) -#define ADC_CLK_Div8 ((uint32_t)0x00000037) -#define ADC_CLK_Div9 ((uint32_t)0x00000038) -#define ADC_CLK_Div10 ((uint32_t)0x00000049) -#define ADC_CLK_Div11 ((uint32_t)0x0000004A) -#define ADC_CLK_Div12 ((uint32_t)0x0000005B) -#define ADC_CLK_Div13 ((uint32_t)0x0000005C) -#define ADC_CLK_Div14 ((uint32_t)0x0000006D) -#define ADC_CLK_Div15 ((uint32_t)0x0000006E) -#define ADC_CLK_Div16 ((uint32_t)0x0000007F) - - -void ADC_DeInit(ADC_TypeDef *ADCx); -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); -void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); -void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); -uint32_t ADC_GetDualModeConversionValue(void); -void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); -void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); -void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); -void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog_x, FunctionalState NewState); -void ADC_AnalogWatchdogScanCmd(ADC_TypeDef *ADCx, FunctionalState NewState); -void ADC_CLKConfig(ADC_TypeDef *ADCx, uint32_t ADC_CLK_Div_x); - - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_adc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * ADC firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_ADC_H +#define __CH32X035_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align, Note:ADC_DataAlign_Left only applies to regular channels */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ + + uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. + This parameter can be a value of @ref ADC_OutputBuffer */ + + uint32_t ADC_Pga; /* Specifies the PGA gain multiple. + This parameter can be a value of @ref ADC_Pga */ +} ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) + +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_15) + +/* ADC_sampling_time */ +#define ADC_SampleTime_4Cycles ((uint8_t)0x00) +#define ADC_SampleTime_5Cycles ((uint8_t)0x01) +#define ADC_SampleTime_6Cycles ((uint8_t)0x02) +#define ADC_SampleTime_7Cycles ((uint8_t)0x03) +#define ADC_SampleTime_8Cycles ((uint8_t)0x04) +#define ADC_SampleTime_9Cycles ((uint8_t)0x05) +#define ADC_SampleTime_10Cycles ((uint8_t)0x06) +#define ADC_SampleTime_11Cycles ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T2_CC2 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +/* ADC_analog_watchdog_reset_enable_selection */ +#define ADC_AnalogWatchdog_0_RST_EN ((uint32_t)0x00001000) +#define ADC_AnalogWatchdog_1_RST_EN ((uint32_t)0x00002000) +#define ADC_AnalogWatchdog_2_RST_EN ((uint32_t)0x00004000) +#define ADC_AnalogWatchdog_3_RST_EN ((uint32_t)0x00008000) + +/* ADC_analog_watchdog_reset_flags_definition */ +#define ADC_AnalogWatchdogResetFLAG_0 ((uint32_t)0x00010000) +#define ADC_AnalogWatchdogResetFLAG_1 ((uint32_t)0x00020000) +#define ADC_AnalogWatchdogResetFLAG_2 ((uint32_t)0x00040000) +#define ADC_AnalogWatchdogResetFLAG_3 ((uint32_t)0x00080000) + +/* ADC_clock */ +#define ADC_CLK_Div4 ((uint32_t)0x00000013) +#define ADC_CLK_Div5 ((uint32_t)0x00000014) +#define ADC_CLK_Div6 ((uint32_t)0x00000025) +#define ADC_CLK_Div7 ((uint32_t)0x00000026) +#define ADC_CLK_Div8 ((uint32_t)0x00000037) +#define ADC_CLK_Div9 ((uint32_t)0x00000038) +#define ADC_CLK_Div10 ((uint32_t)0x00000049) +#define ADC_CLK_Div11 ((uint32_t)0x0000004A) +#define ADC_CLK_Div12 ((uint32_t)0x0000005B) +#define ADC_CLK_Div13 ((uint32_t)0x0000005C) +#define ADC_CLK_Div14 ((uint32_t)0x0000006D) +#define ADC_CLK_Div15 ((uint32_t)0x0000006E) +#define ADC_CLK_Div16 ((uint32_t)0x0000007F) + + +void ADC_DeInit(ADC_TypeDef *ADCx); +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog_x, FunctionalState NewState); +void ADC_AnalogWatchdogScanCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_CLKConfig(ADC_TypeDef *ADCx, uint32_t ADC_CLK_Div_x); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_awu.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_awu.h index 0142551..07064e2 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_awu.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_awu.h @@ -1,48 +1,48 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_awu.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the - * AWU firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_AWU_H -#define __CH32X035_AWU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* PWR_AWU_Prescaler */ -#define AWU_Prescaler_1 ((uint32_t)0x00000000) -#define AWU_Prescaler_2 ((uint32_t)0x00000002) -#define AWU_Prescaler_4 ((uint32_t)0x00000003) -#define AWU_Prescaler_8 ((uint32_t)0x00000004) -#define AWU_Prescaler_16 ((uint32_t)0x00000005) -#define AWU_Prescaler_32 ((uint32_t)0x00000006) -#define AWU_Prescaler_64 ((uint32_t)0x00000007) -#define AWU_Prescaler_128 ((uint32_t)0x00000008) -#define AWU_Prescaler_256 ((uint32_t)0x00000009) -#define AWU_Prescaler_512 ((uint32_t)0x0000000A) -#define AWU_Prescaler_1024 ((uint32_t)0x0000000B) -#define AWU_Prescaler_2048 ((uint32_t)0x0000000C) -#define AWU_Prescaler_4096 ((uint32_t)0x0000000D) -#define AWU_Prescaler_10240 ((uint32_t)0x0000000E) -#define AWU_Prescaler_61440 ((uint32_t)0x0000000F) - - -void AutoWakeUpCmd(FunctionalState NewState); -void AWU_SetPrescaler(uint32_t AWU_Prescaler); -void AWU_SetWindowValue(uint8_t WindowValue); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_awu.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * AWU firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_AWU_H +#define __CH32X035_AWU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* PWR_AWU_Prescaler */ +#define AWU_Prescaler_1 ((uint32_t)0x00000000) +#define AWU_Prescaler_2 ((uint32_t)0x00000002) +#define AWU_Prescaler_4 ((uint32_t)0x00000003) +#define AWU_Prescaler_8 ((uint32_t)0x00000004) +#define AWU_Prescaler_16 ((uint32_t)0x00000005) +#define AWU_Prescaler_32 ((uint32_t)0x00000006) +#define AWU_Prescaler_64 ((uint32_t)0x00000007) +#define AWU_Prescaler_128 ((uint32_t)0x00000008) +#define AWU_Prescaler_256 ((uint32_t)0x00000009) +#define AWU_Prescaler_512 ((uint32_t)0x0000000A) +#define AWU_Prescaler_1024 ((uint32_t)0x0000000B) +#define AWU_Prescaler_2048 ((uint32_t)0x0000000C) +#define AWU_Prescaler_4096 ((uint32_t)0x0000000D) +#define AWU_Prescaler_10240 ((uint32_t)0x0000000E) +#define AWU_Prescaler_61440 ((uint32_t)0x0000000F) + + +void AutoWakeUpCmd(FunctionalState NewState); +void AWU_SetPrescaler(uint32_t AWU_Prescaler); +void AWU_SetWindowValue(uint8_t WindowValue); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_dbgmcu.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_dbgmcu.h index 398db44..5c4e1ac 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_dbgmcu.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_dbgmcu.h @@ -1,41 +1,41 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_dbgmcu.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the - * DBGMCU firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_DBGMCU_H -#define __CH32X035_DBGMCU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) -#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) -#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) - -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -uint32_t __get_DEBUG_CR(void); -void __set_DEBUG_CR(uint32_t value); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -uint32_t DBGMCU_GetCHIPID( void ); -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_dbgmcu.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * DBGMCU firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_DBGMCU_H +#define __CH32X035_DBGMCU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +uint32_t __get_DEBUG_CR(void); +void __set_DEBUG_CR(uint32_t value); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +uint32_t DBGMCU_GetCHIPID( void ); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_dma.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_dma.h index 88b6c87..6cbe2ee 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_dma.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_dma.h @@ -1,184 +1,184 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_dma.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the - * DMA firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_DMA_H -#define __CH32X035_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* DMA Init structure definition */ -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode. - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -} DMA_InitTypeDef; - -/* DMA_data_transfer_direction */ -#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) - -/* DMA_peripheral_incremented_mode */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) - -/* DMA_memory_incremented_mode */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) - -/* DMA_peripheral_data_size */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) - -/* DMA_memory_data_size */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) - -/* DMA_circular_normal_mode */ -#define DMA_Mode_Circular ((uint32_t)0x00000020) -#define DMA_Mode_Normal ((uint32_t)0x00000000) - -/* DMA_priority_level */ -#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) -#define DMA_Priority_High ((uint32_t)0x00002000) -#define DMA_Priority_Medium ((uint32_t)0x00001000) -#define DMA_Priority_Low ((uint32_t)0x00000000) - -/* DMA_memory_to_memory */ -#define DMA_M2M_Enable ((uint32_t)0x00004000) -#define DMA_M2M_Disable ((uint32_t)0x00000000) - -/* DMA_interrupts_definition */ -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) - -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) -#define DMA1_IT_GL8 ((uint32_t)0x10000000) -#define DMA1_IT_TC8 ((uint32_t)0x20000000) -#define DMA1_IT_HT8 ((uint32_t)0x40000000) -#define DMA1_IT_TE8 ((uint32_t)0x80000000) - -/* DMA_flags_definition */ -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) -#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) -#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) -#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) -#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) - -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); -void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); -void DMA_ClearFlag(uint32_t DMAy_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMAy_IT); -void DMA_ClearITPendingBit(uint32_t DMAy_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_dma.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * DMA firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_DMA_H +#define __CH32X035_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) +#define DMA1_IT_GL8 ((uint32_t)0x10000000) +#define DMA1_IT_TC8 ((uint32_t)0x20000000) +#define DMA1_IT_HT8 ((uint32_t)0x40000000) +#define DMA1_IT_TE8 ((uint32_t)0x80000000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) + +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_exti.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_exti.h index 0f16f69..415c2e2 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_exti.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_exti.h @@ -1,99 +1,99 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_exti.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the - * EXTI firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_EXTI_H -#define __CH32X035_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* EXTI mode enumeration */ -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -} EXTIMode_TypeDef; - -/* EXTI Trigger enumeration */ -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -} EXTITrigger_TypeDef; - -/* EXTI Init Structure definition */ -typedef struct -{ - uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -} EXTI_InitTypeDef; - -/* EXTI_Lines */ -#define EXTI_Line0 ((uint32_t)0x00000001) /* External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00000002) /* External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00000004) /* External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00000008) /* External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00000010) /* External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00000020) /* External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00000040) /* External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00000080) /* External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00000100) /* External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00000200) /* External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00000400) /* External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00000800) /* External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x00001000) /* External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x00002000) /* External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x00004000) /* External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x00008000) /* External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x00010000) /* External interrupt line 16 */ -#define EXTI_Line17 ((uint32_t)0x00020000) /* External interrupt line 17 */ -#define EXTI_Line18 ((uint32_t)0x00040000) /* External interrupt line 18 */ -#define EXTI_Line19 ((uint32_t)0x00080000) /* External interrupt line 19 */ -#define EXTI_Line20 ((uint32_t)0x00100000) /* External interrupt line 20 */ -#define EXTI_Line21 ((uint32_t)0x00200000) /* External interrupt line 21 */ -#define EXTI_Line22 ((uint32_t)0x00400000) /* External interrupt line 22 */ -#define EXTI_Line23 ((uint32_t)0x00800000) /* External interrupt line 23 */ -#define EXTI_Line24 ((uint32_t)0x01000000) /* External interrupt line 24 Connected to the PC18(SDI on) */ -#define EXTI_Line25 ((uint32_t)0x02000000) /* External interrupt line 25 Connected to the PC19(SDI on) */ -#define EXTI_Line26 ((uint32_t)0x04000000) /* External interrupt line 26 Connected to the PVD Output */ -#define EXTI_Line27 ((uint32_t)0x08000000) /* External interrupt line 27 Connected to the Auto Wake-up event */ -#define EXTI_Line28 ((uint32_t)0x10000000) /* External interrupt line 28 Connected to the the USBFS Wake-up event */ -#define EXTI_Line29 ((uint32_t)0x20000000) /* External interrupt line 29 Connected to the the USB PD Wake-up event */ - - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_exti.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * EXTI firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_EXTI_H +#define __CH32X035_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitTypeDef; + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00000001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00000002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00000004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00000008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00000010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00000020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00000040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00000080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00000100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00000200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00000400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00000800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x00001000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x00002000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x00004000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x00008000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x00010000) /* External interrupt line 16 */ +#define EXTI_Line17 ((uint32_t)0x00020000) /* External interrupt line 17 */ +#define EXTI_Line18 ((uint32_t)0x00040000) /* External interrupt line 18 */ +#define EXTI_Line19 ((uint32_t)0x00080000) /* External interrupt line 19 */ +#define EXTI_Line20 ((uint32_t)0x00100000) /* External interrupt line 20 */ +#define EXTI_Line21 ((uint32_t)0x00200000) /* External interrupt line 21 */ +#define EXTI_Line22 ((uint32_t)0x00400000) /* External interrupt line 22 */ +#define EXTI_Line23 ((uint32_t)0x00800000) /* External interrupt line 23 */ +#define EXTI_Line24 ((uint32_t)0x01000000) /* External interrupt line 24 Connected to the PC18(SDI on) */ +#define EXTI_Line25 ((uint32_t)0x02000000) /* External interrupt line 25 Connected to the PC19(SDI on) */ +#define EXTI_Line26 ((uint32_t)0x04000000) /* External interrupt line 26 Connected to the PVD Output */ +#define EXTI_Line27 ((uint32_t)0x08000000) /* External interrupt line 27 Connected to the Auto Wake-up event */ +#define EXTI_Line28 ((uint32_t)0x10000000) /* External interrupt line 28 Connected to the the USBFS Wake-up event */ +#define EXTI_Line29 ((uint32_t)0x20000000) /* External interrupt line 29 Connected to the the USB PD Wake-up event */ + + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_flash.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_flash.h index e6b1ce2..54e4bbc 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_flash.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_flash.h @@ -1,144 +1,149 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_flash.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the FLASH - * firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_FLASH_H -#define __CH32X035_FLASH_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* FLASH Status */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT, - FLASH_RDP -} FLASH_Status; - -/* Flash_Latency */ -#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ - -/* Values to be used with devices (1page = 256Byte) */ -#define FLASH_WRProt_Pages0to7 ((uint32_t)0x00000001) /* Write protection of page 0 to 7 */ -#define FLASH_WRProt_Pages8to15 ((uint32_t)0x00000002) /* Write protection of page 8 to 15 */ -#define FLASH_WRProt_Pages16to23 ((uint32_t)0x00000004) /* Write protection of page 16 to 23 */ -#define FLASH_WRProt_Pages24to31 ((uint32_t)0x00000008) /* Write protection of page 24 to 31 */ -#define FLASH_WRProt_Pages32to39 ((uint32_t)0x00000010) /* Write protection of page 32 to 39 */ -#define FLASH_WRProt_Pages40to47 ((uint32_t)0x00000020) /* Write protection of page 40 to 47 */ -#define FLASH_WRProt_Pages48to55 ((uint32_t)0x00000040) /* Write protection of page 48 to 55 */ -#define FLASH_WRProt_Pages56to63 ((uint32_t)0x00000080) /* Write protection of page 56 to 63 */ -#define FLASH_WRProt_Pages64to71 ((uint32_t)0x00000100) /* Write protection of page 64 to 71 */ -#define FLASH_WRProt_Pages72to79 ((uint32_t)0x00000200) /* Write protection of page 72 to 79 */ -#define FLASH_WRProt_Pages80to87 ((uint32_t)0x00000400) /* Write protection of page 80 to 87 */ -#define FLASH_WRProt_Pages88to95 ((uint32_t)0x00000800) /* Write protection of page 88 to 95 */ -#define FLASH_WRProt_Pages96to103 ((uint32_t)0x00001000) /* Write protection of page 96 to 103 */ -#define FLASH_WRProt_Pages104to111 ((uint32_t)0x00002000) /* Write protection of page 104 to 111 */ -#define FLASH_WRProt_Pages112to119 ((uint32_t)0x00004000) /* Write protection of page 112 to 119 */ -#define FLASH_WRProt_Pages120to127 ((uint32_t)0x00008000) /* Write protection of page 120 to 127 */ -#define FLASH_WRProt_Pages128to135 ((uint32_t)0x00010000) /* Write protection of page 128 to 135 */ -#define FLASH_WRProt_Pages136to143 ((uint32_t)0x00020000) /* Write protection of page 136 to 143 */ -#define FLASH_WRProt_Pages144to151 ((uint32_t)0x00040000) /* Write protection of page 144 to 151 */ -#define FLASH_WRProt_Pages152to159 ((uint32_t)0x00080000) /* Write protection of page 152 to 159 */ -#define FLASH_WRProt_Pages160to167 ((uint32_t)0x00100000) /* Write protection of page 160 to 167 */ -#define FLASH_WRProt_Pages168to175 ((uint32_t)0x00200000) /* Write protection of page 168 to 175 */ -#define FLASH_WRProt_Pages176to183 ((uint32_t)0x00400000) /* Write protection of page 176 to 183 */ -#define FLASH_WRProt_Pages184to191 ((uint32_t)0x00800000) /* Write protection of page 184 to 191 */ -#define FLASH_WRProt_Pages192to199 ((uint32_t)0x01000000) /* Write protection of page 192 to 199 */ -#define FLASH_WRProt_Pages200to207 ((uint32_t)0x02000000) /* Write protection of page 200 to 207 */ -#define FLASH_WRProt_Pages208to215 ((uint32_t)0x04000000) /* Write protection of page 208 to 215 */ -#define FLASH_WRProt_Pages216to223 ((uint32_t)0x08000000) /* Write protection of page 216 to 223 */ -#define FLASH_WRProt_Pages224to231 ((uint32_t)0x10000000) /* Write protection of page 224 to 231 */ -#define FLASH_WRProt_Pages232to239 ((uint32_t)0x20000000) /* Write protection of page 232 to 239 */ -#define FLASH_WRProt_Pages240to247 ((uint32_t)0x40000000) /* Write protection of page 240 to 247 */ - - -#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ - -/* Option_Bytes_IWatchdog */ -#define OB_IWDG_SW ((uint8_t)0x01) /* Software IWDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /* Hardware IWDG selected */ - -/* Option_Bytes_nRST_STOP */ -#define OB_STOP_NoRST ((uint8_t)0x02) /* No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /* Reset generated when entering in STOP */ - -/* Option_Bytes_nRST_STDBY */ -#define OB_STDBY_NoRST ((uint8_t)0x04) /* No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /* Reset generated when entering in STANDBY */ - -/* Option_Bytes_RST_ENandDT */ -#define OB_RST_NoEN ((uint8_t)0x18) /* Reset IO disable */ -#define OB_RST_EN_DT12ms ((uint8_t)0x10) /* Reset IO enable and Ignore delay time 12ms */ -#define OB_RST_EN_DT1ms ((uint8_t)0x08) /* Reset IO enable and Ignore delay time 1ms */ -#define OB_RST_EN_DT128us ((uint8_t)0x00) /* Reset IO enable and Ignore delay time 128us */ - -/* FLASH_Interrupts */ -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ - -/* FLASH_Flags */ -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ - -/* System_Reset_Start_Mode */ -#define Start_Mode_USER ((uint32_t)0x00000000) -#define Start_Mode_BOOT ((uint32_t)0x00004000) - - -/*Functions used for all CH32V00x devices*/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); -FLASH_Status FLASH_EnableReadOutProtection(void); -FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_RST); -uint32_t FLASH_GetUserOptionByte(void); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); -void FLASH_Unlock_Fast(void); -void FLASH_Lock_Fast(void); -void FLASH_BufReset(void); -void FLASH_BufLoad(uint32_t Address, uint32_t Data0); -void FLASH_ErasePage_Fast(uint32_t Page_Address); -void FLASH_ProgramPage_Fast(uint32_t Page_Address); -void SystemReset_StartMode(uint32_t Mode); - - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_flash.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the FLASH + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_FLASH_H +#define __CH32X035_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_RDP, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ + +/* Values to be used with devices (1page = 256Byte) */ +#define FLASH_WRProt_Pages0to7 ((uint32_t)0x00000001) /* Write protection of page 0 to 7 */ +#define FLASH_WRProt_Pages8to15 ((uint32_t)0x00000002) /* Write protection of page 8 to 15 */ +#define FLASH_WRProt_Pages16to23 ((uint32_t)0x00000004) /* Write protection of page 16 to 23 */ +#define FLASH_WRProt_Pages24to31 ((uint32_t)0x00000008) /* Write protection of page 24 to 31 */ +#define FLASH_WRProt_Pages32to39 ((uint32_t)0x00000010) /* Write protection of page 32 to 39 */ +#define FLASH_WRProt_Pages40to47 ((uint32_t)0x00000020) /* Write protection of page 40 to 47 */ +#define FLASH_WRProt_Pages48to55 ((uint32_t)0x00000040) /* Write protection of page 48 to 55 */ +#define FLASH_WRProt_Pages56to63 ((uint32_t)0x00000080) /* Write protection of page 56 to 63 */ +#define FLASH_WRProt_Pages64to71 ((uint32_t)0x00000100) /* Write protection of page 64 to 71 */ +#define FLASH_WRProt_Pages72to79 ((uint32_t)0x00000200) /* Write protection of page 72 to 79 */ +#define FLASH_WRProt_Pages80to87 ((uint32_t)0x00000400) /* Write protection of page 80 to 87 */ +#define FLASH_WRProt_Pages88to95 ((uint32_t)0x00000800) /* Write protection of page 88 to 95 */ +#define FLASH_WRProt_Pages96to103 ((uint32_t)0x00001000) /* Write protection of page 96 to 103 */ +#define FLASH_WRProt_Pages104to111 ((uint32_t)0x00002000) /* Write protection of page 104 to 111 */ +#define FLASH_WRProt_Pages112to119 ((uint32_t)0x00004000) /* Write protection of page 112 to 119 */ +#define FLASH_WRProt_Pages120to127 ((uint32_t)0x00008000) /* Write protection of page 120 to 127 */ +#define FLASH_WRProt_Pages128to135 ((uint32_t)0x00010000) /* Write protection of page 128 to 135 */ +#define FLASH_WRProt_Pages136to143 ((uint32_t)0x00020000) /* Write protection of page 136 to 143 */ +#define FLASH_WRProt_Pages144to151 ((uint32_t)0x00040000) /* Write protection of page 144 to 151 */ +#define FLASH_WRProt_Pages152to159 ((uint32_t)0x00080000) /* Write protection of page 152 to 159 */ +#define FLASH_WRProt_Pages160to167 ((uint32_t)0x00100000) /* Write protection of page 160 to 167 */ +#define FLASH_WRProt_Pages168to175 ((uint32_t)0x00200000) /* Write protection of page 168 to 175 */ +#define FLASH_WRProt_Pages176to183 ((uint32_t)0x00400000) /* Write protection of page 176 to 183 */ +#define FLASH_WRProt_Pages184to191 ((uint32_t)0x00800000) /* Write protection of page 184 to 191 */ +#define FLASH_WRProt_Pages192to199 ((uint32_t)0x01000000) /* Write protection of page 192 to 199 */ +#define FLASH_WRProt_Pages200to207 ((uint32_t)0x02000000) /* Write protection of page 200 to 207 */ +#define FLASH_WRProt_Pages208to215 ((uint32_t)0x04000000) /* Write protection of page 208 to 215 */ +#define FLASH_WRProt_Pages216to223 ((uint32_t)0x08000000) /* Write protection of page 216 to 223 */ +#define FLASH_WRProt_Pages224to231 ((uint32_t)0x10000000) /* Write protection of page 224 to 231 */ +#define FLASH_WRProt_Pages232to239 ((uint32_t)0x20000000) /* Write protection of page 232 to 239 */ +#define FLASH_WRProt_Pages240to247 ((uint32_t)0x40000000) /* Write protection of page 240 to 247 */ + + +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint8_t)0x01) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint8_t)0x02) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint8_t)0x04) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /* Reset generated when entering in STANDBY */ + +/* Option_Bytes_RST_ENandDT */ +#define OB_RST_NoEN ((uint8_t)0x18) /* Reset IO disable */ +#define OB_RST_EN_DT12ms ((uint8_t)0x10) /* Reset IO enable and Ignore delay time 12ms */ +#define OB_RST_EN_DT1ms ((uint8_t)0x08) /* Reset IO enable and Ignore delay time 1ms */ +#define OB_RST_EN_DT128us ((uint8_t)0x00) /* Reset IO enable and Ignore delay time 128us */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/* System_Reset_Start_Mode */ +#define Start_Mode_USER ((uint32_t)0x00000000) +#define Start_Mode_BOOT ((uint32_t)0x00004000) + + +/*Functions used for all CH32V00x devices*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_EnableReadOutProtection(void); +FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_RST); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_BufReset(void); +void FLASH_BufLoad(uint32_t Address, uint32_t Data0); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address); +void SystemReset_StartMode(uint32_t Mode); +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_gpio.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_gpio.h index c788e28..d068b83 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_gpio.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_gpio.h @@ -1,183 +1,181 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_gpio.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the - * GPIO firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_GPIO_H -#define __CH32X035_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* Output Maximum frequency selection */ -typedef enum -{ - GPIO_Speed_50MHz = 1, -} GPIOSpeed_TypeDef; - -/* Configuration Mode enumeration */ -typedef enum -{ - GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, /* Only PA0--PA15 and PC16--PC17 support input pull-down */ - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 -} GPIOMode_TypeDef; - -/* GPIO Init structure definition */ -typedef struct -{ - uint32_t GPIO_Pin; /* Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -} GPIO_InitTypeDef; - -/* Bit_SET and Bit_RESET enumeration */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -} BitAction; - -/* GPIO_pins_define */ -#define GPIO_Pin_0 ((uint32_t)0x000001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint32_t)0x000002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint32_t)0x000004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint32_t)0x000008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint32_t)0x000010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint32_t)0x000020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint32_t)0x000040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint32_t)0x000080) /* Pin 7 selected */ -#define GPIO_Pin_8 ((uint32_t)0x000100) /* Pin 8 selected */ -#define GPIO_Pin_9 ((uint32_t)0x000200) /* Pin 9 selected */ -#define GPIO_Pin_10 ((uint32_t)0x000400) /* Pin 10 selected */ -#define GPIO_Pin_11 ((uint32_t)0x000800) /* Pin 11 selected */ -#define GPIO_Pin_12 ((uint32_t)0x001000) /* Pin 12 selected */ -#define GPIO_Pin_13 ((uint32_t)0x002000) /* Pin 13 selected */ -#define GPIO_Pin_14 ((uint32_t)0x004000) /* Pin 14 selected */ -#define GPIO_Pin_15 ((uint32_t)0x008000) /* Pin 15 selected */ -#define GPIO_Pin_16 ((uint32_t)0x010000) /* Pin 16 selected */ -#define GPIO_Pin_17 ((uint32_t)0x020000) /* Pin 17 selected */ -#define GPIO_Pin_18 ((uint32_t)0x040000) /* Pin 18 selected */ -#define GPIO_Pin_19 ((uint32_t)0x080000) /* Pin 19 selected */ -#define GPIO_Pin_20 ((uint32_t)0x100000) /* Pin 20 selected */ -#define GPIO_Pin_21 ((uint32_t)0x200000) /* Pin 21 selected */ -#define GPIO_Pin_22 ((uint32_t)0x400000) /* Pin 22 selected */ -#define GPIO_Pin_23 ((uint32_t)0x800000) /* Pin 23 selected */ -#define GPIO_Pin_All ((uint32_t)0xFFFFFF) /* All pins selected */ - -/* GPIO_Remap_define */ -/* PCFR1 */ -#define GPIO_PartialRemap1_SPI1 ((uint32_t)0x00100001) /* SPI1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_SPI1 ((uint32_t)0x00100002) /* SPI1 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_SPI1 ((uint32_t)0x00100003) /* SPI1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_I2C1 ((uint32_t)0x08000004) /* I2C1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_I2C1 ((uint32_t)0x08000008) /* I2C1 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_I2C1 ((uint32_t)0x0800000C) /* I2C1 Partial3 Alternate Function mapping */ -#define GPIO_PartialRemap4_I2C1 ((uint32_t)0x08000010) /* I2C1 Partial4 Alternate Function mapping */ -#define GPIO_FullRemap_I2C1 ((uint32_t)0x08000014) /* I2C1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_USART1 ((uint32_t)0x00150020) /* USART1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_USART1 ((uint32_t)0x00150040) /* USART1 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_USART1 ((uint32_t)0x00150060) /* USART1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_USART2 ((uint32_t)0x08000080) /* USART2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_USART2 ((uint32_t)0x08000100) /* USART2 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_USART2 ((uint32_t)0x08000180) /* USART2 Partial3 Alternate Function mapping */ -#define GPIO_FullRemap_USART2 ((uint32_t)0x08000200) /* USART2 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_USART3 ((uint32_t)0x00100400) /* USART3 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_USART3 ((uint32_t)0x00100800) /* USART3 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_USART3 ((uint32_t)0x00100C00) /* USART3 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_USART4 ((uint32_t)0x08001000) /* USART4 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_USART4 ((uint32_t)0x08002000) /* USART4 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_USART4 ((uint32_t)0x08003000) /* USART4 Partial3 Alternate Function mapping */ -#define GPIO_PartialRemap4_USART4 ((uint32_t)0x08004000) /* USART4 Partial4 Alternate Function mapping */ -#define GPIO_FullRemap_USART4 ((uint32_t)0x08007000) /* USART4 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x08400001) /* TIM1 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x08400002) /* TIM1 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_TIM1 ((uint32_t)0x08400003) /* TIM1 Partial3 Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x08400004) /* TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x08200004) /* TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x08200008) /* TIM2 Partial2 Alternate Function mapping */ -#define GPIO_PartialRemap3_TIM2 ((uint32_t)0x0820000C) /* TIM2 Partial3 Alternate Function mapping */ -#define GPIO_PartialRemap4_TIM2 ((uint32_t)0x08200010) /* TIM2 Partial4 Alternate Function mapping */ -#define GPIO_PartialRemap5_TIM2 ((uint32_t)0x08200014) /* TIM2 Partial5 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x08200018) /* TIM2 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM3 ((uint32_t)0x00300020) /* TIM3 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM3 ((uint32_t)0x00300040) /* TIM3 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM3 ((uint32_t)0x00300060) /* TIM3 Full Alternate Function mapping */ -#define GPIO_Remap_PIOC ((uint32_t)0x00200080) /* PIOC Alternate Function mapping */ -#define GPIO_Remap_SWJ_Disable ((uint32_t)0x08300400) /* SDI Disabled (SDI) */ - -/* GPIO_Port_Sources */ -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOB ((uint8_t)0x01) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) - -/* GPIO_Pin_sources */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) -#define GPIO_PinSource16 ((uint8_t)0x10) -#define GPIO_PinSource17 ((uint8_t)0x11) -#define GPIO_PinSource18 ((uint8_t)0x12) -#define GPIO_PinSource19 ((uint8_t)0x13) -#define GPIO_PinSource20 ((uint8_t)0x14) -#define GPIO_PinSource21 ((uint8_t)0x15) -#define GPIO_PinSource22 ((uint8_t)0x16) -#define GPIO_PinSource23 ((uint8_t)0x17) - - -void GPIO_DeInit(GPIO_TypeDef *GPIOx); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); -uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); -uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint16_t GPIO_PinSource); -void GPIO_IPD_Unused(void); - - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_gpio.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : This file contains all the functions prototypes for the + * GPIO firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_GPIO_H +#define __CH32X035_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_50MHz = 1, +} GPIOSpeed_TypeDef; + +/* Configuration Mode enumeration */ +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, /* Only PA0--PA15 and PC16--PC17 support input pull-down */ + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint32_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +} GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint32_t)0x000001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint32_t)0x000002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint32_t)0x000004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint32_t)0x000008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint32_t)0x000010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint32_t)0x000020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint32_t)0x000040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint32_t)0x000080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint32_t)0x000100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint32_t)0x000200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint32_t)0x000400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint32_t)0x000800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint32_t)0x001000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint32_t)0x002000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint32_t)0x004000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint32_t)0x008000) /* Pin 15 selected */ +#define GPIO_Pin_16 ((uint32_t)0x010000) /* Pin 16 selected */ +#define GPIO_Pin_17 ((uint32_t)0x020000) /* Pin 17 selected */ +#define GPIO_Pin_18 ((uint32_t)0x040000) /* Pin 18 selected */ +#define GPIO_Pin_19 ((uint32_t)0x080000) /* Pin 19 selected */ +#define GPIO_Pin_20 ((uint32_t)0x100000) /* Pin 20 selected */ +#define GPIO_Pin_21 ((uint32_t)0x200000) /* Pin 21 selected */ +#define GPIO_Pin_22 ((uint32_t)0x400000) /* Pin 22 selected */ +#define GPIO_Pin_23 ((uint32_t)0x800000) /* Pin 23 selected */ +#define GPIO_Pin_All ((uint32_t)0xFFFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +/* PCFR1 */ +#define GPIO_PartialRemap1_SPI1 ((uint32_t)0x00100001) /* SPI1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_SPI1 ((uint32_t)0x00100002) /* SPI1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_SPI1 ((uint32_t)0x00100003) /* SPI1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_I2C1 ((uint32_t)0x08020004) /* I2C1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_I2C1 ((uint32_t)0x08020008) /* I2C1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_I2C1 ((uint32_t)0x0802000C) /* I2C1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_I2C1 ((uint32_t)0x08020010) /* I2C1 Partial4 Alternate Function mapping */ +#define GPIO_FullRemap_I2C1 ((uint32_t)0x08020014) /* I2C1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART1 ((uint32_t)0x00150020) /* USART1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART1 ((uint32_t)0x00150040) /* USART1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART1 ((uint32_t)0x00150060) /* USART1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART2 ((uint32_t)0x08070080) /* USART2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART2 ((uint32_t)0x08070100) /* USART2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART2 ((uint32_t)0x08070180) /* USART2 Partial3 Alternate Function mapping */ +#define GPIO_FullRemap_USART2 ((uint32_t)0x08070200) /* USART2 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART3 ((uint32_t)0x001A0400) /* USART3 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART3 ((uint32_t)0x001A0800) /* USART3 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x001A0C00) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART4 ((uint32_t)0x080C1000) /* USART4 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART4 ((uint32_t)0x080C2000) /* USART4 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART4 ((uint32_t)0x080C3000) /* USART4 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_USART4 ((uint32_t)0x080C4000) /* USART4 Partial4 Alternate Function mapping */ +#define GPIO_FullRemap_USART4 ((uint32_t)0x080C7000) /* USART4 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x084F0001) /* TIM1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x084F0002) /* TIM1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM1 ((uint32_t)0x084F0003) /* TIM1 Partial3 Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x084F0004) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x08220004) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x08220008) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM2 ((uint32_t)0x0822000C) /* TIM2 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM2 ((uint32_t)0x08220010) /* TIM2 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM2 ((uint32_t)0x08220014) /* TIM2 Partial5 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x08220018) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM3 ((uint32_t)0x00350020) /* TIM3 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM3 ((uint32_t)0x00350040) /* TIM3 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x00350060) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_PIOC ((uint32_t)0x00200080) /* PIOC Alternate Function mapping */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x08300400) /* SDI Disabled (SDI) */ + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) +#define GPIO_PinSource16 ((uint8_t)0x10) +#define GPIO_PinSource17 ((uint8_t)0x11) +#define GPIO_PinSource18 ((uint8_t)0x12) +#define GPIO_PinSource19 ((uint8_t)0x13) +#define GPIO_PinSource20 ((uint8_t)0x14) +#define GPIO_PinSource21 ((uint8_t)0x15) +#define GPIO_PinSource22 ((uint8_t)0x16) +#define GPIO_PinSource23 ((uint8_t)0x17) + + +void GPIO_DeInit(GPIO_TypeDef *GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint16_t GPIO_PinSource); +void GPIO_IPD_Unused(void); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_i2c.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_i2c.h index 37e29db..adb2a2e 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_i2c.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_i2c.h @@ -1,416 +1,416 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_i2c.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the - * I2C firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_I2C_H -#define __CH32X035_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* I2C Init structure definition */ -typedef struct -{ - uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /* Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /* Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /* Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -} I2C_InitTypeDef; - -/* I2C_mode */ -#define I2C_Mode_I2C ((uint16_t)0x0000) - -/* I2C_duty_cycle_in_fast_mode */ -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ - -/* I2C_acknowledgement */ -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) - -/* I2C_transfer_direction */ -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) - -/* I2C_acknowledged_address */ -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) - -/* I2C_registers */ -#define I2C_Register_CTLR1 ((uint8_t)0x00) -#define I2C_Register_CTLR2 ((uint8_t)0x04) -#define I2C_Register_OADDR1 ((uint8_t)0x08) -#define I2C_Register_OADDR2 ((uint8_t)0x0C) -#define I2C_Register_DATAR ((uint8_t)0x10) -#define I2C_Register_STAR1 ((uint8_t)0x14) -#define I2C_Register_STAR2 ((uint8_t)0x18) -#define I2C_Register_CKCFGR ((uint8_t)0x1C) -#define I2C_Register_RTR ((uint8_t)0x20) - -/* I2C_PEC_position */ -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) - -/* I2C_NACK_position */ -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) - -/* I2C_interrupts_definition */ -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) - -/* I2C_interrupts_definition */ -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -/* SR2 register flags */ -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/* SR1 register flags */ -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -/****************I2C Master Events (Events grouped in order of communication)********************/ - -/******************************************************************************************************************** - * @brief Start communicate - * - * After master use I2C_GenerateSTART() function sending the START condition,the master - * has to wait for event 5(the Start condition has been correctly - * released on the I2C bus ). - * - */ -/* EVT5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/******************************************************************************************************************** - * @brief Address Acknowledge - * - * When start condition correctly released on the bus(check EVT5), the - * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate - * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will be set: - * - * - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (after generating the START - * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. - * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent - * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part - * of the 10-bit address (LSB) . Then master should wait for event 6. - * - * - */ - -/* EVT6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/*EVT9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/******************************************************************************************************************** - * @brief Communication events - * - * If START condition has generated and slave address - * been acknowledged. then the master has to check one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EVT7 then use - * I2C_ReceiveData() function to read the data received from the slave . - * - * 2) Master Transmitter mode: The master use I2C_SendData() function to send data - * then to wait on event EVT8 or EVT8_2. - * These two events are similar: - * - EVT8 means that the data has been written in the data register and is - * being shifted out. - * - EVT8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EVT8 is sufficient for the application. - * Using EVT8_2 will leads to a slower communication speed but will more reliable . - * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission - * - * - * Note: - * In case the user software does not guarantee that this event EVT7 is managed before - * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. - * - * - */ - -/* Master Receive mode */ -/* EVT7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master Transmitter mode*/ -/* EVT8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* EVT8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - -/******************I2C Slave Events (Events grouped in order of communication)******************/ - -/******************************************************************************************************************** - * @brief Start Communicate events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a start condition of master device generate on the bus. - * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. - * - * - * - * a) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * b) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * c) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* EVT1 */ -/* a) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* b) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* c) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/******************************************************************************************************************** - * @brief Communication events - * - * Wait on one of these events when EVT1 has already been checked : - * - * - Slave Receiver mode: - * - EVT2--The device is expecting to receive a data byte . - * - EVT4--The device is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EVT3--When a byte has been transmitted by the slave and the Master is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee - * the EVT3 is managed before the current byte end of transfer The second one can optionally - * be used. - * - EVT3_2--When the master sends a NACK to tell slave device that data transmission - * shall end . The slave device has to stop sending - * data bytes and wait a Stop condition from bus. - * - * Note: - * If the user software does not guarantee that the event 2 is - * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED - * and I2C_FLAG_BTF flag at the same time . - * In this case the communication will be slower. - * - */ - -/* Slave Receiver mode*/ -/* EVT2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* EVT4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave Transmitter mode*/ -/* EVT3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/*EVT3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - - -void I2C_DeInit(I2C_TypeDef *I2Cx); -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); -void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); -void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); -void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); -void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); - - -/***************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * profit the application requirements and constraints: - * - * - * a) First way: - * Using I2C_CheckEvent() function: - * It compares the status registers (STARR1 and STAR2) content to a given event - * (can be the combination of more flags). - * If the current status registers includes the given flags will return SUCCESS. - * and if the current status registers miss flags will returns ERROR. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (CH64xRM). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs besides to the monitored error, - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * in corrupted state. it is suggeted to use error interrupts to monitor the error - * events and handle them in IRQ handler. - * - * - * Note: - * The following functions are recommended for error management: : - * - I2C_ITConfig() main function of configure and enable the error interrupts. - * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions - * to determine which error occurred. - * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() - * \ I2C_GenerateStop() will be use to clear the error flag and source, - * and return to correct communication status. - * - * - * b) Second way: - * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. - * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). - * - When to use: - * - * - This function is suitable for the same applications above but it - * don't have the limitations of I2C_GetFlagStatus() function . - * The returned value could be compared to events already defined in the - * library (ch64x_i2c.h) or to custom values defined by user. - * - This function can be used to monitor the status of multiple flags simultaneously. - * - Contrary to the I2C_CheckEvent () function, this function can choose the time to - * accept the event according to the user's needs (when all event flags are set and - * no other flags are set, or only when the required flags are set) - * - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * c) Third way: - * Using the function I2C_GetFlagStatus() get the status of - * one single flag . - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed . - * - * - Limitations: - * - Call this function to access the status register. Some flag bits may be cleared. - * - Function may need to be called twice or more in order to monitor one single event. - */ - - - -/********************************************************* - * - * a) Basic state monitoring(First way) - ******************************************************** - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/********************************************************* - * - * b) Advanced state monitoring(Second way:) - ******************************************************** - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/********************************************************* - * - * c) Flag-based state monitoring(Third way) - ********************************************************* - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - -void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_i2c.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * I2C firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_I2C_H +#define __CH32X035_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* STAR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* STAR1 register flags */ +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef *I2Cx); +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); + + +/***************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * profit the application requirements and constraints: + * + * + * a) First way: + * Using I2C_CheckEvent() function: + * It compares the status registers (STARR1 and STAR2) content to a given event + * (can be the combination of more flags). + * If the current status registers includes the given flags will return SUCCESS. + * and if the current status registers miss flags will returns ERROR. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (CH64xRM). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs besides to the monitored error, + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * in corrupted state. it is suggeted to use error interrupts to monitor the error + * events and handle them in IRQ handler. + * + * + * Note: + * The following functions are recommended for error management: : + * - I2C_ITConfig() main function of configure and enable the error interrupts. + * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions + * to determine which error occurred. + * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() + * \ I2C_GenerateStop() will be use to clear the error flag and source, + * and return to correct communication status. + * + * + * b) Second way: + * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. + * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). + * - When to use: + * + * - This function is suitable for the same applications above but it + * don't have the limitations of I2C_GetFlagStatus() function . + * The returned value could be compared to events already defined in the + * library (ch64x_i2c.h) or to custom values defined by user. + * - This function can be used to monitor the status of multiple flags simultaneously. + * - Contrary to the I2C_CheckEvent () function, this function can choose the time to + * accept the event according to the user's needs (when all event flags are set and + * no other flags are set, or only when the required flags are set) + * + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * c) Third way: + * Using the function I2C_GetFlagStatus() get the status of + * one single flag . + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed . + * + * - Limitations: + * - Call this function to access the status register. Some flag bits may be cleared. + * - Function may need to be called twice or more in order to monitor one single event. + */ + + + +/********************************************************* + * + * a) Basic state monitoring(First way) + ******************************************************** + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/********************************************************* + * + * b) Advanced state monitoring(Second way:) + ******************************************************** + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/********************************************************* + * + * c) Flag-based state monitoring(Third way) + ********************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_iwdg.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_iwdg.h index 4afc622..be18525 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_iwdg.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_iwdg.h @@ -1,50 +1,50 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_iwdg.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the - * IWDG firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_IWDG_H -#define __CH32X035_IWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* IWDG_WriteAccess */ -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) - -/* IWDG_prescaler */ -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) - -/* IWDG_Flag */ -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) - -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_Enable(void); -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_iwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * IWDG firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_IWDG_H +#define __CH32X035_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_misc.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_misc.h index aeda03c..d859940 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_misc.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_misc.h @@ -1,45 +1,72 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_misc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the - * miscellaneous firmware library functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_MISC_H -#define __CH32X035_MISC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* NVIC Init Structure definition */ -typedef struct -{ - uint8_t NVIC_IRQChannel; - uint8_t NVIC_IRQChannelPreemptionPriority; - uint8_t NVIC_IRQChannelSubPriority; - FunctionalState NVIC_IRQChannelCmd; -} NVIC_InitTypeDef; - -/* Preemption_Priority_Group */ -#define NVIC_PriorityGroup_0 ((uint32_t)0x00) -#define NVIC_PriorityGroup_1 ((uint32_t)0x01) -#define NVIC_PriorityGroup_2 ((uint32_t)0x02) -#define NVIC_PriorityGroup_3 ((uint32_t)0x03) -#define NVIC_PriorityGroup_4 ((uint32_t)0x04) - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_misc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : This file contains all the functions prototypes for the + * miscellaneous firmware library functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_MISC_H +#define __CH32X035_MISC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* CSR_INTSYSCR_INEST_definition */ +#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ + +/* Check the configuration of CSR(0x804) in the startup file(.S) + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + */ + +#ifndef INTSYSCR_INEST +#define INTSYSCR_INEST INTSYSCR_INEST_EN +#endif + +/* NVIC Init Structure definition + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Preemption_Priority_Group */ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#else +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ +#endif + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_opa.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_opa.h index 1a02236..2a32d57 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_opa.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_opa.h @@ -1,221 +1,221 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_opa.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the - * OPA firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_OPA_H -#define __CH32X035_OPA_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* OPA_member_enumeration */ -typedef enum -{ - OPA1 = 0, - OPA2 -} OPA_Num_TypeDef; - -/* OPA_out_channel_enumeration */ -typedef enum -{ - OUT_IO_OUT0 = 0, - OUT_IO_OUT1 -} OPA_Mode_TypeDef; - -/* OPA_PSEL_enumeration */ -typedef enum -{ - CHP0 = 0, - CHP1, - CHP2, - CHP_OFF -} OPA_PSEL_TypeDef; - -/* OPA_FB_enumeration */ -typedef enum -{ - FB_OFF = 0, - FB_ON -} OPA_FB_TypeDef; - -/* OPA_NSEL_enumeration */ -typedef enum -{ - CHN0 = 0, - CHN1, - CHN2_PGA_16xIN, - CHN_PGA_4xIN, - CHN_PGA_8xIN, - CHN_PGA_16xIN, - CHN_PGA_32xIN, - CHN_OFF -} OPA_NSEL_TypeDef; - -/* OPA_PSEL_POLL_enumeration */ -typedef enum -{ - CHP_OPA1_OFF_OPA2_OFF = 0, - CHP_OPA1_ON_OPA2_OFF, - CHP_OPA1_OFF_OPA2_ON, - CHP_OPA1_ON_OPA2_ON -} OPA_PSEL_POLL_TypeDef; - -/* OPA_BKIN_EN_enumeration */ -typedef enum -{ - BKIN_OPA1_OFF_OPA2_OFF = 0, - BKIN_OPA1_ON_OPA2_OFF, - BKIN_OPA1_OFF_OPA2_ON, - BKIN_OPA1_ON_OPA2_ON -} OPA_BKIN_EN_TypeDef; - -/* OPA_RST_EN_enumeration */ -typedef enum -{ - RST_OPA1_OFF_OPA2_OFF = 0, - RST_OPA1_ON_OPA2_OFF, - RST_OPA1_OFF_OPA2_ON, - RST_OPA1_ON_OPA2_ON -} OPA_RST_EN_TypeDef; - -/* OPA_BKIN_SEL_enumeration */ -typedef enum -{ - BKIN_OPA1_TIM1_OPA2_TIM2 = 0, - BKIN_OPA1_TIM2_OPA2_TIM1 -} OPA_BKIN_SEL_TypeDef; - -/* OPA_OUT_IE_enumeration */ -typedef enum -{ - OUT_IE_OPA1_OFF_OPA2_OFF = 0, - OUT_IE_OPA1_ON_OPA2_OFF, - OUT_IE_OPA1_OFF_OPA2_ON, - OUT_IE_OPA1_ON_OPA2_ON -} OPA_OUT_IE_TypeDef; - -/* OPA_CNT_IE_enumeration */ -typedef enum -{ - CNT_IE_OFF = 0, - CNT_IE_ON, -} OPA_CNT_IE_TypeDef; - -/* OPA_NMI_IE_enumeration */ -typedef enum -{ - NMI_IE_OFF = 0, - NMI_IE_ON, -} OPA_NMI_IE_TypeDef; - -/* OPA_PSEL_POLL_NUM_enumeration */ -typedef enum -{ - CHP_POLL_NUM_1 = 0, - CHP_POLL_NUM_2, - CHP_POLL_NUM_3 -} OPA_PSEL_POLL_NUM_TypeDef; - - -/* OPA Init Structure definition */ -typedef struct -{ - uint16_t OPA_POLL_Interval; /* OPA polling interval = (OPA_POLL_Interval+1)*1us - This parameter must range from 0 to 0x1FF.*/ - OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ - OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ - OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ - OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ - OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ - OPA_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of OPA */ - OPA_BKIN_EN_TypeDef BKIN_EN; /* Specifies the brake input source of OPA */ - OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */ - OPA_BKIN_SEL_TypeDef BKIN_SEL; /* Specifies the brake input source selection of OPA */ - OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */ - OPA_CNT_IE_TypeDef CNT_IE; /* Specifies the out interrupt rising edge of sampling data */ - OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NIM interrupt of OPA */ - OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of forward inputs*/ -} OPA_InitTypeDef; - -/* CMP_member_enumeration */ -typedef enum -{ - CMP1 = 0, - CMP2, - CMP3 -} CMP_Num_TypeDef; - -/* CMP_out_channel_enumeration */ -typedef enum -{ - OUT_IO_TIM2_CH1 = 0, - OUT_IO_PA1 -} CMP_Mode_TypeDef; - -/* CMP_NSEL_enumeration */ -typedef enum -{ - CMP_CHN0 = 0, - CMP_CHN1, -} CMP_NSEL_TypeDef; - -/* CMP_PSEL_enumeration */ -typedef enum -{ - CMP_CHP1 = 0, - CMP_CHP2, -} CMP_PSEL_TypeDef; - -/* CMP_HYEN_enumeration */ -typedef enum -{ - CMP_HYEN1 = 0, - CMP_HYEN2, -} CMP_HYEN_TypeDef; - -/* CMP Init Structure definition */ -typedef struct -{ - CMP_Num_TypeDef CMP_NUM; /* Specifies the members of CMP */ - CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */ - CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ - CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ - CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */ -} CMP_InitTypeDef; - -/* OPA_flags_definition */ -#define OPA_FLAG_OUT_OPA1 ((uint16_t)0x1000) -#define OPA_FLAG_OUT_OPA2 ((uint16_t)0x2000) -#define OPA_FLAG_OUT_CNT ((uint16_t)0x4000) - -void OPA_Unlock(void); -void OPA_Lock(void); -void OPA_POLL_Unlock(void); -void OPA_POLL_Lock(void); -void OPA_CMP_Unlock(void); -void OPA_CMP_Lock(void); -void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); -void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); -void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); -void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct); -void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct); -void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); -FlagStatus OPA_GetFlagStatus( uint16_t OPA_FLAG); -void OPA_ClearFlag(uint16_t OPA_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_opa.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * OPA firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_OPA_H +#define __CH32X035_OPA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* OPA_member_enumeration */ +typedef enum +{ + OPA1 = 0, + OPA2 +} OPA_Num_TypeDef; + +/* OPA_out_channel_enumeration */ +typedef enum +{ + OUT_IO_OUT0 = 0, + OUT_IO_OUT1 +} OPA_Mode_TypeDef; + +/* OPA_PSEL_enumeration */ +typedef enum +{ + CHP0 = 0, + CHP1, + CHP2, + CHP_OFF +} OPA_PSEL_TypeDef; + +/* OPA_FB_enumeration */ +typedef enum +{ + FB_OFF = 0, + FB_ON +} OPA_FB_TypeDef; + +/* OPA_NSEL_enumeration */ +typedef enum +{ + CHN0 = 0, + CHN1, + CHN2_PGA_16xIN, + CHN_PGA_4xIN, + CHN_PGA_8xIN, + CHN_PGA_16xIN, + CHN_PGA_32xIN, + CHN_OFF +} OPA_NSEL_TypeDef; + +/* OPA_PSEL_POLL_enumeration */ +typedef enum +{ + CHP_OPA1_OFF_OPA2_OFF = 0, + CHP_OPA1_ON_OPA2_OFF, + CHP_OPA1_OFF_OPA2_ON, + CHP_OPA1_ON_OPA2_ON +} OPA_PSEL_POLL_TypeDef; + +/* OPA_BKIN_EN_enumeration */ +typedef enum +{ + BKIN_OPA1_OFF_OPA2_OFF = 0, + BKIN_OPA1_ON_OPA2_OFF, + BKIN_OPA1_OFF_OPA2_ON, + BKIN_OPA1_ON_OPA2_ON +} OPA_BKIN_EN_TypeDef; + +/* OPA_RST_EN_enumeration */ +typedef enum +{ + RST_OPA1_OFF_OPA2_OFF = 0, + RST_OPA1_ON_OPA2_OFF, + RST_OPA1_OFF_OPA2_ON, + RST_OPA1_ON_OPA2_ON +} OPA_RST_EN_TypeDef; + +/* OPA_BKIN_SEL_enumeration */ +typedef enum +{ + BKIN_OPA1_TIM1_OPA2_TIM2 = 0, + BKIN_OPA1_TIM2_OPA2_TIM1 +} OPA_BKIN_SEL_TypeDef; + +/* OPA_OUT_IE_enumeration */ +typedef enum +{ + OUT_IE_OPA1_OFF_OPA2_OFF = 0, + OUT_IE_OPA1_ON_OPA2_OFF, + OUT_IE_OPA1_OFF_OPA2_ON, + OUT_IE_OPA1_ON_OPA2_ON +} OPA_OUT_IE_TypeDef; + +/* OPA_CNT_IE_enumeration */ +typedef enum +{ + CNT_IE_OFF = 0, + CNT_IE_ON, +} OPA_CNT_IE_TypeDef; + +/* OPA_NMI_IE_enumeration */ +typedef enum +{ + NMI_IE_OFF = 0, + NMI_IE_ON, +} OPA_NMI_IE_TypeDef; + +/* OPA_PSEL_POLL_NUM_enumeration */ +typedef enum +{ + CHP_POLL_NUM_1 = 0, + CHP_POLL_NUM_2, + CHP_POLL_NUM_3 +} OPA_PSEL_POLL_NUM_TypeDef; + + +/* OPA Init Structure definition */ +typedef struct +{ + uint16_t OPA_POLL_Interval; /* OPA polling interval = (OPA_POLL_Interval+1)*1us + This parameter must range from 0 to 0x1FF.*/ + OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of OPA */ + OPA_BKIN_EN_TypeDef BKIN_EN; /* Specifies the brake input source of OPA */ + OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */ + OPA_BKIN_SEL_TypeDef BKIN_SEL; /* Specifies the brake input source selection of OPA */ + OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */ + OPA_CNT_IE_TypeDef CNT_IE; /* Specifies the out interrupt rising edge of sampling data */ + OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NIM interrupt of OPA */ + OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of forward inputs*/ +} OPA_InitTypeDef; + +/* CMP_member_enumeration */ +typedef enum +{ + CMP1 = 0, + CMP2, + CMP3 +} CMP_Num_TypeDef; + +/* CMP_out_channel_enumeration */ +typedef enum +{ + OUT_IO_TIM2 = 0, + OUT_IO0 +} CMP_Mode_TypeDef; + +/* CMP_NSEL_enumeration */ +typedef enum +{ + CMP_CHN0 = 0, + CMP_CHN1, +} CMP_NSEL_TypeDef; + +/* CMP_PSEL_enumeration */ +typedef enum +{ + CMP_CHP1 = 0, + CMP_CHP2, +} CMP_PSEL_TypeDef; + +/* CMP_HYEN_enumeration */ +typedef enum +{ + CMP_HYEN1 = 0, + CMP_HYEN2, +} CMP_HYEN_TypeDef; + +/* CMP Init Structure definition */ +typedef struct +{ + CMP_Num_TypeDef CMP_NUM; /* Specifies the members of CMP */ + CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */ + CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ + CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ + CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */ +} CMP_InitTypeDef; + +/* OPA_flags_definition */ +#define OPA_FLAG_OUT_OPA1 ((uint16_t)0x1000) +#define OPA_FLAG_OUT_OPA2 ((uint16_t)0x2000) +#define OPA_FLAG_OUT_CNT ((uint16_t)0x4000) + +void OPA_Unlock(void); +void OPA_Lock(void); +void OPA_POLL_Unlock(void); +void OPA_POLL_Lock(void); +void OPA_CMP_Unlock(void); +void OPA_CMP_Lock(void); +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); +void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct); +void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct); +void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); +FlagStatus OPA_GetFlagStatus( uint16_t OPA_FLAG); +void OPA_ClearFlag(uint16_t OPA_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_pwr.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_pwr.h index 9c734c4..d66b587 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_pwr.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_pwr.h @@ -1,46 +1,55 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_pwr.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the PWR - * firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_PWR_H -#define __CH32X035_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* PVD_detection_level */ -#define PWR_PVDLevel_2V1 ((uint32_t)0x00000000) -#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) -#define PWR_PVDLevel_3V0 ((uint32_t)0x00000040) -#define PWR_PVDLevel_4V0 ((uint32_t)0x00000060) - -/* STOP_mode_entry */ -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) - -/* PWR_Flag */ -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) -#define PWR_FLAG_FLASH ((uint32_t)0x00000020) - -void PWR_DeInit(void); -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_pwr.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/14 + * Description : This file contains all the functions prototypes for the PWR + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_PWR_H +#define __CH32X035_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* PVD_detection_level */ +#define PWR_PVDLevel_0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_3 ((uint32_t)0x00000060) + +#define PWR_PVDLevel_2V1 PWR_PVDLevel_0 +#define PWR_PVDLevel_2V3 PWR_PVDLevel_1 +#define PWR_PVDLevel_3V0 PWR_PVDLevel_2 +#define PWR_PVDLevel_4V0 PWR_PVDLevel_3 + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) +#define PWR_FLAG_FLASH ((uint32_t)0x00000020) + +/* PWR_VDD_Supply_Voltage */ +typedef enum {PWR_VDD_5V = 0, PWR_VDD_3V3 = !PWR_VDD_5V} PWR_VDD; + +void PWR_DeInit(void); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +PWR_VDD PWR_VDD_SupplyVoltage(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_rcc.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_rcc.h index 11320da..e4b1d30 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_rcc.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_rcc.h @@ -1,111 +1,111 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_rcc.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the RCC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_RCC_H -#define __CH32X035_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* RCC_Exported_Types */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ -} RCC_ClocksTypeDef; - -/* AHB_clock_source */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) -#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) -#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) -#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) -#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) -#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) - -/* AHB_peripheral */ -#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) -#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000) -#define RCC_AHBPeriph_IO2W ((uint32_t)0x00002000) -#define RCC_AHBPeriph_USBPD ((uint32_t)0x00020000) - -/* APB2_peripheral */ -#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) -#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) - -/* APB1_peripheral */ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_USART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) - -/* Clock_source_to_output_on_MCO_pin */ -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) - -/* RCC_Flag */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_OPARST ((uint8_t)0x79) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -/* SysTick_clock_source */ -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) - - -void RCC_DeInit(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCO); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_rcc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_RCC_H +#define __CH32X035_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ +} RCC_ClocksTypeDef; + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) +#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) +#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) +#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) +#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) +#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000) +#define RCC_AHBPeriph_IO2W ((uint32_t)0x00002000) +#define RCC_AHBPeriph_USBPD ((uint32_t)0x00020000) + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_USART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_OPARST ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + + +void RCC_DeInit(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_spi.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_spi.h index 27f624c..230f3c6 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_spi.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_spi.h @@ -1,153 +1,154 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_spi.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the - * SPI firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_SPI_H -#define __CH32X035_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* SPI Init structure definition */ -typedef struct -{ - uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /* Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /* Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /* Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_transmission */ - - uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ -} SPI_InitTypeDef; - -/* SPI_data_direction */ -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) - -/* SPI_mode */ -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) - -/* SPI_data_size */ -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) - -/* SPI_Clock_Polarity */ -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) - -/* SPI_Clock_Phase */ -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) - -/* SPI_Slave_Select_management */ -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) - -/* SPI_BaudRate_Prescaler */ -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) - -/* SPI_MSB_LSB_transmission */ -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080)//not support SPI slave mode - -/* SPI_I2S_DMA_transfer_requests */ -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) - -/* SPI_NSS_internal_software_management */ -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) - -/* SPI_CRC_Transmit_Receive */ -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) - -/* SPI_direction_transmit_receive */ -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) - -/* SPI_I2S_interrupts_definition */ -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) - -/* SPI_I2S_flags_definition */ -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) - -void SPI_I2S_DeInit(SPI_TypeDef *SPIx); -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); -void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); -void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); -void SPI_TransmitCRC(SPI_TypeDef *SPIx); -void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); -void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_spi.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/05 + * Description : This file contains all the functions prototypes for the + * SPI firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_SPI_H +#define __CH32X035_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity + When using SPI slave mode to send data, the CPOL bit should be set to 1 */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_transmission */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +} SPI_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002)//When using SPI slave mode to send data, the CPOL bit should be set to 1. + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB_transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080)//not support SPI slave mode + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + +void SPI_I2S_DeInit(SPI_TypeDef *SPIx); +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef *SPIx); +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_tim.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_tim.h index 0cfda49..30b3dae 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_tim.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_tim.h @@ -1,530 +1,530 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_tim.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the - * TIM firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_TIM_H -#define __CH32X035_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* TIM Time Base Init structure definition */ -typedef struct -{ - uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /* Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode (TIM1 and TIM2) */ - - uint16_t TIM_Period; /* Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /* Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/* TIM Output Compare Init structure definition */ -typedef struct -{ - uint16_t TIM_OCMode; /* Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_state - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /* Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/* TIM Input Capture Init structure definition */ -typedef struct -{ - uint16_t TIM_Channel; /* Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /* Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /* Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/* BDTR structure definition */ -typedef struct -{ - uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. - This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. - This parameter can be a value of @ref Lock_level */ - - uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/* TIM_Output_Compare_and_PWM_modes */ -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) - -/* TIM_One_Pulse_Mode */ -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) - -/* TIM_Channel */ -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -/* TIM_Clock_Division_CKD */ -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) - -/* TIM_Counter_Mode */ -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) - -/* TIM_Output_Compare_Polarity */ -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) - -/* TIM_Output_Compare_N_Polarity */ -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) - -/* TIM_Output_Compare_state */ -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) - -/* TIM_Output_Compare_N_state */ -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) - -/* TIM_Capture_Compare_state */ -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) - -/* TIM_Capture_Compare_N_state */ -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) - -/* Break_Input_enable_disable */ -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) - -/* Break_Polarity */ -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) - -/* TIM_AOE_Bit_Set_Reset */ -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) - -/* Lock_level */ -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) - -/* OSSI_Off_State_Selection_for_Idle_mode_state */ -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) - -/* OSSR_Off_State_Selection_for_Run_mode_state */ -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Idle_State */ -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Output_Compare_N_Idle_State */ -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) - -/* TIM_Input_Capture_Polarity */ -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) - -/* TIM_Input_Capture_Selection */ -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ - -/* TIM_Input_Capture_Prescaler */ -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ - -/* TIM_interrupt_sources */ -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) - -/* TIM_DMA_Base_address */ -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) - -/* TIM_DMA_Burst_Length */ -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) - -/* TIM_DMA_sources */ -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) - -/* TIM_External_Trigger_Prescaler */ -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) - -/* TIM_Internal_Trigger_Selection */ -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) - -/* TIM_TIx_External_Clock_Source */ -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/* TIM_External_Trigger_Polarity */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) - -/* TIM_Prescaler_Reload_Mode */ -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) - -/* TIM_Forced_Action */ -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) - -/* TIM_Encoder_Mode */ -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) - -/* TIM_Event_Source */ -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) - -/* TIM_Update_Source */ -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ - or the setting of UG bit, or an update generation \ - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ - -/* TIM_Output_Compare_Preload_State */ -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Fast_State */ -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) - -/* TIM_Output_Compare_Clear_State */ -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) - -/* TIM_Trigger_Output_Source */ -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) - -/* TIM_Slave_Mode */ -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) - -/* TIM_Master_Slave_Mode */ -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) - -/* TIM_Flags */ -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) - -/* TIM_Legacy */ -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers - -/* TIM_Supersede_Mode_OC1 */ -#define TIM_Supersede_Mode_OC1_H ((uint16_t)0x0000) -#define TIM_Supersede_Mode_OC1_L ((uint16_t)0x0010) - -/* TIM_Supersede_Mode_OC2 */ -#define TIM_Supersede_Mode_OC2_H ((uint16_t)0x0000) -#define TIM_Supersede_Mode_OC2_L ((uint16_t)0x0020) - -/* TIM_Supersede_Mode_OC3 */ -#define TIM_Supersede_Mode_OC3_H ((uint16_t)0x0000) -#define TIM_Supersede_Mode_OC3_L ((uint16_t)0x0040) - -/* TIM_Supersede_Mode_OC4 */ -#define TIM_Supersede_Mode_OC4_H ((uint16_t)0x0000) -#define TIM_Supersede_Mode_OC4_L ((uint16_t)0x0080) - - - -void TIM_DeInit(TIM_TypeDef *TIMx); -void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); -void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); -void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_InternalClockConfig(TIM_TypeDef *TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); -void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); -void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); -void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); -void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); -void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); -void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); -void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); -void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); -void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); -void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); -void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); -void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); -void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); -void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); -uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); -uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); -uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); -void TIM_CaptureModeCmd(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState); -void TIM_OC12_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC1, uint16_t TIM_Supersede_Mode_OC2, FunctionalState NewState); -void TIM_OC34_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC3, uint16_t TIM_Supersede_Mode_OC4, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_tim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_TIM_H +#define __CH32X035_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode (TIM1 and TIM2) */ + + uint16_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + +/* TIM_Supersede_Mode_OC1 */ +#define TIM_Supersede_Mode_OC1_H ((uint16_t)0x0000) +#define TIM_Supersede_Mode_OC1_L ((uint16_t)0x0010) + +/* TIM_Supersede_Mode_OC2 */ +#define TIM_Supersede_Mode_OC2_H ((uint16_t)0x0000) +#define TIM_Supersede_Mode_OC2_L ((uint16_t)0x0020) + +/* TIM_Supersede_Mode_OC3 */ +#define TIM_Supersede_Mode_OC3_H ((uint16_t)0x0000) +#define TIM_Supersede_Mode_OC3_L ((uint16_t)0x0040) + +/* TIM_Supersede_Mode_OC4 */ +#define TIM_Supersede_Mode_OC4_H ((uint16_t)0x0000) +#define TIM_Supersede_Mode_OC4_L ((uint16_t)0x0080) + + + +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef *TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_CaptureModeCmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_OC12_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC1, uint16_t TIM_Supersede_Mode_OC2, FunctionalState NewState); +void TIM_OC34_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC3, uint16_t TIM_Supersede_Mode_OC4, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_usart.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_usart.h index 79fe683..7d38507 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_usart.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_usart.h @@ -1,185 +1,185 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_usart.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the - * USART firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_USART_H -#define __CH32X035_USART_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* USART Init Structure definition */ -typedef struct -{ - uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /* Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/* USART Clock Init Structure definition */ -typedef struct -{ - uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* USART_Word_Length */ -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -/* USART_Stop_Bits */ -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) - -/* USART_Parity */ -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) - -/* USART_Mode */ -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) - -/* USART_Hardware_Flow_Control */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) - -/* USART_Clock */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) - -/* USART_Clock_Polarity */ -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) - -/* USART_Clock_Phase */ -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) - -/* USART_Last_Bit */ -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) - -/* USART_Interrupt_definition */ -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) - -#define USART_IT_ORE USART_IT_ORE_ER - -/* USART_DMA_Requests */ -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) - -/* USART_WakeUp_methods */ -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) - -/* USART_LIN_Break_Detection_Length */ -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) - -/* USART_IrDA_Low_Power */ -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) - -/* USART_Flags */ -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) - -void USART_DeInit(USART_TypeDef *USARTx); -void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); -void USART_StructInit(USART_InitTypeDef *USART_InitStruct); -void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); -void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); -void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef *USARTx); -void USART_SendBreak(USART_TypeDef *USARTx); -void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); -void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); -void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_usart.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * USART firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_USART_H +#define __CH32X035_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +void USART_DeInit(USART_TypeDef *USARTx); +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); +void USART_StructInit(USART_InitTypeDef *USART_InitStruct); +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef *USARTx); +void USART_SendBreak(USART_TypeDef *USARTx); +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_usb.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_usb.h new file mode 100644 index 0000000..ce112f4 --- /dev/null +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_usb.h @@ -0,0 +1,522 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_usb.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/08/02 + * Description : This file contains all the functions prototypes for the USB + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_USB_H +#define __CH32X035_USB_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +/*******************************************************************************/ +/* Header File */ +#include "stdint.h" + +/*******************************************************************************/ +/* USB Communication Related Macro Definition */ + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_NYET 0x06 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* Bit Define for USB Request Type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 +#define USB_REQ_TYP_OUT 0x00 +#define USB_REQ_TYP_READ 0x80 +#define USB_REQ_TYP_WRITE 0x00 +#define USB_REQ_TYP_MASK 0x60 +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB Descriptor Type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB Device Class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB Hub Class Request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub Class Feature Selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB HID Class Request Code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* USB UDisk */ +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif +/*******************************************************************************/ +/* USBFS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBFS_UC_HOST_MODE 0x80 +#define USBFS_UC_LOW_SPEED 0x40 +#define USBFS_UC_DEV_PU_EN 0x20 +#define USBFS_UC_SYS_CTRL_MASK 0x30 +#define USBFS_UC_SYS_CTRL0 0x00 +#define USBFS_UC_SYS_CTRL1 0x10 +#define USBFS_UC_SYS_CTRL2 0x20 +#define USBFS_UC_SYS_CTRL3 0x30 +#define USBFS_UC_INT_BUSY 0x08 +#define USBFS_UC_RESET_SIE 0x04 +#define USBFS_UC_CLR_ALL 0x02 +#define USBFS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBFS_UIE_DEV_SOF 0x80 +#define USBFS_UIE_DEV_NAK 0x40 +#define USBFS_UID_1_WIRE 0x20 +#define USBFS_UIE_FIFO_OV 0x10 +#define USBFS_UIE_HST_SOF 0x08 +#define USBFS_UIE_SUSPEND 0x04 +#define USBFS_UIE_TRANSFER 0x02 +#define USBFS_UIE_DETECT 0x01 +#define USBFS_UIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +/* R8_USB_MIS_ST */ +#define USBFS_UMS_SOF_PRES 0x80 +#define USBFS_UMS_SOF_ACT 0x40 +#define USBFS_UMS_SIE_FREE 0x20 +#define USBFS_UMS_R_FIFO_RDY 0x10 +#define USBFS_UMS_BUS_RESET 0x08 +#define USBFS_UMS_SUSPEND 0x04 +#define USBFS_UMS_DM_LEVEL 0x02 +#define USBFS_UMS_DEV_ATTACH 0x01 + +/* R8_USB_INT_FG */ +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* R8_USB_INT_ST */ +#define USBFS_SETUP_ACT 0x80 // RO, indicate current USB transfer SETUP is complete +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_SOF 0x10 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +/* R8_UDEV_CTRL */ +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* R8_UEP4_1_MOD */ +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes +// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes +// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes +// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA +// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes +// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes +// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes + +/* R8_UEP2_3_MOD */ +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* R8_UEP567_MOD */ + +#define USBFS_UEP5_RX_EN 0x02 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x01 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP6_RX_EN 0x08 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x04 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP7_RX_EN 0x20 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x10 // enable USB endpoint 7 transmittal (IN) + +/* R8_UEPn_TX_CTRL */ +#define USBFS_UEP_T_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_T_TOG (1<<6) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK (0<<1) +#define USBFS_UEP_T_RES_NONE (1<<0) +#define USBFS_UEP_T_RES_NAK (1<<1) +#define USBFS_UEP_T_RES_STALL (3<<0) +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +// host aux setup + +/* R8_UEPn_RX_CTRL, n=0-7 */ +#define USBFS_UEP_R_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG (1<<7) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_R_RES_MASK (3<<2) // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK (0<<3) +#define USBFS_UEP_R_RES_NONE (1<<2) +#define USBFS_UEP_R_RES_NAK (1<<3) +#define USBFS_UEP_R_RES_STALL (3<<2) +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +/* R8_UHOST_CTRL */ +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +/* R32_UH_EP_MOD */ +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +/* R8_UH_SETUP */ +#define USBFS_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x40 // USB host automatic SOF enable + +/* R8_UH_EP_PID */ +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + + /* R8_UH_RX_CTRL */ + #define USBFS_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle + #define USBFS_UH_R_TOG (1<<7) // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 + #define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + + /* R8_UH_TX_CTRL */ + #define USBFS_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle + #define USBFS_UH_T_TOG (1<<6) // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 + #define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + + +/*******************************************************************************/ +/* Struct Definition */ + +/* USB Setup Request */ +typedef struct __attribute__((packed)) _USB_SETUP_REQ +{ + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + +/* USB Device Descriptor */ +typedef struct __attribute__((packed)) _USB_DEVICE_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + +/* USB Configuration Descriptor */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + +/* USB Interface Descriptor */ +typedef struct __attribute__((packed)) _USB_INTERF_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + +/* USB Endpoint Descriptor */ +typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSizeL; + uint8_t wMaxPacketSizeH; + uint8_t bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + +/* USB Configuration Descriptor Set */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG +{ + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[ 1 ]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + +/* USB HUB Descriptor */ +typedef struct __attribute__((packed)) _USB_HUB_DESCR +{ + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint8_t wHubCharacteristicsL; + uint8_t wHubCharacteristicsH; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + +/* USB HID Descriptor */ +typedef struct __attribute__((packed)) _USB_HID_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bDescriptorTypeX; + uint8_t wDescriptorLengthL; + uint8_t wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CBW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCBW_DataLen; + uint8_t mCBW_Flag; + uint8_t mCBW_LUN; + uint8_t mCBW_CB_Len; + uint8_t mCBW_CB_Buf[ 16 ]; +} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CSW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCSW_Residue; + uint8_t mCSW_Status; +} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; + + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32X035_USB_H */ diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_usbpd.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_usbpd.h new file mode 100644 index 0000000..2b55923 --- /dev/null +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_usbpd.h @@ -0,0 +1,412 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_usbpd.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the USBPD + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_USBPD_H +#define __CH32X035_USBPD_H + + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32x035.h" + +#ifndef VOID +#define VOID void +#endif +#ifndef CONST +#define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif + + /******************************************************************************/ +/* Related macro definitions */ + +/* Define the return value of the function */ +#ifndef SUCCESS +#define SUCCESS 0 +#endif +#ifndef FAIL +#define FAIL 0xFF +#endif + +/* Register Bit Definition */ +/* USBPD->CONFIG */ +#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ +#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ +#define CC_SEL (1<<2) /* Select PD communication port */ +#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ +#define PD_RST_EN (1<<4) /* PD mode reset command enable */ +#define WAKE_POLAR (1<<5) /* PD port wake-up level */ +#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ +#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ +#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ +#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ +#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ +#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ + +/* USBPD->CONTROL */ +#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ +#define BMC_START (1<<1) /* BMC send start signal */ +#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ +#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ +#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ +#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ +#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ +#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ + +/* USBPD->TX_SEL */ +#define TX_SEL1 (0<<0) +#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ +#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ +#define TX_SEL2_Mask (3<<2) +#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ +#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ +#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ +#define TX_SEL3_Mask (3<<4) +#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ +#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ +#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ +#define TX_SEL4_Mask (3<<6) +#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ +#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ +#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ + +/* USBPD->STATUS */ +#define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */ +#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ +#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ +#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ +#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ +#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ +#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ +#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ +#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ +#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ +#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ + +/* USBPD->PORT_CC1 */ +/* USBPD->PORT_CC2 */ +#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ +#define CC_PD (1<<1) /* CC port pull-down resistor enable */ +#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ +#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ +#define CC_PU_330 (1<<2) /* 01-330uA */ +#define CC_PU_180 (2<<2) /* 10-180uA */ +#define CC_PU_80 (3<<2) /* 11-80uA */ +#define CC_LVE (1<<4) /* CC port output low voltage enable */ +#define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/ +#define CC_NO_CMP (0<<5) /* 000-closed */ +#define CC_CMP_22 (2<<5) /* 010-0.22V */ +#define CC_CMP_45 (3<<5) /* 011-0.45V */ +#define CC_CMP_55 (4<<5) /* 100-0.55V */ +#define CC_CMP_66 (5<<5) /* 101-0.66V */ +#define CC_CMP_95 (6<<5) /* 110-0.95V */ +#define CC_CMP_123 (7<<5) /* 111-1.23V */ +#define USBPD_IN_HVT (1<<9) +/********************************************************* + * PD pin PC14/PC15 high threshold input mode: + * 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication + * 0-Normal GPIO threshold input + * *******************************************************/ +#define USBPD_PHY_V33 (1<<8) +/********************************************************** +* PD transceiver PHY pull-up limit configuration bits: +* 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V +* 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V +* ********************************************************/ + +/* Control Message Types */ +#define DEF_TYPE_RESERVED 0x00 +#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ +#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_PING 0x05 /* Send By: Source */ +#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ +#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ +#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ +#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ +#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ +#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ +#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ +#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ +#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ +#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ + +/* Data Message Types */ +#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ +#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ +#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ +#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ +#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ +#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ +#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ +#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ +#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ +#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ + +/* Vendor Define Message Command */ +#define DEF_VDM_DISC_IDENT 0x01 +#define DEF_VDM_DISC_SVID 0x02 +#define DEF_VDM_DISC_MODE 0x03 +#define DEF_VDM_ENTER_MODE 0x04 +#define DEF_VDM_EXIT_MODE 0x05 +#define DEF_VDM_ATTENTION 0x06 +#define DEF_VDM_DP_S_UPDATE 0x10 +#define DEF_VDM_DP_CONFIG 0x11 + +/* PD Revision */ +#define DEF_PD_REVISION_10 0x00 +#define DEF_PD_REVISION_20 0x01 +#define DEF_PD_REVISION_30 0x02 + + +/* PD PHY Channel */ +#define DEF_PD_CC1 0x00 +#define DEF_PD_CC2 0x01 + +#define PIN_CC1 GPIO_Pin_14 +#define PIN_CC2 GPIO_Pin_15 + +/* PD Tx Status */ +#define DEF_PD_TX_OK 0x00 +#define DEF_PD_TX_FAIL 0x01 + +/* PDO INDEX */ +#define PDO_INDEX_1 1 +#define PDO_INDEX_2 2 +#define PDO_INDEX_3 3 +#define PDO_INDEX_4 4 +#define PDO_INDEX_5 5 + +/******************************************************************************/ + +#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ +#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ +#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ +#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ +#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ +#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ + +#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ +#define PD_RX_SOP0 0x01 /* SOP0 received */ +#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ +#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ + +#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ +#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ +#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ +#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ +#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ + + +#define bCC_CMP_22 0X01 +#define bCC_CMP_45 0X02 +#define bCC_CMP_55 0X04 +#define bCC_CMP_66 0X08 +#define bCC_CMP_95 0X10 +#define bCC_CMP_123 0X20 +#define bCC_CMP_220 0X40 + +/******************************************************************************/ +/* PD State Machine */ +typedef enum +{ + STA_IDLE = 0, /* 0: No task status */ + STA_DISCONNECT, /* 1: Disconnection */ + STA_SRC_CONNECT, /* 2: SRC connect */ + STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */ + STA_RX_SRC_CAP, /* 4: SRC_CAP received */ + STA_TX_REQ, /* 5: Send REQUEST */ + STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */ + STA_RX_ACCEPT, /* 7: ACCEPT received */ + STA_RX_REJECT, /* 8: REJECT received */ + STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */ + STA_RX_PS_RDY, /* 10: PS_RDY received */ + STA_SINK_CONNECT, /* 11: SNK access */ + STA_TX_SRC_CAP, /* 12: Send SRC_CAP */ + STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */ + STA_RX_REQ, /* 14: REQUEST received */ + STA_TX_ACCEPT, /* 15: Send ACCEPT */ + STA_TX_REJECT, /* 16: Send REJECT */ + STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */ + STA_TX_PS_RDY, /* 18: Send PS_RDY */ + STA_TX_DR_SWAP, /* 19: Send DR_SWAP */ + STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */ + STA_TX_PR_SWAP, /* 21: Send PR_SWAP */ + STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */ + STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */ + STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */ + STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */ + STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */ + STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */ + STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */ + STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */ + STA_MODE_SWITCH, /* 30: Mode switching */ + STA_TX_SOFTRST, /* 31: Sending a software reset */ + STA_TX_HRST, /* 32: Send hardware reset */ + STA_PHY_RST, /* 33: PHY reset */ + STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */ +} CC_STATUS; + +/******************************************************************************/ +/* PD Message Header Struct */ +typedef union +{ + struct _Message_Header + { + UINT8 MsgType: 5; /* Message Type */ + UINT8 PDRole: 1; /* 0-UFP; 1-DFP */ + UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */ + UINT8 PRRole: 1; /* 0-Sink; 1-Source */ + UINT8 MsgID: 3; + UINT8 NumDO: 3; + UINT8 Ext: 1; + }Message_Header; + UINT16 Data; +}_Message_Header; + +/******************************************************************************/ +/* Bit definition */ +typedef union +{ + struct _BITS_ + { + UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */ + UINT8 Connected: 1; /* PD Physical Layer Connected Flag */ + UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */ + UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */ + UINT8 PR_Role: 1; /* 0-Sink; 1-Source */ + UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */ + UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */ + UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */ + UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */ + UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */ + UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */ + UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */ + UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */ + UINT8 Recv: 3; + }Bit; + UINT16 Bit_Flag; +}_BIT_FLAG; + +/* PD control-related structures */ +typedef struct _PD_CONTROL +{ + CC_STATUS PD_State; /* PD communication status machine */ + CC_STATUS PD_State_Last; /* PD communication status machine (last value) */ + UINT8 Msg_ID; /* ID of the message sent */ + UINT8 Det_Timer; /* PD connection status detection timing */ + UINT8 Det_Cnt; /* Number of PD connection status detections */ + UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */ + UINT8 HPD_Det_Timer; /* HPD connection detection timing */ + UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */ + UINT16 PD_Comm_Timer; /* PD shared timing variables */ + UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */ + UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */ + UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */ + UINT8 Err_Op_Cnt; /* Exception operation count */ + UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */ + _BIT_FLAG Flag; /* Flag byte bit definition */ +}PD_CONTROL, *pPD_CONTROL; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/inc/ch32x035_wwdg.h b/system/CH32X035/SRC/Peripheral/inc/ch32x035_wwdg.h index 689b6fd..98f62e2 100644 --- a/system/CH32X035/SRC/Peripheral/inc/ch32x035_wwdg.h +++ b/system/CH32X035/SRC/Peripheral/inc/ch32x035_wwdg.h @@ -1,41 +1,41 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_wwdg.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file contains all the functions prototypes for the WWDG - * firmware library. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_WWDG_H -#define __CH32X035_WWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ch32x035.h" - -/* WWDG_Prescaler */ -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) - -void WWDG_DeInit(void); -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); -void WWDG_Enable(uint8_t Counter); -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_wwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the WWDG + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_WWDG_H +#define __CH32X035_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_adc.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_adc.c index c8455b7..ac803ef 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_adc.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_adc.c @@ -1,1125 +1,1125 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_adc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the ADC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_adc.h" -#include "ch32x035_rcc.h" - -/* ADC DISCNUM mask */ -#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) -#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) - -/* ADC JAUTO mask */ -#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) -#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) - -/* ADC AWDCH mask */ -#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) - -/* CTLR1 register Mask */ -#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) - -/* ADC ADON mask */ -#define CTLR2_ADON_Set ((uint32_t)0x00000001) -#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CTLR2_DMA_Set ((uint32_t)0x00000100) -#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) - -/* ADC RSTCAL mask */ -#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) - -/* ADC CAL mask */ -#define CTLR2_CAL_Set ((uint32_t)0x00000004) - -/* ADC SWSTART mask */ -#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) - -/* ADC EXTTRIG mask */ -#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) - -/* ADC JEXTSEL mask */ -#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTART mask */ -#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) - -/* ADC TSPD mask */ -#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) -#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) - -/* CTLR2 register Mask */ -#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) - -/* ADC SQx mask */ -#define RSQR3_SQ_Set ((uint32_t)0x0000001F) -#define RSQR2_SQ_Set ((uint32_t)0x0000001F) -#define RSQR1_SQ_Set ((uint32_t)0x0000001F) - -/* RSQR1 register Mask */ -#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define ISQR_JSQ_Set ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define ISQR_JL_Set ((uint32_t)0x00300000) -#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) -#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) - -/* ADC IDATARx registers offset */ -#define IDATAR_Offset ((uint8_t)0x28) - -/* ADC1 RDATAR register base address */ -#define RDATAR_ADDRESS ((uint32_t)0x4001244C) - -/* ADC CLK */ -#define CTLR3_CLK_Mask ((uint32_t)0xFFFFFE00) - -/********************************************************************* - * @fn ADC_DeInit - * - * @brief Deinitializes the ADCx peripheral registers to their default - * reset values. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return none - */ -void ADC_DeInit(ADC_TypeDef *ADCx) -{ - if(ADCx == ADC1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); - } -} - -/********************************************************************* - * @fn ADC_Init - * - * @brief Initializes the ADCx peripheral according to the specified - * parameters in the ADC_InitStruct. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | - (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); - ADCx->CTLR1 = tmpreg1; - - tmpreg1 = ADCx->CTLR2; - tmpreg1 &= CTLR2_CLEAR_Mask; - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - ADCx->CTLR2 = tmpreg1; - - tmpreg1 = ADCx->RSQR1; - tmpreg1 &= RSQR1_CLEAR_Mask; - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); - tmpreg1 |= (uint32_t)tmpreg2 << 20; - ADCx->RSQR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_StructInit - * - * @brief Fills each ADC_InitStruct member with its default value. - * - * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that - * contains the configuration information for the specified ADC - * peripheral. - * - * @return none - */ -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) -{ - ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStruct->ADC_NbrOfChannel = 1; -} - -/********************************************************************* - * @fn ADC_Cmd - * - * @brief Enables or disables the specified ADC peripheral. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_ADON_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_ADON_Reset; - } -} - -/********************************************************************* - * @fn ADC_DMACmd - * - * @brief Enables or disables the specified ADC DMA request. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_DMA_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_DMA_Reset; - } -} - -/********************************************************************* - * @fn ADC_ITConfig - * - * @brief Enables or disables the specified ADC interrupts. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)ADC_IT; - - if(NewState != DISABLE) - { - ADCx->CTLR1 |= itmask; - } - else - { - ADCx->CTLR1 &= (~(uint32_t)itmask); - } -} - -/********************************************************************* - * @fn ADC_SoftwareStartConvCmd - * - * @brief Enables or disables the selected ADC software start conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartConvStatus - * - * @brief Gets the selected ADC Software start conversion Status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus - SET or RESET. - */ - -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_DiscModeChannelCountConfig - * - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * Number - specifies the discontinuous mode regular channel - * count value(1-8). - * - * @return None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->CTLR1; - tmpreg1 &= CTLR1_DISCNUM_Reset; - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - ADCx->CTLR1 = tmpreg1; -} - -/********************************************************************* - * @fn ADC_DiscModeCmd - * - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_DISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_DISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_RegularChannelConfig - * - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_10 - ADC Channel10 selected. - * ADC_Channel_11 - ADC Channel11 selected. - * ADC_Channel_12 - ADC Channel12 selected. - * ADC_Channel_13 - ADC Channel13 selected. - * ADC_Channel_14 - ADC Channel14 selected. - * ADC_Channel_15 - ADC Channel15 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_4Cycles - Sample time equal to 4 cycles. - * ADC_SampleTime_5Cycles - Sample time equal to 5 cycles. - * ADC_SampleTime_6Cycles - Sample time equal to 6 cycles. - * ADC_SampleTime_7Cycles - Sample time equal to 7 cycles. - * ADC_SampleTime_8Cycles - Sample time equal to 8 cycles. - * ADC_SampleTime_9Cycles - Sample time equal to 9 cycles. - * ADC_SampleTime_10Cycles - Sample time equal to 10 cycles. - * ADC_SampleTime_11Cycles - Sample time equal to 11 cycles. - * - * @return None - */ -void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - if(Rank < 7) - { - tmpreg1 = ADCx->RSQR3; - tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - tmpreg1 |= tmpreg2; - ADCx->RSQR3 = tmpreg1; - } - else if(Rank < 13) - { - tmpreg1 = ADCx->RSQR2; - tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - tmpreg1 |= tmpreg2; - ADCx->RSQR2 = tmpreg1; - } - else - { - tmpreg1 = ADCx->RSQR1; - tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - tmpreg1 |= tmpreg2; - ADCx->RSQR1 = tmpreg1; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigConvCmd - * - * @brief Enables or disables the ADCx conversion through external trigger. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetConversionValue - * - * @brief Returns the last ADCx conversion result data for regular channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return ADCx->RDATAR - The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) -{ - return (uint16_t)ADCx->RDATAR; -} - -/********************************************************************* - * @fn ADC_GetDualModeConversionValue - * - * @brief Returns the last ADC1 conversion result data in dual mode. - * - * @return RDATAR_ADDRESS - The Data conversion value. - */ -uint32_t ADC_GetDualModeConversionValue(void) -{ - return (*(__IO uint32_t *)RDATAR_ADDRESS); -} - -/********************************************************************* - * @fn ADC_AutoInjectedConvCmd - * - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JAUTO_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JAUTO_Reset; - } -} - -/********************************************************************* - * @fn ADC_InjectedDiscModeCmd - * - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR1 |= CTLR1_JDISCEN_Set; - } - else - { - ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; - } -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvConfig - * - * @brief Configures the ADCx external trigger for injected channels conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start - * injected conversion. - * ADC_ExternalTrigInjecConv_T1_CC3 - Timer1 TRGO event selected. - * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. - * ADC_ExternalTrigInjecConv_T2_CC3 - Timer2 capture compare3 selected. - * ADC_ExternalTrigInjecConv_T2_CC4 - Timer2 capture compare4 selected. - * ADC_ExternalTrigInjecConv_T2_CC2 - Timer2 capture compare2 selected. - * ADC_ExternalTrigInjecConv_T3_CC2 - Timer3 capture compare2 selected. - * ADC_ExternalTrigInjecConv_ADC_ETRGREG - ADC ETRGREG selected. - * ADC_ExternalTrigInjecConv_None: Injected conversion started - * by software and not by external trigger. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR2; - tmpreg &= CTLR2_JEXTSEL_Reset; - tmpreg |= ADC_ExternalTrigInjecConv; - ADCx->CTLR2 = tmpreg; -} - -/********************************************************************* - * @fn ADC_ExternalTrigInjectedConvCmd - * - * @brief Enables or disables the ADCx injected channels conversion through - * external trigger. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; - } -} - -/********************************************************************* - * @fn ADC_SoftwareStartInjectedConvCmd - * - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return None - */ -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; - } - else - { - ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; - } -} - -/********************************************************************* - * @fn ADC_GetSoftwareStartInjectedConvCmdStatus - * - * @brief Gets the selected ADC Software start injected conversion Status. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_InjectedChannelConfig - * - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_10 - ADC Channel10 selected. - * ADC_Channel_11 - ADC Channel11 selected. - * ADC_Channel_12 - ADC Channel12 selected. - * ADC_Channel_13 - ADC Channel13 selected. - * ADC_Channel_14 - ADC Channel14 selected. - * ADC_Channel_15 - ADC Channel15 selected. - * Rank - The rank in the regular group sequencer. - * This parameter must be between 1 to 4. - * ADC_SampleTime - The sample time value to be set for the selected channel. - * ADC_SampleTime_4Cycles - Sample time equal to 4 cycles. - * ADC_SampleTime_5Cycles - Sample time equal to 5 cycles. - * ADC_SampleTime_6Cycles - Sample time equal to 6 cycles. - * ADC_SampleTime_7Cycles - Sample time equal to 7 cycles. - * ADC_SampleTime_8Cycles - Sample time equal to 8 cycles. - * ADC_SampleTime_9Cycles - Sample time equal to 9 cycles. - * ADC_SampleTime_10Cycles - Sample time equal to 10 cycles. - * ADC_SampleTime_11Cycles - Sample time equal to 11 cycles. - * - * @return None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - - if(ADC_Channel > ADC_Channel_9) - { - tmpreg1 = ADCx->SAMPTR1; - tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR1 = tmpreg1; - } - else - { - tmpreg1 = ADCx->SAMPTR2; - tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - tmpreg1 |= tmpreg2; - ADCx->SAMPTR2 = tmpreg1; - } - - tmpreg1 = ADCx->ISQR; - tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; - tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 &= ~tmpreg2; - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - tmpreg1 |= tmpreg2; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_InjectedSequencerLengthConfig - * - * @brief Configures the sequencer length for injected channels. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * Length - The sequencer length. - * This parameter must be a number between 1 to 4. - * - * @return None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - tmpreg1 = ADCx->ISQR; - tmpreg1 &= ISQR_JL_Reset; - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - ADCx->ISQR = tmpreg1; -} - -/********************************************************************* - * @fn ADC_SetInjectedOffset - * - * @brief Set the injected channels conversion value offset. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InjectedChannel: the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * Offset - the offset value for the selected ADC injected channel. - * This parameter must be a 12bit value. - * - * @return None - */ -void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - *(__IO uint32_t *)tmp = (uint32_t)Offset; -} - -/********************************************************************* - * @fn ADC_GetInjectedConversionValue - * - * @brief Returns the ADC injected channel conversion result. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_InjectedChannel - the ADC injected channel to set its offset. - * ADC_InjectedChannel_1 - Injected Channel1 selected. - * ADC_InjectedChannel_2 - Injected Channel2 selected. - * ADC_InjectedChannel_3 - Injected Channel3 selected. - * ADC_InjectedChannel_4 - Injected Channel4 selected. - * - * @return tmp - The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + IDATAR_Offset; - - return (uint16_t)(*(__IO uint32_t *)tmp); -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogCmd - * - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_AnalogWatchdog - the ADC analog watchdog configuration. - * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a - * single regular channel. - * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a - * single injected channel. - * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog - * on a single regular or injected channel. - * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all - * regular channel. - * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all - * injected channel. - * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on - * all regular and injected channels. - * ADC_AnalogWatchdog_None - No channel guarded by the analog - * watchdog. - * - * @return none - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDMode_Reset; - tmpreg |= ADC_AnalogWatchdog; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogThresholdsConfig - * - * @brief Configures the high and low thresholds of the analog watchdog. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * HighThreshold - the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * LowThreshold - the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * - * @return none - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - ADCx->WDHTR = HighThreshold; - ADCx->WDLTR = LowThreshold; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdog1ThresholdsConfig - * - * @brief Configures the high and low thresholds of the analog watchdog1. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * HighThreshold - the ADC analog watchdog1 High threshold value. - * This parameter must be a 12bit value. - * LowThreshold - the ADC analog watchdog1 Low threshold value. - * This parameter must be a 12bit value. - * - * @return none - */ -void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - ADCx->WDTR1 = (uint32_t)HighThreshold<<16; - ADCx->WDTR1 |= (uint32_t)LowThreshold; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdog2ThresholdsConfig - * - * @brief Configures the high and low thresholds of the analog watchdog2. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * HighThreshold - the ADC analog watchdog2 High threshold value. - * This parameter must be a 12bit value. - * LowThreshold - the ADC analog watchdog2 Low threshold value. - * This parameter must be a 12bit value. - * - * @return none - */ -void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - ADCx->WDTR2 = (uint32_t)HighThreshold<<16; - ADCx->WDTR2 |= (uint32_t)LowThreshold; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdog3ThresholdsConfig - * - * @brief Configures the high and low thresholds of the analog watchdog3. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * HighThreshold - the ADC analog watchdog3 High threshold value. - * This parameter must be a 12bit value. - * LowThreshold - the ADC analog watchdog3 Low threshold value. - * This parameter must be a 12bit value. - * - * @return none - */ -void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - ADCx->WDTR3 = (uint32_t)HighThreshold<<16; - ADCx->WDTR3 |= (uint32_t)LowThreshold; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogSingleChannelConfig - * - * @brief Configures the analog watchdog guarded single channel. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_Channel - the ADC channel to configure. - * ADC_Channel_0 - ADC Channel0 selected. - * ADC_Channel_1 - ADC Channel1 selected. - * ADC_Channel_2 - ADC Channel2 selected. - * ADC_Channel_3 - ADC Channel3 selected. - * ADC_Channel_4 - ADC Channel4 selected. - * ADC_Channel_5 - ADC Channel5 selected. - * ADC_Channel_6 - ADC Channel6 selected. - * ADC_Channel_7 - ADC Channel7 selected. - * ADC_Channel_8 - ADC Channel8 selected. - * ADC_Channel_9 - ADC Channel9 selected. - * ADC_Channel_10 - ADC Channel10 selected. - * ADC_Channel_11 - ADC Channel11 selected. - * ADC_Channel_12 - ADC Channel12 selected. - * ADC_Channel_13 - ADC Channel13 selected. - * ADC_Channel_14 - ADC Channel14 selected. - * ADC_Channel_15 - ADC Channel15 selected. - * - * @return None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR1; - tmpreg &= CTLR1_AWDCH_Reset; - tmpreg |= ADC_Channel; - ADCx->CTLR1 = tmpreg; -} - -/********************************************************************* - * @fn ADC_GetFlagStatus - * - * @brief Checks whether the specified ADC flag is set or not. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to check. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearFlag - * - * @brief Clears the ADCx's pending flags. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_FLAG - specifies the flag to clear. - * ADC_FLAG_AWD - Analog watchdog flag. - * ADC_FLAG_EOC - End of conversion flag. - * ADC_FLAG_JEOC - End of injected group conversion flag. - * ADC_FLAG_JSTRT - Start of injected group conversion flag. - * ADC_FLAG_STRT - Start of regular group conversion flag. - * - * @return none - */ -void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - ADCx->STATR = ~(uint32_t)ADC_FLAG; -} - -/********************************************************************* - * @fn ADC_GetITStatus - * - * @brief Checks whether the specified ADC interrupt has occurred or not. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt source to check. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return FlagStatus: SET or RESET. - */ -ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - itmask = ADC_IT >> 8; - enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); - - if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn ADC_ClearITPendingBit - * - * @brief Clears the ADCx's interrupt pending bits. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_IT - specifies the ADC interrupt pending bit to clear. - * ADC_IT_EOC - End of conversion interrupt mask. - * ADC_IT_AWD - Analog watchdog interrupt mask. - * ADC_IT_JEOC - End of injected conversion interrupt mask. - * - * @return none - */ -void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - - itmask = (uint8_t)(ADC_IT >> 8); - ADCx->STATR = ~(uint32_t)itmask; -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogResetCmd - * - * @brief Enables or disables the analog watchdog reset - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_AnalogWatchdog_x - Analog watchdog X. - * ADC_AnalogWatchdog_0_RST_EN. - * ADC_AnalogWatchdog_1_RST_EN. - * ADC_AnalogWatchdog_2_RST_EN. - * ADC_AnalogWatchdog_3_RST_EN. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog_x, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - ADCx->CTLR3 |= ADC_AnalogWatchdog_x; - } - else - { - ADCx->CTLR3 &= ~ADC_AnalogWatchdog_x; - } -} - -/********************************************************************* - * @fn ADC_AnalogWatchdogScanCmd - * - * @brief Enable ADC clock duty cycle adjustment. - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void ADC_AnalogWatchdogScanCmd(ADC_TypeDef *ADCx, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - ADCx->CTLR3 |= (1<<9); - } - else - { - ADCx->CTLR3 &= ~(1<<9); - } -} - -/********************************************************************* - * @fn ADC_CLKConfig - * - * @brief Configures the PADC clock. - * Note - ADC_CLK_Div_x > H_Level_Cycles_x - * - * @param ADCx - where x can be 1 to select the ADC peripheral. - * ADC_CLK_Div_x - defines the ADC clock divider. - * ADC_CLK_Div4 - ADC clock = SYSCLK/4 - * ADC_CLK_Div5 - ADC clock = SYSCLK/5 - * ADC_CLK_Div6 - ADC clock = SYSCLK/6 - * ADC_CLK_Div7 - ADC clock = SYSCLK/7 - * ADC_CLK_Div8 - ADC clock = SYSCLK/8 - * ADC_CLK_Div9 - ADC clock = SYSCLK/9 - * ADC_CLK_Div10 - ADC clock = SYSCLK/10 - * ADC_CLK_Div11 - ADC clock = SYSCLK/11 - * ADC_CLK_Div12 - ADC clock = SYSCLK/12 - * ADC_CLK_Div13 - ADC clock = SYSCLK/13 - * ADC_CLK_Div14 - ADC clock = SYSCLK/14 - * ADC_CLK_Div15 - ADC clock = SYSCLK/15 - * ADC_CLK_Div16 - ADC clock = SYSCLK/16 - * @return none - */ -void ADC_CLKConfig(ADC_TypeDef *ADCx, uint32_t ADC_CLK_Div_x) -{ - uint32_t tmpreg = 0; - - tmpreg = ADCx->CTLR3; - - tmpreg &= CTLR3_CLK_Mask; - tmpreg |= ADC_CLK_Div_x; - ADCx->CTLR3 = tmpreg; -} - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_adc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the ADC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_adc.h" +#include "ch32x035_rcc.h" + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + +/* ADC CLK */ +#define CTLR3_CLK_Mask ((uint32_t)0xFFFFFE00) + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | + (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ + +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_4Cycles - Sample time equal to 4 cycles. + * ADC_SampleTime_5Cycles - Sample time equal to 5 cycles. + * ADC_SampleTime_6Cycles - Sample time equal to 6 cycles. + * ADC_SampleTime_7Cycles - Sample time equal to 7 cycles. + * ADC_SampleTime_8Cycles - Sample time equal to 8 cycles. + * ADC_SampleTime_9Cycles - Sample time equal to 9 cycles. + * ADC_SampleTime_10Cycles - Sample time equal to 10 cycles. + * ADC_SampleTime_11Cycles - Sample time equal to 11 cycles. + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_GetDualModeConversionValue + * + * @brief Returns the last ADC1 conversion result data in dual mode. + * + * @return RDATAR_ADDRESS - The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + return (*(__IO uint32_t *)RDATAR_ADDRESS); +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_CC3 - Timer1 TRGO event selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_CC3 - Timer2 capture compare3 selected. + * ADC_ExternalTrigInjecConv_T2_CC4 - Timer2 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_CC2 - Timer2 capture compare2 selected. + * ADC_ExternalTrigInjecConv_T3_CC2 - Timer3 capture compare2 selected. + * ADC_ExternalTrigInjecConv_ADC_ETRGREG - ADC ETRGREG selected. + * ADC_ExternalTrigInjecConv_None: Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 4. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_4Cycles - Sample time equal to 4 cycles. + * ADC_SampleTime_5Cycles - Sample time equal to 5 cycles. + * ADC_SampleTime_6Cycles - Sample time equal to 6 cycles. + * ADC_SampleTime_7Cycles - Sample time equal to 7 cycles. + * ADC_SampleTime_8Cycles - Sample time equal to 8 cycles. + * ADC_SampleTime_9Cycles - Sample time equal to 9 cycles. + * ADC_SampleTime_10Cycles - Sample time equal to 10 cycles. + * ADC_SampleTime_11Cycles - Sample time equal to 11 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 12bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdog1ThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog1. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog1 High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog1 Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDTR1 = (uint32_t)HighThreshold<<16; + ADCx->WDTR1 |= (uint32_t)LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdog2ThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog2. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog2 High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog2 Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDTR2 = (uint32_t)HighThreshold<<16; + ADCx->WDTR2 |= (uint32_t)LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdog3ThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog3. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog3 High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog3 Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDTR3 = (uint32_t)HighThreshold<<16; + ADCx->WDTR3 |= (uint32_t)LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogResetCmd + * + * @brief Enables or disables the analog watchdog reset + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_AnalogWatchdog_x - Analog watchdog X. + * ADC_AnalogWatchdog_0_RST_EN. + * ADC_AnalogWatchdog_1_RST_EN. + * ADC_AnalogWatchdog_2_RST_EN. + * ADC_AnalogWatchdog_3_RST_EN. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog_x, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + ADCx->CTLR3 |= ADC_AnalogWatchdog_x; + } + else + { + ADCx->CTLR3 &= ~ADC_AnalogWatchdog_x; + } +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogScanCmd + * + * @brief Enable ADC clock duty cycle adjustment. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_AnalogWatchdogScanCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + ADCx->CTLR3 |= (1<<9); + } + else + { + ADCx->CTLR3 &= ~(1<<9); + } +} + +/********************************************************************* + * @fn ADC_CLKConfig + * + * @brief Configures the PADC clock. + * Note - ADC_CLK_Div_x > H_Level_Cycles_x + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_CLK_Div_x - defines the ADC clock divider. + * ADC_CLK_Div4 - ADC clock = SYSCLK/4 + * ADC_CLK_Div5 - ADC clock = SYSCLK/5 + * ADC_CLK_Div6 - ADC clock = SYSCLK/6 + * ADC_CLK_Div7 - ADC clock = SYSCLK/7 + * ADC_CLK_Div8 - ADC clock = SYSCLK/8 + * ADC_CLK_Div9 - ADC clock = SYSCLK/9 + * ADC_CLK_Div10 - ADC clock = SYSCLK/10 + * ADC_CLK_Div11 - ADC clock = SYSCLK/11 + * ADC_CLK_Div12 - ADC clock = SYSCLK/12 + * ADC_CLK_Div13 - ADC clock = SYSCLK/13 + * ADC_CLK_Div14 - ADC clock = SYSCLK/14 + * ADC_CLK_Div15 - ADC clock = SYSCLK/15 + * ADC_CLK_Div16 - ADC clock = SYSCLK/16 + * @return none + */ +void ADC_CLKConfig(ADC_TypeDef *ADCx, uint32_t ADC_CLK_Div_x) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR3; + + tmpreg &= CTLR3_CLK_Mask; + tmpreg |= ADC_CLK_Div_x; + ADCx->CTLR3 = tmpreg; +} + diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_awu.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_awu.c index 2e0fdff..889dedf 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_awu.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_awu.c @@ -1,92 +1,92 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_awu.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the AWU firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_awu.h" - -/* PSC registers bit mask */ -#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) - -/* WR register bit mask */ -#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) - -/********************************************************************* - * @fn AutoWakeUpCmd - * - * @brief Enables or disables the Auto WakeUp functionality. - * - * @param NewState - new state of the Auto WakeUp functionality - * (ENABLE or DISABLE). - * - * @return none - */ -void AutoWakeUpCmd(FunctionalState NewState) -{ - if(NewState) - { - AWU->CSR |= (1 << 1); - } - else - { - AWU->CSR &= ~(1 << 1); - } -} - -/********************************************************************* - * @fn AWU_SetPrescaler - * - * @brief Sets the Auto Wake up Prescaler - * - * @param AWU_Prescaler - specifies the Auto Wake up Prescaler - * AWU_Prescaler_1 - AWU counter clock = LSI/1 - * AWU_Prescaler_2 - AWU counter clock = LSI/2 - * AWU_Prescaler_4 - AWU counter clock = LSI/4 - * AWU_Prescaler_8 - AWU counter clock = LSI/8 - * AWU_Prescaler_16 - AWU counter clock = LSI/16 - * AWU_Prescaler_32 - AWU counter clock = LSI/32 - * AWU_Prescaler_64 - AWU counter clock = LSI/64 - * AWU_Prescaler_128 - AWU counter clock = LSI/128 - * AWU_Prescaler_256 - AWU counter clock = LSI/256 - * AWU_Prescaler_512 - AWU counter clock = LSI/512 - * AWU_Prescaler_1024 - AWU counter clock = LSI/1024 - * AWU_Prescaler_2048 - AWU counter clock = LSI/2048 - * AWU_Prescaler_4096 - AWU counter clock = LSI/4096 - * AWU_Prescaler_10240 - AWU counter clock = LSI/10240 - * AWU_Prescaler_61440 - AWU counter clock = LSI/61440 - * - * @return none - */ -void AWU_SetPrescaler(uint32_t AWU_Prescaler) -{ - uint32_t tmpreg = 0; - tmpreg = AWU->PSC & AWUPSC_MASK; - tmpreg |= AWU_Prescaler; - AWU->PSC = tmpreg; -} - -/********************************************************************* - * @fn AWU_SetWindowValue - * - * @brief Sets the WWDG window value - * - * @param WindowValue - specifies the window value to be compared to the - * downcounter,which must be lower than 0x3F - * - * @return none - */ -void AWU_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - tmpreg = AWU->WR & AWUWR_MASK; - tmpreg |= WindowValue; - - AWU->WR = tmpreg; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_awu.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the AWU firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_awu.h" + +/* PSC registers bit mask */ +#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) + +/* WR register bit mask */ +#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) + +/********************************************************************* + * @fn AutoWakeUpCmd + * + * @brief Enables or disables the Auto WakeUp functionality. + * + * @param NewState - new state of the Auto WakeUp functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void AutoWakeUpCmd(FunctionalState NewState) +{ + if(NewState) + { + AWU->CSR |= (1 << 1); + } + else + { + AWU->CSR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn AWU_SetPrescaler + * + * @brief Sets the Auto Wake up Prescaler + * + * @param AWU_Prescaler - specifies the Auto Wake up Prescaler + * AWU_Prescaler_1 - AWU counter clock = LSI/1 + * AWU_Prescaler_2 - AWU counter clock = LSI/2 + * AWU_Prescaler_4 - AWU counter clock = LSI/4 + * AWU_Prescaler_8 - AWU counter clock = LSI/8 + * AWU_Prescaler_16 - AWU counter clock = LSI/16 + * AWU_Prescaler_32 - AWU counter clock = LSI/32 + * AWU_Prescaler_64 - AWU counter clock = LSI/64 + * AWU_Prescaler_128 - AWU counter clock = LSI/128 + * AWU_Prescaler_256 - AWU counter clock = LSI/256 + * AWU_Prescaler_512 - AWU counter clock = LSI/512 + * AWU_Prescaler_1024 - AWU counter clock = LSI/1024 + * AWU_Prescaler_2048 - AWU counter clock = LSI/2048 + * AWU_Prescaler_4096 - AWU counter clock = LSI/4096 + * AWU_Prescaler_10240 - AWU counter clock = LSI/10240 + * AWU_Prescaler_61440 - AWU counter clock = LSI/61440 + * + * @return none + */ +void AWU_SetPrescaler(uint32_t AWU_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = AWU->PSC & AWUPSC_MASK; + tmpreg |= AWU_Prescaler; + AWU->PSC = tmpreg; +} + +/********************************************************************* + * @fn AWU_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x3F + * + * @return none + */ +void AWU_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = AWU->WR & AWUWR_MASK; + tmpreg |= WindowValue; + + AWU->WR = tmpreg; +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_dbgmcu.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_dbgmcu.c index c7adf67..36aac5b 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_dbgmcu.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_dbgmcu.c @@ -1,119 +1,120 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_dbgmcu.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the DBGMCU firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_dbgmcu.h" - -#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) - -/********************************************************************* - * @fn DBGMCU_GetREVID - * - * @brief Returns the device revision identifier. - * - * @return Revision identifier. - */ -uint32_t DBGMCU_GetREVID(void) -{ - return ((*(uint32_t *)0x1FFFF704) >> 16); -} - -/********************************************************************* - * @fn DBGMCU_GetDEVID - * - * @brief Returns the device identifier. - * - * @return Device identifier. - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); -} - -/********************************************************************* - * @fn __get_DEBUG_CR - * - * @brief Return the DEBUGE Control Register - * - * @return DEBUGE Control value - */ -uint32_t __get_DEBUG_CR(void) -{ - uint32_t result; - - __asm volatile("csrr %0,""0x7C0" : "=r"(result)); - return (result); -} - -/********************************************************************* - * @fn __set_DEBUG_CR - * - * @brief Set the DEBUGE Control Register - * - * @param value - set DEBUGE Control value - * - * @return none - */ -void __set_DEBUG_CR(uint32_t value) -{ - __asm volatile("csrw 0x7C0, %0" : : "r"(value)); -} - - -/********************************************************************* - * @fn DBGMCU_Config - * - * @brief Configures the specified peripheral and low power mode behavior - * when the MCU under Debug mode. - * - * @param DBGMCU_Periph - specifies the peripheral and low power mode. - * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted - * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted - * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted - * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted - * DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - uint32_t val; - - if(NewState != DISABLE) - { - __set_DEBUG_CR(DBGMCU_Periph); - } - else - { - val = __get_DEBUG_CR(); - val &= ~(uint32_t)DBGMCU_Periph; - __set_DEBUG_CR(val); - } - -} -/********************************************************************* - * @fn DBGMCU_GetCHIPID - * - * @brief Returns the CHIP identifier. - * - * @return Device identifier. - * ChipID List- - * CH32X035R8T6-0x035006x1 - * CH32X035C8T6-0x035106x1 - * CH32X035F8U6-0x035E06x1 - * CH32X035G8U6-0x035606x1 - * CH32X035G8R6-0x035B06x1 - * CH32X035F7P6-0x035706x1 - */ -uint32_t DBGMCU_GetCHIPID( void ) -{ - return( *( uint32_t * )0x1FFFF704 ); -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_dbgmcu.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the DBGMCU firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_dbgmcu.h" + +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) >> 16); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); +} + +/********************************************************************* + * @fn __get_DEBUG_CR + * + * @brief Return the DEBUGE Control Register + * + * @return DEBUGE Control value + */ +uint32_t __get_DEBUG_CR(void) +{ + uint32_t result; + + __asm volatile("csrr %0,""0x7C0" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_DEBUG_CR + * + * @brief Set the DEBUGE Control Register + * + * @param value - set DEBUGE Control value + * + * @return none + */ +void __set_DEBUG_CR(uint32_t value) +{ + __asm volatile("csrw 0x7C0, %0" : : "r"(value)); +} + + +/********************************************************************* + * @fn DBGMCU_Config + * + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * + * @param DBGMCU_Periph - specifies the peripheral and low power mode. + * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted + * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted + * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted + * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted + * DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + uint32_t val; + + if(NewState != DISABLE) + { + __set_DEBUG_CR(DBGMCU_Periph); + } + else + { + val = __get_DEBUG_CR(); + val &= ~(uint32_t)DBGMCU_Periph; + __set_DEBUG_CR(val); + } + +} +/********************************************************************* + * @fn DBGMCU_GetCHIPID + * + * @brief Returns the CHIP identifier. + * + * @return Device identifier. + * ChipID List- + * CH32X035R8T6-0x035006x1 + * CH32X035C8T6-0x035106x1 + * CH32X035F8U6-0x035E06x1 + * CH32X035G8U6-0x035606x1 + * CH32X035G8R6-0x035B06x1 + * CH32X035F7P6-0x035706x1 + * CH32X033F8P6-0x035A06x1 + */ +uint32_t DBGMCU_GetCHIPID( void ) +{ + return( *( uint32_t * )0x1FFFF704 ); +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_dma.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_dma.c index 7e19bcf..b54c697 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_dma.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_dma.c @@ -1,432 +1,432 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_dma.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the DMA firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_dma.h" -#include "ch32x035_rcc.h" - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) -#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) -#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) -#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) -#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) -#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) -#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) -#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) - -/* DMA2 FLAG mask */ -#define FLAG_Mask ((uint32_t)0x10000000) - -/* DMA registers Masks */ -#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) - -/********************************************************************* - * @fn DMA_DeInit - * - * @brief Deinitializes the DMAy Channelx registers to their default - * reset values. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * - * @return none - */ -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) -{ - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - DMAy_Channelx->CFGR = 0; - DMAy_Channelx->CNTR = 0; - DMAy_Channelx->PADDR = 0; - DMAy_Channelx->MADDR = 0; - if(DMAy_Channelx == DMA1_Channel1) - { - DMA1->INTFCR |= DMA1_Channel1_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel2) - { - DMA1->INTFCR |= DMA1_Channel2_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel3) - { - DMA1->INTFCR |= DMA1_Channel3_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel4) - { - DMA1->INTFCR |= DMA1_Channel4_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel5) - { - DMA1->INTFCR |= DMA1_Channel5_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel6) - { - DMA1->INTFCR |= DMA1_Channel6_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel7) - { - DMA1->INTFCR |= DMA1_Channel7_IT_Mask; - } - else if(DMAy_Channelx == DMA1_Channel8) - { - DMA1->INTFCR |= DMA1_Channel8_IT_Mask; - } -} - -/********************************************************************* - * @fn DMA_Init - * - * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - tmpreg = DMAy_Channelx->CFGR; - tmpreg &= CFGR_CLEAR_Mask; - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - DMAy_Channelx->CFGR = tmpreg; - DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; - DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; - DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/********************************************************************* - * @fn DMA_StructInit - * - * @brief Fills each DMA_InitStruct member with its default value. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains - * contains the configuration information for the specified DMA Channel. - * - * @return none - */ -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) -{ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - DMA_InitStruct->DMA_BufferSize = 0; - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/********************************************************************* - * @fn DMA_Cmd - * - * @brief Enables or disables the specified DMAy Channelx. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_CFGR1_EN; - } - else - { - DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); - } -} - -/********************************************************************* - * @fn DMA_ITConfig - * - * @brief Enables or disables the specified DMAy Channelx interrupts. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * DMA_IT - specifies the DMA interrupts sources to be enabled - * or disabled. - * DMA_IT_TC - Transfer complete interrupt mask - * DMA_IT_HT - Half transfer interrupt mask - * DMA_IT_TE - Transfer error interrupt mask - * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). - * - * @return none - */ -void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DMAy_Channelx->CFGR |= DMA_IT; - } - else - { - DMAy_Channelx->CFGR &= ~DMA_IT; - } -} - -/********************************************************************* - * @fn DMA_SetCurrDataCounter - * - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * DataNumber - The number of data units in the current DMAy Channelx - * transfer. - * - * @return none - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) -{ - DMAy_Channelx->CNTR = DataNumber; -} - -/********************************************************************* - * @fn DMA_GetCurrDataCounter - * - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * - * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be - * 1 to 8 for DMA1 to select the DMA Channel. - * - * @return DataNumber - The number of remaining data units in the current - * DMAy Channelx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) -{ - return ((uint16_t)(DMAy_Channelx->CNTR)); -} - -/********************************************************************* - * @fn DMA_GetFlagStatus - * - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. - * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. - * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. - * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. - - * @return The new state of DMAy_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - tmpreg = DMA1->INTFR; - - if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearFlag - * - * @brief Clears the DMAy Channelx's pending flags. - * - * @param DMAy_FLAG - specifies the flag to check. - * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. - * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. - * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. - * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. - * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. - * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. - * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. - * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. - * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. - * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. - * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. - * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. - * @return none - */ -void DMA_ClearFlag(uint32_t DMAy_FLAG) -{ - DMA1->INTFCR = DMAy_FLAG; -} - -/********************************************************************* - * @fn DMA_GetITStatus - * - * @brief Checks whether the specified DMAy Channelx interrupt has - * occurred or not. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * DMA1_IT_GL8 - DMA1 Channel8 global flag. - * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. - * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. - * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. - * @return The new state of DMAy_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMAy_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - tmpreg = DMA1->INTFR; - - if((tmpreg & DMAy_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn DMA_ClearITPendingBit - * - * @brief Clears the DMAy Channelx's interrupt pending bits. - * - * @param DMAy_IT - specifies the DMAy interrupt source to check. - * DMA1_IT_GL1 - DMA1 Channel1 global flag. - * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. - * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. - * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. - * DMA1_IT_GL2 - DMA1 Channel2 global flag. - * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. - * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. - * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. - * DMA1_IT_GL3 - DMA1 Channel3 global flag. - * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. - * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. - * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. - * DMA1_IT_GL4 - DMA1 Channel4 global flag. - * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. - * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. - * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. - * DMA1_IT_GL5 - DMA1 Channel5 global flag. - * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. - * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. - * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. - * DMA1_IT_GL6 - DMA1 Channel6 global flag. - * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. - * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. - * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. - * DMA1_IT_GL7 - DMA1 Channel7 global flag. - * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. - * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. - * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. - * DMA1_IT_GL8 - DMA1 Channel8 global flag. - * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. - * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. - * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. - * @return none - */ -void DMA_ClearITPendingBit(uint32_t DMAy_IT) -{ - DMA1->INTFCR = DMAy_IT; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_dma.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the DMA firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_dma.h" +#include "ch32x035_rcc.h" + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel8) + { + DMA1->INTFCR |= DMA1_Channel8_IT_Mask; + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. + * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. + + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. + * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + DMA1->INTFCR = DMAy_FLAG; +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_IT_GL8 - DMA1 Channel8 global flag. + * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_IT_GL8 - DMA1 Channel8 global flag. + * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + DMA1->INTFCR = DMAy_IT; +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_exti.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_exti.c index b18c383..8646abf 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_exti.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_exti.c @@ -1,182 +1,182 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_exti.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the EXTI firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_exti.h" - -/* No interrupt selected */ -#define EXTI_LINENONE ((uint32_t)0x00000) - -/********************************************************************* - * @fn EXTI_DeInit - * - * @brief Deinitializes the EXTI peripheral registers to their default - * reset values. - * - * @return none. - */ -void EXTI_DeInit(void) -{ - EXTI->INTENR = 0x00000000; - EXTI->EVENR = 0x00000000; - EXTI->RTENR = 0x00000000; - EXTI->FTENR = 0x00000000; - EXTI->INTFR = 0x000FFFFF; -} - -/********************************************************************* - * @fn EXTI_Init - * - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) -{ - uint32_t tmp = 0; - - tmp = (uint32_t)EXTI_BASE; - if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; - if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/********************************************************************* - * @fn EXTI_StructInit - * - * @brief Fills each EXTI_InitStruct member with its reset value. - * - * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure - * - * @return none. - */ -void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/********************************************************************* - * @fn EXTI_GenerateSWInterrupt - * - * @brief Generates a Software interrupt. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none. - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - EXTI->SWIEVR |= EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetFlagStatus - * - * @brief Checks whether the specified EXTI line flag is set or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearFlag - * - * @brief Clears the EXTI's line pending flags. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} - -/********************************************************************* - * @fn EXTI_GetITStatus - * - * @brief Checks whether the specified EXTI line is asserted or not. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = EXTI->INTENR & EXTI_Line; - if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn EXTI_ClearITPendingBit - * - * @brief Clears the EXTI's line pending bits. - * - * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. - * - * @return none - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - EXTI->INTFR = EXTI_Line; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_exti.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the EXTI firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_exti.h" + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x000FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_flash.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_flash.c index 937513d..5766766 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_flash.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_flash.c @@ -1,743 +1,1040 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_flash.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the FLASH firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_flash.h" - -/* Flash Access Control Register bits */ -#define ACR_LATENCY_Mask ((uint32_t)0x00000038) - -/* Flash Control Register bits */ -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) -#define CR_FLOCK_Set ((uint32_t)0x00008000) -#define CR_PAGE_PG ((uint32_t)0x00010000) -#define CR_PAGE_ER ((uint32_t)0x00020000) -#define CR_BUF_LOAD ((uint32_t)0x00040000) -#define CR_BUF_RST ((uint32_t)0x00080000) -#define CR_BER32 ((uint32_t)0x00800000) - -/* FLASH Status Register bits */ -#define SR_BSY ((uint32_t)0x00000001) -#define SR_WRPRTERR ((uint32_t)0x00000010) -#define SR_EOP ((uint32_t)0x00000020) - -/* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) - -/* FLASH Keys */ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) - -/* FLASH BANK address */ -#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) - -/* Delay definition */ -#define EraseTimeout ((uint32_t)0x000B0000) -#define ProgramTimeout ((uint32_t)0x00005000) - -/******************************************************************************** - * @fn FLASH_SetLatency - * - * @brief Sets the code latency value. - * - * @param FLASH_Latency - specifies the FLASH Latency value. - * FLASH_Latency_0 - FLASH Zero Latency cycle - * FLASH_Latency_1 - FLASH One Latency cycle - * FLASH_Latency_2 - FLASH Two Latency cycles - * - * @return None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - tmpreg = FLASH->ACTLR; - tmpreg &= ACR_LATENCY_Mask; - tmpreg |= FLASH_Latency; - FLASH->ACTLR = tmpreg; -} - -/******************************************************************************** - * @fn FLASH_Unlock - * - * @brief Unlocks the FLASH Program Erase Controller. - * - * @return None - */ -void FLASH_Unlock(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -/******************************************************************************** - * @fn FLASH_Lock - * - * @brief Locks the FLASH Program Erase Controller. - * - * @return None - */ -void FLASH_Lock(void) -{ - FLASH->CTLR |= CR_LOCK_Set; -} - -/******************************************************************************** - * @fn FLASH_ErasePage - * - * @brief Erases a specified FLASH page(1KB). - * - * @param Page_Address - The page address to be erased. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_PER_Set; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_PER_Reset; - } - - return status; -} - -/******************************************************************************** - * @fn FLASH_EraseAllPages - * - * @brief Erases all FLASH pages. - * - * @return FLASH Status - The returned value can be:FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH->CTLR |= CR_MER_Set; - FLASH->CTLR |= CR_STRT_Set; - - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_MER_Reset; - } - - return status; -} - -/******************************************************************************** - * @fn FLASH_EraseOptionBytes - * - * @brief Erases the FLASH option bytes. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseOptionBytes(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - FLASH_Unlock(); - - FLASH->OBKEYR = FLASH_KEY1; - FLASH->OBKEYR = FLASH_KEY2; - - FLASH->CTLR |= CR_OPTER_Set; - FLASH->CTLR |= CR_STRT_Set; - status = FLASH_WaitForLastOperation(EraseTimeout); - - FLASH->CTLR &= CR_OPTER_Reset; - - FLASH_Lock(); - } - return status; -} - -/********************************************************************* - * @fn FLASH_OptionBytePR - * - * @brief Programs option bytes. - * - * @param pbuf - data. - * - * @return none - */ -void FLASH_OptionBytePR(u32* pbuf) -{ - uint8_t i; - - FLASH_EraseOptionBytes(); - FLASH_Unlock_Fast(); - FLASH_BufReset(); - - for(i=0; i<4; i++) - { - FLASH_BufLoad((OB_BASE + 4*i), *pbuf++); - } - - FLASH_ProgramPage_Fast(OB_BASE); - FLASH_Lock_Fast(); -} - -/********************************************************************* - * @fn FLASH_EnableWriteProtection - * - * @brief Write protects the desired sectors - * - * @param FLASH_Sectors - specifies the address of the pages to be write protected. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. - */ -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) -{ - uint8_t WRP0_Data = 0xFF, WRP1_Data = 0xFF, WRP2_Data = 0xFF, WRP3_Data = 0xFF; - uint32_t buf[4]; - uint8_t i; - FLASH_Status status = FLASH_COMPLETE; - - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - status = FLASH_RDP; - } - else{ - FLASH_Pages = (uint32_t)(~FLASH_Pages); - WRP0_Data = (uint8_t)(FLASH_Pages & WRP0_Mask); - WRP1_Data = (uint8_t)((FLASH_Pages & WRP1_Mask) >> 8); - WRP2_Data = (uint8_t)((FLASH_Pages & WRP2_Mask) >> 16); - WRP3_Data = (uint8_t)((FLASH_Pages & WRP3_Mask) >> 24); - - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - for(i=0; i<4; i++){ - buf[i] = *(uint32_t*)(OB_BASE + 4*i); - } - - buf[2] = ((uint32_t)(((uint32_t)(WRP0_Data) & 0x00FF) + (((uint32_t)(~WRP0_Data) & 0x00FF) << 8) \ - + (((uint32_t)(WRP1_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP1_Data) & 0x00FF) << 24))); - buf[3] = ((uint32_t)(((uint32_t)(WRP2_Data) & 0x00FF) + (((uint32_t)(~WRP2_Data) & 0x00FF) << 8) \ - + (((uint32_t)(WRP3_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP3_Data) & 0x00FF) << 24))); - - FLASH_OptionBytePR(buf); - } - } - - return status; -} - -/********************************************************************* - * @fn FLASH_EnableReadOutProtection - * - * @brief Enables the read out protection. - * - * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT or FLASH_RDP. - */ -FLASH_Status FLASH_EnableReadOutProtection(void) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t buf[4]; - uint8_t i; - - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - status = FLASH_RDP; - } - else{ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - for(i=0; i<4; i++){ - buf[i] = *(uint32_t*)(OB_BASE + 4*i); - } - - buf[0] = 0x000000FF + (buf[0] & 0xFFFF0000); - FLASH_OptionBytePR(buf); - } - } - - return status; -} - -/********************************************************************* - * @fn FLASH_UserOptionByteConfig - * - * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. - * - * @param OB_IWDG - Selects the IWDG mode - * OB_IWDG_SW - Software IWDG selected - * OB_IWDG_HW - Hardware IWDG selected - * OB_STOP - Reset event when entering STOP mode. - * OB_STOP_NoRST - No reset generated when entering in STOP - * OB_STOP_RST - Reset generated when entering in STOP - * OB_STDBY - Reset event when entering Standby mode. - * OB_STDBY_NoRST - No reset generated when entering in STANDBY - * OB_STDBY_RST - Reset generated when entering in STANDBY - * OB_RST - Selects the reset IO mode and Ignore delay time - * OB_RST_NoEN - Reset IO disable - * OB_RST_EN_DT12ms - Reset IO enable and Ignore delay time 12ms - * OB_RST_EN_DT1ms - Reset IO enable and Ignore delay time 1ms - * OB_RST_EN_DT128us - Reset IO enable and Ignore delay time 128us - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. - */ -FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_RST) -{ - FLASH_Status status = FLASH_COMPLETE; - uint8_t UserByte; - uint32_t buf[4]; - uint8_t i; - - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - status = FLASH_RDP; - } - else{ - UserByte = OB_IWDG | (uint8_t)(OB_STOP | (uint8_t)(OB_STDBY | (uint8_t)(OB_RST | (uint8_t)0xE0))); - - for(i=0; i<4; i++){ - buf[i] = *(uint32_t*)(OB_BASE + 4*i); - } - buf[0] = ((uint32_t)((((uint32_t)(UserByte) & 0x00FF) << 16) + (((uint32_t)(~UserByte) & 0x00FF) << 24))) + 0x00005AA5; - - FLASH_OptionBytePR(buf); - } - - return status; -} - -/********************************************************************* - * @fn FLASH_GetUserOptionByte - * - * @brief Returns the FLASH User Option Bytes values. - * - * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1), - * RST_STDBY(Bit2) ,RST_MOD(bit[4:3]) ,DATA0(bit[17:10]) and - * DATA1(bit[25:18]). - */ -uint32_t FLASH_GetUserOptionByte(void) -{ - return (uint32_t)(FLASH->OBR >> 2); -} - -/********************************************************************* - * @fn FLASH_GetWriteProtectionOptionByte - * - * @brief Returns the FLASH Write Protection Option Bytes Register value. - * - * @return The FLASH Write Protection Option Bytes Register value. - */ -uint32_t FLASH_GetWriteProtectionOptionByte(void) -{ - return (uint32_t)(FLASH->WPR); -} - -/********************************************************************* - * @fn FLASH_GetReadOutProtectionStatus - * - * @brief Checks whether the FLASH Read Out Protection Status is set or not. - * - * @return FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetReadOutProtectionStatus(void) -{ - FlagStatus readoutstatus = RESET; - if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - readoutstatus = SET; - } - else - { - readoutstatus = RESET; - } - return readoutstatus; -} - -/********************************************************************* - * @fn FLASH_ITConfig - * - * @brief Enables or disables the specified FLASH interrupts. - * - * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. - * FLASH_IT_ERROR - FLASH Error Interrupt - * FLASH_IT_EOP - FLASH end of operation Interrupt - * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). - * - * @return FLASH Prefetch Buffer Status (SET or RESET). - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - FLASH->CTLR |= FLASH_IT; - } - else - { - FLASH->CTLR &= ~(uint32_t)FLASH_IT; - } -} - -/********************************************************************* - * @fn FLASH_GetFlagStatus - * - * @brief Checks whether the specified FLASH flag is set or not. - * - * @param FLASH_FLAG - specifies the FLASH flag to check. - * FLASH_FLAG_BSY - FLASH Busy flag - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * FLASH_FLAG_OPTERR - FLASH Option Byte error flag - * - * @return The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - return bitstatus; -} - -/********************************************************************* - * @fn FLASH_ClearFlag - * - * @brief Clears the FLASH's pending flags. - * - * @param FLASH_FLAG - specifies the FLASH flags to clear. - * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag - * FLASH_FLAG_EOP - FLASH End of Operation flag - * - * @return none - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - FLASH->STATR = FLASH_FLAG; -} - -/********************************************************************* - * @fn FLASH_GetStatus - * - * @brief Returns the FLASH Status. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_GetBank1Status - * - * @brief Returns the FLASH Bank1 Status. - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetBank1Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - return flashstatus; -} - -/********************************************************************* - * @fn FLASH_WaitForLastOperation - * - * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_WaitForLastBank1Operation - * - * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. - * - * @param Timeout - FLASH programming Timeout - * - * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - status = FLASH_GetBank1Status(); - while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00) - { - status = FLASH_TIMEOUT; - } - return status; -} - -/********************************************************************* - * @fn FLASH_Unlock_Fast - * - * @brief Unlocks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Unlock_Fast(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - - /* Fast program mode unlock */ - FLASH->MODEKEYR = FLASH_KEY1; - FLASH->MODEKEYR = FLASH_KEY2; -} - -/********************************************************************* - * @fn FLASH_Lock_Fast - * - * @brief Locks the Fast Program Erase Mode. - * - * @return none - */ -void FLASH_Lock_Fast(void) -{ - FLASH->CTLR |= CR_FLOCK_Set; -} - -/********************************************************************* - * @fn FLASH_BufReset - * - * @brief Flash Buffer reset. - * - * @return none - */ -void FLASH_BufReset(void) -{ - FLASH->CTLR |= CR_PAGE_PG; - FLASH->CTLR |= CR_BUF_RST; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; -} - -/********************************************************************* - * @fn FLASH_BufLoad - * - * @brief Flash Buffer load(4Byte). - * - * @param Address - specifies the address to be programmed. - * Data0 - specifies the data0 to be programmed. - * - * @return none - */ -void FLASH_BufLoad(uint32_t Address, uint32_t Data0) -{ - FLASH->CTLR |= CR_PAGE_PG; - *(__IO uint32_t *)(Address) = Data0; - FLASH->CTLR |= CR_BUF_LOAD; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; -} - -/********************************************************************* - * @fn FLASH_ErasePage_Fast - * - * @brief Erases a specified FLASH page (1page = 256Byte). - * - * @param Page_Address - The page address to be erased. - * - * @return none - */ -void FLASH_ErasePage_Fast(uint32_t Page_Address) -{ - FLASH->CTLR |= CR_PAGE_ER; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_ER; -} - -/********************************************************************* - * @fn FLASH_EraseBlock_32K_Fast - * - * @brief Erases a specified FLASH Block (1Block = 32KByte). - * - * @param Block_Address - The block address to be erased. - * - * @return none - */ -void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) -{ - Block_Address &= 0xFFFF8000; - - FLASH->CTLR |= CR_BER32; - FLASH->ADDR = Block_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_BER32; -} - -/********************************************************************* - * @fn FLASH_ProgramPage_Fast - * - * @brief Program a specified FLASH page (1page = 256Byte). - * - * @param Page_Address - The page address to be programed. - * - * @return none - */ -void FLASH_ProgramPage_Fast(uint32_t Page_Address) -{ - FLASH->CTLR |= CR_PAGE_PG; - FLASH->ADDR = Page_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY) - ; - FLASH->CTLR &= ~CR_PAGE_PG; -} - -/********************************************************************* - * @fn SystemReset_StartMode - * - * @brief Start mode after system reset. - * - * @param Mode - Start mode. - * Start_Mode_USER - USER start after system reset - * Start_Mode_BOOT - Boot start after system reset - * @return none - */ -void SystemReset_StartMode(uint32_t Mode) -{ - FLASH_Unlock(); - - FLASH->BOOT_MODEKEYR = FLASH_KEY1; - FLASH->BOOT_MODEKEYR = FLASH_KEY2; - - FLASH->STATR &= ~(1<<14); - if(Mode == Start_Mode_BOOT){ - FLASH->STATR |= (1<<14); - } - - FLASH_Lock(); -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_flash.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : This file provides all the FLASH firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_flash.h" + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0xFFFFFFFC) + +/* Flash Control Register bits */ +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FLOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_PAGE_ER_Reset ((uint32_t)0xFFFDFFFF) +#define CR_BUF_LOAD ((uint32_t)0x00040000) +#define CR_BUF_RST ((uint32_t)0x00080000) +#define CR_BER32 ((uint32_t)0x00800000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00005000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0xF800) + +/* FLASH Size */ +#define Size_256B 0x100 +#define Size_1KB 0x400 +#define Size_32KB 0x8000 + +/******************************************************************************** + * @fn FLASH_SetLatency + * + * @brief Sets the code latency value. + * + * @param FLASH_Latency - specifies the FLASH Latency value. + * FLASH_Latency_0 - FLASH Zero Latency cycle + * FLASH_Latency_1 - FLASH One Latency cycle + * FLASH_Latency_2 - FLASH Two Latency cycles + * + * @return None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + tmpreg = FLASH->ACTLR; + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + FLASH->ACTLR = tmpreg; +} + +/******************************************************************************** + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/******************************************************************************** + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/******************************************************************************** + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page(1KB). + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - The returned value can be:FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH_Unlock(); + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_OPTER_Reset; + + FLASH_Lock(); + } + return status; +} + +/********************************************************************* + * @fn FLASH_OptionBytePR + * + * @brief Programs option bytes. + * + * @param pbuf - data. + * + * @return none + */ +void FLASH_OptionBytePR(u32* pbuf) +{ + uint8_t i; + + FLASH_EraseOptionBytes(); + FLASH_Unlock_Fast(); + FLASH_BufReset(); + + for(i=0; i<4; i++) + { + FLASH_BufLoad((OB_BASE + 4*i), *pbuf++); + } + + FLASH_ProgramPage_Fast(OB_BASE); + FLASH_Lock_Fast(); +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Sectors - specifies the address of the pages to be write protected. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint8_t WRP0_Data = 0xFF, WRP1_Data = 0xFF, WRP2_Data = 0xFF, WRP3_Data = 0xFF; + uint32_t buf[4]; + uint8_t i; + FLASH_Status status = FLASH_COMPLETE; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint8_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint8_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint8_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint8_t)((FLASH_Pages & WRP3_Mask) >> 24); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + + buf[2] = ((uint32_t)(((uint32_t)(WRP0_Data) & 0x00FF) + (((uint32_t)(~WRP0_Data) & 0x00FF) << 8) \ + + (((uint32_t)(WRP1_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP1_Data) & 0x00FF) << 24))); + buf[3] = ((uint32_t)(((uint32_t)(WRP2_Data) & 0x00FF) + (((uint32_t)(~WRP2_Data) & 0x00FF) << 8) \ + + (((uint32_t)(WRP3_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP3_Data) & 0x00FF) << 24))); + + FLASH_OptionBytePR(buf); + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EnableReadOutProtection + * + * @brief Enables the read out protection. + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_EnableReadOutProtection(void) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t buf[4]; + uint8_t i; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + + buf[0] = 0x000000FF + (buf[0] & 0xFFFF0000); + FLASH_OptionBytePR(buf); + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. + * + * @param OB_IWDG - Selects the IWDG mode + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STOP - Reset event when entering STOP mode. + * OB_STOP_NoRST - No reset generated when entering in STOP + * OB_STOP_RST - Reset generated when entering in STOP + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY + * OB_STDBY_RST - Reset generated when entering in STANDBY + * OB_RST - Selects the reset IO mode and Ignore delay time + * OB_RST_NoEN - Reset IO disable + * OB_RST_EN_DT12ms - Reset IO enable and Ignore delay time 12ms + * OB_RST_EN_DT1ms - Reset IO enable and Ignore delay time 1ms + * OB_RST_EN_DT128us - Reset IO enable and Ignore delay time 128us + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_RST) +{ + FLASH_Status status = FLASH_COMPLETE; + uint8_t UserByte; + uint32_t buf[4]; + uint8_t i; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + UserByte = OB_IWDG | (uint8_t)(OB_STOP | (uint8_t)(OB_STDBY | (uint8_t)(OB_RST | (uint8_t)0xE0))); + + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + buf[0] = ((uint32_t)((((uint32_t)(UserByte) & 0x00FF) << 16) + (((uint32_t)(~UserByte) & 0x00FF) << 24))) + 0x00005AA5; + + FLASH_OptionBytePR(buf); + } + + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1), + * RST_STDBY(Bit2) ,RST_MOD(bit[4:3]) ,DATA0(bit[17:10]) and + * DATA1(bit[25:18]). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt + * FLASH_IT_EOP - FLASH end of operation Interrupt + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + FLASH->STATR = FLASH_FLAG; +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_FLOCK_Set; +} + +/********************************************************************* + * @fn FLASH_BufReset + * + * @brief Flash Buffer reset. + * + * @return none + */ +void FLASH_BufReset(void) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_BufLoad + * + * @brief Flash Buffer load(4Byte). + * + * @param Address - specifies the address to be programmed. + * Data0 - specifies the data0 to be programmed. + * + * @return none + */ +void FLASH_BufLoad(uint32_t Address, uint32_t Data0) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + *(__IO uint32_t *)(Address) = Data0; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_ER; +} + +/********************************************************************* + * @fn FLASH_EraseBlock_32K_Fast + * + * @brief Erases a specified FLASH Block (1Block = 32KByte). + * + * @param Block_Address - The block address to be erased. + * + * @return none + */ +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + Block_Address &= 0xFFFF8000; + + FLASH->CTLR |= CR_BER32; + FLASH->ADDR = Block_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_BER32; +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + FLASH->CTLR |= CR_PAGE_PG; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn SystemReset_StartMode + * + * @brief Start mode after system reset. + * + * @param Mode - Start mode. + * Start_Mode_USER - USER start after system reset + * Start_Mode_BOOT - Boot start after system reset + * @return none + */ +void SystemReset_StartMode(uint32_t Mode) +{ + FLASH_Unlock(); + + FLASH->BOOT_MODEKEYR = FLASH_KEY1; + FLASH->BOOT_MODEKEYR = FLASH_KEY2; + + FLASH->STATR &= ~(1<<14); + if(Mode == Start_Mode_BOOT){ + FLASH->STATR |= (1<<14); + } + + FLASH_Lock(); +} + +/********************************************************************* + * @fn ROM_ERASE + * + * @brief Select erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Cnt - Erases count. + * Erase_Size - Erases size select.The returned value can be: + * Size_32KB, Size_1KB, Size_256B. + * + * @return none. + */ +static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) +{ + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + do{ + if(Erase_Size == Size_32KB) + { + FLASH->CTLR |= CR_BER32; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR |= CR_PER_Set; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR |= CR_PAGE_ER; + } + + FLASH->ADDR = StartAddr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + + if(Erase_Size == Size_32KB) + { + FLASH->CTLR &= ~CR_BER32; + StartAddr += Size_32KB; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR &= ~CR_PER_Set; + StartAddr += Size_1KB; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR &= ~CR_PAGE_ER; + StartAddr += Size_256B; + } + }while(--Cnt); +} + +/********************************************************************* + * @fn FLASH_ROM_ERASE + * + * @brief Erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Length - Erases Flash start Length(Length%256 == 0). + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length) +{ + uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + Addr0 = StartAddr; + + if(Length >= Size_32KB) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_1KB) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_256B) + { + Length0 = Length; + } + + /* Erase 32KB */ + if(Length0 >= Size_32KB)//front + { + Length = Length0; + if(Addr0 & (Size_32KB - 1)) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB); + } + + if(Length1 >= Size_32KB)//back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_32KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1))); + Length1 = (StartAddr + Length1) & (Size_32KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB); + } + + /* Erase 1KB */ + if(Length0 >= Size_1KB) //front + { + Length = Length0; + if(Addr0 & (Size_1KB - 1)) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB); + } + + if(Length1 >= Size_1KB) //back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_1KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1))); + Length1 = (StartAddr + Length1) & (Size_1KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB); + } + + /* Erase 256B */ + if(Length0)//front + { + ROM_ERASE(Addr0, (Length0 >> 8), Size_256B); + } + + if(Length1)//back + { + ROM_ERASE(Addr1, (Length1 >> 8), Size_256B); + } + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + +/********************************************************************* + * @fn FLASH_ROM_WRITE + * + * @brief Writes a specified FLASH . + * + * @param StartAddr - Writes Flash start address(StartAddr%256 == 0). + * Length - Writes Flash start Length(Length%256 == 0). + * pbuf - Writes Flash value buffer. + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length) +{ + uint32_t i, adr; + uint8_t size; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + adr = StartAddr; + i = Length >> 8; + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset); + + do{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + size = 64; + while(size) + { + *(uint32_t *)StartAddr = *(uint32_t *)pbuf; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + StartAddr += 4; + pbuf += 1; + size -= 1; + } + + FLASH->ADDR = adr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + adr += 256; + }while(--i); + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_gpio.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_gpio.c index 6aff8f3..b32bc5e 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_gpio.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_gpio.c @@ -1,591 +1,745 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_gpio.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the GPIO firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_gpio.h" -#include "ch32x035_rcc.h" - -/* MASK */ -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) -#define DBGAFR_TIM1RP_MASK ((uint32_t)0x00400000) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) - -volatile uint32_t CFGHR_tmpA = 0x44444444; -volatile uint32_t CFGHR_tmpB = 0x44444444; -volatile uint32_t CFGHR_tmpC = 0x44444444; - -/********************************************************************* - * @fn GPIO_DeInit - * - * @brief Deinitializes the GPIOx peripheral registers to their default - * reset values. - * - * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. - * - * @return none - */ -void GPIO_DeInit(GPIO_TypeDef *GPIOx) -{ - if(GPIOx == GPIOA) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); - } - else if(GPIOx == GPIOB) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); - } - else if(GPIOx == GPIOC) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); - } -} - -/********************************************************************* - * @fn GPIO_AFIODeInit - * - * @brief Deinitializes the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * - * @return none - */ -void GPIO_AFIODeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); -} - -/********************************************************************* - * @fn GPIO_Init - * - * @brief GPIOx - where x can be (A..C) to select the GPIO peripheral. - * Note - Only PA0--PA15 and PC16--PC17 support input pull-down - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. - * - * @return none - */ -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - - if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - { - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } - - if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x0000FF)) != 0x00) - { - tmpreg = GPIOx->CFGLR; - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << pinpos); - } - else - { - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CFGLR = tmpreg; - } - - if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF00)) != 0x00) - { - if(GPIOx == GPIOA) - { - tmpreg = CFGHR_tmpA; - } - else if(GPIOx == GPIOB) - { - tmpreg = CFGHR_tmpB; - } - else if(GPIOx == GPIOC) - { - tmpreg = CFGHR_tmpC; - } - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x08)); - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - } - } - GPIOx->CFGHR = tmpreg; - - if(GPIOx == GPIOA) - { - CFGHR_tmpA = tmpreg; - } - else if(GPIOx == GPIOB) - { - CFGHR_tmpB = tmpreg; - } - else if(GPIOx == GPIOC) - { - CFGHR_tmpC = tmpreg; - } - } - - if(GPIO_InitStruct->GPIO_Pin > 0x00FFFF) - { - tmpreg = GPIOx->CFGXR; - - for(pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x10)); - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - - if(currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x10)); - } - - if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSXR = (((uint32_t)0x01) << (pinpos)); - } - } - } - GPIOx->CFGXR = tmpreg; - } -} - -/********************************************************************* - * @fn GPIO_StructInit - * - * @brief Fills each GPIO_InitStruct member with its default - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) -{ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/********************************************************************* - * @fn GPIO_ReadInputDataBit - * - * @brief GPIOx - where x can be (A..C) to select the GPIO peripheral. - * - * @param GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..23). - * - * @return The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadInputData - * - * @brief Reads the specified GPIO input data port. - * - * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. - * - * @return The output port pin value. - */ -uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) -{ - uint32_t val; - - val = ( uint32_t )GPIOx->INDR; - - return ( val ); -} - -/********************************************************************* - * @fn GPIO_ReadOutputDataBit - * - * @brief Reads the specified output data port bit. - * - * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..23). - * - * @return none - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadOutputData - * - * @brief Reads the specified GPIO output data port. - * - * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. - * - * @return GPIO output port pin value. - */ -uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) -{ - uint32_t val; - - val = ( uint32_t )GPIOx->OUTDR; - - return ( val ); -} - -/********************************************************************* - * @fn GPIO_SetBits - * - * @brief Sets the selected data port bits. - * - * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..23). - * - * @return none - */ -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - if((GPIO_Pin & ((uint32_t)0x00FFFF)) != 0x00) - { - GPIOx->BSHR = GPIO_Pin; - } - - if(GPIO_Pin > 0x00FFFF) - { - GPIOx->BSXR = (GPIO_Pin>>0x10); - } -} - -/********************************************************************* - * @fn GPIO_ResetBits - * - * @brief Clears the selected data port bits. - * - * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..23). - * - * @return none - */ -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - GPIOx->BCR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_WriteBit - * - * @brief Sets or clears the selected data port bit. - * - * @param GPIO_Pin - specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..23). - * BitVal - specifies the value to be written to the selected bit. - * Bit_RESET - to clear the port pin. - * Bit_SET - to set the port pin. - * - * @return none - */ -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal) -{ - if(BitVal != Bit_RESET) - { - if((GPIO_Pin & ((uint32_t)0x00FFFF)) != 0x00) - { - GPIOx->BSHR = GPIO_Pin; - } - - if(GPIO_Pin > 0x00FFFF) - { - GPIOx->BSXR = (GPIO_Pin>>0x10); - } - } - else - { - GPIOx->BCR = GPIO_Pin; - } -} - -/********************************************************************* - * @fn GPIO_Write - * - * @brief Writes data to the specified GPIO data port. - * - * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. - * PortVal - specifies the value to be written to the port output data register. - * - * @return none - */ -void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal) -{ - GPIOx->OUTDR = PortVal; -} - -/********************************************************************* - * @fn GPIO_PinLockConfig - * - * @brief Locks GPIO Pins configuration registers. - * - * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..23). - * - * @return none - */ -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint32_t tmp = 0x01000000; - - tmp |= GPIO_Pin; - GPIOx->LCKR = tmp; - GPIOx->LCKR = GPIO_Pin; - GPIOx->LCKR = tmp; - tmp = GPIOx->LCKR; - tmp = GPIOx->LCKR; -} - -/********************************************************************* - * @fn GPIO_PinRemapConfig - * - * @brief Changes the mapping of the specified pin. - * - * @param GPIO_Remap - selects the pin to remap. - * GPIO_Remap_SPI1 - SPI1 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_SPI1 - SPI1 Partial2 Alternate Function mapping - * GPIO_FullRemap_SPI1 - SPI1 Full Alternate Function mapping - * GPIO_PartialRemap1_I2C1 - I2C1 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_I2C1 - I2C1 Partial2 Alternate Function mapping - * GPIO_PartialRemap3_I2C1 - I2C1 Partial3 Alternate Function mapping - * GPIO_PartialRemap4_I2C1 - I2C1 Partial4 Alternate Function mapping - * GPIO_FullRemap_I2C1 - I2C1 Full Alternate Function mapping - * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping - * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping - * GPIO_PartialRemap1_USART2 - USART2 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_USART2 - USART2 Partial2 Alternate Function mapping - * GPIO_PartialRemap3_USART2 - USART2 Partial3 Alternate Function mapping - * GPIO_FullRemap_USART2 - USART2 Full Alternate Function mapping - * GPIO_PartialRemap1_USART3 - USART3 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_USART3 - USART3 Partial2 Alternate Function mapping - * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping - * GPIO_PartialRemap1_USART4 - USART4 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_USART4 - USART4 Partial2 Alternate Function mapping - * GPIO_PartialRemap3_USART4 - USART4 Partial3 Alternate Function mapping - * GPIO_PartialRemap4_USART4 - USART4 Partial4 Alternate Function mapping - * GPIO_PartialRemap5_USART4 - USART4 Partial5 Alternate Function mapping - * GPIO_PartialRemap6_USART4 - USART4 Partial6 Alternate Function mapping - * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping - * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping - * GPIO_PartialRemap3_TIM1 - TIM1 Partial3 Alternate Function mapping - * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping - * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping - * GPIO_PartialRemap3_TIM2 - TIM2 Partial3 Alternate Function mapping - * GPIO_PartialRemap4_TIM2 - TIM2 Partial4 Alternate Function mapping - * GPIO_PartialRemap5_TIM2 - TIM2 Partial5 Alternate Function mapping - * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping - * GPIO_PartialRemap1_TIM3 - TIM3 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_TIM3 - TIM3 Partial2 Alternate Function mapping - * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping - * GPIO_Remap_PIOC - PIOC Alternate Function mapping - * GPIO_Remap_SWJ_Disable - SDI Disabled (SDI) - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) -{ - uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; - - tmpreg = AFIO->PCFR1; - - tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - tmp = GPIO_Remap & LSB_MASK; - - /* Clear bit */ - if((GPIO_Remap & 0x08000000) == 0x08000000) /* 3bit */ - { - if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] SDI */ - { - tmpreg &= DBGAFR_SWJCFG_MASK; - AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; - } - else if((GPIO_Remap & DBGAFR_TIM1RP_MASK) == DBGAFR_TIM1RP_MASK) /* [31:16] 3bit */ - { - tmp1 = ((uint32_t)0x07) << 15; - tmpreg &= ~tmp1; - - if(NewState != DISABLE) - { - tmpreg |= (tmp << 15); - } - - AFIO->PCFR1 = tmpreg; - return; - } - else if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == DBGAFR_LOCATION_MASK) /* [31:16] 3bit */ - { - tmp1 = ((uint32_t)0x07) << (tmpmask + 0x10); - tmpreg &= ~tmp1; - } - else /* [15:0] 3bit */ - { - tmp1 = ((uint32_t)0x07) << tmpmask; - tmpreg &= ~tmp1; - } - } - else - { - if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */ - { - tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10); - tmpreg &= ~tmp1; - } - else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - } - else /* [31:0] 1bit */ - { - tmpreg &= ~(tmp << (((GPIO_Remap & 0x00FFFFFF ) >> 0x15) * 0x10)); - } - } - - /* Set bit */ - if(NewState != DISABLE) - { - tmpreg |= (tmp << (((GPIO_Remap & 0x00FFFFFF )>> 0x15) * 0x10)); - } - - AFIO->PCFR1 = tmpreg; -} - -/********************************************************************* - * @fn GPIO_EXTILineConfig - * - * @brief Selects the GPIO pin used as EXTI Line. - * - * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..C). - * GPIO_PinSource - specifies the EXTI line to be configured. - * This parameter can be GPIO_PinSourcex where x can be (0..23). - * - * @return none - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint16_t GPIO_PinSource) -{ - uint32_t tmp = 0x00; - - tmp = ((uint32_t)0x03) << (0x02 * (GPIO_PinSource & (uint8_t)0x0F)); - AFIO->EXTICR[GPIO_PinSource >> 0x04] &= ~tmp; - AFIO->EXTICR[GPIO_PinSource >> 0x04] |= (((uint32_t)GPIO_PortSource) << (0x02 * (GPIO_PinSource & (uint8_t)0x0F))); -} - -/********************************************************************* - * @fn GPIO_IPD_Unused - * - * @brief Configure unused GPIO as input pull-up. - * - * @param none - * - * @return none - */ -void GPIO_IPD_Unused(void) -{ - GPIO_InitTypeDef GPIO_InitStructure = {0}; - - /* All pull-up */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE); - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - GPIO_PinRemapConfig(GPIO_Remap_SWJ_Disable, ENABLE); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_Init(GPIOC, &GPIO_InitStructure); - -} - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_gpio.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/08/06 + * Description : This file provides all the GPIO firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_gpio.h" +#include "ch32x035_rcc.h" + +/* MASK */ +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_TIM1RP_MASK ((uint32_t)0x00400000) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +volatile uint32_t CFGHR_tmpA = 0x44444444; +volatile uint32_t CFGHR_tmpB = 0x44444444; +volatile uint32_t CFGHR_tmpC = 0x44444444; + +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..C) to select the GPIO peripheral. + * Note - Only PA0--PA15 and PC16--PC17 support input pull-down + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x0000FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF00)) != 0x00) + { + if(((*( uint32_t * )0x1FFFF704) & 0x000000F0) == 0) + { + if(GPIOx == GPIOA) + { + tmpreg = CFGHR_tmpA; + } + else if(GPIOx == GPIOB) + { + tmpreg = CFGHR_tmpB; + } + else if(GPIOx == GPIOC) + { + tmpreg = CFGHR_tmpC; + } + } + else + { + tmpreg = GPIOx->CFGHR; + } + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CFGHR = tmpreg; + if(((*( uint32_t * )0x1FFFF704) & 0x000000F0) == 0) + { + if(GPIOx == GPIOA) + { + CFGHR_tmpA = tmpreg; + } + else if(GPIOx == GPIOB) + { + CFGHR_tmpB = tmpreg; + } + else if(GPIOx == GPIOC) + { + CFGHR_tmpC = tmpreg; + } + } + } + + if(GPIO_InitStruct->GPIO_Pin > 0x00FFFF) + { + tmpreg = GPIOx->CFGXR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x10)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x10)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSXR = (((uint32_t)0x01) << (pinpos)); + } + } + } + GPIOx->CFGXR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..C) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..23). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * + * @return The output port pin value. + */ +uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + uint32_t val; + + val = ( uint32_t )GPIOx->INDR; + + return ( val ); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..23). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + uint32_t val; + + val = ( uint32_t )GPIOx->OUTDR; + + return ( val ); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..23). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + GPIOx->BSHR = (GPIO_Pin & (uint32_t)0x0000FFFF); + GPIOx->BSXR = ((GPIO_Pin & (uint32_t)0xFFFF0000) >> 0x10); +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..23). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..23). + * BitVal - specifies the value to be written to the selected bit. + * Bit_RESET - to clear the port pin. + * Bit_SET - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = (GPIO_Pin & (uint32_t)0x0000FFFF); + GPIOx->BSXR = ((GPIO_Pin & (uint32_t)0xFFFF0000) >> 0x10); + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..23). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t tmp = 0x01000000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_Remap_SPI1 - SPI1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_SPI1 - SPI1 Partial2 Alternate Function mapping + * GPIO_FullRemap_SPI1 - SPI1 Full Alternate Function mapping + * GPIO_PartialRemap1_I2C1 - I2C1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_I2C1 - I2C1 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_I2C1 - I2C1 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_I2C1 - I2C1 Partial4 Alternate Function mapping + * GPIO_FullRemap_I2C1 - I2C1 Full Alternate Function mapping + * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping + * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping + * GPIO_PartialRemap1_USART2 - USART2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART2 - USART2 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_USART2 - USART2 Partial3 Alternate Function mapping + * GPIO_FullRemap_USART2 - USART2 Full Alternate Function mapping + * GPIO_PartialRemap1_USART3 - USART3 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART3 - USART3 Partial2 Alternate Function mapping + * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping + * GPIO_PartialRemap1_USART4 - USART4 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART4 - USART4 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_USART4 - USART4 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_USART4 - USART4 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_USART4 - USART4 Partial5 Alternate Function mapping + * GPIO_PartialRemap6_USART4 - USART4 Partial6 Alternate Function mapping + * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_TIM1 - TIM1 Partial3 Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_TIM2 - TIM2 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_TIM2 - TIM2 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_TIM2 - TIM2 Partial5 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM3 - TIM3 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM3 - TIM3 Partial2 Alternate Function mapping + * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping + * GPIO_Remap_PIOC - PIOC Alternate Function mapping + * GPIO_Remap_SWJ_Disable - SDI Disabled (SDI) + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + tmpreg = AFIO->PCFR1; + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + /* Clear bit */ + if((GPIO_Remap & 0x08000000) == 0x08000000) /* 3bit */ + { + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] SDI */ + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; + } + else if((GPIO_Remap & DBGAFR_TIM1RP_MASK) == DBGAFR_TIM1RP_MASK) /* [31:16] 3bit */ + { + tmp1 = ((uint32_t)0x07) << 15; + tmpreg &= ~tmp1; + + if(NewState != DISABLE) + { + tmpreg |= (tmp << 15); + } + + AFIO->PCFR1 = tmpreg; + return; + } + else if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == DBGAFR_LOCATION_MASK) /* [31:16] 3bit */ + { + tmp1 = ((uint32_t)0x07) << (tmpmask + 0x10); + tmpreg &= ~tmp1; + } + else /* [15:0] 3bit */ + { + tmp1 = ((uint32_t)0x07) << tmpmask; + tmpreg &= ~tmp1; + } + } + else + { + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */ + { + tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10); + tmpreg &= ~tmp1; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + } + else /* [31:0] 1bit */ + { + tmpreg &= ~(tmp << (((GPIO_Remap & 0x00FFFFFF ) >> 0x15) * 0x10)); + } + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg |= (tmp << (((GPIO_Remap & 0x00FFFFFF )>> 0x15) * 0x10)); + } + + AFIO->PCFR1 = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..C). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..23). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint16_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)0x03) << (0x02 * (GPIO_PinSource & (uint8_t)0x0F)); + AFIO->EXTICR[GPIO_PinSource >> 0x04] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x04] |= (((uint32_t)GPIO_PortSource) << (0x02 * (GPIO_PinSource & (uint8_t)0x0F))); +} + +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-up. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE); + chip = *( uint32_t * )0x1FFFF704 & (~0x000000F1); + switch(chip) + { + case 0x03510600: //CH32X035C8T6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x03560600: //CH32X035G8U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20\ + |GPIO_Pin_21|GPIO_Pin_22\ + |GPIO_Pin_23|GPIO_Pin_14\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x035B0600: //CH32X035G8R6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20\ + |GPIO_Pin_21|GPIO_Pin_22\ + |GPIO_Pin_23|GPIO_Pin_14\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x035E0600: //CH32X035F8U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20\ + |GPIO_Pin_21|GPIO_Pin_22|GPIO_Pin_23\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_10\ + |GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_14|GPIO_Pin_13\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x03570600: //CH32X035F7P6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21\ + |GPIO_Pin_22|GPIO_Pin_23; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x03117000: //CH32X033F8P6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20\ + |GPIO_Pin_21|GPIO_Pin_22|GPIO_Pin_23\ + |GPIO_Pin_8|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21\ + |GPIO_Pin_22|GPIO_Pin_23; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_20|GPIO_Pin_21\ + |GPIO_Pin_22|GPIO_Pin_23; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + default: + { + break; + } + + } + +} + diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_i2c.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_i2c.c index 77e7dbb..b1b37b9 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_i2c.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_i2c.c @@ -1,967 +1,967 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_i2c.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the I2C firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_i2c.h" -#include "ch32x035_rcc.h" - -/* I2C SPE mask */ -#define CTLR1_PE_Set ((uint16_t)0x0001) -#define CTLR1_PE_Reset ((uint16_t)0xFFFE) - -/* I2C START mask */ -#define CTLR1_START_Set ((uint16_t)0x0100) -#define CTLR1_START_Reset ((uint16_t)0xFEFF) - -/* I2C STOP mask */ -#define CTLR1_STOP_Set ((uint16_t)0x0200) -#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) - -/* I2C ACK mask */ -#define CTLR1_ACK_Set ((uint16_t)0x0400) -#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) - -/* I2C ENGC mask */ -#define CTLR1_ENGC_Set ((uint16_t)0x0040) -#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) - -/* I2C SWRST mask */ -#define CTLR1_SWRST_Set ((uint16_t)0x8000) -#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) - -/* I2C PEC mask */ -#define CTLR1_PEC_Set ((uint16_t)0x1000) -#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) - -/* I2C ENPEC mask */ -#define CTLR1_ENPEC_Set ((uint16_t)0x0020) -#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) - -/* I2C ENARP mask */ -#define CTLR1_ENARP_Set ((uint16_t)0x0010) -#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) - -/* I2C NOSTRETCH mask */ -#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) -#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) - -/* I2C registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) - -/* I2C DMAEN mask */ -#define CTLR2_DMAEN_Set ((uint16_t)0x0800) -#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) - -/* I2C LAST mask */ -#define CTLR2_LAST_Set ((uint16_t)0x1000) -#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) - -/* I2C FREQ mask */ -#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) - -/* I2C ADD0 mask */ -#define OADDR1_ADD0_Set ((uint16_t)0x0001) -#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) - -/* I2C ENDUAL mask */ -#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) -#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) - -/* I2C ADD2 mask */ -#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) - -/* I2C F/S mask */ -#define CKCFGR_FS_Set ((uint16_t)0x8000) - -/* I2C CCR mask */ -#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) - -/* I2C FLAG mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) - -/* I2C Interrupt Enable mask */ -#define ITEN_Mask ((uint32_t)0x07000000) - -/********************************************************************* - * @fn I2C_DeInit - * - * @brief Deinitializes the I2Cx peripheral registers to their default - * reset values. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * - * @return none - */ -void I2C_DeInit(I2C_TypeDef *I2Cx) -{ - if(I2Cx == I2C1) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); - } -} - -/********************************************************************* - * @fn I2C_Init - * - * @brief Initializes the I2Cx peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified I2C peripheral. - * - * @return none - */ -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) -{ - uint16_t tmpreg = 0, freqrange = 0; - uint16_t result = 0x04; - uint32_t pclk1 = 8000000; - - RCC_ClocksTypeDef rcc_clocks; - - tmpreg = I2Cx->CTLR2; - tmpreg &= CTLR2_FREQ_Reset; - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - I2Cx->CTLR2 = tmpreg; - - I2Cx->CTLR1 &= CTLR1_PE_Reset; - tmpreg = 0; - - if(I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - - if(result < 0x04) - { - result = 0x04; - } - - tmpreg |= result; - } - else - { - if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else - { - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - result |= I2C_DutyCycle_16_9; - } - - if((result & CKCFGR_CCR_Set) == 0) - { - result |= (uint16_t)0x0001; - } - - tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); - } - - I2Cx->CKCFGR = tmpreg; - I2Cx->CTLR1 |= CTLR1_PE_Set; - - tmpreg = I2Cx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - I2Cx->CTLR1 = tmpreg; - - I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/********************************************************************* - * @fn I2C_StructInit - * - * @brief Fills each I2C_InitStruct member with its default value. - * - * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) -{ - I2C_InitStruct->I2C_ClockSpeed = 5000; - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStruct->I2C_OwnAddress1 = 0; - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/********************************************************************* - * @fn I2C_Cmd - * - * @brief Enables or disables the specified I2C peripheral. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PE_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PE_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMACmd - * - * @brief Enables or disables the specified I2C DMA requests. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_DMAEN_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; - } -} - -/********************************************************************* - * @fn I2C_DMALastTransferCmd - * - * @brief Specifies if the next DMA transfer will be the last one. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= CTLR2_LAST_Set; - } - else - { - I2Cx->CTLR2 &= CTLR2_LAST_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTART - * - * @brief Generates I2Cx communication START condition. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_START_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_START_Reset; - } -} - -/********************************************************************* - * @fn I2C_GenerateSTOP - * - * @brief Generates I2Cx communication STOP condition. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_STOP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_STOP_Reset; - } -} - -/********************************************************************* - * @fn I2C_AcknowledgeConfig - * - * @brief Enables or disables the specified I2C acknowledge feature. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ACK_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ACK_Reset; - } -} - -/********************************************************************* - * @fn I2C_OwnAddress2Config - * - * @brief Configures the specified I2C own address2. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * Address - specifies the 7bit I2C own address2. - * - * @return none - */ -void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - tmpreg = I2Cx->OADDR2; - tmpreg &= OADDR2_ADD2_Reset; - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - I2Cx->OADDR2 = tmpreg; -} - -/********************************************************************* - * @fn I2C_DualAddressCmd - * - * @brief Enables or disables the specified I2C dual addressing mode. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; - } - else - { - I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; - } -} - -/********************************************************************* - * @fn I2C_GeneralCallCmd - * - * @brief Enables or disables the specified I2C general call feature. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENGC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENGC_Reset; - } -} - -/********************************************************************* - * @fn I2C_ITConfig - * - * @brief Enables or disables the specified I2C interrupts. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. - * I2C_IT_BUF - Buffer interrupt mask. - * I2C_IT_EVT - Event interrupt mask. - * I2C_IT_ERR - Error interrupt mask. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR2 |= I2C_IT; - } - else - { - I2Cx->CTLR2 &= (uint16_t)~I2C_IT; - } -} - -/********************************************************************* - * @fn I2C_SendData - * - * @brief Sends a data byte through the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * Data - Byte to be transmitted. - * - * @return none - */ -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) -{ - I2Cx->DATAR = Data; -} - -/********************************************************************* - * @fn I2C_ReceiveData - * - * @brief Returns the most recent received data by the I2Cx peripheral. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * - * @return The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) -{ - return (uint8_t)I2Cx->DATAR; -} - -/********************************************************************* - * @fn I2C_Send7bitAddress - * - * @brief Transmits the address byte to select the slave device. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * Address - specifies the slave address which will be transmitted. - * I2C_Direction - specifies whether the I2C device will be a - * Transmitter or a Receiver. - * I2C_Direction_Transmitter - Transmitter mode. - * I2C_Direction_Receiver - Receiver mode. - * - * @return none - */ -void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - if(I2C_Direction != I2C_Direction_Transmitter) - { - Address |= OADDR1_ADD0_Set; - } - else - { - Address &= OADDR1_ADD0_Reset; - } - - I2Cx->DATAR = Address; -} - -/********************************************************************* - * @fn I2C_ReadRegister - * - * @brief Reads the specified I2C register and returns its value. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_Register - specifies the register to read. - * I2C_Register_CTLR1. - * I2C_Register_CTLR2. - * I2C_Register_OADDR1. - * I2C_Register_OADDR2. - * I2C_Register_DATAR. - * I2C_Register_STAR1. - * I2C_Register_STAR2. - * I2C_Register_CKCFGR. - * I2C_Register_RTR. - * - * @return none - */ -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)I2Cx; - tmp += I2C_Register; - - return (*(__IO uint16_t *)tmp); -} - -/********************************************************************* - * @fn I2C_SoftwareResetCmd - * - * @brief Enables or disables the specified I2C software reset. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_SWRST_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_SWRST_Reset; - } -} - -/********************************************************************* - * @fn I2C_NACKPositionConfig - * - * @brief Selects the specified I2C NACK position in master receiver mode. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_NACKPosition - specifies the NACK position. - * I2C_NACKPosition_Next - indicates that the next byte will be - * the last received byte. - * I2C_NACKPosition_Current - indicates that current byte is the - * last received byte. - * Note- - * This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * @return none - */ -void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) -{ - if(I2C_NACKPosition == I2C_NACKPosition_Next) - { - I2Cx->CTLR1 |= I2C_NACKPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_NACKPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_TransmitPEC - * - * @brief Enables or disables the specified I2C PEC transfer. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_PEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_PEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_PECPositionConfig - * - * @brief Selects the specified I2C PEC position. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_PECPosition - specifies the PEC position. - * I2C_PECPosition_Next - indicates that the next byte is PEC. - * I2C_PECPosition_Current - indicates that current byte is PEC. - * - * @return none - */ -void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) -{ - if(I2C_PECPosition == I2C_PECPosition_Next) - { - I2Cx->CTLR1 |= I2C_PECPosition_Next; - } - else - { - I2Cx->CTLR1 &= I2C_PECPosition_Current; - } -} - -/********************************************************************* - * @fn I2C_CalculatePEC - * - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * - * @param I2Cx- where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENPEC_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; - } -} - -/********************************************************************* - * @fn I2C_GetPEC - * - * @brief Returns the PEC value for the specified I2C. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * - * @return The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) -{ - return ((I2Cx->STAR2) >> 8); -} - -/********************************************************************* - * @fn I2C_ARPCmd - * - * @brief Enables or disables the specified I2C ARP. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return The PEC value. - */ -void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - I2Cx->CTLR1 |= CTLR1_ENARP_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_ENARP_Reset; - } -} - -/********************************************************************* - * @fn I2C_StretchClockCmd - * - * @brief Enables or disables the specified I2C Clock stretching. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if(NewState == DISABLE) - { - I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; - } - else - { - I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; - } -} - -/********************************************************************* - * @fn I2C_FastModeDutyCycleConfig - * - * @brief Selects the specified I2C fast mode duty cycle. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_DutyCycle - specifies the fast mode duty cycle. - * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. - * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. - * - * @return none - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) -{ - if(I2C_DutyCycle != I2C_DutyCycle_16_9) - { - I2Cx->CKCFGR &= I2C_DutyCycle_2; - } - else - { - I2Cx->CKCFGR |= I2C_DutyCycle_16_9; - } -} - -/********************************************************************* - * @fn I2C_CheckEvent - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx- where x can be 1 to select the I2C peripheral. - * I2C_EVENT: specifies the event to be checked. - * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. - * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. - * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. - * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. - * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. - * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. - * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. - * I2C_EVENT_MASTER_MODE_SELECT - EVT5. - * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. - * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. - * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. - * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. - * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. - * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. - * - * @return ErrorStatus - READY or NoREADY. - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = NoREADY; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - - lastevent = (flag1 | flag2) & FLAG_Mask; - - if((lastevent & I2C_EVENT) == I2C_EVENT) - { - status = READY; - } - else - { - status = NoREADY; - } - - return status; -} - -/********************************************************************* - * @fn I2C_GetLastEvent - * - * @brief Returns the last I2Cx Event. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * - * @return none - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - flag1 = I2Cx->STAR1; - flag2 = I2Cx->STAR2; - flag2 = flag2 << 16; - lastevent = (flag1 | flag2) & FLAG_Mask; - - return lastevent; -} - -/********************************************************************* - * @fn I2C_GetFlagStatus - * - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to check. - * I2C_FLAG_DUALF - Dual flag (Slave mode). - * I2C_FLAG_GENCALL - General call header flag (Slave mode). - * I2C_FLAG_TRA - Transmitter/Receiver flag. - * I2C_FLAG_BUSY - Bus busy flag. - * I2C_FLAG_MSL - Master/Slave flag. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * I2C_FLAG_TXE - Data register empty flag (Transmitter). - * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. - * I2C_FLAG_STOPF - Stop detection flag (Slave mode). - * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). - * I2C_FLAG_BTF - Byte transfer finished flag. - * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDA". - * I2C_FLAG_SB - Start bit flag (Master mode). - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - i2cxbase = (uint32_t)I2Cx; - i2creg = I2C_FLAG >> 28; - I2C_FLAG &= FLAG_Mask; - - if(i2creg != 0) - { - i2cxbase += 0x14; - } - else - { - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearFlag - * - * @brief Clears the I2Cx's pending flags. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_FLAG - specifies the flag to clear. - * I2C_FLAG_PECERR - PEC error in reception flag. - * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). - * I2C_FLAG_AF - Acknowledge failure flag. - * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). - * I2C_FLAG_BERR - Bus error flag. - * Note- - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DATAR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DATAR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SATR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR - * register (I2C_SendData()). - * @return none - */ -void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - - flagpos = I2C_FLAG & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} - -/********************************************************************* - * @fn I2C_GetITStatus - * - * @brief Checks whether the specified I2C interrupt has occurred or not. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * II2C_IT - specifies the interrupt source to check. - * I2C_IT_PECERR - PEC error in reception flag. - * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). - * I2C_IT_AF - Acknowledge failure flag. - * I2C_IT_ARLO - Arbitration lost flag (Master mode). - * I2C_IT_BERR - Bus error flag. - * I2C_IT_TXE - Data register empty flag (Transmitter). - * I2C_IT_RXNE - Data register not empty (Receiver) flag. - * I2C_IT_STOPF - Stop detection flag (Slave mode). - * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). - * I2C_IT_BTF - Byte transfer finished flag. - * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched - * flag (Slave mode)"ENDAD". - * I2C_IT_SB - Start bit flag (Master mode). - * - * @return none - */ -ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); - I2C_IT &= FLAG_Mask; - - if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn I2C_ClearITPendingBit - * - * @brief Clears the I2Cx interrupt pending bits. - * - * @param I2Cx - where x can be 1 to select the I2C peripheral. - * I2C_IT - specifies the interrupt pending bit to clear. - * I2C_IT_PECERR - PEC error in reception interrupt. - * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). - * I2C_IT_AF - Acknowledge failure interrupt. - * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). - * I2C_IT_BERR - Bus error interrupt. - * Note- - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DATAR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DATAR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_STAR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DATAR register (I2C_SendData()). - * - * @return none - */ -void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - - flagpos = I2C_IT & FLAG_Mask; - I2Cx->STAR1 = (uint16_t)~flagpos; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_i2c.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/03/19 + * Description : This file provides all the I2C firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_i2c.h" +#include "ch32x035_rcc.h" + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * I2C_Register_RTR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * Note- + * This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. + * I2C_EVENT_MASTER_MODE_SELECT - EVT5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. + * + * @return ErrorStatus - READY or NoREADY. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = NoREADY; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = READY; + } + else + { + status = NoREADY; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SATR2 register ((void)(I2Cx->STAR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR + * register (I2C_SendData()). + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_STAR2 register ((void)(I2Cx->STAR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DATAR register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_iwdg.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_iwdg.c index b519a12..bcac646 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_iwdg.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_iwdg.c @@ -1,122 +1,122 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_iwdg.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the IWDG firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_iwdg.h" - -/* CTLR register bit mask */ -#define CTLR_KEY_Reload ((uint16_t)0xAAAA) -#define CTLR_KEY_Enable ((uint16_t)0xCCCC) - -/********************************************************************* - * @fn IWDG_WriteAccessCmd - * - * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. - * - * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and - * IWDG_RLDR registers. - * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR - * and IWDG_RLDR registers. - * - * @return none - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - IWDG->CTLR = IWDG_WriteAccess; -} - -/********************************************************************* - * @fn IWDG_SetPrescaler - * - * @brief Sets IWDG Prescaler value. - * - * @param IWDG_Prescaler - specifies the IWDG Prescaler value. - * IWDG_Prescaler_4 - IWDG prescaler set to 4. - * IWDG_Prescaler_8 - IWDG prescaler set to 8. - * IWDG_Prescaler_16 - IWDG prescaler set to 16. - * IWDG_Prescaler_32 - IWDG prescaler set to 32. - * IWDG_Prescaler_64 - IWDG prescaler set to 64. - * IWDG_Prescaler_128 - IWDG prescaler set to 128. - * IWDG_Prescaler_256 - IWDG prescaler set to 256. - * - * @return none - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - IWDG->PSCR = IWDG_Prescaler; -} - -/********************************************************************* - * @fn IWDG_SetReload - * - * @brief Sets IWDG Reload value. - * - * @param Reload - specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * - * @return none - */ -void IWDG_SetReload(uint16_t Reload) -{ - IWDG->RLDR = Reload; -} - -/********************************************************************* - * @fn IWDG_ReloadCounter - * - * @brief Reloads IWDG counter with value defined in the reload register. - * - * @return none - */ -void IWDG_ReloadCounter(void) -{ - IWDG->CTLR = CTLR_KEY_Reload; -} - -/********************************************************************* - * @fn IWDG_Enable - * - * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). - * - * @return none - */ -void IWDG_Enable(void) -{ - IWDG->CTLR = CTLR_KEY_Enable; -} - -/********************************************************************* - * @fn IWDG_GetFlagStatus - * - * @brief Checks whether the specified IWDG flag is set or not. - * - * @param IWDG_FLAG - specifies the flag to check. - * IWDG_FLAG_PVU - Prescaler Value Update on going. - * IWDG_FLAG_RVU - Reload Value Update on going. - * - * @return none - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_iwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the IWDG firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_iwdg.h" + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_misc.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_misc.c index bb5330b..a7a7568 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_misc.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_misc.c @@ -1,109 +1,81 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_misc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the miscellaneous firmware functions . -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_misc.h" - -__IO uint32_t NVIC_Priority_Group = 0; - -/********************************************************************* - * @fn NVIC_PriorityGroupConfig - * - * @brief Configures the priority grouping - pre-emption priority and subpriority. - * - * @param NVIC_PriorityGroup - specifies the priority grouping bits length. - * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority - * 4 bits for subpriority - * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority - * 3 bits for subpriority - * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority - * 2 bits for subpriority - * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority - * 1 bits for subpriority - * NVIC_PriorityGroup_4 - 4 bits for pre-emption priority - * 0 bits for subpriority - * - * @return none - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - NVIC_Priority_Group = NVIC_PriorityGroup; -} - -/********************************************************************* - * @fn NVIC_Init - * - * @brief Initializes the NVIC peripheral according to the specified parameters in - * the NVIC_InitStruct. - * - * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the - * configuration information for the specified NVIC peripheral. - * - * @return none - */ -void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) -{ - uint8_t tmppre = 0; - - if(NVIC_Priority_Group == NVIC_PriorityGroup_0) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); - } - else - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); - } - else - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) - { - if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3) - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); - } - else - { - tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4)); - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); - } - } - else if(NVIC_Priority_Group == NVIC_PriorityGroup_4) - { - NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4); - } - - if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } - else - { - NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); - } -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_misc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : This file provides all the miscellaneous firmware functions . +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_misc.h" + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 3 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 2 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); + } +#else + if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + } +#endif + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_opa.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_opa.c index 94a4f0d..499ab65 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_opa.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_opa.c @@ -1,319 +1,320 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_opa.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the OPA firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_opa.h" - - -/* FLASH Keys */ -#define OPA_KEY1 ((uint32_t)0x45670123) -#define OPA_KEY2 ((uint32_t)0xCDEF89AB) - -volatile uint32_t CTLR2_tmp = 0; - -/******************************************************************************** - * @fn OPA_Unlock - * - * @brief Unlocks the OPA Controller. - * - * @return None - */ -void OPA_Unlock(void) -{ - OPA->OPAKEY = OPA_KEY1; - OPA->OPAKEY = OPA_KEY2; -} - -/******************************************************************************** - * @fn OPA_Lock - * - * @brief Locks the OPA Controller. - * - * @return None - */ -void OPA_Lock(void) -{ - OPA->CTLR1 |= (1<<31); -} - -/******************************************************************************** - * @fn OPA_POLL_Unlock - * - * @brief Unlocks the OPA POLL Controller. - * - * @return None - */ -void OPA_POLL_Unlock(void) -{ - OPA->POLLKEY = OPA_KEY1; - OPA->POLLKEY = OPA_KEY2; -} - -/******************************************************************************** - * @fn OPA_POLL_Lock - * - * @brief Locks the OPA POLL Controller. - * - * @return None - */ -void OPA_POLL_Lock(void) -{ - OPA->CFGR1 |= (1<<7); -} - -/******************************************************************************** - * @fn OPA_CMP_Unlock - * - * @brief Unlocks the CMP Controller. - * - * @return None - */ -void OPA_CMP_Unlock(void) -{ - OPA->CMPKEY = OPA_KEY1; - OPA->CMPKEY = OPA_KEY2; -} - -/******************************************************************************** - * @fn OPA_CMP_Lock - * - * @brief Locks the CMP Controller. - * - * @return None - */ -void OPA_CMP_Lock(void) -{ - CTLR2_tmp |= (1<<31); - OPA->CTLR2 = CTLR2_tmp; - CTLR2_tmp &= ~(1<<31); -} - -/********************************************************************* - * @fn OPA_Init - * - * @brief Initializes the OPA peripheral according to the specified - * parameters in the OPA_InitStruct. - * - * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure - * - * @return none - */ -void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) -{ - uint16_t tmp0 = 0, tmp1 = 0; - uint32_t tmp2 = 0; - - tmp0 = OPA->CFGR1; - tmp1 = OPA->CFGR2; - tmp2 = OPA->CTLR1; - - if(OPA_InitStruct->OPA_NUM == OPA1) - { - tmp1 &= 0xFCFF; - tmp2 &= 0xFFFF0001; - - tmp1 |= (OPA_InitStruct->POLL_NUM << 9); - tmp2 |= (OPA_InitStruct->Mode << 1) | (OPA_InitStruct->PSEL << 3) - | (OPA_InitStruct->FB << 5) | (OPA_InitStruct->NSEL << 6); - } - else if(OPA_InitStruct->OPA_NUM == OPA2) - { - tmp1 &= 0xF3FF; - tmp2 &= 0x0001FFFF; - - tmp1 |= (OPA_InitStruct->POLL_NUM << 11); - tmp2 |= (OPA_InitStruct->Mode << 17) | (OPA_InitStruct->PSEL << 19) - | (OPA_InitStruct->FB << 21) | (OPA_InitStruct->NSEL << 22); - } - - tmp0 |= (OPA_InitStruct->PSEL_POLL) | (OPA_InitStruct->BKIN_EN << 2) - | (OPA_InitStruct->RST_EN << 4) | (OPA_InitStruct->BKIN_SEL << 6) - | (OPA_InitStruct->OUT_IE << 8) | (OPA_InitStruct->CNT_IE << 10) - | (OPA_InitStruct->NMI_IE << 11); - tmp1 |= OPA_InitStruct->OPA_POLL_Interval; - - OPA->CFGR1 = tmp0; - OPA->CFGR2 = tmp1; - OPA->CTLR1 = tmp2; -} - -/********************************************************************* - * @fn OPA_StructInit - * - * @brief Fills each OPA_StructInit member with its reset value. - * - * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure - * - * @return none - */ -void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) -{ - OPA_InitStruct->OPA_POLL_Interval = 0; - OPA_InitStruct->OPA_NUM = OPA1; - OPA_InitStruct->Mode = OUT_IO_OUT0; - OPA_InitStruct->PSEL = CHP0; - OPA_InitStruct->FB = FB_OFF; - OPA_InitStruct->NSEL = CHN0; - OPA_InitStruct->PSEL_POLL = CHP_OPA1_OFF_OPA2_OFF; - OPA_InitStruct->BKIN_EN = BKIN_OPA1_OFF_OPA2_OFF; - OPA_InitStruct->RST_EN = RST_OPA1_OFF_OPA2_OFF; - OPA_InitStruct->BKIN_SEL = BKIN_OPA1_TIM1_OPA2_TIM2; - OPA_InitStruct->OUT_IE = OUT_IE_OPA1_OFF_OPA2_OFF; - OPA_InitStruct->CNT_IE = CNT_IE_OFF; - OPA_InitStruct->NMI_IE = NMI_IE_OFF; - OPA_InitStruct->POLL_NUM = CHP_POLL_NUM_1; -} - -/********************************************************************* - * @fn OPA_Cmd - * - * @brief Enables or disables the specified OPA peripheral. - * - * @param OPA_NUM - Select OPA - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - OPA->CTLR1 |= (uint32_t)(1 << (OPA_NUM*16)); - } - else - { - OPA->CTLR1 &= ~(uint32_t)(1 << (OPA_NUM*16)); - } -} - -/********************************************************************* - * @fn OPA_CMP_Init - * - * @brief Initializes the CMP peripheral according to the specified - * parameters in the CMP_InitTypeDef. - * - * @param CMP_InitStruct - pointer to a CMP_InitTypeDef structure - * - * @return none - */ -void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct) -{ - uint32_t tmp1 = 0; - - tmp1 = CTLR2_tmp; - - if(CMP_InitStruct->CMP_NUM == CMP1) - { - tmp1 &= 0xFFFFFFE1; - tmp1 |= (CMP_InitStruct->Mode << 1) | (CMP_InitStruct->NSEL << 2) - | (CMP_InitStruct->PSEL << 3) | (CMP_InitStruct->HYEN << 4); - } - else if(CMP_InitStruct->CMP_NUM == CMP2) - { - tmp1 &= 0xFFFFFC3F; - tmp1 |= (CMP_InitStruct->Mode << 6) | (CMP_InitStruct->NSEL << 7) - | (CMP_InitStruct->PSEL << 8) | (CMP_InitStruct->HYEN << 9); - } - else if(CMP_InitStruct->CMP_NUM == CMP3) - { - tmp1 &= 0xFFFF87FF; - tmp1 |= (CMP_InitStruct->Mode << 11) | (CMP_InitStruct->NSEL << 12) - | (CMP_InitStruct->PSEL << 13) | (CMP_InitStruct->HYEN << 14); - } - - CTLR2_tmp = tmp1; - OPA->CTLR2 = tmp1; -} - -/********************************************************************* - * @fn OPA_CMP_StructInit - * - * @brief Fills each OPA_CMP_StructInit member with its reset value. - * - * @param CMP_StructInit - pointer to a OPA_CMP_StructInit structure - * - * @return none - */ -void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct) -{ - CMP_InitStruct->CMP_NUM = CMP1; - CMP_InitStruct->Mode = OUT_IO_TIM2_CH1; - CMP_InitStruct->NSEL = CMP_CHN0; - CMP_InitStruct->PSEL = CMP_CHP1; - CMP_InitStruct->HYEN = CMP_HYEN1; -} - -/********************************************************************* - * @fn OPA_CMP_Cmd - * - * @brief Enables or disables the specified CMP peripheral. - * - * @param CMP_NUM - Select CMP - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - CTLR2_tmp |= (uint32_t)(1 << (CMP_NUM*5)); - } - else - { - CTLR2_tmp &= ~(uint32_t)(1 << (CMP_NUM*5)); - } - - OPA->CTLR2 = CTLR2_tmp; -} - -/********************************************************************* - * @fn OPA_GetFlagStatus - * - * @brief Checks whether the OPA flag is set or not. - * - * @param OPA_FLAG - specifies the SPI/I2S flag to check. - * OPA_FLAG_OUT_OPA1 - OPA1 out flag - * OPA_FLAG_OUT_OPA2 - OPA2 out flag - * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus OPA_GetFlagStatus(uint16_t OPA_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((OPA->CFGR1 & OPA_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn OPA_ClearFlag - * - * @brief Clears the OPA flag. - * - * @param OPA_FLAG - specifies the OPA flag to clear. - * OPA_FLAG_OUT_OPA1 - OPA1 out flag - * OPA_FLAG_OUT_OPA2 - OPA2 out flag - * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data - * @return none - */ -void OPA_ClearFlag(uint16_t OPA_FLAG) -{ - OPA->CFGR1 &= (uint16_t)~OPA_FLAG; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_opa.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the OPA firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_opa.h" + + +/* FLASH Keys */ +#define OPA_KEY1 ((uint32_t)0x45670123) +#define OPA_KEY2 ((uint32_t)0xCDEF89AB) + +volatile uint32_t CTLR2_tmp = 0; + +/******************************************************************************** + * @fn OPA_Unlock + * + * @brief Unlocks the OPA Controller. + * + * @return None + */ +void OPA_Unlock(void) +{ + OPA->OPAKEY = OPA_KEY1; + OPA->OPAKEY = OPA_KEY2; +} + +/******************************************************************************** + * @fn OPA_Lock + * + * @brief Locks the OPA Controller. + * + * @return None + */ +void OPA_Lock(void) +{ + OPA->CTLR1 |= (1<<31); +} + +/******************************************************************************** + * @fn OPA_POLL_Unlock + * + * @brief Unlocks the OPA POLL Controller. + * + * @return None + */ +void OPA_POLL_Unlock(void) +{ + OPA->POLLKEY = OPA_KEY1; + OPA->POLLKEY = OPA_KEY2; +} + +/******************************************************************************** + * @fn OPA_POLL_Lock + * + * @brief Locks the OPA POLL Controller. + * + * @return None + */ +void OPA_POLL_Lock(void) +{ + OPA->CFGR1 |= (1<<7); +} + +/******************************************************************************** + * @fn OPA_CMP_Unlock + * + * @brief Unlocks the CMP Controller. + * + * @return None + */ +void OPA_CMP_Unlock(void) +{ + OPA->CMPKEY = OPA_KEY1; + OPA->CMPKEY = OPA_KEY2; +} + +/******************************************************************************** + * @fn OPA_CMP_Lock + * + * @brief Locks the CMP Controller. + * + * @return None + */ +void OPA_CMP_Lock(void) +{ + CTLR2_tmp |= (1<<31); + OPA->CTLR2 = CTLR2_tmp; + CTLR2_tmp &= ~(1<<31); +} + +/********************************************************************* + * @fn OPA_Init + * + * @brief Initializes the OPA peripheral according to the specified + * parameters in the OPA_InitStruct. + * + * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) +{ + uint16_t tmp0 = 0, tmp1 = 0; + uint32_t tmp2 = 0; + + tmp0 = OPA->CFGR1; + tmp1 = OPA->CFGR2; + tmp2 = OPA->CTLR1; + + if(OPA_InitStruct->OPA_NUM == OPA1) + { + tmp1 &= 0xFCFF; + tmp2 &= 0xFFFF0001; + + tmp1 |= (OPA_InitStruct->POLL_NUM << 9); + tmp2 |= (OPA_InitStruct->Mode << 1) | (OPA_InitStruct->PSEL << 3) + | (OPA_InitStruct->FB << 5) | (OPA_InitStruct->NSEL << 6); + } + else if(OPA_InitStruct->OPA_NUM == OPA2) + { + tmp1 &= 0xF3FF; + tmp2 &= 0x0001FFFF; + + tmp1 |= (OPA_InitStruct->POLL_NUM << 11); + tmp2 |= (OPA_InitStruct->Mode << 17) | (OPA_InitStruct->PSEL << 19) + | (OPA_InitStruct->FB << 21) | (OPA_InitStruct->NSEL << 22); + } + + tmp0 |= (OPA_InitStruct->PSEL_POLL) | (OPA_InitStruct->BKIN_EN << 2) + | (OPA_InitStruct->RST_EN << 4) | (OPA_InitStruct->BKIN_SEL << 6) + | (OPA_InitStruct->OUT_IE << 8) | (OPA_InitStruct->CNT_IE << 10) + | (OPA_InitStruct->NMI_IE << 11); + tmp1 &= 0xFF00; + tmp1 |= OPA_InitStruct->OPA_POLL_Interval; + + OPA->CFGR1 = tmp0; + OPA->CFGR2 = tmp1; + OPA->CTLR1 = tmp2; +} + +/********************************************************************* + * @fn OPA_StructInit + * + * @brief Fills each OPA_StructInit member with its reset value. + * + * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) +{ + OPA_InitStruct->OPA_POLL_Interval = 0; + OPA_InitStruct->OPA_NUM = OPA1; + OPA_InitStruct->Mode = OUT_IO_OUT0; + OPA_InitStruct->PSEL = CHP0; + OPA_InitStruct->FB = FB_OFF; + OPA_InitStruct->NSEL = CHN0; + OPA_InitStruct->PSEL_POLL = CHP_OPA1_OFF_OPA2_OFF; + OPA_InitStruct->BKIN_EN = BKIN_OPA1_OFF_OPA2_OFF; + OPA_InitStruct->RST_EN = RST_OPA1_OFF_OPA2_OFF; + OPA_InitStruct->BKIN_SEL = BKIN_OPA1_TIM1_OPA2_TIM2; + OPA_InitStruct->OUT_IE = OUT_IE_OPA1_OFF_OPA2_OFF; + OPA_InitStruct->CNT_IE = CNT_IE_OFF; + OPA_InitStruct->NMI_IE = NMI_IE_OFF; + OPA_InitStruct->POLL_NUM = CHP_POLL_NUM_1; +} + +/********************************************************************* + * @fn OPA_Cmd + * + * @brief Enables or disables the specified OPA peripheral. + * + * @param OPA_NUM - Select OPA + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CTLR1 |= (uint32_t)(1 << (OPA_NUM*16)); + } + else + { + OPA->CTLR1 &= ~(uint32_t)(1 << (OPA_NUM*16)); + } +} + +/********************************************************************* + * @fn OPA_CMP_Init + * + * @brief Initializes the CMP peripheral according to the specified + * parameters in the CMP_InitTypeDef. + * + * @param CMP_InitStruct - pointer to a CMP_InitTypeDef structure + * + * @return none + */ +void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct) +{ + uint32_t tmp1 = 0; + + tmp1 = CTLR2_tmp; + + if(CMP_InitStruct->CMP_NUM == CMP1) + { + tmp1 &= 0xFFFFFFE1; + tmp1 |= (CMP_InitStruct->Mode << 1) | (CMP_InitStruct->NSEL << 2) + | (CMP_InitStruct->PSEL << 3) | (CMP_InitStruct->HYEN << 4); + } + else if(CMP_InitStruct->CMP_NUM == CMP2) + { + tmp1 &= 0xFFFFFC3F; + tmp1 |= (CMP_InitStruct->Mode << 6) | (CMP_InitStruct->NSEL << 7) + | (CMP_InitStruct->PSEL << 8) | (CMP_InitStruct->HYEN << 9); + } + else if(CMP_InitStruct->CMP_NUM == CMP3) + { + tmp1 &= 0xFFFF87FF; + tmp1 |= (CMP_InitStruct->Mode << 11) | (CMP_InitStruct->NSEL << 12) + | (CMP_InitStruct->PSEL << 13) | (CMP_InitStruct->HYEN << 14); + } + + CTLR2_tmp = tmp1; + OPA->CTLR2 = tmp1; +} + +/********************************************************************* + * @fn OPA_CMP_StructInit + * + * @brief Fills each OPA_CMP_StructInit member with its reset value. + * + * @param CMP_StructInit - pointer to a OPA_CMP_StructInit structure + * + * @return none + */ +void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct) +{ + CMP_InitStruct->CMP_NUM = CMP1; + CMP_InitStruct->Mode = OUT_IO_TIM2; + CMP_InitStruct->NSEL = CMP_CHN0; + CMP_InitStruct->PSEL = CMP_CHP1; + CMP_InitStruct->HYEN = CMP_HYEN1; +} + +/********************************************************************* + * @fn OPA_CMP_Cmd + * + * @brief Enables or disables the specified CMP peripheral. + * + * @param CMP_NUM - Select CMP + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + CTLR2_tmp |= (uint32_t)(1 << (CMP_NUM*5)); + } + else + { + CTLR2_tmp &= ~(uint32_t)(1 << (CMP_NUM*5)); + } + + OPA->CTLR2 = CTLR2_tmp; +} + +/********************************************************************* + * @fn OPA_GetFlagStatus + * + * @brief Checks whether the OPA flag is set or not. + * + * @param OPA_FLAG - specifies the SPI/I2S flag to check. + * OPA_FLAG_OUT_OPA1 - OPA1 out flag + * OPA_FLAG_OUT_OPA2 - OPA2 out flag + * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus OPA_GetFlagStatus(uint16_t OPA_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((OPA->CFGR1 & OPA_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn OPA_ClearFlag + * + * @brief Clears the OPA flag. + * + * @param OPA_FLAG - specifies the OPA flag to clear. + * OPA_FLAG_OUT_OPA1 - OPA1 out flag + * OPA_FLAG_OUT_OPA2 - OPA2 out flag + * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data + * @return none + */ +void OPA_ClearFlag(uint16_t OPA_FLAG) +{ + OPA->CFGR1 &= (uint16_t)~OPA_FLAG; +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_pwr.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_pwr.c index 9c1295c..890e41f 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_pwr.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_pwr.c @@ -1,130 +1,156 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_pwr.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the PWR firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_pwr.h" -#include "ch32x035_rcc.h" - -/* PWR registers bit mask */ -/* CTLR register bit mask */ -#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) -#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF9F) - -/********************************************************************* - * @fn PWR_DeInit - * - * @brief Deinitializes the PWR peripheral registers to their default - * reset values. - * - * @return none - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/********************************************************************* - * @fn PWR_PVDLevelConfig - * - * @brief Configures the voltage threshold detected by the Power Voltage - * Detector(PVD). - * - * @param PWR_PVDLevel - specifies the PVD detection level - * PWR_PVDLevel_2V1 - PVD detection level set to 2.1V - * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V - * PWR_PVDLevel_3V0 - PVD detection level set to 3.0V - * PWR_PVDLevel_4V0 - PVD detection level set to 4.0V - * - * @return none - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_PLS_MASK; - tmpreg |= PWR_PVDLevel; - PWR->CTLR = tmpreg; -} - -/********************************************************************* - * @fn PWR_EnterSTOPMode - * - * @brief Enters STOP mode. - * - * @param PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. - * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction - * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction - * - * @return none - */ -void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - tmpreg = PWR->CTLR; - tmpreg &= CTLR_DS_MASK; - PWR->CTLR = tmpreg; - - NVIC->SCTLR |= (1 << 2); - - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - __WFI(); - } - else - { - __WFE(); - } - - NVIC->SCTLR &= ~(1 << 2); -} - -/********************************************************************* - * @fn PWR_EnterSTANDBYMode - * - * @brief Enters STANDBY mode. - * - * @return none - */ -void PWR_EnterSTANDBYMode(void) -{ - PWR->CTLR |= PWR_CTLR_PDDS; - NVIC->SCTLR |= (1 << 2); - - __WFI(); -} - -/********************************************************************* - * @fn PWR_GetFlagStatus - * - * @brief Checks whether the specified PWR flag is set or not. - * - * @param PWR_FLAG - specifies the flag to check. - * PWR_FLAG_PVDO - PVD Output - * PWR_FLAG_FLASH - Flash low power flag - * - * @return none - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_pwr.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/14 + * Description : This file provides all the PWR firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_pwr.h" +#include "ch32x035_rcc.h" + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF9F) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_0 - PVD detection level set to mode 0 + * PWR_PVDLevel_1 - PVD detection level set to mode 1 + * PWR_PVDLevel_2 - PVD detection level set to mode 2 + * PWR_PVDLevel_3 - PVD detection level set to mode 3 + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_EnterSTOPMode + * + * @brief Enters STOP mode. + * + * @param PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @return none + */ +void PWR_EnterSTANDBYMode(void) +{ + PWR->CTLR |= PWR_CTLR_PDDS; + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_PVDO - PVD Output + * PWR_FLAG_FLASH - Flash low power flag + * + * @return The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn PWR_VDD_SupplyVoltage + * + * @brief Checks VDD Supply Voltage. + * + * @param none + * + * @return PWR_VDD - VDD Supply Voltage. + * PWR_VDD_5V - VDD = 5V + * PWR_VDD_3V3 - VDD = 3.3V + */ +PWR_VDD PWR_VDD_SupplyVoltage(void) +{ + + PWR_VDD VDD_Voltage = PWR_VDD_3V3; + Delay_Init(); + RCC_APB1PeriphClockCmd( RCC_APB1Periph_PWR, ENABLE); + PWR_PVDLevelConfig(PWR_PVDLevel_3); + Delay_Us(10); + if( PWR_GetFlagStatus(PWR_FLAG_PVDO) == (uint32_t)RESET) + { + VDD_Voltage = PWR_VDD_5V; + } + PWR_PVDLevelConfig(PWR_PVDLevel_0); + + return VDD_Voltage; +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_rcc.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_rcc.c index 565d2a6..0813607 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_rcc.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_rcc.c @@ -1,411 +1,411 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_rcc.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the RCC firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_rcc.h" - -/* RCC registers bit mask */ - -/* CTLR register bit mask */ -#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -/* CFGR0 register bit mask */ -#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) - -/* RSTSCKR register bit mask */ -#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -/* CFGR0 register byte 4 (Bits[31:24]) base address */ -#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) - - -static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; - -/********************************************************************* - * @fn RCC_DeInit - * - * @brief Resets the RCC clock configuration to the default reset state. - * Note- - * HSE can not be stopped if it is used directly or through the PLL as system clock. - * @return none - */ -void RCC_DeInit(void) -{ - RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 |= (uint32_t)0x00000050; - RCC->CFGR0 &= (uint32_t)0xF8FFFF5F; -} - -/********************************************************************* - * @fn RCC_AdjustHSICalibrationValue - * - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * - * @param HSICalibrationValue - specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * - * @return none - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CTLR; - tmpreg &= CTLR_HSITRIM_Mask; - tmpreg |= (uint32_t)HSICalibrationValue << 3; - RCC->CTLR = tmpreg; -} - -/********************************************************************* - * @fn RCC_HSICmd - * - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_HSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<0); - } - else{ - RCC->CTLR &= ~(1<<0); - } -} - -/********************************************************************* - * @fn RCC_HCLKConfig - * - * @brief Configures the AHB clock (HCLK). - * - * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. - * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. - * RCC_SYSCLK_Div3 - AHB clock = SYSCLK/3. - * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. - * RCC_SYSCLK_Div5 - AHB clock = SYSCLK/5. - * RCC_SYSCLK_Div6 - AHB clock = SYSCLK/6. - * RCC_SYSCLK_Div7 - AHB clock = SYSCLK/7. - * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. - * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. - * RCC_SYSCLK_Div32 - AHB clock = SYSCLK/32. - * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. - * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. - * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. - * - * @return none - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_HPRE_Reset_Mask; - tmpreg |= RCC_SYSCLK; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_GetClocksFreq - * - * @brief The result of this function could be not correct when using - * fractional value for HSE crystal. - * - * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @return none - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, presc = 0; - - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - - tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - - if(((RCC->CFGR0 & CFGR0_HPRE_Set_Mask) >> 4) < 8) - { - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency / presc; - } - else - { - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - } - - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency; - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency; -} - -/********************************************************************* - * @fn RCC_AHBPeriphClockCmd - * - * @brief Enables or disables the AHB peripheral clock. - * - * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. - * RCC_AHBPeriph_DMA1. - * RCC_AHBPeriph_SRAM. - * RCC_AHBPeriph_USBFS. - * RCC_AHBPeriph_USBPD - * Note- - * SRAM clock can be disabled only during sleep mode. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->AHBPCENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBPCENR &= ~RCC_AHBPeriph; - } -} - -/********************************************************************* - * @fn RCC_APB2PeriphClockCmd - * - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * - * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. - * RCC_APB2Periph_AFIO. - * RCC_APB2Periph_GPIOA. - * RCC_APB2Periph_GPIOB. - * RCC_APB2Periph_GPIOC. - * RCC_APB2Periph_ADC1. - * RCC_APB2Periph_TIM1. - * RCC_APB2Periph_SPI1. - * RCC_APB2Periph_USART1. - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->APB2PCENR |= RCC_APB2Periph; - } - else - { - RCC->APB2PCENR &= ~RCC_APB2Periph; - } -} - -/********************************************************************* - * @fn RCC_APB1PeriphClockCmd - * - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * - * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. - * RCC_APB1Periph_TIM2. - * RCC_APB1Periph_TIM3. - * RCC_APB1Periph_WWDG. - * RCC_APB1Periph_USART2. - * RCC_APB1Periph_USART3. - * RCC_APB1Periph_USART4 - * RCC_APB1Periph_I2C1. - * RCC_APB1Periph_PWR. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->APB1PCENR |= RCC_APB1Periph; - } - else - { - RCC->APB1PCENR &= ~RCC_APB1Periph; - } -} - -/********************************************************************* - * @fn RCC_AHBPeriphResetCmd - * - * @brief Forces or releases AHB peripheral reset. - * - * @param RCC_AHBPeriph - specifies the AHB peripheral to reset. - * RCC_AHBPeriph_USBFS. - * RCC_AHBPeriph_IO2W. - * RCC_AHBPeriph_USBPD. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->AHBPCENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBPCENR &= ~RCC_AHBPeriph; - } -} - -/********************************************************************* - * @fn RCC_APB2PeriphResetCmd - * - * @brief Forces or releases APB (APB2) peripheral reset. - * - * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. - * RCC_APB2Periph_AFIO. - * RCC_APB2Periph_GPIOA. - * RCC_APB2Periph_GPIOB. - * RCC_APB2Periph_GPIOC. - * RCC_APB2Periph_ADC1. - * RCC_APB2Periph_TIM1. - * RCC_APB2Periph_SPI1. - * RCC_APB2Periph_USART1. - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->APB2PRSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2PRSTR &= ~RCC_APB2Periph; - } -} - -/********************************************************************* - * @fn RCC_APB1PeriphResetCmd - * - * @brief Forces or releases APB (APB1) peripheral reset. - * - * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. - * RCC_APB1Periph_TIM2. - * RCC_APB1Periph_TIM3. - * RCC_APB1Periph_WWDG. - * RCC_APB1Periph_USART2. - * RCC_APB1Periph_USART3. - * RCC_APB1Periph_USART4 - * RCC_APB1Periph_I2C1. - * RCC_APB1Periph_PWR. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->APB1PRSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1PRSTR &= ~RCC_APB1Periph; - } -} - -/********************************************************************* - * @fn RCC_MCOConfig - * - * @brief Selects the clock source to output on MCO pin. - * - * @param RCC_MCO - specifies the clock source to output. - * RCC_MCO_NoClock - No clock selected. - * RCC_MCO_SYSCLK - System clock selected. - * RCC_MCO_HSI - HSI oscillator clock selected. - * - * @return none - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO; -} - -/********************************************************************* - * @fn RCC_GetFlagStatus - * - * @brief Checks whether the specified RCC flag is set or not. - * - * @param RCC_FLAG - specifies the flag to check. - * RCC_FLAG_HSIRDY - HSI oscillator clock ready. - * RCC_FLAG_OPARST - OPA reset. - * RCC_FLAG_PINRST - Pin reset. - * RCC_FLAG_PORRST - POR/PDR reset. - * RCC_FLAG_SFTRST - Software reset. - * RCC_FLAG_IWDGRST - Independent Watchdog reset. - * RCC_FLAG_WWDGRST - Window Watchdog reset. - * RCC_FLAG_LPWRRST - Low Power reset. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - - FlagStatus bitstatus = RESET; - tmp = RCC_FLAG >> 5; - - if (tmp == 1) - { - statusreg = RCC->CTLR; - } - else - { - statusreg = RCC->RSTSCKR; - } - - tmp = RCC_FLAG & FLAG_Mask; - - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearFlag - * - * @brief Clears the RCC reset flags. - * Note- - * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @return none - */ -void RCC_ClearFlag(void) -{ - RCC->RSTSCKR |= RSTSCKR_RMVF_Set; -} - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_rcc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_rcc.h" + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR0 register bit mask */ +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + + +static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 |= (uint32_t)0x00000050; + RCC->CFGR0 &= (uint32_t)0xF8FFFF5F; +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<0); + } + else{ + RCC->CTLR &= ~(1<<0); + } +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the AHB clock (HCLK). + * + * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. + * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. + * RCC_SYSCLK_Div3 - AHB clock = SYSCLK/3. + * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. + * RCC_SYSCLK_Div5 - AHB clock = SYSCLK/5. + * RCC_SYSCLK_Div6 - AHB clock = SYSCLK/6. + * RCC_SYSCLK_Div7 - AHB clock = SYSCLK/7. + * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. + * RCC_SYSCLK_Div32 - AHB clock = SYSCLK/32. + * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, presc = 0; + + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + + if(((RCC->CFGR0 & CFGR0_HPRE_Set_Mask) >> 4) < 8) + { + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency / presc; + } + else + { + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + } + + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency; +} + +/********************************************************************* + * @fn RCC_AHBPeriphClockCmd + * + * @brief Enables or disables the AHB peripheral clock. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. + * RCC_AHBPeriph_DMA1. + * RCC_AHBPeriph_SRAM. + * RCC_AHBPeriph_USBFS. + * RCC_AHBPeriph_USBPD + * Note- + * SRAM clock can be disabled only during sleep mode. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->AHBPCENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCENR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphClockCmd + * + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->APB2PCENR |= RCC_APB2Periph; + } + else + { + RCC->APB2PCENR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_USART4 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_PWR. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->APB1PCENR |= RCC_APB1Periph; + } + else + { + RCC->APB1PCENR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_AHBPeriphResetCmd + * + * @brief Forces or releases AHB peripheral reset. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to reset. + * RCC_AHBPeriph_USBFS. + * RCC_AHBPeriph_IO2W. + * RCC_AHBPeriph_USBPD. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->AHBPCENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCENR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphResetCmd + * + * @brief Forces or releases APB (APB2) peripheral reset. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->APB2PRSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2PRSTR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphResetCmd + * + * @brief Forces or releases APB (APB1) peripheral reset. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_USART4 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_PWR. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->APB1PRSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1PRSTR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_OPARST - OPA reset. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if (tmp == 1) + { + statusreg = RCC->CTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * Note- + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + + + + diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_spi.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_spi.c index 7a79142..07a98b0 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_spi.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_spi.c @@ -1,506 +1,507 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_spi.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the SPI firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_spi.h" -#include "ch32x035_rcc.h" - -/* SPI SPE mask */ -#define CTLR1_SPE_Set ((uint16_t)0x0040) -#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) - -/* SPI CRCNext mask */ -#define CTLR1_CRCNext_Set ((uint16_t)0x1000) - -/* SPI CRCEN mask */ -#define CTLR1_CRCEN_Set ((uint16_t)0x2000) -#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) - -/* SPI SSOE mask */ -#define CTLR2_SSOE_Set ((uint16_t)0x0004) -#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) - -/* SPI registers Masks */ -#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) - -/********************************************************************* - * @fn SPI_I2S_DeInit - * - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values (Affects also the I2Ss). - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * - * @return none - */ -void SPI_I2S_DeInit(SPI_TypeDef *SPIx) -{ - if(SPIx == SPI1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } -} - -/********************************************************************* - * @fn SPI_Init - * - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * - * @return none - */ -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - tmpreg = SPIx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - - SPIx->CTLR1 = tmpreg; - SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/********************************************************************* - * @fn SPI_StructInit - * - * @brief Fills each SPI_InitStruct member with its default value. - * - * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which - * will be initialized. - * - * @return none - */ -void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) -{ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /*"SPI_FirstBit_LSB" not support SPI slave mode*/ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/********************************************************************* - * @fn SPI_Cmd - * - * @brief Enables or disables the specified SPI peripheral. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_SPE_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_SPE_Reset; - } -} - -/********************************************************************* - * @fn SPI_I2S_ITConfig - * - * @brief Enables or disables the specified SPI interrupts. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_IT - specifies the SPI interrupt source to be - * enabled or disabled. - * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. - * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. - * SPI_I2S_IT_ERR - Error interrupt mask. - * NewState: ENABLE or DISABLE. - * @return none - */ -void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0; - - itpos = SPI_I2S_IT >> 4; - itmask = (uint16_t)1 << (uint16_t)itpos; - - if(NewState != DISABLE) - { - SPIx->CTLR2 |= itmask; - } - else - { - SPIx->CTLR2 &= (uint16_t)~itmask; - } -} - -/********************************************************************* - * @fn SPI_I2S_DMACmd - * - * @brief Enables or disables the SPIxDMA interface. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_DMAReq - specifies the SPI DMA transfer request to - * be enabled or disabled. - * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. - * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= SPI_I2S_DMAReq; - } - else - { - SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/********************************************************************* - * @fn SPI_I2S_SendData - * - * @brief Transmits a Data through the SPIx peripheral. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * Data - Data to be transmitted. - * - * @return none - */ -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) -{ - SPIx->DATAR = Data; -} - -/********************************************************************* - * @fn SPI_I2S_ReceiveData - * - * @brief Returns the most recent received data by the SPIx peripheral. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * Data - Data to be transmitted. - * - * @return SPIx->DATAR - The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) -{ - return SPIx->DATAR; -} - -/********************************************************************* - * @fn SPI_NSSInternalSoftwareConfig - * - * @brief Configures internally by software the NSS pin for the selected SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_NSSInternalSoft - - * SPI_NSSInternalSoft_Set - Set NSS pin internally. - * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. - * - * @return none - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) -{ - if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; - } - else - { - SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/********************************************************************* - * @fn SPI_SSOutputCmd - * - * @brief Enables or disables the SS output for the selected SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * NewState - new state of the SPIx SS output. - * - * @return none - */ -void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR2 |= CTLR2_SSOE_Set; - } - else - { - SPIx->CTLR2 &= CTLR2_SSOE_Reset; - } -} - -/********************************************************************* - * @fn SPI_DataSizeConfig - * - * @brief Configures the data size for the selected SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_DataSize - specifies the SPI data size. - * SPI_DataSize_16b - Set data frame format to 16bit. - * SPI_DataSize_8b - Set data frame format to 8bit. - * - * @return none - */ -void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) -{ - SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; - SPIx->CTLR1 |= SPI_DataSize; -} - -/********************************************************************* - * @fn SPI_TransmitCRC - * - * @brief Transmit the SPIx CRC value. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * - * @return none - */ -void SPI_TransmitCRC(SPI_TypeDef *SPIx) -{ - SPIx->CTLR1 |= CTLR1_CRCNext_Set; -} - -/********************************************************************* - * @fn SPI_CalculateCRC - * - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * NewState - new state of the SPIx CRC value calculation. - * - * @return none - */ -void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - SPIx->CTLR1 |= CTLR1_CRCEN_Set; - } - else - { - SPIx->CTLR1 &= CTLR1_CRCEN_Reset; - } -} - -/********************************************************************* - * @fn SPI_GetCRC - * - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_CRC - specifies the CRC register to be read. - * SPI_CRC_Tx - Selects Tx CRC register. - * SPI_CRC_Rx - Selects Rx CRC register. - * - * @return crcreg: The selected CRC register value. - */ -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - - if(SPI_CRC != SPI_CRC_Rx) - { - crcreg = SPIx->TCRCR; - } - else - { - crcreg = SPIx->RCRCR; - } - - return crcreg; -} - -/********************************************************************* - * @fn SPI_GetCRCPolynomial - * - * @brief Returns the CRC Polynomial register value for the specified SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * - * @return SPIx->CRCR - The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) -{ - return SPIx->CRCR; -} - -/********************************************************************* - * @fn SPI_BiDirectionalLineConfig - * - * @brief Selects the data transfer direction in bi-directional mode - * for the specified SPI. - * - * @param SPIx - where x can be 1 to select the SPI peripheral. - * SPI_Direction - specifies the data transfer direction in - * bi-directional mode. - * SPI_Direction_Tx - Selects Tx transmission direction. - * SPI_Direction_Rx - Selects Rx receive direction. - * - * @return none - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) -{ - if(SPI_Direction == SPI_Direction_Tx) - { - SPIx->CTLR1 |= SPI_Direction_Tx; - } - else - { - SPIx->CTLR1 &= SPI_Direction_Rx; - } -} - -/********************************************************************* - * @fn SPI_I2S_GetFlagStatus - * - * @brief Checks whether the specified SPI/I2S flag is set or not. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. - * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. - * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. - * SPI_I2S_FLAG_BSY - Busy flag. - * SPI_I2S_FLAG_OVR - Overrun flag. - * SPI_FLAG_MODF - Mode Fault flag. - * SPI_FLAG_CRCERR - CRC Error flag. - * - * @return FlagStatus: SET or RESET. - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - - if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearFlag - * - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_FLAG - specifies the SPI flag to clear. - * SPI_FLAG_CRCERR - CRC Error flag. - * Note- - * - OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). - * - UDR (UnderRun error) flag is cleared by a read operation to - * SPI_STATR register (SPI_I2S_GetFlagStatus()). - * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). - * @return FlagStatus: SET or RESET. - */ -void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; -} - -/********************************************************************* - * @fn SPI_I2S_GetITStatus - * - * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_IT - specifies the SPI/I2S interrupt source to check.. - * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. - * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. - * SPI_I2S_IT_OVR - Overrun interrupt. - * SPI_IT_MODF - Mode Fault interrupt. - * SPI_IT_CRCERR - CRC Error interrupt. - * - * @return FlagStatus: SET or RESET. - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - itmask = SPI_I2S_IT >> 4; - itmask = 0x01 << itmask; - enablestatus = (SPIx->CTLR2 & itmask); - - if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn SPI_I2S_ClearITPendingBit - * - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * - * @param SPIx - where x can be - * - 1 in SPI mode. - * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. - * SPI_IT_CRCERR - CRC Error interrupt. - * Note- - * - OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). - * - UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_STATR register (SPI_I2S_GetITStatus()). - * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable - * the SPI). - * @return none - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - SPIx->STATR = (uint16_t)~itpos; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_spi.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/05 + * Description : This file provides all the SPI firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_spi.h" +#include "ch32x035_rcc.h" + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * When using SPI slave mode to send data, the CPOL bit should be set to 1. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /*"SPI_FirstBit_LSB" not support SPI slave mode*/ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI interrupts. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState: ENABLE or DISABLE. + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIxDMA interface. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_DMAReq - specifies the SPI DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg: The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI/I2S flag is set or not. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * Note- + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). + * @return FlagStatus: SET or RESET. + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * Note- + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable + * the SPI). + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_tim.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_tim.c index 9f6f1b1..3102d1b 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_tim.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_tim.c @@ -1,2457 +1,2457 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_tim.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the TIM firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_tim.h" -#include "ch32x035_rcc.h" - -/* TIM registers bit mask */ -#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) -#define CHCTLR_Offset ((uint16_t)0x0018) -#define CCER_CCE_Set ((uint16_t)0x0001) -#define CCER_CCNE_Set ((uint16_t)0x0004) -#define SPEC_OC12_Mask ((uint16_t)0xFFCE) -#define SPEC_OC34_Mask ((uint16_t)0xFF3D) - -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/********************************************************************* - * @fn TIM_DeInit - * - * @brief Deinitializes the TIMx peripheral registers to their default - * reset values. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * - * @return none - */ -void TIM_DeInit(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if(TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if(TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } -} - -/********************************************************************* - * @fn TIM_TimeBaseInit - * - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef - * structure. - * - * @return none - */ -void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - tmpcr1 = TIMx->CTLR1; - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - - TIMx->CTLR1 = tmpcr1; - TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; -} - -/********************************************************************* - * @fn TIM_OC1Init - * - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); - - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2Init - * - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR1; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR1 = tmpccmrx; - TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3Init - * - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4Init - * - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); - tmpccer = TIMx->CCER; - tmpcr2 = TIMx->CTLR2; - tmpccmrx = TIMx->CHCTLR2; - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1) || (TIMx == TIM2)) - { - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - - TIMx->CTLR2 = tmpcr2; - TIMx->CHCTLR2 = tmpccmrx; - TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ICInit - * - * @brief IInitializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_PWMIConfig - * - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external - * PWM signal. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - - if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - - if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/********************************************************************* - * @fn TIM_BDTRConfig - * - * @brief Configures the: Break feature, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable). - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/********************************************************************* - * @fn TIM_TimeBaseStructInit - * - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * - * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. - * - * @return none - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) -{ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/********************************************************************* - * @fn TIM_OCStructInit - * - * @brief Fills each TIM_OCInitStruct member with its default value. - * - * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. - * - * @return none - */ -void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) -{ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/********************************************************************* - * @fn TIM_ICStructInit - * - * @brief Fills each TIM_ICInitStruct member with its default value. - * - * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. - * - * @return none - */ -void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) -{ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/********************************************************************* - * @fn TIM_BDTRStructInit - * - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * - * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. - * - * @return none - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/********************************************************************* - * @fn TIM_Cmd - * - * @brief Enables or disables the specified TIM peripheral. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_CEN; - } - else - { - TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); - } -} - -/********************************************************************* - * @fn TIM_CtrlPWMOutputs - * - * @brief Enables or disables the TIM peripheral Main Outputs. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->BDTR |= TIM_MOE; - } - else - { - TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); - } -} - -/********************************************************************* - * @fn TIM_ITConfig - * - * @brief Enables or disables the specified TIM interrupts. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->DMAINTENR |= TIM_IT; - } - else - { - TIMx->DMAINTENR &= (uint16_t)~TIM_IT; - } -} - -/******************************************************************************* - * @fn TIM_GenerateEvent - * - * @brief Configures the TIMx event to be generate by software. - * - * @param TIMx: where x can be 1 to 3 to select the TIM peripheral. - * TIM_EventSource: specifies the event source. - * TIM_EventSource_Update: Timer update Event source. - * TIM_EventSource_CC1: Timer Capture Compare 1 Event source. - * TIM_EventSource_CC2: Timer Capture Compare 2 Event source. - * TIM_EventSource_CC3: Timer Capture Compare 3 Event source. - * TIM_EventSource_CC4: Timer Capture Compare 4 Event source. - * TIM_EventSource_COM: Timer COM event source. - * TIM_EventSource_Trigger: Timer Trigger Event source. - * TIM_EventSource_Break: Timer Break event source. - * - * @return None - */ -void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) -{ - TIMx->SWEVGR = TIM_EventSource; -} - -/********************************************************************* - * @fn TIM_DMAConfig - * - * @brief Configures the TIMx's DMA interface. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_DMABase: DMA Base address. - * TIM_DMABase_CR. - * TIM_DMABase_CR2. - * TIM_DMABase_SMCR. - * TIM_DMABase_DIER. - * TIM1_DMABase_SR. - * TIM_DMABase_EGR. - * TIM_DMABase_CCMR1. - * TIM_DMABase_CCMR2. - * TIM_DMABase_CCER. - * TIM_DMABase_CNT. - * TIM_DMABase_PSC. - * TIM_DMABase_CCR1. - * TIM_DMABase_CCR2. - * TIM_DMABase_CCR3. - * TIM_DMABase_CCR4. - * TIM_DMABase_BDTR. - * TIM_DMABase_DCR. - * TIM_DMABurstLength - DMA Burst length. - * TIM_DMABurstLength_1Transfer. - * TIM_DMABurstLength_18Transfers. - * - * @return none - */ -void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; -} - -/********************************************************************* - * @fn TIM_DMACmd - * - * @brief Enables or disables the TIMx's DMA Requests. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_DMASource - specifies the DMA Request sources. - * TIM_DMA_Update - TIM update Interrupt source. - * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. - * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. - * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. - * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. - * TIM_DMA_COM - TIM Commutation DMA source. - * TIM_DMA_Trigger - TIM Trigger DMA source. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->DMAINTENR |= TIM_DMASource; - } - else - { - TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; - } -} - -/********************************************************************* - * @fn TIM_InternalClockConfig - * - * @brief Configures the TIMx internal Clock. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * - * @return none - */ -void TIM_InternalClockConfig(TIM_TypeDef *TIMx) -{ - TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); -} - -/********************************************************************* - * @fn TIM_ITRxExternalClockConfig - * - * @brief Configures the TIMx Internal Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_InputTriggerSource: Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * - * @return none - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_TIxExternalClockConfig - * - * @brief Configures the TIMx Trigger as External Clock. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_TIxExternalCLKSource - Trigger source. - * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. - * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. - * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. - * TIM_ICPolarity - specifies the TIx Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_DMA_COM - TIM Commutation DMA source. - * TIM_DMA_Trigger - TIM Trigger DMA source. - * ICFilter - specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - TIMx->SMCFGR |= TIM_SlaveMode_External1; -} - -/********************************************************************* - * @fn TIM_ETRClockMode1Config - * - * @brief Configures the External clock Mode1. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_SlaveMode_External1; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_TS_ETRF; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_ETRClockMode2Config - * - * @brief Configures the External clock Mode2. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - TIMx->SMCFGR |= TIM_ECE; -} - -/********************************************************************* - * @fn TIM_ETRConfig - * - * @brief Configures the TIMx External Trigger (ETR). - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_ExtTRGPrescaler - The external Trigger Prescaler. - * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. - * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. - * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. - * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. - * TIM_ExtTRGPolarity - The external Trigger Polarity. - * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. - * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. - * ExtTRGFilter - External Trigger Filter. - * This parameter must be a value between 0x0 and 0xF. - * - * @return none - */ -void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= SMCFGR_ETR_Mask; - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_PrescalerConfig - * - * @brief Configures the TIMx Prescaler. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * Prescaler - specifies the Prescaler Register value. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. - * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. - * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. - * - * @return none - */ -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - TIMx->PSC = Prescaler; - TIMx->SWEVGR = TIM_PSCReloadMode; -} - -/********************************************************************* - * @fn TIM_CounterModeConfig - * - * @brief Specifies the TIMx Counter Mode to be used. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_CounterMode - specifies the Counter Mode to be used. - * TIM_CounterMode_Up - TIM Up Counting Mode. - * TIM_CounterMode_Down - TIM Down Counting Mode. - * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. - * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. - * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. - * - * @return none - */ -void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - tmpcr1 = TIMx->CTLR1; - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); - tmpcr1 |= TIM_CounterMode; - TIMx->CTLR1 = tmpcr1; -} - -/********************************************************************* - * @fn TIM_SelectInputTrigger - * - * @brief Selects the Input Trigger source. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_InputTriggerSource - The Input Trigger source. - * TIM_TS_ITR0 - Internal Trigger 0. - * TIM_TS_ITR1 - Internal Trigger 1. - * TIM_TS_ITR2 - Internal Trigger 2. - * TIM_TS_ITR3 - Internal Trigger 3. - * TIM_TS_TI1F_ED - TI1 Edge Detector. - * TIM_TS_TI1FP1 - Filtered Timer Input 1. - * TIM_TS_TI2FP2 - Filtered Timer Input 2. - * TIM_TS_ETRF - External Trigger input. - * - * @return none - */ -void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); - tmpsmcr |= TIM_InputTriggerSource; - TIMx->SMCFGR = tmpsmcr; -} - -/********************************************************************* - * @fn TIM_EncoderInterfaceConfig - * - * @brief Configures the TIMx Encoder Interface. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_EncoderMode - specifies the TIMx Encoder Mode. - * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending - * on TI2FP2 level. - * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending - * on TI1FP1 level. - * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and - * TI2FP2 edges depending. - * TIM_IC1Polarity - specifies the IC1 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TTIM_ICPolarity_Rising - IC Rising edge. - * TIM_IC2Polarity - specifies the IC2 Polarity. - * TIM_ICPolarity_Falling - IC Falling edge. - * TIM_ICPolarity_Rising - IC Rising edge. - * - * @return none - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - tmpsmcr = TIMx->SMCFGR; - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); - tmpsmcr |= TIM_EncoderMode; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); - tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; - tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - TIMx->SMCFGR = tmpsmcr; - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_ForcedOC1Config - * - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC1REF. - * TIM_ForcedAction_InActive - Force inactive level on OC1REF. - * - * @return none - */ -void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); - tmpccmr1 |= TIM_ForcedAction; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC2Config - * - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC2REF. - * TIM_ForcedAction_InActive - Force inactive level on OC2REF. - * - * @return none - */ -void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ForcedOC3Config - * - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC3REF. - * TIM_ForcedAction_InActive - Force inactive level on OC3REF. - * - * @return none - */ -void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); - tmpccmr2 |= TIM_ForcedAction; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ForcedOC4Config - * - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_ForcedAction - specifies the forced Action to be set to the - * output waveform. - * TIM_ForcedAction_Active - Force active level on OC4REF. - * TIM_ForcedAction_InActive - Force inactive level on OC4REF. - * - * @return none - */ -void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ARRPreloadConfig - * - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_ARPE; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); - } -} - -/********************************************************************* - * @fn TIM_SelectCOM - * - * @brief Selects the TIM peripheral Commutation event. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCUS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); - } -} - -/********************************************************************* - * @fn TIM_SelectCCDMA - * - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCDS; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); - } -} - -/********************************************************************* - * @fn TIM_CCPreloadControl - * - * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. - * reset values (Affects also the I2Ss). - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_CCPC; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); - } -} - -/********************************************************************* - * @fn TIM_OC1PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); - tmpccmr1 |= TIM_OCPreload; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC2PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC3PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); - tmpccmr2 |= TIM_OCPreload; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC4PreloadConfig - * - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCPreload - new state of the TIMx peripheral Preload register. - * TIM_OCPreload_Enable. - * TIM_OCPreload_Disable. - * - * @return none - */ -void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC1FastConfig - * - * @brief Configures the TIMx Output Compare 1 Fast feature. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); - tmpccmr1 |= TIM_OCFast; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC2FastConfig - * - * @brief Configures the TIMx Output Compare 2 Fast feature. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_OC3FastConfig - * - * @brief Configures the TIMx Output Compare 3 Fast feature. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); - tmpccmr2 |= TIM_OCFast; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC4FastConfig - * - * @brief Configures the TIMx Output Compare 4 Fast feature. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCFast - new state of the Output Compare Fast Enable Bit. - * TIM_OCFast_Enable - TIM output compare fast enable. - * TIM_OCFast_Disable - TIM output compare fast disable. - * - * @return none - */ -void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC1Ref - * - * @brief Clears or safeguards the OCREF1 signal on an external event. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); - tmpccmr1 |= TIM_OCClear; - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC2Ref - * - * @brief Clears or safeguards the OCREF2 signal on an external event. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - tmpccmr1 = TIMx->CHCTLR1; - tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR1 = tmpccmr1; -} - -/********************************************************************* - * @fn TIM_ClearOC3Ref - * - * @brief Clears or safeguards the OCREF3 signal on an external event. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); - tmpccmr2 |= TIM_OCClear; - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_ClearOC4Ref - * - * @brief Clears or safeguards the OCREF4 signal on an external event. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCClear - new state of the Output Compare Clear Enable Bit. - * TIM_OCClear_Enable - TIM Output clear enable. - * TIM_OCClear_Disable - TIM Output clear disable. - * - * @return none - */ -void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - tmpccmr2 = TIMx->CHCTLR2; - tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - TIMx->CHCTLR2 = tmpccmr2; -} - -/********************************************************************* - * @fn TIM_OC1PolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC1 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); - tmpccer |= TIM_OCPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC1NPolarityConfig - * - * @brief Configures the TIMx channel 1 polarity. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); - tmpccer |= TIM_OCNPolarity; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2PolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. - * TIM_OCPolarity - specifies the OC2 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC2NPolarityConfig - * - * @brief Configures the TIMx channel 2 polarity. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC1N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3PolarityConfig - * - * @brief Configures the TIMx Channel 3 polarity. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC3NPolarityConfig - * - * @brief Configures the TIMx Channel 3N polarity. - * - * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. - * TIM_OCNPolarity - specifies the OC2N Polarity. - * TIM_OCNPolarity_High - Output Compare active high. - * TIM_OCNPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_OC4PolarityConfig - * - * @brief Configures the TIMx Channel 4 polarity. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_OCPolarit - specifies the OC3 Polarity. - * TIM_OCPolarity_High - Output Compare active high. - * TIM_OCPolarity_Low - Output Compare active low. - * - * @return none - */ -void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - tmpccer = TIMx->CCER; - tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_CCxCmd - * - * @brief Enables or disables the TIM Capture Compare Channel x. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_CCx - specifies the TIM Channel CCxE bit new state. - * TIM_CCx_Enable. - * TIM_CCx_Disable. - * - * @return none - */ -void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - tmp = CCER_CCE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_CCxNCmd - * - * @brief Enables or disables the TIM Capture Compare Channel xN. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. - * TIM_CCxN_Enable. - * TIM_CCxN_Disable. - * - * @return none - */ -void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - tmp = CCER_CCNE_Set << TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp; - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/********************************************************************* - * @fn TIM_SelectOCxM - * - * @brief Selects the TIM Output Compare Mode. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_Channel - specifies the TIM Channel. - * TIM_Channel_1 - TIM Channel 1. - * TIM_Channel_2 - TIM Channel 2. - * TIM_Channel_3 - TIM Channel 3. - * TIM_Channel_4 - TIM Channel 4. - * TIM_OCMode - specifies the TIM Output Compare Mode. - * TIM_OCMode_Timing. - * TIM_OCMode_Active. - * TIM_OCMode_Toggle. - * TIM_OCMode_PWM1. - * TIM_OCMode_PWM2. - * TIM_ForcedAction_Active. - * TIM_ForcedAction_InActive. - * - * @return none - */ -void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - tmp = (uint32_t)TIMx; - tmp += CHCTLR_Offset; - tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; - TIMx->CCER &= (uint16_t)~tmp1; - - if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel >> 1); - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); - *(__IO uint32_t *)tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; - *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); - *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/********************************************************************* - * @fn TIM_UpdateDisableConfig - * - * @brief Enables or Disables the TIMx Update event. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR1 |= TIM_UDIS; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); - } -} - -/********************************************************************* - * @fn TIM_UpdateRequestConfig - * - * @brief Configures the TIMx Update Request Interrupt source. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_UpdateSource - specifies the Update source. - * TIM_UpdateSource_Regular. - * TIM_UpdateSource_Global. - * - * @return none - */ -void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) -{ - if(TIM_UpdateSource != TIM_UpdateSource_Global) - { - TIMx->CTLR1 |= TIM_URS; - } - else - { - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); - } -} - -/********************************************************************* - * @fn TIM_SelectHallSensor - * - * @brief Enables or disables the TIMx's Hall sensor interface. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - TIMx->CTLR2 |= TIM_TI1S; - } - else - { - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); - } -} - -/********************************************************************* - * @fn TIM_SelectOnePulseMode - * - * @brief Selects the TIMx's One Pulse Mode. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_OPMode - specifies the OPM Mode to be used. - * TIM_OPMode_Single. - * TIM_OPMode_Repetitive. - * - * @return none - */ -void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); - TIMx->CTLR1 |= TIM_OPMode; -} - -/********************************************************************* - * @fn TIM_SelectOutputTrigger - * - * @brief Selects the TIMx Trigger Output Mode. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_TRGOSource - specifies the Trigger Output source. - * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is - * used as the trigger output (TRGO). - * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the - * trigger output (TRGO). - * TIM_TRGOSource_Update - The update event is selected as the - * trigger output (TRGO). - * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse - * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). - * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). - * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). - * - * @return none - */ -void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) -{ - TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); - TIMx->CTLR2 |= TIM_TRGOSource; -} - -/********************************************************************* - * @fn TIM_SelectSlaveMode - * - * @brief Selects the TIMx Slave Mode. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_SlaveMode - specifies the Timer Slave Mode. - * TIM_SlaveMode_Reset - Rising edge of the selected trigger - * signal (TRGI) re-initializes. - * TIM_SlaveMode_Gated - The counter clock is enabled when the - * trigger signal (TRGI) is high. - * TIM_SlaveMode_Trigger - The counter starts at a rising edge - * of the trigger TRGI. - * TIM_SlaveMode_External1 - Rising edges of the selected trigger - * (TRGI) clock the counter. - * - * @return none - */ -void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) -{ - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); - TIMx->SMCFGR |= TIM_SlaveMode; -} - -/********************************************************************* - * @fn TIM_SelectMasterSlaveMode - * - * @brief Sets or Resets the TIMx Master/Slave Mode. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. - * TIM_MasterSlaveMode_Enable - synchronization between the current - * timer and its slaves (through TRGO). - * TIM_MasterSlaveMode_Disable - No action. - * - * @return none - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) -{ - TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); - TIMx->SMCFGR |= TIM_MasterSlaveMode; -} - -/********************************************************************* - * @fn TIM_SetCounter - * - * @brief Sets the TIMx Counter Register value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * Counter - specifies the Counter register new value. - * - * @return none - */ -void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) -{ - TIMx->CNT = Counter; -} - -/********************************************************************* - * @fn TIM_SetAutoreload - * - * @brief Sets the TIMx Autoreload Register value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * Autoreload - specifies the Autoreload register new value. - * - * @return none - */ -void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) -{ - TIMx->ATRLR = Autoreload; -} - -/********************************************************************* - * @fn TIM_SetCompare1 - * - * @brief Sets the TIMx Capture Compare1 Register value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) -{ - TIMx->CH1CVR = Compare1; -} - -/********************************************************************* - * @fn TIM_SetCompare2 - * - * @brief Sets the TIMx Capture Compare2 Register value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) -{ - TIMx->CH2CVR = Compare2; -} - -/********************************************************************* - * @fn TIM_SetCompare3 - * - * @brief Sets the TIMx Capture Compare3 Register value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) -{ - TIMx->CH3CVR = Compare3; -} - -/********************************************************************* - * @fn TIM_SetCompare4 - * - * @brief Sets the TIMx Capture Compare4 Register value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * Compare1 - specifies the Capture Compare1 register new value. - * - * @return none - */ -void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) -{ - TIMx->CH4CVR = Compare4; -} - -/********************************************************************* - * @fn TIM_SetIC1Prescaler - * - * @brief Sets the TIMx Input Capture 1 prescaler. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); - TIMx->CHCTLR1 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC2Prescaler - * - * @brief Sets the TIMx Input Capture 2 prescaler. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); - TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetIC3Prescaler - * - * @brief Sets the TIMx Input Capture 3 prescaler. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); - TIMx->CHCTLR2 |= TIM_ICPSC; -} - -/********************************************************************* - * @fn TIM_SetIC4Prescaler - * - * @brief Sets the TIMx Input Capture 4 prescaler. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_ICPSC - specifies the Input Capture1 prescaler new value. - * TIM_ICPSC_DIV1 - no prescaler. - * TIM_ICPSC_DIV2 - capture is done once every 2 events. - * TIM_ICPSC_DIV4 - capture is done once every 4 events. - * TIM_ICPSC_DIV8 - capture is done once every 8 events. - * - * @return none - */ -void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) -{ - TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); - TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/********************************************************************* - * @fn TIM_SetClockDivision - * - * @brief Sets the TIMx Clock Division value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_CKD - specifies the clock division value. - * TIM_CKD_DIV1 - TDTS = Tck_tim. - * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. - * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. - * - * @return none - */ -void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) -{ - TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); - TIMx->CTLR1 |= TIM_CKD; -} - -/********************************************************************* - * @fn TIM_GetCapture1 - * - * @brief Gets the TIMx Input Capture 1 value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * - * @return TIMx->CH1CVR - Capture Compare 1 Register value. - */ -uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) -{ - return TIMx->CH1CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture2 - * - * @brief Gets the TIMx Input Capture 2 value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * - * @return TIMx->CH2CVR - Capture Compare 2 Register value. - */ -uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) -{ - return TIMx->CH2CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture3 - * - * @brief Gets the TIMx Input Capture 3 value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * - * @return TIMx->CH3CVR - Capture Compare 3 Register value. - */ -uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) -{ - return TIMx->CH3CVR; -} - -/********************************************************************* - * @fn TIM_GetCapture4 - * - * @brief Gets the TIMx Input Capture 4 value. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * - * @return TIMx->CH4CVR - Capture Compare 4 Register value. - */ -uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) -{ - return TIMx->CH4CVR; -} - -/********************************************************************* - * @fn TIM_GetCounter - * - * @brief Gets the TIMx Counter value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * - * @return TIMx->CNT - Counter Register value. - */ -uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) -{ - return TIMx->CNT; -} - -/********************************************************************* - * @fn TIM_GetPrescaler - * - * @brief Gets the TIMx Prescaler value. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * - * @return TIMx->PSC - Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) -{ - return TIMx->PSC; -} - -/********************************************************************* - * @fn TIM_GetFlagStatus - * - * @brief Checks whether the specified TIM flag is set or not. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return none - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - - if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearFlag - * - * @brief Clears the TIMx's pending flags. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_FLAG - specifies the flag to check. - * TIM_FLAG_Update - TIM update Flag. - * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. - * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. - * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. - * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. - * TIM_FLAG_COM - TIM Commutation Flag. - * TIM_FLAG_Trigger - TIM Trigger Flag. - * TIM_FLAG_Break - TIM Break Flag. - * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. - * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. - * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. - * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. - * - * @return none - */ -void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) -{ - TIMx->INTFR = (uint16_t)~TIM_FLAG; -} - -/********************************************************************* - * @fn TIM_GetITStatus - * - * @brief Checks whether the TIM interrupt has occurred or not. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - - itstatus = TIMx->INTFR & TIM_IT; - - itenable = TIMx->DMAINTENR & TIM_IT; - if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn TIM_ClearITPendingBit - * - * @brief Clears the TIMx's interrupt pending bits. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_IT - specifies the TIM interrupt source to check. - * TIM_IT_Update - TIM update Interrupt source. - * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. - * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. - * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. - * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. - * TIM_IT_COM - TIM Commutation Interrupt source. - * TIM_IT_Trigger - TIM Trigger Interrupt source. - * TIM_IT_Break - TIM Break Interrupt source. - * - * @return none - */ -void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) -{ - TIMx->INTFR = (uint16_t)~TIM_IT; -} - -/********************************************************************* - * @fn TI1_Config - * - * @brief Configure the TI1 as Input. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI2_Config - * - * @brief Configure the TI2 as Input. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); - tmpccmr1 = TIMx->CHCTLR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); - } - - TIMx->CHCTLR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI3_Config - * - * @brief Configure the TI3 as Input. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TI4_Config - * - * @brief Configure the TI4 as Input. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * IM_ICPolarity - The Input Polarity. - * TIM_ICPolarity_Rising. - * TIM_ICPolarity_Falling. - * TIM_ICSelection - specifies the input to be used. - * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be - * connected to IC1. - * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be - * connected to IC2. - * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected - * to TRC. - * TIM_ICFilter - Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * - * @return none - */ -static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); - tmpccmr2 = TIMx->CHCTLR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); - } - else - { - tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC4NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); - } - - TIMx->CHCTLR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/********************************************************************* - * @fn TIM_CaptureModeCmd - * - * @brief Enables or disables the TIM capture over mode. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_CaptureModeCmd(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState) - { - TIMx->CTLR1 |= (1<<14); - } - else{ - TIMx->CTLR1 &= ~(1<<14); - } -} - -/********************************************************************* - * @fn TIM_IndicateCaptureLevelCmd - * - * @brief Enables or disables the TIMx capture level indication. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState) -{ - if(NewState) - { - TIMx->CTLR1 |= (1<<15); - } - else{ - TIMx->CTLR1 &= ~(1<<15); - } -} - -/********************************************************************* - * @fn TIM_OC12_SupersedeModeCmd - * - * @brief Enables or disables the TIMx Channel (1 and 2) supersede mode. - * - * @param TIMx - where x can be 1 to 3 select the TIM peripheral. - * TIM_Supersede_Mode_OC1 - Channel 1 Supersede Mode invalid level. - * TIM_Supersede_Mode_OC1_H - Invalid level is high level. - * TIM_Supersede_Mode_OC1_L - Invalid level is low level. - * TIM_Supersede_Mode_OC2 - Channel 2 Supersede Mode invalid level. - * TIM_Supersede_Mode_OC2_H - Invalid level is high level. - * TIM_Supersede_Mode_OC2_L - Invalid level is low level. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_OC12_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC1, uint16_t TIM_Supersede_Mode_OC2, - FunctionalState NewState) -{ - uint32_t tmpreg = 0; - - tmpreg = TIMx->SPEC; - - tmpreg &= SPEC_OC12_Mask; - tmpreg |= TIM_Supersede_Mode_OC1 | TIM_Supersede_Mode_OC2; - - - if(NewState) - { - tmpreg |= (1<<0); - } - - TIMx->SPEC = tmpreg; -} - -/********************************************************************* - * @fn TIM_OC34_SupersedeModeCmd - * - * @brief Enables or disables the TIMx Channel (3 and 4) supersede mode. - * - * @param TIMx - where x can be 1 to 2 select the TIM peripheral. - * TIM_Supersede_Mode_OC3 - Channel 3 Supersede Mode invalid level. - * TIM_Supersede_Mode_OC3_H - Invalid level is high level. - * TIM_Supersede_Mode_OC3_L - Invalid level is low level. - * TIM_Supersede_Mode_OC4 - Channel 4 Supersede Mode invalid level. - * TIM_Supersede_Mode_OC4_H - Invalid level is high level. - * TIM_Supersede_Mode_OC4_L - Invalid level is low level. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void TIM_OC34_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC3, uint16_t TIM_Supersede_Mode_OC4, - FunctionalState NewState) -{ - uint32_t tmpreg = 0; - - tmpreg = TIMx->SPEC; - - tmpreg &= SPEC_OC34_Mask; - tmpreg |= TIM_Supersede_Mode_OC3 | TIM_Supersede_Mode_OC4; - - - if(NewState) - { - tmpreg |= (1<<1); - } - - TIMx->SPEC = tmpreg; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_tim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : This file provides all the TIM firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_tim.h" +#include "ch32x035_rcc.h" + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) +#define SPEC_OC12_Mask ((uint16_t)0xFFCE) +#define SPEC_OC34_Mask ((uint16_t)0xFF3D) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if(TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + + TIMx->CTLR1 = tmpcr1; + TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +/******************************************************************************* + * @fn TIM_GenerateEvent + * + * @brief Configures the TIMx event to be generate by software. + * + * @param TIMx: where x can be 1 to 3 to select the TIM peripheral. + * TIM_EventSource: specifies the event source. + * TIM_EventSource_Update: Timer update Event source. + * TIM_EventSource_CC1: Timer Capture Compare 1 Event source. + * TIM_EventSource_CC2: Timer Capture Compare 2 Event source. + * TIM_EventSource_CC3: Timer Capture Compare 3 Event source. + * TIM_EventSource_CC4: Timer Capture Compare 4 Event source. + * TIM_EventSource_COM: Timer COM event source. + * TIM_EventSource_Trigger: Timer Trigger Event source. + * TIM_EventSource_Break: Timer Break event source. + * + * @return None + */ +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_DMABase: DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values (Affects also the I2Ss). + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 4 polarity. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) +{ + TIMx->CNT = Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) +{ + TIMx->ATRLR = Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) +{ + TIMx->CH1CVR = Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) +{ + TIMx->CH2CVR = Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) +{ + TIMx->CH3CVR = Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) +{ + TIMx->CH4CVR = Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture3 + * + * @brief Gets the TIMx Input Capture 3 value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CH3CVR - Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CaptureModeCmd + * + * @brief Enables or disables the TIM capture over mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CaptureModeCmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState) + { + TIMx->CTLR1 |= (1<<14); + } + else{ + TIMx->CTLR1 &= ~(1<<14); + } +} + +/********************************************************************* + * @fn TIM_IndicateCaptureLevelCmd + * + * @brief Enables or disables the TIMx capture level indication. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState) + { + TIMx->CTLR1 |= (1<<15); + } + else{ + TIMx->CTLR1 &= ~(1<<15); + } +} + +/********************************************************************* + * @fn TIM_OC12_SupersedeModeCmd + * + * @brief Enables or disables the TIMx Channel (1 and 2) supersede mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_Supersede_Mode_OC1 - Channel 1 Supersede Mode invalid level. + * TIM_Supersede_Mode_OC1_H - Invalid level is high level. + * TIM_Supersede_Mode_OC1_L - Invalid level is low level. + * TIM_Supersede_Mode_OC2 - Channel 2 Supersede Mode invalid level. + * TIM_Supersede_Mode_OC2_H - Invalid level is high level. + * TIM_Supersede_Mode_OC2_L - Invalid level is low level. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_OC12_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC1, uint16_t TIM_Supersede_Mode_OC2, + FunctionalState NewState) +{ + uint32_t tmpreg = 0; + + tmpreg = TIMx->SPEC; + + tmpreg &= SPEC_OC12_Mask; + tmpreg |= TIM_Supersede_Mode_OC1 | TIM_Supersede_Mode_OC2; + + + if(NewState) + { + tmpreg |= (1<<0); + } + + TIMx->SPEC = tmpreg; +} + +/********************************************************************* + * @fn TIM_OC34_SupersedeModeCmd + * + * @brief Enables or disables the TIMx Channel (3 and 4) supersede mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_Supersede_Mode_OC3 - Channel 3 Supersede Mode invalid level. + * TIM_Supersede_Mode_OC3_H - Invalid level is high level. + * TIM_Supersede_Mode_OC3_L - Invalid level is low level. + * TIM_Supersede_Mode_OC4 - Channel 4 Supersede Mode invalid level. + * TIM_Supersede_Mode_OC4_H - Invalid level is high level. + * TIM_Supersede_Mode_OC4_L - Invalid level is low level. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_OC34_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC3, uint16_t TIM_Supersede_Mode_OC4, + FunctionalState NewState) +{ + uint32_t tmpreg = 0; + + tmpreg = TIMx->SPEC; + + tmpreg &= SPEC_OC34_Mask; + tmpreg |= TIM_Supersede_Mode_OC3 | TIM_Supersede_Mode_OC4; + + + if(NewState) + { + tmpreg |= (1<<1); + } + + TIMx->SPEC = tmpreg; +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_usart.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_usart.c index bc0593f..3855497 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_usart.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_usart.c @@ -1,743 +1,743 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_usart.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the USART firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_usart.h" -#include "ch32x035_rcc.h" - -/* USART_Private_Defines */ -#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ -#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ - -#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ - -#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ -#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ -#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ -#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ - -#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ -#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ - -#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ -#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ -#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ - -#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ -#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ - -#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ -#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ - -#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ -#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ - -#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ -#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ - -#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ -#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ -#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ -#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ -#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ - -/********************************************************************* - * @fn USART_DeInit - * - * @brief Deinitializes the USARTx peripheral registers to their default - * reset values. - * - * @param USARTx - where x can be 1, 2 , 3 or 4 to select the UART peripheral. - * - * @return none - */ -void USART_DeInit(USART_TypeDef *USARTx) -{ - if(USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if(USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if(USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if(USARTx == USART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, DISABLE); - } -} - -/********************************************************************* - * @fn USART_Init - * - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct. - * - * @param USARTx - where x can be 1, 2 , 3 or 4 to select the UART peripheral. - * USART_InitStruct - pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified - * USART peripheral. - * - * @return none - */ -void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - uint32_t usartxbase = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - - if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - } - - usartxbase = (uint32_t)USARTx; - tmpreg = USARTx->CTLR2; - tmpreg &= CTLR2_STOP_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - USARTx->CTLR2 = (uint16_t)tmpreg; - tmpreg = USARTx->CTLR1; - tmpreg &= CTLR1_CLEAR_Mask; - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - USARTx->CTLR1 = (uint16_t)tmpreg; - - tmpreg = USARTx->CTLR3; - tmpreg &= CTLR3_CLEAR_Mask; - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - USARTx->CTLR3 = (uint16_t)tmpreg; - - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if(usartxbase == USART1_BASE) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - tmpreg = (integerdivider / 100) << 4; - - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - - USARTx->BRR = (uint16_t)tmpreg; -} - -/********************************************************************* - * @fn USART_StructInit - * - * @brief Fills each USART_InitStruct member with its default value. - * - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void USART_StructInit(USART_InitTypeDef *USART_InitStruct) -{ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/********************************************************************* - * @fn USART_ClockInit - * - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * - * @return none - */ -void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - - tmpreg = USARTx->CTLR2; - tmpreg &= CTLR2_CLOCK_CLEAR_Mask; - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - USARTx->CTLR2 = (uint16_t)tmpreg; -} - -/********************************************************************* - * @fn USART_ClockStructInit - * - * @brief Fills each USART_ClockStructInit member with its default value. - * - * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * - * @return none - */ -void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/********************************************************************* - * @fn USART_Cmd - * - * @brief Enables or disables the specified USART peripheral. - * reset values (Affects also the I2Ss). - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_UE_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_UE_Reset; - } -} - -/********************************************************************* - * @fn USART_ITConfig - * - * @brief Enables or disables the specified USART interrupts. - * reset values (Affects also the I2Ss). - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_IT - specifies the USART interrupt sources to be enabled or disabled. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Transmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_PE - Parity Error interrupt. - * USART_IT_ERR - Error interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - - - usartxbase = (uint32_t)USARTx; - usartreg = (((uint8_t)USART_IT) >> 0x05); - itpos = USART_IT & IT_Mask; - itmask = (((uint32_t)0x01) << itpos); - - if(usartreg == 0x01) - { - usartxbase += 0x0C; - } - else if(usartreg == 0x02) - { - usartxbase += 0x10; - } - else - { - usartxbase += 0x14; - } - - if(NewState != DISABLE) - { - *(__IO uint32_t *)usartxbase |= itmask; - } - else - { - *(__IO uint32_t *)usartxbase &= ~itmask; - } -} - -/********************************************************************* - * @fn USART_DMACmd - * - * @brief Enables or disables the USART DMA interface. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_DMAReq - specifies the DMA request. - * USART_DMAReq_Tx - USART DMA transmit request. - * USART_DMAReq_Rx - USART DMA receive request. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= USART_DMAReq; - } - else - { - USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; - } -} - -/********************************************************************* - * @fn USART_SetAddress - * - * @brief Sets the address of the USART node. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_Address - Indicates the address of the USART node. - * - * @return none - */ -void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) -{ - USARTx->CTLR2 &= CTLR2_Address_Mask; - USARTx->CTLR2 |= USART_Address; -} - -/********************************************************************* - * @fn USART_WakeUpConfig - * - * @brief Selects the USART WakeUp method. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_WakeUp - specifies the USART wakeup method. - * USART_WakeUp_IdleLine - WakeUp by an idle line detection. - * USART_WakeUp_AddressMark - WakeUp by an address mark. - * - * @return none - */ -void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) -{ - USARTx->CTLR1 &= CTLR1_WAKE_Mask; - USARTx->CTLR1 |= USART_WakeUp; -} - -/********************************************************************* - * @fn USART_ReceiverWakeUpCmd - * - * @brief Determines if the USART is in mute mode or not. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR1 |= CTLR1_RWU_Set; - } - else - { - USARTx->CTLR1 &= CTLR1_RWU_Reset; - } -} - -/********************************************************************* - * @fn USART_LINBreakDetectLengthConfig - * - * @brief Sets the USART LIN Break detection length. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_LINBreakDetectLength - specifies the LIN break detection length. - * USART_LINBreakDetectLength_10b - 10-bit break detection. - * USART_LINBreakDetectLength_11b - 11-bit break detection. - * - * @return none - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) -{ - USARTx->CTLR2 &= CTLR2_LBDL_Mask; - USARTx->CTLR2 |= USART_LINBreakDetectLength; -} - -/********************************************************************* - * @fn USART_LINCmd - * - * @brief Enables or disables the USART LIN mode. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR2 |= CTLR2_LINEN_Set; - } - else - { - USARTx->CTLR2 &= CTLR2_LINEN_Reset; - } -} - -/********************************************************************* - * @fn USART_SendData - * - * @brief Transmits single data through the USARTx peripheral. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * Data - the data to transmit. - * - * @return none - */ -void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) -{ - USARTx->DATAR = (Data & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_ReceiveData - * - * @brief Returns the most recent received data by the USARTx peripheral. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * - * @return The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef *USARTx) -{ - return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); -} - -/********************************************************************* - * @fn USART_SendBreak - * - * @brief Transmits break characters. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * - * @return none - */ -void USART_SendBreak(USART_TypeDef *USARTx) -{ - USARTx->CTLR1 |= CTLR1_SBK_Set; -} - -/********************************************************************* - * @fn USART_SetGuardTime - * - * @brief Sets the specified USART guard time. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_GuardTime - specifies the guard time. - * - * @return none - */ -void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) -{ - USARTx->GPR &= GPR_LSB_Mask; - USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/********************************************************************* - * @fn USART_SetPrescaler - * - * @brief Sets the system clock prescaler. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_Prescaler - specifies the prescaler clock. - * - * @return none - */ -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) -{ - USARTx->GPR &= GPR_MSB_Mask; - USARTx->GPR |= USART_Prescaler; -} - -/********************************************************************* - * @fn USART_SmartCardCmd - * - * @brief Enables or disables the USART Smart Card mode. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_SCEN_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_SCEN_Reset; - } -} - -/********************************************************************* - * @fn USART_SmartCardNACKCmd - * - * @brief Enables or disables NACK transmission. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_NACK_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_NACK_Reset; - } -} - -/********************************************************************* - * @fn USART_HalfDuplexCmd - * - * @brief Enables or disables the USART Half Duplex communication. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_HDSEL_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_HDSEL_Reset; - } -} - -/********************************************************************* - * @fn USART_IrDAConfig - * - * @brief Configures the USART's IrDA interface. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_IrDAMode - specifies the IrDA mode. - * USART_IrDAMode_LowPower. - * USART_IrDAMode_Normal. - * - * @return none - */ -void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) -{ - USARTx->CTLR3 &= CTLR3_IRLP_Mask; - USARTx->CTLR3 |= USART_IrDAMode; -} - -/********************************************************************* - * @fn USART_IrDACmd - * - * @brief Enables or disables the USART's IrDA interface. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - USARTx->CTLR3 |= CTLR3_IREN_Set; - } - else - { - USARTx->CTLR3 &= CTLR3_IREN_Reset; - } -} - -/********************************************************************* - * @fn USART_GetFlagStatus - * - * @brief Checks whether the specified USART flag is set or not. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_FLAG - specifies the flag to check. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TXE - Transmit data register empty flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * USART_FLAG_IDLE - Idle Line detection flag. - * USART_FLAG_ORE - OverRun Error flag. - * USART_FLAG_NE - Noise Error flag. - * USART_FLAG_FE - Framing Error flag. - * USART_FLAG_PE - Parity Error flag. - * - * @return bitstatus: SET or RESET - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - - - if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearFlag - * - * @brief Clears the USARTx's pending flags. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_FLAG - specifies the flag to clear. - * USART_FLAG_LBD - LIN Break detection flag. - * USART_FLAG_TC - Transmission Complete flag. - * USART_FLAG_RXNE - Receive data register not empty flag. - * Note- - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DATAR register (USART_ReceiveData()). - * - RXNE flag can be also cleared by a read to the USART_DATAR register - * (USART_ReceiveData()). - * - TC flag can be also cleared by software sequence: a read operation to - * USART_STATR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DATAR register (USART_SendData()). - * - TXE flag is cleared only by a write to the USART_DATAR register - * (USART_SendData()). - * @return none - */ -void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - - USARTx->STATR = (uint16_t)~USART_FLAG; -} - -/********************************************************************* - * @fn USART_GetITStatus - * - * @brief Checks whether the specified USART interrupt has occurred or not. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_IT - specifies the USART interrupt source to check. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TXE - Tansmit Data Register empty interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * USART_IT_IDLE - Idle line detection interrupt. - * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. - * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. - * USART_IT_NE - Noise Error interrupt. - * USART_IT_FE - Framing Error interrupt. - * USART_IT_PE - Parity Error interrupt. - * - * @return bitstatus: SET or RESET. - */ -ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - - usartreg = (((uint8_t)USART_IT) >> 0x05); - itmask = USART_IT & IT_Mask; - itmask = (uint32_t)0x01 << itmask; - - if(usartreg == 0x01) - { - itmask &= USARTx->CTLR1; - } - else if(usartreg == 0x02) - { - itmask &= USARTx->CTLR2; - } - else - { - itmask &= USARTx->CTLR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->STATR; - - if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn USART_ClearITPendingBit - * - * @brief Clears the USARTx's interrupt pending bits. - * - * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. - * USART_IT - specifies the interrupt pending bit to clear. - * USART_IT_LBD - LIN Break detection interrupt. - * USART_IT_TC - Transmission complete interrupt. - * USART_IT_RXNE - Receive Data register not empty interrupt. - * Note- - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_STATR register - * (USART_GetITStatus()) followed by a read operation to USART_DATAR register - * (USART_ReceiveData()). - * - RXNE pending bit can be also cleared by a read to the USART_DATAR register - * (USART_ReceiveData()). - * - TC pending bit can be also cleared by software sequence: a read - * operation to USART_STATR register (USART_GetITStatus()) followed by a write - * operation to USART_DATAR register (USART_SendData()). - * - TXE pending bit is cleared only by a write to the USART_DATAR register - * (USART_SendData()). - * @return none - */ -void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->STATR = (uint16_t)~itmask; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_usart.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the USART firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_usart.h" +#include "ch32x035_rcc.h" + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1, 2 , 3 or 4 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if(USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if(USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if(USARTx == USART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, DISABLE); + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1, 2 , 3 or 4 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + tmpreg = (integerdivider / 100) << 4; + + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return bitstatus: SET or RESET + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DATAR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_STATR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DATAR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return bitstatus: SET or RESET. + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_STATR register + * (USART_GetITStatus()) followed by a read operation to USART_DATAR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_STATR register (USART_GetITStatus()) followed by a write + * operation to USART_DATAR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/system/CH32X035/SRC/Peripheral/src/ch32x035_wwdg.c b/system/CH32X035/SRC/Peripheral/src/ch32x035_wwdg.c index 2d80561..704a627 100644 --- a/system/CH32X035/SRC/Peripheral/src/ch32x035_wwdg.c +++ b/system/CH32X035/SRC/Peripheral/src/ch32x035_wwdg.c @@ -1,141 +1,141 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_wwdg.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : This file provides all the WWDG firmware functions. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_wwdg.h" -#include "ch32x035_rcc.h" - -/* CTLR register bit mask */ -#define CTLR_WDGA_Set ((uint32_t)0x00000080) - -/* CFGR register bit mask */ -#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) -#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) -#define BIT_Mask ((uint8_t)0x7F) - -/********************************************************************* - * @fn WWDG_DeInit - * - * @brief Deinitializes the WWDG peripheral registers to their default reset values - * - * @return none - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/********************************************************************* - * @fn WWDG_SetPrescaler - * - * @brief Sets the WWDG Prescaler - * - * @param WWDG_Prescaler - specifies the WWDG Prescaler - * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 - * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 - * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 - * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 - * - * @return none - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; - tmpreg |= WWDG_Prescaler; - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_SetWindowValue - * - * @brief Sets the WWDG window value - * - * @param WindowValue - specifies the window value to be compared to the - * downcounter,which must be lower than 0x80 - * - * @return none - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - tmpreg = WWDG->CFGR & CFGR_W_Mask; - - tmpreg |= WindowValue & (uint32_t)BIT_Mask; - - WWDG->CFGR = tmpreg; -} - -/********************************************************************* - * @fn WWDG_EnableIT - * - * @brief Enables the WWDG Early Wakeup interrupt(EWI) - * - * @return none - */ -void WWDG_EnableIT(void) -{ - WWDG->CFGR |= (1 << 9); -} - -/********************************************************************* - * @fn WWDG_SetCounter - * - * @brief Sets the WWDG counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * - * @return none - */ -void WWDG_SetCounter(uint8_t Counter) -{ - WWDG->CTLR = Counter & BIT_Mask; -} - -/********************************************************************* - * @fn WWDG_Enable - * - * @brief Enables WWDG and load the counter value - * - * @param Counter - specifies the watchdog counter value,which must be a - * number between 0x40 and 0x7F - * @return none - */ -void WWDG_Enable(uint8_t Counter) -{ - WWDG->CTLR = CTLR_WDGA_Set | Counter; -} - -/********************************************************************* - * @fn WWDG_GetFlagStatus - * - * @brief Checks whether the Early Wakeup interrupt flag is set or not - * - * @return The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - return (FlagStatus)(WWDG->STATR); -} - -/********************************************************************* - * @fn WWDG_ClearFlag - * - * @brief Clears Early Wakeup interrupt flag - * - * @return none - */ -void WWDG_ClearFlag(void) -{ - WWDG->STATR = (uint32_t)RESET; -} +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_wwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the WWDG firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_wwdg.h" +#include "ch32x035_rcc.h" + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/system/CH32X035/SRC/Startup/startup_ch32x035.S b/system/CH32X035/SRC/Startup/startup_ch32x035.S index 84b4203..3883a4a 100644 --- a/system/CH32X035/SRC/Startup/startup_ch32x035.S +++ b/system/CH32X035/SRC/Startup/startup_ch32x035.S @@ -1,8 +1,8 @@ ;/********************************** (C) COPYRIGHT ******************************* ;* File Name : startup_ch32x035.s ;* Author : WCH -;* Version : V1.0.0 -;* Date : 2023/04/06 +;* Version : V1.0.1 +;* Date : 2023/12/06 ;* Description : vector table for eclipse toolchain. ;********************************************************************************* ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -15,6 +15,7 @@ .align 1 _start: j handle_reset + .section .vector,"ax",@progbits .align 1 _vector_base: @@ -77,7 +78,6 @@ _vector_base: .word TIM3_IRQHandler /* TIM3 */ .option rvc; - .section .text.vector_handler, "ax", @progbits .weak NMI_Handler /* NMI */ .weak HardFault_Handler /* Hard Fault */ @@ -125,51 +125,53 @@ _vector_base: .weak TIM2_BRK_IRQHandler /* TIM2 Break */ .weak TIM3_IRQHandler /* TIM3 */ -NMI_Handler: 1: j 1b -HardFault_Handler: 1: j 1b -Ecall_M_Mode_Handler: 1: j 1b -Ecall_U_Mode_Handler: 1: j 1b -Break_Point_Handler: 1: j 1b -SysTick_Handler: 1: j 1b -SW_Handler: 1: j 1b -WWDG_IRQHandler: 1: j 1b -PVD_IRQHandler: 1: j 1b -FLASH_IRQHandler: 1: j 1b -EXTI7_0_IRQHandler: 1: j 1b -AWU_IRQHandler: 1: j 1b -DMA1_Channel1_IRQHandler: 1: j 1b -DMA1_Channel2_IRQHandler: 1: j 1b -DMA1_Channel3_IRQHandler: 1: j 1b -DMA1_Channel4_IRQHandler: 1: j 1b -DMA1_Channel5_IRQHandler: 1: j 1b -DMA1_Channel6_IRQHandler: 1: j 1b -DMA1_Channel7_IRQHandler: 1: j 1b -ADC1_IRQHandler: 1: j 1b -I2C1_EV_IRQHandler: 1: j 1b -I2C1_ER_IRQHandler: 1: j 1b -USART1_IRQHandler: 1: j 1b -SPI1_IRQHandler: 1: j 1b -TIM1_BRK_IRQHandler: 1: j 1b -TIM1_UP_IRQHandler: 1: j 1b -TIM1_TRG_COM_IRQHandler: 1: j 1b -TIM1_CC_IRQHandler: 1: j 1b -TIM2_UP_IRQHandler: 1: j 1b -USART2_IRQHandler: 1: j 1b -EXTI15_8_IRQHandler: 1: j 1b -EXTI25_16_IRQHandler: 1: j 1b -USART3_IRQHandler: 1: j 1b -USART4_IRQHandler: 1: j 1b -DMA1_Channel8_IRQHandler: 1: j 1b -USBFS_IRQHandler: 1: j 1b -USBFSWakeUp_IRQHandler: 1: j 1b -PIOC_IRQHandler: 1: j 1b -OPA_IRQHandler: 1: j 1b -USBPD_IRQHandler: 1: j 1b -USBPDWakeUp_IRQHandler: 1: j 1b -TIM2_CC_IRQHandler: 1: j 1b -TIM2_TRG_COM_IRQHandler: 1: j 1b -TIM2_BRK_IRQHandler: 1: j 1b -TIM3_IRQHandler: 1: j 1b +NMI_Handler: +HardFault_Handler: +Ecall_M_Mode_Handler: +Ecall_U_Mode_Handler: +Break_Point_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +FLASH_IRQHandler: +EXTI7_0_IRQHandler: +AWU_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +USART1_IRQHandler: +SPI1_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_UP_IRQHandler: +USART2_IRQHandler: +EXTI15_8_IRQHandler: +EXTI25_16_IRQHandler: +USART3_IRQHandler: +USART4_IRQHandler: +DMA1_Channel8_IRQHandler: +USBFS_IRQHandler: +USBFSWakeUp_IRQHandler: +PIOC_IRQHandler: +OPA_IRQHandler: +USBPD_IRQHandler: +USBPDWakeUp_IRQHandler: +TIM2_CC_IRQHandler: +TIM2_TRG_COM_IRQHandler: +TIM2_BRK_IRQHandler: +TIM3_IRQHandler: +1: + j 1b .section .text.handle_reset,"ax",@progbits .weak handle_reset @@ -182,7 +184,7 @@ handle_reset: 1: la sp, _eusrstack 2: - /* Load data section from flash to RAM */ +/* Load data section from flash to RAM */ la a0, _data_lma la a1, _data_vma la a2, _edata @@ -194,7 +196,7 @@ handle_reset: addi a1, a1, 4 bltu a1, a2, 1b 2: - /* Clear bss section */ +/* Clear bss section */ la a0, _sbss la a1, _ebss bgeu a0, a1, 2f @@ -203,25 +205,20 @@ handle_reset: addi a0, a0, 4 bltu a0, a1, 1b 2: +/* Configure pipelining and instruction prediction */ li t0, 0x1f csrw 0xbc0, t0 - - /* Enable nested and hardware stack */ +/* Enable interrupt nesting and hardware stack */ li t0, 0x3 csrw 0x804, t0 - - /* Enable interrupt */ +/* Enable global interrupt and configure privileged mode */ li t0, 0x88 - csrs mstatus, t0 - + csrw mstatus, t0 +/* Configure the interrupt vector table recognition mode and entry address mode */ la t0, _vector_base ori t0, t0, 3 csrw mtvec, t0 - la a0, __libc_fini_array - call atexit - call __libc_init_array - jal SystemInit la t0, main csrw mepc, t0 diff --git a/system/CH32X035/USER/ch32x035_conf.h b/system/CH32X035/USER/ch32x035_conf.h index 996db41..0ee8ee5 100644 --- a/system/CH32X035/USER/ch32x035_conf.h +++ b/system/CH32X035/USER/ch32x035_conf.h @@ -1,39 +1,39 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_conf.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : Library configuration file. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __CH32X035_CONF_H -#define __CH32X035_CONF_H - -#include "ch32x035_adc.h" -#include "ch32x035_awu.h" -#include "ch32x035_dbgmcu.h" -#include "ch32x035_dma.h" -#include "ch32x035_exti.h" -#include "ch32x035_flash.h" -#include "ch32x035_gpio.h" -#include "ch32x035_i2c.h" -#include "ch32x035_iwdg.h" -#include "ch32x035_pwr.h" -#include "ch32x035_rcc.h" -#include "ch32x035_spi.h" -#include "ch32x035_tim.h" -#include "ch32x035_usart.h" -#include "ch32x035_wwdg.h" -#include "ch32x035_it.h" -#include "ch32x035_misc.h" - - -#endif - - - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : Library configuration file. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_CONF_H +#define __CH32X035_CONF_H + +#include "ch32x035_adc.h" +#include "ch32x035_awu.h" +#include "ch32x035_dbgmcu.h" +#include "ch32x035_dma.h" +#include "ch32x035_exti.h" +#include "ch32x035_flash.h" +#include "ch32x035_gpio.h" +#include "ch32x035_i2c.h" +#include "ch32x035_iwdg.h" +#include "ch32x035_pwr.h" +#include "ch32x035_rcc.h" +#include "ch32x035_spi.h" +#include "ch32x035_tim.h" +#include "ch32x035_usart.h" +#include "ch32x035_wwdg.h" +#include "ch32x035_it.h" +#include "ch32x035_misc.h" + + +#endif + + + + + diff --git a/system/CH32X035/USER/ch32x035_it.c b/system/CH32X035/USER/ch32x035_it.c index e4301bd..987c658 100644 --- a/system/CH32X035/USER/ch32x035_it.c +++ b/system/CH32X035/USER/ch32x035_it.c @@ -1,42 +1,46 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : ch32x035_it.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : Main Interrupt Service Routines. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035_it.h" - -void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); -void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); - -/********************************************************************* - * @fn NMI_Handler - * - * @brief This function handles NMI exception. - * - * @return none - */ -void NMI_Handler(void) -{ -} - -/********************************************************************* - * @fn HardFault_Handler - * - * @brief This function handles Hard Fault exception. - * - * @return none - */ -void HardFault_Handler(void) -{ - while (1) - { - } -} - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_it.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/10/28 + * Description : Main Interrupt Service Routines. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_it.h" + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ + while (1) + { + } +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + NVIC_SystemReset(); + while (1) + { + } +} + + diff --git a/system/CH32X035/USER/system_ch32x035.c b/system/CH32X035/USER/system_ch32x035.c index 461b9f2..7ec09db 100644 --- a/system/CH32X035/USER/system_ch32x035.c +++ b/system/CH32X035/USER/system_ch32x035.c @@ -1,241 +1,241 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : system_ch32x035.c - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : CH32X035 Device Peripheral Access Layer System Source File. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#include "ch32x035.h" - -/* -* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after -* reset the HSI is used as SYSCLK source). -*/ - -//#define SYSCLK_FREQ_8MHz_HSI 8000000 -//#define SYSCLK_FREQ_12MHz_HSI 12000000 -//#define SYSCLK_FREQ_16MHz_HSI 16000000 -//#define SYSCLK_FREQ_24MHz_HSI 24000000 -// #define SYSCLK_FREQ_48MHz_HSI HSI_VALUE - -/* Clock Definitions */ -#ifdef SYSCLK_FREQ_8MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_12MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_12MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_16MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_16MHz_HSI; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /* System Clock Frequency (Core Clock) */ -#else -uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ - -#endif - -__I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; - - -/* system_private_function_proto_types */ -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_8MHz_HSI -static void SetSysClockTo8_HSI( void ); -#elif defined SYSCLK_FREQ_12MHz_HSI -static void SetSysClockTo12_HSI( void ); -#elif defined SYSCLK_FREQ_16MHz_HSI -static void SetSysClockTo16_HSI( void ); -#elif defined SYSCLK_FREQ_24MHz_HSI -static void SetSysClockTo24_HSI( void ); -#elif defined SYSCLK_FREQ_48MHz_HSI -static void SetSysClockTo48_HSI( void ); - -#endif - -/********************************************************************* - * @fn SystemInit - * - * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, - * update the SystemCoreClock variable. - * - * @return none - */ -void SystemInit (void) -{ - RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 |= (uint32_t)0x00000050; - RCC->CFGR0 &= (uint32_t)0xF8FFFF5F; - SetSysClock(); -} - -/********************************************************************* - * @fn SystemCoreClockUpdate - * - * @brief Update SystemCoreClock variable according to Clock Register Values. - * - * @return none - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0; - - SystemCoreClock = HSI_VALUE; - tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; - - if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8) - { - SystemCoreClock /= tmp; - } - else - { - SystemCoreClock >>= tmp; - } -} - -/********************************************************************* - * @fn SetSysClock - * - * @brief Configures the System clock frequency, HCLK prescalers. - * - * @return none - */ -static void SetSysClock(void) -{ -// GPIO_IPD_Unused(); - -#ifdef SYSCLK_FREQ_8MHz_HSI - SetSysClockTo8_HSI(); -#elif defined SYSCLK_FREQ_12MHz_HSI - SetSysClockTo12_HSI(); -#elif defined SYSCLK_FREQ_16MHz_HSI - SetSysClockTo16_HSI(); -#elif defined SYSCLK_FREQ_24MHz_HSI - SetSysClockTo24_HSI(); -#elif defined SYSCLK_FREQ_48MHz_HSI - SetSysClockTo48_HSI(); - -#endif -} - - -#ifdef SYSCLK_FREQ_8MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo8_HSI - * - * @brief Sets HSE as System clock source and configure HCLK prescalers. - * - * @return none - */ -static void SetSysClockTo8_HSI(void) -{ - /* Flash 2 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; - - /* HCLK = SYSCLK = APB1 */ - RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV6; - - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; -} - -#elif defined SYSCLK_FREQ_12MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo12_HSI - * - * @brief Sets System clock frequency to 12MHz and configure HCLK prescalers. - * - * @return none - */ -static void SetSysClockTo12_HSI(void) -{ - /* Flash 2 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; - - /* HCLK = SYSCLK = APB1 */ - RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV4; - - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; -} - -#elif defined SYSCLK_FREQ_16MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo16_HSI - * - * @brief Sets System clock frequency to 16MHz and configure HCLK prescalers. - * - * @return none - */ -static void SetSysClockTo16_HSI(void) -{ - /* Flash 2 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; - - /* HCLK = SYSCLK = APB1 */ - RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; - - /* Flash 0 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; -} - -#elif defined SYSCLK_FREQ_24MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo24_HSI - * - * @brief Sets System clock frequency to 24MHz and configure HCLK prescalers. - * - * @return none - */ -static void SetSysClockTo24_HSI(void) -{ - /* Flash 2 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; - - /* HCLK = SYSCLK = APB1 */ - RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2; - - /* Flash 1 wait state */ - FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; -} - - -#elif defined SYSCLK_FREQ_48MHz_HSI - -/********************************************************************* - * @fn SetSysClockTo48_HSI - * - * @brief Sets System clock frequency to 48MHz and configure HCLK prescalers. - * - * @return none - */ -static void SetSysClockTo48_HSI(void) -{ - /* Flash 2 wait state */ - FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; - - /* HCLK = SYSCLK = APB1 */ - RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; -} - -#endif - +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32x035.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : CH32X035 Device Peripheral Access Layer System Source File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035.h" + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +*/ + +//#define SYSCLK_FREQ_8MHz_HSI 8000000 +//#define SYSCLK_FREQ_12MHz_HSI 12000000 +//#define SYSCLK_FREQ_16MHz_HSI 16000000 +//#define SYSCLK_FREQ_24MHz_HSI 24000000 +// #define SYSCLK_FREQ_48MHz_HSI HSI_VALUE + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_8MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_12MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_12MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_16MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_16MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /* System Clock Frequency (Core Clock) */ +#else +uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ + +#endif + +__I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_8MHz_HSI +static void SetSysClockTo8_HSI( void ); +#elif defined SYSCLK_FREQ_12MHz_HSI +static void SetSysClockTo12_HSI( void ); +#elif defined SYSCLK_FREQ_16MHz_HSI +static void SetSysClockTo16_HSI( void ); +#elif defined SYSCLK_FREQ_24MHz_HSI +static void SetSysClockTo24_HSI( void ); +#elif defined SYSCLK_FREQ_48MHz_HSI +static void SetSysClockTo48_HSI( void ); + +#endif + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 |= (uint32_t)0x00000050; + RCC->CFGR0 &= (uint32_t)0xF8FFFF5F; + SetSysClock(); +} + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0; + + SystemCoreClock = HSI_VALUE; + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + + if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8) + { + SystemCoreClock /= tmp; + } + else + { + SystemCoreClock >>= tmp; + } +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ +// GPIO_IPD_Unused(); + +#ifdef SYSCLK_FREQ_8MHz_HSI + SetSysClockTo8_HSI(); +#elif defined SYSCLK_FREQ_12MHz_HSI + SetSysClockTo12_HSI(); +#elif defined SYSCLK_FREQ_16MHz_HSI + SetSysClockTo16_HSI(); +#elif defined SYSCLK_FREQ_24MHz_HSI + SetSysClockTo24_HSI(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); + +#endif +} + + +#ifdef SYSCLK_FREQ_8MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo8_HSI + * + * @brief Sets HSE as System clock source and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo8_HSI(void) +{ + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV6; + + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; +} + +#elif defined SYSCLK_FREQ_12MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo12_HSI + * + * @brief Sets System clock frequency to 12MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo12_HSI(void) +{ + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV4; + + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; +} + +#elif defined SYSCLK_FREQ_16MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo16_HSI + * + * @brief Sets System clock frequency to 16MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo16_HSI(void) +{ + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; + + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; +} + +#elif defined SYSCLK_FREQ_24MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo24_HSI + * + * @brief Sets System clock frequency to 24MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo24_HSI(void) +{ + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2; + + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; +} + + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; +} + +#endif + diff --git a/system/CH32X035/USER/system_ch32x035.h b/system/CH32X035/USER/system_ch32x035.h index c476797..9cad09b 100644 --- a/system/CH32X035/USER/system_ch32x035.h +++ b/system/CH32X035/USER/system_ch32x035.h @@ -1,32 +1,32 @@ -/********************************** (C) COPYRIGHT ******************************* - * File Name : system_ch32x035.h - * Author : WCH - * Version : V1.0.0 - * Date : 2023/04/06 - * Description : CH32X035 Device Peripheral Access Layer System Header File. -********************************************************************************* -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* Attention: This software (modified or not) and binary are used for -* microcontroller manufactured by Nanjing Qinheng Microelectronics. -*******************************************************************************/ -#ifndef __SYSTEM_CH32X035_H -#define __SYSTEM_CH32X035_H - -#ifdef __cplusplus - extern "C" { -#endif - -extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ - -/* System_Exported_Functions */ -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif - - - +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32x035.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : CH32X035 Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_CH32X035_H +#define __SYSTEM_CH32X035_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + diff --git a/variants/CH32V20x/PinAF_CH32V20x.h b/variants/CH32V20x/PinAF_CH32V20x.h index 59ded56..b9de222 100644 --- a/variants/CH32V20x/PinAF_CH32V20x.h +++ b/variants/CH32V20x/PinAF_CH32V20x.h @@ -102,8 +102,6 @@ enum { AFIO_Remap_ADC2_ETRGREG_ENABLE, AFIO_Remap_ADC2_ETRGREG_DISABLE, - AFIO_Remap_SWJ_NONJTRST, - AFIO_Remap_SWJ_NOJTAG, AFIO_Remap_SWJ_DISABLE, AFIO_Remap_SPI3_ENABLE, @@ -314,12 +312,6 @@ static inline void pin_SetV32AFPin(uint32_t afnum) GPIO_PinRemapConfig(GPIO_Remap_ADC2_ETRGREG,DISABLE); break; - case AFIO_Remap_SWJ_NONJTRST: - GPIO_PinRemapConfig(GPIO_Remap_SWJ_NoJTRST,ENABLE); - break; - case AFIO_Remap_SWJ_NOJTAG: - GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable,ENABLE); - break; case AFIO_Remap_SWJ_DISABLE: GPIO_PinRemapConfig(GPIO_Remap_SWJ_Disable,ENABLE); break;